Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/serial/mpsc.c | |
3 | * | |
4 | * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, | |
5 | * GT64260, MV64340, MV64360, GT96100, ... ). | |
6 | * | |
7 | * Author: Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * Based on an old MPSC driver that was in the linuxppc tree. It appears to | |
10 | * have been created by Chris Zankel (formerly of MontaVista) but there | |
11 | * is no proper Copyright so I'm not sure. Apparently, parts were also | |
12 | * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c | |
13 | * by Russell King. | |
14 | * | |
15 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under | |
16 | * the terms of the GNU General Public License version 2. This program | |
17 | * is licensed "as is" without any warranty of any kind, whether express | |
18 | * or implied. | |
19 | */ | |
20 | /* | |
21 | * The MPSC interface is much like a typical network controller's interface. | |
22 | * That is, you set up separate rings of descriptors for transmitting and | |
23 | * receiving data. There is also a pool of buffers with (one buffer per | |
24 | * descriptor) that incoming data are dma'd into or outgoing data are dma'd | |
25 | * out of. | |
26 | * | |
27 | * The MPSC requires two other controllers to be able to work. The Baud Rate | |
28 | * Generator (BRG) provides a clock at programmable frequencies which determines | |
29 | * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the | |
30 | * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the | |
31 | * MPSC. It is actually the SDMA interrupt that the driver uses to keep the | |
32 | * transmit and receive "engines" going (i.e., indicate data has been | |
33 | * transmitted or received). | |
34 | * | |
35 | * NOTES: | |
36 | * | |
37 | * 1) Some chips have an erratum where several regs cannot be | |
38 | * read. To work around that, we keep a local copy of those regs in | |
39 | * 'mpsc_port_info'. | |
40 | * | |
41 | * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr | |
42 | * accesses system mem with coherency enabled. For that reason, the driver | |
43 | * assumes that coherency for that ctlr has been disabled. This means | |
44 | * that when in a cache coherent system, the driver has to manually manage | |
45 | * the data cache on the areas that it touches because the dma_* macro are | |
46 | * basically no-ops. | |
47 | * | |
48 | * 3) There is an erratum (on PPC) where you can't use the instruction to do | |
49 | * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places | |
50 | * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed. | |
51 | * | |
52 | * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. | |
53 | */ | |
54 | ||
55 | #include "mpsc.h" | |
56 | ||
57 | /* | |
58 | * Define how this driver is known to the outside (we've been assigned a | |
59 | * range on the "Low-density serial ports" major). | |
60 | */ | |
61 | #define MPSC_MAJOR 204 | |
62 | #define MPSC_MINOR_START 44 | |
63 | #define MPSC_DRIVER_NAME "MPSC" | |
64 | #define MPSC_DEVFS_NAME "ttymm/" | |
65 | #define MPSC_DEV_NAME "ttyMM" | |
66 | #define MPSC_VERSION "1.00" | |
67 | ||
68 | static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS]; | |
69 | static struct mpsc_shared_regs mpsc_shared_regs; | |
4d0145a7 | 70 | static struct uart_driver mpsc_reg; |
1da177e4 | 71 | |
4d0145a7 LN |
72 | static void mpsc_start_rx(struct mpsc_port_info *pi); |
73 | static void mpsc_free_ring_mem(struct mpsc_port_info *pi); | |
74 | static void mpsc_release_port(struct uart_port *port); | |
1da177e4 LT |
75 | /* |
76 | ****************************************************************************** | |
77 | * | |
78 | * Baud Rate Generator Routines (BRG) | |
79 | * | |
80 | ****************************************************************************** | |
81 | */ | |
82 | static void | |
83 | mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) | |
84 | { | |
85 | u32 v; | |
86 | ||
87 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
88 | v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18); | |
89 | ||
90 | if (pi->brg_can_tune) | |
91 | v &= ~(1 << 25); | |
92 | ||
93 | if (pi->mirror_regs) | |
94 | pi->BRG_BCR_m = v; | |
95 | writel(v, pi->brg_base + BRG_BCR); | |
96 | ||
97 | writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, | |
98 | pi->brg_base + BRG_BTR); | |
99 | return; | |
100 | } | |
101 | ||
102 | static void | |
103 | mpsc_brg_enable(struct mpsc_port_info *pi) | |
104 | { | |
105 | u32 v; | |
106 | ||
107 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
108 | v |= (1 << 16); | |
109 | ||
110 | if (pi->mirror_regs) | |
111 | pi->BRG_BCR_m = v; | |
112 | writel(v, pi->brg_base + BRG_BCR); | |
113 | return; | |
114 | } | |
115 | ||
116 | static void | |
117 | mpsc_brg_disable(struct mpsc_port_info *pi) | |
118 | { | |
119 | u32 v; | |
120 | ||
121 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
122 | v &= ~(1 << 16); | |
123 | ||
124 | if (pi->mirror_regs) | |
125 | pi->BRG_BCR_m = v; | |
126 | writel(v, pi->brg_base + BRG_BCR); | |
127 | return; | |
128 | } | |
129 | ||
130 | static inline void | |
131 | mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) | |
132 | { | |
133 | /* | |
134 | * To set the baud, we adjust the CDV field in the BRG_BCR reg. | |
135 | * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1. | |
136 | * However, the input clock is divided by 16 in the MPSC b/c of how | |
137 | * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our | |
138 | * calculation by 16 to account for that. So the real calculation | |
139 | * that accounts for the way the mpsc is set up is: | |
140 | * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1. | |
141 | */ | |
142 | u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; | |
143 | u32 v; | |
144 | ||
145 | mpsc_brg_disable(pi); | |
146 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
147 | v = (v & 0xffff0000) | (cdv & 0xffff); | |
148 | ||
149 | if (pi->mirror_regs) | |
150 | pi->BRG_BCR_m = v; | |
151 | writel(v, pi->brg_base + BRG_BCR); | |
152 | mpsc_brg_enable(pi); | |
153 | ||
154 | return; | |
155 | } | |
156 | ||
157 | /* | |
158 | ****************************************************************************** | |
159 | * | |
160 | * Serial DMA Routines (SDMA) | |
161 | * | |
162 | ****************************************************************************** | |
163 | */ | |
164 | ||
165 | static void | |
166 | mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) | |
167 | { | |
168 | u32 v; | |
169 | ||
170 | pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n", | |
171 | pi->port.line, burst_size); | |
172 | ||
173 | burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */ | |
174 | ||
175 | if (burst_size < 2) | |
176 | v = 0x0; /* 1 64-bit word */ | |
177 | else if (burst_size < 4) | |
178 | v = 0x1; /* 2 64-bit words */ | |
179 | else if (burst_size < 8) | |
180 | v = 0x2; /* 4 64-bit words */ | |
181 | else | |
182 | v = 0x3; /* 8 64-bit words */ | |
183 | ||
184 | writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), | |
185 | pi->sdma_base + SDMA_SDC); | |
186 | return; | |
187 | } | |
188 | ||
189 | static void | |
190 | mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) | |
191 | { | |
192 | pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, | |
193 | burst_size); | |
194 | ||
195 | writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, | |
196 | pi->sdma_base + SDMA_SDC); | |
197 | mpsc_sdma_burstsize(pi, burst_size); | |
198 | return; | |
199 | } | |
200 | ||
201 | static inline u32 | |
202 | mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) | |
203 | { | |
204 | u32 old, v; | |
205 | ||
206 | pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); | |
207 | ||
208 | old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : | |
209 | readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
210 | ||
211 | mask &= 0xf; | |
212 | if (pi->port.line) | |
213 | mask <<= 8; | |
214 | v &= ~mask; | |
215 | ||
216 | if (pi->mirror_regs) | |
217 | pi->shared_regs->SDMA_INTR_MASK_m = v; | |
218 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
219 | ||
220 | if (pi->port.line) | |
221 | old >>= 8; | |
222 | return old & 0xf; | |
223 | } | |
224 | ||
225 | static inline void | |
226 | mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) | |
227 | { | |
228 | u32 v; | |
229 | ||
230 | pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); | |
231 | ||
232 | v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : | |
233 | readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
234 | ||
235 | mask &= 0xf; | |
236 | if (pi->port.line) | |
237 | mask <<= 8; | |
238 | v |= mask; | |
239 | ||
240 | if (pi->mirror_regs) | |
241 | pi->shared_regs->SDMA_INTR_MASK_m = v; | |
242 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
243 | return; | |
244 | } | |
245 | ||
246 | static inline void | |
247 | mpsc_sdma_intr_ack(struct mpsc_port_info *pi) | |
248 | { | |
249 | pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); | |
250 | ||
251 | if (pi->mirror_regs) | |
252 | pi->shared_regs->SDMA_INTR_CAUSE_m = 0; | |
253 | writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE); | |
254 | return; | |
255 | } | |
256 | ||
257 | static inline void | |
258 | mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p) | |
259 | { | |
260 | pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", | |
261 | pi->port.line, (u32) rxre_p); | |
262 | ||
263 | writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); | |
264 | return; | |
265 | } | |
266 | ||
267 | static inline void | |
268 | mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p) | |
269 | { | |
270 | writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); | |
271 | writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); | |
272 | return; | |
273 | } | |
274 | ||
275 | static inline void | |
276 | mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) | |
277 | { | |
278 | u32 v; | |
279 | ||
280 | v = readl(pi->sdma_base + SDMA_SDCM); | |
281 | if (val) | |
282 | v |= val; | |
283 | else | |
284 | v = 0; | |
285 | wmb(); | |
286 | writel(v, pi->sdma_base + SDMA_SDCM); | |
287 | wmb(); | |
288 | return; | |
289 | } | |
290 | ||
291 | static inline uint | |
292 | mpsc_sdma_tx_active(struct mpsc_port_info *pi) | |
293 | { | |
294 | return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; | |
295 | } | |
296 | ||
297 | static inline void | |
298 | mpsc_sdma_start_tx(struct mpsc_port_info *pi) | |
299 | { | |
300 | struct mpsc_tx_desc *txre, *txre_p; | |
301 | ||
302 | /* If tx isn't running & there's a desc ready to go, start it */ | |
303 | if (!mpsc_sdma_tx_active(pi)) { | |
304 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
305 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
306 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); | |
307 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
308 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
309 | invalidate_dcache_range((ulong)txre, | |
310 | (ulong)txre + MPSC_TXRE_SIZE); | |
311 | #endif | |
312 | ||
313 | if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { | |
314 | txre_p = (struct mpsc_tx_desc *)(pi->txr_p + | |
315 | (pi->txr_tail * | |
316 | MPSC_TXRE_SIZE)); | |
317 | ||
318 | mpsc_sdma_set_tx_ring(pi, txre_p); | |
319 | mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); | |
320 | } | |
321 | } | |
322 | ||
323 | return; | |
324 | } | |
325 | ||
326 | static inline void | |
327 | mpsc_sdma_stop(struct mpsc_port_info *pi) | |
328 | { | |
329 | pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); | |
330 | ||
331 | /* Abort any SDMA transfers */ | |
332 | mpsc_sdma_cmd(pi, 0); | |
333 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); | |
334 | ||
335 | /* Clear the SDMA current and first TX and RX pointers */ | |
2c6e7599 AV |
336 | mpsc_sdma_set_tx_ring(pi, NULL); |
337 | mpsc_sdma_set_rx_ring(pi, NULL); | |
1da177e4 LT |
338 | |
339 | /* Disable interrupts */ | |
340 | mpsc_sdma_intr_mask(pi, 0xf); | |
341 | mpsc_sdma_intr_ack(pi); | |
342 | ||
343 | return; | |
344 | } | |
345 | ||
346 | /* | |
347 | ****************************************************************************** | |
348 | * | |
349 | * Multi-Protocol Serial Controller Routines (MPSC) | |
350 | * | |
351 | ****************************************************************************** | |
352 | */ | |
353 | ||
354 | static void | |
355 | mpsc_hw_init(struct mpsc_port_info *pi) | |
356 | { | |
357 | u32 v; | |
358 | ||
359 | pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); | |
360 | ||
361 | /* Set up clock routing */ | |
362 | if (pi->mirror_regs) { | |
363 | v = pi->shared_regs->MPSC_MRR_m; | |
364 | v &= ~0x1c7; | |
365 | pi->shared_regs->MPSC_MRR_m = v; | |
366 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
367 | ||
368 | v = pi->shared_regs->MPSC_RCRR_m; | |
369 | v = (v & ~0xf0f) | 0x100; | |
370 | pi->shared_regs->MPSC_RCRR_m = v; | |
371 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
372 | ||
373 | v = pi->shared_regs->MPSC_TCRR_m; | |
374 | v = (v & ~0xf0f) | 0x100; | |
375 | pi->shared_regs->MPSC_TCRR_m = v; | |
376 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
377 | } | |
378 | else { | |
379 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
380 | v &= ~0x1c7; | |
381 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
382 | ||
383 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
384 | v = (v & ~0xf0f) | 0x100; | |
385 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
386 | ||
387 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
388 | v = (v & ~0xf0f) | 0x100; | |
389 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
390 | } | |
391 | ||
392 | /* Put MPSC in UART mode & enabel Tx/Rx egines */ | |
393 | writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); | |
394 | ||
395 | /* No preamble, 16x divider, low-latency, */ | |
396 | writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); | |
397 | ||
398 | if (pi->mirror_regs) { | |
399 | pi->MPSC_CHR_1_m = 0; | |
400 | pi->MPSC_CHR_2_m = 0; | |
401 | } | |
402 | writel(0, pi->mpsc_base + MPSC_CHR_1); | |
403 | writel(0, pi->mpsc_base + MPSC_CHR_2); | |
404 | writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); | |
405 | writel(0, pi->mpsc_base + MPSC_CHR_4); | |
406 | writel(0, pi->mpsc_base + MPSC_CHR_5); | |
407 | writel(0, pi->mpsc_base + MPSC_CHR_6); | |
408 | writel(0, pi->mpsc_base + MPSC_CHR_7); | |
409 | writel(0, pi->mpsc_base + MPSC_CHR_8); | |
410 | writel(0, pi->mpsc_base + MPSC_CHR_9); | |
411 | writel(0, pi->mpsc_base + MPSC_CHR_10); | |
412 | ||
413 | return; | |
414 | } | |
415 | ||
416 | static inline void | |
417 | mpsc_enter_hunt(struct mpsc_port_info *pi) | |
418 | { | |
419 | pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); | |
420 | ||
421 | if (pi->mirror_regs) { | |
422 | writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, | |
423 | pi->mpsc_base + MPSC_CHR_2); | |
424 | /* Erratum prevents reading CHR_2 so just delay for a while */ | |
425 | udelay(100); | |
426 | } | |
427 | else { | |
428 | writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, | |
429 | pi->mpsc_base + MPSC_CHR_2); | |
430 | ||
431 | while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) | |
432 | udelay(10); | |
433 | } | |
434 | ||
435 | return; | |
436 | } | |
437 | ||
438 | static inline void | |
439 | mpsc_freeze(struct mpsc_port_info *pi) | |
440 | { | |
441 | u32 v; | |
442 | ||
443 | pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); | |
444 | ||
445 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
446 | readl(pi->mpsc_base + MPSC_MPCR); | |
447 | v |= MPSC_MPCR_FRZ; | |
448 | ||
449 | if (pi->mirror_regs) | |
450 | pi->MPSC_MPCR_m = v; | |
451 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
452 | return; | |
453 | } | |
454 | ||
455 | static inline void | |
456 | mpsc_unfreeze(struct mpsc_port_info *pi) | |
457 | { | |
458 | u32 v; | |
459 | ||
460 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
461 | readl(pi->mpsc_base + MPSC_MPCR); | |
462 | v &= ~MPSC_MPCR_FRZ; | |
463 | ||
464 | if (pi->mirror_regs) | |
465 | pi->MPSC_MPCR_m = v; | |
466 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
467 | ||
468 | pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); | |
469 | return; | |
470 | } | |
471 | ||
472 | static inline void | |
473 | mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) | |
474 | { | |
475 | u32 v; | |
476 | ||
477 | pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); | |
478 | ||
479 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
480 | readl(pi->mpsc_base + MPSC_MPCR); | |
481 | v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12); | |
482 | ||
483 | if (pi->mirror_regs) | |
484 | pi->MPSC_MPCR_m = v; | |
485 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
486 | return; | |
487 | } | |
488 | ||
489 | static inline void | |
490 | mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) | |
491 | { | |
492 | u32 v; | |
493 | ||
494 | pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n", | |
495 | pi->port.line, len); | |
496 | ||
497 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
498 | readl(pi->mpsc_base + MPSC_MPCR); | |
499 | ||
500 | v = (v & ~(1 << 14)) | ((len & 0x1) << 14); | |
501 | ||
502 | if (pi->mirror_regs) | |
503 | pi->MPSC_MPCR_m = v; | |
504 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
505 | return; | |
506 | } | |
507 | ||
508 | static inline void | |
509 | mpsc_set_parity(struct mpsc_port_info *pi, u32 p) | |
510 | { | |
511 | u32 v; | |
512 | ||
513 | pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); | |
514 | ||
515 | v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : | |
516 | readl(pi->mpsc_base + MPSC_CHR_2); | |
517 | ||
518 | p &= 0x3; | |
519 | v = (v & ~0xc000c) | (p << 18) | (p << 2); | |
520 | ||
521 | if (pi->mirror_regs) | |
522 | pi->MPSC_CHR_2_m = v; | |
523 | writel(v, pi->mpsc_base + MPSC_CHR_2); | |
524 | return; | |
525 | } | |
526 | ||
527 | /* | |
528 | ****************************************************************************** | |
529 | * | |
530 | * Driver Init Routines | |
531 | * | |
532 | ****************************************************************************** | |
533 | */ | |
534 | ||
535 | static void | |
536 | mpsc_init_hw(struct mpsc_port_info *pi) | |
537 | { | |
538 | pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); | |
539 | ||
540 | mpsc_brg_init(pi, pi->brg_clk_src); | |
541 | mpsc_brg_enable(pi); | |
542 | mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ | |
543 | mpsc_sdma_stop(pi); | |
544 | mpsc_hw_init(pi); | |
545 | ||
546 | return; | |
547 | } | |
548 | ||
549 | static int | |
550 | mpsc_alloc_ring_mem(struct mpsc_port_info *pi) | |
551 | { | |
552 | int rc = 0; | |
1da177e4 LT |
553 | |
554 | pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n", | |
555 | pi->port.line); | |
556 | ||
557 | if (!pi->dma_region) { | |
558 | if (!dma_supported(pi->port.dev, 0xffffffff)) { | |
559 | printk(KERN_ERR "MPSC: Inadequate DMA support\n"); | |
560 | rc = -ENXIO; | |
561 | } | |
562 | else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, | |
563 | MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL)) | |
564 | == NULL) { | |
565 | ||
566 | printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); | |
567 | rc = -ENOMEM; | |
568 | } | |
569 | } | |
570 | ||
571 | return rc; | |
572 | } | |
573 | ||
574 | static void | |
575 | mpsc_free_ring_mem(struct mpsc_port_info *pi) | |
576 | { | |
577 | pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); | |
578 | ||
579 | if (pi->dma_region) { | |
580 | dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, | |
581 | pi->dma_region, pi->dma_region_p); | |
582 | pi->dma_region = NULL; | |
583 | pi->dma_region_p = (dma_addr_t) NULL; | |
584 | } | |
585 | ||
586 | return; | |
587 | } | |
588 | ||
589 | static void | |
590 | mpsc_init_rings(struct mpsc_port_info *pi) | |
591 | { | |
592 | struct mpsc_rx_desc *rxre; | |
593 | struct mpsc_tx_desc *txre; | |
594 | dma_addr_t dp, dp_p; | |
595 | u8 *bp, *bp_p; | |
596 | int i; | |
597 | ||
598 | pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); | |
599 | ||
600 | BUG_ON(pi->dma_region == NULL); | |
601 | ||
602 | memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); | |
603 | ||
604 | /* | |
605 | * Descriptors & buffers are multiples of cacheline size and must be | |
606 | * cacheline aligned. | |
607 | */ | |
608 | dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment()); | |
609 | dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment()); | |
610 | ||
611 | /* | |
612 | * Partition dma region into rx ring descriptor, rx buffers, | |
613 | * tx ring descriptors, and tx buffers. | |
614 | */ | |
615 | pi->rxr = dp; | |
616 | pi->rxr_p = dp_p; | |
617 | dp += MPSC_RXR_SIZE; | |
618 | dp_p += MPSC_RXR_SIZE; | |
619 | ||
620 | pi->rxb = (u8 *) dp; | |
621 | pi->rxb_p = (u8 *) dp_p; | |
622 | dp += MPSC_RXB_SIZE; | |
623 | dp_p += MPSC_RXB_SIZE; | |
624 | ||
625 | pi->rxr_posn = 0; | |
626 | ||
627 | pi->txr = dp; | |
628 | pi->txr_p = dp_p; | |
629 | dp += MPSC_TXR_SIZE; | |
630 | dp_p += MPSC_TXR_SIZE; | |
631 | ||
632 | pi->txb = (u8 *) dp; | |
633 | pi->txb_p = (u8 *) dp_p; | |
634 | ||
635 | pi->txr_head = 0; | |
636 | pi->txr_tail = 0; | |
637 | ||
638 | /* Init rx ring descriptors */ | |
639 | dp = pi->rxr; | |
640 | dp_p = pi->rxr_p; | |
641 | bp = pi->rxb; | |
642 | bp_p = pi->rxb_p; | |
643 | ||
644 | for (i = 0; i < MPSC_RXR_ENTRIES; i++) { | |
645 | rxre = (struct mpsc_rx_desc *)dp; | |
646 | ||
647 | rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); | |
648 | rxre->bytecnt = cpu_to_be16(0); | |
649 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | | |
650 | SDMA_DESC_CMDSTAT_EI | | |
651 | SDMA_DESC_CMDSTAT_F | | |
652 | SDMA_DESC_CMDSTAT_L); | |
653 | rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); | |
654 | rxre->buf_ptr = cpu_to_be32(bp_p); | |
655 | ||
656 | dp += MPSC_RXRE_SIZE; | |
657 | dp_p += MPSC_RXRE_SIZE; | |
658 | bp += MPSC_RXBE_SIZE; | |
659 | bp_p += MPSC_RXBE_SIZE; | |
660 | } | |
661 | rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ | |
662 | ||
663 | /* Init tx ring descriptors */ | |
664 | dp = pi->txr; | |
665 | dp_p = pi->txr_p; | |
666 | bp = pi->txb; | |
667 | bp_p = pi->txb_p; | |
668 | ||
669 | for (i = 0; i < MPSC_TXR_ENTRIES; i++) { | |
670 | txre = (struct mpsc_tx_desc *)dp; | |
671 | ||
672 | txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE); | |
673 | txre->buf_ptr = cpu_to_be32(bp_p); | |
674 | ||
675 | dp += MPSC_TXRE_SIZE; | |
676 | dp_p += MPSC_TXRE_SIZE; | |
677 | bp += MPSC_TXBE_SIZE; | |
678 | bp_p += MPSC_TXBE_SIZE; | |
679 | } | |
680 | txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ | |
681 | ||
682 | dma_cache_sync((void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE, | |
683 | DMA_BIDIRECTIONAL); | |
684 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
685 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
686 | flush_dcache_range((ulong)pi->dma_region, | |
687 | (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE); | |
688 | #endif | |
689 | ||
690 | return; | |
691 | } | |
692 | ||
693 | static void | |
694 | mpsc_uninit_rings(struct mpsc_port_info *pi) | |
695 | { | |
696 | pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); | |
697 | ||
698 | BUG_ON(pi->dma_region == NULL); | |
699 | ||
700 | pi->rxr = 0; | |
701 | pi->rxr_p = 0; | |
702 | pi->rxb = NULL; | |
703 | pi->rxb_p = NULL; | |
704 | pi->rxr_posn = 0; | |
705 | ||
706 | pi->txr = 0; | |
707 | pi->txr_p = 0; | |
708 | pi->txb = NULL; | |
709 | pi->txb_p = NULL; | |
710 | pi->txr_head = 0; | |
711 | pi->txr_tail = 0; | |
712 | ||
713 | return; | |
714 | } | |
715 | ||
716 | static int | |
717 | mpsc_make_ready(struct mpsc_port_info *pi) | |
718 | { | |
719 | int rc; | |
720 | ||
721 | pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); | |
722 | ||
723 | if (!pi->ready) { | |
724 | mpsc_init_hw(pi); | |
725 | if ((rc = mpsc_alloc_ring_mem(pi))) | |
726 | return rc; | |
727 | mpsc_init_rings(pi); | |
728 | pi->ready = 1; | |
729 | } | |
730 | ||
731 | return 0; | |
732 | } | |
733 | ||
734 | /* | |
735 | ****************************************************************************** | |
736 | * | |
737 | * Interrupt Handling Routines | |
738 | * | |
739 | ****************************************************************************** | |
740 | */ | |
741 | ||
742 | static inline int | |
743 | mpsc_rx_intr(struct mpsc_port_info *pi, struct pt_regs *regs) | |
744 | { | |
745 | struct mpsc_rx_desc *rxre; | |
746 | struct tty_struct *tty = pi->port.info->tty; | |
747 | u32 cmdstat, bytes_in, i; | |
748 | int rc = 0; | |
749 | u8 *bp; | |
750 | char flag = TTY_NORMAL; | |
1da177e4 LT |
751 | |
752 | pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); | |
753 | ||
754 | rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); | |
755 | ||
756 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); | |
757 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
758 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
759 | invalidate_dcache_range((ulong)rxre, | |
760 | (ulong)rxre + MPSC_RXRE_SIZE); | |
761 | #endif | |
762 | ||
763 | /* | |
764 | * Loop through Rx descriptors handling ones that have been completed. | |
765 | */ | |
766 | while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){ | |
767 | bytes_in = be16_to_cpu(rxre->bytecnt); | |
768 | ||
769 | /* Following use of tty struct directly is deprecated */ | |
770 | if (unlikely((tty->flip.count + bytes_in) >= TTY_FLIPBUF_SIZE)){ | |
771 | if (tty->low_latency) | |
772 | tty_flip_buffer_push(tty); | |
773 | /* | |
774 | * If this failed then we will throw awa the bytes | |
775 | * but mst do so to clear interrupts. | |
776 | */ | |
777 | } | |
778 | ||
779 | bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); | |
780 | dma_cache_sync((void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE); | |
781 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
782 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
783 | invalidate_dcache_range((ulong)bp, | |
784 | (ulong)bp + MPSC_RXBE_SIZE); | |
785 | #endif | |
786 | ||
787 | /* | |
788 | * Other than for parity error, the manual provides little | |
789 | * info on what data will be in a frame flagged by any of | |
790 | * these errors. For parity error, it is the last byte in | |
791 | * the buffer that had the error. As for the rest, I guess | |
792 | * we'll assume there is no data in the buffer. | |
793 | * If there is...it gets lost. | |
794 | */ | |
795 | if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | | |
796 | SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) { | |
797 | ||
798 | pi->port.icount.rx++; | |
799 | ||
800 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */ | |
801 | pi->port.icount.brk++; | |
802 | ||
803 | if (uart_handle_break(&pi->port)) | |
804 | goto next_frame; | |
805 | } | |
806 | else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */ | |
807 | pi->port.icount.frame++; | |
808 | else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */ | |
809 | pi->port.icount.overrun++; | |
810 | ||
811 | cmdstat &= pi->port.read_status_mask; | |
812 | ||
813 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) | |
814 | flag = TTY_BREAK; | |
815 | else if (cmdstat & SDMA_DESC_CMDSTAT_FR) | |
816 | flag = TTY_FRAME; | |
817 | else if (cmdstat & SDMA_DESC_CMDSTAT_OR) | |
818 | flag = TTY_OVERRUN; | |
819 | else if (cmdstat & SDMA_DESC_CMDSTAT_PE) | |
820 | flag = TTY_PARITY; | |
821 | } | |
822 | ||
823 | if (uart_handle_sysrq_char(&pi->port, *bp, regs)) { | |
824 | bp++; | |
825 | bytes_in--; | |
826 | goto next_frame; | |
827 | } | |
828 | ||
829 | if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | | |
830 | SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && | |
831 | !(cmdstat & pi->port.ignore_status_mask)) | |
832 | ||
833 | tty_insert_flip_char(tty, *bp, flag); | |
834 | else { | |
835 | for (i=0; i<bytes_in; i++) | |
836 | tty_insert_flip_char(tty, *bp++, TTY_NORMAL); | |
837 | ||
838 | pi->port.icount.rx += bytes_in; | |
839 | } | |
840 | ||
841 | next_frame: | |
842 | rxre->bytecnt = cpu_to_be16(0); | |
843 | wmb(); | |
844 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | | |
845 | SDMA_DESC_CMDSTAT_EI | | |
846 | SDMA_DESC_CMDSTAT_F | | |
847 | SDMA_DESC_CMDSTAT_L); | |
848 | wmb(); | |
849 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); | |
850 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
851 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
852 | flush_dcache_range((ulong)rxre, | |
853 | (ulong)rxre + MPSC_RXRE_SIZE); | |
854 | #endif | |
855 | ||
856 | /* Advance to next descriptor */ | |
857 | pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); | |
858 | rxre = (struct mpsc_rx_desc *)(pi->rxr + | |
859 | (pi->rxr_posn * MPSC_RXRE_SIZE)); | |
860 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); | |
861 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
862 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
863 | invalidate_dcache_range((ulong)rxre, | |
864 | (ulong)rxre + MPSC_RXRE_SIZE); | |
865 | #endif | |
866 | ||
867 | rc = 1; | |
868 | } | |
869 | ||
870 | /* Restart rx engine, if its stopped */ | |
871 | if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) | |
872 | mpsc_start_rx(pi); | |
873 | ||
874 | tty_flip_buffer_push(tty); | |
875 | return rc; | |
876 | } | |
877 | ||
878 | static inline void | |
879 | mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) | |
880 | { | |
881 | struct mpsc_tx_desc *txre; | |
882 | ||
883 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
884 | (pi->txr_head * MPSC_TXRE_SIZE)); | |
885 | ||
886 | txre->bytecnt = cpu_to_be16(count); | |
887 | txre->shadow = txre->bytecnt; | |
888 | wmb(); /* ensure cmdstat is last field updated */ | |
889 | txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F | | |
890 | SDMA_DESC_CMDSTAT_L | ((intr) ? | |
891 | SDMA_DESC_CMDSTAT_EI | |
892 | : 0)); | |
893 | wmb(); | |
894 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL); | |
895 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
896 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
897 | flush_dcache_range((ulong)txre, | |
898 | (ulong)txre + MPSC_TXRE_SIZE); | |
899 | #endif | |
900 | ||
901 | return; | |
902 | } | |
903 | ||
904 | static inline void | |
905 | mpsc_copy_tx_data(struct mpsc_port_info *pi) | |
906 | { | |
907 | struct circ_buf *xmit = &pi->port.info->xmit; | |
908 | u8 *bp; | |
909 | u32 i; | |
910 | ||
911 | /* Make sure the desc ring isn't full */ | |
912 | while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) < | |
913 | (MPSC_TXR_ENTRIES - 1)) { | |
914 | if (pi->port.x_char) { | |
915 | /* | |
916 | * Ideally, we should use the TCS field in | |
917 | * CHR_1 to put the x_char out immediately but | |
918 | * errata prevents us from being able to read | |
919 | * CHR_2 to know that its safe to write to | |
920 | * CHR_1. Instead, just put it in-band with | |
921 | * all the other Tx data. | |
922 | */ | |
923 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
924 | *bp = pi->port.x_char; | |
925 | pi->port.x_char = 0; | |
926 | i = 1; | |
927 | } | |
928 | else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){ | |
929 | i = min((u32) MPSC_TXBE_SIZE, | |
930 | (u32) uart_circ_chars_pending(xmit)); | |
931 | i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail, | |
932 | UART_XMIT_SIZE)); | |
933 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
934 | memcpy(bp, &xmit->buf[xmit->tail], i); | |
935 | xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1); | |
936 | ||
937 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
938 | uart_write_wakeup(&pi->port); | |
939 | } | |
940 | else /* All tx data copied into ring bufs */ | |
941 | return; | |
942 | ||
943 | dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); | |
944 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
945 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
946 | flush_dcache_range((ulong)bp, | |
947 | (ulong)bp + MPSC_TXBE_SIZE); | |
948 | #endif | |
949 | mpsc_setup_tx_desc(pi, i, 1); | |
950 | ||
951 | /* Advance to next descriptor */ | |
952 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); | |
953 | } | |
954 | ||
955 | return; | |
956 | } | |
957 | ||
958 | static inline int | |
959 | mpsc_tx_intr(struct mpsc_port_info *pi) | |
960 | { | |
961 | struct mpsc_tx_desc *txre; | |
962 | int rc = 0; | |
963 | ||
964 | if (!mpsc_sdma_tx_active(pi)) { | |
965 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
966 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
967 | ||
968 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); | |
969 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
970 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
971 | invalidate_dcache_range((ulong)txre, | |
972 | (ulong)txre + MPSC_TXRE_SIZE); | |
973 | #endif | |
974 | ||
975 | while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) { | |
976 | rc = 1; | |
977 | pi->port.icount.tx += be16_to_cpu(txre->bytecnt); | |
978 | pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); | |
979 | ||
980 | /* If no more data to tx, fall out of loop */ | |
981 | if (pi->txr_head == pi->txr_tail) | |
982 | break; | |
983 | ||
984 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
985 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
986 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, | |
987 | DMA_FROM_DEVICE); | |
988 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
989 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
990 | invalidate_dcache_range((ulong)txre, | |
991 | (ulong)txre + MPSC_TXRE_SIZE); | |
992 | #endif | |
993 | } | |
994 | ||
995 | mpsc_copy_tx_data(pi); | |
996 | mpsc_sdma_start_tx(pi); /* start next desc if ready */ | |
997 | } | |
998 | ||
999 | return rc; | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * This is the driver's interrupt handler. To avoid a race, we first clear | |
1004 | * the interrupt, then handle any completed Rx/Tx descriptors. When done | |
1005 | * handling those descriptors, we restart the Rx/Tx engines if they're stopped. | |
1006 | */ | |
1007 | static irqreturn_t | |
1008 | mpsc_sdma_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1009 | { | |
1010 | struct mpsc_port_info *pi = dev_id; | |
1011 | ulong iflags; | |
1012 | int rc = IRQ_NONE; | |
1013 | ||
1014 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); | |
1015 | ||
1016 | spin_lock_irqsave(&pi->port.lock, iflags); | |
1017 | mpsc_sdma_intr_ack(pi); | |
1018 | if (mpsc_rx_intr(pi, regs)) | |
1019 | rc = IRQ_HANDLED; | |
1020 | if (mpsc_tx_intr(pi)) | |
1021 | rc = IRQ_HANDLED; | |
1022 | spin_unlock_irqrestore(&pi->port.lock, iflags); | |
1023 | ||
1024 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); | |
1025 | return rc; | |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | ****************************************************************************** | |
1030 | * | |
1031 | * serial_core.c Interface routines | |
1032 | * | |
1033 | ****************************************************************************** | |
1034 | */ | |
1035 | static uint | |
1036 | mpsc_tx_empty(struct uart_port *port) | |
1037 | { | |
1038 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1039 | ulong iflags; | |
1040 | uint rc; | |
1041 | ||
1042 | spin_lock_irqsave(&pi->port.lock, iflags); | |
1043 | rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; | |
1044 | spin_unlock_irqrestore(&pi->port.lock, iflags); | |
1045 | ||
1046 | return rc; | |
1047 | } | |
1048 | ||
1049 | static void | |
1050 | mpsc_set_mctrl(struct uart_port *port, uint mctrl) | |
1051 | { | |
1052 | /* Have no way to set modem control lines AFAICT */ | |
1053 | return; | |
1054 | } | |
1055 | ||
1056 | static uint | |
1057 | mpsc_get_mctrl(struct uart_port *port) | |
1058 | { | |
1059 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1060 | u32 mflags, status; | |
1da177e4 | 1061 | |
1da177e4 LT |
1062 | status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : |
1063 | readl(pi->mpsc_base + MPSC_CHR_10); | |
1da177e4 LT |
1064 | |
1065 | mflags = 0; | |
1066 | if (status & 0x1) | |
1067 | mflags |= TIOCM_CTS; | |
1068 | if (status & 0x2) | |
1069 | mflags |= TIOCM_CAR; | |
1070 | ||
1071 | return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ | |
1072 | } | |
1073 | ||
1074 | static void | |
b129a8cc | 1075 | mpsc_stop_tx(struct uart_port *port) |
1da177e4 LT |
1076 | { |
1077 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1078 | ||
b129a8cc | 1079 | pr_debug("mpsc_stop_tx[%d]\n", port->line); |
1da177e4 LT |
1080 | |
1081 | mpsc_freeze(pi); | |
1082 | return; | |
1083 | } | |
1084 | ||
1085 | static void | |
b129a8cc | 1086 | mpsc_start_tx(struct uart_port *port) |
1da177e4 LT |
1087 | { |
1088 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1089 | ||
1090 | mpsc_unfreeze(pi); | |
1091 | mpsc_copy_tx_data(pi); | |
1092 | mpsc_sdma_start_tx(pi); | |
1093 | ||
b129a8cc | 1094 | pr_debug("mpsc_start_tx[%d]\n", port->line); |
1da177e4 LT |
1095 | return; |
1096 | } | |
1097 | ||
1098 | static void | |
1099 | mpsc_start_rx(struct mpsc_port_info *pi) | |
1100 | { | |
1101 | pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); | |
1102 | ||
1103 | if (pi->rcv_data) { | |
1104 | mpsc_enter_hunt(pi); | |
1105 | mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); | |
1106 | } | |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | static void | |
1111 | mpsc_stop_rx(struct uart_port *port) | |
1112 | { | |
1113 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1114 | ||
1115 | pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line); | |
1116 | ||
1117 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR); | |
1118 | return; | |
1119 | } | |
1120 | ||
1121 | static void | |
1122 | mpsc_enable_ms(struct uart_port *port) | |
1123 | { | |
1124 | return; /* Not supported */ | |
1125 | } | |
1126 | ||
1127 | static void | |
1128 | mpsc_break_ctl(struct uart_port *port, int ctl) | |
1129 | { | |
1130 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1131 | ulong flags; | |
1132 | u32 v; | |
1133 | ||
1134 | v = ctl ? 0x00ff0000 : 0; | |
1135 | ||
1136 | spin_lock_irqsave(&pi->port.lock, flags); | |
1137 | if (pi->mirror_regs) | |
1138 | pi->MPSC_CHR_1_m = v; | |
1139 | writel(v, pi->mpsc_base + MPSC_CHR_1); | |
1140 | spin_unlock_irqrestore(&pi->port.lock, flags); | |
1141 | ||
1142 | return; | |
1143 | } | |
1144 | ||
1145 | static int | |
1146 | mpsc_startup(struct uart_port *port) | |
1147 | { | |
1148 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1149 | u32 flag = 0; | |
1150 | int rc; | |
1151 | ||
1152 | pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n", | |
1153 | port->line, pi->port.irq); | |
1154 | ||
1155 | if ((rc = mpsc_make_ready(pi)) == 0) { | |
1156 | /* Setup IRQ handler */ | |
1157 | mpsc_sdma_intr_ack(pi); | |
1158 | ||
1159 | /* If irq's are shared, need to set flag */ | |
1160 | if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq) | |
1161 | flag = SA_SHIRQ; | |
1162 | ||
1163 | if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, | |
1164 | "mpsc/sdma", pi)) | |
1165 | printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", | |
1166 | pi->port.irq); | |
1167 | ||
1168 | mpsc_sdma_intr_unmask(pi, 0xf); | |
1169 | mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p + | |
1170 | (pi->rxr_posn * MPSC_RXRE_SIZE))); | |
1171 | } | |
1172 | ||
1173 | return rc; | |
1174 | } | |
1175 | ||
1176 | static void | |
1177 | mpsc_shutdown(struct uart_port *port) | |
1178 | { | |
1179 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1da177e4 LT |
1180 | |
1181 | pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line); | |
1182 | ||
1183 | mpsc_sdma_stop(pi); | |
1184 | free_irq(pi->port.irq, pi); | |
1185 | return; | |
1186 | } | |
1187 | ||
1188 | static void | |
1189 | mpsc_set_termios(struct uart_port *port, struct termios *termios, | |
1190 | struct termios *old) | |
1191 | { | |
1192 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1193 | u32 baud; | |
1194 | ulong flags; | |
1195 | u32 chr_bits, stop_bits, par; | |
1196 | ||
1197 | pi->c_iflag = termios->c_iflag; | |
1198 | pi->c_cflag = termios->c_cflag; | |
1199 | ||
1200 | switch (termios->c_cflag & CSIZE) { | |
1201 | case CS5: | |
1202 | chr_bits = MPSC_MPCR_CL_5; | |
1203 | break; | |
1204 | case CS6: | |
1205 | chr_bits = MPSC_MPCR_CL_6; | |
1206 | break; | |
1207 | case CS7: | |
1208 | chr_bits = MPSC_MPCR_CL_7; | |
1209 | break; | |
1210 | case CS8: | |
1211 | default: | |
1212 | chr_bits = MPSC_MPCR_CL_8; | |
1213 | break; | |
1214 | } | |
1215 | ||
1216 | if (termios->c_cflag & CSTOPB) | |
1217 | stop_bits = MPSC_MPCR_SBL_2; | |
1218 | else | |
1219 | stop_bits = MPSC_MPCR_SBL_1; | |
1220 | ||
1221 | par = MPSC_CHR_2_PAR_EVEN; | |
1222 | if (termios->c_cflag & PARENB) | |
1223 | if (termios->c_cflag & PARODD) | |
1224 | par = MPSC_CHR_2_PAR_ODD; | |
1225 | #ifdef CMSPAR | |
1226 | if (termios->c_cflag & CMSPAR) { | |
1227 | if (termios->c_cflag & PARODD) | |
1228 | par = MPSC_CHR_2_PAR_MARK; | |
1229 | else | |
1230 | par = MPSC_CHR_2_PAR_SPACE; | |
1231 | } | |
1232 | #endif | |
1233 | ||
1234 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); | |
1235 | ||
1236 | spin_lock_irqsave(&pi->port.lock, flags); | |
1237 | ||
1238 | uart_update_timeout(port, termios->c_cflag, baud); | |
1239 | ||
1240 | mpsc_set_char_length(pi, chr_bits); | |
1241 | mpsc_set_stop_bit_length(pi, stop_bits); | |
1242 | mpsc_set_parity(pi, par); | |
1243 | mpsc_set_baudrate(pi, baud); | |
1244 | ||
1245 | /* Characters/events to read */ | |
1246 | pi->rcv_data = 1; | |
1247 | pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; | |
1248 | ||
1249 | if (termios->c_iflag & INPCK) | |
1250 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | | |
1251 | SDMA_DESC_CMDSTAT_FR; | |
1252 | ||
1253 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
1254 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; | |
1255 | ||
1256 | /* Characters/events to ignore */ | |
1257 | pi->port.ignore_status_mask = 0; | |
1258 | ||
1259 | if (termios->c_iflag & IGNPAR) | |
1260 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE | | |
1261 | SDMA_DESC_CMDSTAT_FR; | |
1262 | ||
1263 | if (termios->c_iflag & IGNBRK) { | |
1264 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; | |
1265 | ||
1266 | if (termios->c_iflag & IGNPAR) | |
1267 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; | |
1268 | } | |
1269 | ||
1270 | /* Ignore all chars if CREAD not set */ | |
1271 | if (!(termios->c_cflag & CREAD)) | |
1272 | pi->rcv_data = 0; | |
1273 | else | |
1274 | mpsc_start_rx(pi); | |
1275 | ||
1276 | spin_unlock_irqrestore(&pi->port.lock, flags); | |
1277 | return; | |
1278 | } | |
1279 | ||
1280 | static const char * | |
1281 | mpsc_type(struct uart_port *port) | |
1282 | { | |
1283 | pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); | |
1284 | return MPSC_DRIVER_NAME; | |
1285 | } | |
1286 | ||
1287 | static int | |
1288 | mpsc_request_port(struct uart_port *port) | |
1289 | { | |
1290 | /* Should make chip/platform specific call */ | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static void | |
1295 | mpsc_release_port(struct uart_port *port) | |
1296 | { | |
1297 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1298 | ||
1299 | if (pi->ready) { | |
1300 | mpsc_uninit_rings(pi); | |
1301 | mpsc_free_ring_mem(pi); | |
1302 | pi->ready = 0; | |
1303 | } | |
1304 | ||
1305 | return; | |
1306 | } | |
1307 | ||
1308 | static void | |
1309 | mpsc_config_port(struct uart_port *port, int flags) | |
1310 | { | |
1311 | return; | |
1312 | } | |
1313 | ||
1314 | static int | |
1315 | mpsc_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1316 | { | |
1317 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1318 | int rc = 0; | |
1319 | ||
1320 | pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); | |
1321 | ||
1322 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC) | |
1323 | rc = -EINVAL; | |
1324 | else if (pi->port.irq != ser->irq) | |
1325 | rc = -EINVAL; | |
1326 | else if (ser->io_type != SERIAL_IO_MEM) | |
1327 | rc = -EINVAL; | |
1328 | else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ | |
1329 | rc = -EINVAL; | |
1330 | else if ((void *)pi->port.mapbase != ser->iomem_base) | |
1331 | rc = -EINVAL; | |
1332 | else if (pi->port.iobase != ser->port) | |
1333 | rc = -EINVAL; | |
1334 | else if (ser->hub6 != 0) | |
1335 | rc = -EINVAL; | |
1336 | ||
1337 | return rc; | |
1338 | } | |
1339 | ||
1340 | static struct uart_ops mpsc_pops = { | |
1341 | .tx_empty = mpsc_tx_empty, | |
1342 | .set_mctrl = mpsc_set_mctrl, | |
1343 | .get_mctrl = mpsc_get_mctrl, | |
1344 | .stop_tx = mpsc_stop_tx, | |
1345 | .start_tx = mpsc_start_tx, | |
1346 | .stop_rx = mpsc_stop_rx, | |
1347 | .enable_ms = mpsc_enable_ms, | |
1348 | .break_ctl = mpsc_break_ctl, | |
1349 | .startup = mpsc_startup, | |
1350 | .shutdown = mpsc_shutdown, | |
1351 | .set_termios = mpsc_set_termios, | |
1352 | .type = mpsc_type, | |
1353 | .release_port = mpsc_release_port, | |
1354 | .request_port = mpsc_request_port, | |
1355 | .config_port = mpsc_config_port, | |
1356 | .verify_port = mpsc_verify_port, | |
1357 | }; | |
1358 | ||
1359 | /* | |
1360 | ****************************************************************************** | |
1361 | * | |
1362 | * Console Interface Routines | |
1363 | * | |
1364 | ****************************************************************************** | |
1365 | */ | |
1366 | ||
1367 | #ifdef CONFIG_SERIAL_MPSC_CONSOLE | |
1368 | static void | |
1369 | mpsc_console_write(struct console *co, const char *s, uint count) | |
1370 | { | |
1371 | struct mpsc_port_info *pi = &mpsc_ports[co->index]; | |
1372 | u8 *bp, *dp, add_cr = 0; | |
1373 | int i; | |
1374 | ||
1375 | while (mpsc_sdma_tx_active(pi)) | |
1376 | udelay(100); | |
1377 | ||
1378 | while (count > 0) { | |
1379 | bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
1380 | ||
1381 | for (i = 0; i < MPSC_TXBE_SIZE; i++) { | |
1382 | if (count == 0) | |
1383 | break; | |
1384 | ||
1385 | if (add_cr) { | |
1386 | *(dp++) = '\r'; | |
1387 | add_cr = 0; | |
1388 | } | |
1389 | else { | |
1390 | *(dp++) = *s; | |
1391 | ||
1392 | if (*(s++) == '\n') { /* add '\r' after '\n' */ | |
1393 | add_cr = 1; | |
1394 | count++; | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | count--; | |
1399 | } | |
1400 | ||
1401 | dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); | |
1402 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
1403 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
1404 | flush_dcache_range((ulong)bp, | |
1405 | (ulong)bp + MPSC_TXBE_SIZE); | |
1406 | #endif | |
1407 | mpsc_setup_tx_desc(pi, i, 0); | |
1408 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); | |
1409 | mpsc_sdma_start_tx(pi); | |
1410 | ||
1411 | while (mpsc_sdma_tx_active(pi)) | |
1412 | udelay(100); | |
1413 | ||
1414 | pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); | |
1415 | } | |
1416 | ||
1417 | return; | |
1418 | } | |
1419 | ||
1420 | static int __init | |
1421 | mpsc_console_setup(struct console *co, char *options) | |
1422 | { | |
1423 | struct mpsc_port_info *pi; | |
1424 | int baud, bits, parity, flow; | |
1425 | ||
1426 | pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options); | |
1427 | ||
1428 | if (co->index >= MPSC_NUM_CTLRS) | |
1429 | co->index = 0; | |
1430 | ||
1431 | pi = &mpsc_ports[co->index]; | |
1432 | ||
1433 | baud = pi->default_baud; | |
1434 | bits = pi->default_bits; | |
1435 | parity = pi->default_parity; | |
1436 | flow = pi->default_flow; | |
1437 | ||
1438 | if (!pi->port.ops) | |
1439 | return -ENODEV; | |
1440 | ||
1441 | spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ | |
1442 | ||
1443 | if (options) | |
1444 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1445 | ||
1446 | return uart_set_options(&pi->port, co, baud, parity, bits, flow); | |
1447 | } | |
1448 | ||
1da177e4 LT |
1449 | static struct console mpsc_console = { |
1450 | .name = MPSC_DEV_NAME, | |
1451 | .write = mpsc_console_write, | |
1452 | .device = uart_console_device, | |
1453 | .setup = mpsc_console_setup, | |
1454 | .flags = CON_PRINTBUFFER, | |
1455 | .index = -1, | |
1456 | .data = &mpsc_reg, | |
1457 | }; | |
1458 | ||
1459 | static int __init | |
1460 | mpsc_late_console_init(void) | |
1461 | { | |
1462 | pr_debug("mpsc_late_console_init: Enter\n"); | |
1463 | ||
1464 | if (!(mpsc_console.flags & CON_ENABLED)) | |
1465 | register_console(&mpsc_console); | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | late_initcall(mpsc_late_console_init); | |
1470 | ||
1471 | #define MPSC_CONSOLE &mpsc_console | |
1472 | #else | |
1473 | #define MPSC_CONSOLE NULL | |
1474 | #endif | |
1475 | /* | |
1476 | ****************************************************************************** | |
1477 | * | |
1478 | * Dummy Platform Driver to extract & map shared register regions | |
1479 | * | |
1480 | ****************************************************************************** | |
1481 | */ | |
1482 | static void | |
1483 | mpsc_resource_err(char *s) | |
1484 | { | |
1485 | printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | static int | |
1490 | mpsc_shared_map_regs(struct platform_device *pd) | |
1491 | { | |
1492 | struct resource *r; | |
1493 | ||
1494 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1495 | MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start, | |
1496 | MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) { | |
1497 | ||
1498 | mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, | |
1499 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1500 | mpsc_shared_regs.mpsc_routing_base_p = r->start; | |
1501 | } | |
1502 | else { | |
1503 | mpsc_resource_err("MPSC routing base"); | |
1504 | return -ENOMEM; | |
1505 | } | |
1506 | ||
1507 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1508 | MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start, | |
1509 | MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) { | |
1510 | ||
1511 | mpsc_shared_regs.sdma_intr_base = ioremap(r->start, | |
1512 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); | |
1513 | mpsc_shared_regs.sdma_intr_base_p = r->start; | |
1514 | } | |
1515 | else { | |
1516 | iounmap(mpsc_shared_regs.mpsc_routing_base); | |
1517 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, | |
1518 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1519 | mpsc_resource_err("SDMA intr base"); | |
1520 | return -ENOMEM; | |
1521 | } | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | static void | |
1527 | mpsc_shared_unmap_regs(void) | |
1528 | { | |
1529 | if (!mpsc_shared_regs.mpsc_routing_base) { | |
1530 | iounmap(mpsc_shared_regs.mpsc_routing_base); | |
1531 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, | |
1532 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1533 | } | |
1534 | if (!mpsc_shared_regs.sdma_intr_base) { | |
1535 | iounmap(mpsc_shared_regs.sdma_intr_base); | |
1536 | release_mem_region(mpsc_shared_regs.sdma_intr_base_p, | |
1537 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); | |
1538 | } | |
1539 | ||
2c6e7599 AV |
1540 | mpsc_shared_regs.mpsc_routing_base = NULL; |
1541 | mpsc_shared_regs.sdma_intr_base = NULL; | |
1da177e4 LT |
1542 | |
1543 | mpsc_shared_regs.mpsc_routing_base_p = 0; | |
1544 | mpsc_shared_regs.sdma_intr_base_p = 0; | |
1545 | ||
1546 | return; | |
1547 | } | |
1548 | ||
1549 | static int | |
1550 | mpsc_shared_drv_probe(struct device *dev) | |
1551 | { | |
1552 | struct platform_device *pd = to_platform_device(dev); | |
1553 | struct mpsc_shared_pdata *pdata; | |
1554 | int rc = -ENODEV; | |
1555 | ||
1556 | if (pd->id == 0) { | |
1557 | if (!(rc = mpsc_shared_map_regs(pd))) { | |
1558 | pdata = (struct mpsc_shared_pdata *)dev->platform_data; | |
1559 | ||
1560 | mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; | |
1561 | mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; | |
1562 | mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val; | |
1563 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = | |
1564 | pdata->intr_cause_val; | |
1565 | mpsc_shared_regs.SDMA_INTR_MASK_m = | |
1566 | pdata->intr_mask_val; | |
1567 | ||
1568 | rc = 0; | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | return rc; | |
1573 | } | |
1574 | ||
1575 | static int | |
1576 | mpsc_shared_drv_remove(struct device *dev) | |
1577 | { | |
1578 | struct platform_device *pd = to_platform_device(dev); | |
1579 | int rc = -ENODEV; | |
1580 | ||
1581 | if (pd->id == 0) { | |
1582 | mpsc_shared_unmap_regs(); | |
1583 | mpsc_shared_regs.MPSC_MRR_m = 0; | |
1584 | mpsc_shared_regs.MPSC_RCRR_m = 0; | |
1585 | mpsc_shared_regs.MPSC_TCRR_m = 0; | |
1586 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0; | |
1587 | mpsc_shared_regs.SDMA_INTR_MASK_m = 0; | |
1588 | rc = 0; | |
1589 | } | |
1590 | ||
1591 | return rc; | |
1592 | } | |
1593 | ||
1594 | static struct device_driver mpsc_shared_driver = { | |
1595 | .name = MPSC_SHARED_NAME, | |
1596 | .bus = &platform_bus_type, | |
1597 | .probe = mpsc_shared_drv_probe, | |
1598 | .remove = mpsc_shared_drv_remove, | |
1599 | }; | |
1600 | ||
1601 | /* | |
1602 | ****************************************************************************** | |
1603 | * | |
1604 | * Driver Interface Routines | |
1605 | * | |
1606 | ****************************************************************************** | |
1607 | */ | |
1608 | static struct uart_driver mpsc_reg = { | |
1609 | .owner = THIS_MODULE, | |
1610 | .driver_name = MPSC_DRIVER_NAME, | |
1611 | .devfs_name = MPSC_DEVFS_NAME, | |
1612 | .dev_name = MPSC_DEV_NAME, | |
1613 | .major = MPSC_MAJOR, | |
1614 | .minor = MPSC_MINOR_START, | |
1615 | .nr = MPSC_NUM_CTLRS, | |
1616 | .cons = MPSC_CONSOLE, | |
1617 | }; | |
1618 | ||
1619 | static int | |
1620 | mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) | |
1621 | { | |
1622 | struct resource *r; | |
1623 | ||
1624 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) && | |
1625 | request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){ | |
1626 | ||
1627 | pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); | |
1628 | pi->mpsc_base_p = r->start; | |
1629 | } | |
1630 | else { | |
1631 | mpsc_resource_err("MPSC base"); | |
1632 | return -ENOMEM; | |
1633 | } | |
1634 | ||
1635 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1636 | MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start, | |
1637 | MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { | |
1638 | ||
1639 | pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); | |
1640 | pi->sdma_base_p = r->start; | |
1641 | } | |
1642 | else { | |
1643 | mpsc_resource_err("SDMA base"); | |
1644 | return -ENOMEM; | |
1645 | } | |
1646 | ||
1647 | if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) | |
1648 | && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE, | |
1649 | "brg_regs")) { | |
1650 | ||
1651 | pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); | |
1652 | pi->brg_base_p = r->start; | |
1653 | } | |
1654 | else { | |
1655 | mpsc_resource_err("BRG base"); | |
1656 | return -ENOMEM; | |
1657 | } | |
1658 | ||
1659 | return 0; | |
1660 | } | |
1661 | ||
1662 | static void | |
1663 | mpsc_drv_unmap_regs(struct mpsc_port_info *pi) | |
1664 | { | |
1665 | if (!pi->mpsc_base) { | |
1666 | iounmap(pi->mpsc_base); | |
1667 | release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); | |
1668 | } | |
1669 | if (!pi->sdma_base) { | |
1670 | iounmap(pi->sdma_base); | |
1671 | release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); | |
1672 | } | |
1673 | if (!pi->brg_base) { | |
1674 | iounmap(pi->brg_base); | |
1675 | release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); | |
1676 | } | |
1677 | ||
2c6e7599 AV |
1678 | pi->mpsc_base = NULL; |
1679 | pi->sdma_base = NULL; | |
1680 | pi->brg_base = NULL; | |
1da177e4 LT |
1681 | |
1682 | pi->mpsc_base_p = 0; | |
1683 | pi->sdma_base_p = 0; | |
1684 | pi->brg_base_p = 0; | |
1685 | ||
1686 | return; | |
1687 | } | |
1688 | ||
1689 | static void | |
1690 | mpsc_drv_get_platform_data(struct mpsc_port_info *pi, | |
1691 | struct platform_device *pd, int num) | |
1692 | { | |
1693 | struct mpsc_pdata *pdata; | |
1694 | ||
1695 | pdata = (struct mpsc_pdata *)pd->dev.platform_data; | |
1696 | ||
1697 | pi->port.uartclk = pdata->brg_clk_freq; | |
1698 | pi->port.iotype = UPIO_MEM; | |
1699 | pi->port.line = num; | |
1700 | pi->port.type = PORT_MPSC; | |
1701 | pi->port.fifosize = MPSC_TXBE_SIZE; | |
1702 | pi->port.membase = pi->mpsc_base; | |
1703 | pi->port.mapbase = (ulong)pi->mpsc_base; | |
1704 | pi->port.ops = &mpsc_pops; | |
1705 | ||
1706 | pi->mirror_regs = pdata->mirror_regs; | |
1707 | pi->cache_mgmt = pdata->cache_mgmt; | |
1708 | pi->brg_can_tune = pdata->brg_can_tune; | |
1709 | pi->brg_clk_src = pdata->brg_clk_src; | |
1710 | pi->mpsc_max_idle = pdata->max_idle; | |
1711 | pi->default_baud = pdata->default_baud; | |
1712 | pi->default_bits = pdata->default_bits; | |
1713 | pi->default_parity = pdata->default_parity; | |
1714 | pi->default_flow = pdata->default_flow; | |
1715 | ||
1716 | /* Initial values of mirrored regs */ | |
1717 | pi->MPSC_CHR_1_m = pdata->chr_1_val; | |
1718 | pi->MPSC_CHR_2_m = pdata->chr_2_val; | |
1719 | pi->MPSC_CHR_10_m = pdata->chr_10_val; | |
1720 | pi->MPSC_MPCR_m = pdata->mpcr_val; | |
1721 | pi->BRG_BCR_m = pdata->bcr_val; | |
1722 | ||
1723 | pi->shared_regs = &mpsc_shared_regs; | |
1724 | ||
1725 | pi->port.irq = platform_get_irq(pd, 0); | |
1726 | ||
1727 | return; | |
1728 | } | |
1729 | ||
1730 | static int | |
1731 | mpsc_drv_probe(struct device *dev) | |
1732 | { | |
1733 | struct platform_device *pd = to_platform_device(dev); | |
1734 | struct mpsc_port_info *pi; | |
1735 | int rc = -ENODEV; | |
1736 | ||
1737 | pr_debug("mpsc_drv_probe: Adding MPSC %d\n", pd->id); | |
1738 | ||
1739 | if (pd->id < MPSC_NUM_CTLRS) { | |
1740 | pi = &mpsc_ports[pd->id]; | |
1741 | ||
1742 | if (!(rc = mpsc_drv_map_regs(pi, pd))) { | |
1743 | mpsc_drv_get_platform_data(pi, pd, pd->id); | |
1744 | ||
1745 | if (!(rc = mpsc_make_ready(pi))) | |
1746 | if (!(rc = uart_add_one_port(&mpsc_reg, | |
1747 | &pi->port))) | |
1748 | rc = 0; | |
1749 | else { | |
1750 | mpsc_release_port( | |
1751 | (struct uart_port *)pi); | |
1752 | mpsc_drv_unmap_regs(pi); | |
1753 | } | |
1754 | else | |
1755 | mpsc_drv_unmap_regs(pi); | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | return rc; | |
1760 | } | |
1761 | ||
1762 | static int | |
1763 | mpsc_drv_remove(struct device *dev) | |
1764 | { | |
1765 | struct platform_device *pd = to_platform_device(dev); | |
1766 | ||
1767 | pr_debug("mpsc_drv_exit: Removing MPSC %d\n", pd->id); | |
1768 | ||
1769 | if (pd->id < MPSC_NUM_CTLRS) { | |
1770 | uart_remove_one_port(&mpsc_reg, &mpsc_ports[pd->id].port); | |
1771 | mpsc_release_port((struct uart_port *)&mpsc_ports[pd->id].port); | |
1772 | mpsc_drv_unmap_regs(&mpsc_ports[pd->id]); | |
1773 | return 0; | |
1774 | } | |
1775 | else | |
1776 | return -ENODEV; | |
1777 | } | |
1778 | ||
1779 | static struct device_driver mpsc_driver = { | |
1780 | .name = MPSC_CTLR_NAME, | |
1781 | .bus = &platform_bus_type, | |
1782 | .probe = mpsc_drv_probe, | |
1783 | .remove = mpsc_drv_remove, | |
1784 | }; | |
1785 | ||
1786 | static int __init | |
1787 | mpsc_drv_init(void) | |
1788 | { | |
1789 | int rc; | |
1790 | ||
1791 | printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n"); | |
1792 | ||
1793 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); | |
1794 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); | |
1795 | ||
1796 | if (!(rc = uart_register_driver(&mpsc_reg))) { | |
1797 | if (!(rc = driver_register(&mpsc_shared_driver))) { | |
1798 | if ((rc = driver_register(&mpsc_driver))) { | |
1799 | driver_unregister(&mpsc_shared_driver); | |
1800 | uart_unregister_driver(&mpsc_reg); | |
1801 | } | |
1802 | } | |
1803 | else | |
1804 | uart_unregister_driver(&mpsc_reg); | |
1805 | } | |
1806 | ||
1807 | return rc; | |
1808 | ||
1809 | } | |
1810 | ||
1811 | static void __exit | |
1812 | mpsc_drv_exit(void) | |
1813 | { | |
1814 | driver_unregister(&mpsc_driver); | |
1815 | driver_unregister(&mpsc_shared_driver); | |
1816 | uart_unregister_driver(&mpsc_reg); | |
1817 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); | |
1818 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); | |
1819 | return; | |
1820 | } | |
1821 | ||
1822 | module_init(mpsc_drv_init); | |
1823 | module_exit(mpsc_drv_exit); | |
1824 | ||
1825 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
1826 | MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $"); | |
1827 | MODULE_VERSION(MPSC_VERSION); | |
1828 | MODULE_LICENSE("GPL"); | |
1829 | MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR); |