Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/imx.c | |
3 | * | |
4 | * Driver for Motorola IMX serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Author: Sascha Hauer <sascha@saschahauer.de> | |
9 | * Copyright (C) 2004 Pengutronix | |
10 | * | |
b6e49138 FG |
11 | * Copyright (C) 2009 emlix GmbH |
12 | * Author: Fabian Godehardt (added IrDA support for iMX) | |
13 | * | |
1da177e4 LT |
14 | * This program is free software; you can redistribute it and/or modify |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | * | |
28 | * [29-Mar-2005] Mike Lee | |
29 | * Added hardware handshake | |
30 | */ | |
1da177e4 LT |
31 | |
32 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
33 | #define SUPPORT_SYSRQ | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 LT |
42 | #include <linux/tty.h> |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | #include <linux/serial.h> | |
38a41fdf | 46 | #include <linux/clk.h> |
b6e49138 | 47 | #include <linux/delay.h> |
534fca06 | 48 | #include <linux/rational.h> |
1da177e4 LT |
49 | |
50 | #include <asm/io.h> | |
51 | #include <asm/irq.h> | |
a09e64fb RK |
52 | #include <mach/hardware.h> |
53 | #include <mach/imx-uart.h> | |
1da177e4 | 54 | |
ff4bfb21 SH |
55 | /* Register definitions */ |
56 | #define URXD0 0x0 /* Receiver Register */ | |
57 | #define URTX0 0x40 /* Transmitter Register */ | |
58 | #define UCR1 0x80 /* Control Register 1 */ | |
59 | #define UCR2 0x84 /* Control Register 2 */ | |
60 | #define UCR3 0x88 /* Control Register 3 */ | |
61 | #define UCR4 0x8c /* Control Register 4 */ | |
62 | #define UFCR 0x90 /* FIFO Control Register */ | |
63 | #define USR1 0x94 /* Status Register 1 */ | |
64 | #define USR2 0x98 /* Status Register 2 */ | |
65 | #define UESC 0x9c /* Escape Character Register */ | |
66 | #define UTIM 0xa0 /* Escape Timer Register */ | |
67 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
68 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
69 | #define UBRC 0xac /* Baud Rate Count Register */ | |
37d6fb62 SH |
70 | #define MX2_ONEMS 0xb0 /* One Millisecond register */ |
71 | #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */ | |
ff4bfb21 SH |
72 | |
73 | /* UART Control Register Bit Fields.*/ | |
74 | #define URXD_CHARRDY (1<<15) | |
75 | #define URXD_ERR (1<<14) | |
76 | #define URXD_OVRRUN (1<<13) | |
77 | #define URXD_FRMERR (1<<12) | |
78 | #define URXD_BRK (1<<11) | |
79 | #define URXD_PRERR (1<<10) | |
80 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ | |
81 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
82 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
83 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
84 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | |
85 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
86 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
87 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
88 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
89 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
90 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
37d6fb62 | 91 | #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */ |
ff4bfb21 SH |
92 | #define UCR1_DOZE (1<<1) /* Doze */ |
93 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
94 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | |
95 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
96 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
97 | #define UCR2_CTS (1<<12) /* Clear to send */ | |
98 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
99 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
100 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
101 | #define UCR2_STPB (1<<6) /* Stop */ | |
102 | #define UCR2_WS (1<<5) /* Word size */ | |
103 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
104 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
105 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
106 | #define UCR2_SRST (1<<0) /* SW reset */ | |
107 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
108 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | |
109 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
110 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
111 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
112 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
113 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | |
114 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | |
115 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
116 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
37d6fb62 SH |
117 | #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ |
118 | #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | |
119 | #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */ | |
ff4bfb21 SH |
120 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
121 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
122 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ | |
123 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | |
124 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
125 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
126 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
127 | #define UCR4_IRSC (1<<5) /* IR special case */ | |
128 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
129 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
130 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
131 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
132 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | |
133 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
b6e49138 | 134 | #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) |
ff4bfb21 SH |
135 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
136 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
137 | #define USR1_RTSS (1<<14) /* RTS pin status */ | |
138 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
139 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
140 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
141 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | |
142 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
143 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
144 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | |
145 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | |
146 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | |
147 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
148 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
149 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
150 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
151 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
152 | #define USR2_WAKE (1<<7) /* Wake */ | |
153 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
154 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
155 | #define USR2_BRCD (1<<2) /* Break condition */ | |
156 | #define USR2_ORE (1<<1) /* Overrun error */ | |
157 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
158 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
159 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
160 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
161 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
162 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | |
163 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
164 | #define UTS_SOFTRST (1<<0) /* Software reset */ | |
165 | ||
1da177e4 | 166 | /* We've been assigned a range on the "Low-density serial ports" major */ |
e3d13ff4 SH |
167 | #define SERIAL_IMX_MAJOR 207 |
168 | #define MINOR_START 16 | |
169 | #define DEV_NAME "ttymxc" | |
9d631b83 | 170 | #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS |
1da177e4 | 171 | |
1da177e4 LT |
172 | /* |
173 | * This determines how often we check the modem status signals | |
174 | * for any change. They generally aren't connected to an IRQ | |
175 | * so we have to poll them. We also check immediately before | |
176 | * filling the TX fifo incase CTS has been dropped. | |
177 | */ | |
178 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
179 | ||
180 | #define DRIVER_NAME "IMX-uart" | |
181 | ||
dbff4e9e SH |
182 | #define UART_NR 8 |
183 | ||
1da177e4 LT |
184 | struct imx_port { |
185 | struct uart_port port; | |
186 | struct timer_list timer; | |
187 | unsigned int old_status; | |
5b802344 | 188 | int txirq,rxirq,rtsirq; |
26bbb3ff | 189 | unsigned int have_rtscts:1; |
b6e49138 FG |
190 | unsigned int use_irda:1; |
191 | unsigned int irda_inv_rx:1; | |
192 | unsigned int irda_inv_tx:1; | |
193 | unsigned short trcv_delay; /* transceiver delay */ | |
38a41fdf | 194 | struct clk *clk; |
1da177e4 LT |
195 | }; |
196 | ||
b6e49138 FG |
197 | #ifdef CONFIG_IRDA |
198 | #define USE_IRDA(sport) ((sport)->use_irda) | |
199 | #else | |
200 | #define USE_IRDA(sport) (0) | |
201 | #endif | |
202 | ||
1da177e4 LT |
203 | /* |
204 | * Handle any change of modem status signal since we were last called. | |
205 | */ | |
206 | static void imx_mctrl_check(struct imx_port *sport) | |
207 | { | |
208 | unsigned int status, changed; | |
209 | ||
210 | status = sport->port.ops->get_mctrl(&sport->port); | |
211 | changed = status ^ sport->old_status; | |
212 | ||
213 | if (changed == 0) | |
214 | return; | |
215 | ||
216 | sport->old_status = status; | |
217 | ||
218 | if (changed & TIOCM_RI) | |
219 | sport->port.icount.rng++; | |
220 | if (changed & TIOCM_DSR) | |
221 | sport->port.icount.dsr++; | |
222 | if (changed & TIOCM_CAR) | |
223 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
224 | if (changed & TIOCM_CTS) | |
225 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
226 | ||
ebd2c8f6 | 227 | wake_up_interruptible(&sport->port.state->delta_msr_wait); |
1da177e4 LT |
228 | } |
229 | ||
230 | /* | |
231 | * This is our per-port timeout handler, for checking the | |
232 | * modem status signals. | |
233 | */ | |
234 | static void imx_timeout(unsigned long data) | |
235 | { | |
236 | struct imx_port *sport = (struct imx_port *)data; | |
237 | unsigned long flags; | |
238 | ||
ebd2c8f6 | 239 | if (sport->port.state) { |
1da177e4 LT |
240 | spin_lock_irqsave(&sport->port.lock, flags); |
241 | imx_mctrl_check(sport); | |
242 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
243 | ||
244 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
245 | } | |
246 | } | |
247 | ||
248 | /* | |
249 | * interrupts disabled on entry | |
250 | */ | |
b129a8cc | 251 | static void imx_stop_tx(struct uart_port *port) |
1da177e4 LT |
252 | { |
253 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
254 | unsigned long temp; |
255 | ||
b6e49138 FG |
256 | if (USE_IRDA(sport)) { |
257 | /* half duplex - wait for end of transmission */ | |
258 | int n = 256; | |
259 | while ((--n > 0) && | |
260 | !(readl(sport->port.membase + USR2) & USR2_TXDC)) { | |
261 | udelay(5); | |
262 | barrier(); | |
263 | } | |
264 | /* | |
265 | * irda transceiver - wait a bit more to avoid | |
266 | * cutoff, hardware dependent | |
267 | */ | |
268 | udelay(sport->trcv_delay); | |
269 | ||
270 | /* | |
271 | * half duplex - reactivate receive mode, | |
272 | * flush receive pipe echo crap | |
273 | */ | |
274 | if (readl(sport->port.membase + USR2) & USR2_TXDC) { | |
275 | temp = readl(sport->port.membase + UCR1); | |
276 | temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); | |
277 | writel(temp, sport->port.membase + UCR1); | |
278 | ||
279 | temp = readl(sport->port.membase + UCR4); | |
280 | temp &= ~(UCR4_TCEN); | |
281 | writel(temp, sport->port.membase + UCR4); | |
282 | ||
283 | while (readl(sport->port.membase + URXD0) & | |
284 | URXD_CHARRDY) | |
285 | barrier(); | |
286 | ||
287 | temp = readl(sport->port.membase + UCR1); | |
288 | temp |= UCR1_RRDYEN; | |
289 | writel(temp, sport->port.membase + UCR1); | |
290 | ||
291 | temp = readl(sport->port.membase + UCR4); | |
292 | temp |= UCR4_DREN; | |
293 | writel(temp, sport->port.membase + UCR4); | |
294 | } | |
295 | return; | |
296 | } | |
297 | ||
ff4bfb21 SH |
298 | temp = readl(sport->port.membase + UCR1); |
299 | writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 LT |
300 | } |
301 | ||
302 | /* | |
303 | * interrupts disabled on entry | |
304 | */ | |
305 | static void imx_stop_rx(struct uart_port *port) | |
306 | { | |
307 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
308 | unsigned long temp; |
309 | ||
310 | temp = readl(sport->port.membase + UCR2); | |
311 | writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); | |
1da177e4 LT |
312 | } |
313 | ||
314 | /* | |
315 | * Set the modem control timer to fire immediately. | |
316 | */ | |
317 | static void imx_enable_ms(struct uart_port *port) | |
318 | { | |
319 | struct imx_port *sport = (struct imx_port *)port; | |
320 | ||
321 | mod_timer(&sport->timer, jiffies); | |
322 | } | |
323 | ||
324 | static inline void imx_transmit_buffer(struct imx_port *sport) | |
325 | { | |
ebd2c8f6 | 326 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 | 327 | |
ff4bfb21 | 328 | while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) { |
1da177e4 LT |
329 | /* send xmit->buf[xmit->tail] |
330 | * out the port here */ | |
ff4bfb21 | 331 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); |
d3810cd4 | 332 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1da177e4 LT |
333 | sport->port.icount.tx++; |
334 | if (uart_circ_empty(xmit)) | |
335 | break; | |
8c0b254b | 336 | } |
1da177e4 | 337 | |
97775731 FG |
338 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
339 | uart_write_wakeup(&sport->port); | |
340 | ||
1da177e4 | 341 | if (uart_circ_empty(xmit)) |
b129a8cc | 342 | imx_stop_tx(&sport->port); |
1da177e4 LT |
343 | } |
344 | ||
345 | /* | |
346 | * interrupts disabled on entry | |
347 | */ | |
b129a8cc | 348 | static void imx_start_tx(struct uart_port *port) |
1da177e4 LT |
349 | { |
350 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 351 | unsigned long temp; |
1da177e4 | 352 | |
b6e49138 FG |
353 | if (USE_IRDA(sport)) { |
354 | /* half duplex in IrDA mode; have to disable receive mode */ | |
355 | temp = readl(sport->port.membase + UCR4); | |
356 | temp &= ~(UCR4_DREN); | |
357 | writel(temp, sport->port.membase + UCR4); | |
358 | ||
359 | temp = readl(sport->port.membase + UCR1); | |
360 | temp &= ~(UCR1_RRDYEN); | |
361 | writel(temp, sport->port.membase + UCR1); | |
362 | } | |
363 | ||
ff4bfb21 SH |
364 | temp = readl(sport->port.membase + UCR1); |
365 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 | 366 | |
b6e49138 FG |
367 | if (USE_IRDA(sport)) { |
368 | temp = readl(sport->port.membase + UCR1); | |
369 | temp |= UCR1_TRDYEN; | |
370 | writel(temp, sport->port.membase + UCR1); | |
371 | ||
372 | temp = readl(sport->port.membase + UCR4); | |
373 | temp |= UCR4_TCEN; | |
374 | writel(temp, sport->port.membase + UCR4); | |
375 | } | |
376 | ||
ff4bfb21 SH |
377 | if (readl(sport->port.membase + UTS) & UTS_TXEMPTY) |
378 | imx_transmit_buffer(sport); | |
1da177e4 LT |
379 | } |
380 | ||
7d12e780 | 381 | static irqreturn_t imx_rtsint(int irq, void *dev_id) |
ceca629e | 382 | { |
15aafa2f | 383 | struct imx_port *sport = dev_id; |
ff4bfb21 | 384 | unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS; |
ceca629e SH |
385 | unsigned long flags; |
386 | ||
387 | spin_lock_irqsave(&sport->port.lock, flags); | |
388 | ||
ff4bfb21 | 389 | writel(USR1_RTSD, sport->port.membase + USR1); |
ceca629e | 390 | uart_handle_cts_change(&sport->port, !!val); |
ebd2c8f6 | 391 | wake_up_interruptible(&sport->port.state->delta_msr_wait); |
ceca629e SH |
392 | |
393 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
394 | return IRQ_HANDLED; | |
395 | } | |
396 | ||
7d12e780 | 397 | static irqreturn_t imx_txint(int irq, void *dev_id) |
1da177e4 | 398 | { |
15aafa2f | 399 | struct imx_port *sport = dev_id; |
ebd2c8f6 | 400 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 LT |
401 | unsigned long flags; |
402 | ||
403 | spin_lock_irqsave(&sport->port.lock,flags); | |
404 | if (sport->port.x_char) | |
405 | { | |
406 | /* Send next char */ | |
ff4bfb21 | 407 | writel(sport->port.x_char, sport->port.membase + URTX0); |
1da177e4 LT |
408 | goto out; |
409 | } | |
410 | ||
411 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 412 | imx_stop_tx(&sport->port); |
1da177e4 LT |
413 | goto out; |
414 | } | |
415 | ||
416 | imx_transmit_buffer(sport); | |
417 | ||
418 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
419 | uart_write_wakeup(&sport->port); | |
420 | ||
421 | out: | |
422 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
423 | return IRQ_HANDLED; | |
424 | } | |
425 | ||
7d12e780 | 426 | static irqreturn_t imx_rxint(int irq, void *dev_id) |
1da177e4 LT |
427 | { |
428 | struct imx_port *sport = dev_id; | |
429 | unsigned int rx,flg,ignored = 0; | |
ebd2c8f6 | 430 | struct tty_struct *tty = sport->port.state->port.tty; |
ff4bfb21 | 431 | unsigned long flags, temp; |
1da177e4 | 432 | |
1da177e4 LT |
433 | spin_lock_irqsave(&sport->port.lock,flags); |
434 | ||
0d3c3938 | 435 | while (readl(sport->port.membase + USR2) & USR2_RDR) { |
1da177e4 LT |
436 | flg = TTY_NORMAL; |
437 | sport->port.icount.rx++; | |
438 | ||
0d3c3938 SH |
439 | rx = readl(sport->port.membase + URXD0); |
440 | ||
ff4bfb21 | 441 | temp = readl(sport->port.membase + USR2); |
864eeed0 | 442 | if (temp & USR2_BRCD) { |
ff4bfb21 | 443 | writel(temp | USR2_BRCD, sport->port.membase + USR2); |
864eeed0 SH |
444 | if (uart_handle_break(&sport->port)) |
445 | continue; | |
1da177e4 LT |
446 | } |
447 | ||
d3810cd4 | 448 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) |
864eeed0 SH |
449 | continue; |
450 | ||
451 | if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { | |
452 | if (rx & URXD_PRERR) | |
453 | sport->port.icount.parity++; | |
454 | else if (rx & URXD_FRMERR) | |
455 | sport->port.icount.frame++; | |
456 | if (rx & URXD_OVRRUN) | |
457 | sport->port.icount.overrun++; | |
458 | ||
459 | if (rx & sport->port.ignore_status_mask) { | |
460 | if (++ignored > 100) | |
461 | goto out; | |
462 | continue; | |
463 | } | |
464 | ||
465 | rx &= sport->port.read_status_mask; | |
466 | ||
467 | if (rx & URXD_PRERR) | |
468 | flg = TTY_PARITY; | |
469 | else if (rx & URXD_FRMERR) | |
470 | flg = TTY_FRAME; | |
471 | if (rx & URXD_OVRRUN) | |
472 | flg = TTY_OVERRUN; | |
1da177e4 | 473 | |
864eeed0 SH |
474 | #ifdef SUPPORT_SYSRQ |
475 | sport->port.sysrq = 0; | |
476 | #endif | |
477 | } | |
1da177e4 | 478 | |
1da177e4 | 479 | tty_insert_flip_char(tty, rx, flg); |
864eeed0 | 480 | } |
1da177e4 LT |
481 | |
482 | out: | |
483 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
484 | tty_flip_buffer_push(tty); | |
485 | return IRQ_HANDLED; | |
1da177e4 LT |
486 | } |
487 | ||
e3d13ff4 SH |
488 | static irqreturn_t imx_int(int irq, void *dev_id) |
489 | { | |
490 | struct imx_port *sport = dev_id; | |
491 | unsigned int sts; | |
492 | ||
493 | sts = readl(sport->port.membase + USR1); | |
494 | ||
495 | if (sts & USR1_RRDY) | |
496 | imx_rxint(irq, dev_id); | |
497 | ||
498 | if (sts & USR1_TRDY && | |
499 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | |
500 | imx_txint(irq, dev_id); | |
501 | ||
9fbe6044 | 502 | if (sts & USR1_RTSD) |
e3d13ff4 SH |
503 | imx_rtsint(irq, dev_id); |
504 | ||
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
1da177e4 LT |
508 | /* |
509 | * Return TIOCSER_TEMT when transmitter is not busy. | |
510 | */ | |
511 | static unsigned int imx_tx_empty(struct uart_port *port) | |
512 | { | |
513 | struct imx_port *sport = (struct imx_port *)port; | |
514 | ||
ff4bfb21 | 515 | return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
516 | } |
517 | ||
0f302dc3 SH |
518 | /* |
519 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. | |
520 | */ | |
1da177e4 LT |
521 | static unsigned int imx_get_mctrl(struct uart_port *port) |
522 | { | |
d3810cd4 OS |
523 | struct imx_port *sport = (struct imx_port *)port; |
524 | unsigned int tmp = TIOCM_DSR | TIOCM_CAR; | |
0f302dc3 | 525 | |
d3810cd4 OS |
526 | if (readl(sport->port.membase + USR1) & USR1_RTSS) |
527 | tmp |= TIOCM_CTS; | |
0f302dc3 | 528 | |
d3810cd4 OS |
529 | if (readl(sport->port.membase + UCR2) & UCR2_CTS) |
530 | tmp |= TIOCM_RTS; | |
0f302dc3 | 531 | |
d3810cd4 | 532 | return tmp; |
1da177e4 LT |
533 | } |
534 | ||
535 | static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
536 | { | |
d3810cd4 | 537 | struct imx_port *sport = (struct imx_port *)port; |
ff4bfb21 SH |
538 | unsigned long temp; |
539 | ||
540 | temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; | |
0f302dc3 | 541 | |
d3810cd4 | 542 | if (mctrl & TIOCM_RTS) |
ff4bfb21 SH |
543 | temp |= UCR2_CTS; |
544 | ||
545 | writel(temp, sport->port.membase + UCR2); | |
1da177e4 LT |
546 | } |
547 | ||
548 | /* | |
549 | * Interrupts always disabled. | |
550 | */ | |
551 | static void imx_break_ctl(struct uart_port *port, int break_state) | |
552 | { | |
553 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 554 | unsigned long flags, temp; |
1da177e4 LT |
555 | |
556 | spin_lock_irqsave(&sport->port.lock, flags); | |
557 | ||
ff4bfb21 SH |
558 | temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; |
559 | ||
1da177e4 | 560 | if ( break_state != 0 ) |
ff4bfb21 SH |
561 | temp |= UCR1_SNDBRK; |
562 | ||
563 | writel(temp, sport->port.membase + UCR1); | |
1da177e4 LT |
564 | |
565 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
566 | } | |
567 | ||
568 | #define TXTL 2 /* reset default */ | |
569 | #define RXTL 1 /* reset default */ | |
570 | ||
587897f5 SH |
571 | static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) |
572 | { | |
573 | unsigned int val; | |
574 | unsigned int ufcr_rfdiv; | |
575 | ||
576 | /* set receiver / transmitter trigger level. | |
577 | * RFDIV is set such way to satisfy requested uartclk value | |
578 | */ | |
ff4bfb21 | 579 | val = TXTL << 10 | RXTL; |
38a41fdf SH |
580 | ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) |
581 | / sport->port.uartclk; | |
587897f5 SH |
582 | |
583 | if(!ufcr_rfdiv) | |
584 | ufcr_rfdiv = 1; | |
585 | ||
b6e49138 | 586 | val |= UFCR_RFDIV_REG(ufcr_rfdiv); |
587897f5 | 587 | |
ff4bfb21 | 588 | writel(val, sport->port.membase + UFCR); |
587897f5 SH |
589 | |
590 | return 0; | |
591 | } | |
592 | ||
1da177e4 LT |
593 | static int imx_startup(struct uart_port *port) |
594 | { | |
595 | struct imx_port *sport = (struct imx_port *)port; | |
596 | int retval; | |
ff4bfb21 | 597 | unsigned long flags, temp; |
1da177e4 | 598 | |
587897f5 | 599 | imx_setup_ufcr(sport, 0); |
1da177e4 LT |
600 | |
601 | /* disable the DREN bit (Data Ready interrupt enable) before | |
602 | * requesting IRQs | |
603 | */ | |
ff4bfb21 | 604 | temp = readl(sport->port.membase + UCR4); |
b6e49138 FG |
605 | |
606 | if (USE_IRDA(sport)) | |
607 | temp |= UCR4_IRSC; | |
608 | ||
ff4bfb21 | 609 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
1da177e4 | 610 | |
b6e49138 FG |
611 | if (USE_IRDA(sport)) { |
612 | /* reset fifo's and state machines */ | |
613 | int i = 100; | |
614 | temp = readl(sport->port.membase + UCR2); | |
615 | temp &= ~UCR2_SRST; | |
616 | writel(temp, sport->port.membase + UCR2); | |
617 | while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && | |
618 | (--i > 0)) { | |
619 | udelay(1); | |
620 | } | |
621 | } | |
622 | ||
1da177e4 | 623 | /* |
e3d13ff4 SH |
624 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
625 | * chips only have one interrupt. | |
1da177e4 | 626 | */ |
e3d13ff4 SH |
627 | if (sport->txirq > 0) { |
628 | retval = request_irq(sport->rxirq, imx_rxint, 0, | |
629 | DRIVER_NAME, sport); | |
630 | if (retval) | |
631 | goto error_out1; | |
632 | ||
633 | retval = request_irq(sport->txirq, imx_txint, 0, | |
634 | DRIVER_NAME, sport); | |
635 | if (retval) | |
636 | goto error_out2; | |
637 | ||
b6e49138 FG |
638 | /* do not use RTS IRQ on IrDA */ |
639 | if (!USE_IRDA(sport)) { | |
640 | retval = request_irq(sport->rtsirq, imx_rtsint, | |
641 | (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : | |
642 | IRQF_TRIGGER_FALLING | | |
643 | IRQF_TRIGGER_RISING, | |
644 | DRIVER_NAME, sport); | |
645 | if (retval) | |
646 | goto error_out3; | |
647 | } | |
e3d13ff4 SH |
648 | } else { |
649 | retval = request_irq(sport->port.irq, imx_int, 0, | |
650 | DRIVER_NAME, sport); | |
651 | if (retval) { | |
652 | free_irq(sport->port.irq, sport); | |
653 | goto error_out1; | |
654 | } | |
655 | } | |
ceca629e | 656 | |
1da177e4 LT |
657 | /* |
658 | * Finally, clear and enable interrupts | |
659 | */ | |
ff4bfb21 SH |
660 | writel(USR1_RTSD, sport->port.membase + USR1); |
661 | ||
662 | temp = readl(sport->port.membase + UCR1); | |
789d5258 | 663 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
b6e49138 FG |
664 | |
665 | if (USE_IRDA(sport)) { | |
666 | temp |= UCR1_IREN; | |
667 | temp &= ~(UCR1_RTSDEN); | |
668 | } | |
669 | ||
ff4bfb21 | 670 | writel(temp, sport->port.membase + UCR1); |
1da177e4 | 671 | |
ff4bfb21 SH |
672 | temp = readl(sport->port.membase + UCR2); |
673 | temp |= (UCR2_RXEN | UCR2_TXEN); | |
674 | writel(temp, sport->port.membase + UCR2); | |
1da177e4 | 675 | |
b6e49138 FG |
676 | if (USE_IRDA(sport)) { |
677 | /* clear RX-FIFO */ | |
678 | int i = 64; | |
679 | while ((--i > 0) && | |
680 | (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { | |
681 | barrier(); | |
682 | } | |
683 | } | |
684 | ||
37d6fb62 SH |
685 | if (!cpu_is_mx1()) { |
686 | temp = readl(sport->port.membase + UCR3); | |
687 | temp |= MX2_UCR3_RXDMUXSEL; | |
688 | writel(temp, sport->port.membase + UCR3); | |
689 | } | |
4411805b | 690 | |
b6e49138 FG |
691 | if (USE_IRDA(sport)) { |
692 | temp = readl(sport->port.membase + UCR4); | |
693 | if (sport->irda_inv_rx) | |
694 | temp |= UCR4_INVR; | |
695 | else | |
696 | temp &= ~(UCR4_INVR); | |
697 | writel(temp | UCR4_DREN, sport->port.membase + UCR4); | |
698 | ||
699 | temp = readl(sport->port.membase + UCR3); | |
700 | if (sport->irda_inv_tx) | |
701 | temp |= UCR3_INVT; | |
702 | else | |
703 | temp &= ~(UCR3_INVT); | |
704 | writel(temp, sport->port.membase + UCR3); | |
705 | } | |
706 | ||
1da177e4 LT |
707 | /* |
708 | * Enable modem status interrupts | |
709 | */ | |
710 | spin_lock_irqsave(&sport->port.lock,flags); | |
711 | imx_enable_ms(&sport->port); | |
712 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
713 | ||
b6e49138 FG |
714 | if (USE_IRDA(sport)) { |
715 | struct imxuart_platform_data *pdata; | |
716 | pdata = sport->port.dev->platform_data; | |
717 | sport->irda_inv_rx = pdata->irda_inv_rx; | |
718 | sport->irda_inv_tx = pdata->irda_inv_tx; | |
719 | sport->trcv_delay = pdata->transceiver_delay; | |
720 | if (pdata->irda_enable) | |
721 | pdata->irda_enable(1); | |
722 | } | |
723 | ||
1da177e4 LT |
724 | return 0; |
725 | ||
ceca629e | 726 | error_out3: |
e3d13ff4 SH |
727 | if (sport->txirq) |
728 | free_irq(sport->txirq, sport); | |
1da177e4 | 729 | error_out2: |
e3d13ff4 SH |
730 | if (sport->rxirq) |
731 | free_irq(sport->rxirq, sport); | |
86371d07 | 732 | error_out1: |
1da177e4 LT |
733 | return retval; |
734 | } | |
735 | ||
736 | static void imx_shutdown(struct uart_port *port) | |
737 | { | |
738 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 739 | unsigned long temp; |
1da177e4 | 740 | |
2e146392 FG |
741 | temp = readl(sport->port.membase + UCR2); |
742 | temp &= ~(UCR2_TXEN); | |
743 | writel(temp, sport->port.membase + UCR2); | |
744 | ||
b6e49138 FG |
745 | if (USE_IRDA(sport)) { |
746 | struct imxuart_platform_data *pdata; | |
747 | pdata = sport->port.dev->platform_data; | |
748 | if (pdata->irda_enable) | |
749 | pdata->irda_enable(0); | |
750 | } | |
751 | ||
1da177e4 LT |
752 | /* |
753 | * Stop our timer. | |
754 | */ | |
755 | del_timer_sync(&sport->timer); | |
756 | ||
757 | /* | |
758 | * Free the interrupts | |
759 | */ | |
e3d13ff4 | 760 | if (sport->txirq > 0) { |
b6e49138 FG |
761 | if (!USE_IRDA(sport)) |
762 | free_irq(sport->rtsirq, sport); | |
e3d13ff4 SH |
763 | free_irq(sport->txirq, sport); |
764 | free_irq(sport->rxirq, sport); | |
765 | } else | |
766 | free_irq(sport->port.irq, sport); | |
1da177e4 LT |
767 | |
768 | /* | |
769 | * Disable all interrupts, port and break condition. | |
770 | */ | |
771 | ||
ff4bfb21 SH |
772 | temp = readl(sport->port.membase + UCR1); |
773 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | |
b6e49138 FG |
774 | if (USE_IRDA(sport)) |
775 | temp &= ~(UCR1_IREN); | |
776 | ||
ff4bfb21 | 777 | writel(temp, sport->port.membase + UCR1); |
1da177e4 LT |
778 | } |
779 | ||
780 | static void | |
606d099c AC |
781 | imx_set_termios(struct uart_port *port, struct ktermios *termios, |
782 | struct ktermios *old) | |
1da177e4 LT |
783 | { |
784 | struct imx_port *sport = (struct imx_port *)port; | |
785 | unsigned long flags; | |
786 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | |
787 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
534fca06 OS |
788 | unsigned int div, ufcr; |
789 | unsigned long num, denom; | |
d7f8d437 | 790 | uint64_t tdiv64; |
1da177e4 LT |
791 | |
792 | /* | |
793 | * If we don't support modem control lines, don't allow | |
794 | * these to be set. | |
795 | */ | |
796 | if (0) { | |
797 | termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); | |
798 | termios->c_cflag |= CLOCAL; | |
799 | } | |
800 | ||
801 | /* | |
802 | * We only support CS7 and CS8. | |
803 | */ | |
804 | while ((termios->c_cflag & CSIZE) != CS7 && | |
805 | (termios->c_cflag & CSIZE) != CS8) { | |
806 | termios->c_cflag &= ~CSIZE; | |
807 | termios->c_cflag |= old_csize; | |
808 | old_csize = CS8; | |
809 | } | |
810 | ||
811 | if ((termios->c_cflag & CSIZE) == CS8) | |
812 | ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; | |
813 | else | |
814 | ucr2 = UCR2_SRST | UCR2_IRTS; | |
815 | ||
816 | if (termios->c_cflag & CRTSCTS) { | |
5b802344 SH |
817 | if( sport->have_rtscts ) { |
818 | ucr2 &= ~UCR2_IRTS; | |
819 | ucr2 |= UCR2_CTSC; | |
820 | } else { | |
821 | termios->c_cflag &= ~CRTSCTS; | |
822 | } | |
1da177e4 LT |
823 | } |
824 | ||
825 | if (termios->c_cflag & CSTOPB) | |
826 | ucr2 |= UCR2_STPB; | |
827 | if (termios->c_cflag & PARENB) { | |
828 | ucr2 |= UCR2_PREN; | |
3261e362 | 829 | if (termios->c_cflag & PARODD) |
1da177e4 LT |
830 | ucr2 |= UCR2_PROE; |
831 | } | |
832 | ||
833 | /* | |
834 | * Ask the core to calculate the divisor for us. | |
835 | */ | |
036bb15e | 836 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); |
1da177e4 LT |
837 | quot = uart_get_divisor(port, baud); |
838 | ||
839 | spin_lock_irqsave(&sport->port.lock, flags); | |
840 | ||
841 | sport->port.read_status_mask = 0; | |
842 | if (termios->c_iflag & INPCK) | |
843 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); | |
844 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
845 | sport->port.read_status_mask |= URXD_BRK; | |
846 | ||
847 | /* | |
848 | * Characters to ignore | |
849 | */ | |
850 | sport->port.ignore_status_mask = 0; | |
851 | if (termios->c_iflag & IGNPAR) | |
852 | sport->port.ignore_status_mask |= URXD_PRERR; | |
853 | if (termios->c_iflag & IGNBRK) { | |
854 | sport->port.ignore_status_mask |= URXD_BRK; | |
855 | /* | |
856 | * If we're ignoring parity and break indicators, | |
857 | * ignore overruns too (for real raw support). | |
858 | */ | |
859 | if (termios->c_iflag & IGNPAR) | |
860 | sport->port.ignore_status_mask |= URXD_OVRRUN; | |
861 | } | |
862 | ||
863 | del_timer_sync(&sport->timer); | |
864 | ||
865 | /* | |
866 | * Update the per-port timeout. | |
867 | */ | |
868 | uart_update_timeout(port, termios->c_cflag, baud); | |
869 | ||
870 | /* | |
871 | * disable interrupts and drain transmitter | |
872 | */ | |
ff4bfb21 SH |
873 | old_ucr1 = readl(sport->port.membase + UCR1); |
874 | writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), | |
875 | sport->port.membase + UCR1); | |
1da177e4 | 876 | |
ff4bfb21 | 877 | while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) |
1da177e4 LT |
878 | barrier(); |
879 | ||
880 | /* then, disable everything */ | |
ff4bfb21 SH |
881 | old_txrxen = readl(sport->port.membase + UCR2); |
882 | writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), | |
883 | sport->port.membase + UCR2); | |
884 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | |
1da177e4 | 885 | |
b6e49138 FG |
886 | if (USE_IRDA(sport)) { |
887 | /* | |
888 | * use maximum available submodule frequency to | |
889 | * avoid missing short pulses due to low sampling rate | |
890 | */ | |
036bb15e | 891 | div = 1; |
b6e49138 FG |
892 | } else { |
893 | div = sport->port.uartclk / (baud * 16); | |
894 | if (div > 7) | |
895 | div = 7; | |
896 | if (!div) | |
897 | div = 1; | |
898 | } | |
036bb15e | 899 | |
534fca06 OS |
900 | rational_best_approximation(16 * div * baud, sport->port.uartclk, |
901 | 1 << 16, 1 << 16, &num, &denom); | |
036bb15e | 902 | |
ebd2c8f6 | 903 | if (port->state && port->state->port.tty) { |
1a2c4b31 SH |
904 | tdiv64 = sport->port.uartclk; |
905 | tdiv64 *= num; | |
906 | do_div(tdiv64, denom * 16 * div); | |
ebd2c8f6 | 907 | tty_encode_baud_rate(sport->port.state->port.tty, |
1a2c4b31 SH |
908 | (speed_t)tdiv64, (speed_t)tdiv64); |
909 | } | |
d7f8d437 | 910 | |
534fca06 OS |
911 | num -= 1; |
912 | denom -= 1; | |
036bb15e SH |
913 | |
914 | ufcr = readl(sport->port.membase + UFCR); | |
b6e49138 | 915 | ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); |
036bb15e SH |
916 | writel(ufcr, sport->port.membase + UFCR); |
917 | ||
534fca06 OS |
918 | writel(num, sport->port.membase + UBIR); |
919 | writel(denom, sport->port.membase + UBMR); | |
920 | ||
37d6fb62 SH |
921 | if (!cpu_is_mx1()) |
922 | writel(sport->port.uartclk / div / 1000, | |
923 | sport->port.membase + MX2_ONEMS); | |
ff4bfb21 SH |
924 | |
925 | writel(old_ucr1, sport->port.membase + UCR1); | |
1da177e4 | 926 | |
ff4bfb21 SH |
927 | /* set the parity, stop bits and data size */ |
928 | writel(ucr2 | old_txrxen, sport->port.membase + UCR2); | |
1da177e4 LT |
929 | |
930 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
931 | imx_enable_ms(&sport->port); | |
932 | ||
933 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
934 | } | |
935 | ||
936 | static const char *imx_type(struct uart_port *port) | |
937 | { | |
938 | struct imx_port *sport = (struct imx_port *)port; | |
939 | ||
940 | return sport->port.type == PORT_IMX ? "IMX" : NULL; | |
941 | } | |
942 | ||
943 | /* | |
944 | * Release the memory region(s) being used by 'port'. | |
945 | */ | |
946 | static void imx_release_port(struct uart_port *port) | |
947 | { | |
3d454446 SH |
948 | struct platform_device *pdev = to_platform_device(port->dev); |
949 | struct resource *mmres; | |
1da177e4 | 950 | |
3d454446 SH |
951 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
952 | release_mem_region(mmres->start, mmres->end - mmres->start + 1); | |
1da177e4 LT |
953 | } |
954 | ||
955 | /* | |
956 | * Request the memory region(s) being used by 'port'. | |
957 | */ | |
958 | static int imx_request_port(struct uart_port *port) | |
959 | { | |
3d454446 SH |
960 | struct platform_device *pdev = to_platform_device(port->dev); |
961 | struct resource *mmres; | |
962 | void *ret; | |
963 | ||
964 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
965 | if (!mmres) | |
966 | return -ENODEV; | |
967 | ||
968 | ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, | |
969 | "imx-uart"); | |
1da177e4 | 970 | |
3d454446 | 971 | return ret ? 0 : -EBUSY; |
1da177e4 LT |
972 | } |
973 | ||
974 | /* | |
975 | * Configure/autoconfigure the port. | |
976 | */ | |
977 | static void imx_config_port(struct uart_port *port, int flags) | |
978 | { | |
979 | struct imx_port *sport = (struct imx_port *)port; | |
980 | ||
981 | if (flags & UART_CONFIG_TYPE && | |
982 | imx_request_port(&sport->port) == 0) | |
983 | sport->port.type = PORT_IMX; | |
984 | } | |
985 | ||
986 | /* | |
987 | * Verify the new serial_struct (for TIOCSSERIAL). | |
988 | * The only change we allow are to the flags and type, and | |
989 | * even then only between PORT_IMX and PORT_UNKNOWN | |
990 | */ | |
991 | static int | |
992 | imx_verify_port(struct uart_port *port, struct serial_struct *ser) | |
993 | { | |
994 | struct imx_port *sport = (struct imx_port *)port; | |
995 | int ret = 0; | |
996 | ||
997 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) | |
998 | ret = -EINVAL; | |
999 | if (sport->port.irq != ser->irq) | |
1000 | ret = -EINVAL; | |
1001 | if (ser->io_type != UPIO_MEM) | |
1002 | ret = -EINVAL; | |
1003 | if (sport->port.uartclk / 16 != ser->baud_base) | |
1004 | ret = -EINVAL; | |
1005 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
1006 | ret = -EINVAL; | |
1007 | if (sport->port.iobase != ser->port) | |
1008 | ret = -EINVAL; | |
1009 | if (ser->hub6 != 0) | |
1010 | ret = -EINVAL; | |
1011 | return ret; | |
1012 | } | |
1013 | ||
1014 | static struct uart_ops imx_pops = { | |
1015 | .tx_empty = imx_tx_empty, | |
1016 | .set_mctrl = imx_set_mctrl, | |
1017 | .get_mctrl = imx_get_mctrl, | |
1018 | .stop_tx = imx_stop_tx, | |
1019 | .start_tx = imx_start_tx, | |
1020 | .stop_rx = imx_stop_rx, | |
1021 | .enable_ms = imx_enable_ms, | |
1022 | .break_ctl = imx_break_ctl, | |
1023 | .startup = imx_startup, | |
1024 | .shutdown = imx_shutdown, | |
1025 | .set_termios = imx_set_termios, | |
1026 | .type = imx_type, | |
1027 | .release_port = imx_release_port, | |
1028 | .request_port = imx_request_port, | |
1029 | .config_port = imx_config_port, | |
1030 | .verify_port = imx_verify_port, | |
1031 | }; | |
1032 | ||
dbff4e9e | 1033 | static struct imx_port *imx_ports[UART_NR]; |
1da177e4 LT |
1034 | |
1035 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | |
d358788f RK |
1036 | static void imx_console_putchar(struct uart_port *port, int ch) |
1037 | { | |
1038 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
1039 | |
1040 | while (readl(sport->port.membase + UTS) & UTS_TXFULL) | |
d358788f | 1041 | barrier(); |
ff4bfb21 SH |
1042 | |
1043 | writel(ch, sport->port.membase + URTX0); | |
d358788f | 1044 | } |
1da177e4 LT |
1045 | |
1046 | /* | |
1047 | * Interrupts are disabled on entering | |
1048 | */ | |
1049 | static void | |
1050 | imx_console_write(struct console *co, const char *s, unsigned int count) | |
1051 | { | |
dbff4e9e | 1052 | struct imx_port *sport = imx_ports[co->index]; |
37d6fb62 | 1053 | unsigned int old_ucr1, old_ucr2, ucr1; |
1da177e4 LT |
1054 | |
1055 | /* | |
1056 | * First, save UCR1/2 and then disable interrupts | |
1057 | */ | |
37d6fb62 | 1058 | ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); |
ff4bfb21 | 1059 | old_ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 | 1060 | |
37d6fb62 SH |
1061 | if (cpu_is_mx1()) |
1062 | ucr1 |= MX1_UCR1_UARTCLKEN; | |
1063 | ucr1 |= UCR1_UARTEN; | |
1064 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); | |
1065 | ||
1066 | writel(ucr1, sport->port.membase + UCR1); | |
ff4bfb21 SH |
1067 | |
1068 | writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); | |
1da177e4 | 1069 | |
d358788f | 1070 | uart_console_write(&sport->port, s, count, imx_console_putchar); |
1da177e4 LT |
1071 | |
1072 | /* | |
1073 | * Finally, wait for transmitter to become empty | |
1074 | * and restore UCR1/2 | |
1075 | */ | |
ff4bfb21 | 1076 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); |
1da177e4 | 1077 | |
ff4bfb21 SH |
1078 | writel(old_ucr1, sport->port.membase + UCR1); |
1079 | writel(old_ucr2, sport->port.membase + UCR2); | |
1da177e4 LT |
1080 | } |
1081 | ||
1082 | /* | |
1083 | * If the port was already initialised (eg, by a boot loader), | |
1084 | * try to determine the current setup. | |
1085 | */ | |
1086 | static void __init | |
1087 | imx_console_get_options(struct imx_port *sport, int *baud, | |
1088 | int *parity, int *bits) | |
1089 | { | |
587897f5 | 1090 | |
ff4bfb21 | 1091 | if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) { |
1da177e4 LT |
1092 | /* ok, the port was enabled */ |
1093 | unsigned int ucr2, ubir,ubmr, uartclk; | |
587897f5 SH |
1094 | unsigned int baud_raw; |
1095 | unsigned int ucfr_rfdiv; | |
1da177e4 | 1096 | |
ff4bfb21 | 1097 | ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 LT |
1098 | |
1099 | *parity = 'n'; | |
1100 | if (ucr2 & UCR2_PREN) { | |
1101 | if (ucr2 & UCR2_PROE) | |
1102 | *parity = 'o'; | |
1103 | else | |
1104 | *parity = 'e'; | |
1105 | } | |
1106 | ||
1107 | if (ucr2 & UCR2_WS) | |
1108 | *bits = 8; | |
1109 | else | |
1110 | *bits = 7; | |
1111 | ||
ff4bfb21 SH |
1112 | ubir = readl(sport->port.membase + UBIR) & 0xffff; |
1113 | ubmr = readl(sport->port.membase + UBMR) & 0xffff; | |
587897f5 | 1114 | |
ff4bfb21 | 1115 | ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; |
587897f5 SH |
1116 | if (ucfr_rfdiv == 6) |
1117 | ucfr_rfdiv = 7; | |
1118 | else | |
1119 | ucfr_rfdiv = 6 - ucfr_rfdiv; | |
1120 | ||
38a41fdf | 1121 | uartclk = clk_get_rate(sport->clk); |
587897f5 SH |
1122 | uartclk /= ucfr_rfdiv; |
1123 | ||
1124 | { /* | |
1125 | * The next code provides exact computation of | |
1126 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) | |
1127 | * without need of float support or long long division, | |
1128 | * which would be required to prevent 32bit arithmetic overflow | |
1129 | */ | |
1130 | unsigned int mul = ubir + 1; | |
1131 | unsigned int div = 16 * (ubmr + 1); | |
1132 | unsigned int rem = uartclk % div; | |
1133 | ||
1134 | baud_raw = (uartclk / div) * mul; | |
1135 | baud_raw += (rem * mul + div / 2) / div; | |
1136 | *baud = (baud_raw + 50) / 100 * 100; | |
1137 | } | |
1138 | ||
1139 | if(*baud != baud_raw) | |
1140 | printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", | |
1141 | baud_raw, *baud); | |
1da177e4 LT |
1142 | } |
1143 | } | |
1144 | ||
1145 | static int __init | |
1146 | imx_console_setup(struct console *co, char *options) | |
1147 | { | |
1148 | struct imx_port *sport; | |
1149 | int baud = 9600; | |
1150 | int bits = 8; | |
1151 | int parity = 'n'; | |
1152 | int flow = 'n'; | |
1153 | ||
1154 | /* | |
1155 | * Check whether an invalid uart number has been specified, and | |
1156 | * if so, search for the first available port that does have | |
1157 | * console support. | |
1158 | */ | |
1159 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | |
1160 | co->index = 0; | |
dbff4e9e | 1161 | sport = imx_ports[co->index]; |
e76afc4e EL |
1162 | if(sport == NULL) |
1163 | return -ENODEV; | |
1da177e4 LT |
1164 | |
1165 | if (options) | |
1166 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1167 | else | |
1168 | imx_console_get_options(sport, &baud, &parity, &bits); | |
1169 | ||
587897f5 SH |
1170 | imx_setup_ufcr(sport, 0); |
1171 | ||
1da177e4 LT |
1172 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); |
1173 | } | |
1174 | ||
9f4426dd | 1175 | static struct uart_driver imx_reg; |
1da177e4 | 1176 | static struct console imx_console = { |
e3d13ff4 | 1177 | .name = DEV_NAME, |
1da177e4 LT |
1178 | .write = imx_console_write, |
1179 | .device = uart_console_device, | |
1180 | .setup = imx_console_setup, | |
1181 | .flags = CON_PRINTBUFFER, | |
1182 | .index = -1, | |
1183 | .data = &imx_reg, | |
1184 | }; | |
1185 | ||
1da177e4 LT |
1186 | #define IMX_CONSOLE &imx_console |
1187 | #else | |
1188 | #define IMX_CONSOLE NULL | |
1189 | #endif | |
1190 | ||
1191 | static struct uart_driver imx_reg = { | |
1192 | .owner = THIS_MODULE, | |
1193 | .driver_name = DRIVER_NAME, | |
e3d13ff4 | 1194 | .dev_name = DEV_NAME, |
1da177e4 LT |
1195 | .major = SERIAL_IMX_MAJOR, |
1196 | .minor = MINOR_START, | |
1197 | .nr = ARRAY_SIZE(imx_ports), | |
1198 | .cons = IMX_CONSOLE, | |
1199 | }; | |
1200 | ||
3ae5eaec | 1201 | static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1202 | { |
d3810cd4 | 1203 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 1204 | |
d3810cd4 OS |
1205 | if (sport) |
1206 | uart_suspend_port(&imx_reg, &sport->port); | |
1da177e4 | 1207 | |
d3810cd4 | 1208 | return 0; |
1da177e4 LT |
1209 | } |
1210 | ||
3ae5eaec | 1211 | static int serial_imx_resume(struct platform_device *dev) |
1da177e4 | 1212 | { |
d3810cd4 | 1213 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 1214 | |
d3810cd4 OS |
1215 | if (sport) |
1216 | uart_resume_port(&imx_reg, &sport->port); | |
1da177e4 | 1217 | |
d3810cd4 | 1218 | return 0; |
1da177e4 LT |
1219 | } |
1220 | ||
2582d8c1 | 1221 | static int serial_imx_probe(struct platform_device *pdev) |
1da177e4 | 1222 | { |
dbff4e9e | 1223 | struct imx_port *sport; |
5b802344 | 1224 | struct imxuart_platform_data *pdata; |
dbff4e9e SH |
1225 | void __iomem *base; |
1226 | int ret = 0; | |
1227 | struct resource *res; | |
1228 | ||
1229 | sport = kzalloc(sizeof(*sport), GFP_KERNEL); | |
1230 | if (!sport) | |
1231 | return -ENOMEM; | |
5b802344 | 1232 | |
dbff4e9e SH |
1233 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1234 | if (!res) { | |
1235 | ret = -ENODEV; | |
1236 | goto free; | |
1237 | } | |
1238 | ||
1239 | base = ioremap(res->start, PAGE_SIZE); | |
1240 | if (!base) { | |
1241 | ret = -ENOMEM; | |
1242 | goto free; | |
1243 | } | |
1244 | ||
1245 | sport->port.dev = &pdev->dev; | |
1246 | sport->port.mapbase = res->start; | |
1247 | sport->port.membase = base; | |
1248 | sport->port.type = PORT_IMX, | |
1249 | sport->port.iotype = UPIO_MEM; | |
1250 | sport->port.irq = platform_get_irq(pdev, 0); | |
1251 | sport->rxirq = platform_get_irq(pdev, 0); | |
1252 | sport->txirq = platform_get_irq(pdev, 1); | |
1253 | sport->rtsirq = platform_get_irq(pdev, 2); | |
1254 | sport->port.fifosize = 32; | |
1255 | sport->port.ops = &imx_pops; | |
1256 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
1257 | sport->port.line = pdev->id; | |
1258 | init_timer(&sport->timer); | |
1259 | sport->timer.function = imx_timeout; | |
1260 | sport->timer.data = (unsigned long)sport; | |
38a41fdf | 1261 | |
e65fb009 | 1262 | sport->clk = clk_get(&pdev->dev, "uart"); |
38a41fdf SH |
1263 | if (IS_ERR(sport->clk)) { |
1264 | ret = PTR_ERR(sport->clk); | |
1265 | goto unmap; | |
1266 | } | |
1267 | clk_enable(sport->clk); | |
1268 | ||
1269 | sport->port.uartclk = clk_get_rate(sport->clk); | |
dbff4e9e SH |
1270 | |
1271 | imx_ports[pdev->id] = sport; | |
5b802344 | 1272 | |
2582d8c1 | 1273 | pdata = pdev->dev.platform_data; |
d3810cd4 | 1274 | if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) |
dbff4e9e | 1275 | sport->have_rtscts = 1; |
2582d8c1 | 1276 | |
b6e49138 FG |
1277 | #ifdef CONFIG_IRDA |
1278 | if (pdata && (pdata->flags & IMXUART_IRDA)) | |
1279 | sport->use_irda = 1; | |
1280 | #endif | |
1281 | ||
c45e7d7b DA |
1282 | if (pdata->init) { |
1283 | ret = pdata->init(pdev); | |
1284 | if (ret) | |
1285 | goto clkput; | |
1286 | } | |
2582d8c1 | 1287 | |
9f322ad0 DG |
1288 | ret = uart_add_one_port(&imx_reg, &sport->port); |
1289 | if (ret) | |
1290 | goto deinit; | |
dbff4e9e | 1291 | platform_set_drvdata(pdev, &sport->port); |
5b802344 | 1292 | |
1da177e4 | 1293 | return 0; |
9f322ad0 DG |
1294 | deinit: |
1295 | if (pdata->exit) | |
1296 | pdata->exit(pdev); | |
c45e7d7b DA |
1297 | clkput: |
1298 | clk_put(sport->clk); | |
1299 | clk_disable(sport->clk); | |
38a41fdf SH |
1300 | unmap: |
1301 | iounmap(sport->port.membase); | |
dbff4e9e SH |
1302 | free: |
1303 | kfree(sport); | |
1304 | ||
1305 | return ret; | |
1da177e4 LT |
1306 | } |
1307 | ||
2582d8c1 | 1308 | static int serial_imx_remove(struct platform_device *pdev) |
1da177e4 | 1309 | { |
2582d8c1 SH |
1310 | struct imxuart_platform_data *pdata; |
1311 | struct imx_port *sport = platform_get_drvdata(pdev); | |
1da177e4 | 1312 | |
2582d8c1 SH |
1313 | pdata = pdev->dev.platform_data; |
1314 | ||
1315 | platform_set_drvdata(pdev, NULL); | |
1da177e4 | 1316 | |
38a41fdf | 1317 | if (sport) { |
1da177e4 | 1318 | uart_remove_one_port(&imx_reg, &sport->port); |
38a41fdf SH |
1319 | clk_put(sport->clk); |
1320 | } | |
1321 | ||
1322 | clk_disable(sport->clk); | |
1da177e4 | 1323 | |
2582d8c1 SH |
1324 | if (pdata->exit) |
1325 | pdata->exit(pdev); | |
1326 | ||
dbff4e9e SH |
1327 | iounmap(sport->port.membase); |
1328 | kfree(sport); | |
1329 | ||
1da177e4 LT |
1330 | return 0; |
1331 | } | |
1332 | ||
3ae5eaec | 1333 | static struct platform_driver serial_imx_driver = { |
d3810cd4 OS |
1334 | .probe = serial_imx_probe, |
1335 | .remove = serial_imx_remove, | |
1da177e4 LT |
1336 | |
1337 | .suspend = serial_imx_suspend, | |
1338 | .resume = serial_imx_resume, | |
3ae5eaec | 1339 | .driver = { |
d3810cd4 | 1340 | .name = "imx-uart", |
e169c139 | 1341 | .owner = THIS_MODULE, |
3ae5eaec | 1342 | }, |
1da177e4 LT |
1343 | }; |
1344 | ||
1345 | static int __init imx_serial_init(void) | |
1346 | { | |
1347 | int ret; | |
1348 | ||
1349 | printk(KERN_INFO "Serial: IMX driver\n"); | |
1350 | ||
1da177e4 LT |
1351 | ret = uart_register_driver(&imx_reg); |
1352 | if (ret) | |
1353 | return ret; | |
1354 | ||
3ae5eaec | 1355 | ret = platform_driver_register(&serial_imx_driver); |
1da177e4 LT |
1356 | if (ret != 0) |
1357 | uart_unregister_driver(&imx_reg); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | static void __exit imx_serial_exit(void) | |
1363 | { | |
c889b896 | 1364 | platform_driver_unregister(&serial_imx_driver); |
4b300c36 | 1365 | uart_unregister_driver(&imx_reg); |
1da177e4 LT |
1366 | } |
1367 | ||
1368 | module_init(imx_serial_init); | |
1369 | module_exit(imx_serial_exit); | |
1370 | ||
1371 | MODULE_AUTHOR("Sascha Hauer"); | |
1372 | MODULE_DESCRIPTION("IMX generic serial port driver"); | |
1373 | MODULE_LICENSE("GPL"); | |
e169c139 | 1374 | MODULE_ALIAS("platform:imx-uart"); |