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[ARM] 4994/1: <IMX UART>: Move error handling into execution path
[linux-block.git] / drivers / serial / imx.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
1da177e4
LT		 28
29#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4
LT		 39#include <linux/tty.h>
40#include <linux/tty_flip.h>
41#include <linux/serial_core.h>
42#include <linux/serial.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/hardware.h>
5b802344 47#include <asm/arch/imx-uart.h>
1da177e4 48
ff4bfb21
SH		 49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define BIPR1 0xb0 /* Incremental Preset Register 1 */
65#define BIPR2 0xb4 /* Incremental Preset Register 2 */
66#define BIPR3 0xb8 /* Incremental Preset Register 3 */
67#define BIPR4 0xbc /* Incremental Preset Register 4 */
68#define BMPR1 0xc0 /* BRM Modulator Register 1 */
69#define BMPR2 0xc4 /* BRM Modulator Register 2 */
70#define BMPR3 0xc8 /* BRM Modulator Register 3 */
71#define BMPR4 0xcc /* BRM Modulator Register 4 */
72#define UTS 0xd0 /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
163#define UTS_SOFTRST (1<<0) /* Software reset */
164
1da177e4
LT		 165/* We've been assigned a range on the "Low-density serial ports" major */
166#define SERIAL_IMX_MAJOR 204
167#define MINOR_START 41
168
1da177e4
LT		 169/*
170 * This is the size of our serial port register set.
171 */
172#define UART_PORT_SIZE 0x100
173
174/*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180#define MCTRL_TIMEOUT (250*HZ/1000)
181
182#define DRIVER_NAME "IMX-uart"
183
184struct imx_port {
185 struct uart_port port;
186 struct timer_list timer;
187 unsigned int old_status;
5b802344
SH		 188 int txirq,rxirq,rtsirq;
189 int have_rtscts:1;
1da177e4
LT		 190};
191
192/*
193 * Handle any change of modem status signal since we were last called.
194 */
195static void imx_mctrl_check(struct imx_port *sport)
196{
197 unsigned int status, changed;
198
199 status = sport->port.ops->get_mctrl(&sport->port);
200 changed = status ^ sport->old_status;
201
202 if (changed == 0)
203 return;
204
205 sport->old_status = status;
206
207 if (changed & TIOCM_RI)
208 sport->port.icount.rng++;
209 if (changed & TIOCM_DSR)
210 sport->port.icount.dsr++;
211 if (changed & TIOCM_CAR)
212 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
213 if (changed & TIOCM_CTS)
214 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
215
216 wake_up_interruptible(&sport->port.info->delta_msr_wait);
217}
218
219/*
220 * This is our per-port timeout handler, for checking the
221 * modem status signals.
222 */
223static void imx_timeout(unsigned long data)
224{
225 struct imx_port *sport = (struct imx_port *)data;
226 unsigned long flags;
227
228 if (sport->port.info) {
229 spin_lock_irqsave(&sport->port.lock, flags);
230 imx_mctrl_check(sport);
231 spin_unlock_irqrestore(&sport->port.lock, flags);
232
233 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
234 }
235}
236
237/*
238 * interrupts disabled on entry
239 */
b129a8cc 240static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 241{
242 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 243 unsigned long temp;
244
245 temp = readl(sport->port.membase + UCR1);
246 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 247}
248
249/*
250 * interrupts disabled on entry
251 */
252static void imx_stop_rx(struct uart_port *port)
253{
254 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 255 unsigned long temp;
256
257 temp = readl(sport->port.membase + UCR2);
258 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
1da177e4
LT		 259}
260
261/*
262 * Set the modem control timer to fire immediately.
263 */
264static void imx_enable_ms(struct uart_port *port)
265{
266 struct imx_port *sport = (struct imx_port *)port;
267
268 mod_timer(&sport->timer, jiffies);
269}
270
271static inline void imx_transmit_buffer(struct imx_port *sport)
272{
273 struct circ_buf *xmit = &sport->port.info->xmit;
274
ff4bfb21 275 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
1da177e4
LT		 276 /* send xmit->buf[xmit->tail]
277 * out the port here */
ff4bfb21 278 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
1da177e4
LT		 279 xmit->tail = (xmit->tail + 1) &
280 (UART_XMIT_SIZE - 1);
281 sport->port.icount.tx++;
282 if (uart_circ_empty(xmit))
283 break;
8c0b254b 284 }
1da177e4
LT		 285
286 if (uart_circ_empty(xmit))
b129a8cc 287 imx_stop_tx(&sport->port);
1da177e4
LT		 288}
289
290/*
291 * interrupts disabled on entry
292 */
b129a8cc 293static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 294{
295 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 296 unsigned long temp;
1da177e4 297
ff4bfb21
SH		 298 temp = readl(sport->port.membase + UCR1);
299 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4 300
ff4bfb21
SH		 301 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
302 imx_transmit_buffer(sport);
1da177e4
LT		 303}
304
7d12e780 305static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 306{
15aafa2f 307 struct imx_port *sport = dev_id;
ff4bfb21 308 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e
SH		 309 unsigned long flags;
310
311 spin_lock_irqsave(&sport->port.lock, flags);
312
ff4bfb21 313 writel(USR1_RTSD, sport->port.membase + USR1);
ceca629e
SH		 314 uart_handle_cts_change(&sport->port, !!val);
315 wake_up_interruptible(&sport->port.info->delta_msr_wait);
316
317 spin_unlock_irqrestore(&sport->port.lock, flags);
318 return IRQ_HANDLED;
319}
320
7d12e780 321static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 322{
15aafa2f 323 struct imx_port *sport = dev_id;
1da177e4
LT		 324 struct circ_buf *xmit = &sport->port.info->xmit;
325 unsigned long flags;
326
327 spin_lock_irqsave(&sport->port.lock,flags);
328 if (sport->port.x_char)
329 {
330 /* Send next char */
ff4bfb21 331 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 332 goto out;
333 }
334
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 336 imx_stop_tx(&sport->port);
1da177e4
LT		 337 goto out;
338 }
339
340 imx_transmit_buffer(sport);
341
342 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(&sport->port);
344
345out:
346 spin_unlock_irqrestore(&sport->port.lock,flags);
347 return IRQ_HANDLED;
348}
349
7d12e780 350static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 351{
352 struct imx_port *sport = dev_id;
353 unsigned int rx,flg,ignored = 0;
354 struct tty_struct *tty = sport->port.info->tty;
ff4bfb21 355 unsigned long flags, temp;
1da177e4 356
1da177e4
LT		 357 spin_lock_irqsave(&sport->port.lock,flags);
358
864eeed0 359 while ((rx = readl(sport->port.membase + URXD0)) & URXD_CHARRDY) {
1da177e4
LT		 360 flg = TTY_NORMAL;
361 sport->port.icount.rx++;
362
ff4bfb21 363 temp = readl(sport->port.membase + USR2);
864eeed0 364 if (temp & USR2_BRCD) {
ff4bfb21 365 writel(temp | USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 366 if (uart_handle_break(&sport->port))
367 continue;
1da177e4
LT		 368 }
369
370 if (uart_handle_sysrq_char
7d12e780 371 (&sport->port, (unsigned char)rx))
864eeed0
SH		 372 continue;
373
374 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
375 if (rx & URXD_PRERR)
376 sport->port.icount.parity++;
377 else if (rx & URXD_FRMERR)
378 sport->port.icount.frame++;
379 if (rx & URXD_OVRRUN)
380 sport->port.icount.overrun++;
381
382 if (rx & sport->port.ignore_status_mask) {
383 if (++ignored > 100)
384 goto out;
385 continue;
386 }
387
388 rx &= sport->port.read_status_mask;
389
390 if (rx & URXD_PRERR)
391 flg = TTY_PARITY;
392 else if (rx & URXD_FRMERR)
393 flg = TTY_FRAME;
394 if (rx & URXD_OVRRUN)
395 flg = TTY_OVERRUN;
1da177e4 396
864eeed0
SH		 397#ifdef SUPPORT_SYSRQ
398 sport->port.sysrq = 0;
399#endif
400 }
1da177e4 401
1da177e4 402 tty_insert_flip_char(tty, rx, flg);
864eeed0 403 }
1da177e4
LT		 404
405out:
406 spin_unlock_irqrestore(&sport->port.lock,flags);
407 tty_flip_buffer_push(tty);
408 return IRQ_HANDLED;
1da177e4
LT		 409}
410
411/*
412 * Return TIOCSER_TEMT when transmitter is not busy.
413 */
414static unsigned int imx_tx_empty(struct uart_port *port)
415{
416 struct imx_port *sport = (struct imx_port *)port;
417
ff4bfb21 418 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4
LT		 419}
420
0f302dc3
SH		 421/*
422 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
423 */
1da177e4
LT		 424static unsigned int imx_get_mctrl(struct uart_port *port)
425{
0f302dc3
SH		 426 struct imx_port *sport = (struct imx_port *)port;
427 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
428
ff4bfb21 429 if (readl(sport->port.membase + USR1) & USR1_RTSS)
0f302dc3
SH		 430 tmp |= TIOCM_CTS;
431
ff4bfb21 432 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
0f302dc3
SH		 433 tmp |= TIOCM_RTS;
434
435 return tmp;
1da177e4
LT		 436}
437
438static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
439{
0f302dc3 440 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 441 unsigned long temp;
442
443 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3
SH		 444
445 if (mctrl & TIOCM_RTS)
ff4bfb21
SH		 446 temp |= UCR2_CTS;
447
448 writel(temp, sport->port.membase + UCR2);
1da177e4
LT		 449}
450
451/*
452 * Interrupts always disabled.
453 */
454static void imx_break_ctl(struct uart_port *port, int break_state)
455{
456 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 457 unsigned long flags, temp;
1da177e4
LT		 458
459 spin_lock_irqsave(&sport->port.lock, flags);
460
ff4bfb21
SH		 461 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
462
1da177e4 463 if ( break_state != 0 )
ff4bfb21
SH		 464 temp |= UCR1_SNDBRK;
465
466 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 467
468 spin_unlock_irqrestore(&sport->port.lock, flags);
469}
470
471#define TXTL 2 /* reset default */
472#define RXTL 1 /* reset default */
473
587897f5
SH		 474static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
475{
476 unsigned int val;
477 unsigned int ufcr_rfdiv;
478
479 /* set receiver / transmitter trigger level.
480 * RFDIV is set such way to satisfy requested uartclk value
481 */
ff4bfb21 482 val = TXTL << 10 | RXTL;
587897f5
SH		 483 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
484
485 if(!ufcr_rfdiv)
486 ufcr_rfdiv = 1;
487
488 if(ufcr_rfdiv >= 7)
489 ufcr_rfdiv = 6;
490 else
491 ufcr_rfdiv = 6 - ufcr_rfdiv;
492
493 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
494
ff4bfb21 495 writel(val, sport->port.membase + UFCR);
587897f5
SH		 496
497 return 0;
498}
499
1da177e4
LT		 500static int imx_startup(struct uart_port *port)
501{
502 struct imx_port *sport = (struct imx_port *)port;
503 int retval;
ff4bfb21 504 unsigned long flags, temp;
1da177e4 505
587897f5 506 imx_setup_ufcr(sport, 0);
1da177e4
LT		 507
508 /* disable the DREN bit (Data Ready interrupt enable) before
509 * requesting IRQs
510 */
ff4bfb21
SH		 511 temp = readl(sport->port.membase + UCR4);
512 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4
LT		 513
514 /*
515 * Allocate the IRQ
516 */
517 retval = request_irq(sport->rxirq, imx_rxint, 0,
518 DRIVER_NAME, sport);
86371d07 519 if (retval) goto error_out1;
1da177e4
LT		 520
521 retval = request_irq(sport->txirq, imx_txint, 0,
ceca629e 522 DRIVER_NAME, sport);
86371d07 523 if (retval) goto error_out2;
1da177e4 524
f43aaba1 525 retval = request_irq(sport->rtsirq, imx_rtsint,
d7ea10d9
PP		 526 (sport->rtsirq < IMX_IRQS) ? 0 :
527 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
ceca629e
SH		 528 DRIVER_NAME, sport);
529 if (retval) goto error_out3;
ceca629e 530
1da177e4
LT		 531 /*
532 * Finally, clear and enable interrupts
533 */
ff4bfb21
SH		 534 writel(USR1_RTSD, sport->port.membase + USR1);
535
536 temp = readl(sport->port.membase + UCR1);
537 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
538 writel(temp, sport->port.membase + UCR1);
1da177e4 539
ff4bfb21
SH		 540 temp = readl(sport->port.membase + UCR2);
541 temp |= (UCR2_RXEN | UCR2_TXEN);
542 writel(temp, sport->port.membase + UCR2);
1da177e4 543
1da177e4
LT		 544 /*
545 * Enable modem status interrupts
546 */
547 spin_lock_irqsave(&sport->port.lock,flags);
548 imx_enable_ms(&sport->port);
549 spin_unlock_irqrestore(&sport->port.lock,flags);
550
551 return 0;
552
ceca629e
SH		 553error_out3:
554 free_irq(sport->txirq, sport);
1da177e4 555error_out2:
86371d07
SH		 556 free_irq(sport->rxirq, sport);
557error_out1:
1da177e4
LT		 558 return retval;
559}
560
561static void imx_shutdown(struct uart_port *port)
562{
563 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 564 unsigned long temp;
1da177e4
LT		 565
566 /*
567 * Stop our timer.
568 */
569 del_timer_sync(&sport->timer);
570
571 /*
572 * Free the interrupts
573 */
ceca629e 574 free_irq(sport->rtsirq, sport);
1da177e4
LT		 575 free_irq(sport->txirq, sport);
576 free_irq(sport->rxirq, sport);
577
578 /*
579 * Disable all interrupts, port and break condition.
580 */
581
ff4bfb21
SH		 582 temp = readl(sport->port.membase + UCR1);
583 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
584 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 585}
586
587static void
606d099c
AC		 588imx_set_termios(struct uart_port *port, struct ktermios *termios,
589 struct ktermios *old)
1da177e4
LT		 590{
591 struct imx_port *sport = (struct imx_port *)port;
592 unsigned long flags;
593 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
594 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
595
596 /*
597 * If we don't support modem control lines, don't allow
598 * these to be set.
599 */
600 if (0) {
601 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
602 termios->c_cflag |= CLOCAL;
603 }
604
605 /*
606 * We only support CS7 and CS8.
607 */
608 while ((termios->c_cflag & CSIZE) != CS7 &&
609 (termios->c_cflag & CSIZE) != CS8) {
610 termios->c_cflag &= ~CSIZE;
611 termios->c_cflag |= old_csize;
612 old_csize = CS8;
613 }
614
615 if ((termios->c_cflag & CSIZE) == CS8)
616 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
617 else
618 ucr2 = UCR2_SRST | UCR2_IRTS;
619
620 if (termios->c_cflag & CRTSCTS) {
5b802344
SH		 621 if( sport->have_rtscts ) {
622 ucr2 &= ~UCR2_IRTS;
623 ucr2 |= UCR2_CTSC;
624 } else {
625 termios->c_cflag &= ~CRTSCTS;
626 }
1da177e4
LT		 627 }
628
629 if (termios->c_cflag & CSTOPB)
630 ucr2 |= UCR2_STPB;
631 if (termios->c_cflag & PARENB) {
632 ucr2 |= UCR2_PREN;
3261e362 633 if (termios->c_cflag & PARODD)
1da177e4
LT		 634 ucr2 |= UCR2_PROE;
635 }
636
637 /*
638 * Ask the core to calculate the divisor for us.
639 */
640 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
641 quot = uart_get_divisor(port, baud);
642
643 spin_lock_irqsave(&sport->port.lock, flags);
644
645 sport->port.read_status_mask = 0;
646 if (termios->c_iflag & INPCK)
647 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
648 if (termios->c_iflag & (BRKINT | PARMRK))
649 sport->port.read_status_mask |= URXD_BRK;
650
651 /*
652 * Characters to ignore
653 */
654 sport->port.ignore_status_mask = 0;
655 if (termios->c_iflag & IGNPAR)
656 sport->port.ignore_status_mask |= URXD_PRERR;
657 if (termios->c_iflag & IGNBRK) {
658 sport->port.ignore_status_mask |= URXD_BRK;
659 /*
660 * If we're ignoring parity and break indicators,
661 * ignore overruns too (for real raw support).
662 */
663 if (termios->c_iflag & IGNPAR)
664 sport->port.ignore_status_mask |= URXD_OVRRUN;
665 }
666
667 del_timer_sync(&sport->timer);
668
669 /*
670 * Update the per-port timeout.
671 */
672 uart_update_timeout(port, termios->c_cflag, baud);
673
674 /*
675 * disable interrupts and drain transmitter
676 */
ff4bfb21
SH		 677 old_ucr1 = readl(sport->port.membase + UCR1);
678 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
679 sport->port.membase + UCR1);
1da177e4 680
ff4bfb21 681 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 682 barrier();
683
684 /* then, disable everything */
ff4bfb21
SH		 685 old_txrxen = readl(sport->port.membase + UCR2);
686 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
687 sport->port.membase + UCR2);
688 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4
LT		 689
690 /* set the baud rate. We assume uartclk = 16 MHz
691 *
692 * baud * 16 UBIR - 1
693 * --------- = --------
694 * uartclk UBMR - 1
695 */
ff4bfb21
SH		 696 writel((baud / 100) - 1, sport->port.membase + UBIR);
697 writel(10000 - 1, sport->port.membase + UBMR);
698
699 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 700
ff4bfb21
SH		 701 /* set the parity, stop bits and data size */
702 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 703
704 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
705 imx_enable_ms(&sport->port);
706
707 spin_unlock_irqrestore(&sport->port.lock, flags);
708}
709
710static const char *imx_type(struct uart_port *port)
711{
712 struct imx_port *sport = (struct imx_port *)port;
713
714 return sport->port.type == PORT_IMX ? "IMX" : NULL;
715}
716
717/*
718 * Release the memory region(s) being used by 'port'.
719 */
720static void imx_release_port(struct uart_port *port)
721{
722 struct imx_port *sport = (struct imx_port *)port;
723
724 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
725}
726
727/*
728 * Request the memory region(s) being used by 'port'.
729 */
730static int imx_request_port(struct uart_port *port)
731{
732 struct imx_port *sport = (struct imx_port *)port;
733
734 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
735 "imx-uart") != NULL ? 0 : -EBUSY;
736}
737
738/*
739 * Configure/autoconfigure the port.
740 */
741static void imx_config_port(struct uart_port *port, int flags)
742{
743 struct imx_port *sport = (struct imx_port *)port;
744
745 if (flags & UART_CONFIG_TYPE &&
746 imx_request_port(&sport->port) == 0)
747 sport->port.type = PORT_IMX;
748}
749
750/*
751 * Verify the new serial_struct (for TIOCSSERIAL).
752 * The only change we allow are to the flags and type, and
753 * even then only between PORT_IMX and PORT_UNKNOWN
754 */
755static int
756imx_verify_port(struct uart_port *port, struct serial_struct *ser)
757{
758 struct imx_port *sport = (struct imx_port *)port;
759 int ret = 0;
760
761 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
762 ret = -EINVAL;
763 if (sport->port.irq != ser->irq)
764 ret = -EINVAL;
765 if (ser->io_type != UPIO_MEM)
766 ret = -EINVAL;
767 if (sport->port.uartclk / 16 != ser->baud_base)
768 ret = -EINVAL;
769 if ((void *)sport->port.mapbase != ser->iomem_base)
770 ret = -EINVAL;
771 if (sport->port.iobase != ser->port)
772 ret = -EINVAL;
773 if (ser->hub6 != 0)
774 ret = -EINVAL;
775 return ret;
776}
777
778static struct uart_ops imx_pops = {
779 .tx_empty = imx_tx_empty,
780 .set_mctrl = imx_set_mctrl,
781 .get_mctrl = imx_get_mctrl,
782 .stop_tx = imx_stop_tx,
783 .start_tx = imx_start_tx,
784 .stop_rx = imx_stop_rx,
785 .enable_ms = imx_enable_ms,
786 .break_ctl = imx_break_ctl,
787 .startup = imx_startup,
788 .shutdown = imx_shutdown,
789 .set_termios = imx_set_termios,
790 .type = imx_type,
791 .release_port = imx_release_port,
792 .request_port = imx_request_port,
793 .config_port = imx_config_port,
794 .verify_port = imx_verify_port,
795};
796
797static struct imx_port imx_ports[] = {
798 {
799 .txirq = UART1_MINT_TX,
800 .rxirq = UART1_MINT_RX,
ceca629e 801 .rtsirq = UART1_MINT_RTS,
1da177e4
LT		 802 .port = {
803 .type = PORT_IMX,
9b4a1617 804 .iotype = UPIO_MEM,
1da177e4
LT		 805 .membase = (void *)IMX_UART1_BASE,
806 .mapbase = IMX_UART1_BASE, /* FIXME */
807 .irq = UART1_MINT_RX,
808 .uartclk = 16000000,
8c0b254b 809 .fifosize = 32,
ce8337cb 810 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 811 .ops = &imx_pops,
812 .line = 0,
813 },
814 }, {
815 .txirq = UART2_MINT_TX,
816 .rxirq = UART2_MINT_RX,
ceca629e 817 .rtsirq = UART2_MINT_RTS,
1da177e4
LT		 818 .port = {
819 .type = PORT_IMX,
9b4a1617 820 .iotype = UPIO_MEM,
1da177e4
LT		 821 .membase = (void *)IMX_UART2_BASE,
822 .mapbase = IMX_UART2_BASE, /* FIXME */
823 .irq = UART2_MINT_RX,
824 .uartclk = 16000000,
8c0b254b 825 .fifosize = 32,
ce8337cb 826 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 827 .ops = &imx_pops,
828 .line = 1,
829 },
830 }
831};
832
833/*
834 * Setup the IMX serial ports.
835 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
836 * Which serial port this ends up being depends on the machine you're
837 * running this kernel on. I'm not convinced that this is a good idea,
838 * but that's the way it traditionally works.
839 *
840 */
841static void __init imx_init_ports(void)
842{
843 static int first = 1;
844 int i;
845
846 if (!first)
847 return;
848 first = 0;
849
850 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
851 init_timer(&imx_ports[i].timer);
852 imx_ports[i].timer.function = imx_timeout;
853 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
854 }
1da177e4
LT		 855}
856
857#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 858static void imx_console_putchar(struct uart_port *port, int ch)
859{
860 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 861
862 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
d358788f 863 barrier();
ff4bfb21
SH		 864
865 writel(ch, sport->port.membase + URTX0);
d358788f 866}
1da177e4
LT		 867
868/*
869 * Interrupts are disabled on entering
870 */
871static void
872imx_console_write(struct console *co, const char *s, unsigned int count)
873{
874 struct imx_port *sport = &imx_ports[co->index];
d358788f 875 unsigned int old_ucr1, old_ucr2;
1da177e4
LT		 876
877 /*
878 * First, save UCR1/2 and then disable interrupts
879 */
ff4bfb21
SH		 880 old_ucr1 = readl(sport->port.membase + UCR1);
881 old_ucr2 = readl(sport->port.membase + UCR2);
1da177e4 882
ff4bfb21
SH		 883 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
884 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
885 sport->port.membase + UCR1);
886
887 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 888
d358788f 889 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 890
891 /*
892 * Finally, wait for transmitter to become empty
893 * and restore UCR1/2
894 */
ff4bfb21 895 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 896
ff4bfb21
SH		 897 writel(old_ucr1, sport->port.membase + UCR1);
898 writel(old_ucr2, sport->port.membase + UCR2);
1da177e4
LT		 899}
900
901/*
902 * If the port was already initialised (eg, by a boot loader),
903 * try to determine the current setup.
904 */
905static void __init
906imx_console_get_options(struct imx_port *sport, int *baud,
907 int *parity, int *bits)
908{
587897f5 909
ff4bfb21 910 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1da177e4
LT		 911 /* ok, the port was enabled */
912 unsigned int ucr2, ubir,ubmr, uartclk;
587897f5
SH		 913 unsigned int baud_raw;
914 unsigned int ucfr_rfdiv;
1da177e4 915
ff4bfb21 916 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 917
918 *parity = 'n';
919 if (ucr2 & UCR2_PREN) {
920 if (ucr2 & UCR2_PROE)
921 *parity = 'o';
922 else
923 *parity = 'e';
924 }
925
926 if (ucr2 & UCR2_WS)
927 *bits = 8;
928 else
929 *bits = 7;
930
ff4bfb21
SH		 931 ubir = readl(sport->port.membase + UBIR) & 0xffff;
932 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 933
ff4bfb21 934 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 935 if (ucfr_rfdiv == 6)
936 ucfr_rfdiv = 7;
937 else
938 ucfr_rfdiv = 6 - ucfr_rfdiv;
939
940 uartclk = imx_get_perclk1();
941 uartclk /= ucfr_rfdiv;
942
943 { /*
944 * The next code provides exact computation of
945 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
946 * without need of float support or long long division,
947 * which would be required to prevent 32bit arithmetic overflow
948 */
949 unsigned int mul = ubir + 1;
950 unsigned int div = 16 * (ubmr + 1);
951 unsigned int rem = uartclk % div;
952
953 baud_raw = (uartclk / div) * mul;
954 baud_raw += (rem * mul + div / 2) / div;
955 *baud = (baud_raw + 50) / 100 * 100;
956 }
957
958 if(*baud != baud_raw)
959 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
960 baud_raw, *baud);
1da177e4
LT		 961 }
962}
963
964static int __init
965imx_console_setup(struct console *co, char *options)
966{
967 struct imx_port *sport;
968 int baud = 9600;
969 int bits = 8;
970 int parity = 'n';
971 int flow = 'n';
972
973 /*
974 * Check whether an invalid uart number has been specified, and
975 * if so, search for the first available port that does have
976 * console support.
977 */
978 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
979 co->index = 0;
980 sport = &imx_ports[co->index];
981
982 if (options)
983 uart_parse_options(options, &baud, &parity, &bits, &flow);
984 else
985 imx_console_get_options(sport, &baud, &parity, &bits);
986
587897f5
SH		 987 imx_setup_ufcr(sport, 0);
988
1da177e4
LT		 989 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
990}
991
9f4426dd 992static struct uart_driver imx_reg;
1da177e4
LT		 993static struct console imx_console = {
994 .name = "ttySMX",
995 .write = imx_console_write,
996 .device = uart_console_device,
997 .setup = imx_console_setup,
998 .flags = CON_PRINTBUFFER,
999 .index = -1,
1000 .data = &imx_reg,
1001};
1002
1003static int __init imx_rs_console_init(void)
1004{
1005 imx_init_ports();
1006 register_console(&imx_console);
1007 return 0;
1008}
1009console_initcall(imx_rs_console_init);
1010
1011#define IMX_CONSOLE &imx_console
1012#else
1013#define IMX_CONSOLE NULL
1014#endif
1015
1016static struct uart_driver imx_reg = {
1017 .owner = THIS_MODULE,
1018 .driver_name = DRIVER_NAME,
1019 .dev_name = "ttySMX",
1da177e4
LT		 1020 .major = SERIAL_IMX_MAJOR,
1021 .minor = MINOR_START,
1022 .nr = ARRAY_SIZE(imx_ports),
1023 .cons = IMX_CONSOLE,
1024};
1025
3ae5eaec 1026static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1027{
3ae5eaec 1028 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1029
9480e307 1030 if (sport)
1da177e4
LT		 1031 uart_suspend_port(&imx_reg, &sport->port);
1032
1033 return 0;
1034}
1035
3ae5eaec 1036static int serial_imx_resume(struct platform_device *dev)
1da177e4 1037{
3ae5eaec 1038 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1039
9480e307 1040 if (sport)
1da177e4
LT		 1041 uart_resume_port(&imx_reg, &sport->port);
1042
1043 return 0;
1044}
1045
3ae5eaec 1046static int serial_imx_probe(struct platform_device *dev)
1da177e4 1047{
5b802344
SH		 1048 struct imxuart_platform_data *pdata;
1049
3ae5eaec 1050 imx_ports[dev->id].port.dev = &dev->dev;
5b802344
SH		 1051
1052 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1053 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1054 imx_ports[dev->id].have_rtscts = 1;
1055
1da177e4 1056 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
3ae5eaec 1057 platform_set_drvdata(dev, &imx_ports[dev->id]);
1da177e4
LT		 1058 return 0;
1059}
1060
3ae5eaec 1061static int serial_imx_remove(struct platform_device *dev)
1da177e4 1062{
3ae5eaec 1063 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1064
3ae5eaec 1065 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1066
1067 if (sport)
1068 uart_remove_one_port(&imx_reg, &sport->port);
1069
1070 return 0;
1071}
1072
3ae5eaec 1073static struct platform_driver serial_imx_driver = {
1da177e4
LT		 1074 .probe = serial_imx_probe,
1075 .remove = serial_imx_remove,
1076
1077 .suspend = serial_imx_suspend,
1078 .resume = serial_imx_resume,
3ae5eaec
RK		 1079 .driver = {
1080 .name = "imx-uart",
1081 },
1da177e4
LT		 1082};
1083
1084static int __init imx_serial_init(void)
1085{
1086 int ret;
1087
1088 printk(KERN_INFO "Serial: IMX driver\n");
1089
1090 imx_init_ports();
1091
1092 ret = uart_register_driver(&imx_reg);
1093 if (ret)
1094 return ret;
1095
3ae5eaec 1096 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 1097 if (ret != 0)
1098 uart_unregister_driver(&imx_reg);
1099
1100 return 0;
1101}
1102
1103static void __exit imx_serial_exit(void)
1104{
c889b896 1105 platform_driver_unregister(&serial_imx_driver);
4b300c36 1106 uart_unregister_driver(&imx_reg);
1da177e4
LT		 1107}
1108
1109module_init(imx_serial_init);
1110module_exit(imx_serial_exit);
1111
1112MODULE_AUTHOR("Sascha Hauer");
1113MODULE_DESCRIPTION("IMX generic serial port driver");
1114MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)