Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * dz.h: Serial port driver for DECStations equiped | |
3 | * with the DZ chipset. | |
4 | * | |
5 | * Copyright (C) 1998 Olivier A. D. Lebaillif | |
6 | * | |
7 | * Email: olivier.lebaillif@ifrsys.com | |
8 | * | |
9 | */ | |
10 | #ifndef DZ_SERIAL_H | |
11 | #define DZ_SERIAL_H | |
12 | ||
13 | /* | |
14 | * Definitions for the Control and Status Received. | |
15 | */ | |
16 | #define DZ_TRDY 0x8000 /* Transmitter empty */ | |
17 | #define DZ_TIE 0x4000 /* Transmitter Interrupt Enable */ | |
18 | #define DZ_RDONE 0x0080 /* Receiver data ready */ | |
19 | #define DZ_RIE 0x0040 /* Receive Interrupt Enable */ | |
20 | #define DZ_MSE 0x0020 /* Master Scan Enable */ | |
21 | #define DZ_CLR 0x0010 /* Master reset */ | |
22 | #define DZ_MAINT 0x0008 /* Loop Back Mode */ | |
23 | ||
24 | /* | |
25 | * Definitions for the Received buffer. | |
26 | */ | |
27 | #define DZ_RBUF_MASK 0x00FF /* Data Mask in the Receive Buffer */ | |
28 | #define DZ_LINE_MASK 0x0300 /* Line Mask in the Receive Buffer */ | |
29 | #define DZ_DVAL 0x8000 /* Valid Data indicator */ | |
30 | #define DZ_OERR 0x4000 /* Overrun error indicator */ | |
31 | #define DZ_FERR 0x2000 /* Frame error indicator */ | |
32 | #define DZ_PERR 0x1000 /* Parity error indicator */ | |
33 | ||
34 | #define LINE(x) (x & DZ_LINE_MASK) >> 8 /* Get the line number from the input buffer */ | |
35 | #define UCHAR(x) (unsigned char)(x & DZ_RBUF_MASK) | |
36 | ||
37 | /* | |
38 | * Definitions for the Transmit Register. | |
39 | */ | |
40 | #define DZ_LINE_KEYBOARD 0x0001 | |
41 | #define DZ_LINE_MOUSE 0x0002 | |
42 | #define DZ_LINE_MODEM 0x0004 | |
43 | #define DZ_LINE_PRINTER 0x0008 | |
44 | ||
45 | #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */ | |
46 | ||
47 | /* | |
48 | * Definitions for the Modem Status Register. | |
49 | */ | |
50 | #define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */ | |
51 | ||
52 | /* | |
53 | * Definitions for the Transmit Data Register. | |
54 | */ | |
55 | #define DZ_BRK0 0x0100 /* Break assertion for line 0 */ | |
56 | #define DZ_BRK1 0x0200 /* Break assertion for line 1 */ | |
57 | #define DZ_BRK2 0x0400 /* Break assertion for line 2 */ | |
58 | #define DZ_BRK3 0x0800 /* Break assertion for line 3 */ | |
59 | ||
60 | /* | |
61 | * Definitions for the Line Parameter Register. | |
62 | */ | |
63 | #define DZ_KEYBOARD 0x0000 /* line 0 = keyboard */ | |
64 | #define DZ_MOUSE 0x0001 /* line 1 = mouse */ | |
65 | #define DZ_MODEM 0x0002 /* line 2 = modem */ | |
66 | #define DZ_PRINTER 0x0003 /* line 3 = printer */ | |
67 | ||
68 | #define DZ_CSIZE 0x0018 /* Number of bits per byte (mask) */ | |
69 | #define DZ_CS5 0x0000 /* 5 bits per byte */ | |
70 | #define DZ_CS6 0x0008 /* 6 bits per byte */ | |
71 | #define DZ_CS7 0x0010 /* 7 bits per byte */ | |
72 | #define DZ_CS8 0x0018 /* 8 bits per byte */ | |
73 | ||
74 | #define DZ_CSTOPB 0x0020 /* 2 stop bits instead of one */ | |
75 | ||
76 | #define DZ_PARENB 0x0040 /* Parity enable */ | |
77 | #define DZ_PARODD 0x0080 /* Odd parity instead of even */ | |
78 | ||
79 | #define DZ_CBAUD 0x0E00 /* Baud Rate (mask) */ | |
80 | #define DZ_B50 0x0000 | |
81 | #define DZ_B75 0x0100 | |
82 | #define DZ_B110 0x0200 | |
83 | #define DZ_B134 0x0300 | |
84 | #define DZ_B150 0x0400 | |
85 | #define DZ_B300 0x0500 | |
86 | #define DZ_B600 0x0600 | |
87 | #define DZ_B1200 0x0700 | |
88 | #define DZ_B1800 0x0800 | |
89 | #define DZ_B2000 0x0900 | |
90 | #define DZ_B2400 0x0A00 | |
91 | #define DZ_B3600 0x0B00 | |
92 | #define DZ_B4800 0x0C00 | |
93 | #define DZ_B7200 0x0D00 | |
94 | #define DZ_B9600 0x0E00 | |
95 | ||
96 | #define DZ_CREAD 0x1000 /* Enable receiver */ | |
97 | #define DZ_RXENAB 0x1000 /* enable receive char */ | |
98 | /* | |
99 | * Addresses for the DZ registers | |
100 | */ | |
101 | #define DZ_CSR 0x00 /* Control and Status Register */ | |
102 | #define DZ_RBUF 0x08 /* Receive Buffer */ | |
103 | #define DZ_LPR 0x08 /* Line Parameters Register */ | |
104 | #define DZ_TCR 0x10 /* Transmitter Control Register */ | |
105 | #define DZ_MSR 0x18 /* Modem Status Register */ | |
106 | #define DZ_TDR 0x18 /* Transmit Data Register */ | |
107 | ||
108 | #define DZ_NB_PORT 4 | |
109 | ||
110 | #define DZ_XMIT_SIZE 4096 /* buffer size */ | |
111 | #define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4 | |
112 | ||
113 | #ifdef MODULE | |
114 | int init_module (void) | |
115 | void cleanup_module (void) | |
116 | #endif | |
117 | ||
118 | #endif /* DZ_SERIAL_H */ |