projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] cpm_uart: Fix 2nd serial port on MPC8560 ADS
[linux-2.6-block.git] / drivers / serial / cpm_uart / cpm_uart_core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; core driver
5 *
6 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
7 * Based on ppc8xx.c by Thomas Gleixner
8 * Based on drivers/serial/amba.c by Russell King
9 *
10 * Maintainer: Kumar Gala (kumar.gala@freescale.com) (CPM2)
11 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
311c4627 12 *
1da177e4
LT		 13 * Copyright (C) 2004 Freescale Semiconductor, Inc.
14 * (C) 2004 Intracom, S.A.
311c4627 15 * (C) 2005 MontaVista Software, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
1da177e4
LT		 16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 *
31 */
32
33#include <linux/config.h>
34#include <linux/module.h>
35#include <linux/tty.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/serial.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/bootmem.h>
43#include <linux/dma-mapping.h>
44
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/delay.h>
48
49#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54#include <linux/kernel.h>
55
56#include "cpm_uart.h"
57
58/***********************************************************************/
59
60/* Track which ports are configured as uarts */
61int cpm_uart_port_map[UART_NR];
62/* How many ports did we config as uarts */
63int cpm_uart_nr;
64
65/**************************************************************/
66
67static int cpm_uart_tx_pump(struct uart_port *port);
68static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
69static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
70static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
71
72/**************************************************************/
73
311c4627
KG		 74static inline unsigned long cpu2cpm_addr(void *addr)
75{
76 if ((unsigned long)addr >= CPM_ADDR)
77 return (unsigned long)addr;
78 return virt_to_bus(addr);
79}
80
81static inline void *cpm2cpu_addr(unsigned long addr)
82{
83 if (addr >= CPM_ADDR)
84 return (void *)addr;
85 return bus_to_virt(addr);
86}
87
1da177e4 88/*
311c4627 89 * Check, if transmit buffers are processed
1da177e4
LT		 90*/
91static unsigned int cpm_uart_tx_empty(struct uart_port *port)
92{
93 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
94 volatile cbd_t *bdp = pinfo->tx_bd_base;
95 int ret = 0;
96
97 while (1) {
98 if (bdp->cbd_sc & BD_SC_READY)
99 break;
100
101 if (bdp->cbd_sc & BD_SC_WRAP) {
102 ret = TIOCSER_TEMT;
103 break;
104 }
105 bdp++;
106 }
107
108 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
109
110 return ret;
111}
112
113static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
114{
115 /* Whee. Do nothing. */
116}
117
118static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
119{
120 /* Whee. Do nothing. */
121 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
122}
123
124/*
125 * Stop transmitter
126 */
b129a8cc 127static void cpm_uart_stop_tx(struct uart_port *port)
1da177e4
LT		 128{
129 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
130 volatile smc_t *smcp = pinfo->smcp;
131 volatile scc_t *sccp = pinfo->sccp;
132
133 pr_debug("CPM uart[%d]:stop tx\n", port->line);
134
135 if (IS_SMC(pinfo))
136 smcp->smc_smcm &= ~SMCM_TX;
137 else
138 sccp->scc_sccm &= ~UART_SCCM_TX;
139}
140
141/*
142 * Start transmitter
143 */
b129a8cc 144static void cpm_uart_start_tx(struct uart_port *port)
1da177e4
LT		 145{
146 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
147 volatile smc_t *smcp = pinfo->smcp;
148 volatile scc_t *sccp = pinfo->sccp;
149
150 pr_debug("CPM uart[%d]:start tx\n", port->line);
151
152 if (IS_SMC(pinfo)) {
153 if (smcp->smc_smcm & SMCM_TX)
154 return;
155 } else {
156 if (sccp->scc_sccm & UART_SCCM_TX)
157 return;
158 }
159
160 if (cpm_uart_tx_pump(port) != 0) {
311c4627 161 if (IS_SMC(pinfo)) {
1da177e4 162 smcp->smc_smcm |= SMCM_TX;
311c4627
KG		 163 smcp->smc_smcmr |= SMCMR_TEN;
164 } else {
1da177e4 165 sccp->scc_sccm |= UART_SCCM_TX;
311c4627
KG		 166 pinfo->sccp->scc_gsmrl |= SCC_GSMRL_ENT;
167 }
1da177e4
LT		 168 }
169}
170
171/*
311c4627 172 * Stop receiver
1da177e4
LT		 173 */
174static void cpm_uart_stop_rx(struct uart_port *port)
175{
176 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
177 volatile smc_t *smcp = pinfo->smcp;
178 volatile scc_t *sccp = pinfo->sccp;
179
180 pr_debug("CPM uart[%d]:stop rx\n", port->line);
181
182 if (IS_SMC(pinfo))
183 smcp->smc_smcm &= ~SMCM_RX;
184 else
185 sccp->scc_sccm &= ~UART_SCCM_RX;
186}
187
188/*
189 * Enable Modem status interrupts
190 */
191static void cpm_uart_enable_ms(struct uart_port *port)
192{
193 pr_debug("CPM uart[%d]:enable ms\n", port->line);
194}
195
196/*
311c4627 197 * Generate a break.
1da177e4
LT		 198 */
199static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
200{
201 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
202 int line = pinfo - cpm_uart_ports;
203
204 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
205 break_state);
206
207 if (break_state)
208 cpm_line_cr_cmd(line, CPM_CR_STOP_TX);
209 else
210 cpm_line_cr_cmd(line, CPM_CR_RESTART_TX);
211}
212
213/*
214 * Transmit characters, refill buffer descriptor, if possible
215 */
216static void cpm_uart_int_tx(struct uart_port *port, struct pt_regs *regs)
217{
218 pr_debug("CPM uart[%d]:TX INT\n", port->line);
219
220 cpm_uart_tx_pump(port);
221}
222
223/*
224 * Receive characters
225 */
226static void cpm_uart_int_rx(struct uart_port *port, struct pt_regs *regs)
227{
228 int i;
229 unsigned char ch, *cp;
230 struct tty_struct *tty = port->info->tty;
231 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
232 volatile cbd_t *bdp;
233 u16 status;
234 unsigned int flg;
235
236 pr_debug("CPM uart[%d]:RX INT\n", port->line);
237
238 /* Just loop through the closed BDs and copy the characters into
239 * the buffer.
240 */
241 bdp = pinfo->rx_cur;
242 for (;;) {
243 /* get status */
244 status = bdp->cbd_sc;
245 /* If this one is empty, return happy */
246 if (status & BD_SC_EMPTY)
247 break;
248
249 /* get number of characters, and check spce in flip-buffer */
250 i = bdp->cbd_datlen;
251
311c4627 252 /* If we have not enough room in tty flip buffer, then we try
1da177e4
LT		 253 * later, which will be the next rx-interrupt or a timeout
254 */
255 if ((tty->flip.count + i) >= TTY_FLIPBUF_SIZE) {
256 tty->flip.work.func((void *)tty);
257 if ((tty->flip.count + i) >= TTY_FLIPBUF_SIZE) {
258 printk(KERN_WARNING "TTY_DONT_FLIP set\n");
259 return;
260 }
261 }
262
263 /* get pointer */
311c4627 264 cp = cpm2cpu_addr(bdp->cbd_bufaddr);
1da177e4
LT		 265
266 /* loop through the buffer */
267 while (i-- > 0) {
268 ch = *cp++;
269 port->icount.rx++;
270 flg = TTY_NORMAL;
271
272 if (status &
273 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
274 goto handle_error;
275 if (uart_handle_sysrq_char(port, ch, regs))
276 continue;
277
278 error_return:
279 *tty->flip.char_buf_ptr++ = ch;
280 *tty->flip.flag_buf_ptr++ = flg;
281 tty->flip.count++;
282
283 } /* End while (i--) */
284
285 /* This BD is ready to be used again. Clear status. get next */
311c4627 286 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1da177e4
LT		 287 bdp->cbd_sc |= BD_SC_EMPTY;
288
289 if (bdp->cbd_sc & BD_SC_WRAP)
290 bdp = pinfo->rx_bd_base;
291 else
292 bdp++;
311c4627 293
1da177e4
LT		 294 } /* End for (;;) */
295
296 /* Write back buffer pointer */
297 pinfo->rx_cur = (volatile cbd_t *) bdp;
298
299 /* activate BH processing */
300 tty_flip_buffer_push(tty);
301
302 return;
303
304 /* Error processing */
305
306 handle_error:
307 /* Statistics */
308 if (status & BD_SC_BR)
309 port->icount.brk++;
310 if (status & BD_SC_PR)
311 port->icount.parity++;
312 if (status & BD_SC_FR)
313 port->icount.frame++;
314 if (status & BD_SC_OV)
315 port->icount.overrun++;
316
317 /* Mask out ignored conditions */
318 status &= port->read_status_mask;
319
320 /* Handle the remaining ones */
321 if (status & BD_SC_BR)
322 flg = TTY_BREAK;
323 else if (status & BD_SC_PR)
324 flg = TTY_PARITY;
325 else if (status & BD_SC_FR)
326 flg = TTY_FRAME;
327
328 /* overrun does not affect the current character ! */
329 if (status & BD_SC_OV) {
330 ch = 0;
331 flg = TTY_OVERRUN;
332 /* We skip this buffer */
333 /* CHECK: Is really nothing senseful there */
334 /* ASSUMPTION: it contains nothing valid */
335 i = 0;
336 }
337#ifdef SUPPORT_SYSRQ
338 port->sysrq = 0;
339#endif
340 goto error_return;
341}
342
343/*
344 * Asynchron mode interrupt handler
345 */
346static irqreturn_t cpm_uart_int(int irq, void *data, struct pt_regs *regs)
347{
348 u8 events;
349 struct uart_port *port = (struct uart_port *)data;
350 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
351 volatile smc_t *smcp = pinfo->smcp;
352 volatile scc_t *sccp = pinfo->sccp;
353
354 pr_debug("CPM uart[%d]:IRQ\n", port->line);
355
356 if (IS_SMC(pinfo)) {
357 events = smcp->smc_smce;
311c4627 358 smcp->smc_smce = events;
1da177e4
LT		 359 if (events & SMCM_BRKE)
360 uart_handle_break(port);
361 if (events & SMCM_RX)
362 cpm_uart_int_rx(port, regs);
363 if (events & SMCM_TX)
364 cpm_uart_int_tx(port, regs);
1da177e4
LT		 365 } else {
366 events = sccp->scc_scce;
311c4627 367 sccp->scc_scce = events;
1da177e4
LT		 368 if (events & UART_SCCM_BRKE)
369 uart_handle_break(port);
370 if (events & UART_SCCM_RX)
371 cpm_uart_int_rx(port, regs);
372 if (events & UART_SCCM_TX)
373 cpm_uart_int_tx(port, regs);
1da177e4
LT		 374 }
375 return (events) ? IRQ_HANDLED : IRQ_NONE;
376}
377
378static int cpm_uart_startup(struct uart_port *port)
379{
380 int retval;
381 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
311c4627 382 int line = pinfo - cpm_uart_ports;
1da177e4
LT		 383
384 pr_debug("CPM uart[%d]:startup\n", port->line);
385
386 /* Install interrupt handler. */
387 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
388 if (retval)
389 return retval;
390
391 /* Startup rx-int */
392 if (IS_SMC(pinfo)) {
393 pinfo->smcp->smc_smcm |= SMCM_RX;
394 pinfo->smcp->smc_smcmr |= SMCMR_REN;
395 } else {
396 pinfo->sccp->scc_sccm |= UART_SCCM_RX;
397 }
398
311c4627
KG		 399 if (!(pinfo->flags & FLAG_CONSOLE))
400 cpm_line_cr_cmd(line,CPM_CR_INIT_TRX);
1da177e4
LT		 401 return 0;
402}
403
311c4627
KG		 404inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
405{
406 unsigned long target_jiffies = jiffies + pinfo->wait_closing;
407
408 while (!time_after(jiffies, target_jiffies))
409 schedule();
410}
411
1da177e4
LT		 412/*
413 * Shutdown the uart
414 */
415static void cpm_uart_shutdown(struct uart_port *port)
416{
417 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
418 int line = pinfo - cpm_uart_ports;
419
420 pr_debug("CPM uart[%d]:shutdown\n", port->line);
421
422 /* free interrupt handler */
423 free_irq(port->irq, port);
424
425 /* If the port is not the console, disable Rx and Tx. */
426 if (!(pinfo->flags & FLAG_CONSOLE)) {
311c4627
KG		 427 /* Wait for all the BDs marked sent */
428 while(!cpm_uart_tx_empty(port))
429 schedule_timeout(2);
430 if(pinfo->wait_closing)
431 cpm_uart_wait_until_send(pinfo);
432
1da177e4
LT		 433 /* Stop uarts */
434 if (IS_SMC(pinfo)) {
435 volatile smc_t *smcp = pinfo->smcp;
436 smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
437 smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
438 } else {
439 volatile scc_t *sccp = pinfo->sccp;
440 sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
441 sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
442 }
443
444 /* Shut them really down and reinit buffer descriptors */
445 cpm_line_cr_cmd(line, CPM_CR_STOP_TX);
446 cpm_uart_initbd(pinfo);
447 }
448}
449
450static void cpm_uart_set_termios(struct uart_port *port,
451 struct termios *termios, struct termios *old)
452{
453 int baud;
454 unsigned long flags;
455 u16 cval, scval, prev_mode;
456 int bits, sbits;
457 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
458 volatile smc_t *smcp = pinfo->smcp;
459 volatile scc_t *sccp = pinfo->sccp;
460
461 pr_debug("CPM uart[%d]:set_termios\n", port->line);
462
463 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
464
465 /* Character length programmed into the mode register is the
466 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
467 * 1 or 2 stop bits, minus 1.
468 * The value 'bits' counts this for us.
469 */
470 cval = 0;
471 scval = 0;
472
473 /* byte size */
474 switch (termios->c_cflag & CSIZE) {
475 case CS5:
476 bits = 5;
477 break;
478 case CS6:
479 bits = 6;
480 break;
481 case CS7:
482 bits = 7;
483 break;
484 case CS8:
485 bits = 8;
486 break;
487 /* Never happens, but GCC is too dumb to figure it out */
488 default:
489 bits = 8;
490 break;
491 }
492 sbits = bits - 5;
493
494 if (termios->c_cflag & CSTOPB) {
495 cval |= SMCMR_SL; /* Two stops */
496 scval |= SCU_PSMR_SL;
497 bits++;
498 }
499
500 if (termios->c_cflag & PARENB) {
501 cval |= SMCMR_PEN;
502 scval |= SCU_PSMR_PEN;
503 bits++;
504 if (!(termios->c_cflag & PARODD)) {
505 cval |= SMCMR_PM_EVEN;
506 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
507 }
508 }
509
510 /*
511 * Set up parity check flag
512 */
513#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
514
515 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
516 if (termios->c_iflag & INPCK)
517 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
518 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
519 port->read_status_mask |= BD_SC_BR;
520
521 /*
522 * Characters to ignore
523 */
524 port->ignore_status_mask = 0;
525 if (termios->c_iflag & IGNPAR)
526 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
527 if (termios->c_iflag & IGNBRK) {
528 port->ignore_status_mask |= BD_SC_BR;
529 /*
530 * If we're ignore parity and break indicators, ignore
531 * overruns too. (For real raw support).
532 */
533 if (termios->c_iflag & IGNPAR)
534 port->ignore_status_mask |= BD_SC_OV;
535 }
536 /*
537 * !!! ignore all characters if CREAD is not set
538 */
539 if ((termios->c_cflag & CREAD) == 0)
540 port->read_status_mask &= ~BD_SC_EMPTY;
311c4627 541
1da177e4
LT		 542 spin_lock_irqsave(&port->lock, flags);
543
544 /* Start bit has not been added (so don't, because we would just
545 * subtract it later), and we need to add one for the number of
546 * stops bits (there is always at least one).
547 */
548 bits++;
549 if (IS_SMC(pinfo)) {
550 /* Set the mode register. We want to keep a copy of the
551 * enables, because we want to put them back if they were
552 * present.
553 */
554 prev_mode = smcp->smc_smcmr;
555 smcp->smc_smcmr = smcr_mk_clen(bits) | cval | SMCMR_SM_UART;
556 smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN));
557 } else {
558 sccp->scc_psmr = (sbits << 12) | scval;
559 }
560
561 cpm_set_brg(pinfo->brg - 1, baud);
562 spin_unlock_irqrestore(&port->lock, flags);
563
564}
565
566static const char *cpm_uart_type(struct uart_port *port)
567{
568 pr_debug("CPM uart[%d]:uart_type\n", port->line);
569
570 return port->type == PORT_CPM ? "CPM UART" : NULL;
571}
572
573/*
574 * verify the new serial_struct (for TIOCSSERIAL).
575 */
576static int cpm_uart_verify_port(struct uart_port *port,
577 struct serial_struct *ser)
578{
579 int ret = 0;
580
581 pr_debug("CPM uart[%d]:verify_port\n", port->line);
582
583 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
584 ret = -EINVAL;
585 if (ser->irq < 0 || ser->irq >= NR_IRQS)
586 ret = -EINVAL;
587 if (ser->baud_base < 9600)
588 ret = -EINVAL;
589 return ret;
590}
591
592/*
593 * Transmit characters, refill buffer descriptor, if possible
594 */
595static int cpm_uart_tx_pump(struct uart_port *port)
596{
597 volatile cbd_t *bdp;
598 unsigned char *p;
599 int count;
600 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
601 struct circ_buf *xmit = &port->info->xmit;
602
603 /* Handle xon/xoff */
604 if (port->x_char) {
605 /* Pick next descriptor and fill from buffer */
606 bdp = pinfo->tx_cur;
607
311c4627
KG		 608 p = cpm2cpu_addr(bdp->cbd_bufaddr);
609
1da177e4
LT		 610 *p++ = xmit->buf[xmit->tail];
611 bdp->cbd_datlen = 1;
612 bdp->cbd_sc |= BD_SC_READY;
613 /* Get next BD. */
614 if (bdp->cbd_sc & BD_SC_WRAP)
615 bdp = pinfo->tx_bd_base;
616 else
617 bdp++;
618 pinfo->tx_cur = bdp;
619
620 port->icount.tx++;
621 port->x_char = 0;
622 return 1;
623 }
624
625 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
b129a8cc 626 cpm_uart_stop_tx(port);
1da177e4
LT		 627 return 0;
628 }
629
630 /* Pick next descriptor and fill from buffer */
631 bdp = pinfo->tx_cur;
632
633 while (!(bdp->cbd_sc & BD_SC_READY) && (xmit->tail != xmit->head)) {
634 count = 0;
311c4627 635 p = cpm2cpu_addr(bdp->cbd_bufaddr);
1da177e4
LT		 636 while (count < pinfo->tx_fifosize) {
637 *p++ = xmit->buf[xmit->tail];
638 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
639 port->icount.tx++;
640 count++;
641 if (xmit->head == xmit->tail)
642 break;
643 }
644 bdp->cbd_datlen = count;
645 bdp->cbd_sc |= BD_SC_READY;
311c4627 646 __asm__("eieio");
1da177e4
LT		 647 /* Get next BD. */
648 if (bdp->cbd_sc & BD_SC_WRAP)
649 bdp = pinfo->tx_bd_base;
650 else
651 bdp++;
652 }
653 pinfo->tx_cur = bdp;
654
655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(port);
657
658 if (uart_circ_empty(xmit)) {
b129a8cc 659 cpm_uart_stop_tx(port);
1da177e4
LT		 660 return 0;
661 }
662
663 return 1;
664}
665
666/*
667 * init buffer descriptors
668 */
669static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
670{
671 int i;
672 u8 *mem_addr;
673 volatile cbd_t *bdp;
674
675 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
676
677 /* Set the physical address of the host memory
678 * buffers in the buffer descriptors, and the
679 * virtual address for us to work with.
680 */
681 mem_addr = pinfo->mem_addr;
682 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
683 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
311c4627 684 bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr);
1da177e4
LT		 685 bdp->cbd_sc = BD_SC_EMPTY | BD_SC_INTRPT;
686 mem_addr += pinfo->rx_fifosize;
687 }
311c4627
KG		 688
689 bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr);
1da177e4
LT		 690 bdp->cbd_sc = BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT;
691
692 /* Set the physical address of the host memory
693 * buffers in the buffer descriptors, and the
694 * virtual address for us to work with.
695 */
696 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
697 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
698 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
311c4627 699 bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr);
1da177e4
LT		 700 bdp->cbd_sc = BD_SC_INTRPT;
701 mem_addr += pinfo->tx_fifosize;
702 }
311c4627
KG		 703
704 bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr);
1da177e4
LT		 705 bdp->cbd_sc = BD_SC_WRAP | BD_SC_INTRPT;
706}
707
708static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
709{
710 int line = pinfo - cpm_uart_ports;
711 volatile scc_t *scp;
712 volatile scc_uart_t *sup;
713
714 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
715
716 scp = pinfo->sccp;
717 sup = pinfo->sccup;
718
719 /* Store address */
720 pinfo->sccup->scc_genscc.scc_rbase = (unsigned char *)pinfo->rx_bd_base - DPRAM_BASE;
721 pinfo->sccup->scc_genscc.scc_tbase = (unsigned char *)pinfo->tx_bd_base - DPRAM_BASE;
722
723 /* Set up the uart parameters in the
724 * parameter ram.
725 */
726
727 cpm_set_scc_fcr(sup);
728
729 sup->scc_genscc.scc_mrblr = pinfo->rx_fifosize;
730 sup->scc_maxidl = pinfo->rx_fifosize;
731 sup->scc_brkcr = 1;
732 sup->scc_parec = 0;
733 sup->scc_frmec = 0;
734 sup->scc_nosec = 0;
735 sup->scc_brkec = 0;
736 sup->scc_uaddr1 = 0;
737 sup->scc_uaddr2 = 0;
738 sup->scc_toseq = 0;
739 sup->scc_char1 = 0x8000;
740 sup->scc_char2 = 0x8000;
741 sup->scc_char3 = 0x8000;
742 sup->scc_char4 = 0x8000;
743 sup->scc_char5 = 0x8000;
744 sup->scc_char6 = 0x8000;
745 sup->scc_char7 = 0x8000;
746 sup->scc_char8 = 0x8000;
747 sup->scc_rccm = 0xc0ff;
748
749 /* Send the CPM an initialize command.
750 */
751 cpm_line_cr_cmd(line, CPM_CR_INIT_TRX);
752
753 /* Set UART mode, 8 bit, no parity, one stop.
754 * Enable receive and transmit.
755 */
756 scp->scc_gsmrh = 0;
757 scp->scc_gsmrl =
758 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
759
760 /* Enable rx interrupts and clear all pending events. */
761 scp->scc_sccm = 0;
762 scp->scc_scce = 0xffff;
763 scp->scc_dsr = 0x7e7e;
764 scp->scc_psmr = 0x3000;
765
766 scp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
767}
768
769static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
770{
771 int line = pinfo - cpm_uart_ports;
772 volatile smc_t *sp;
773 volatile smc_uart_t *up;
774
775 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
776
777 sp = pinfo->smcp;
778 up = pinfo->smcup;
779
780 /* Store address */
781 pinfo->smcup->smc_rbase = (u_char *)pinfo->rx_bd_base - DPRAM_BASE;
782 pinfo->smcup->smc_tbase = (u_char *)pinfo->tx_bd_base - DPRAM_BASE;
783
784/*
785 * In case SMC1 is being relocated...
786 */
787#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
788 up->smc_rbptr = pinfo->smcup->smc_rbase;
789 up->smc_tbptr = pinfo->smcup->smc_tbase;
790 up->smc_rstate = 0;
791 up->smc_tstate = 0;
792 up->smc_brkcr = 1; /* number of break chars */
793 up->smc_brkec = 0;
794#endif
795
796 /* Set up the uart parameters in the
797 * parameter ram.
798 */
799 cpm_set_smc_fcr(up);
800
801 /* Using idle charater time requires some additional tuning. */
802 up->smc_mrblr = pinfo->rx_fifosize;
803 up->smc_maxidl = pinfo->rx_fifosize;
311c4627
KG		 804 up->smc_brklen = 0;
805 up->smc_brkec = 0;
1da177e4
LT		 806 up->smc_brkcr = 1;
807
808 cpm_line_cr_cmd(line, CPM_CR_INIT_TRX);
809
810 /* Set UART mode, 8 bit, no parity, one stop.
811 * Enable receive and transmit.
812 */
813 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
814
815 /* Enable only rx interrupts clear all pending events. */
816 sp->smc_smcm = 0;
817 sp->smc_smce = 0xff;
818
819 sp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN);
820}
821
822/*
823 * Initialize port. This is called from early_console stuff
824 * so we have to be careful here !
825 */
826static int cpm_uart_request_port(struct uart_port *port)
827{
828 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
829 int ret;
830
831 pr_debug("CPM uart[%d]:request port\n", port->line);
832
833 if (pinfo->flags & FLAG_CONSOLE)
834 return 0;
835
836 /*
837 * Setup any port IO, connect any baud rate generators,
838 * etc. This is expected to be handled by board
311c4627 839 * dependant code
1da177e4
LT		 840 */
841 if (pinfo->set_lineif)
842 pinfo->set_lineif(pinfo);
843
844 if (IS_SMC(pinfo)) {
845 pinfo->smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
846 pinfo->smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
847 } else {
848 pinfo->sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
849 pinfo->sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
850 }
851
852 ret = cpm_uart_allocbuf(pinfo, 0);
853
854 if (ret)
855 return ret;
856
857 cpm_uart_initbd(pinfo);
311c4627
KG		 858 if (IS_SMC(pinfo))
859 cpm_uart_init_smc(pinfo);
860 else
861 cpm_uart_init_scc(pinfo);
1da177e4
LT		 862
863 return 0;
864}
865
866static void cpm_uart_release_port(struct uart_port *port)
867{
868 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
869
870 if (!(pinfo->flags & FLAG_CONSOLE))
871 cpm_uart_freebuf(pinfo);
872}
873
874/*
875 * Configure/autoconfigure the port.
876 */
877static void cpm_uart_config_port(struct uart_port *port, int flags)
878{
879 pr_debug("CPM uart[%d]:config_port\n", port->line);
880
881 if (flags & UART_CONFIG_TYPE) {
882 port->type = PORT_CPM;
883 cpm_uart_request_port(port);
884 }
885}
886static struct uart_ops cpm_uart_pops = {
887 .tx_empty = cpm_uart_tx_empty,
888 .set_mctrl = cpm_uart_set_mctrl,
889 .get_mctrl = cpm_uart_get_mctrl,
890 .stop_tx = cpm_uart_stop_tx,
891 .start_tx = cpm_uart_start_tx,
892 .stop_rx = cpm_uart_stop_rx,
893 .enable_ms = cpm_uart_enable_ms,
894 .break_ctl = cpm_uart_break_ctl,
895 .startup = cpm_uart_startup,
896 .shutdown = cpm_uart_shutdown,
897 .set_termios = cpm_uart_set_termios,
898 .type = cpm_uart_type,
899 .release_port = cpm_uart_release_port,
900 .request_port = cpm_uart_request_port,
901 .config_port = cpm_uart_config_port,
902 .verify_port = cpm_uart_verify_port,
903};
904
905struct uart_cpm_port cpm_uart_ports[UART_NR] = {
906 [UART_SMC1] = {
907 .port = {
908 .irq = SMC1_IRQ,
909 .ops = &cpm_uart_pops,
910 .iotype = SERIAL_IO_MEM,
911 .lock = SPIN_LOCK_UNLOCKED,
912 },
913 .flags = FLAG_SMC,
914 .tx_nrfifos = TX_NUM_FIFO,
915 .tx_fifosize = TX_BUF_SIZE,
311c4627 916 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 917 .rx_fifosize = RX_BUF_SIZE,
918 .set_lineif = smc1_lineif,
919 },
920 [UART_SMC2] = {
921 .port = {
922 .irq = SMC2_IRQ,
923 .ops = &cpm_uart_pops,
924 .iotype = SERIAL_IO_MEM,
925 .lock = SPIN_LOCK_UNLOCKED,
926 },
927 .flags = FLAG_SMC,
928 .tx_nrfifos = TX_NUM_FIFO,
929 .tx_fifosize = TX_BUF_SIZE,
311c4627 930 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 931 .rx_fifosize = RX_BUF_SIZE,
932 .set_lineif = smc2_lineif,
933#ifdef CONFIG_SERIAL_CPM_ALT_SMC2
934 .is_portb = 1,
935#endif
936 },
937 [UART_SCC1] = {
938 .port = {
939 .irq = SCC1_IRQ,
940 .ops = &cpm_uart_pops,
941 .iotype = SERIAL_IO_MEM,
942 .lock = SPIN_LOCK_UNLOCKED,
943 },
944 .tx_nrfifos = TX_NUM_FIFO,
945 .tx_fifosize = TX_BUF_SIZE,
311c4627 946 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 947 .rx_fifosize = RX_BUF_SIZE,
948 .set_lineif = scc1_lineif,
311c4627 949 .wait_closing = SCC_WAIT_CLOSING,
1da177e4
LT		 950 },
951 [UART_SCC2] = {
952 .port = {
953 .irq = SCC2_IRQ,
954 .ops = &cpm_uart_pops,
955 .iotype = SERIAL_IO_MEM,
956 .lock = SPIN_LOCK_UNLOCKED,
957 },
958 .tx_nrfifos = TX_NUM_FIFO,
959 .tx_fifosize = TX_BUF_SIZE,
311c4627 960 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 961 .rx_fifosize = RX_BUF_SIZE,
962 .set_lineif = scc2_lineif,
311c4627 963 .wait_closing = SCC_WAIT_CLOSING,
1da177e4
LT		 964 },
965 [UART_SCC3] = {
966 .port = {
967 .irq = SCC3_IRQ,
968 .ops = &cpm_uart_pops,
969 .iotype = SERIAL_IO_MEM,
970 .lock = SPIN_LOCK_UNLOCKED,
971 },
972 .tx_nrfifos = TX_NUM_FIFO,
973 .tx_fifosize = TX_BUF_SIZE,
311c4627 974 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 975 .rx_fifosize = RX_BUF_SIZE,
976 .set_lineif = scc3_lineif,
311c4627 977 .wait_closing = SCC_WAIT_CLOSING,
1da177e4
LT		 978 },
979 [UART_SCC4] = {
980 .port = {
981 .irq = SCC4_IRQ,
982 .ops = &cpm_uart_pops,
983 .iotype = SERIAL_IO_MEM,
984 .lock = SPIN_LOCK_UNLOCKED,
985 },
986 .tx_nrfifos = TX_NUM_FIFO,
987 .tx_fifosize = TX_BUF_SIZE,
311c4627 988 .rx_nrfifos = RX_NUM_FIFO,
1da177e4
LT		 989 .rx_fifosize = RX_BUF_SIZE,
990 .set_lineif = scc4_lineif,
311c4627 991 .wait_closing = SCC_WAIT_CLOSING,
1da177e4
LT		 992 },
993};
994
995#ifdef CONFIG_SERIAL_CPM_CONSOLE
996/*
997 * Print a string to the serial port trying not to disturb
998 * any possible real use of the port...
999 *
1000 * Note that this is called with interrupts already disabled
1001 */
1002static void cpm_uart_console_write(struct console *co, const char *s,
1003 u_int count)
1004{
1005 struct uart_cpm_port *pinfo =
1006 &cpm_uart_ports[cpm_uart_port_map[co->index]];
1007 unsigned int i;
1008 volatile cbd_t *bdp, *bdbase;
1009 volatile unsigned char *cp;
1010
1011 /* Get the address of the host memory buffer.
1012 */
1013 bdp = pinfo->tx_cur;
1014 bdbase = pinfo->tx_bd_base;
1015
1016 /*
1017 * Now, do each character. This is not as bad as it looks
1018 * since this is a holding FIFO and not a transmitting FIFO.
1019 * We could add the complexity of filling the entire transmit
1020 * buffer, but we would just wait longer between accesses......
1021 */
1022 for (i = 0; i < count; i++, s++) {
1023 /* Wait for transmitter fifo to empty.
1024 * Ready indicates output is ready, and xmt is doing
1025 * that, not that it is ready for us to send.
1026 */
1027 while ((bdp->cbd_sc & BD_SC_READY) != 0)
1028 ;
1029
1030 /* Send the character out.
1031 * If the buffer address is in the CPM DPRAM, don't
1032 * convert it.
1033 */
311c4627
KG		 1034 cp = cpm2cpu_addr(bdp->cbd_bufaddr);
1035
1da177e4
LT		 1036 *cp = *s;
1037
1038 bdp->cbd_datlen = 1;
1039 bdp->cbd_sc |= BD_SC_READY;
1040
1041 if (bdp->cbd_sc & BD_SC_WRAP)
1042 bdp = bdbase;
1043 else
1044 bdp++;
1045
1046 /* if a LF, also do CR... */
1047 if (*s == 10) {
1048 while ((bdp->cbd_sc & BD_SC_READY) != 0)
1049 ;
1050
311c4627 1051 cp = cpm2cpu_addr(bdp->cbd_bufaddr);
1da177e4
LT		 1052
1053 *cp = 13;
1054 bdp->cbd_datlen = 1;
1055 bdp->cbd_sc |= BD_SC_READY;
1056
1057 if (bdp->cbd_sc & BD_SC_WRAP)
1058 bdp = bdbase;
1059 else
1060 bdp++;
1061 }
1062 }
1063
1064 /*
1065 * Finally, Wait for transmitter & holding register to empty
1066 * and restore the IER
1067 */
1068 while ((bdp->cbd_sc & BD_SC_READY) != 0)
1069 ;
1070
1071 pinfo->tx_cur = (volatile cbd_t *) bdp;
1072}
1073
1074/*
1075 * Setup console. Be careful is called early !
1076 */
1077static int __init cpm_uart_console_setup(struct console *co, char *options)
1078{
1079 struct uart_port *port;
1080 struct uart_cpm_port *pinfo;
1081 int baud = 38400;
1082 int bits = 8;
1083 int parity = 'n';
1084 int flow = 'n';
1085 int ret;
1086
1087 port =
1088 (struct uart_port *)&cpm_uart_ports[cpm_uart_port_map[co->index]];
1089 pinfo = (struct uart_cpm_port *)port;
311c4627 1090
1da177e4
LT		 1091 pinfo->flags |= FLAG_CONSOLE;
1092
1093 if (options) {
1094 uart_parse_options(options, &baud, &parity, &bits, &flow);
1095 } else {
1096 bd_t *bd = (bd_t *) __res;
1097
1098 if (bd->bi_baudrate)
1099 baud = bd->bi_baudrate;
1100 else
1101 baud = 9600;
1102 }
1103
1104 /*
1105 * Setup any port IO, connect any baud rate generators,
1106 * etc. This is expected to be handled by board
311c4627 1107 * dependant code
1da177e4
LT		 1108 */
1109 if (pinfo->set_lineif)
1110 pinfo->set_lineif(pinfo);
1111
1112 if (IS_SMC(pinfo)) {
1113 pinfo->smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
1114 pinfo->smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
1115 } else {
1116 pinfo->sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
1117 pinfo->sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1118 }
1119
1120 ret = cpm_uart_allocbuf(pinfo, 1);
1121
1122 if (ret)
1123 return ret;
1124
1125 cpm_uart_initbd(pinfo);
1126
1127 if (IS_SMC(pinfo))
1128 cpm_uart_init_smc(pinfo);
1129 else
1130 cpm_uart_init_scc(pinfo);
1131
1132 uart_set_options(port, co, baud, parity, bits, flow);
1133
1134 return 0;
1135}
1136
36d2f5a1 1137static struct uart_driver cpm_reg;
1da177e4 1138static struct console cpm_scc_uart_console = {
36d2f5a1
KG		 1139 .name = "ttyCPM",
1140 .write = cpm_uart_console_write,
1141 .device = uart_console_device,
1142 .setup = cpm_uart_console_setup,
1143 .flags = CON_PRINTBUFFER,
1144 .index = -1,
1da177e4
LT		 1145 .data = &cpm_reg,
1146};
1147
1148int __init cpm_uart_console_init(void)
1149{
1150 int ret = cpm_uart_init_portdesc();
1151
1152 if (!ret)
1153 register_console(&cpm_scc_uart_console);
1154 return ret;
1155}
1156
1157console_initcall(cpm_uart_console_init);
1158
1159#define CPM_UART_CONSOLE &cpm_scc_uart_console
1160#else
1161#define CPM_UART_CONSOLE NULL
1162#endif
1163
1164static struct uart_driver cpm_reg = {
1165 .owner = THIS_MODULE,
1166 .driver_name = "ttyCPM",
1167 .dev_name = "ttyCPM",
1168 .major = SERIAL_CPM_MAJOR,
1169 .minor = SERIAL_CPM_MINOR,
1170 .cons = CPM_UART_CONSOLE,
1171};
1172
1173static int __init cpm_uart_init(void)
1174{
1175 int ret, i;
1176
1177 printk(KERN_INFO "Serial: CPM driver $Revision: 0.01 $\n");
1178
1179#ifndef CONFIG_SERIAL_CPM_CONSOLE
1180 ret = cpm_uart_init_portdesc();
1181 if (ret)
1182 return ret;
1183#endif
1184
1185 cpm_reg.nr = cpm_uart_nr;
1186 ret = uart_register_driver(&cpm_reg);
1187
1188 if (ret)
1189 return ret;
1190
1191 for (i = 0; i < cpm_uart_nr; i++) {
1192 int con = cpm_uart_port_map[i];
1193 cpm_uart_ports[con].port.line = i;
1194 cpm_uart_ports[con].port.flags = UPF_BOOT_AUTOCONF;
1195 uart_add_one_port(&cpm_reg, &cpm_uart_ports[con].port);
1196 }
1197
1198 return ret;
1199}
1200
1201static void __exit cpm_uart_exit(void)
1202{
1203 int i;
1204
1205 for (i = 0; i < cpm_uart_nr; i++) {
1206 int con = cpm_uart_port_map[i];
1207 uart_remove_one_port(&cpm_reg, &cpm_uart_ports[con].port);
1208 }
1209
1210 uart_unregister_driver(&cpm_reg);
1211}
1212
1213module_init(cpm_uart_init);
1214module_exit(cpm_uart_exit);
1215
1216MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1217MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1218MODULE_LICENSE("GPL");
1219MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
Linux 6.x block layer and io_uring tree(s)