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serial: fit blackfin uart over sport driver into common uart infrastructure
[linux-2.6-block.git] / drivers / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
31#include <linux/platform_device.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_core.h>
35
36#include <asm/delay.h>
37#include <asm/portmux.h>
38
39#include "bfin_sport_uart.h"
40
ccf68e59 41#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2f351741
BW		 42unsigned short bfin_uart_pin_req_sport0[] =
43 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
44 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
ccf68e59 45#endif
46#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2f351741
BW		 47unsigned short bfin_uart_pin_req_sport1[] =
48 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
49 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
ccf68e59 50#endif
51#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
52unsigned short bfin_uart_pin_req_sport2[] =
53 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \
54 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0};
55#endif
56#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
57unsigned short bfin_uart_pin_req_sport3[] =
58 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \
59 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0};
60#endif
2f351741
BW		 61
62struct sport_uart_port {
63 struct uart_port port;
2f351741 64 int err_irq;
ccf68e59 65 unsigned short csize;
66 unsigned short rxmask;
67 unsigned short txmask1;
68 unsigned short txmask2;
69 unsigned char stopb;
70/* unsigned char parib; */
2f351741
BW		 71};
72
73static void sport_uart_tx_chars(struct sport_uart_port *up);
74static void sport_stop_tx(struct uart_port *port);
75
76static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
77{
ccf68e59 78 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
79 up->txmask1, up->txmask2);
80
81 /* Place Start and Stop bits */
4328e3e5 82 __asm__ __volatile__ (
ccf68e59 83 "%[val] <<= 1;"
84 "%[val] = %[val] & %[mask1];"
85 "%[val] = %[val] | %[mask2];"
86 : [val]"+d"(value)
87 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
88 : "ASTAT"
4328e3e5 89 );
6ef53066 90 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 91
92 SPORT_PUT_TX(up, value);
93}
94
ccf68e59 95static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 96{
ccf68e59 97 unsigned int value;
98 unsigned char extract;
4328e3e5 99 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 100
ccf68e59 101 if ((up->csize + up->stopb) > 7)
102 value = SPORT_GET_RX32(up);
103 else
104 value = SPORT_GET_RX(up);
105
106 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
107 up->csize, up->rxmask);
2f351741 108
ccf68e59 109 /* Extract data */
4328e3e5
MF		 110 __asm__ __volatile__ (
111 "%[extr] = 0;"
ccf68e59 112 "%[mask1] = %[rxmask];"
113 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 114 "%[shift] = 0;"
115 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
116 ".Lloop_s:"
117 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
118 "%[tmp] <<= %[shift];"
119 "%[extr] = %[extr] | %[tmp];"
120 "%[mask1] = %[mask1] - %[mask2];"
121 ".Lloop_e:"
122 "%[shift] += 1;"
ccf68e59 123 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
124 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
125 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 126 : "ASTAT", "LB0", "LC0", "LT0"
127 );
2f351741
BW		 128
129 pr_debug(" extract:%x\n", extract);
130 return extract;
131}
132
ccf68e59 133static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 134{
ccf68e59 135 int tclkdiv, rclkdiv;
136 unsigned int sclk = get_sclk();
2f351741 137
ccf68e59 138 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
139 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
140 SPORT_PUT_TCR2(up, size + 1);
6ef53066 141 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 142
143 /* Set RCR1 and RCR2 */
144 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 145 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 146 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 147
ccf68e59 148 tclkdiv = sclk / (2 * baud_rate) - 1;
149 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
2f351741 150 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 151 SPORT_PUT_RCLKDIV(up, rclkdiv);
152 SSYNC();
ccf68e59 153 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
154 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 155
156 return 0;
157}
158
159static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
160{
161 struct sport_uart_port *up = dev_id;
ebd2c8f6 162 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 163 unsigned int ch;
164
ccf68e59 165 spin_lock(&up->port.lock);
166
167 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 168 ch = rx_one_byte(up);
169 up->port.icount.rx++;
170
ccf68e59 171 if (!uart_handle_sysrq_char(&up->port, ch))
2f351741 172 tty_insert_flip_char(tty, ch, TTY_NORMAL);
ccf68e59 173 }
2f351741
BW		 174 tty_flip_buffer_push(tty);
175
ccf68e59 176 spin_unlock(&up->port.lock);
177
2f351741
BW		 178 return IRQ_HANDLED;
179}
180
181static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
182{
ccf68e59 183 struct sport_uart_port *up = dev_id;
184
185 spin_lock(&up->port.lock);
186 sport_uart_tx_chars(up);
187 spin_unlock(&up->port.lock);
2f351741
BW		 188
189 return IRQ_HANDLED;
190}
191
192static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
193{
194 struct sport_uart_port *up = dev_id;
ebd2c8f6 195 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 196 unsigned int stat = SPORT_GET_STAT(up);
197
ccf68e59 198 spin_lock(&up->port.lock);
199
2f351741
BW		 200 /* Overflow in RX FIFO */
201 if (stat & ROVF) {
202 up->port.icount.overrun++;
203 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
204 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
205 }
206 /* These should not happen */
207 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 208 pr_err("SPORT Error:%s %s %s\n",
209 (stat & TOVF) ? "TX overflow" : "",
210 (stat & TUVF) ? "TX underflow" : "",
211 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 212 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
213 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
214 }
215 SSYNC();
216
ccf68e59 217 spin_unlock(&up->port.lock);
2f351741
BW		 218 return IRQ_HANDLED;
219}
220
221/* Reqeust IRQ, Setup clock */
222static int sport_startup(struct uart_port *port)
223{
224 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 225 int ret;
2f351741 226
6ef53066 227 pr_debug("%s enter\n", __func__);
ccf68e59 228 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
229 "SPORT_UART_RX", up);
230 if (ret) {
231 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
232 return ret;
2f351741
BW		 233 }
234
ccf68e59 235 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
236 "SPORT_UART_TX", up);
237 if (ret) {
238 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 239 goto fail1;
240 }
241
ccf68e59 242 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
243 "SPORT_UART_STATUS", up);
244 if (ret) {
245 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 246 goto fail2;
247 }
248
2f351741 249 return 0;
ccf68e59 250 fail2:
251 free_irq(up->port.irq+1, up);
252 fail1:
253 free_irq(up->port.irq, up);
2f351741 254
ccf68e59 255 return ret;
2f351741
BW		 256}
257
258static void sport_uart_tx_chars(struct sport_uart_port *up)
259{
ebd2c8f6 260 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 261
262 if (SPORT_GET_STAT(up) & TXF)
263 return;
264
265 if (up->port.x_char) {
266 tx_one_byte(up, up->port.x_char);
267 up->port.icount.tx++;
268 up->port.x_char = 0;
269 return;
270 }
271
272 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
273 sport_stop_tx(&up->port);
274 return;
275 }
276
277 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
278 tx_one_byte(up, xmit->buf[xmit->tail]);
279 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
280 up->port.icount.tx++;
281 }
282
283 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
284 uart_write_wakeup(&up->port);
285}
286
287static unsigned int sport_tx_empty(struct uart_port *port)
288{
289 struct sport_uart_port *up = (struct sport_uart_port *)port;
290 unsigned int stat;
291
292 stat = SPORT_GET_STAT(up);
6ef53066 293 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 294 if (stat & TXHRE) {
295 return TIOCSER_TEMT;
296 } else
297 return 0;
298}
299
300static unsigned int sport_get_mctrl(struct uart_port *port)
301{
6ef53066 302 pr_debug("%s enter\n", __func__);
2f351741
BW		 303 return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
304}
305
306static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
307{
6ef53066 308 pr_debug("%s enter\n", __func__);
2f351741
BW		 309}
310
311static void sport_stop_tx(struct uart_port *port)
312{
313 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 314
6ef53066 315 pr_debug("%s enter\n", __func__);
2f351741 316
2f351741 317 /* Although the hold register is empty, last byte is still in shift
ccf68e59 318 * register and not sent out yet. So, put a dummy data into TX FIFO.
319 * Then, sport tx stops when last byte is shift out and the dummy
320 * data is moved into the shift register.
321 */
322 SPORT_PUT_TX(up, 0xffff);
323 while (!(SPORT_GET_STAT(up) & TXHRE))
324 cpu_relax();
2f351741
BW		 325
326 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
327 SSYNC();
328
329 return;
330}
331
332static void sport_start_tx(struct uart_port *port)
333{
334 struct sport_uart_port *up = (struct sport_uart_port *)port;
335
6ef53066 336 pr_debug("%s enter\n", __func__);
ccf68e59 337
2f351741
BW		 338 /* Write data into SPORT FIFO before enable SPROT to transmit */
339 sport_uart_tx_chars(up);
340
341 /* Enable transmit, then an interrupt will generated */
342 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
343 SSYNC();
6ef53066 344 pr_debug("%s exit\n", __func__);
2f351741
BW		 345}
346
347static void sport_stop_rx(struct uart_port *port)
348{
349 struct sport_uart_port *up = (struct sport_uart_port *)port;
350
6ef53066 351 pr_debug("%s enter\n", __func__);
2f351741
BW		 352 /* Disable sport to stop rx */
353 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
354 SSYNC();
355}
356
357static void sport_enable_ms(struct uart_port *port)
358{
6ef53066 359 pr_debug("%s enter\n", __func__);
2f351741
BW		 360}
361
362static void sport_break_ctl(struct uart_port *port, int break_state)
363{
6ef53066 364 pr_debug("%s enter\n", __func__);
2f351741
BW		 365}
366
367static void sport_shutdown(struct uart_port *port)
368{
369 struct sport_uart_port *up = (struct sport_uart_port *)port;
370
ccf68e59 371 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 372
373 /* Disable sport */
374 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
375 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
376 SSYNC();
377
ccf68e59 378 free_irq(up->port.irq, up);
379 free_irq(up->port.irq+1, up);
2f351741
BW		 380 free_irq(up->err_irq, up);
381}
382
2f351741
BW		 383static const char *sport_type(struct uart_port *port)
384{
385 struct sport_uart_port *up = (struct sport_uart_port *)port;
386
6ef53066 387 pr_debug("%s enter\n", __func__);
ccf68e59 388 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 389}
390
391static void sport_release_port(struct uart_port *port)
392{
6ef53066 393 pr_debug("%s enter\n", __func__);
2f351741
BW		 394}
395
396static int sport_request_port(struct uart_port *port)
397{
6ef53066 398 pr_debug("%s enter\n", __func__);
2f351741
BW		 399 return 0;
400}
401
402static void sport_config_port(struct uart_port *port, int flags)
403{
404 struct sport_uart_port *up = (struct sport_uart_port *)port;
405
6ef53066 406 pr_debug("%s enter\n", __func__);
2f351741
BW		 407 up->port.type = PORT_BFIN_SPORT;
408}
409
410static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
411{
6ef53066 412 pr_debug("%s enter\n", __func__);
2f351741
BW		 413 return 0;
414}
415
ccf68e59 416static void sport_set_termios(struct uart_port *port,
417 struct ktermios *termios, struct ktermios *old)
418{
419 struct sport_uart_port *up = (struct sport_uart_port *)port;
420 unsigned long flags;
421 int i;
422
423 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
424
425 switch (termios->c_cflag & CSIZE) {
426 case CS8:
427 up->csize = 8;
428 break;
429 case CS7:
430 up->csize = 7;
431 break;
432 case CS6:
433 up->csize = 6;
434 break;
435 case CS5:
436 up->csize = 5;
437 break;
438 default:
439 pr_warning("requested word length not supported\n");
440 }
441
442 if (termios->c_cflag & CSTOPB) {
443 up->stopb = 1;
444 }
445 if (termios->c_cflag & PARENB) {
446 pr_warning("PAREN bits is not supported yet\n");
447 /* up->parib = 1; */
448 }
449
450 port->read_status_mask = OE;
451 if (termios->c_iflag & INPCK)
452 port->read_status_mask |= (FE | PE);
453 if (termios->c_iflag & (BRKINT | PARMRK))
454 port->read_status_mask |= BI;
455
456 /*
457 * Characters to ignore
458 */
459 port->ignore_status_mask = 0;
460 if (termios->c_iflag & IGNPAR)
461 port->ignore_status_mask |= FE | PE;
462 if (termios->c_iflag & IGNBRK) {
463 port->ignore_status_mask |= BI;
464 /*
465 * If we're ignoring parity and break indicators,
466 * ignore overruns too (for real raw support).
467 */
468 if (termios->c_iflag & IGNPAR)
469 port->ignore_status_mask |= OE;
470 }
471
472 /* RX extract mask */
473 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
474 /* TX masks, 8 bit data and 1 bit stop for example:
475 * mask1 = b#0111111110
476 * mask2 = b#1000000000
477 */
478 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
479 up->txmask1 |= (1<<i);
480 up->txmask2 = (1<<i);
481 if (up->stopb) {
482 ++i;
483 up->txmask2 |= (1<<i);
484 }
485 up->txmask1 <<= 1;
486 up->txmask2 <<= 1;
487 /* uart baud rate */
488 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
489
490 spin_lock_irqsave(&up->port.lock, flags);
491
492 /* Disable UART */
493 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
494 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
495
496 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
497
498 /* driver TX line high after config, one dummy data is
499 * necessary to stop sport after shift one byte
500 */
501 SPORT_PUT_TX(up, 0xffff);
502 SPORT_PUT_TX(up, 0xffff);
503 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
504 SSYNC();
505 while (!(SPORT_GET_STAT(up) & TXHRE))
506 cpu_relax();
507 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
508 SSYNC();
509
510 /* Port speed changed, update the per-port timeout. */
511 uart_update_timeout(port, termios->c_cflag, port->uartclk);
512
513 /* Enable sport rx */
514 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
515 SSYNC();
516
517 spin_unlock_irqrestore(&up->port.lock, flags);
518}
519
2f351741
BW		 520struct uart_ops sport_uart_ops = {
521 .tx_empty = sport_tx_empty,
522 .set_mctrl = sport_set_mctrl,
523 .get_mctrl = sport_get_mctrl,
524 .stop_tx = sport_stop_tx,
525 .start_tx = sport_start_tx,
526 .stop_rx = sport_stop_rx,
527 .enable_ms = sport_enable_ms,
528 .break_ctl = sport_break_ctl,
529 .startup = sport_startup,
530 .shutdown = sport_shutdown,
531 .set_termios = sport_set_termios,
532 .type = sport_type,
533 .release_port = sport_release_port,
534 .request_port = sport_request_port,
535 .config_port = sport_config_port,
536 .verify_port = sport_verify_port,
537};
538
ccf68e59 539#define BFIN_SPORT_UART_MAX_PORTS 4
540
541static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
542
543#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
544static int __init
545sport_uart_console_setup(struct console *co, char *options)
546{
547 struct sport_uart_port *up;
548 int baud = 57600;
549 int bits = 8;
550 int parity = 'n';
551 int flow = 'n';
552
553 /* Check whether an invalid uart number has been specified */
554 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
555 return -ENODEV;
556
557 up = bfin_sport_uart_ports[co->index];
558 if (!up)
559 return -ENODEV;
560
561 if (options)
562 uart_parse_options(options, &baud, &parity, &bits, &flow);
563
564 return uart_set_options(&up->port, co, baud, parity, bits, flow);
565}
566
567static void sport_uart_console_putchar(struct uart_port *port, int ch)
568{
569 struct sport_uart_port *up = (struct sport_uart_port *)port;
570
571 while (SPORT_GET_STAT(up) & TXF)
572 barrier();
573
574 tx_one_byte(up, ch);
575}
576
577/*
578 * Interrupts are disabled on entering
579 */
580static void
581sport_uart_console_write(struct console *co, const char *s, unsigned int count)
582{
583 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
584 unsigned long flags;
585
586 spin_lock_irqsave(&up->port.lock, flags);
587
588 if (SPORT_GET_TCR1(up) & TSPEN)
589 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
590 else {
591 /* dummy data to start sport */
592 while (SPORT_GET_STAT(up) & TXF)
593 barrier();
594 SPORT_PUT_TX(up, 0xffff);
595 /* Enable transmit, then an interrupt will generated */
596 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
597 SSYNC();
598
599 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
600
601 /* Although the hold register is empty, last byte is still in shift
602 * register and not sent out yet. So, put a dummy data into TX FIFO.
603 * Then, sport tx stops when last byte is shift out and the dummy
604 * data is moved into the shift register.
605 */
606 while (SPORT_GET_STAT(up) & TXF)
607 barrier();
608 SPORT_PUT_TX(up, 0xffff);
609 while (!(SPORT_GET_STAT(up) & TXHRE))
610 barrier();
611
612 /* Stop sport tx transfer */
613 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
614 SSYNC();
2f351741 615 }
ccf68e59 616
617 spin_unlock_irqrestore(&up->port.lock, flags);
618}
619
620static struct uart_driver sport_uart_reg;
621
622static struct console sport_uart_console = {
623 .name = DEVICE_NAME,
624 .write = sport_uart_console_write,
625 .device = uart_console_device,
626 .setup = sport_uart_console_setup,
627 .flags = CON_PRINTBUFFER,
628 .index = -1,
629 .data = &sport_uart_reg,
2f351741
BW		 630};
631
ccf68e59 632#define SPORT_UART_CONSOLE (&sport_uart_console)
633#else
634#define SPORT_UART_CONSOLE NULL
635#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
636
637
2f351741
BW		 638static struct uart_driver sport_uart_reg = {
639 .owner = THIS_MODULE,
ccf68e59 640 .driver_name = DRV_NAME,
641 .dev_name = DEVICE_NAME,
2f351741
BW		 642 .major = 204,
643 .minor = 84,
ccf68e59 644 .nr = BFIN_SPORT_UART_MAX_PORTS,
645 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 646};
647
ccf68e59 648#ifdef CONFIG_PM
649static int sport_uart_suspend(struct device *dev)
2f351741 650{
ccf68e59 651 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 652
ccf68e59 653 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 654 if (sport)
655 uart_suspend_port(&sport_uart_reg, &sport->port);
656
657 return 0;
658}
659
ccf68e59 660static int sport_uart_resume(struct device *dev)
2f351741 661{
ccf68e59 662 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 663
ccf68e59 664 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 665 if (sport)
666 uart_resume_port(&sport_uart_reg, &sport->port);
667
668 return 0;
669}
670
ccf68e59 671static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
672 .suspend = sport_uart_suspend,
673 .resume = sport_uart_resume,
674};
675#endif
676
677static int __devinit sport_uart_probe(struct platform_device *pdev)
2f351741 678{
ccf68e59 679 struct resource *res;
680 struct sport_uart_port *sport;
681 int ret = 0;
2f351741 682
ccf68e59 683 dev_dbg(&pdev->dev, "%s enter\n", __func__);
684
685 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
686 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
687 return -ENOENT;
688 }
689
690 if (bfin_sport_uart_ports[pdev->id] == NULL) {
691 bfin_sport_uart_ports[pdev->id] =
692 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
693 sport = bfin_sport_uart_ports[pdev->id];
694 if (!sport) {
695 dev_err(&pdev->dev,
696 "Fail to kmalloc sport_uart_port\n");
697 return -ENOMEM;
698 }
699
700 ret = peripheral_request_list(
701 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
702 if (ret) {
703 dev_err(&pdev->dev,
704 "Fail to request SPORT peripherals\n");
705 goto out_error_free_mem;
706 }
707
708 spin_lock_init(&sport->port.lock);
709 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
710 sport->port.ops = &sport_uart_ops;
711 sport->port.line = pdev->id;
712 sport->port.iotype = UPIO_MEM;
713 sport->port.flags = UPF_BOOT_AUTOCONF;
714
715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 if (res == NULL) {
717 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
718 ret = -ENOENT;
719 goto out_error_free_peripherals;
720 }
721
722 sport->port.membase = ioremap(res->start,
723 res->end - res->start);
724 if (!sport->port.membase) {
725 dev_err(&pdev->dev, "Cannot map sport IO\n");
726 ret = -ENXIO;
727 goto out_error_free_peripherals;
728 }
729
730 sport->port.irq = platform_get_irq(pdev, 0);
731 if (sport->port.irq < 0) {
732 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
733 ret = -ENOENT;
734 goto out_error_unmap;
735 }
736
737 sport->err_irq = platform_get_irq(pdev, 1);
738 if (sport->err_irq < 0) {
739 dev_err(&pdev->dev, "No sport status IRQ specified\n");
740 ret = -ENOENT;
741 goto out_error_unmap;
742 }
743 }
744
745#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
746 if (!is_early_platform_device(pdev)) {
747#endif
748 sport = bfin_sport_uart_ports[pdev->id];
749 sport->port.dev = &pdev->dev;
750 dev_set_drvdata(&pdev->dev, sport);
751 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
752#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
753 }
754#endif
755 if (!ret)
756 return 0;
757
758 if (sport) {
759out_error_unmap:
760 iounmap(sport->port.membase);
761out_error_free_peripherals:
762 peripheral_free_list(
763 (unsigned short *)pdev->dev.platform_data);
764out_error_free_mem:
765 kfree(sport);
766 bfin_sport_uart_ports[pdev->id] = NULL;
767 }
768
769 return ret;
2f351741
BW		 770}
771
ccf68e59 772static int __devexit sport_uart_remove(struct platform_device *pdev)
2f351741 773{
ccf68e59 774 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 775
ccf68e59 776 dev_dbg(&pdev->dev, "%s enter\n", __func__);
777 dev_set_drvdata(&pdev->dev, NULL);
2f351741 778
ccf68e59 779 if (sport) {
2f351741 780 uart_remove_one_port(&sport_uart_reg, &sport->port);
ccf68e59 781 iounmap(sport->port.membase);
782 peripheral_free_list(
783 (unsigned short *)pdev->dev.platform_data);
784 kfree(sport);
785 bfin_sport_uart_ports[pdev->id] = NULL;
786 }
2f351741
BW		 787
788 return 0;
789}
790
791static struct platform_driver sport_uart_driver = {
792 .probe = sport_uart_probe,
ccf68e59 793 .remove = __devexit_p(sport_uart_remove),
2f351741
BW		 794 .driver = {
795 .name = DRV_NAME,
ccf68e59 796#ifdef CONFIG_PM
797 .pm = &bfin_sport_uart_dev_pm_ops,
798#endif
2f351741
BW		 799 },
800};
801
ccf68e59 802#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
803static __initdata struct early_platform_driver early_sport_uart_driver = {
804 .class_str = DRV_NAME,
805 .pdrv = &sport_uart_driver,
806 .requested_id = EARLY_PLATFORM_ID_UNSET,
807};
808
809static int __init sport_uart_rs_console_init(void)
810{
811 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
812
813 early_platform_driver_probe(DRV_NAME, BFIN_SPORT_UART_MAX_PORTS, 0);
814
815 register_console(&sport_uart_console);
816
817 return 0;
818}
819console_initcall(sport_uart_rs_console_init);
820#endif
821
2f351741
BW		 822static int __init sport_uart_init(void)
823{
824 int ret;
825
ccf68e59 826 pr_info("Serial: Blackfin uart over sport driver\n");
827
2f351741 828 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 829 if (ret) {
830 pr_err("failed to register %s:%d\n",
2f351741
BW		 831 sport_uart_reg.driver_name, ret);
832 return ret;
833 }
834
835 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 836 if (ret) {
837 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 838 uart_unregister_driver(&sport_uart_reg);
839 }
840
2f351741
BW		 841 return ret;
842}
ccf68e59 843module_init(sport_uart_init);
2f351741
BW		 844
845static void __exit sport_uart_exit(void)
846{
2f351741
BW		 847 platform_driver_unregister(&sport_uart_driver);
848 uart_unregister_driver(&sport_uart_reg);
849}
2f351741
BW		 850module_exit(sport_uart_exit);
851
ccf68e59 852MODULE_AUTHOR("Sonic Zhang, Roy Huang");
853MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 854MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)