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serial: bfin_sport_uart: shorten the SPORT TX waiting loop
[linux-2.6-block.git] / drivers / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW		 32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
37#include <asm/delay.h>
38#include <asm/portmux.h>
39
40#include "bfin_sport_uart.h"
41
ccf68e59 42#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2f351741
BW		 43unsigned short bfin_uart_pin_req_sport0[] =
44 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
45 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
ccf68e59 46#endif
47#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2f351741
BW		 48unsigned short bfin_uart_pin_req_sport1[] =
49 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
50 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
ccf68e59 51#endif
52#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
53unsigned short bfin_uart_pin_req_sport2[] =
54 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \
55 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0};
56#endif
57#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
58unsigned short bfin_uart_pin_req_sport3[] =
59 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \
60 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0};
61#endif
2f351741
BW		 62
63struct sport_uart_port {
64 struct uart_port port;
2f351741 65 int err_irq;
ccf68e59 66 unsigned short csize;
67 unsigned short rxmask;
68 unsigned short txmask1;
69 unsigned short txmask2;
70 unsigned char stopb;
71/* unsigned char parib; */
2f351741
BW		 72};
73
74static void sport_uart_tx_chars(struct sport_uart_port *up);
75static void sport_stop_tx(struct uart_port *port);
76
77static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
78{
ccf68e59 79 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
80 up->txmask1, up->txmask2);
81
82 /* Place Start and Stop bits */
4328e3e5 83 __asm__ __volatile__ (
ccf68e59 84 "%[val] <<= 1;"
85 "%[val] = %[val] & %[mask1];"
86 "%[val] = %[val] | %[mask2];"
87 : [val]"+d"(value)
88 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
89 : "ASTAT"
4328e3e5 90 );
6ef53066 91 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 92
93 SPORT_PUT_TX(up, value);
94}
95
ccf68e59 96static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 97{
ccf68e59 98 unsigned int value;
99 unsigned char extract;
4328e3e5 100 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 101
ccf68e59 102 if ((up->csize + up->stopb) > 7)
103 value = SPORT_GET_RX32(up);
104 else
105 value = SPORT_GET_RX(up);
106
107 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
108 up->csize, up->rxmask);
2f351741 109
ccf68e59 110 /* Extract data */
4328e3e5
MF		 111 __asm__ __volatile__ (
112 "%[extr] = 0;"
ccf68e59 113 "%[mask1] = %[rxmask];"
114 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 115 "%[shift] = 0;"
116 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
117 ".Lloop_s:"
118 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
119 "%[tmp] <<= %[shift];"
120 "%[extr] = %[extr] | %[tmp];"
121 "%[mask1] = %[mask1] - %[mask2];"
122 ".Lloop_e:"
123 "%[shift] += 1;"
ccf68e59 124 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
125 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
126 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 127 : "ASTAT", "LB0", "LC0", "LT0"
128 );
2f351741
BW		 129
130 pr_debug(" extract:%x\n", extract);
131 return extract;
132}
133
ccf68e59 134static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 135{
ccf68e59 136 int tclkdiv, rclkdiv;
137 unsigned int sclk = get_sclk();
2f351741 138
ccf68e59 139 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
140 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
141 SPORT_PUT_TCR2(up, size + 1);
6ef53066 142 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 143
144 /* Set RCR1 and RCR2 */
145 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 146 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 147 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 148
ccf68e59 149 tclkdiv = sclk / (2 * baud_rate) - 1;
150 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
2f351741 151 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 152 SPORT_PUT_RCLKDIV(up, rclkdiv);
153 SSYNC();
ccf68e59 154 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
155 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 156
157 return 0;
158}
159
160static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
161{
162 struct sport_uart_port *up = dev_id;
ebd2c8f6 163 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 164 unsigned int ch;
165
ccf68e59 166 spin_lock(&up->port.lock);
167
168 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 169 ch = rx_one_byte(up);
170 up->port.icount.rx++;
171
ccf68e59 172 if (!uart_handle_sysrq_char(&up->port, ch))
2f351741 173 tty_insert_flip_char(tty, ch, TTY_NORMAL);
ccf68e59 174 }
2f351741
BW		 175 tty_flip_buffer_push(tty);
176
ccf68e59 177 spin_unlock(&up->port.lock);
178
2f351741
BW		 179 return IRQ_HANDLED;
180}
181
182static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
183{
ccf68e59 184 struct sport_uart_port *up = dev_id;
185
186 spin_lock(&up->port.lock);
187 sport_uart_tx_chars(up);
188 spin_unlock(&up->port.lock);
2f351741
BW		 189
190 return IRQ_HANDLED;
191}
192
193static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
194{
195 struct sport_uart_port *up = dev_id;
ebd2c8f6 196 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 197 unsigned int stat = SPORT_GET_STAT(up);
198
ccf68e59 199 spin_lock(&up->port.lock);
200
2f351741
BW		 201 /* Overflow in RX FIFO */
202 if (stat & ROVF) {
203 up->port.icount.overrun++;
204 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
205 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
206 }
207 /* These should not happen */
208 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 209 pr_err("SPORT Error:%s %s %s\n",
210 (stat & TOVF) ? "TX overflow" : "",
211 (stat & TUVF) ? "TX underflow" : "",
212 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 213 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
214 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
215 }
216 SSYNC();
217
ccf68e59 218 spin_unlock(&up->port.lock);
2f351741
BW		 219 return IRQ_HANDLED;
220}
221
222/* Reqeust IRQ, Setup clock */
223static int sport_startup(struct uart_port *port)
224{
225 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 226 int ret;
2f351741 227
6ef53066 228 pr_debug("%s enter\n", __func__);
ccf68e59 229 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
230 "SPORT_UART_RX", up);
231 if (ret) {
232 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
233 return ret;
2f351741
BW		 234 }
235
ccf68e59 236 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
237 "SPORT_UART_TX", up);
238 if (ret) {
239 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 240 goto fail1;
241 }
242
ccf68e59 243 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
244 "SPORT_UART_STATUS", up);
245 if (ret) {
246 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 247 goto fail2;
248 }
249
2f351741 250 return 0;
ccf68e59 251 fail2:
252 free_irq(up->port.irq+1, up);
253 fail1:
254 free_irq(up->port.irq, up);
2f351741 255
ccf68e59 256 return ret;
2f351741
BW		 257}
258
259static void sport_uart_tx_chars(struct sport_uart_port *up)
260{
ebd2c8f6 261 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 262
263 if (SPORT_GET_STAT(up) & TXF)
264 return;
265
266 if (up->port.x_char) {
267 tx_one_byte(up, up->port.x_char);
268 up->port.icount.tx++;
269 up->port.x_char = 0;
270 return;
271 }
272
273 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ		 274 /* The waiting loop to stop SPORT TX from TX interrupt is
275 * too long. This may block SPORT RX interrupts and cause
276 * RX FIFO overflow. So, do stop sport TX only after the last
277 * char in TX FIFO is moved into the shift register.
278 */
279 if (SPORT_GET_STAT(up) & TXHRE)
280 sport_stop_tx(&up->port);
2f351741
BW		 281 return;
282 }
283
284 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
285 tx_one_byte(up, xmit->buf[xmit->tail]);
286 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
287 up->port.icount.tx++;
288 }
289
290 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
291 uart_write_wakeup(&up->port);
292}
293
294static unsigned int sport_tx_empty(struct uart_port *port)
295{
296 struct sport_uart_port *up = (struct sport_uart_port *)port;
297 unsigned int stat;
298
299 stat = SPORT_GET_STAT(up);
6ef53066 300 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 301 if (stat & TXHRE) {
302 return TIOCSER_TEMT;
303 } else
304 return 0;
305}
306
307static unsigned int sport_get_mctrl(struct uart_port *port)
308{
6ef53066 309 pr_debug("%s enter\n", __func__);
2f351741
BW		 310 return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
311}
312
313static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
314{
6ef53066 315 pr_debug("%s enter\n", __func__);
2f351741
BW		 316}
317
318static void sport_stop_tx(struct uart_port *port)
319{
320 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 321
6ef53066 322 pr_debug("%s enter\n", __func__);
2f351741 323
2f351741 324 /* Although the hold register is empty, last byte is still in shift
ccf68e59 325 * register and not sent out yet. So, put a dummy data into TX FIFO.
326 * Then, sport tx stops when last byte is shift out and the dummy
327 * data is moved into the shift register.
328 */
329 SPORT_PUT_TX(up, 0xffff);
330 while (!(SPORT_GET_STAT(up) & TXHRE))
331 cpu_relax();
2f351741
BW		 332
333 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
334 SSYNC();
335
336 return;
337}
338
339static void sport_start_tx(struct uart_port *port)
340{
341 struct sport_uart_port *up = (struct sport_uart_port *)port;
342
6ef53066 343 pr_debug("%s enter\n", __func__);
ccf68e59 344
2f351741
BW		 345 /* Write data into SPORT FIFO before enable SPROT to transmit */
346 sport_uart_tx_chars(up);
347
348 /* Enable transmit, then an interrupt will generated */
349 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
350 SSYNC();
6ef53066 351 pr_debug("%s exit\n", __func__);
2f351741
BW		 352}
353
354static void sport_stop_rx(struct uart_port *port)
355{
356 struct sport_uart_port *up = (struct sport_uart_port *)port;
357
6ef53066 358 pr_debug("%s enter\n", __func__);
2f351741
BW		 359 /* Disable sport to stop rx */
360 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
361 SSYNC();
362}
363
364static void sport_enable_ms(struct uart_port *port)
365{
6ef53066 366 pr_debug("%s enter\n", __func__);
2f351741
BW		 367}
368
369static void sport_break_ctl(struct uart_port *port, int break_state)
370{
6ef53066 371 pr_debug("%s enter\n", __func__);
2f351741
BW		 372}
373
374static void sport_shutdown(struct uart_port *port)
375{
376 struct sport_uart_port *up = (struct sport_uart_port *)port;
377
ccf68e59 378 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 379
380 /* Disable sport */
381 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
382 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
383 SSYNC();
384
ccf68e59 385 free_irq(up->port.irq, up);
386 free_irq(up->port.irq+1, up);
2f351741
BW		 387 free_irq(up->err_irq, up);
388}
389
2f351741
BW		 390static const char *sport_type(struct uart_port *port)
391{
392 struct sport_uart_port *up = (struct sport_uart_port *)port;
393
6ef53066 394 pr_debug("%s enter\n", __func__);
ccf68e59 395 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 396}
397
398static void sport_release_port(struct uart_port *port)
399{
6ef53066 400 pr_debug("%s enter\n", __func__);
2f351741
BW		 401}
402
403static int sport_request_port(struct uart_port *port)
404{
6ef53066 405 pr_debug("%s enter\n", __func__);
2f351741
BW		 406 return 0;
407}
408
409static void sport_config_port(struct uart_port *port, int flags)
410{
411 struct sport_uart_port *up = (struct sport_uart_port *)port;
412
6ef53066 413 pr_debug("%s enter\n", __func__);
2f351741
BW		 414 up->port.type = PORT_BFIN_SPORT;
415}
416
417static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
418{
6ef53066 419 pr_debug("%s enter\n", __func__);
2f351741
BW		 420 return 0;
421}
422
ccf68e59 423static void sport_set_termios(struct uart_port *port,
424 struct ktermios *termios, struct ktermios *old)
425{
426 struct sport_uart_port *up = (struct sport_uart_port *)port;
427 unsigned long flags;
428 int i;
429
430 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
431
432 switch (termios->c_cflag & CSIZE) {
433 case CS8:
434 up->csize = 8;
435 break;
436 case CS7:
437 up->csize = 7;
438 break;
439 case CS6:
440 up->csize = 6;
441 break;
442 case CS5:
443 up->csize = 5;
444 break;
445 default:
446 pr_warning("requested word length not supported\n");
447 }
448
449 if (termios->c_cflag & CSTOPB) {
450 up->stopb = 1;
451 }
452 if (termios->c_cflag & PARENB) {
453 pr_warning("PAREN bits is not supported yet\n");
454 /* up->parib = 1; */
455 }
456
457 port->read_status_mask = OE;
458 if (termios->c_iflag & INPCK)
459 port->read_status_mask |= (FE | PE);
460 if (termios->c_iflag & (BRKINT | PARMRK))
461 port->read_status_mask |= BI;
462
463 /*
464 * Characters to ignore
465 */
466 port->ignore_status_mask = 0;
467 if (termios->c_iflag & IGNPAR)
468 port->ignore_status_mask |= FE | PE;
469 if (termios->c_iflag & IGNBRK) {
470 port->ignore_status_mask |= BI;
471 /*
472 * If we're ignoring parity and break indicators,
473 * ignore overruns too (for real raw support).
474 */
475 if (termios->c_iflag & IGNPAR)
476 port->ignore_status_mask |= OE;
477 }
478
479 /* RX extract mask */
480 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
481 /* TX masks, 8 bit data and 1 bit stop for example:
482 * mask1 = b#0111111110
483 * mask2 = b#1000000000
484 */
485 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
486 up->txmask1 |= (1<<i);
487 up->txmask2 = (1<<i);
488 if (up->stopb) {
489 ++i;
490 up->txmask2 |= (1<<i);
491 }
492 up->txmask1 <<= 1;
493 up->txmask2 <<= 1;
494 /* uart baud rate */
495 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
496
497 spin_lock_irqsave(&up->port.lock, flags);
498
499 /* Disable UART */
500 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
501 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
502
503 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
504
505 /* driver TX line high after config, one dummy data is
506 * necessary to stop sport after shift one byte
507 */
508 SPORT_PUT_TX(up, 0xffff);
509 SPORT_PUT_TX(up, 0xffff);
510 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
511 SSYNC();
512 while (!(SPORT_GET_STAT(up) & TXHRE))
513 cpu_relax();
514 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
515 SSYNC();
516
517 /* Port speed changed, update the per-port timeout. */
518 uart_update_timeout(port, termios->c_cflag, port->uartclk);
519
520 /* Enable sport rx */
521 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
522 SSYNC();
523
524 spin_unlock_irqrestore(&up->port.lock, flags);
525}
526
2f351741
BW		 527struct uart_ops sport_uart_ops = {
528 .tx_empty = sport_tx_empty,
529 .set_mctrl = sport_set_mctrl,
530 .get_mctrl = sport_get_mctrl,
531 .stop_tx = sport_stop_tx,
532 .start_tx = sport_start_tx,
533 .stop_rx = sport_stop_rx,
534 .enable_ms = sport_enable_ms,
535 .break_ctl = sport_break_ctl,
536 .startup = sport_startup,
537 .shutdown = sport_shutdown,
538 .set_termios = sport_set_termios,
539 .type = sport_type,
540 .release_port = sport_release_port,
541 .request_port = sport_request_port,
542 .config_port = sport_config_port,
543 .verify_port = sport_verify_port,
544};
545
ccf68e59 546#define BFIN_SPORT_UART_MAX_PORTS 4
547
548static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
549
550#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
551static int __init
552sport_uart_console_setup(struct console *co, char *options)
553{
554 struct sport_uart_port *up;
555 int baud = 57600;
556 int bits = 8;
557 int parity = 'n';
558 int flow = 'n';
559
560 /* Check whether an invalid uart number has been specified */
561 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
562 return -ENODEV;
563
564 up = bfin_sport_uart_ports[co->index];
565 if (!up)
566 return -ENODEV;
567
568 if (options)
569 uart_parse_options(options, &baud, &parity, &bits, &flow);
570
571 return uart_set_options(&up->port, co, baud, parity, bits, flow);
572}
573
574static void sport_uart_console_putchar(struct uart_port *port, int ch)
575{
576 struct sport_uart_port *up = (struct sport_uart_port *)port;
577
578 while (SPORT_GET_STAT(up) & TXF)
579 barrier();
580
581 tx_one_byte(up, ch);
582}
583
584/*
585 * Interrupts are disabled on entering
586 */
587static void
588sport_uart_console_write(struct console *co, const char *s, unsigned int count)
589{
590 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
591 unsigned long flags;
592
593 spin_lock_irqsave(&up->port.lock, flags);
594
595 if (SPORT_GET_TCR1(up) & TSPEN)
596 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
597 else {
598 /* dummy data to start sport */
599 while (SPORT_GET_STAT(up) & TXF)
600 barrier();
601 SPORT_PUT_TX(up, 0xffff);
602 /* Enable transmit, then an interrupt will generated */
603 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
604 SSYNC();
605
606 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
607
608 /* Although the hold register is empty, last byte is still in shift
609 * register and not sent out yet. So, put a dummy data into TX FIFO.
610 * Then, sport tx stops when last byte is shift out and the dummy
611 * data is moved into the shift register.
612 */
613 while (SPORT_GET_STAT(up) & TXF)
614 barrier();
615 SPORT_PUT_TX(up, 0xffff);
616 while (!(SPORT_GET_STAT(up) & TXHRE))
617 barrier();
618
619 /* Stop sport tx transfer */
620 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
621 SSYNC();
2f351741 622 }
ccf68e59 623
624 spin_unlock_irqrestore(&up->port.lock, flags);
625}
626
627static struct uart_driver sport_uart_reg;
628
629static struct console sport_uart_console = {
630 .name = DEVICE_NAME,
631 .write = sport_uart_console_write,
632 .device = uart_console_device,
633 .setup = sport_uart_console_setup,
634 .flags = CON_PRINTBUFFER,
635 .index = -1,
636 .data = &sport_uart_reg,
2f351741
BW		 637};
638
ccf68e59 639#define SPORT_UART_CONSOLE (&sport_uart_console)
640#else
641#define SPORT_UART_CONSOLE NULL
642#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
643
644
2f351741
BW		 645static struct uart_driver sport_uart_reg = {
646 .owner = THIS_MODULE,
ccf68e59 647 .driver_name = DRV_NAME,
648 .dev_name = DEVICE_NAME,
2f351741
BW		 649 .major = 204,
650 .minor = 84,
ccf68e59 651 .nr = BFIN_SPORT_UART_MAX_PORTS,
652 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 653};
654
ccf68e59 655#ifdef CONFIG_PM
656static int sport_uart_suspend(struct device *dev)
2f351741 657{
ccf68e59 658 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 659
ccf68e59 660 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 661 if (sport)
662 uart_suspend_port(&sport_uart_reg, &sport->port);
663
664 return 0;
665}
666
ccf68e59 667static int sport_uart_resume(struct device *dev)
2f351741 668{
ccf68e59 669 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 670
ccf68e59 671 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 672 if (sport)
673 uart_resume_port(&sport_uart_reg, &sport->port);
674
675 return 0;
676}
677
ccf68e59 678static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
679 .suspend = sport_uart_suspend,
680 .resume = sport_uart_resume,
681};
682#endif
683
684static int __devinit sport_uart_probe(struct platform_device *pdev)
2f351741 685{
ccf68e59 686 struct resource *res;
687 struct sport_uart_port *sport;
688 int ret = 0;
2f351741 689
ccf68e59 690 dev_dbg(&pdev->dev, "%s enter\n", __func__);
691
692 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
693 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
694 return -ENOENT;
695 }
696
697 if (bfin_sport_uart_ports[pdev->id] == NULL) {
698 bfin_sport_uart_ports[pdev->id] =
699 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
700 sport = bfin_sport_uart_ports[pdev->id];
701 if (!sport) {
702 dev_err(&pdev->dev,
703 "Fail to kmalloc sport_uart_port\n");
704 return -ENOMEM;
705 }
706
707 ret = peripheral_request_list(
708 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
709 if (ret) {
710 dev_err(&pdev->dev,
711 "Fail to request SPORT peripherals\n");
712 goto out_error_free_mem;
713 }
714
715 spin_lock_init(&sport->port.lock);
716 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
717 sport->port.ops = &sport_uart_ops;
718 sport->port.line = pdev->id;
719 sport->port.iotype = UPIO_MEM;
720 sport->port.flags = UPF_BOOT_AUTOCONF;
721
722 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 if (res == NULL) {
724 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
725 ret = -ENOENT;
726 goto out_error_free_peripherals;
727 }
728
729 sport->port.membase = ioremap(res->start,
730 res->end - res->start);
731 if (!sport->port.membase) {
732 dev_err(&pdev->dev, "Cannot map sport IO\n");
733 ret = -ENXIO;
734 goto out_error_free_peripherals;
735 }
736
737 sport->port.irq = platform_get_irq(pdev, 0);
738 if (sport->port.irq < 0) {
739 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
740 ret = -ENOENT;
741 goto out_error_unmap;
742 }
743
744 sport->err_irq = platform_get_irq(pdev, 1);
745 if (sport->err_irq < 0) {
746 dev_err(&pdev->dev, "No sport status IRQ specified\n");
747 ret = -ENOENT;
748 goto out_error_unmap;
749 }
750 }
751
752#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
753 if (!is_early_platform_device(pdev)) {
754#endif
755 sport = bfin_sport_uart_ports[pdev->id];
756 sport->port.dev = &pdev->dev;
757 dev_set_drvdata(&pdev->dev, sport);
758 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
759#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
760 }
761#endif
762 if (!ret)
763 return 0;
764
765 if (sport) {
766out_error_unmap:
767 iounmap(sport->port.membase);
768out_error_free_peripherals:
769 peripheral_free_list(
770 (unsigned short *)pdev->dev.platform_data);
771out_error_free_mem:
772 kfree(sport);
773 bfin_sport_uart_ports[pdev->id] = NULL;
774 }
775
776 return ret;
2f351741
BW		 777}
778
ccf68e59 779static int __devexit sport_uart_remove(struct platform_device *pdev)
2f351741 780{
ccf68e59 781 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 782
ccf68e59 783 dev_dbg(&pdev->dev, "%s enter\n", __func__);
784 dev_set_drvdata(&pdev->dev, NULL);
2f351741 785
ccf68e59 786 if (sport) {
2f351741 787 uart_remove_one_port(&sport_uart_reg, &sport->port);
ccf68e59 788 iounmap(sport->port.membase);
789 peripheral_free_list(
790 (unsigned short *)pdev->dev.platform_data);
791 kfree(sport);
792 bfin_sport_uart_ports[pdev->id] = NULL;
793 }
2f351741
BW		 794
795 return 0;
796}
797
798static struct platform_driver sport_uart_driver = {
799 .probe = sport_uart_probe,
ccf68e59 800 .remove = __devexit_p(sport_uart_remove),
2f351741
BW		 801 .driver = {
802 .name = DRV_NAME,
ccf68e59 803#ifdef CONFIG_PM
804 .pm = &bfin_sport_uart_dev_pm_ops,
805#endif
2f351741
BW		 806 },
807};
808
ccf68e59 809#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
810static __initdata struct early_platform_driver early_sport_uart_driver = {
811 .class_str = DRV_NAME,
812 .pdrv = &sport_uart_driver,
813 .requested_id = EARLY_PLATFORM_ID_UNSET,
814};
815
816static int __init sport_uart_rs_console_init(void)
817{
818 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
819
820 early_platform_driver_probe(DRV_NAME, BFIN_SPORT_UART_MAX_PORTS, 0);
821
822 register_console(&sport_uart_console);
823
824 return 0;
825}
826console_initcall(sport_uart_rs_console_init);
827#endif
828
2f351741
BW		 829static int __init sport_uart_init(void)
830{
831 int ret;
832
ccf68e59 833 pr_info("Serial: Blackfin uart over sport driver\n");
834
2f351741 835 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 836 if (ret) {
837 pr_err("failed to register %s:%d\n",
2f351741
BW		 838 sport_uart_reg.driver_name, ret);
839 return ret;
840 }
841
842 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 843 if (ret) {
844 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 845 uart_unregister_driver(&sport_uart_reg);
846 }
847
2f351741
BW		 848 return ret;
849}
ccf68e59 850module_init(sport_uart_init);
2f351741
BW		 851
852static void __exit sport_uart_exit(void)
853{
2f351741
BW		 854 platform_driver_unregister(&sport_uart_driver);
855 uart_unregister_driver(&sport_uart_reg);
856}
2f351741
BW		 857module_exit(sport_uart_exit);
858
ccf68e59 859MODULE_AUTHOR("Sonic Zhang, Roy Huang");
860MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 861MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)