Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
607c268e MF |
41 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
42 | # undef CONFIG_EARLY_PRINTK | |
43 | #endif | |
44 | ||
0271edd4 MF |
45 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
46 | # undef CONFIG_EARLY_PRINTK | |
47 | #endif | |
48 | ||
194de561 BW |
49 | /* UART name and device definitions */ |
50 | #define BFIN_SERIAL_NAME "ttyBF" | |
51 | #define BFIN_SERIAL_MAJOR 204 | |
52 | #define BFIN_SERIAL_MINOR 64 | |
53 | ||
c9607ecc MF |
54 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
55 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
56 | ||
52e15f0e SZ |
57 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
58 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
59 | ||
60 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
61 | # error KGDB only support UART in PIO mode. | |
62 | # endif | |
63 | ||
64 | static int kgdboc_port_line; | |
65 | static int kgdboc_break_enabled; | |
66 | #endif | |
194de561 BW |
67 | /* |
68 | * Setup for console. Argument comes from the menuconfig | |
69 | */ | |
70 | #define DMA_RX_XCOUNT 512 | |
71 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
72 | ||
0aef4564 | 73 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
74 | |
75 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
76 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
77 | #else | |
194de561 | 78 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
79 | #endif |
80 | ||
80d5c474 GY |
81 | static void bfin_serial_reset_irda(struct uart_port *port); |
82 | ||
d307d36a SZ |
83 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
84 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
85 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
86 | { | |
87 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
88 | if (uart->cts_pin < 0) | |
89 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
90 | ||
91 | /* CTS PIN is negative assertive. */ | |
92 | if (UART_GET_CTS(uart)) | |
93 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
94 | else | |
95 | return TIOCM_DSR | TIOCM_CAR; | |
96 | } | |
97 | ||
98 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
99 | { | |
100 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
101 | if (uart->rts_pin < 0) | |
102 | return; | |
103 | ||
104 | /* RTS PIN is negative assertive. */ | |
105 | if (mctrl & TIOCM_RTS) | |
106 | UART_ENABLE_RTS(uart); | |
107 | else | |
108 | UART_DISABLE_RTS(uart); | |
109 | } | |
110 | ||
111 | /* | |
112 | * Handle any change of modem status signal. | |
113 | */ | |
114 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) | |
115 | { | |
116 | struct bfin_serial_port *uart = dev_id; | |
117 | unsigned int status; | |
118 | ||
119 | status = bfin_serial_get_mctrl(&uart->port); | |
120 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
121 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
122 | uart->scts = 1; | |
123 | UART_CLEAR_SCTS(uart); | |
124 | UART_CLEAR_IER(uart, EDSSI); | |
125 | #endif | |
126 | ||
127 | return IRQ_HANDLED; | |
128 | } | |
129 | #else | |
130 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
131 | { | |
132 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
133 | } | |
134 | ||
135 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
136 | { | |
137 | } | |
138 | #endif | |
139 | ||
194de561 BW |
140 | /* |
141 | * interrupts are disabled on entry | |
142 | */ | |
143 | static void bfin_serial_stop_tx(struct uart_port *port) | |
144 | { | |
145 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 146 | #ifdef CONFIG_SERIAL_BFIN_DMA |
ebd2c8f6 | 147 | struct circ_buf *xmit = &uart->port.state->xmit; |
68a784cb | 148 | #endif |
194de561 | 149 | |
f4d640c9 | 150 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 151 | cpu_relax(); |
f4d640c9 | 152 | |
194de561 BW |
153 | #ifdef CONFIG_SERIAL_BFIN_DMA |
154 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
155 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
156 | uart->port.icount.tx += uart->tx_count; | |
157 | uart->tx_count = 0; | |
158 | uart->tx_done = 1; | |
f4d640c9 RH |
159 | #else |
160 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
161 | /* Clear TFI bit */ |
162 | UART_PUT_LSR(uart, TFI); | |
194de561 | 163 | #endif |
89bf6dc5 | 164 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 165 | #endif |
194de561 BW |
166 | } |
167 | ||
168 | /* | |
169 | * port is locked and interrupts are disabled | |
170 | */ | |
171 | static void bfin_serial_start_tx(struct uart_port *port) | |
172 | { | |
173 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
ebd2c8f6 | 174 | struct tty_struct *tty = uart->port.state->port.tty; |
80d5c474 | 175 | |
d307d36a | 176 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 177 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
178 | uart->scts = 0; |
179 | uart_handle_cts_change(&uart->port, uart->scts); | |
180 | } | |
181 | #endif | |
182 | ||
80d5c474 GY |
183 | /* |
184 | * To avoid losting RX interrupt, we reset IR function | |
185 | * before sending data. | |
186 | */ | |
187 | if (tty->termios->c_line == N_IRDA) | |
188 | bfin_serial_reset_irda(port); | |
194de561 BW |
189 | |
190 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
191 | if (uart->tx_done) |
192 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 193 | #else |
f4d640c9 | 194 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 195 | bfin_serial_tx_chars(uart); |
f4d640c9 | 196 | #endif |
194de561 BW |
197 | } |
198 | ||
199 | /* | |
200 | * Interrupts are enabled | |
201 | */ | |
202 | static void bfin_serial_stop_rx(struct uart_port *port) | |
203 | { | |
204 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 205 | |
f4d640c9 | 206 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
207 | } |
208 | ||
209 | /* | |
210 | * Set the modem control timer to fire immediately. | |
211 | */ | |
212 | static void bfin_serial_enable_ms(struct uart_port *port) | |
213 | { | |
214 | } | |
215 | ||
474f1a66 | 216 | |
50e2e15a | 217 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
218 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
219 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
220 | #else | |
221 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
222 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
223 | #endif | |
224 | ||
194de561 | 225 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
226 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
227 | { | |
52e15f0e | 228 | struct tty_struct *tty = NULL; |
194de561 | 229 | unsigned int status, ch, flg; |
8851c71e | 230 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 231 | |
759eb040 | 232 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
233 | UART_CLEAR_LSR(uart); |
234 | ||
235 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
236 | uart->port.icount.rx++; |
237 | ||
52e15f0e SZ |
238 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
239 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
240 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
241 | if (ch == 0x3) {/* Ctrl + C */ | |
242 | kgdb_breakpoint(); | |
474f1a66 | 243 | return; |
474f1a66 | 244 | } |
52e15f0e | 245 | |
ebd2c8f6 | 246 | if (!uart->port.state || !uart->port.state->port.tty) |
52e15f0e | 247 | return; |
474f1a66 | 248 | #endif |
ebd2c8f6 | 249 | tty = uart->port.state->port.tty; |
bbf275f0 | 250 | |
50e2e15a | 251 | if (ANOMALY_05000363) { |
8851c71e MF |
252 | /* The BF533 (and BF561) family of processors have a nice anomaly |
253 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 254 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
255 | * character comes across. Due to the nature of the flood, it is |
256 | * not possible to reliably catch bytes that are sent too quickly | |
257 | * after this break. So application code talking to the Blackfin | |
258 | * which sends a break signal must allow at least 1.5 character | |
259 | * times after the end of the break for things to stabilize. This | |
260 | * timeout was picked as it must absolutely be larger than 1 | |
261 | * character time +/- some percent. So 1.5 sounds good. All other | |
262 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 263 | */ |
8851c71e MF |
264 | if (anomaly_start.tv_sec) { |
265 | struct timeval curr; | |
266 | suseconds_t usecs; | |
267 | ||
268 | if ((~ch & (~ch + 1)) & 0xff) | |
269 | goto known_good_char; | |
270 | ||
271 | do_gettimeofday(&curr); | |
272 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
273 | goto known_good_char; | |
274 | ||
275 | usecs = 0; | |
276 | if (curr.tv_sec != anomaly_start.tv_sec) | |
277 | usecs += USEC_PER_SEC; | |
278 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
279 | ||
280 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
281 | goto known_good_char; | |
282 | ||
283 | if (ch) | |
284 | anomaly_start.tv_sec = 0; | |
285 | else | |
286 | anomaly_start = curr; | |
287 | ||
288 | return; | |
289 | ||
290 | known_good_char: | |
e482a237 | 291 | status &= ~BI; |
8851c71e | 292 | anomaly_start.tv_sec = 0; |
bbf275f0 | 293 | } |
194de561 | 294 | } |
194de561 BW |
295 | |
296 | if (status & BI) { | |
50e2e15a | 297 | if (ANOMALY_05000363) |
8851c71e MF |
298 | if (bfin_revid() < 5) |
299 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
300 | uart->port.icount.brk++; |
301 | if (uart_handle_break(&uart->port)) | |
302 | goto ignore_char; | |
9808901b | 303 | status &= ~(PE | FE); |
2ac5ee47 MF |
304 | } |
305 | if (status & PE) | |
194de561 | 306 | uart->port.icount.parity++; |
2ac5ee47 | 307 | if (status & OE) |
194de561 | 308 | uart->port.icount.overrun++; |
2ac5ee47 | 309 | if (status & FE) |
194de561 | 310 | uart->port.icount.frame++; |
2ac5ee47 MF |
311 | |
312 | status &= uart->port.read_status_mask; | |
313 | ||
314 | if (status & BI) | |
315 | flg = TTY_BREAK; | |
316 | else if (status & PE) | |
317 | flg = TTY_PARITY; | |
318 | else if (status & FE) | |
319 | flg = TTY_FRAME; | |
320 | else | |
194de561 BW |
321 | flg = TTY_NORMAL; |
322 | ||
323 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
324 | goto ignore_char; | |
194de561 | 325 | |
2ac5ee47 MF |
326 | uart_insert_char(&uart->port, status, OE, ch, flg); |
327 | ||
328 | ignore_char: | |
329 | tty_flip_buffer_push(tty); | |
194de561 BW |
330 | } |
331 | ||
332 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
333 | { | |
ebd2c8f6 | 334 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 335 | |
194de561 | 336 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
5ffdeea2 SZ |
337 | #ifdef CONFIG_BF54x |
338 | /* Clear TFI bit */ | |
339 | UART_PUT_LSR(uart, TFI); | |
340 | #endif | |
0efa4f2c SZ |
341 | /* Anomaly notes: |
342 | * 05000215 - we always clear ETBEI within last UART TX | |
343 | * interrupt to end a string. It is always set | |
344 | * when start a new tx. | |
345 | */ | |
5ffdeea2 | 346 | UART_CLEAR_IER(uart, ETBEI); |
194de561 BW |
347 | return; |
348 | } | |
349 | ||
f30ac0ce SZ |
350 | if (uart->port.x_char) { |
351 | UART_PUT_CHAR(uart, uart->port.x_char); | |
352 | uart->port.icount.tx++; | |
353 | uart->port.x_char = 0; | |
354 | } | |
355 | ||
759eb040 SZ |
356 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
357 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
358 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
359 | uart->port.icount.tx++; | |
360 | SSYNC(); | |
361 | } | |
194de561 BW |
362 | |
363 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
364 | uart_write_wakeup(&uart->port); | |
194de561 BW |
365 | } |
366 | ||
5c4e472b AL |
367 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
368 | { | |
369 | struct bfin_serial_port *uart = dev_id; | |
370 | ||
f4d640c9 | 371 | spin_lock(&uart->port.lock); |
0bcfd70e | 372 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 373 | bfin_serial_rx_chars(uart); |
f4d640c9 | 374 | spin_unlock(&uart->port.lock); |
759eb040 | 375 | |
5c4e472b AL |
376 | return IRQ_HANDLED; |
377 | } | |
378 | ||
379 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
380 | { |
381 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 382 | |
d307d36a | 383 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 384 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
385 | uart->scts = 0; |
386 | uart_handle_cts_change(&uart->port, uart->scts); | |
387 | } | |
388 | #endif | |
f4d640c9 | 389 | spin_lock(&uart->port.lock); |
0bcfd70e | 390 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 391 | bfin_serial_tx_chars(uart); |
f4d640c9 | 392 | spin_unlock(&uart->port.lock); |
759eb040 | 393 | |
194de561 BW |
394 | return IRQ_HANDLED; |
395 | } | |
4cb4f22b | 396 | #endif |
194de561 | 397 | |
194de561 BW |
398 | #ifdef CONFIG_SERIAL_BFIN_DMA |
399 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
400 | { | |
ebd2c8f6 | 401 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 402 | |
194de561 BW |
403 | uart->tx_done = 0; |
404 | ||
1b73351c | 405 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 406 | uart->tx_count = 0; |
1b73351c SZ |
407 | uart->tx_done = 1; |
408 | return; | |
409 | } | |
410 | ||
194de561 BW |
411 | if (uart->port.x_char) { |
412 | UART_PUT_CHAR(uart, uart->port.x_char); | |
413 | uart->port.icount.tx++; | |
414 | uart->port.x_char = 0; | |
194de561 | 415 | } |
1b73351c | 416 | |
194de561 BW |
417 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
418 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
419 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
420 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
421 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
422 | set_dma_config(uart->tx_dma_channel, | |
423 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
424 | INTR_ON_BUF, | |
425 | DIMENSION_LINEAR, | |
2047e40d MH |
426 | DATA_SIZE_8, |
427 | DMA_SYNC_RESTART)); | |
194de561 BW |
428 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
429 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
430 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
f9d36da9 | 431 | SSYNC(); |
194de561 | 432 | enable_dma(uart->tx_dma_channel); |
99ee7b5f | 433 | |
f4d640c9 | 434 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
435 | } |
436 | ||
2ac5ee47 | 437 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 438 | { |
ebd2c8f6 | 439 | struct tty_struct *tty = uart->port.state->port.tty; |
194de561 BW |
440 | int i, flg, status; |
441 | ||
442 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
443 | UART_CLEAR_LSR(uart); |
444 | ||
56f5de8f SZ |
445 | uart->port.icount.rx += |
446 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
447 | UART_XMIT_SIZE); | |
194de561 BW |
448 | |
449 | if (status & BI) { | |
450 | uart->port.icount.brk++; | |
451 | if (uart_handle_break(&uart->port)) | |
452 | goto dma_ignore_char; | |
9808901b | 453 | status &= ~(PE | FE); |
2ac5ee47 MF |
454 | } |
455 | if (status & PE) | |
194de561 | 456 | uart->port.icount.parity++; |
2ac5ee47 | 457 | if (status & OE) |
194de561 | 458 | uart->port.icount.overrun++; |
2ac5ee47 | 459 | if (status & FE) |
194de561 | 460 | uart->port.icount.frame++; |
2ac5ee47 MF |
461 | |
462 | status &= uart->port.read_status_mask; | |
463 | ||
464 | if (status & BI) | |
465 | flg = TTY_BREAK; | |
466 | else if (status & PE) | |
467 | flg = TTY_PARITY; | |
468 | else if (status & FE) | |
469 | flg = TTY_FRAME; | |
470 | else | |
194de561 BW |
471 | flg = TTY_NORMAL; |
472 | ||
8c4210e3 | 473 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
474 | if (i >= UART_XMIT_SIZE) |
475 | i = 0; | |
8c4210e3 SZ |
476 | if (i == uart->rx_dma_buf.head) |
477 | break; | |
56f5de8f SZ |
478 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
479 | uart_insert_char(&uart->port, status, OE, | |
480 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 481 | } |
2ac5ee47 MF |
482 | |
483 | dma_ignore_char: | |
194de561 BW |
484 | tty_flip_buffer_push(tty); |
485 | } | |
486 | ||
487 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
488 | { | |
59e4e3e6 | 489 | int x_pos, pos; |
68a784cb | 490 | |
2860b791 SZ |
491 | dma_disable_irq(uart->rx_dma_channel); |
492 | spin_lock_bh(&uart->port.lock); | |
194de561 | 493 | |
8516c568 SZ |
494 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
495 | * curr_x_count can't be read as an atomic operation, | |
496 | * curr_y_count should be read before curr_x_count. When | |
497 | * curr_x_count is read, curr_y_count may already indicate | |
498 | * next buffer line. But, the position calculated here is | |
499 | * still indicate the old line. The wrong position data may | |
500 | * be smaller than current buffer tail, which cause garbages | |
501 | * are received if it is not prohibit. | |
502 | */ | |
56f5de8f SZ |
503 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
504 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
505 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
35ff6935 | 506 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
56f5de8f SZ |
507 | uart->rx_dma_nrows = 0; |
508 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
509 | if (x_pos == DMA_RX_XCOUNT) |
510 | x_pos = 0; | |
511 | ||
512 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
8516c568 SZ |
513 | /* Ignore receiving data if new position is in the same line of |
514 | * current buffer tail and small. | |
515 | */ | |
516 | if (pos > uart->rx_dma_buf.tail || | |
517 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
56f5de8f | 518 | uart->rx_dma_buf.head = pos; |
194de561 | 519 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 520 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 521 | } |
0aef4564 | 522 | |
2860b791 SZ |
523 | spin_unlock_bh(&uart->port.lock); |
524 | dma_enable_irq(uart->rx_dma_channel); | |
68a784cb | 525 | |
0a278423 | 526 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
527 | } |
528 | ||
529 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
530 | { | |
531 | struct bfin_serial_port *uart = dev_id; | |
ebd2c8f6 | 532 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 533 | |
d307d36a | 534 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 535 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) { |
d307d36a SZ |
536 | uart->scts = 0; |
537 | uart_handle_cts_change(&uart->port, uart->scts); | |
538 | } | |
539 | #endif | |
540 | ||
194de561 BW |
541 | spin_lock(&uart->port.lock); |
542 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 543 | disable_dma(uart->tx_dma_channel); |
0711d857 | 544 | clear_dma_irqstat(uart->tx_dma_channel); |
0efa4f2c SZ |
545 | /* Anomaly notes: |
546 | * 05000215 - we always clear ETBEI within last UART TX | |
547 | * interrupt to end a string. It is always set | |
548 | * when start a new tx. | |
549 | */ | |
f4d640c9 | 550 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
551 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
552 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 553 | |
56f5de8f SZ |
554 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
555 | uart_write_wakeup(&uart->port); | |
556 | ||
1b73351c | 557 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
558 | } |
559 | ||
560 | spin_unlock(&uart->port.lock); | |
561 | return IRQ_HANDLED; | |
562 | } | |
563 | ||
564 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
565 | { | |
566 | struct bfin_serial_port *uart = dev_id; | |
567 | unsigned short irqstat; | |
35ff6935 | 568 | int x_pos, pos; |
0711d857 | 569 | |
194de561 BW |
570 | spin_lock(&uart->port.lock); |
571 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
572 | clear_dma_irqstat(uart->rx_dma_channel); | |
8516c568 SZ |
573 | |
574 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); | |
35ff6935 | 575 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); |
8516c568 | 576 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; |
35ff6935 | 577 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
8516c568 SZ |
578 | uart->rx_dma_nrows = 0; |
579 | ||
580 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT; | |
581 | if (pos > uart->rx_dma_buf.tail || | |
582 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
583 | uart->rx_dma_buf.head = pos; | |
584 | bfin_serial_dma_rx_chars(uart); | |
585 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; | |
586 | } | |
587 | ||
194de561 | 588 | spin_unlock(&uart->port.lock); |
0aef4564 | 589 | |
194de561 BW |
590 | return IRQ_HANDLED; |
591 | } | |
592 | #endif | |
593 | ||
594 | /* | |
595 | * Return TIOCSER_TEMT when transmitter is not busy. | |
596 | */ | |
597 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
598 | { | |
599 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
600 | unsigned short lsr; | |
601 | ||
602 | lsr = UART_GET_LSR(uart); | |
603 | if (lsr & TEMT) | |
604 | return TIOCSER_TEMT; | |
605 | else | |
606 | return 0; | |
607 | } | |
608 | ||
194de561 BW |
609 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) |
610 | { | |
cf686762 MF |
611 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
612 | u16 lcr = UART_GET_LCR(uart); | |
613 | if (break_state) | |
614 | lcr |= SB; | |
615 | else | |
616 | lcr &= ~SB; | |
617 | UART_PUT_LCR(uart, lcr); | |
618 | SSYNC(); | |
194de561 BW |
619 | } |
620 | ||
621 | static int bfin_serial_startup(struct uart_port *port) | |
622 | { | |
623 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
624 | ||
625 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
626 | dma_addr_t dma_handle; | |
627 | ||
628 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
629 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
630 | return -EBUSY; | |
631 | } | |
632 | ||
633 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
634 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
635 | free_dma(uart->rx_dma_channel); | |
636 | return -EBUSY; | |
637 | } | |
638 | ||
639 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
640 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
641 | ||
642 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
643 | uart->rx_dma_buf.head = 0; | |
644 | uart->rx_dma_buf.tail = 0; | |
645 | uart->rx_dma_nrows = 0; | |
646 | ||
647 | set_dma_config(uart->rx_dma_channel, | |
648 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
649 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
650 | DATA_SIZE_8, |
651 | DMA_SYNC_RESTART)); | |
194de561 BW |
652 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
653 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
654 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
655 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
656 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
657 | enable_dma(uart->rx_dma_channel); | |
658 | ||
659 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
660 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
661 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
662 | add_timer(&(uart->rx_dma_timer)); | |
663 | #else | |
6f95570e | 664 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
665 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
666 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
667 | kgdboc_break_enabled = 0; | |
668 | else { | |
669 | # endif | |
a359cca7 SZ |
670 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
671 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
672 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
673 | return -EBUSY; | |
674 | } | |
675 | ||
676 | if (request_irq | |
5c4e472b | 677 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
678 | "BFIN_UART_TX", uart)) { |
679 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
680 | free_irq(uart->port.irq, uart); | |
681 | return -EBUSY; | |
682 | } | |
ab2375f2 SZ |
683 | |
684 | # ifdef CONFIG_BF54x | |
685 | { | |
686 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
687 | ||
688 | switch (uart->port.irq) { | |
689 | case IRQ_UART3_RX: | |
690 | uart_dma_ch_rx = CH_UART3_RX; | |
691 | uart_dma_ch_tx = CH_UART3_TX; | |
692 | break; | |
693 | case IRQ_UART2_RX: | |
694 | uart_dma_ch_rx = CH_UART2_RX; | |
695 | uart_dma_ch_tx = CH_UART2_TX; | |
696 | break; | |
697 | default: | |
698 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
699 | break; | |
700 | }; | |
701 | ||
702 | if (uart_dma_ch_rx && | |
703 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
704 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
705 | free_irq(uart->port.irq, uart); | |
706 | free_irq(uart->port.irq + 1, uart); | |
707 | return -EBUSY; | |
708 | } | |
709 | if (uart_dma_ch_tx && | |
710 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
711 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
712 | free_dma(uart_dma_ch_rx); | |
713 | free_irq(uart->port.irq, uart); | |
714 | free_irq(uart->port.irq + 1, uart); | |
715 | return -EBUSY; | |
716 | } | |
717 | } | |
718 | # endif | |
6f95570e | 719 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
720 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
721 | } | |
722 | # endif | |
6f95570e SZ |
723 | #endif |
724 | ||
725 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
726 | if (uart->cts_pin >= 0) { | |
727 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
728 | bfin_serial_mctrl_cts_int, | |
729 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
730 | IRQF_DISABLED, "BFIN_UART_CTS", uart)) { | |
731 | uart->cts_pin = -1; | |
732 | pr_info("Unable to attach BlackFin UART CTS interrupt.\ | |
733 | So, disable it.\n"); | |
734 | } | |
735 | } | |
736 | if (uart->rts_pin >= 0) { | |
737 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
738 | gpio_direction_output(uart->rts_pin, 0); | |
739 | } | |
194de561 | 740 | #endif |
d307d36a SZ |
741 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
742 | if (request_irq(uart->status_irq, | |
743 | bfin_serial_mctrl_cts_int, | |
744 | IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) { | |
745 | pr_info("Unable to attach BlackFin UART Modem \ | |
746 | Status interrupt.\n"); | |
747 | } | |
748 | ||
749 | if (uart->cts_pin >= 0) { | |
750 | gpio_request(uart->cts_pin, DRIVER_NAME); | |
751 | gpio_direction_output(uart->cts_pin, 1); | |
752 | } | |
753 | if (uart->rts_pin >= 0) { | |
754 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
755 | gpio_direction_output(uart->rts_pin, 0); | |
756 | } | |
757 | ||
758 | /* CTS RTS PINs are negative assertive. */ | |
759 | UART_PUT_MCR(uart, ACTS); | |
760 | UART_SET_IER(uart, EDSSI); | |
761 | #endif | |
762 | ||
f4d640c9 | 763 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
764 | return 0; |
765 | } | |
766 | ||
767 | static void bfin_serial_shutdown(struct uart_port *port) | |
768 | { | |
769 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
770 | ||
771 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
772 | disable_dma(uart->tx_dma_channel); | |
773 | free_dma(uart->tx_dma_channel); | |
774 | disable_dma(uart->rx_dma_channel); | |
775 | free_dma(uart->rx_dma_channel); | |
776 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 777 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 778 | #else |
ab2375f2 SZ |
779 | #ifdef CONFIG_BF54x |
780 | switch (uart->port.irq) { | |
781 | case IRQ_UART3_RX: | |
782 | free_dma(CH_UART3_RX); | |
783 | free_dma(CH_UART3_TX); | |
784 | break; | |
785 | case IRQ_UART2_RX: | |
786 | free_dma(CH_UART2_RX); | |
787 | free_dma(CH_UART2_TX); | |
788 | break; | |
789 | default: | |
790 | break; | |
791 | }; | |
474f1a66 | 792 | #endif |
194de561 BW |
793 | free_irq(uart->port.irq, uart); |
794 | free_irq(uart->port.irq+1, uart); | |
795 | #endif | |
6f95570e | 796 | |
d307d36a | 797 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
6f95570e SZ |
798 | if (uart->cts_pin >= 0) |
799 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
800 | if (uart->rts_pin >= 0) | |
801 | gpio_free(uart->rts_pin); | |
d307d36a SZ |
802 | #endif |
803 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
804 | if (uart->cts_pin >= 0) | |
805 | gpio_free(uart->cts_pin); | |
806 | if (uart->rts_pin >= 0) | |
807 | gpio_free(uart->rts_pin); | |
808 | if (UART_GET_IER(uart) && EDSSI) | |
809 | free_irq(uart->status_irq, uart); | |
810 | #endif | |
194de561 BW |
811 | } |
812 | ||
813 | static void | |
814 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
815 | struct ktermios *old) | |
816 | { | |
817 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
818 | unsigned long flags; | |
819 | unsigned int baud, quot; | |
0c44a86d | 820 | unsigned short val, ier, lcr = 0; |
194de561 BW |
821 | |
822 | switch (termios->c_cflag & CSIZE) { | |
823 | case CS8: | |
824 | lcr = WLS(8); | |
825 | break; | |
826 | case CS7: | |
827 | lcr = WLS(7); | |
828 | break; | |
829 | case CS6: | |
830 | lcr = WLS(6); | |
831 | break; | |
832 | case CS5: | |
833 | lcr = WLS(5); | |
834 | break; | |
835 | default: | |
836 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 837 | __func__); |
194de561 BW |
838 | } |
839 | ||
84507794 SZ |
840 | /* Anomaly notes: |
841 | * 05000231 - STOP bit is always set to 1 whatever the user is set. | |
842 | */ | |
843 | if (termios->c_cflag & CSTOPB) { | |
844 | if (ANOMALY_05000231) | |
845 | printk(KERN_WARNING "STOP bits other than 1 is not " | |
846 | "supported in case of anomaly 05000231.\n"); | |
847 | else | |
848 | lcr |= STB; | |
849 | } | |
19aa6382 | 850 | if (termios->c_cflag & PARENB) |
194de561 | 851 | lcr |= PEN; |
19aa6382 MF |
852 | if (!(termios->c_cflag & PARODD)) |
853 | lcr |= EPS; | |
854 | if (termios->c_cflag & CMSPAR) | |
855 | lcr |= STP; | |
194de561 | 856 | |
2ac5ee47 MF |
857 | port->read_status_mask = OE; |
858 | if (termios->c_iflag & INPCK) | |
859 | port->read_status_mask |= (FE | PE); | |
860 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
861 | port->read_status_mask |= BI; | |
194de561 | 862 | |
2ac5ee47 MF |
863 | /* |
864 | * Characters to ignore | |
865 | */ | |
866 | port->ignore_status_mask = 0; | |
867 | if (termios->c_iflag & IGNPAR) | |
868 | port->ignore_status_mask |= FE | PE; | |
869 | if (termios->c_iflag & IGNBRK) { | |
870 | port->ignore_status_mask |= BI; | |
871 | /* | |
872 | * If we're ignoring parity and break indicators, | |
873 | * ignore overruns too (for real raw support). | |
874 | */ | |
875 | if (termios->c_iflag & IGNPAR) | |
876 | port->ignore_status_mask |= OE; | |
877 | } | |
194de561 BW |
878 | |
879 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
f4487101 | 880 | quot = uart_get_divisor(port, baud) - ANOMALY_05000230; |
194de561 BW |
881 | spin_lock_irqsave(&uart->port.lock, flags); |
882 | ||
8851c71e MF |
883 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
884 | ||
194de561 BW |
885 | /* Disable UART */ |
886 | ier = UART_GET_IER(uart); | |
1feaa51d | 887 | UART_DISABLE_INTS(uart); |
194de561 BW |
888 | |
889 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 890 | UART_SET_DLAB(uart); |
194de561 BW |
891 | |
892 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
893 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
894 | SSYNC(); | |
895 | ||
896 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 897 | UART_CLEAR_DLAB(uart); |
194de561 BW |
898 | |
899 | UART_PUT_LCR(uart, lcr); | |
900 | ||
901 | /* Enable UART */ | |
1feaa51d | 902 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
903 | |
904 | val = UART_GET_GCTL(uart); | |
905 | val |= UCEN; | |
906 | UART_PUT_GCTL(uart, val); | |
907 | ||
b3ef5aba GY |
908 | /* Port speed changed, update the per-port timeout. */ |
909 | uart_update_timeout(port, termios->c_cflag, baud); | |
910 | ||
194de561 BW |
911 | spin_unlock_irqrestore(&uart->port.lock, flags); |
912 | } | |
913 | ||
914 | static const char *bfin_serial_type(struct uart_port *port) | |
915 | { | |
916 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
917 | ||
918 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
919 | } | |
920 | ||
921 | /* | |
922 | * Release the memory region(s) being used by 'port'. | |
923 | */ | |
924 | static void bfin_serial_release_port(struct uart_port *port) | |
925 | { | |
926 | } | |
927 | ||
928 | /* | |
929 | * Request the memory region(s) being used by 'port'. | |
930 | */ | |
931 | static int bfin_serial_request_port(struct uart_port *port) | |
932 | { | |
933 | return 0; | |
934 | } | |
935 | ||
936 | /* | |
937 | * Configure/autoconfigure the port. | |
938 | */ | |
939 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
940 | { | |
941 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
942 | ||
943 | if (flags & UART_CONFIG_TYPE && | |
944 | bfin_serial_request_port(&uart->port) == 0) | |
945 | uart->port.type = PORT_BFIN; | |
946 | } | |
947 | ||
948 | /* | |
949 | * Verify the new serial_struct (for TIOCSSERIAL). | |
950 | * The only change we allow are to the flags and type, and | |
951 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
952 | */ | |
953 | static int | |
954 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
955 | { | |
956 | return 0; | |
957 | } | |
958 | ||
7d01b475 GY |
959 | /* |
960 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
961 | * In other cases, disable IrDA function. | |
962 | */ | |
3b8458a9 | 963 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 964 | { |
3b8458a9 | 965 | int line = port->line; |
7d01b475 GY |
966 | unsigned short val; |
967 | ||
ebd2c8f6 | 968 | if (line >= port->state->port.tty->driver->num) |
7d01b475 GY |
969 | return; |
970 | ||
ebd2c8f6 | 971 | switch (port->state->port.tty->termios->c_line) { |
7d01b475 GY |
972 | case N_IRDA: |
973 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
974 | val |= (IREN | RPOLC); | |
975 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
976 | break; | |
977 | default: | |
978 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
979 | val &= ~(IREN | RPOLC); | |
980 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
981 | } | |
982 | } | |
983 | ||
6f95570e SZ |
984 | static void bfin_serial_reset_irda(struct uart_port *port) |
985 | { | |
986 | int line = port->line; | |
987 | unsigned short val; | |
988 | ||
989 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
990 | val &= ~(IREN | RPOLC); | |
991 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
992 | SSYNC(); | |
993 | val |= (IREN | RPOLC); | |
994 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
995 | SSYNC(); | |
996 | } | |
997 | ||
52e15f0e | 998 | #ifdef CONFIG_CONSOLE_POLL |
0efa4f2c SZ |
999 | /* Anomaly notes: |
1000 | * 05000099 - Because we only use THRE in poll_put and DR in poll_get, | |
1001 | * losing other bits of UART_LSR is not a problem here. | |
1002 | */ | |
52e15f0e SZ |
1003 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) |
1004 | { | |
1005 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1006 | ||
1007 | while (!(UART_GET_LSR(uart) & THRE)) | |
1008 | cpu_relax(); | |
1009 | ||
1010 | UART_CLEAR_DLAB(uart); | |
1011 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
1012 | } | |
1013 | ||
1014 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
1015 | { | |
1016 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1017 | unsigned char chr; | |
1018 | ||
1019 | while (!(UART_GET_LSR(uart) & DR)) | |
1020 | cpu_relax(); | |
1021 | ||
1022 | UART_CLEAR_DLAB(uart); | |
1023 | chr = UART_GET_CHAR(uart); | |
1024 | ||
1025 | return chr; | |
1026 | } | |
1027 | #endif | |
1028 | ||
1029 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
1030 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1031 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
1032 | { | |
1033 | if (kgdboc_break_enabled) { | |
1034 | kgdboc_break_enabled = 0; | |
1035 | bfin_serial_shutdown(port); | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
1040 | { | |
1041 | kgdboc_port_line = port->line; | |
1042 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
1043 | return 0; | |
1044 | } | |
1045 | #endif | |
1046 | ||
194de561 BW |
1047 | static struct uart_ops bfin_serial_pops = { |
1048 | .tx_empty = bfin_serial_tx_empty, | |
1049 | .set_mctrl = bfin_serial_set_mctrl, | |
1050 | .get_mctrl = bfin_serial_get_mctrl, | |
1051 | .stop_tx = bfin_serial_stop_tx, | |
1052 | .start_tx = bfin_serial_start_tx, | |
1053 | .stop_rx = bfin_serial_stop_rx, | |
1054 | .enable_ms = bfin_serial_enable_ms, | |
1055 | .break_ctl = bfin_serial_break_ctl, | |
1056 | .startup = bfin_serial_startup, | |
1057 | .shutdown = bfin_serial_shutdown, | |
1058 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 1059 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
1060 | .type = bfin_serial_type, |
1061 | .release_port = bfin_serial_release_port, | |
1062 | .request_port = bfin_serial_request_port, | |
1063 | .config_port = bfin_serial_config_port, | |
1064 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
1065 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
1066 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1067 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
1068 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
1069 | #endif | |
1070 | #ifdef CONFIG_CONSOLE_POLL | |
1071 | .poll_put_char = bfin_serial_poll_put_char, | |
1072 | .poll_get_char = bfin_serial_poll_get_char, | |
1073 | #endif | |
194de561 BW |
1074 | }; |
1075 | ||
6f95570e SZ |
1076 | static void __init bfin_serial_hw_init(void) |
1077 | { | |
1078 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
1079 | peripheral_request(P_UART0_TX, DRIVER_NAME); | |
1080 | peripheral_request(P_UART0_RX, DRIVER_NAME); | |
1081 | #endif | |
1082 | ||
1083 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1084 | peripheral_request(P_UART1_TX, DRIVER_NAME); | |
1085 | peripheral_request(P_UART1_RX, DRIVER_NAME); | |
1086 | ||
1087 | # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x) | |
1088 | peripheral_request(P_UART1_RTS, DRIVER_NAME); | |
1089 | peripheral_request(P_UART1_CTS, DRIVER_NAME); | |
1090 | # endif | |
1091 | #endif | |
1092 | ||
1093 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1094 | peripheral_request(P_UART2_TX, DRIVER_NAME); | |
1095 | peripheral_request(P_UART2_RX, DRIVER_NAME); | |
1096 | #endif | |
1097 | ||
1098 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1099 | peripheral_request(P_UART3_TX, DRIVER_NAME); | |
1100 | peripheral_request(P_UART3_RX, DRIVER_NAME); | |
1101 | ||
1102 | # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x) | |
1103 | peripheral_request(P_UART3_RTS, DRIVER_NAME); | |
1104 | peripheral_request(P_UART3_CTS, DRIVER_NAME); | |
1105 | # endif | |
1106 | #endif | |
1107 | } | |
1108 | ||
194de561 BW |
1109 | static void __init bfin_serial_init_ports(void) |
1110 | { | |
1111 | static int first = 1; | |
1112 | int i; | |
1113 | ||
1114 | if (!first) | |
1115 | return; | |
1116 | first = 0; | |
1117 | ||
6f95570e SZ |
1118 | bfin_serial_hw_init(); |
1119 | ||
c9607ecc | 1120 | for (i = 0; i < nr_active_ports; i++) { |
9c529a3d | 1121 | spin_lock_init(&bfin_serial_ports[i].port.lock); |
194de561 | 1122 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 1123 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
1124 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
1125 | bfin_serial_ports[i].port.line = i; | |
1126 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
1127 | bfin_serial_ports[i].port.membase = | |
1128 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
1129 | bfin_serial_ports[i].port.mapbase = | |
1130 | bfin_serial_resource[i].uart_base_addr; | |
1131 | bfin_serial_ports[i].port.irq = | |
1132 | bfin_serial_resource[i].uart_irq; | |
d307d36a SZ |
1133 | bfin_serial_ports[i].status_irq = |
1134 | bfin_serial_resource[i].uart_status_irq; | |
194de561 BW |
1135 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; |
1136 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
1137 | bfin_serial_ports[i].tx_done = 1; | |
1138 | bfin_serial_ports[i].tx_count = 0; | |
1139 | bfin_serial_ports[i].tx_dma_channel = | |
1140 | bfin_serial_resource[i].uart_tx_dma_channel; | |
1141 | bfin_serial_ports[i].rx_dma_channel = | |
1142 | bfin_serial_resource[i].uart_rx_dma_channel; | |
1143 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 | 1144 | #endif |
d307d36a SZ |
1145 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1146 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 BW |
1147 | bfin_serial_ports[i].cts_pin = |
1148 | bfin_serial_resource[i].uart_cts_pin; | |
1149 | bfin_serial_ports[i].rts_pin = | |
1150 | bfin_serial_resource[i].uart_rts_pin; | |
1151 | #endif | |
194de561 BW |
1152 | } |
1153 | } | |
1154 | ||
b6efa1ea | 1155 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1156 | /* |
1157 | * If the port was already initialised (eg, by a boot loader), | |
1158 | * try to determine the current setup. | |
1159 | */ | |
1160 | static void __init | |
1161 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1162 | int *parity, int *bits) | |
1163 | { | |
1164 | unsigned short status; | |
1165 | ||
1166 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1167 | if (status == (ERBFI | ETBEI)) { | |
1168 | /* ok, the port was enabled */ | |
45828b81 | 1169 | u16 lcr, dlh, dll; |
194de561 BW |
1170 | |
1171 | lcr = UART_GET_LCR(uart); | |
1172 | ||
1173 | *parity = 'n'; | |
1174 | if (lcr & PEN) { | |
1175 | if (lcr & EPS) | |
1176 | *parity = 'e'; | |
1177 | else | |
1178 | *parity = 'o'; | |
1179 | } | |
1180 | switch (lcr & 0x03) { | |
1181 | case 0: *bits = 5; break; | |
1182 | case 1: *bits = 6; break; | |
1183 | case 2: *bits = 7; break; | |
1184 | case 3: *bits = 8; break; | |
1185 | } | |
1186 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1187 | UART_SET_DLAB(uart); |
194de561 BW |
1188 | |
1189 | dll = UART_GET_DLL(uart); | |
1190 | dlh = UART_GET_DLH(uart); | |
1191 | ||
1192 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1193 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1194 | |
1195 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1196 | } | |
71cc2c21 | 1197 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1198 | } |
0ae53640 | 1199 | |
0ae53640 | 1200 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1201 | |
1202 | static int __init | |
1203 | bfin_serial_console_setup(struct console *co, char *options) | |
1204 | { | |
1205 | struct bfin_serial_port *uart; | |
1206 | int baud = 57600; | |
1207 | int bits = 8; | |
1208 | int parity = 'n'; | |
d307d36a SZ |
1209 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1210 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 | 1211 | int flow = 'r'; |
b6efa1ea | 1212 | # else |
194de561 | 1213 | int flow = 'n'; |
0ae53640 | 1214 | # endif |
194de561 BW |
1215 | |
1216 | /* | |
1217 | * Check whether an invalid uart number has been specified, and | |
1218 | * if so, search for the first available port that does have | |
1219 | * console support. | |
1220 | */ | |
c9607ecc | 1221 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1222 | co->index = 0; |
1223 | uart = &bfin_serial_ports[co->index]; | |
1224 | ||
1225 | if (options) | |
1226 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1227 | else | |
1228 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1229 | ||
1230 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1231 | } |
1232 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1233 | defined (CONFIG_EARLY_PRINTK) */ | |
1234 | ||
1235 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1236 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1237 | { | |
1238 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1239 | while (!(UART_GET_LSR(uart) & THRE)) | |
1240 | barrier(); | |
1241 | UART_PUT_CHAR(uart, ch); | |
1242 | SSYNC(); | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * Interrupts are disabled on entering | |
1247 | */ | |
1248 | static void | |
1249 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1250 | { | |
1251 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
59e4e3e6 | 1252 | unsigned long flags; |
0ae53640 RG |
1253 | |
1254 | spin_lock_irqsave(&uart->port.lock, flags); | |
1255 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1256 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1257 | ||
194de561 BW |
1258 | } |
1259 | ||
194de561 BW |
1260 | static struct console bfin_serial_console = { |
1261 | .name = BFIN_SERIAL_NAME, | |
1262 | .write = bfin_serial_console_write, | |
1263 | .device = uart_console_device, | |
1264 | .setup = bfin_serial_console_setup, | |
1265 | .flags = CON_PRINTBUFFER, | |
1266 | .index = -1, | |
1267 | .data = &bfin_serial_reg, | |
1268 | }; | |
1269 | ||
1270 | static int __init bfin_serial_rs_console_init(void) | |
1271 | { | |
1272 | bfin_serial_init_ports(); | |
1273 | register_console(&bfin_serial_console); | |
52e15f0e | 1274 | |
194de561 BW |
1275 | return 0; |
1276 | } | |
1277 | console_initcall(bfin_serial_rs_console_init); | |
1278 | ||
1279 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1280 | #else | |
1281 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1282 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1283 | ||
1284 | ||
1285 | #ifdef CONFIG_EARLY_PRINTK | |
1286 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1287 | { | |
1288 | unsigned timeout = 0xffff; | |
1289 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1290 | ||
1291 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1292 | cpu_relax(); | |
1293 | UART_PUT_CHAR(uart, ch); | |
1294 | } | |
1295 | ||
1296 | static __init void early_serial_write(struct console *con, const char *s, | |
1297 | unsigned int n) | |
1298 | { | |
1299 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1300 | unsigned int i; | |
1301 | ||
1302 | for (i = 0; i < n; i++, s++) { | |
1303 | if (*s == '\n') | |
1304 | early_serial_putc(&uart->port, '\r'); | |
1305 | early_serial_putc(&uart->port, *s); | |
1306 | } | |
1307 | } | |
1308 | ||
7de7c55b RG |
1309 | /* |
1310 | * This should have a .setup or .early_setup in it, but then things get called | |
1311 | * without the command line options, and the baud rate gets messed up - so | |
1312 | * don't let the common infrastructure play with things. (see calls to setup | |
1313 | * & earlysetup in ./kernel/printk.c:register_console() | |
1314 | */ | |
c1113400 | 1315 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1316 | .name = "early_BFuart", |
1317 | .write = early_serial_write, | |
1318 | .device = uart_console_device, | |
1319 | .flags = CON_PRINTBUFFER, | |
0ae53640 RG |
1320 | .index = -1, |
1321 | .data = &bfin_serial_reg, | |
1322 | }; | |
1323 | ||
1324 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1325 | unsigned int cflag) | |
1326 | { | |
1327 | struct bfin_serial_port *uart; | |
1328 | struct ktermios t; | |
1329 | ||
c9607ecc | 1330 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1331 | port = 0; |
1332 | bfin_serial_init_ports(); | |
1333 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1334 | uart = &bfin_serial_ports[port]; |
1335 | t.c_cflag = cflag; | |
1336 | t.c_iflag = 0; | |
1337 | t.c_oflag = 0; | |
1338 | t.c_lflag = ICANON; | |
1339 | t.c_line = port; | |
1340 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1341 | return &bfin_early_serial_console; | |
1342 | } | |
1343 | ||
b6efa1ea | 1344 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1345 | |
1346 | static struct uart_driver bfin_serial_reg = { | |
1347 | .owner = THIS_MODULE, | |
1348 | .driver_name = "bfin-uart", | |
1349 | .dev_name = BFIN_SERIAL_NAME, | |
1350 | .major = BFIN_SERIAL_MAJOR, | |
1351 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1352 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1353 | .cons = BFIN_SERIAL_CONSOLE, |
1354 | }; | |
1355 | ||
1356 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1357 | { | |
ccfbc3e1 | 1358 | int i; |
194de561 | 1359 | |
c9607ecc | 1360 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1361 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1362 | continue; | |
1363 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1364 | } | |
194de561 BW |
1365 | |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static int bfin_serial_resume(struct platform_device *dev) | |
1370 | { | |
ccfbc3e1 | 1371 | int i; |
194de561 | 1372 | |
c9607ecc | 1373 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1374 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1375 | continue; | |
1376 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1377 | } | |
194de561 BW |
1378 | |
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | static int bfin_serial_probe(struct platform_device *dev) | |
1383 | { | |
1384 | struct resource *res = dev->resource; | |
1385 | int i; | |
1386 | ||
1387 | for (i = 0; i < dev->num_resources; i++, res++) | |
1388 | if (res->flags & IORESOURCE_MEM) | |
1389 | break; | |
1390 | ||
1391 | if (i < dev->num_resources) { | |
c9607ecc | 1392 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1393 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1394 | continue; | |
1395 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1396 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1397 | } |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
ccfbc3e1 | 1403 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1404 | { |
ccfbc3e1 | 1405 | int i; |
194de561 | 1406 | |
c9607ecc | 1407 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1408 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1409 | continue; | |
1410 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1411 | bfin_serial_ports[i].port.dev = NULL; | |
d307d36a SZ |
1412 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1413 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
ccfbc3e1 SZ |
1414 | gpio_free(bfin_serial_ports[i].cts_pin); |
1415 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1416 | #endif |
ccfbc3e1 | 1417 | } |
194de561 BW |
1418 | |
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | static struct platform_driver bfin_serial_driver = { | |
1423 | .probe = bfin_serial_probe, | |
1424 | .remove = bfin_serial_remove, | |
1425 | .suspend = bfin_serial_suspend, | |
1426 | .resume = bfin_serial_resume, | |
1427 | .driver = { | |
1428 | .name = "bfin-uart", | |
e169c139 | 1429 | .owner = THIS_MODULE, |
194de561 BW |
1430 | }, |
1431 | }; | |
1432 | ||
1433 | static int __init bfin_serial_init(void) | |
1434 | { | |
1435 | int ret; | |
1436 | ||
1437 | pr_info("Serial: Blackfin serial driver\n"); | |
1438 | ||
1439 | bfin_serial_init_ports(); | |
1440 | ||
1441 | ret = uart_register_driver(&bfin_serial_reg); | |
1442 | if (ret == 0) { | |
1443 | ret = platform_driver_register(&bfin_serial_driver); | |
1444 | if (ret) { | |
1445 | pr_debug("uart register failed\n"); | |
1446 | uart_unregister_driver(&bfin_serial_reg); | |
1447 | } | |
1448 | } | |
1449 | return ret; | |
1450 | } | |
1451 | ||
1452 | static void __exit bfin_serial_exit(void) | |
1453 | { | |
1454 | platform_driver_unregister(&bfin_serial_driver); | |
1455 | uart_unregister_driver(&bfin_serial_reg); | |
1456 | } | |
1457 | ||
52e15f0e | 1458 | |
194de561 BW |
1459 | module_init(bfin_serial_init); |
1460 | module_exit(bfin_serial_exit); | |
1461 | ||
1462 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1463 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1464 | MODULE_LICENSE("GPL"); | |
1465 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1466 | MODULE_ALIAS("platform:bfin-uart"); |