Commit | Line | Data |
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194de561 BW |
1 | /* |
2 | * File: drivers/serial/bfin_5xx.c | |
3 | * Based on: Based on drivers/serial/sa1100.c | |
4 | * Author: Aubrey Li <aubrey.li@analog.com> | |
5 | * | |
6 | * Created: | |
7 | * Description: Driver for blackfin 5xx serial ports | |
8 | * | |
194de561 BW |
9 | * Modified: |
10 | * Copyright 2006 Analog Devices Inc. | |
11 | * | |
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, see the file COPYING, or write | |
26 | * to the Free Software Foundation, Inc., | |
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
28 | */ | |
29 | ||
30 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
31 | #define SUPPORT_SYSRQ | |
32 | #endif | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/sysrq.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/tty.h> | |
41 | #include <linux/tty_flip.h> | |
42 | #include <linux/serial_core.h> | |
43 | ||
474f1a66 SZ |
44 | #ifdef CONFIG_KGDB_UART |
45 | #include <linux/kgdb.h> | |
46 | #include <asm/irq_regs.h> | |
47 | #endif | |
48 | ||
194de561 BW |
49 | #include <asm/gpio.h> |
50 | #include <asm/mach/bfin_serial_5xx.h> | |
51 | ||
52 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
53 | #include <linux/dma-mapping.h> | |
54 | #include <asm/io.h> | |
55 | #include <asm/irq.h> | |
56 | #include <asm/cacheflush.h> | |
57 | #endif | |
58 | ||
59 | /* UART name and device definitions */ | |
60 | #define BFIN_SERIAL_NAME "ttyBF" | |
61 | #define BFIN_SERIAL_MAJOR 204 | |
62 | #define BFIN_SERIAL_MINOR 64 | |
63 | ||
64 | /* | |
65 | * Setup for console. Argument comes from the menuconfig | |
66 | */ | |
67 | #define DMA_RX_XCOUNT 512 | |
68 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
69 | ||
70 | #define DMA_RX_FLUSH_JIFFIES 5 | |
71 | ||
72 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
73 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
74 | #else | |
75 | static void bfin_serial_do_work(struct work_struct *work); | |
76 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); | |
194de561 BW |
77 | #endif |
78 | ||
79 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); | |
80 | ||
81 | /* | |
82 | * interrupts are disabled on entry | |
83 | */ | |
84 | static void bfin_serial_stop_tx(struct uart_port *port) | |
85 | { | |
86 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1b73351c | 87 | #if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA) |
759eb040 SZ |
88 | unsigned short ier; |
89 | #endif | |
194de561 | 90 | |
f4d640c9 RH |
91 | while (!(UART_GET_LSR(uart) & TEMT)) |
92 | continue; | |
f4d640c9 | 93 | |
194de561 BW |
94 | #ifdef CONFIG_SERIAL_BFIN_DMA |
95 | disable_dma(uart->tx_dma_channel); | |
f4d640c9 RH |
96 | #else |
97 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
98 | /* Clear TFI bit */ |
99 | UART_PUT_LSR(uart, TFI); | |
100 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 | 101 | #else |
194de561 BW |
102 | ier = UART_GET_IER(uart); |
103 | ier &= ~ETBEI; | |
104 | UART_PUT_IER(uart, ier); | |
105 | #endif | |
f4d640c9 | 106 | #endif |
194de561 BW |
107 | } |
108 | ||
109 | /* | |
110 | * port is locked and interrupts are disabled | |
111 | */ | |
112 | static void bfin_serial_start_tx(struct uart_port *port) | |
113 | { | |
114 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
115 | ||
116 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
117 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 RH |
118 | #else |
119 | #ifdef CONFIG_BF54x | |
120 | UART_SET_IER(uart, ETBEI); | |
194de561 BW |
121 | #else |
122 | unsigned short ier; | |
123 | ier = UART_GET_IER(uart); | |
124 | ier |= ETBEI; | |
125 | UART_PUT_IER(uart, ier); | |
194de561 | 126 | #endif |
a359cca7 | 127 | bfin_serial_tx_chars(uart); |
f4d640c9 | 128 | #endif |
194de561 BW |
129 | } |
130 | ||
131 | /* | |
132 | * Interrupts are enabled | |
133 | */ | |
134 | static void bfin_serial_stop_rx(struct uart_port *port) | |
135 | { | |
136 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
a359cca7 SZ |
137 | #ifdef CONFIG_KGDB_UART |
138 | if (uart->port.line != CONFIG_KGDB_UART_PORT) { | |
139 | #endif | |
f4d640c9 RH |
140 | #ifdef CONFIG_BF54x |
141 | UART_CLEAR_IER(uart, ERBFI); | |
142 | #else | |
194de561 BW |
143 | unsigned short ier; |
144 | ||
145 | ier = UART_GET_IER(uart); | |
146 | ier &= ~ERBFI; | |
147 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 148 | #endif |
a359cca7 SZ |
149 | #ifdef CONFIG_KGDB_UART |
150 | } | |
151 | #endif | |
194de561 BW |
152 | } |
153 | ||
154 | /* | |
155 | * Set the modem control timer to fire immediately. | |
156 | */ | |
157 | static void bfin_serial_enable_ms(struct uart_port *port) | |
158 | { | |
159 | } | |
160 | ||
474f1a66 SZ |
161 | #ifdef CONFIG_KGDB_UART |
162 | static int kgdb_entry_state; | |
163 | ||
164 | void kgdb_put_debug_char(int chr) | |
165 | { | |
166 | struct bfin_serial_port *uart; | |
167 | ||
168 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
169 | uart = &bfin_serial_ports[0]; | |
170 | else | |
171 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
172 | ||
173 | while (!(UART_GET_LSR(uart) & THRE)) { | |
d5148ffa | 174 | SSYNC(); |
474f1a66 | 175 | } |
a359cca7 SZ |
176 | |
177 | #ifndef CONFIG_BF54x | |
474f1a66 | 178 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); |
d5148ffa | 179 | SSYNC(); |
a359cca7 | 180 | #endif |
474f1a66 | 181 | UART_PUT_CHAR(uart, (unsigned char)chr); |
d5148ffa | 182 | SSYNC(); |
474f1a66 SZ |
183 | } |
184 | ||
185 | int kgdb_get_debug_char(void) | |
186 | { | |
187 | struct bfin_serial_port *uart; | |
188 | unsigned char chr; | |
189 | ||
190 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
191 | uart = &bfin_serial_ports[0]; | |
192 | else | |
193 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
194 | ||
195 | while(!(UART_GET_LSR(uart) & DR)) { | |
d5148ffa | 196 | SSYNC(); |
474f1a66 | 197 | } |
a359cca7 | 198 | #ifndef CONFIG_BF54x |
474f1a66 | 199 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); |
d5148ffa | 200 | SSYNC(); |
a359cca7 | 201 | #endif |
474f1a66 | 202 | chr = UART_GET_CHAR(uart); |
d5148ffa | 203 | SSYNC(); |
474f1a66 SZ |
204 | |
205 | return chr; | |
206 | } | |
207 | #endif | |
208 | ||
8851c71e MF |
209 | #if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO) |
210 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) | |
211 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
212 | #else | |
213 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
214 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
215 | #endif | |
216 | ||
194de561 | 217 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
218 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
219 | { | |
2ac5ee47 | 220 | struct tty_struct *tty = uart->port.info->tty; |
194de561 | 221 | unsigned int status, ch, flg; |
8851c71e | 222 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
474f1a66 SZ |
223 | #ifdef CONFIG_KGDB_UART |
224 | struct pt_regs *regs = get_irq_regs(); | |
225 | #endif | |
194de561 | 226 | |
759eb040 | 227 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
228 | UART_CLEAR_LSR(uart); |
229 | ||
230 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
231 | uart->port.icount.rx++; |
232 | ||
474f1a66 SZ |
233 | #ifdef CONFIG_KGDB_UART |
234 | if (uart->port.line == CONFIG_KGDB_UART_PORT) { | |
235 | if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */ | |
236 | kgdb_breakkey_pressed(regs); | |
237 | return; | |
238 | } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */ | |
239 | kgdb_entry_state = 1; | |
240 | } else if (kgdb_entry_state == 1 && ch == 'q') { | |
241 | kgdb_entry_state = 0; | |
242 | kgdb_breakkey_pressed(regs); | |
243 | return; | |
244 | } else if (ch == 0x3) {/* Ctrl + C */ | |
245 | kgdb_entry_state = 0; | |
246 | kgdb_breakkey_pressed(regs); | |
247 | return; | |
248 | } else { | |
249 | kgdb_entry_state = 0; | |
250 | } | |
251 | } | |
252 | #endif | |
bbf275f0 MF |
253 | |
254 | if (ANOMALY_05000230) { | |
8851c71e MF |
255 | /* The BF533 (and BF561) family of processors have a nice anomaly |
256 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 257 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
258 | * character comes across. Due to the nature of the flood, it is |
259 | * not possible to reliably catch bytes that are sent too quickly | |
260 | * after this break. So application code talking to the Blackfin | |
261 | * which sends a break signal must allow at least 1.5 character | |
262 | * times after the end of the break for things to stabilize. This | |
263 | * timeout was picked as it must absolutely be larger than 1 | |
264 | * character time +/- some percent. So 1.5 sounds good. All other | |
265 | * Blackfin families operate properly. Woo. | |
bbf275f0 MF |
266 | * Note: While Anomaly 05000230 does not directly address this, |
267 | * the changes that went in for it also fixed this issue. | |
8851c71e | 268 | * That anomaly was fixed in 0.5+ silicon. I like bunnies. |
bbf275f0 | 269 | */ |
8851c71e MF |
270 | if (anomaly_start.tv_sec) { |
271 | struct timeval curr; | |
272 | suseconds_t usecs; | |
273 | ||
274 | if ((~ch & (~ch + 1)) & 0xff) | |
275 | goto known_good_char; | |
276 | ||
277 | do_gettimeofday(&curr); | |
278 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
279 | goto known_good_char; | |
280 | ||
281 | usecs = 0; | |
282 | if (curr.tv_sec != anomaly_start.tv_sec) | |
283 | usecs += USEC_PER_SEC; | |
284 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
285 | ||
286 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
287 | goto known_good_char; | |
288 | ||
289 | if (ch) | |
290 | anomaly_start.tv_sec = 0; | |
291 | else | |
292 | anomaly_start = curr; | |
293 | ||
294 | return; | |
295 | ||
296 | known_good_char: | |
297 | anomaly_start.tv_sec = 0; | |
bbf275f0 | 298 | } |
194de561 | 299 | } |
194de561 BW |
300 | |
301 | if (status & BI) { | |
bbf275f0 | 302 | if (ANOMALY_05000230) |
8851c71e MF |
303 | if (bfin_revid() < 5) |
304 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
305 | uart->port.icount.brk++; |
306 | if (uart_handle_break(&uart->port)) | |
307 | goto ignore_char; | |
9808901b | 308 | status &= ~(PE | FE); |
2ac5ee47 MF |
309 | } |
310 | if (status & PE) | |
194de561 | 311 | uart->port.icount.parity++; |
2ac5ee47 | 312 | if (status & OE) |
194de561 | 313 | uart->port.icount.overrun++; |
2ac5ee47 | 314 | if (status & FE) |
194de561 | 315 | uart->port.icount.frame++; |
2ac5ee47 MF |
316 | |
317 | status &= uart->port.read_status_mask; | |
318 | ||
319 | if (status & BI) | |
320 | flg = TTY_BREAK; | |
321 | else if (status & PE) | |
322 | flg = TTY_PARITY; | |
323 | else if (status & FE) | |
324 | flg = TTY_FRAME; | |
325 | else | |
194de561 BW |
326 | flg = TTY_NORMAL; |
327 | ||
328 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
329 | goto ignore_char; | |
194de561 | 330 | |
2ac5ee47 MF |
331 | uart_insert_char(&uart->port, status, OE, ch, flg); |
332 | ||
333 | ignore_char: | |
334 | tty_flip_buffer_push(tty); | |
194de561 BW |
335 | } |
336 | ||
337 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
338 | { | |
339 | struct circ_buf *xmit = &uart->port.info->xmit; | |
340 | ||
341 | if (uart->port.x_char) { | |
342 | UART_PUT_CHAR(uart, uart->port.x_char); | |
343 | uart->port.icount.tx++; | |
344 | uart->port.x_char = 0; | |
194de561 BW |
345 | } |
346 | /* | |
347 | * Check the modem control lines before | |
348 | * transmitting anything. | |
349 | */ | |
350 | bfin_serial_mctrl_check(uart); | |
351 | ||
352 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
353 | bfin_serial_stop_tx(&uart->port); | |
354 | return; | |
355 | } | |
356 | ||
759eb040 SZ |
357 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
358 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
359 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
360 | uart->port.icount.tx++; | |
361 | SSYNC(); | |
362 | } | |
194de561 BW |
363 | |
364 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
365 | uart_write_wakeup(&uart->port); | |
366 | ||
367 | if (uart_circ_empty(xmit)) | |
368 | bfin_serial_stop_tx(&uart->port); | |
369 | } | |
370 | ||
5c4e472b AL |
371 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
372 | { | |
373 | struct bfin_serial_port *uart = dev_id; | |
374 | ||
f4d640c9 | 375 | spin_lock(&uart->port.lock); |
0bcfd70e | 376 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 377 | bfin_serial_rx_chars(uart); |
f4d640c9 | 378 | spin_unlock(&uart->port.lock); |
759eb040 | 379 | |
5c4e472b AL |
380 | return IRQ_HANDLED; |
381 | } | |
382 | ||
383 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
384 | { |
385 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 386 | |
f4d640c9 | 387 | spin_lock(&uart->port.lock); |
0bcfd70e | 388 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 389 | bfin_serial_tx_chars(uart); |
f4d640c9 | 390 | spin_unlock(&uart->port.lock); |
759eb040 | 391 | |
194de561 BW |
392 | return IRQ_HANDLED; |
393 | } | |
394 | ||
5c4e472b | 395 | |
194de561 BW |
396 | static void bfin_serial_do_work(struct work_struct *work) |
397 | { | |
398 | struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue); | |
399 | ||
400 | bfin_serial_mctrl_check(uart); | |
401 | } | |
194de561 BW |
402 | #endif |
403 | ||
404 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
405 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
406 | { | |
407 | struct circ_buf *xmit = &uart->port.info->xmit; | |
408 | unsigned short ier; | |
409 | int flags = 0; | |
410 | ||
411 | if (!uart->tx_done) | |
412 | return; | |
194de561 BW |
413 | uart->tx_done = 0; |
414 | ||
1b73351c SZ |
415 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
416 | bfin_serial_stop_tx(&uart->port); | |
417 | uart->tx_done = 1; | |
418 | return; | |
419 | } | |
420 | ||
194de561 BW |
421 | if (uart->port.x_char) { |
422 | UART_PUT_CHAR(uart, uart->port.x_char); | |
423 | uart->port.icount.tx++; | |
424 | uart->port.x_char = 0; | |
194de561 | 425 | } |
1b73351c | 426 | |
194de561 BW |
427 | /* |
428 | * Check the modem control lines before | |
429 | * transmitting anything. | |
430 | */ | |
431 | bfin_serial_mctrl_check(uart); | |
432 | ||
194de561 BW |
433 | spin_lock_irqsave(&uart->port.lock, flags); |
434 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
435 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
436 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
437 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
438 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
439 | set_dma_config(uart->tx_dma_channel, | |
440 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
441 | INTR_ON_BUF, | |
442 | DIMENSION_LINEAR, | |
2047e40d MH |
443 | DATA_SIZE_8, |
444 | DMA_SYNC_RESTART)); | |
194de561 BW |
445 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
446 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
447 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
448 | enable_dma(uart->tx_dma_channel); | |
99ee7b5f SZ |
449 | |
450 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); | |
451 | uart->port.icount.tx += uart->tx_count; | |
452 | ||
f4d640c9 RH |
453 | #ifdef CONFIG_BF54x |
454 | UART_SET_IER(uart, ETBEI); | |
455 | #else | |
194de561 BW |
456 | ier = UART_GET_IER(uart); |
457 | ier |= ETBEI; | |
458 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 459 | #endif |
194de561 BW |
460 | spin_unlock_irqrestore(&uart->port.lock, flags); |
461 | } | |
462 | ||
2ac5ee47 | 463 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 BW |
464 | { |
465 | struct tty_struct *tty = uart->port.info->tty; | |
466 | int i, flg, status; | |
467 | ||
468 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
469 | UART_CLEAR_LSR(uart); |
470 | ||
194de561 BW |
471 | uart->port.icount.rx += CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, UART_XMIT_SIZE);; |
472 | ||
473 | if (status & BI) { | |
474 | uart->port.icount.brk++; | |
475 | if (uart_handle_break(&uart->port)) | |
476 | goto dma_ignore_char; | |
9808901b | 477 | status &= ~(PE | FE); |
2ac5ee47 MF |
478 | } |
479 | if (status & PE) | |
194de561 | 480 | uart->port.icount.parity++; |
2ac5ee47 | 481 | if (status & OE) |
194de561 | 482 | uart->port.icount.overrun++; |
2ac5ee47 | 483 | if (status & FE) |
194de561 | 484 | uart->port.icount.frame++; |
2ac5ee47 MF |
485 | |
486 | status &= uart->port.read_status_mask; | |
487 | ||
488 | if (status & BI) | |
489 | flg = TTY_BREAK; | |
490 | else if (status & PE) | |
491 | flg = TTY_PARITY; | |
492 | else if (status & FE) | |
493 | flg = TTY_FRAME; | |
494 | else | |
194de561 BW |
495 | flg = TTY_NORMAL; |
496 | ||
497 | for (i = uart->rx_dma_buf.head; i < uart->rx_dma_buf.tail; i++) { | |
498 | if (uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) | |
499 | goto dma_ignore_char; | |
2ac5ee47 | 500 | uart_insert_char(&uart->port, status, OE, uart->rx_dma_buf.buf[i], flg); |
194de561 | 501 | } |
2ac5ee47 MF |
502 | |
503 | dma_ignore_char: | |
194de561 BW |
504 | tty_flip_buffer_push(tty); |
505 | } | |
506 | ||
507 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
508 | { | |
509 | int x_pos, pos; | |
510 | int flags = 0; | |
511 | ||
194de561 BW |
512 | spin_lock_irqsave(&uart->port.lock, flags); |
513 | x_pos = DMA_RX_XCOUNT - get_dma_curr_xcount(uart->rx_dma_channel); | |
514 | if (x_pos == DMA_RX_XCOUNT) | |
515 | x_pos = 0; | |
516 | ||
517 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
518 | ||
519 | if (pos>uart->rx_dma_buf.tail) { | |
520 | uart->rx_dma_buf.tail = pos; | |
521 | bfin_serial_dma_rx_chars(uart); | |
522 | uart->rx_dma_buf.head = uart->rx_dma_buf.tail; | |
523 | } | |
524 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
525 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
526 | add_timer(&(uart->rx_dma_timer)); | |
527 | } | |
528 | ||
529 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
530 | { | |
531 | struct bfin_serial_port *uart = dev_id; | |
532 | struct circ_buf *xmit = &uart->port.info->xmit; | |
533 | unsigned short ier; | |
534 | ||
535 | spin_lock(&uart->port.lock); | |
536 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
537 | clear_dma_irqstat(uart->tx_dma_channel); | |
538 | disable_dma(uart->tx_dma_channel); | |
f4d640c9 RH |
539 | #ifdef CONFIG_BF54x |
540 | UART_CLEAR_IER(uart, ETBEI); | |
541 | #else | |
194de561 BW |
542 | ier = UART_GET_IER(uart); |
543 | ier &= ~ETBEI; | |
544 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 545 | #endif |
194de561 BW |
546 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
547 | uart_write_wakeup(&uart->port); | |
548 | ||
194de561 | 549 | uart->tx_done = 1; |
1b73351c SZ |
550 | |
551 | bfin_serial_dma_tx_chars(uart); | |
194de561 BW |
552 | } |
553 | ||
554 | spin_unlock(&uart->port.lock); | |
555 | return IRQ_HANDLED; | |
556 | } | |
557 | ||
558 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
559 | { | |
560 | struct bfin_serial_port *uart = dev_id; | |
561 | unsigned short irqstat; | |
562 | ||
563 | uart->rx_dma_nrows++; | |
564 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) { | |
565 | uart->rx_dma_nrows = 0; | |
566 | uart->rx_dma_buf.tail = DMA_RX_XCOUNT*DMA_RX_YCOUNT; | |
567 | bfin_serial_dma_rx_chars(uart); | |
568 | uart->rx_dma_buf.head = uart->rx_dma_buf.tail = 0; | |
569 | } | |
570 | spin_lock(&uart->port.lock); | |
571 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
572 | clear_dma_irqstat(uart->rx_dma_channel); | |
573 | ||
574 | spin_unlock(&uart->port.lock); | |
575 | return IRQ_HANDLED; | |
576 | } | |
577 | #endif | |
578 | ||
579 | /* | |
580 | * Return TIOCSER_TEMT when transmitter is not busy. | |
581 | */ | |
582 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
583 | { | |
584 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
585 | unsigned short lsr; | |
586 | ||
587 | lsr = UART_GET_LSR(uart); | |
588 | if (lsr & TEMT) | |
589 | return TIOCSER_TEMT; | |
590 | else | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
595 | { | |
596 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
597 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
598 | if (uart->cts_pin < 0) | |
599 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
600 | ||
601 | if (gpio_get_value(uart->cts_pin)) | |
602 | return TIOCM_DSR | TIOCM_CAR; | |
603 | else | |
604 | #endif | |
605 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
606 | } | |
607 | ||
608 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
609 | { | |
610 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
611 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
612 | if (uart->rts_pin < 0) | |
613 | return; | |
614 | ||
615 | if (mctrl & TIOCM_RTS) | |
616 | gpio_set_value(uart->rts_pin, 0); | |
617 | else | |
618 | gpio_set_value(uart->rts_pin, 1); | |
619 | #endif | |
620 | } | |
621 | ||
622 | /* | |
623 | * Handle any change of modem status signal since we were last called. | |
624 | */ | |
625 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |
626 | { | |
627 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
628 | unsigned int status; | |
629 | # ifdef CONFIG_SERIAL_BFIN_DMA | |
630 | struct uart_info *info = uart->port.info; | |
631 | struct tty_struct *tty = info->tty; | |
632 | ||
633 | status = bfin_serial_get_mctrl(&uart->port); | |
634 | if (!(status & TIOCM_CTS)) { | |
635 | tty->hw_stopped = 1; | |
636 | } else { | |
637 | tty->hw_stopped = 0; | |
638 | } | |
639 | # else | |
640 | status = bfin_serial_get_mctrl(&uart->port); | |
641 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
642 | if (!(status & TIOCM_CTS)) | |
643 | schedule_work(&uart->cts_workqueue); | |
644 | # endif | |
645 | #endif | |
646 | } | |
647 | ||
648 | /* | |
649 | * Interrupts are always disabled. | |
650 | */ | |
651 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
652 | { | |
cf686762 MF |
653 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
654 | u16 lcr = UART_GET_LCR(uart); | |
655 | if (break_state) | |
656 | lcr |= SB; | |
657 | else | |
658 | lcr &= ~SB; | |
659 | UART_PUT_LCR(uart, lcr); | |
660 | SSYNC(); | |
194de561 BW |
661 | } |
662 | ||
663 | static int bfin_serial_startup(struct uart_port *port) | |
664 | { | |
665 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
666 | ||
667 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
668 | dma_addr_t dma_handle; | |
669 | ||
670 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
671 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
672 | return -EBUSY; | |
673 | } | |
674 | ||
675 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
676 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
677 | free_dma(uart->rx_dma_channel); | |
678 | return -EBUSY; | |
679 | } | |
680 | ||
681 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
682 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
683 | ||
684 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
685 | uart->rx_dma_buf.head = 0; | |
686 | uart->rx_dma_buf.tail = 0; | |
687 | uart->rx_dma_nrows = 0; | |
688 | ||
689 | set_dma_config(uart->rx_dma_channel, | |
690 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
691 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
692 | DATA_SIZE_8, |
693 | DMA_SYNC_RESTART)); | |
194de561 BW |
694 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
695 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
696 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
697 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
698 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
699 | enable_dma(uart->rx_dma_channel); | |
700 | ||
701 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
702 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
703 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
704 | add_timer(&(uart->rx_dma_timer)); | |
705 | #else | |
a359cca7 SZ |
706 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
707 | "BFIN_UART_RX", uart)) { | |
474f1a66 | 708 | # ifdef CONFIG_KGDB_UART |
a359cca7 | 709 | if (uart->port.line != CONFIG_KGDB_UART_PORT) { |
474f1a66 | 710 | # endif |
194de561 BW |
711 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
712 | return -EBUSY; | |
a359cca7 SZ |
713 | # ifdef CONFIG_KGDB_UART |
714 | } | |
715 | # endif | |
194de561 BW |
716 | } |
717 | ||
a359cca7 | 718 | |
194de561 | 719 | if (request_irq |
5c4e472b | 720 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
721 | "BFIN_UART_TX", uart)) { |
722 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
723 | free_irq(uart->port.irq, uart); | |
724 | return -EBUSY; | |
725 | } | |
726 | #endif | |
f4d640c9 RH |
727 | #ifdef CONFIG_BF54x |
728 | UART_SET_IER(uart, ERBFI); | |
729 | #else | |
194de561 | 730 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); |
f4d640c9 | 731 | #endif |
194de561 BW |
732 | return 0; |
733 | } | |
734 | ||
735 | static void bfin_serial_shutdown(struct uart_port *port) | |
736 | { | |
737 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
738 | ||
739 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
740 | disable_dma(uart->tx_dma_channel); | |
741 | free_dma(uart->tx_dma_channel); | |
742 | disable_dma(uart->rx_dma_channel); | |
743 | free_dma(uart->rx_dma_channel); | |
744 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 745 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 746 | #else |
474f1a66 SZ |
747 | #ifdef CONFIG_KGDB_UART |
748 | if (uart->port.line != CONFIG_KGDB_UART_PORT) | |
749 | #endif | |
194de561 BW |
750 | free_irq(uart->port.irq, uart); |
751 | free_irq(uart->port.irq+1, uart); | |
752 | #endif | |
753 | } | |
754 | ||
755 | static void | |
756 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
757 | struct ktermios *old) | |
758 | { | |
759 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
760 | unsigned long flags; | |
761 | unsigned int baud, quot; | |
762 | unsigned short val, ier, lsr, lcr = 0; | |
763 | ||
764 | switch (termios->c_cflag & CSIZE) { | |
765 | case CS8: | |
766 | lcr = WLS(8); | |
767 | break; | |
768 | case CS7: | |
769 | lcr = WLS(7); | |
770 | break; | |
771 | case CS6: | |
772 | lcr = WLS(6); | |
773 | break; | |
774 | case CS5: | |
775 | lcr = WLS(5); | |
776 | break; | |
777 | default: | |
778 | printk(KERN_ERR "%s: word lengh not supported\n", | |
779 | __FUNCTION__); | |
780 | } | |
781 | ||
782 | if (termios->c_cflag & CSTOPB) | |
783 | lcr |= STB; | |
19aa6382 | 784 | if (termios->c_cflag & PARENB) |
194de561 | 785 | lcr |= PEN; |
19aa6382 MF |
786 | if (!(termios->c_cflag & PARODD)) |
787 | lcr |= EPS; | |
788 | if (termios->c_cflag & CMSPAR) | |
789 | lcr |= STP; | |
194de561 | 790 | |
2ac5ee47 MF |
791 | port->read_status_mask = OE; |
792 | if (termios->c_iflag & INPCK) | |
793 | port->read_status_mask |= (FE | PE); | |
794 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
795 | port->read_status_mask |= BI; | |
194de561 | 796 | |
2ac5ee47 MF |
797 | /* |
798 | * Characters to ignore | |
799 | */ | |
800 | port->ignore_status_mask = 0; | |
801 | if (termios->c_iflag & IGNPAR) | |
802 | port->ignore_status_mask |= FE | PE; | |
803 | if (termios->c_iflag & IGNBRK) { | |
804 | port->ignore_status_mask |= BI; | |
805 | /* | |
806 | * If we're ignoring parity and break indicators, | |
807 | * ignore overruns too (for real raw support). | |
808 | */ | |
809 | if (termios->c_iflag & IGNPAR) | |
810 | port->ignore_status_mask |= OE; | |
811 | } | |
194de561 BW |
812 | |
813 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
814 | quot = uart_get_divisor(port, baud); | |
815 | spin_lock_irqsave(&uart->port.lock, flags); | |
816 | ||
8851c71e MF |
817 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
818 | ||
194de561 BW |
819 | do { |
820 | lsr = UART_GET_LSR(uart); | |
821 | } while (!(lsr & TEMT)); | |
822 | ||
823 | /* Disable UART */ | |
824 | ier = UART_GET_IER(uart); | |
f4d640c9 RH |
825 | #ifdef CONFIG_BF54x |
826 | UART_CLEAR_IER(uart, 0xF); | |
827 | #else | |
194de561 | 828 | UART_PUT_IER(uart, 0); |
f4d640c9 | 829 | #endif |
194de561 | 830 | |
f4d640c9 | 831 | #ifndef CONFIG_BF54x |
194de561 BW |
832 | /* Set DLAB in LCR to Access DLL and DLH */ |
833 | val = UART_GET_LCR(uart); | |
834 | val |= DLAB; | |
835 | UART_PUT_LCR(uart, val); | |
836 | SSYNC(); | |
f4d640c9 | 837 | #endif |
194de561 BW |
838 | |
839 | UART_PUT_DLL(uart, quot & 0xFF); | |
840 | SSYNC(); | |
841 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); | |
842 | SSYNC(); | |
843 | ||
f4d640c9 | 844 | #ifndef CONFIG_BF54x |
194de561 BW |
845 | /* Clear DLAB in LCR to Access THR RBR IER */ |
846 | val = UART_GET_LCR(uart); | |
847 | val &= ~DLAB; | |
848 | UART_PUT_LCR(uart, val); | |
849 | SSYNC(); | |
f4d640c9 | 850 | #endif |
194de561 BW |
851 | |
852 | UART_PUT_LCR(uart, lcr); | |
853 | ||
854 | /* Enable UART */ | |
f4d640c9 RH |
855 | #ifdef CONFIG_BF54x |
856 | UART_SET_IER(uart, ier); | |
857 | #else | |
194de561 | 858 | UART_PUT_IER(uart, ier); |
f4d640c9 | 859 | #endif |
194de561 BW |
860 | |
861 | val = UART_GET_GCTL(uart); | |
862 | val |= UCEN; | |
863 | UART_PUT_GCTL(uart, val); | |
864 | ||
865 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
866 | } | |
867 | ||
868 | static const char *bfin_serial_type(struct uart_port *port) | |
869 | { | |
870 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
871 | ||
872 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Release the memory region(s) being used by 'port'. | |
877 | */ | |
878 | static void bfin_serial_release_port(struct uart_port *port) | |
879 | { | |
880 | } | |
881 | ||
882 | /* | |
883 | * Request the memory region(s) being used by 'port'. | |
884 | */ | |
885 | static int bfin_serial_request_port(struct uart_port *port) | |
886 | { | |
887 | return 0; | |
888 | } | |
889 | ||
890 | /* | |
891 | * Configure/autoconfigure the port. | |
892 | */ | |
893 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
894 | { | |
895 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
896 | ||
897 | if (flags & UART_CONFIG_TYPE && | |
898 | bfin_serial_request_port(&uart->port) == 0) | |
899 | uart->port.type = PORT_BFIN; | |
900 | } | |
901 | ||
902 | /* | |
903 | * Verify the new serial_struct (for TIOCSSERIAL). | |
904 | * The only change we allow are to the flags and type, and | |
905 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
906 | */ | |
907 | static int | |
908 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
909 | { | |
910 | return 0; | |
911 | } | |
912 | ||
913 | static struct uart_ops bfin_serial_pops = { | |
914 | .tx_empty = bfin_serial_tx_empty, | |
915 | .set_mctrl = bfin_serial_set_mctrl, | |
916 | .get_mctrl = bfin_serial_get_mctrl, | |
917 | .stop_tx = bfin_serial_stop_tx, | |
918 | .start_tx = bfin_serial_start_tx, | |
919 | .stop_rx = bfin_serial_stop_rx, | |
920 | .enable_ms = bfin_serial_enable_ms, | |
921 | .break_ctl = bfin_serial_break_ctl, | |
922 | .startup = bfin_serial_startup, | |
923 | .shutdown = bfin_serial_shutdown, | |
924 | .set_termios = bfin_serial_set_termios, | |
925 | .type = bfin_serial_type, | |
926 | .release_port = bfin_serial_release_port, | |
927 | .request_port = bfin_serial_request_port, | |
928 | .config_port = bfin_serial_config_port, | |
929 | .verify_port = bfin_serial_verify_port, | |
930 | }; | |
931 | ||
932 | static void __init bfin_serial_init_ports(void) | |
933 | { | |
934 | static int first = 1; | |
935 | int i; | |
936 | ||
937 | if (!first) | |
938 | return; | |
939 | first = 0; | |
940 | ||
941 | for (i = 0; i < nr_ports; i++) { | |
942 | bfin_serial_ports[i].port.uartclk = get_sclk(); | |
943 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; | |
944 | bfin_serial_ports[i].port.line = i; | |
945 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
946 | bfin_serial_ports[i].port.membase = | |
947 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
948 | bfin_serial_ports[i].port.mapbase = | |
949 | bfin_serial_resource[i].uart_base_addr; | |
950 | bfin_serial_ports[i].port.irq = | |
951 | bfin_serial_resource[i].uart_irq; | |
952 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
953 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
954 | bfin_serial_ports[i].tx_done = 1; | |
955 | bfin_serial_ports[i].tx_count = 0; | |
956 | bfin_serial_ports[i].tx_dma_channel = | |
957 | bfin_serial_resource[i].uart_tx_dma_channel; | |
958 | bfin_serial_ports[i].rx_dma_channel = | |
959 | bfin_serial_resource[i].uart_rx_dma_channel; | |
960 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
961 | #else | |
962 | INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work); | |
963 | #endif | |
964 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
965 | bfin_serial_ports[i].cts_pin = | |
966 | bfin_serial_resource[i].uart_cts_pin; | |
967 | bfin_serial_ports[i].rts_pin = | |
968 | bfin_serial_resource[i].uart_rts_pin; | |
969 | #endif | |
970 | bfin_serial_hw_init(&bfin_serial_ports[i]); | |
194de561 | 971 | } |
f4d640c9 | 972 | |
194de561 BW |
973 | } |
974 | ||
975 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
194de561 BW |
976 | /* |
977 | * If the port was already initialised (eg, by a boot loader), | |
978 | * try to determine the current setup. | |
979 | */ | |
980 | static void __init | |
981 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
982 | int *parity, int *bits) | |
983 | { | |
984 | unsigned short status; | |
985 | ||
986 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
987 | if (status == (ERBFI | ETBEI)) { | |
988 | /* ok, the port was enabled */ | |
989 | unsigned short lcr, val; | |
990 | unsigned short dlh, dll; | |
991 | ||
992 | lcr = UART_GET_LCR(uart); | |
993 | ||
994 | *parity = 'n'; | |
995 | if (lcr & PEN) { | |
996 | if (lcr & EPS) | |
997 | *parity = 'e'; | |
998 | else | |
999 | *parity = 'o'; | |
1000 | } | |
1001 | switch (lcr & 0x03) { | |
1002 | case 0: *bits = 5; break; | |
1003 | case 1: *bits = 6; break; | |
1004 | case 2: *bits = 7; break; | |
1005 | case 3: *bits = 8; break; | |
1006 | } | |
f4d640c9 | 1007 | #ifndef CONFIG_BF54x |
194de561 BW |
1008 | /* Set DLAB in LCR to Access DLL and DLH */ |
1009 | val = UART_GET_LCR(uart); | |
1010 | val |= DLAB; | |
1011 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1012 | #endif |
194de561 BW |
1013 | |
1014 | dll = UART_GET_DLL(uart); | |
1015 | dlh = UART_GET_DLH(uart); | |
1016 | ||
f4d640c9 | 1017 | #ifndef CONFIG_BF54x |
194de561 BW |
1018 | /* Clear DLAB in LCR to Access THR RBR IER */ |
1019 | val = UART_GET_LCR(uart); | |
1020 | val &= ~DLAB; | |
1021 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1022 | #endif |
194de561 BW |
1023 | |
1024 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1025 | } | |
1026 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits); | |
1027 | } | |
0ae53640 RG |
1028 | #endif |
1029 | ||
1030 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
1031 | static struct uart_driver bfin_serial_reg; | |
194de561 BW |
1032 | |
1033 | static int __init | |
1034 | bfin_serial_console_setup(struct console *co, char *options) | |
1035 | { | |
1036 | struct bfin_serial_port *uart; | |
0ae53640 | 1037 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1038 | int baud = 57600; |
1039 | int bits = 8; | |
1040 | int parity = 'n'; | |
0ae53640 | 1041 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1042 | int flow = 'r'; |
0ae53640 | 1043 | # else |
194de561 | 1044 | int flow = 'n'; |
0ae53640 RG |
1045 | # endif |
1046 | # endif | |
194de561 BW |
1047 | |
1048 | /* | |
1049 | * Check whether an invalid uart number has been specified, and | |
1050 | * if so, search for the first available port that does have | |
1051 | * console support. | |
1052 | */ | |
1053 | if (co->index == -1 || co->index >= nr_ports) | |
1054 | co->index = 0; | |
1055 | uart = &bfin_serial_ports[co->index]; | |
1056 | ||
0ae53640 | 1057 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1058 | if (options) |
1059 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1060 | else | |
1061 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1062 | ||
1063 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1064 | # else |
1065 | return 0; | |
1066 | # endif | |
1067 | } | |
1068 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1069 | defined (CONFIG_EARLY_PRINTK) */ | |
1070 | ||
1071 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1072 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1073 | { | |
1074 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1075 | while (!(UART_GET_LSR(uart) & THRE)) | |
1076 | barrier(); | |
1077 | UART_PUT_CHAR(uart, ch); | |
1078 | SSYNC(); | |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * Interrupts are disabled on entering | |
1083 | */ | |
1084 | static void | |
1085 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1086 | { | |
1087 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
1088 | int flags = 0; | |
1089 | ||
1090 | spin_lock_irqsave(&uart->port.lock, flags); | |
1091 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1092 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1093 | ||
194de561 BW |
1094 | } |
1095 | ||
194de561 BW |
1096 | static struct console bfin_serial_console = { |
1097 | .name = BFIN_SERIAL_NAME, | |
1098 | .write = bfin_serial_console_write, | |
1099 | .device = uart_console_device, | |
1100 | .setup = bfin_serial_console_setup, | |
1101 | .flags = CON_PRINTBUFFER, | |
1102 | .index = -1, | |
1103 | .data = &bfin_serial_reg, | |
1104 | }; | |
1105 | ||
1106 | static int __init bfin_serial_rs_console_init(void) | |
1107 | { | |
1108 | bfin_serial_init_ports(); | |
1109 | register_console(&bfin_serial_console); | |
474f1a66 SZ |
1110 | #ifdef CONFIG_KGDB_UART |
1111 | kgdb_entry_state = 0; | |
1112 | init_kgdb_uart(); | |
1113 | #endif | |
194de561 BW |
1114 | return 0; |
1115 | } | |
1116 | console_initcall(bfin_serial_rs_console_init); | |
1117 | ||
1118 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1119 | #else | |
1120 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1121 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1122 | ||
1123 | ||
1124 | #ifdef CONFIG_EARLY_PRINTK | |
1125 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1126 | { | |
1127 | unsigned timeout = 0xffff; | |
1128 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1129 | ||
1130 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1131 | cpu_relax(); | |
1132 | UART_PUT_CHAR(uart, ch); | |
1133 | } | |
1134 | ||
1135 | static __init void early_serial_write(struct console *con, const char *s, | |
1136 | unsigned int n) | |
1137 | { | |
1138 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1139 | unsigned int i; | |
1140 | ||
1141 | for (i = 0; i < n; i++, s++) { | |
1142 | if (*s == '\n') | |
1143 | early_serial_putc(&uart->port, '\r'); | |
1144 | early_serial_putc(&uart->port, *s); | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | static struct __init console bfin_early_serial_console = { | |
1149 | .name = "early_BFuart", | |
1150 | .write = early_serial_write, | |
1151 | .device = uart_console_device, | |
1152 | .flags = CON_PRINTBUFFER, | |
1153 | .setup = bfin_serial_console_setup, | |
1154 | .index = -1, | |
1155 | .data = &bfin_serial_reg, | |
1156 | }; | |
1157 | ||
1158 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1159 | unsigned int cflag) | |
1160 | { | |
1161 | struct bfin_serial_port *uart; | |
1162 | struct ktermios t; | |
1163 | ||
1164 | if (port == -1 || port >= nr_ports) | |
1165 | port = 0; | |
1166 | bfin_serial_init_ports(); | |
1167 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1168 | uart = &bfin_serial_ports[port]; |
1169 | t.c_cflag = cflag; | |
1170 | t.c_iflag = 0; | |
1171 | t.c_oflag = 0; | |
1172 | t.c_lflag = ICANON; | |
1173 | t.c_line = port; | |
1174 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1175 | return &bfin_early_serial_console; | |
1176 | } | |
1177 | ||
1178 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ | |
194de561 BW |
1179 | |
1180 | static struct uart_driver bfin_serial_reg = { | |
1181 | .owner = THIS_MODULE, | |
1182 | .driver_name = "bfin-uart", | |
1183 | .dev_name = BFIN_SERIAL_NAME, | |
1184 | .major = BFIN_SERIAL_MAJOR, | |
1185 | .minor = BFIN_SERIAL_MINOR, | |
1186 | .nr = NR_PORTS, | |
1187 | .cons = BFIN_SERIAL_CONSOLE, | |
1188 | }; | |
1189 | ||
1190 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1191 | { | |
1192 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1193 | ||
1194 | if (uart) | |
1195 | uart_suspend_port(&bfin_serial_reg, &uart->port); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static int bfin_serial_resume(struct platform_device *dev) | |
1201 | { | |
1202 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1203 | ||
1204 | if (uart) | |
1205 | uart_resume_port(&bfin_serial_reg, &uart->port); | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static int bfin_serial_probe(struct platform_device *dev) | |
1211 | { | |
1212 | struct resource *res = dev->resource; | |
1213 | int i; | |
1214 | ||
1215 | for (i = 0; i < dev->num_resources; i++, res++) | |
1216 | if (res->flags & IORESOURCE_MEM) | |
1217 | break; | |
1218 | ||
1219 | if (i < dev->num_resources) { | |
1220 | for (i = 0; i < nr_ports; i++, res++) { | |
1221 | if (bfin_serial_ports[i].port.mapbase != res->start) | |
1222 | continue; | |
1223 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1224 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1225 | platform_set_drvdata(dev, &bfin_serial_ports[i]); | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static int bfin_serial_remove(struct platform_device *pdev) | |
1233 | { | |
1234 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); | |
1235 | ||
1236 | ||
1237 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
1238 | gpio_free(uart->cts_pin); | |
1239 | gpio_free(uart->rts_pin); | |
1240 | #endif | |
1241 | ||
1242 | platform_set_drvdata(pdev, NULL); | |
1243 | ||
1244 | if (uart) | |
1245 | uart_remove_one_port(&bfin_serial_reg, &uart->port); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static struct platform_driver bfin_serial_driver = { | |
1251 | .probe = bfin_serial_probe, | |
1252 | .remove = bfin_serial_remove, | |
1253 | .suspend = bfin_serial_suspend, | |
1254 | .resume = bfin_serial_resume, | |
1255 | .driver = { | |
1256 | .name = "bfin-uart", | |
1257 | }, | |
1258 | }; | |
1259 | ||
1260 | static int __init bfin_serial_init(void) | |
1261 | { | |
1262 | int ret; | |
474f1a66 SZ |
1263 | #ifdef CONFIG_KGDB_UART |
1264 | struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
a359cca7 | 1265 | struct ktermios t; |
474f1a66 | 1266 | #endif |
194de561 BW |
1267 | |
1268 | pr_info("Serial: Blackfin serial driver\n"); | |
1269 | ||
1270 | bfin_serial_init_ports(); | |
1271 | ||
1272 | ret = uart_register_driver(&bfin_serial_reg); | |
1273 | if (ret == 0) { | |
1274 | ret = platform_driver_register(&bfin_serial_driver); | |
1275 | if (ret) { | |
1276 | pr_debug("uart register failed\n"); | |
1277 | uart_unregister_driver(&bfin_serial_reg); | |
1278 | } | |
1279 | } | |
474f1a66 SZ |
1280 | #ifdef CONFIG_KGDB_UART |
1281 | if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) { | |
a359cca7 | 1282 | request_irq(uart->port.irq, bfin_serial_rx_int, |
474f1a66 SZ |
1283 | IRQF_DISABLED, "BFIN_UART_RX", uart); |
1284 | pr_info("Request irq for kgdb uart port\n"); | |
a359cca7 SZ |
1285 | #ifdef CONFIG_BF54x |
1286 | UART_SET_IER(uart, ERBFI); | |
1287 | #else | |
474f1a66 | 1288 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); |
a359cca7 | 1289 | #endif |
d5148ffa | 1290 | SSYNC(); |
474f1a66 SZ |
1291 | t.c_cflag = CS8|B57600; |
1292 | t.c_iflag = 0; | |
1293 | t.c_oflag = 0; | |
1294 | t.c_lflag = ICANON; | |
1295 | t.c_line = CONFIG_KGDB_UART_PORT; | |
1296 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1297 | } | |
1298 | #endif | |
194de561 BW |
1299 | return ret; |
1300 | } | |
1301 | ||
1302 | static void __exit bfin_serial_exit(void) | |
1303 | { | |
1304 | platform_driver_unregister(&bfin_serial_driver); | |
1305 | uart_unregister_driver(&bfin_serial_reg); | |
1306 | } | |
1307 | ||
1308 | module_init(bfin_serial_init); | |
1309 | module_exit(bfin_serial_exit); | |
1310 | ||
1311 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1312 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1313 | MODULE_LICENSE("GPL"); | |
1314 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); |