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Blackfin Serial Driver: fix error while transferring large files
[linux-block.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
d273e201 4 * Copyright 2006-2008 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
52e15f0e
SZ		 25#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
26 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
474f1a66
SZ		 27#include <linux/kgdb.h>
28#include <asm/irq_regs.h>
29#endif
30
194de561 31#include <asm/gpio.h>
639f6571 32#include <mach/bfin_serial_5xx.h>
194de561
BW		 33
34#ifdef CONFIG_SERIAL_BFIN_DMA
35#include <linux/dma-mapping.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/cacheflush.h>
39#endif
40
41/* UART name and device definitions */
42#define BFIN_SERIAL_NAME "ttyBF"
43#define BFIN_SERIAL_MAJOR 204
44#define BFIN_SERIAL_MINOR 64
45
c9607ecc
MF		 46static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
47static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
48
52e15f0e
SZ		 49#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
50 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
51
52# ifndef CONFIG_SERIAL_BFIN_PIO
53# error KGDB only support UART in PIO mode.
54# endif
55
56static int kgdboc_port_line;
57static int kgdboc_break_enabled;
58#endif
194de561
BW		 59/*
60 * Setup for console. Argument comes from the menuconfig
61 */
62#define DMA_RX_XCOUNT 512
63#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
64
0aef4564 65#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW		 66
67#ifdef CONFIG_SERIAL_BFIN_DMA
68static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
69#else
194de561 70static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 71#endif
72
80d5c474
GY		 73static void bfin_serial_reset_irda(struct uart_port *port);
74
d307d36a
SZ		 75#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
76 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
77static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
78{
79 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80 if (uart->cts_pin < 0)
81 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
82
83 /* CTS PIN is negative assertive. */
84 if (UART_GET_CTS(uart))
85 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
86 else
87 return TIOCM_DSR | TIOCM_CAR;
88}
89
90static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
91{
92 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
93 if (uart->rts_pin < 0)
94 return;
95
96 /* RTS PIN is negative assertive. */
97 if (mctrl & TIOCM_RTS)
98 UART_ENABLE_RTS(uart);
99 else
100 UART_DISABLE_RTS(uart);
101}
102
103/*
104 * Handle any change of modem status signal.
105 */
106static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
107{
108 struct bfin_serial_port *uart = dev_id;
109 unsigned int status;
110
111 status = bfin_serial_get_mctrl(&uart->port);
112 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
113#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
114 uart->scts = 1;
115 UART_CLEAR_SCTS(uart);
116 UART_CLEAR_IER(uart, EDSSI);
117#endif
118
119 return IRQ_HANDLED;
120}
121#else
122static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
123{
124 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
125}
126
127static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
128{
129}
130#endif
131
194de561
BW		 132/*
133 * interrupts are disabled on entry
134 */
135static void bfin_serial_stop_tx(struct uart_port *port)
136{
137 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
68a784cb 138#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857 139 struct circ_buf *xmit = &uart->port.info->xmit;
68a784cb 140#endif
194de561 141
f4d640c9 142 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 143 cpu_relax();
f4d640c9 144
194de561
BW		 145#ifdef CONFIG_SERIAL_BFIN_DMA
146 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 147 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
148 uart->port.icount.tx += uart->tx_count;
149 uart->tx_count = 0;
150 uart->tx_done = 1;
f4d640c9
RH		 151#else
152#ifdef CONFIG_BF54x
f4d640c9
RH		 153 /* Clear TFI bit */
154 UART_PUT_LSR(uart, TFI);
194de561 155#endif
89bf6dc5 156 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 157#endif
194de561
BW		 158}
159
160/*
161 * port is locked and interrupts are disabled
162 */
163static void bfin_serial_start_tx(struct uart_port *port)
164{
165 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80d5c474
GY		 166 struct tty_struct *tty = uart->port.info->port.tty;
167
d307d36a 168#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 169 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
d307d36a
SZ		 170 uart->scts = 0;
171 uart_handle_cts_change(&uart->port, uart->scts);
172 }
173#endif
174
80d5c474
GY		 175 /*
176 * To avoid losting RX interrupt, we reset IR function
177 * before sending data.
178 */
179 if (tty->termios->c_line == N_IRDA)
180 bfin_serial_reset_irda(port);
194de561
BW		 181
182#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 183 if (uart->tx_done)
184 bfin_serial_dma_tx_chars(uart);
f4d640c9 185#else
f4d640c9 186 UART_SET_IER(uart, ETBEI);
a359cca7 187 bfin_serial_tx_chars(uart);
f4d640c9 188#endif
194de561
BW		 189}
190
191/*
192 * Interrupts are enabled
193 */
194static void bfin_serial_stop_rx(struct uart_port *port)
195{
196 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
52e15f0e 197
f4d640c9 198 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 199}
200
201/*
202 * Set the modem control timer to fire immediately.
203 */
204static void bfin_serial_enable_ms(struct uart_port *port)
205{
206}
207
474f1a66 208
50e2e15a 209#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 210# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
211# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
212#else
213# define UART_GET_ANOMALY_THRESHOLD(uart) 0
214# define UART_SET_ANOMALY_THRESHOLD(uart, v)
215#endif
216
194de561 217#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 218static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
219{
52e15f0e 220 struct tty_struct *tty = NULL;
194de561 221 unsigned int status, ch, flg;
8851c71e 222 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 223
759eb040 224 status = UART_GET_LSR(uart);
0bcfd70e
MF		 225 UART_CLEAR_LSR(uart);
226
227 ch = UART_GET_CHAR(uart);
194de561
BW		 228 uart->port.icount.rx++;
229
52e15f0e
SZ		 230#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
231 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
232 if (kgdb_connected && kgdboc_port_line == uart->port.line)
233 if (ch == 0x3) {/* Ctrl + C */
234 kgdb_breakpoint();
474f1a66 235 return;
474f1a66 236 }
52e15f0e 237
df04baf1 238 if (!uart->port.info || !uart->port.info->port.tty)
52e15f0e 239 return;
474f1a66 240#endif
df04baf1 241 tty = uart->port.info->port.tty;
bbf275f0 242
50e2e15a 243 if (ANOMALY_05000363) {
8851c71e
MF		 244 /* The BF533 (and BF561) family of processors have a nice anomaly
245 * where they continuously generate characters for a "single" break.
bbf275f0 246 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 247 * character comes across. Due to the nature of the flood, it is
248 * not possible to reliably catch bytes that are sent too quickly
249 * after this break. So application code talking to the Blackfin
250 * which sends a break signal must allow at least 1.5 character
251 * times after the end of the break for things to stabilize. This
252 * timeout was picked as it must absolutely be larger than 1
253 * character time +/- some percent. So 1.5 sounds good. All other
254 * Blackfin families operate properly. Woo.
bbf275f0 255 */
8851c71e
MF		 256 if (anomaly_start.tv_sec) {
257 struct timeval curr;
258 suseconds_t usecs;
259
260 if ((~ch & (~ch + 1)) & 0xff)
261 goto known_good_char;
262
263 do_gettimeofday(&curr);
264 if (curr.tv_sec - anomaly_start.tv_sec > 1)
265 goto known_good_char;
266
267 usecs = 0;
268 if (curr.tv_sec != anomaly_start.tv_sec)
269 usecs += USEC_PER_SEC;
270 usecs += curr.tv_usec - anomaly_start.tv_usec;
271
272 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
273 goto known_good_char;
274
275 if (ch)
276 anomaly_start.tv_sec = 0;
277 else
278 anomaly_start = curr;
279
280 return;
281
282 known_good_char:
e482a237 283 status &= ~BI;
8851c71e 284 anomaly_start.tv_sec = 0;
bbf275f0 285 }
194de561 286 }
194de561
BW		 287
288 if (status & BI) {
50e2e15a 289 if (ANOMALY_05000363)
8851c71e
MF		 290 if (bfin_revid() < 5)
291 do_gettimeofday(&anomaly_start);
194de561
BW		 292 uart->port.icount.brk++;
293 if (uart_handle_break(&uart->port))
294 goto ignore_char;
9808901b 295 status &= ~(PE | FE);
2ac5ee47
MF		 296 }
297 if (status & PE)
194de561 298 uart->port.icount.parity++;
2ac5ee47 299 if (status & OE)
194de561 300 uart->port.icount.overrun++;
2ac5ee47 301 if (status & FE)
194de561 302 uart->port.icount.frame++;
2ac5ee47
MF		 303
304 status &= uart->port.read_status_mask;
305
306 if (status & BI)
307 flg = TTY_BREAK;
308 else if (status & PE)
309 flg = TTY_PARITY;
310 else if (status & FE)
311 flg = TTY_FRAME;
312 else
194de561
BW		 313 flg = TTY_NORMAL;
314
315 if (uart_handle_sysrq_char(&uart->port, ch))
316 goto ignore_char;
194de561 317
2ac5ee47
MF		 318 uart_insert_char(&uart->port, status, OE, ch, flg);
319
320 ignore_char:
321 tty_flip_buffer_push(tty);
194de561
BW		 322}
323
324static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
325{
326 struct circ_buf *xmit = &uart->port.info->xmit;
327
194de561 328 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
5ffdeea2
SZ		 329#ifdef CONFIG_BF54x
330 /* Clear TFI bit */
331 UART_PUT_LSR(uart, TFI);
332#endif
333 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 334 return;
335 }
336
f30ac0ce
SZ		 337 if (uart->port.x_char) {
338 UART_PUT_CHAR(uart, uart->port.x_char);
339 uart->port.icount.tx++;
340 uart->port.x_char = 0;
341 }
342
759eb040
SZ		 343 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
344 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
345 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
346 uart->port.icount.tx++;
347 SSYNC();
348 }
194de561
BW		 349
350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
351 uart_write_wakeup(&uart->port);
194de561
BW		 352}
353
5c4e472b
AL		 354static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
355{
356 struct bfin_serial_port *uart = dev_id;
357
f4d640c9 358 spin_lock(&uart->port.lock);
0bcfd70e 359 while (UART_GET_LSR(uart) & DR)
f4d640c9 360 bfin_serial_rx_chars(uart);
f4d640c9 361 spin_unlock(&uart->port.lock);
759eb040 362
5c4e472b
AL		 363 return IRQ_HANDLED;
364}
365
366static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 367{
368 struct bfin_serial_port *uart = dev_id;
194de561 369
d307d36a 370#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 371 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
d307d36a
SZ		 372 uart->scts = 0;
373 uart_handle_cts_change(&uart->port, uart->scts);
374 }
375#endif
f4d640c9 376 spin_lock(&uart->port.lock);
0bcfd70e 377 if (UART_GET_LSR(uart) & THRE)
f4d640c9 378 bfin_serial_tx_chars(uart);
f4d640c9 379 spin_unlock(&uart->port.lock);
759eb040 380
194de561
BW		 381 return IRQ_HANDLED;
382}
4cb4f22b 383#endif
194de561 384
194de561
BW		 385#ifdef CONFIG_SERIAL_BFIN_DMA
386static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
387{
388 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 389
194de561
BW		 390 uart->tx_done = 0;
391
1b73351c 392 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 393 uart->tx_count = 0;
1b73351c
SZ		 394 uart->tx_done = 1;
395 return;
396 }
397
194de561
BW		 398 if (uart->port.x_char) {
399 UART_PUT_CHAR(uart, uart->port.x_char);
400 uart->port.icount.tx++;
401 uart->port.x_char = 0;
194de561 402 }
1b73351c 403
194de561
BW		 404 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
405 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
406 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
407 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
408 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
409 set_dma_config(uart->tx_dma_channel,
410 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
411 INTR_ON_BUF,
412 DIMENSION_LINEAR,
2047e40d
MH		 413 DATA_SIZE_8,
414 DMA_SYNC_RESTART));
194de561
BW		 415 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
416 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
417 set_dma_x_modify(uart->tx_dma_channel, 1);
418 enable_dma(uart->tx_dma_channel);
99ee7b5f 419
f4d640c9 420 UART_SET_IER(uart, ETBEI);
194de561
BW		 421}
422
2ac5ee47 423static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 424{
a88487c7 425 struct tty_struct *tty = uart->port.info->port.tty;
194de561
BW		 426 int i, flg, status;
427
428 status = UART_GET_LSR(uart);
0bcfd70e
MF		 429 UART_CLEAR_LSR(uart);
430
56f5de8f
SZ		 431 uart->port.icount.rx +=
432 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
433 UART_XMIT_SIZE);
194de561
BW		 434
435 if (status & BI) {
436 uart->port.icount.brk++;
437 if (uart_handle_break(&uart->port))
438 goto dma_ignore_char;
9808901b 439 status &= ~(PE | FE);
2ac5ee47
MF		 440 }
441 if (status & PE)
194de561 442 uart->port.icount.parity++;
2ac5ee47 443 if (status & OE)
194de561 444 uart->port.icount.overrun++;
2ac5ee47 445 if (status & FE)
194de561 446 uart->port.icount.frame++;
2ac5ee47
MF		 447
448 status &= uart->port.read_status_mask;
449
450 if (status & BI)
451 flg = TTY_BREAK;
452 else if (status & PE)
453 flg = TTY_PARITY;
454 else if (status & FE)
455 flg = TTY_FRAME;
456 else
194de561
BW		 457 flg = TTY_NORMAL;
458
8c4210e3 459 for (i = uart->rx_dma_buf.tail; ; i++) {
56f5de8f
SZ		 460 if (i >= UART_XMIT_SIZE)
461 i = 0;
8c4210e3
SZ		 462 if (i == uart->rx_dma_buf.head)
463 break;
56f5de8f
SZ		 464 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
465 uart_insert_char(&uart->port, status, OE,
466 uart->rx_dma_buf.buf[i], flg);
194de561 467 }
2ac5ee47
MF		 468
469 dma_ignore_char:
194de561
BW		 470 tty_flip_buffer_push(tty);
471}
472
473void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
474{
59e4e3e6
MF		 475 int x_pos, pos;
476 unsigned long flags;
68a784cb
SZ		 477
478 spin_lock_irqsave(&uart->port.lock, flags);
194de561 479
8516c568
SZ		 480 /* 2D DMA RX buffer ring is used. Because curr_y_count and
481 * curr_x_count can't be read as an atomic operation,
482 * curr_y_count should be read before curr_x_count. When
483 * curr_x_count is read, curr_y_count may already indicate
484 * next buffer line. But, the position calculated here is
485 * still indicate the old line. The wrong position data may
486 * be smaller than current buffer tail, which cause garbages
487 * are received if it is not prohibit.
488 */
56f5de8f
SZ		 489 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
490 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
491 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
492 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
493 uart->rx_dma_nrows = 0;
494 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 495 if (x_pos == DMA_RX_XCOUNT)
496 x_pos = 0;
497
498 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
8516c568
SZ		 499 /* Ignore receiving data if new position is in the same line of
500 * current buffer tail and small.
501 */
502 if (pos > uart->rx_dma_buf.tail ||
503 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
56f5de8f 504 uart->rx_dma_buf.head = pos;
194de561 505 bfin_serial_dma_rx_chars(uart);
56f5de8f 506 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 507 }
0aef4564 508
68a784cb
SZ		 509 spin_unlock_irqrestore(&uart->port.lock, flags);
510
0a278423 511 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 512}
513
514static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
515{
516 struct bfin_serial_port *uart = dev_id;
517 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 518
d307d36a 519#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 520 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
d307d36a
SZ		 521 uart->scts = 0;
522 uart_handle_cts_change(&uart->port, uart->scts);
523 }
524#endif
525
194de561
BW		 526 spin_lock(&uart->port.lock);
527 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 528 disable_dma(uart->tx_dma_channel);
0711d857 529 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9 530 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ		 531 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
532 uart->port.icount.tx += uart->tx_count;
1b73351c 533
56f5de8f
SZ		 534 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
535 uart_write_wakeup(&uart->port);
536
1b73351c 537 bfin_serial_dma_tx_chars(uart);
194de561
BW		 538 }
539
540 spin_unlock(&uart->port.lock);
541 return IRQ_HANDLED;
542}
543
544static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
545{
546 struct bfin_serial_port *uart = dev_id;
547 unsigned short irqstat;
8516c568 548 int pos;
0711d857 549
194de561
BW		 550 spin_lock(&uart->port.lock);
551 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
552 clear_dma_irqstat(uart->rx_dma_channel);
8516c568
SZ		 553
554 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
555 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
556 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
557 uart->rx_dma_nrows = 0;
558
559 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
560 if (pos > uart->rx_dma_buf.tail ||
561 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
562 uart->rx_dma_buf.head = pos;
563 bfin_serial_dma_rx_chars(uart);
564 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
565 }
566
194de561 567 spin_unlock(&uart->port.lock);
0aef4564 568
194de561
BW		 569 return IRQ_HANDLED;
570}
571#endif
572
573/*
574 * Return TIOCSER_TEMT when transmitter is not busy.
575 */
576static unsigned int bfin_serial_tx_empty(struct uart_port *port)
577{
578 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
579 unsigned short lsr;
580
581 lsr = UART_GET_LSR(uart);
582 if (lsr & TEMT)
583 return TIOCSER_TEMT;
584 else
585 return 0;
586}
587
194de561
BW		 588static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
589{
cf686762
MF		 590 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
591 u16 lcr = UART_GET_LCR(uart);
592 if (break_state)
593 lcr |= SB;
594 else
595 lcr &= ~SB;
596 UART_PUT_LCR(uart, lcr);
597 SSYNC();
194de561
BW		 598}
599
600static int bfin_serial_startup(struct uart_port *port)
601{
602 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
603
604#ifdef CONFIG_SERIAL_BFIN_DMA
605 dma_addr_t dma_handle;
606
607 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
608 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
609 return -EBUSY;
610 }
611
612 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
613 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
614 free_dma(uart->rx_dma_channel);
615 return -EBUSY;
616 }
617
618 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
619 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
620
621 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
622 uart->rx_dma_buf.head = 0;
623 uart->rx_dma_buf.tail = 0;
624 uart->rx_dma_nrows = 0;
625
626 set_dma_config(uart->rx_dma_channel,
627 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
628 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 629 DATA_SIZE_8,
630 DMA_SYNC_RESTART));
194de561
BW		 631 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
632 set_dma_x_modify(uart->rx_dma_channel, 1);
633 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
634 set_dma_y_modify(uart->rx_dma_channel, 1);
635 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
636 enable_dma(uart->rx_dma_channel);
637
638 uart->rx_dma_timer.data = (unsigned long)(uart);
639 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
640 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
641 add_timer(&(uart->rx_dma_timer));
642#else
6f95570e 643# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 644 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
645 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
646 kgdboc_break_enabled = 0;
647 else {
648# endif
a359cca7
SZ		 649 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
650 "BFIN_UART_RX", uart)) {
194de561
BW		 651 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
652 return -EBUSY;
653 }
654
655 if (request_irq
5c4e472b 656 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 657 "BFIN_UART_TX", uart)) {
658 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
659 free_irq(uart->port.irq, uart);
660 return -EBUSY;
661 }
ab2375f2
SZ		 662
663# ifdef CONFIG_BF54x
664 {
665 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
666
667 switch (uart->port.irq) {
668 case IRQ_UART3_RX:
669 uart_dma_ch_rx = CH_UART3_RX;
670 uart_dma_ch_tx = CH_UART3_TX;
671 break;
672 case IRQ_UART2_RX:
673 uart_dma_ch_rx = CH_UART2_RX;
674 uart_dma_ch_tx = CH_UART2_TX;
675 break;
676 default:
677 uart_dma_ch_rx = uart_dma_ch_tx = 0;
678 break;
679 };
680
681 if (uart_dma_ch_rx &&
682 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
683 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
684 free_irq(uart->port.irq, uart);
685 free_irq(uart->port.irq + 1, uart);
686 return -EBUSY;
687 }
688 if (uart_dma_ch_tx &&
689 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
690 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
691 free_dma(uart_dma_ch_rx);
692 free_irq(uart->port.irq, uart);
693 free_irq(uart->port.irq + 1, uart);
694 return -EBUSY;
695 }
696 }
697# endif
6f95570e 698# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 699 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
700 }
701# endif
6f95570e
SZ		 702#endif
703
704#ifdef CONFIG_SERIAL_BFIN_CTSRTS
705 if (uart->cts_pin >= 0) {
706 if (request_irq(gpio_to_irq(uart->cts_pin),
707 bfin_serial_mctrl_cts_int,
708 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
709 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
710 uart->cts_pin = -1;
711 pr_info("Unable to attach BlackFin UART CTS interrupt.\
712 So, disable it.\n");
713 }
714 }
715 if (uart->rts_pin >= 0) {
716 gpio_request(uart->rts_pin, DRIVER_NAME);
717 gpio_direction_output(uart->rts_pin, 0);
718 }
194de561 719#endif
d307d36a
SZ		 720#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
721 if (request_irq(uart->status_irq,
722 bfin_serial_mctrl_cts_int,
723 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
724 pr_info("Unable to attach BlackFin UART Modem \
725 Status interrupt.\n");
726 }
727
728 if (uart->cts_pin >= 0) {
729 gpio_request(uart->cts_pin, DRIVER_NAME);
730 gpio_direction_output(uart->cts_pin, 1);
731 }
732 if (uart->rts_pin >= 0) {
733 gpio_request(uart->rts_pin, DRIVER_NAME);
734 gpio_direction_output(uart->rts_pin, 0);
735 }
736
737 /* CTS RTS PINs are negative assertive. */
738 UART_PUT_MCR(uart, ACTS);
739 UART_SET_IER(uart, EDSSI);
740#endif
741
f4d640c9 742 UART_SET_IER(uart, ERBFI);
194de561
BW		 743 return 0;
744}
745
746static void bfin_serial_shutdown(struct uart_port *port)
747{
748 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
749
750#ifdef CONFIG_SERIAL_BFIN_DMA
751 disable_dma(uart->tx_dma_channel);
752 free_dma(uart->tx_dma_channel);
753 disable_dma(uart->rx_dma_channel);
754 free_dma(uart->rx_dma_channel);
755 del_timer(&(uart->rx_dma_timer));
75b780bd 756 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 757#else
ab2375f2
SZ		 758#ifdef CONFIG_BF54x
759 switch (uart->port.irq) {
760 case IRQ_UART3_RX:
761 free_dma(CH_UART3_RX);
762 free_dma(CH_UART3_TX);
763 break;
764 case IRQ_UART2_RX:
765 free_dma(CH_UART2_RX);
766 free_dma(CH_UART2_TX);
767 break;
768 default:
769 break;
770 };
474f1a66 771#endif
194de561
BW		 772 free_irq(uart->port.irq, uart);
773 free_irq(uart->port.irq+1, uart);
774#endif
6f95570e 775
d307d36a 776#ifdef CONFIG_SERIAL_BFIN_CTSRTS
6f95570e
SZ		 777 if (uart->cts_pin >= 0)
778 free_irq(gpio_to_irq(uart->cts_pin), uart);
779 if (uart->rts_pin >= 0)
780 gpio_free(uart->rts_pin);
d307d36a
SZ		 781#endif
782#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
783 if (uart->cts_pin >= 0)
784 gpio_free(uart->cts_pin);
785 if (uart->rts_pin >= 0)
786 gpio_free(uart->rts_pin);
787 if (UART_GET_IER(uart) && EDSSI)
788 free_irq(uart->status_irq, uart);
789#endif
194de561
BW		 790}
791
792static void
793bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
794 struct ktermios *old)
795{
796 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
797 unsigned long flags;
798 unsigned int baud, quot;
0c44a86d 799 unsigned short val, ier, lcr = 0;
194de561
BW		 800
801 switch (termios->c_cflag & CSIZE) {
802 case CS8:
803 lcr = WLS(8);
804 break;
805 case CS7:
806 lcr = WLS(7);
807 break;
808 case CS6:
809 lcr = WLS(6);
810 break;
811 case CS5:
812 lcr = WLS(5);
813 break;
814 default:
815 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 816 __func__);
194de561
BW		 817 }
818
819 if (termios->c_cflag & CSTOPB)
820 lcr |= STB;
19aa6382 821 if (termios->c_cflag & PARENB)
194de561 822 lcr |= PEN;
19aa6382
MF		 823 if (!(termios->c_cflag & PARODD))
824 lcr |= EPS;
825 if (termios->c_cflag & CMSPAR)
826 lcr |= STP;
194de561 827
2ac5ee47
MF		 828 port->read_status_mask = OE;
829 if (termios->c_iflag & INPCK)
830 port->read_status_mask |= (FE | PE);
831 if (termios->c_iflag & (BRKINT | PARMRK))
832 port->read_status_mask |= BI;
194de561 833
2ac5ee47
MF		 834 /*
835 * Characters to ignore
836 */
837 port->ignore_status_mask = 0;
838 if (termios->c_iflag & IGNPAR)
839 port->ignore_status_mask |= FE | PE;
840 if (termios->c_iflag & IGNBRK) {
841 port->ignore_status_mask |= BI;
842 /*
843 * If we're ignoring parity and break indicators,
844 * ignore overruns too (for real raw support).
845 */
846 if (termios->c_iflag & IGNPAR)
847 port->ignore_status_mask |= OE;
848 }
194de561
BW		 849
850 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
f4487101 851 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
194de561
BW		 852 spin_lock_irqsave(&uart->port.lock, flags);
853
8851c71e
MF		 854 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
855
194de561
BW		 856 /* Disable UART */
857 ier = UART_GET_IER(uart);
1feaa51d 858 UART_DISABLE_INTS(uart);
194de561
BW		 859
860 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 861 UART_SET_DLAB(uart);
194de561
BW		 862
863 UART_PUT_DLL(uart, quot & 0xFF);
194de561
BW		 864 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
865 SSYNC();
866
867 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 868 UART_CLEAR_DLAB(uart);
194de561
BW		 869
870 UART_PUT_LCR(uart, lcr);
871
872 /* Enable UART */
1feaa51d 873 UART_ENABLE_INTS(uart, ier);
194de561
BW		 874
875 val = UART_GET_GCTL(uart);
876 val |= UCEN;
877 UART_PUT_GCTL(uart, val);
878
b3ef5aba
GY		 879 /* Port speed changed, update the per-port timeout. */
880 uart_update_timeout(port, termios->c_cflag, baud);
881
194de561
BW		 882 spin_unlock_irqrestore(&uart->port.lock, flags);
883}
884
885static const char *bfin_serial_type(struct uart_port *port)
886{
887 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
888
889 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
890}
891
892/*
893 * Release the memory region(s) being used by 'port'.
894 */
895static void bfin_serial_release_port(struct uart_port *port)
896{
897}
898
899/*
900 * Request the memory region(s) being used by 'port'.
901 */
902static int bfin_serial_request_port(struct uart_port *port)
903{
904 return 0;
905}
906
907/*
908 * Configure/autoconfigure the port.
909 */
910static void bfin_serial_config_port(struct uart_port *port, int flags)
911{
912 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
913
914 if (flags & UART_CONFIG_TYPE &&
915 bfin_serial_request_port(&uart->port) == 0)
916 uart->port.type = PORT_BFIN;
917}
918
919/*
920 * Verify the new serial_struct (for TIOCSSERIAL).
921 * The only change we allow are to the flags and type, and
922 * even then only between PORT_BFIN and PORT_UNKNOWN
923 */
924static int
925bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
926{
927 return 0;
928}
929
7d01b475
GY		 930/*
931 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
932 * In other cases, disable IrDA function.
933 */
3b8458a9 934static void bfin_serial_set_ldisc(struct uart_port *port)
7d01b475 935{
3b8458a9 936 int line = port->line;
7d01b475
GY		 937 unsigned short val;
938
a88487c7 939 if (line >= port->info->port.tty->driver->num)
7d01b475
GY		 940 return;
941
b1cbefe5 942 switch (port->info->port.tty->termios->c_line) {
7d01b475
GY		 943 case N_IRDA:
944 val = UART_GET_GCTL(&bfin_serial_ports[line]);
945 val |= (IREN | RPOLC);
946 UART_PUT_GCTL(&bfin_serial_ports[line], val);
947 break;
948 default:
949 val = UART_GET_GCTL(&bfin_serial_ports[line]);
950 val &= ~(IREN | RPOLC);
951 UART_PUT_GCTL(&bfin_serial_ports[line], val);
952 }
953}
954
6f95570e
SZ		 955static void bfin_serial_reset_irda(struct uart_port *port)
956{
957 int line = port->line;
958 unsigned short val;
959
960 val = UART_GET_GCTL(&bfin_serial_ports[line]);
961 val &= ~(IREN | RPOLC);
962 UART_PUT_GCTL(&bfin_serial_ports[line], val);
963 SSYNC();
964 val |= (IREN | RPOLC);
965 UART_PUT_GCTL(&bfin_serial_ports[line], val);
966 SSYNC();
967}
968
52e15f0e
SZ		 969#ifdef CONFIG_CONSOLE_POLL
970static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
971{
972 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
973
974 while (!(UART_GET_LSR(uart) & THRE))
975 cpu_relax();
976
977 UART_CLEAR_DLAB(uart);
978 UART_PUT_CHAR(uart, (unsigned char)chr);
979}
980
981static int bfin_serial_poll_get_char(struct uart_port *port)
982{
983 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
984 unsigned char chr;
985
986 while (!(UART_GET_LSR(uart) & DR))
987 cpu_relax();
988
989 UART_CLEAR_DLAB(uart);
990 chr = UART_GET_CHAR(uart);
991
992 return chr;
993}
994#endif
995
996#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
997 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
998static void bfin_kgdboc_port_shutdown(struct uart_port *port)
999{
1000 if (kgdboc_break_enabled) {
1001 kgdboc_break_enabled = 0;
1002 bfin_serial_shutdown(port);
1003 }
1004}
1005
1006static int bfin_kgdboc_port_startup(struct uart_port *port)
1007{
1008 kgdboc_port_line = port->line;
1009 kgdboc_break_enabled = !bfin_serial_startup(port);
1010 return 0;
1011}
1012#endif
1013
194de561
BW		 1014static struct uart_ops bfin_serial_pops = {
1015 .tx_empty = bfin_serial_tx_empty,
1016 .set_mctrl = bfin_serial_set_mctrl,
1017 .get_mctrl = bfin_serial_get_mctrl,
1018 .stop_tx = bfin_serial_stop_tx,
1019 .start_tx = bfin_serial_start_tx,
1020 .stop_rx = bfin_serial_stop_rx,
1021 .enable_ms = bfin_serial_enable_ms,
1022 .break_ctl = bfin_serial_break_ctl,
1023 .startup = bfin_serial_startup,
1024 .shutdown = bfin_serial_shutdown,
1025 .set_termios = bfin_serial_set_termios,
3b8458a9 1026 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 1027 .type = bfin_serial_type,
1028 .release_port = bfin_serial_release_port,
1029 .request_port = bfin_serial_request_port,
1030 .config_port = bfin_serial_config_port,
1031 .verify_port = bfin_serial_verify_port,
52e15f0e
SZ		 1032#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1033 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1034 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1035 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1036#endif
1037#ifdef CONFIG_CONSOLE_POLL
1038 .poll_put_char = bfin_serial_poll_put_char,
1039 .poll_get_char = bfin_serial_poll_get_char,
1040#endif
194de561
BW		 1041};
1042
6f95570e
SZ		 1043static void __init bfin_serial_hw_init(void)
1044{
1045#ifdef CONFIG_SERIAL_BFIN_UART0
1046 peripheral_request(P_UART0_TX, DRIVER_NAME);
1047 peripheral_request(P_UART0_RX, DRIVER_NAME);
1048#endif
1049
1050#ifdef CONFIG_SERIAL_BFIN_UART1
1051 peripheral_request(P_UART1_TX, DRIVER_NAME);
1052 peripheral_request(P_UART1_RX, DRIVER_NAME);
1053
1054# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1055 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1056 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1057# endif
1058#endif
1059
1060#ifdef CONFIG_SERIAL_BFIN_UART2
1061 peripheral_request(P_UART2_TX, DRIVER_NAME);
1062 peripheral_request(P_UART2_RX, DRIVER_NAME);
1063#endif
1064
1065#ifdef CONFIG_SERIAL_BFIN_UART3
1066 peripheral_request(P_UART3_TX, DRIVER_NAME);
1067 peripheral_request(P_UART3_RX, DRIVER_NAME);
1068
1069# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1070 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1071 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1072# endif
1073#endif
1074}
1075
194de561
BW		 1076static void __init bfin_serial_init_ports(void)
1077{
1078 static int first = 1;
1079 int i;
1080
1081 if (!first)
1082 return;
1083 first = 0;
1084
6f95570e
SZ		 1085 bfin_serial_hw_init();
1086
c9607ecc 1087 for (i = 0; i < nr_active_ports; i++) {
194de561 1088 bfin_serial_ports[i].port.uartclk = get_sclk();
b3ef5aba 1089 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
194de561
BW		 1090 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1091 bfin_serial_ports[i].port.line = i;
1092 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1093 bfin_serial_ports[i].port.membase =
1094 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1095 bfin_serial_ports[i].port.mapbase =
1096 bfin_serial_resource[i].uart_base_addr;
1097 bfin_serial_ports[i].port.irq =
1098 bfin_serial_resource[i].uart_irq;
d307d36a
SZ		 1099 bfin_serial_ports[i].status_irq =
1100 bfin_serial_resource[i].uart_status_irq;
194de561
BW		 1101 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1102#ifdef CONFIG_SERIAL_BFIN_DMA
1103 bfin_serial_ports[i].tx_done = 1;
1104 bfin_serial_ports[i].tx_count = 0;
1105 bfin_serial_ports[i].tx_dma_channel =
1106 bfin_serial_resource[i].uart_tx_dma_channel;
1107 bfin_serial_ports[i].rx_dma_channel =
1108 bfin_serial_resource[i].uart_rx_dma_channel;
1109 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561 1110#endif
d307d36a
SZ		 1111#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1112 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561
BW		 1113 bfin_serial_ports[i].cts_pin =
1114 bfin_serial_resource[i].uart_cts_pin;
1115 bfin_serial_ports[i].rts_pin =
1116 bfin_serial_resource[i].uart_rts_pin;
1117#endif
194de561
BW		 1118 }
1119}
1120
b6efa1ea 1121#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
194de561
BW		 1122/*
1123 * If the port was already initialised (eg, by a boot loader),
1124 * try to determine the current setup.
1125 */
1126static void __init
1127bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1128 int *parity, int *bits)
1129{
1130 unsigned short status;
1131
1132 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1133 if (status == (ERBFI | ETBEI)) {
1134 /* ok, the port was enabled */
45828b81 1135 u16 lcr, dlh, dll;
194de561
BW		 1136
1137 lcr = UART_GET_LCR(uart);
1138
1139 *parity = 'n';
1140 if (lcr & PEN) {
1141 if (lcr & EPS)
1142 *parity = 'e';
1143 else
1144 *parity = 'o';
1145 }
1146 switch (lcr & 0x03) {
1147 case 0: *bits = 5; break;
1148 case 1: *bits = 6; break;
1149 case 2: *bits = 7; break;
1150 case 3: *bits = 8; break;
1151 }
1152 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 1153 UART_SET_DLAB(uart);
194de561
BW		 1154
1155 dll = UART_GET_DLL(uart);
1156 dlh = UART_GET_DLH(uart);
1157
1158 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 1159 UART_CLEAR_DLAB(uart);
194de561
BW		 1160
1161 *baud = get_sclk() / (16*(dll | dlh << 8));
1162 }
71cc2c21 1163 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 1164}
0ae53640 1165
0ae53640 1166static struct uart_driver bfin_serial_reg;
194de561
BW		 1167
1168static int __init
1169bfin_serial_console_setup(struct console *co, char *options)
1170{
1171 struct bfin_serial_port *uart;
1172 int baud = 57600;
1173 int bits = 8;
1174 int parity = 'n';
d307d36a
SZ		 1175# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1176 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561 1177 int flow = 'r';
b6efa1ea 1178# else
194de561 1179 int flow = 'n';
0ae53640 1180# endif
194de561
BW		 1181
1182 /*
1183 * Check whether an invalid uart number has been specified, and
1184 * if so, search for the first available port that does have
1185 * console support.
1186 */
c9607ecc 1187 if (co->index == -1 || co->index >= nr_active_ports)
194de561
BW		 1188 co->index = 0;
1189 uart = &bfin_serial_ports[co->index];
1190
1191 if (options)
1192 uart_parse_options(options, &baud, &parity, &bits, &flow);
1193 else
1194 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1195
1196 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1197}
1198#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1199 defined (CONFIG_EARLY_PRINTK) */
1200
1201#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1202static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1203{
1204 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1205 while (!(UART_GET_LSR(uart) & THRE))
1206 barrier();
1207 UART_PUT_CHAR(uart, ch);
1208 SSYNC();
1209}
1210
1211/*
1212 * Interrupts are disabled on entering
1213 */
1214static void
1215bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1216{
1217 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
59e4e3e6 1218 unsigned long flags;
0ae53640
RG		 1219
1220 spin_lock_irqsave(&uart->port.lock, flags);
1221 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1222 spin_unlock_irqrestore(&uart->port.lock, flags);
1223
194de561
BW		 1224}
1225
194de561
BW		 1226static struct console bfin_serial_console = {
1227 .name = BFIN_SERIAL_NAME,
1228 .write = bfin_serial_console_write,
1229 .device = uart_console_device,
1230 .setup = bfin_serial_console_setup,
1231 .flags = CON_PRINTBUFFER,
1232 .index = -1,
1233 .data = &bfin_serial_reg,
1234};
1235
1236static int __init bfin_serial_rs_console_init(void)
1237{
1238 bfin_serial_init_ports();
1239 register_console(&bfin_serial_console);
52e15f0e 1240
194de561
BW		 1241 return 0;
1242}
1243console_initcall(bfin_serial_rs_console_init);
1244
1245#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1246#else
1247#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1248#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1249
1250
1251#ifdef CONFIG_EARLY_PRINTK
1252static __init void early_serial_putc(struct uart_port *port, int ch)
1253{
1254 unsigned timeout = 0xffff;
1255 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1256
1257 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1258 cpu_relax();
1259 UART_PUT_CHAR(uart, ch);
1260}
1261
1262static __init void early_serial_write(struct console *con, const char *s,
1263 unsigned int n)
1264{
1265 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1266 unsigned int i;
1267
1268 for (i = 0; i < n; i++, s++) {
1269 if (*s == '\n')
1270 early_serial_putc(&uart->port, '\r');
1271 early_serial_putc(&uart->port, *s);
1272 }
1273}
1274
c1113400 1275static struct __initdata console bfin_early_serial_console = {
0ae53640
RG		 1276 .name = "early_BFuart",
1277 .write = early_serial_write,
1278 .device = uart_console_device,
1279 .flags = CON_PRINTBUFFER,
1280 .setup = bfin_serial_console_setup,
1281 .index = -1,
1282 .data = &bfin_serial_reg,
1283};
1284
1285struct console __init *bfin_earlyserial_init(unsigned int port,
1286 unsigned int cflag)
1287{
1288 struct bfin_serial_port *uart;
1289 struct ktermios t;
1290
c9607ecc 1291 if (port == -1 || port >= nr_active_ports)
0ae53640
RG		 1292 port = 0;
1293 bfin_serial_init_ports();
1294 bfin_early_serial_console.index = port;
0ae53640
RG		 1295 uart = &bfin_serial_ports[port];
1296 t.c_cflag = cflag;
1297 t.c_iflag = 0;
1298 t.c_oflag = 0;
1299 t.c_lflag = ICANON;
1300 t.c_line = port;
1301 bfin_serial_set_termios(&uart->port, &t, &t);
1302 return &bfin_early_serial_console;
1303}
1304
b6efa1ea 1305#endif /* CONFIG_EARLY_PRINTK */
194de561
BW		 1306
1307static struct uart_driver bfin_serial_reg = {
1308 .owner = THIS_MODULE,
1309 .driver_name = "bfin-uart",
1310 .dev_name = BFIN_SERIAL_NAME,
1311 .major = BFIN_SERIAL_MAJOR,
1312 .minor = BFIN_SERIAL_MINOR,
2ade9729 1313 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1314 .cons = BFIN_SERIAL_CONSOLE,
1315};
1316
1317static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1318{
ccfbc3e1 1319 int i;
194de561 1320
c9607ecc 1321 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1322 if (bfin_serial_ports[i].port.dev != &dev->dev)
1323 continue;
1324 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1325 }
194de561
BW		 1326
1327 return 0;
1328}
1329
1330static int bfin_serial_resume(struct platform_device *dev)
1331{
ccfbc3e1 1332 int i;
194de561 1333
c9607ecc 1334 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1335 if (bfin_serial_ports[i].port.dev != &dev->dev)
1336 continue;
1337 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1338 }
194de561
BW		 1339
1340 return 0;
1341}
1342
1343static int bfin_serial_probe(struct platform_device *dev)
1344{
1345 struct resource *res = dev->resource;
1346 int i;
1347
1348 for (i = 0; i < dev->num_resources; i++, res++)
1349 if (res->flags & IORESOURCE_MEM)
1350 break;
1351
1352 if (i < dev->num_resources) {
c9607ecc 1353 for (i = 0; i < nr_active_ports; i++, res++) {
194de561
BW		 1354 if (bfin_serial_ports[i].port.mapbase != res->start)
1355 continue;
1356 bfin_serial_ports[i].port.dev = &dev->dev;
1357 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
194de561
BW		 1358 }
1359 }
1360
1361 return 0;
1362}
1363
ccfbc3e1 1364static int bfin_serial_remove(struct platform_device *dev)
194de561 1365{
ccfbc3e1 1366 int i;
194de561 1367
c9607ecc 1368 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1369 if (bfin_serial_ports[i].port.dev != &dev->dev)
1370 continue;
1371 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1372 bfin_serial_ports[i].port.dev = NULL;
d307d36a
SZ		 1373#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1374 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
ccfbc3e1
SZ		 1375 gpio_free(bfin_serial_ports[i].cts_pin);
1376 gpio_free(bfin_serial_ports[i].rts_pin);
194de561 1377#endif
ccfbc3e1 1378 }
194de561
BW		 1379
1380 return 0;
1381}
1382
1383static struct platform_driver bfin_serial_driver = {
1384 .probe = bfin_serial_probe,
1385 .remove = bfin_serial_remove,
1386 .suspend = bfin_serial_suspend,
1387 .resume = bfin_serial_resume,
1388 .driver = {
1389 .name = "bfin-uart",
e169c139 1390 .owner = THIS_MODULE,
194de561
BW		 1391 },
1392};
1393
1394static int __init bfin_serial_init(void)
1395{
1396 int ret;
1397
1398 pr_info("Serial: Blackfin serial driver\n");
1399
1400 bfin_serial_init_ports();
1401
1402 ret = uart_register_driver(&bfin_serial_reg);
1403 if (ret == 0) {
1404 ret = platform_driver_register(&bfin_serial_driver);
1405 if (ret) {
1406 pr_debug("uart register failed\n");
1407 uart_unregister_driver(&bfin_serial_reg);
1408 }
1409 }
1410 return ret;
1411}
1412
1413static void __exit bfin_serial_exit(void)
1414{
1415 platform_driver_unregister(&bfin_serial_driver);
1416 uart_unregister_driver(&bfin_serial_reg);
1417}
1418
52e15f0e 1419
194de561
BW		 1420module_init(bfin_serial_init);
1421module_exit(bfin_serial_exit);
1422
1423MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1424MODULE_DESCRIPTION("Blackfin generic serial port driver");
1425MODULE_LICENSE("GPL");
1426MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1427MODULE_ALIAS("platform:bfin-uart");
Linux 6.x block layer and io_uring tree(s)