Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
41 | /* UART name and device definitions */ | |
42 | #define BFIN_SERIAL_NAME "ttyBF" | |
43 | #define BFIN_SERIAL_MAJOR 204 | |
44 | #define BFIN_SERIAL_MINOR 64 | |
45 | ||
c9607ecc MF |
46 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
47 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
48 | ||
52e15f0e SZ |
49 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
50 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
51 | ||
52 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
53 | # error KGDB only support UART in PIO mode. | |
54 | # endif | |
55 | ||
56 | static int kgdboc_port_line; | |
57 | static int kgdboc_break_enabled; | |
58 | #endif | |
194de561 BW |
59 | /* |
60 | * Setup for console. Argument comes from the menuconfig | |
61 | */ | |
62 | #define DMA_RX_XCOUNT 512 | |
63 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
64 | ||
0aef4564 | 65 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
66 | |
67 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
68 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
69 | #else | |
194de561 | 70 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
71 | #endif |
72 | ||
80d5c474 GY |
73 | static void bfin_serial_reset_irda(struct uart_port *port); |
74 | ||
194de561 BW |
75 | /* |
76 | * interrupts are disabled on entry | |
77 | */ | |
78 | static void bfin_serial_stop_tx(struct uart_port *port) | |
79 | { | |
80 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 81 | #ifdef CONFIG_SERIAL_BFIN_DMA |
0711d857 | 82 | struct circ_buf *xmit = &uart->port.info->xmit; |
68a784cb | 83 | #endif |
194de561 | 84 | |
f4d640c9 | 85 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 86 | cpu_relax(); |
f4d640c9 | 87 | |
194de561 BW |
88 | #ifdef CONFIG_SERIAL_BFIN_DMA |
89 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
90 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
91 | uart->port.icount.tx += uart->tx_count; | |
92 | uart->tx_count = 0; | |
93 | uart->tx_done = 1; | |
f4d640c9 RH |
94 | #else |
95 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
96 | /* Clear TFI bit */ |
97 | UART_PUT_LSR(uart, TFI); | |
194de561 | 98 | #endif |
89bf6dc5 | 99 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 100 | #endif |
194de561 BW |
101 | } |
102 | ||
103 | /* | |
104 | * port is locked and interrupts are disabled | |
105 | */ | |
106 | static void bfin_serial_start_tx(struct uart_port *port) | |
107 | { | |
108 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80d5c474 GY |
109 | struct tty_struct *tty = uart->port.info->port.tty; |
110 | ||
111 | /* | |
112 | * To avoid losting RX interrupt, we reset IR function | |
113 | * before sending data. | |
114 | */ | |
115 | if (tty->termios->c_line == N_IRDA) | |
116 | bfin_serial_reset_irda(port); | |
194de561 BW |
117 | |
118 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
119 | if (uart->tx_done) |
120 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 121 | #else |
f4d640c9 | 122 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 123 | bfin_serial_tx_chars(uart); |
f4d640c9 | 124 | #endif |
194de561 BW |
125 | } |
126 | ||
127 | /* | |
128 | * Interrupts are enabled | |
129 | */ | |
130 | static void bfin_serial_stop_rx(struct uart_port *port) | |
131 | { | |
132 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 133 | |
f4d640c9 | 134 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
135 | } |
136 | ||
137 | /* | |
138 | * Set the modem control timer to fire immediately. | |
139 | */ | |
140 | static void bfin_serial_enable_ms(struct uart_port *port) | |
141 | { | |
142 | } | |
143 | ||
474f1a66 | 144 | |
50e2e15a | 145 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
146 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
147 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
148 | #else | |
149 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
150 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
151 | #endif | |
152 | ||
194de561 | 153 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
154 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
155 | { | |
52e15f0e | 156 | struct tty_struct *tty = NULL; |
194de561 | 157 | unsigned int status, ch, flg; |
8851c71e | 158 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 159 | |
759eb040 | 160 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
161 | UART_CLEAR_LSR(uart); |
162 | ||
163 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
164 | uart->port.icount.rx++; |
165 | ||
52e15f0e SZ |
166 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
167 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
168 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
169 | if (ch == 0x3) {/* Ctrl + C */ | |
170 | kgdb_breakpoint(); | |
474f1a66 | 171 | return; |
474f1a66 | 172 | } |
52e15f0e | 173 | |
df04baf1 | 174 | if (!uart->port.info || !uart->port.info->port.tty) |
52e15f0e | 175 | return; |
474f1a66 | 176 | #endif |
df04baf1 | 177 | tty = uart->port.info->port.tty; |
bbf275f0 | 178 | |
50e2e15a | 179 | if (ANOMALY_05000363) { |
8851c71e MF |
180 | /* The BF533 (and BF561) family of processors have a nice anomaly |
181 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 182 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
183 | * character comes across. Due to the nature of the flood, it is |
184 | * not possible to reliably catch bytes that are sent too quickly | |
185 | * after this break. So application code talking to the Blackfin | |
186 | * which sends a break signal must allow at least 1.5 character | |
187 | * times after the end of the break for things to stabilize. This | |
188 | * timeout was picked as it must absolutely be larger than 1 | |
189 | * character time +/- some percent. So 1.5 sounds good. All other | |
190 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 191 | */ |
8851c71e MF |
192 | if (anomaly_start.tv_sec) { |
193 | struct timeval curr; | |
194 | suseconds_t usecs; | |
195 | ||
196 | if ((~ch & (~ch + 1)) & 0xff) | |
197 | goto known_good_char; | |
198 | ||
199 | do_gettimeofday(&curr); | |
200 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
201 | goto known_good_char; | |
202 | ||
203 | usecs = 0; | |
204 | if (curr.tv_sec != anomaly_start.tv_sec) | |
205 | usecs += USEC_PER_SEC; | |
206 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
207 | ||
208 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
209 | goto known_good_char; | |
210 | ||
211 | if (ch) | |
212 | anomaly_start.tv_sec = 0; | |
213 | else | |
214 | anomaly_start = curr; | |
215 | ||
216 | return; | |
217 | ||
218 | known_good_char: | |
e482a237 | 219 | status &= ~BI; |
8851c71e | 220 | anomaly_start.tv_sec = 0; |
bbf275f0 | 221 | } |
194de561 | 222 | } |
194de561 BW |
223 | |
224 | if (status & BI) { | |
50e2e15a | 225 | if (ANOMALY_05000363) |
8851c71e MF |
226 | if (bfin_revid() < 5) |
227 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
228 | uart->port.icount.brk++; |
229 | if (uart_handle_break(&uart->port)) | |
230 | goto ignore_char; | |
9808901b | 231 | status &= ~(PE | FE); |
2ac5ee47 MF |
232 | } |
233 | if (status & PE) | |
194de561 | 234 | uart->port.icount.parity++; |
2ac5ee47 | 235 | if (status & OE) |
194de561 | 236 | uart->port.icount.overrun++; |
2ac5ee47 | 237 | if (status & FE) |
194de561 | 238 | uart->port.icount.frame++; |
2ac5ee47 MF |
239 | |
240 | status &= uart->port.read_status_mask; | |
241 | ||
242 | if (status & BI) | |
243 | flg = TTY_BREAK; | |
244 | else if (status & PE) | |
245 | flg = TTY_PARITY; | |
246 | else if (status & FE) | |
247 | flg = TTY_FRAME; | |
248 | else | |
194de561 BW |
249 | flg = TTY_NORMAL; |
250 | ||
251 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
252 | goto ignore_char; | |
194de561 | 253 | |
2ac5ee47 MF |
254 | uart_insert_char(&uart->port, status, OE, ch, flg); |
255 | ||
256 | ignore_char: | |
257 | tty_flip_buffer_push(tty); | |
194de561 BW |
258 | } |
259 | ||
260 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
261 | { | |
262 | struct circ_buf *xmit = &uart->port.info->xmit; | |
263 | ||
194de561 | 264 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
5ffdeea2 SZ |
265 | #ifdef CONFIG_BF54x |
266 | /* Clear TFI bit */ | |
267 | UART_PUT_LSR(uart, TFI); | |
268 | #endif | |
269 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 BW |
270 | return; |
271 | } | |
272 | ||
f30ac0ce SZ |
273 | if (uart->port.x_char) { |
274 | UART_PUT_CHAR(uart, uart->port.x_char); | |
275 | uart->port.icount.tx++; | |
276 | uart->port.x_char = 0; | |
277 | } | |
278 | ||
759eb040 SZ |
279 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
280 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
281 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
282 | uart->port.icount.tx++; | |
283 | SSYNC(); | |
284 | } | |
194de561 BW |
285 | |
286 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
287 | uart_write_wakeup(&uart->port); | |
194de561 BW |
288 | } |
289 | ||
5c4e472b AL |
290 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
291 | { | |
292 | struct bfin_serial_port *uart = dev_id; | |
293 | ||
f4d640c9 | 294 | spin_lock(&uart->port.lock); |
0bcfd70e | 295 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 296 | bfin_serial_rx_chars(uart); |
f4d640c9 | 297 | spin_unlock(&uart->port.lock); |
759eb040 | 298 | |
5c4e472b AL |
299 | return IRQ_HANDLED; |
300 | } | |
301 | ||
302 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
303 | { |
304 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 305 | |
f4d640c9 | 306 | spin_lock(&uart->port.lock); |
0bcfd70e | 307 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 308 | bfin_serial_tx_chars(uart); |
f4d640c9 | 309 | spin_unlock(&uart->port.lock); |
759eb040 | 310 | |
194de561 BW |
311 | return IRQ_HANDLED; |
312 | } | |
4cb4f22b | 313 | #endif |
194de561 | 314 | |
194de561 BW |
315 | #ifdef CONFIG_SERIAL_BFIN_DMA |
316 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
317 | { | |
318 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 319 | |
194de561 BW |
320 | uart->tx_done = 0; |
321 | ||
1b73351c | 322 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 323 | uart->tx_count = 0; |
1b73351c SZ |
324 | uart->tx_done = 1; |
325 | return; | |
326 | } | |
327 | ||
194de561 BW |
328 | if (uart->port.x_char) { |
329 | UART_PUT_CHAR(uart, uart->port.x_char); | |
330 | uart->port.icount.tx++; | |
331 | uart->port.x_char = 0; | |
194de561 | 332 | } |
1b73351c | 333 | |
194de561 BW |
334 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
335 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
336 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
337 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
338 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
339 | set_dma_config(uart->tx_dma_channel, | |
340 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
341 | INTR_ON_BUF, | |
342 | DIMENSION_LINEAR, | |
2047e40d MH |
343 | DATA_SIZE_8, |
344 | DMA_SYNC_RESTART)); | |
194de561 BW |
345 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
346 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
347 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
348 | enable_dma(uart->tx_dma_channel); | |
99ee7b5f | 349 | |
f4d640c9 | 350 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
351 | } |
352 | ||
2ac5ee47 | 353 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 354 | { |
a88487c7 | 355 | struct tty_struct *tty = uart->port.info->port.tty; |
194de561 BW |
356 | int i, flg, status; |
357 | ||
358 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
359 | UART_CLEAR_LSR(uart); |
360 | ||
56f5de8f SZ |
361 | uart->port.icount.rx += |
362 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
363 | UART_XMIT_SIZE); | |
194de561 BW |
364 | |
365 | if (status & BI) { | |
366 | uart->port.icount.brk++; | |
367 | if (uart_handle_break(&uart->port)) | |
368 | goto dma_ignore_char; | |
9808901b | 369 | status &= ~(PE | FE); |
2ac5ee47 MF |
370 | } |
371 | if (status & PE) | |
194de561 | 372 | uart->port.icount.parity++; |
2ac5ee47 | 373 | if (status & OE) |
194de561 | 374 | uart->port.icount.overrun++; |
2ac5ee47 | 375 | if (status & FE) |
194de561 | 376 | uart->port.icount.frame++; |
2ac5ee47 MF |
377 | |
378 | status &= uart->port.read_status_mask; | |
379 | ||
380 | if (status & BI) | |
381 | flg = TTY_BREAK; | |
382 | else if (status & PE) | |
383 | flg = TTY_PARITY; | |
384 | else if (status & FE) | |
385 | flg = TTY_FRAME; | |
386 | else | |
194de561 BW |
387 | flg = TTY_NORMAL; |
388 | ||
8c4210e3 | 389 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
390 | if (i >= UART_XMIT_SIZE) |
391 | i = 0; | |
8c4210e3 SZ |
392 | if (i == uart->rx_dma_buf.head) |
393 | break; | |
56f5de8f SZ |
394 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
395 | uart_insert_char(&uart->port, status, OE, | |
396 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 397 | } |
2ac5ee47 MF |
398 | |
399 | dma_ignore_char: | |
194de561 BW |
400 | tty_flip_buffer_push(tty); |
401 | } | |
402 | ||
403 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
404 | { | |
59e4e3e6 MF |
405 | int x_pos, pos; |
406 | unsigned long flags; | |
68a784cb SZ |
407 | |
408 | spin_lock_irqsave(&uart->port.lock, flags); | |
194de561 | 409 | |
56f5de8f SZ |
410 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
411 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
412 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
413 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
414 | uart->rx_dma_nrows = 0; | |
415 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
416 | if (x_pos == DMA_RX_XCOUNT) |
417 | x_pos = 0; | |
418 | ||
419 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
56f5de8f SZ |
420 | if (pos != uart->rx_dma_buf.tail) { |
421 | uart->rx_dma_buf.head = pos; | |
194de561 | 422 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 423 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 424 | } |
0aef4564 | 425 | |
68a784cb SZ |
426 | spin_unlock_irqrestore(&uart->port.lock, flags); |
427 | ||
0a278423 | 428 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
429 | } |
430 | ||
431 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
432 | { | |
433 | struct bfin_serial_port *uart = dev_id; | |
434 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 BW |
435 | |
436 | spin_lock(&uart->port.lock); | |
437 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 438 | disable_dma(uart->tx_dma_channel); |
0711d857 | 439 | clear_dma_irqstat(uart->tx_dma_channel); |
f4d640c9 | 440 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
441 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
442 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 443 | |
56f5de8f SZ |
444 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
445 | uart_write_wakeup(&uart->port); | |
446 | ||
1b73351c | 447 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
448 | } |
449 | ||
450 | spin_unlock(&uart->port.lock); | |
451 | return IRQ_HANDLED; | |
452 | } | |
453 | ||
454 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
455 | { | |
456 | struct bfin_serial_port *uart = dev_id; | |
457 | unsigned short irqstat; | |
0711d857 | 458 | |
194de561 BW |
459 | spin_lock(&uart->port.lock); |
460 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
461 | clear_dma_irqstat(uart->rx_dma_channel); | |
68a784cb | 462 | bfin_serial_dma_rx_chars(uart); |
194de561 | 463 | spin_unlock(&uart->port.lock); |
0aef4564 | 464 | |
194de561 BW |
465 | return IRQ_HANDLED; |
466 | } | |
467 | #endif | |
468 | ||
469 | /* | |
470 | * Return TIOCSER_TEMT when transmitter is not busy. | |
471 | */ | |
472 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
473 | { | |
474 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
475 | unsigned short lsr; | |
476 | ||
477 | lsr = UART_GET_LSR(uart); | |
478 | if (lsr & TEMT) | |
479 | return TIOCSER_TEMT; | |
480 | else | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
485 | { | |
486 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
487 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
488 | if (uart->cts_pin < 0) | |
489 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
490 | ||
1feaa51d | 491 | if (UART_GET_CTS(uart)) |
194de561 BW |
492 | return TIOCM_DSR | TIOCM_CAR; |
493 | else | |
494 | #endif | |
495 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
496 | } | |
497 | ||
498 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
499 | { | |
500 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
501 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
502 | if (uart->rts_pin < 0) | |
503 | return; | |
504 | ||
505 | if (mctrl & TIOCM_RTS) | |
1feaa51d | 506 | UART_CLEAR_RTS(uart); |
194de561 | 507 | else |
1feaa51d | 508 | UART_SET_RTS(uart); |
194de561 BW |
509 | #endif |
510 | } | |
511 | ||
6f95570e | 512 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 513 | /* |
6f95570e | 514 | * Handle any change of modem status signal. |
194de561 | 515 | */ |
6f95570e | 516 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) |
194de561 | 517 | { |
6f95570e | 518 | struct bfin_serial_port *uart = dev_id; |
194de561 | 519 | unsigned int status; |
194de561 BW |
520 | |
521 | status = bfin_serial_get_mctrl(&uart->port); | |
4cb4f22b | 522 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
6f95570e SZ |
523 | |
524 | return IRQ_HANDLED; | |
194de561 | 525 | } |
6f95570e | 526 | #endif |
194de561 BW |
527 | |
528 | /* | |
529 | * Interrupts are always disabled. | |
530 | */ | |
531 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
532 | { | |
cf686762 MF |
533 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
534 | u16 lcr = UART_GET_LCR(uart); | |
535 | if (break_state) | |
536 | lcr |= SB; | |
537 | else | |
538 | lcr &= ~SB; | |
539 | UART_PUT_LCR(uart, lcr); | |
540 | SSYNC(); | |
194de561 BW |
541 | } |
542 | ||
543 | static int bfin_serial_startup(struct uart_port *port) | |
544 | { | |
545 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
546 | ||
547 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
548 | dma_addr_t dma_handle; | |
549 | ||
550 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
551 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
552 | return -EBUSY; | |
553 | } | |
554 | ||
555 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
556 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
557 | free_dma(uart->rx_dma_channel); | |
558 | return -EBUSY; | |
559 | } | |
560 | ||
561 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
562 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
563 | ||
564 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
565 | uart->rx_dma_buf.head = 0; | |
566 | uart->rx_dma_buf.tail = 0; | |
567 | uart->rx_dma_nrows = 0; | |
568 | ||
569 | set_dma_config(uart->rx_dma_channel, | |
570 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
571 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
572 | DATA_SIZE_8, |
573 | DMA_SYNC_RESTART)); | |
194de561 BW |
574 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
575 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
576 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
577 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
578 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
579 | enable_dma(uart->rx_dma_channel); | |
580 | ||
581 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
582 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
583 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
584 | add_timer(&(uart->rx_dma_timer)); | |
585 | #else | |
6f95570e | 586 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
587 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
588 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
589 | kgdboc_break_enabled = 0; | |
590 | else { | |
591 | # endif | |
a359cca7 SZ |
592 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
593 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
594 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
595 | return -EBUSY; | |
596 | } | |
597 | ||
598 | if (request_irq | |
5c4e472b | 599 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
600 | "BFIN_UART_TX", uart)) { |
601 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
602 | free_irq(uart->port.irq, uart); | |
603 | return -EBUSY; | |
604 | } | |
ab2375f2 SZ |
605 | |
606 | # ifdef CONFIG_BF54x | |
607 | { | |
608 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
609 | ||
610 | switch (uart->port.irq) { | |
611 | case IRQ_UART3_RX: | |
612 | uart_dma_ch_rx = CH_UART3_RX; | |
613 | uart_dma_ch_tx = CH_UART3_TX; | |
614 | break; | |
615 | case IRQ_UART2_RX: | |
616 | uart_dma_ch_rx = CH_UART2_RX; | |
617 | uart_dma_ch_tx = CH_UART2_TX; | |
618 | break; | |
619 | default: | |
620 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
621 | break; | |
622 | }; | |
623 | ||
624 | if (uart_dma_ch_rx && | |
625 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
626 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
627 | free_irq(uart->port.irq, uart); | |
628 | free_irq(uart->port.irq + 1, uart); | |
629 | return -EBUSY; | |
630 | } | |
631 | if (uart_dma_ch_tx && | |
632 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
633 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
634 | free_dma(uart_dma_ch_rx); | |
635 | free_irq(uart->port.irq, uart); | |
636 | free_irq(uart->port.irq + 1, uart); | |
637 | return -EBUSY; | |
638 | } | |
639 | } | |
640 | # endif | |
6f95570e | 641 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
642 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
643 | } | |
644 | # endif | |
6f95570e SZ |
645 | #endif |
646 | ||
647 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
648 | if (uart->cts_pin >= 0) { | |
649 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
650 | bfin_serial_mctrl_cts_int, | |
651 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
652 | IRQF_DISABLED, "BFIN_UART_CTS", uart)) { | |
653 | uart->cts_pin = -1; | |
654 | pr_info("Unable to attach BlackFin UART CTS interrupt.\ | |
655 | So, disable it.\n"); | |
656 | } | |
657 | } | |
658 | if (uart->rts_pin >= 0) { | |
659 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
660 | gpio_direction_output(uart->rts_pin, 0); | |
661 | } | |
194de561 | 662 | #endif |
f4d640c9 | 663 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
664 | return 0; |
665 | } | |
666 | ||
667 | static void bfin_serial_shutdown(struct uart_port *port) | |
668 | { | |
669 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
670 | ||
671 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
672 | disable_dma(uart->tx_dma_channel); | |
673 | free_dma(uart->tx_dma_channel); | |
674 | disable_dma(uart->rx_dma_channel); | |
675 | free_dma(uart->rx_dma_channel); | |
676 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 677 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 678 | #else |
ab2375f2 SZ |
679 | #ifdef CONFIG_BF54x |
680 | switch (uart->port.irq) { | |
681 | case IRQ_UART3_RX: | |
682 | free_dma(CH_UART3_RX); | |
683 | free_dma(CH_UART3_TX); | |
684 | break; | |
685 | case IRQ_UART2_RX: | |
686 | free_dma(CH_UART2_RX); | |
687 | free_dma(CH_UART2_TX); | |
688 | break; | |
689 | default: | |
690 | break; | |
691 | }; | |
474f1a66 | 692 | #endif |
194de561 BW |
693 | free_irq(uart->port.irq, uart); |
694 | free_irq(uart->port.irq+1, uart); | |
695 | #endif | |
6f95570e SZ |
696 | |
697 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
698 | if (uart->cts_pin >= 0) | |
699 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
700 | if (uart->rts_pin >= 0) | |
701 | gpio_free(uart->rts_pin); | |
702 | # endif | |
194de561 BW |
703 | } |
704 | ||
705 | static void | |
706 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
707 | struct ktermios *old) | |
708 | { | |
709 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
710 | unsigned long flags; | |
711 | unsigned int baud, quot; | |
0c44a86d | 712 | unsigned short val, ier, lcr = 0; |
194de561 BW |
713 | |
714 | switch (termios->c_cflag & CSIZE) { | |
715 | case CS8: | |
716 | lcr = WLS(8); | |
717 | break; | |
718 | case CS7: | |
719 | lcr = WLS(7); | |
720 | break; | |
721 | case CS6: | |
722 | lcr = WLS(6); | |
723 | break; | |
724 | case CS5: | |
725 | lcr = WLS(5); | |
726 | break; | |
727 | default: | |
728 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 729 | __func__); |
194de561 BW |
730 | } |
731 | ||
732 | if (termios->c_cflag & CSTOPB) | |
733 | lcr |= STB; | |
19aa6382 | 734 | if (termios->c_cflag & PARENB) |
194de561 | 735 | lcr |= PEN; |
19aa6382 MF |
736 | if (!(termios->c_cflag & PARODD)) |
737 | lcr |= EPS; | |
738 | if (termios->c_cflag & CMSPAR) | |
739 | lcr |= STP; | |
194de561 | 740 | |
2ac5ee47 MF |
741 | port->read_status_mask = OE; |
742 | if (termios->c_iflag & INPCK) | |
743 | port->read_status_mask |= (FE | PE); | |
744 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
745 | port->read_status_mask |= BI; | |
194de561 | 746 | |
2ac5ee47 MF |
747 | /* |
748 | * Characters to ignore | |
749 | */ | |
750 | port->ignore_status_mask = 0; | |
751 | if (termios->c_iflag & IGNPAR) | |
752 | port->ignore_status_mask |= FE | PE; | |
753 | if (termios->c_iflag & IGNBRK) { | |
754 | port->ignore_status_mask |= BI; | |
755 | /* | |
756 | * If we're ignoring parity and break indicators, | |
757 | * ignore overruns too (for real raw support). | |
758 | */ | |
759 | if (termios->c_iflag & IGNPAR) | |
760 | port->ignore_status_mask |= OE; | |
761 | } | |
194de561 BW |
762 | |
763 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
f4487101 | 764 | quot = uart_get_divisor(port, baud) - ANOMALY_05000230; |
194de561 BW |
765 | spin_lock_irqsave(&uart->port.lock, flags); |
766 | ||
8851c71e MF |
767 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
768 | ||
194de561 BW |
769 | /* Disable UART */ |
770 | ier = UART_GET_IER(uart); | |
1feaa51d | 771 | UART_DISABLE_INTS(uart); |
194de561 BW |
772 | |
773 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 774 | UART_SET_DLAB(uart); |
194de561 BW |
775 | |
776 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
777 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
778 | SSYNC(); | |
779 | ||
780 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 781 | UART_CLEAR_DLAB(uart); |
194de561 BW |
782 | |
783 | UART_PUT_LCR(uart, lcr); | |
784 | ||
785 | /* Enable UART */ | |
1feaa51d | 786 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
787 | |
788 | val = UART_GET_GCTL(uart); | |
789 | val |= UCEN; | |
790 | UART_PUT_GCTL(uart, val); | |
791 | ||
b3ef5aba GY |
792 | /* Port speed changed, update the per-port timeout. */ |
793 | uart_update_timeout(port, termios->c_cflag, baud); | |
794 | ||
194de561 BW |
795 | spin_unlock_irqrestore(&uart->port.lock, flags); |
796 | } | |
797 | ||
798 | static const char *bfin_serial_type(struct uart_port *port) | |
799 | { | |
800 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
801 | ||
802 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
803 | } | |
804 | ||
805 | /* | |
806 | * Release the memory region(s) being used by 'port'. | |
807 | */ | |
808 | static void bfin_serial_release_port(struct uart_port *port) | |
809 | { | |
810 | } | |
811 | ||
812 | /* | |
813 | * Request the memory region(s) being used by 'port'. | |
814 | */ | |
815 | static int bfin_serial_request_port(struct uart_port *port) | |
816 | { | |
817 | return 0; | |
818 | } | |
819 | ||
820 | /* | |
821 | * Configure/autoconfigure the port. | |
822 | */ | |
823 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
824 | { | |
825 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
826 | ||
827 | if (flags & UART_CONFIG_TYPE && | |
828 | bfin_serial_request_port(&uart->port) == 0) | |
829 | uart->port.type = PORT_BFIN; | |
830 | } | |
831 | ||
832 | /* | |
833 | * Verify the new serial_struct (for TIOCSSERIAL). | |
834 | * The only change we allow are to the flags and type, and | |
835 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
836 | */ | |
837 | static int | |
838 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
839 | { | |
840 | return 0; | |
841 | } | |
842 | ||
7d01b475 GY |
843 | /* |
844 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
845 | * In other cases, disable IrDA function. | |
846 | */ | |
3b8458a9 | 847 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 848 | { |
3b8458a9 | 849 | int line = port->line; |
7d01b475 GY |
850 | unsigned short val; |
851 | ||
a88487c7 | 852 | if (line >= port->info->port.tty->driver->num) |
7d01b475 GY |
853 | return; |
854 | ||
b1cbefe5 | 855 | switch (port->info->port.tty->termios->c_line) { |
7d01b475 GY |
856 | case N_IRDA: |
857 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
858 | val |= (IREN | RPOLC); | |
859 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
860 | break; | |
861 | default: | |
862 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
863 | val &= ~(IREN | RPOLC); | |
864 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
865 | } | |
866 | } | |
867 | ||
6f95570e SZ |
868 | static void bfin_serial_reset_irda(struct uart_port *port) |
869 | { | |
870 | int line = port->line; | |
871 | unsigned short val; | |
872 | ||
873 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
874 | val &= ~(IREN | RPOLC); | |
875 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
876 | SSYNC(); | |
877 | val |= (IREN | RPOLC); | |
878 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
879 | SSYNC(); | |
880 | } | |
881 | ||
52e15f0e SZ |
882 | #ifdef CONFIG_CONSOLE_POLL |
883 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) | |
884 | { | |
885 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
886 | ||
887 | while (!(UART_GET_LSR(uart) & THRE)) | |
888 | cpu_relax(); | |
889 | ||
890 | UART_CLEAR_DLAB(uart); | |
891 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
892 | } | |
893 | ||
894 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
895 | { | |
896 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
897 | unsigned char chr; | |
898 | ||
899 | while (!(UART_GET_LSR(uart) & DR)) | |
900 | cpu_relax(); | |
901 | ||
902 | UART_CLEAR_DLAB(uart); | |
903 | chr = UART_GET_CHAR(uart); | |
904 | ||
905 | return chr; | |
906 | } | |
907 | #endif | |
908 | ||
909 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
910 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
911 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
912 | { | |
913 | if (kgdboc_break_enabled) { | |
914 | kgdboc_break_enabled = 0; | |
915 | bfin_serial_shutdown(port); | |
916 | } | |
917 | } | |
918 | ||
919 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
920 | { | |
921 | kgdboc_port_line = port->line; | |
922 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
923 | return 0; | |
924 | } | |
925 | #endif | |
926 | ||
194de561 BW |
927 | static struct uart_ops bfin_serial_pops = { |
928 | .tx_empty = bfin_serial_tx_empty, | |
929 | .set_mctrl = bfin_serial_set_mctrl, | |
930 | .get_mctrl = bfin_serial_get_mctrl, | |
931 | .stop_tx = bfin_serial_stop_tx, | |
932 | .start_tx = bfin_serial_start_tx, | |
933 | .stop_rx = bfin_serial_stop_rx, | |
934 | .enable_ms = bfin_serial_enable_ms, | |
935 | .break_ctl = bfin_serial_break_ctl, | |
936 | .startup = bfin_serial_startup, | |
937 | .shutdown = bfin_serial_shutdown, | |
938 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 939 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
940 | .type = bfin_serial_type, |
941 | .release_port = bfin_serial_release_port, | |
942 | .request_port = bfin_serial_request_port, | |
943 | .config_port = bfin_serial_config_port, | |
944 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
945 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
946 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
947 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
948 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
949 | #endif | |
950 | #ifdef CONFIG_CONSOLE_POLL | |
951 | .poll_put_char = bfin_serial_poll_put_char, | |
952 | .poll_get_char = bfin_serial_poll_get_char, | |
953 | #endif | |
194de561 BW |
954 | }; |
955 | ||
6f95570e SZ |
956 | static void __init bfin_serial_hw_init(void) |
957 | { | |
958 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
959 | peripheral_request(P_UART0_TX, DRIVER_NAME); | |
960 | peripheral_request(P_UART0_RX, DRIVER_NAME); | |
961 | #endif | |
962 | ||
963 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
964 | peripheral_request(P_UART1_TX, DRIVER_NAME); | |
965 | peripheral_request(P_UART1_RX, DRIVER_NAME); | |
966 | ||
967 | # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x) | |
968 | peripheral_request(P_UART1_RTS, DRIVER_NAME); | |
969 | peripheral_request(P_UART1_CTS, DRIVER_NAME); | |
970 | # endif | |
971 | #endif | |
972 | ||
973 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
974 | peripheral_request(P_UART2_TX, DRIVER_NAME); | |
975 | peripheral_request(P_UART2_RX, DRIVER_NAME); | |
976 | #endif | |
977 | ||
978 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
979 | peripheral_request(P_UART3_TX, DRIVER_NAME); | |
980 | peripheral_request(P_UART3_RX, DRIVER_NAME); | |
981 | ||
982 | # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x) | |
983 | peripheral_request(P_UART3_RTS, DRIVER_NAME); | |
984 | peripheral_request(P_UART3_CTS, DRIVER_NAME); | |
985 | # endif | |
986 | #endif | |
987 | } | |
988 | ||
194de561 BW |
989 | static void __init bfin_serial_init_ports(void) |
990 | { | |
991 | static int first = 1; | |
992 | int i; | |
993 | ||
994 | if (!first) | |
995 | return; | |
996 | first = 0; | |
997 | ||
6f95570e SZ |
998 | bfin_serial_hw_init(); |
999 | ||
c9607ecc | 1000 | for (i = 0; i < nr_active_ports; i++) { |
194de561 | 1001 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 1002 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
1003 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
1004 | bfin_serial_ports[i].port.line = i; | |
1005 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
1006 | bfin_serial_ports[i].port.membase = | |
1007 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
1008 | bfin_serial_ports[i].port.mapbase = | |
1009 | bfin_serial_resource[i].uart_base_addr; | |
1010 | bfin_serial_ports[i].port.irq = | |
1011 | bfin_serial_resource[i].uart_irq; | |
1012 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
1013 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
1014 | bfin_serial_ports[i].tx_done = 1; | |
1015 | bfin_serial_ports[i].tx_count = 0; | |
1016 | bfin_serial_ports[i].tx_dma_channel = | |
1017 | bfin_serial_resource[i].uart_tx_dma_channel; | |
1018 | bfin_serial_ports[i].rx_dma_channel = | |
1019 | bfin_serial_resource[i].uart_rx_dma_channel; | |
1020 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 BW |
1021 | #endif |
1022 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
1023 | bfin_serial_ports[i].cts_pin = | |
1024 | bfin_serial_resource[i].uart_cts_pin; | |
1025 | bfin_serial_ports[i].rts_pin = | |
1026 | bfin_serial_resource[i].uart_rts_pin; | |
1027 | #endif | |
194de561 BW |
1028 | } |
1029 | } | |
1030 | ||
b6efa1ea | 1031 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1032 | /* |
1033 | * If the port was already initialised (eg, by a boot loader), | |
1034 | * try to determine the current setup. | |
1035 | */ | |
1036 | static void __init | |
1037 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1038 | int *parity, int *bits) | |
1039 | { | |
1040 | unsigned short status; | |
1041 | ||
1042 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1043 | if (status == (ERBFI | ETBEI)) { | |
1044 | /* ok, the port was enabled */ | |
45828b81 | 1045 | u16 lcr, dlh, dll; |
194de561 BW |
1046 | |
1047 | lcr = UART_GET_LCR(uart); | |
1048 | ||
1049 | *parity = 'n'; | |
1050 | if (lcr & PEN) { | |
1051 | if (lcr & EPS) | |
1052 | *parity = 'e'; | |
1053 | else | |
1054 | *parity = 'o'; | |
1055 | } | |
1056 | switch (lcr & 0x03) { | |
1057 | case 0: *bits = 5; break; | |
1058 | case 1: *bits = 6; break; | |
1059 | case 2: *bits = 7; break; | |
1060 | case 3: *bits = 8; break; | |
1061 | } | |
1062 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1063 | UART_SET_DLAB(uart); |
194de561 BW |
1064 | |
1065 | dll = UART_GET_DLL(uart); | |
1066 | dlh = UART_GET_DLH(uart); | |
1067 | ||
1068 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1069 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1070 | |
1071 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1072 | } | |
71cc2c21 | 1073 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1074 | } |
0ae53640 | 1075 | |
0ae53640 | 1076 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1077 | |
1078 | static int __init | |
1079 | bfin_serial_console_setup(struct console *co, char *options) | |
1080 | { | |
1081 | struct bfin_serial_port *uart; | |
1082 | int baud = 57600; | |
1083 | int bits = 8; | |
1084 | int parity = 'n'; | |
b6efa1ea | 1085 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1086 | int flow = 'r'; |
b6efa1ea | 1087 | # else |
194de561 | 1088 | int flow = 'n'; |
0ae53640 | 1089 | # endif |
194de561 BW |
1090 | |
1091 | /* | |
1092 | * Check whether an invalid uart number has been specified, and | |
1093 | * if so, search for the first available port that does have | |
1094 | * console support. | |
1095 | */ | |
c9607ecc | 1096 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1097 | co->index = 0; |
1098 | uart = &bfin_serial_ports[co->index]; | |
1099 | ||
1100 | if (options) | |
1101 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1102 | else | |
1103 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1104 | ||
1105 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1106 | } |
1107 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1108 | defined (CONFIG_EARLY_PRINTK) */ | |
1109 | ||
1110 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1111 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1112 | { | |
1113 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1114 | while (!(UART_GET_LSR(uart) & THRE)) | |
1115 | barrier(); | |
1116 | UART_PUT_CHAR(uart, ch); | |
1117 | SSYNC(); | |
1118 | } | |
1119 | ||
1120 | /* | |
1121 | * Interrupts are disabled on entering | |
1122 | */ | |
1123 | static void | |
1124 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1125 | { | |
1126 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
59e4e3e6 | 1127 | unsigned long flags; |
0ae53640 RG |
1128 | |
1129 | spin_lock_irqsave(&uart->port.lock, flags); | |
1130 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1131 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1132 | ||
194de561 BW |
1133 | } |
1134 | ||
194de561 BW |
1135 | static struct console bfin_serial_console = { |
1136 | .name = BFIN_SERIAL_NAME, | |
1137 | .write = bfin_serial_console_write, | |
1138 | .device = uart_console_device, | |
1139 | .setup = bfin_serial_console_setup, | |
1140 | .flags = CON_PRINTBUFFER, | |
1141 | .index = -1, | |
1142 | .data = &bfin_serial_reg, | |
1143 | }; | |
1144 | ||
1145 | static int __init bfin_serial_rs_console_init(void) | |
1146 | { | |
1147 | bfin_serial_init_ports(); | |
1148 | register_console(&bfin_serial_console); | |
52e15f0e | 1149 | |
194de561 BW |
1150 | return 0; |
1151 | } | |
1152 | console_initcall(bfin_serial_rs_console_init); | |
1153 | ||
1154 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1155 | #else | |
1156 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1157 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1158 | ||
1159 | ||
1160 | #ifdef CONFIG_EARLY_PRINTK | |
1161 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1162 | { | |
1163 | unsigned timeout = 0xffff; | |
1164 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1165 | ||
1166 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1167 | cpu_relax(); | |
1168 | UART_PUT_CHAR(uart, ch); | |
1169 | } | |
1170 | ||
1171 | static __init void early_serial_write(struct console *con, const char *s, | |
1172 | unsigned int n) | |
1173 | { | |
1174 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1175 | unsigned int i; | |
1176 | ||
1177 | for (i = 0; i < n; i++, s++) { | |
1178 | if (*s == '\n') | |
1179 | early_serial_putc(&uart->port, '\r'); | |
1180 | early_serial_putc(&uart->port, *s); | |
1181 | } | |
1182 | } | |
1183 | ||
c1113400 | 1184 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1185 | .name = "early_BFuart", |
1186 | .write = early_serial_write, | |
1187 | .device = uart_console_device, | |
1188 | .flags = CON_PRINTBUFFER, | |
1189 | .setup = bfin_serial_console_setup, | |
1190 | .index = -1, | |
1191 | .data = &bfin_serial_reg, | |
1192 | }; | |
1193 | ||
1194 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1195 | unsigned int cflag) | |
1196 | { | |
1197 | struct bfin_serial_port *uart; | |
1198 | struct ktermios t; | |
1199 | ||
c9607ecc | 1200 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1201 | port = 0; |
1202 | bfin_serial_init_ports(); | |
1203 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1204 | uart = &bfin_serial_ports[port]; |
1205 | t.c_cflag = cflag; | |
1206 | t.c_iflag = 0; | |
1207 | t.c_oflag = 0; | |
1208 | t.c_lflag = ICANON; | |
1209 | t.c_line = port; | |
1210 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1211 | return &bfin_early_serial_console; | |
1212 | } | |
1213 | ||
b6efa1ea | 1214 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1215 | |
1216 | static struct uart_driver bfin_serial_reg = { | |
1217 | .owner = THIS_MODULE, | |
1218 | .driver_name = "bfin-uart", | |
1219 | .dev_name = BFIN_SERIAL_NAME, | |
1220 | .major = BFIN_SERIAL_MAJOR, | |
1221 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1222 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1223 | .cons = BFIN_SERIAL_CONSOLE, |
1224 | }; | |
1225 | ||
1226 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1227 | { | |
ccfbc3e1 | 1228 | int i; |
194de561 | 1229 | |
c9607ecc | 1230 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1231 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1232 | continue; | |
1233 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1234 | } | |
194de561 BW |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static int bfin_serial_resume(struct platform_device *dev) | |
1240 | { | |
ccfbc3e1 | 1241 | int i; |
194de561 | 1242 | |
c9607ecc | 1243 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1244 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1245 | continue; | |
1246 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1247 | } | |
194de561 BW |
1248 | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int bfin_serial_probe(struct platform_device *dev) | |
1253 | { | |
1254 | struct resource *res = dev->resource; | |
1255 | int i; | |
1256 | ||
1257 | for (i = 0; i < dev->num_resources; i++, res++) | |
1258 | if (res->flags & IORESOURCE_MEM) | |
1259 | break; | |
1260 | ||
1261 | if (i < dev->num_resources) { | |
c9607ecc | 1262 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1263 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1264 | continue; | |
1265 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1266 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1267 | } |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
ccfbc3e1 | 1273 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1274 | { |
ccfbc3e1 | 1275 | int i; |
194de561 | 1276 | |
c9607ecc | 1277 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1278 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1279 | continue; | |
1280 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1281 | bfin_serial_ports[i].port.dev = NULL; | |
194de561 | 1282 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
ccfbc3e1 SZ |
1283 | gpio_free(bfin_serial_ports[i].cts_pin); |
1284 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1285 | #endif |
ccfbc3e1 | 1286 | } |
194de561 BW |
1287 | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static struct platform_driver bfin_serial_driver = { | |
1292 | .probe = bfin_serial_probe, | |
1293 | .remove = bfin_serial_remove, | |
1294 | .suspend = bfin_serial_suspend, | |
1295 | .resume = bfin_serial_resume, | |
1296 | .driver = { | |
1297 | .name = "bfin-uart", | |
e169c139 | 1298 | .owner = THIS_MODULE, |
194de561 BW |
1299 | }, |
1300 | }; | |
1301 | ||
1302 | static int __init bfin_serial_init(void) | |
1303 | { | |
1304 | int ret; | |
1305 | ||
1306 | pr_info("Serial: Blackfin serial driver\n"); | |
1307 | ||
1308 | bfin_serial_init_ports(); | |
1309 | ||
1310 | ret = uart_register_driver(&bfin_serial_reg); | |
1311 | if (ret == 0) { | |
1312 | ret = platform_driver_register(&bfin_serial_driver); | |
1313 | if (ret) { | |
1314 | pr_debug("uart register failed\n"); | |
1315 | uart_unregister_driver(&bfin_serial_reg); | |
1316 | } | |
1317 | } | |
1318 | return ret; | |
1319 | } | |
1320 | ||
1321 | static void __exit bfin_serial_exit(void) | |
1322 | { | |
1323 | platform_driver_unregister(&bfin_serial_driver); | |
1324 | uart_unregister_driver(&bfin_serial_reg); | |
1325 | } | |
1326 | ||
52e15f0e | 1327 | |
194de561 BW |
1328 | module_init(bfin_serial_init); |
1329 | module_exit(bfin_serial_exit); | |
1330 | ||
1331 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1332 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1333 | MODULE_LICENSE("GPL"); | |
1334 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1335 | MODULE_ALIAS("platform:bfin-uart"); |