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Blackfin Serial Driver: updates kgdb over Blackfin serial driver with kgdb framework
[linux-block.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
d273e201 4 * Copyright 2006-2008 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
52e15f0e
SZ		 25#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
26 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
474f1a66
SZ		 27#include <linux/kgdb.h>
28#include <asm/irq_regs.h>
29#endif
30
194de561 31#include <asm/gpio.h>
639f6571 32#include <mach/bfin_serial_5xx.h>
194de561
BW		 33
34#ifdef CONFIG_SERIAL_BFIN_DMA
35#include <linux/dma-mapping.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/cacheflush.h>
39#endif
40
41/* UART name and device definitions */
42#define BFIN_SERIAL_NAME "ttyBF"
43#define BFIN_SERIAL_MAJOR 204
44#define BFIN_SERIAL_MINOR 64
45
c9607ecc
MF		 46static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
47static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
48
52e15f0e
SZ		 49#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
50 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
51
52# ifndef CONFIG_SERIAL_BFIN_PIO
53# error KGDB only support UART in PIO mode.
54# endif
55
56static int kgdboc_port_line;
57static int kgdboc_break_enabled;
58#endif
194de561
BW		 59/*
60 * Setup for console. Argument comes from the menuconfig
61 */
62#define DMA_RX_XCOUNT 512
63#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
64
0aef4564 65#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
f30ac0ce 66#define CTS_CHECK_JIFFIES (HZ / 50)
194de561
BW		 67
68#ifdef CONFIG_SERIAL_BFIN_DMA
69static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
70#else
194de561 71static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 72#endif
73
74static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
75
76/*
77 * interrupts are disabled on entry
78 */
79static void bfin_serial_stop_tx(struct uart_port *port)
80{
81 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
0711d857 82 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 83
f4d640c9 84 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 85 cpu_relax();
f4d640c9 86
194de561
BW		 87#ifdef CONFIG_SERIAL_BFIN_DMA
88 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 89 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
90 uart->port.icount.tx += uart->tx_count;
91 uart->tx_count = 0;
92 uart->tx_done = 1;
f4d640c9
RH		 93#else
94#ifdef CONFIG_BF54x
f4d640c9
RH		 95 /* Clear TFI bit */
96 UART_PUT_LSR(uart, TFI);
194de561 97#endif
89bf6dc5 98 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 99#endif
194de561
BW		 100}
101
102/*
103 * port is locked and interrupts are disabled
104 */
105static void bfin_serial_start_tx(struct uart_port *port)
106{
107 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
108
109#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 110 if (uart->tx_done)
111 bfin_serial_dma_tx_chars(uart);
f4d640c9 112#else
f4d640c9 113 UART_SET_IER(uart, ETBEI);
a359cca7 114 bfin_serial_tx_chars(uart);
f4d640c9 115#endif
194de561
BW		 116}
117
118/*
119 * Interrupts are enabled
120 */
121static void bfin_serial_stop_rx(struct uart_port *port)
122{
123 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
52e15f0e 124
f4d640c9 125 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 126}
127
128/*
129 * Set the modem control timer to fire immediately.
130 */
131static void bfin_serial_enable_ms(struct uart_port *port)
132{
133}
134
474f1a66 135
50e2e15a 136#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 137# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
138# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
139#else
140# define UART_GET_ANOMALY_THRESHOLD(uart) 0
141# define UART_SET_ANOMALY_THRESHOLD(uart, v)
142#endif
143
194de561 144#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 145static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
146{
52e15f0e 147 struct tty_struct *tty = NULL;
194de561 148 unsigned int status, ch, flg;
8851c71e 149 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 150
759eb040 151 status = UART_GET_LSR(uart);
0bcfd70e
MF		 152 UART_CLEAR_LSR(uart);
153
154 ch = UART_GET_CHAR(uart);
194de561
BW		 155 uart->port.icount.rx++;
156
52e15f0e
SZ		 157#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
158 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
159 if (kgdb_connected && kgdboc_port_line == uart->port.line)
160 if (ch == 0x3) {/* Ctrl + C */
161 kgdb_breakpoint();
474f1a66 162 return;
474f1a66 163 }
52e15f0e
SZ		 164
165 if (!uart->port.info || !uart->port.info->tty)
166 return;
474f1a66 167#endif
52e15f0e 168 tty = uart->port.info->tty;
bbf275f0 169
50e2e15a 170 if (ANOMALY_05000363) {
8851c71e
MF		 171 /* The BF533 (and BF561) family of processors have a nice anomaly
172 * where they continuously generate characters for a "single" break.
bbf275f0 173 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 174 * character comes across. Due to the nature of the flood, it is
175 * not possible to reliably catch bytes that are sent too quickly
176 * after this break. So application code talking to the Blackfin
177 * which sends a break signal must allow at least 1.5 character
178 * times after the end of the break for things to stabilize. This
179 * timeout was picked as it must absolutely be larger than 1
180 * character time +/- some percent. So 1.5 sounds good. All other
181 * Blackfin families operate properly. Woo.
bbf275f0 182 */
8851c71e
MF		 183 if (anomaly_start.tv_sec) {
184 struct timeval curr;
185 suseconds_t usecs;
186
187 if ((~ch & (~ch + 1)) & 0xff)
188 goto known_good_char;
189
190 do_gettimeofday(&curr);
191 if (curr.tv_sec - anomaly_start.tv_sec > 1)
192 goto known_good_char;
193
194 usecs = 0;
195 if (curr.tv_sec != anomaly_start.tv_sec)
196 usecs += USEC_PER_SEC;
197 usecs += curr.tv_usec - anomaly_start.tv_usec;
198
199 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
200 goto known_good_char;
201
202 if (ch)
203 anomaly_start.tv_sec = 0;
204 else
205 anomaly_start = curr;
206
207 return;
208
209 known_good_char:
210 anomaly_start.tv_sec = 0;
bbf275f0 211 }
194de561 212 }
194de561
BW		 213
214 if (status & BI) {
50e2e15a 215 if (ANOMALY_05000363)
8851c71e
MF		 216 if (bfin_revid() < 5)
217 do_gettimeofday(&anomaly_start);
194de561
BW		 218 uart->port.icount.brk++;
219 if (uart_handle_break(&uart->port))
220 goto ignore_char;
9808901b 221 status &= ~(PE | FE);
2ac5ee47
MF		 222 }
223 if (status & PE)
194de561 224 uart->port.icount.parity++;
2ac5ee47 225 if (status & OE)
194de561 226 uart->port.icount.overrun++;
2ac5ee47 227 if (status & FE)
194de561 228 uart->port.icount.frame++;
2ac5ee47
MF		 229
230 status &= uart->port.read_status_mask;
231
232 if (status & BI)
233 flg = TTY_BREAK;
234 else if (status & PE)
235 flg = TTY_PARITY;
236 else if (status & FE)
237 flg = TTY_FRAME;
238 else
194de561
BW		 239 flg = TTY_NORMAL;
240
241 if (uart_handle_sysrq_char(&uart->port, ch))
242 goto ignore_char;
194de561 243
2ac5ee47
MF		 244 uart_insert_char(&uart->port, status, OE, ch, flg);
245
246 ignore_char:
247 tty_flip_buffer_push(tty);
194de561
BW		 248}
249
250static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
251{
252 struct circ_buf *xmit = &uart->port.info->xmit;
253
194de561
BW		 254 /*
255 * Check the modem control lines before
256 * transmitting anything.
257 */
258 bfin_serial_mctrl_check(uart);
259
260 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
5ffdeea2
SZ		 261#ifdef CONFIG_BF54x
262 /* Clear TFI bit */
263 UART_PUT_LSR(uart, TFI);
264#endif
265 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 266 return;
267 }
268
f30ac0ce
SZ		 269 if (uart->port.x_char) {
270 UART_PUT_CHAR(uart, uart->port.x_char);
271 uart->port.icount.tx++;
272 uart->port.x_char = 0;
273 }
274
759eb040
SZ		 275 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
276 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
277 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
278 uart->port.icount.tx++;
279 SSYNC();
280 }
194de561
BW		 281
282 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
283 uart_write_wakeup(&uart->port);
194de561
BW		 284}
285
5c4e472b
AL		 286static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
287{
288 struct bfin_serial_port *uart = dev_id;
289
f4d640c9 290 spin_lock(&uart->port.lock);
0bcfd70e 291 while (UART_GET_LSR(uart) & DR)
f4d640c9 292 bfin_serial_rx_chars(uart);
f4d640c9 293 spin_unlock(&uart->port.lock);
759eb040 294
5c4e472b
AL		 295 return IRQ_HANDLED;
296}
297
298static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 299{
300 struct bfin_serial_port *uart = dev_id;
194de561 301
f4d640c9 302 spin_lock(&uart->port.lock);
0bcfd70e 303 if (UART_GET_LSR(uart) & THRE)
f4d640c9 304 bfin_serial_tx_chars(uart);
f4d640c9 305 spin_unlock(&uart->port.lock);
759eb040 306
194de561
BW		 307 return IRQ_HANDLED;
308}
4cb4f22b 309#endif
194de561 310
194de561
BW		 311#ifdef CONFIG_SERIAL_BFIN_DMA
312static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
313{
314 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 315
194de561
BW		 316 uart->tx_done = 0;
317
f30ac0ce
SZ		 318 /*
319 * Check the modem control lines before
320 * transmitting anything.
321 */
322 bfin_serial_mctrl_check(uart);
323
1b73351c 324 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 325 uart->tx_count = 0;
1b73351c
SZ		 326 uart->tx_done = 1;
327 return;
328 }
329
194de561
BW		 330 if (uart->port.x_char) {
331 UART_PUT_CHAR(uart, uart->port.x_char);
332 uart->port.icount.tx++;
333 uart->port.x_char = 0;
194de561 334 }
1b73351c 335
194de561
BW		 336 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
337 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
338 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
339 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
340 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
341 set_dma_config(uart->tx_dma_channel,
342 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
343 INTR_ON_BUF,
344 DIMENSION_LINEAR,
2047e40d
MH		 345 DATA_SIZE_8,
346 DMA_SYNC_RESTART));
194de561
BW		 347 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
348 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
349 set_dma_x_modify(uart->tx_dma_channel, 1);
350 enable_dma(uart->tx_dma_channel);
99ee7b5f 351
f4d640c9 352 UART_SET_IER(uart, ETBEI);
194de561
BW		 353}
354
2ac5ee47 355static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 356{
a88487c7 357 struct tty_struct *tty = uart->port.info->port.tty;
194de561
BW		 358 int i, flg, status;
359
360 status = UART_GET_LSR(uart);
0bcfd70e
MF		 361 UART_CLEAR_LSR(uart);
362
56f5de8f
SZ		 363 uart->port.icount.rx +=
364 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
365 UART_XMIT_SIZE);
194de561
BW		 366
367 if (status & BI) {
368 uart->port.icount.brk++;
369 if (uart_handle_break(&uart->port))
370 goto dma_ignore_char;
9808901b 371 status &= ~(PE | FE);
2ac5ee47
MF		 372 }
373 if (status & PE)
194de561 374 uart->port.icount.parity++;
2ac5ee47 375 if (status & OE)
194de561 376 uart->port.icount.overrun++;
2ac5ee47 377 if (status & FE)
194de561 378 uart->port.icount.frame++;
2ac5ee47
MF		 379
380 status &= uart->port.read_status_mask;
381
382 if (status & BI)
383 flg = TTY_BREAK;
384 else if (status & PE)
385 flg = TTY_PARITY;
386 else if (status & FE)
387 flg = TTY_FRAME;
388 else
194de561
BW		 389 flg = TTY_NORMAL;
390
56f5de8f
SZ		 391 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
392 if (i >= UART_XMIT_SIZE)
393 i = 0;
394 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
395 uart_insert_char(&uart->port, status, OE,
396 uart->rx_dma_buf.buf[i], flg);
194de561 397 }
2ac5ee47
MF		 398
399 dma_ignore_char:
194de561
BW		 400 tty_flip_buffer_push(tty);
401}
402
403void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
404{
405 int x_pos, pos;
194de561 406
56f5de8f
SZ		 407 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
408 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
409 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
410 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
411 uart->rx_dma_nrows = 0;
412 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 413 if (x_pos == DMA_RX_XCOUNT)
414 x_pos = 0;
415
416 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
56f5de8f
SZ		 417 if (pos != uart->rx_dma_buf.tail) {
418 uart->rx_dma_buf.head = pos;
194de561 419 bfin_serial_dma_rx_chars(uart);
56f5de8f 420 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 421 }
0aef4564 422
0a278423 423 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 424}
425
426static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
427{
428 struct bfin_serial_port *uart = dev_id;
429 struct circ_buf *xmit = &uart->port.info->xmit;
194de561
BW		 430
431 spin_lock(&uart->port.lock);
432 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 433 disable_dma(uart->tx_dma_channel);
0711d857 434 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9 435 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ		 436 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
437 uart->port.icount.tx += uart->tx_count;
1b73351c 438
56f5de8f
SZ		 439 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
440 uart_write_wakeup(&uart->port);
441
1b73351c 442 bfin_serial_dma_tx_chars(uart);
194de561
BW		 443 }
444
445 spin_unlock(&uart->port.lock);
446 return IRQ_HANDLED;
447}
448
449static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
450{
451 struct bfin_serial_port *uart = dev_id;
452 unsigned short irqstat;
0711d857 453
194de561
BW		 454 spin_lock(&uart->port.lock);
455 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
456 clear_dma_irqstat(uart->rx_dma_channel);
194de561 457 spin_unlock(&uart->port.lock);
0aef4564 458
0a278423 459 mod_timer(&(uart->rx_dma_timer), jiffies);
0aef4564 460
194de561
BW		 461 return IRQ_HANDLED;
462}
463#endif
464
465/*
466 * Return TIOCSER_TEMT when transmitter is not busy.
467 */
468static unsigned int bfin_serial_tx_empty(struct uart_port *port)
469{
470 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
471 unsigned short lsr;
472
473 lsr = UART_GET_LSR(uart);
474 if (lsr & TEMT)
475 return TIOCSER_TEMT;
476 else
477 return 0;
478}
479
480static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
481{
482#ifdef CONFIG_SERIAL_BFIN_CTSRTS
483 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
484 if (uart->cts_pin < 0)
485 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
486
1feaa51d 487 if (UART_GET_CTS(uart))
194de561
BW		 488 return TIOCM_DSR | TIOCM_CAR;
489 else
490#endif
491 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
492}
493
494static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
495{
496#ifdef CONFIG_SERIAL_BFIN_CTSRTS
497 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
498 if (uart->rts_pin < 0)
499 return;
500
501 if (mctrl & TIOCM_RTS)
1feaa51d 502 UART_CLEAR_RTS(uart);
194de561 503 else
1feaa51d 504 UART_SET_RTS(uart);
194de561
BW		 505#endif
506}
507
508/*
509 * Handle any change of modem status signal since we were last called.
510 */
511static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
512{
513#ifdef CONFIG_SERIAL_BFIN_CTSRTS
514 unsigned int status;
194de561 515 struct uart_info *info = uart->port.info;
a88487c7 516 struct tty_struct *tty = info->port.tty;
194de561
BW		 517
518 status = bfin_serial_get_mctrl(&uart->port);
4cb4f22b 519 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
194de561
BW		 520 if (!(status & TIOCM_CTS)) {
521 tty->hw_stopped = 1;
f30ac0ce
SZ		 522 uart->cts_timer.data = (unsigned long)(uart);
523 uart->cts_timer.function = (void *)bfin_serial_mctrl_check;
524 uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES;
525 add_timer(&(uart->cts_timer));
194de561
BW		 526 } else {
527 tty->hw_stopped = 0;
528 }
194de561
BW		 529#endif
530}
531
532/*
533 * Interrupts are always disabled.
534 */
535static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
536{
cf686762
MF		 537 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
538 u16 lcr = UART_GET_LCR(uart);
539 if (break_state)
540 lcr |= SB;
541 else
542 lcr &= ~SB;
543 UART_PUT_LCR(uart, lcr);
544 SSYNC();
194de561
BW		 545}
546
547static int bfin_serial_startup(struct uart_port *port)
548{
549 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
550
551#ifdef CONFIG_SERIAL_BFIN_DMA
552 dma_addr_t dma_handle;
553
554 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
555 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
556 return -EBUSY;
557 }
558
559 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
560 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
561 free_dma(uart->rx_dma_channel);
562 return -EBUSY;
563 }
564
565 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
566 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
567
568 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
569 uart->rx_dma_buf.head = 0;
570 uart->rx_dma_buf.tail = 0;
571 uart->rx_dma_nrows = 0;
572
573 set_dma_config(uart->rx_dma_channel,
574 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
575 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 576 DATA_SIZE_8,
577 DMA_SYNC_RESTART));
194de561
BW		 578 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
579 set_dma_x_modify(uart->rx_dma_channel, 1);
580 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
581 set_dma_y_modify(uart->rx_dma_channel, 1);
582 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
583 enable_dma(uart->rx_dma_channel);
584
585 uart->rx_dma_timer.data = (unsigned long)(uart);
586 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
587 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
588 add_timer(&(uart->rx_dma_timer));
589#else
52e15f0e
SZ		 590#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
591 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
592 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
593 kgdboc_break_enabled = 0;
594 else {
595# endif
a359cca7
SZ		 596 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
597 "BFIN_UART_RX", uart)) {
194de561
BW		 598 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
599 return -EBUSY;
600 }
601
602 if (request_irq
5c4e472b 603 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 604 "BFIN_UART_TX", uart)) {
605 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
606 free_irq(uart->port.irq, uart);
607 return -EBUSY;
608 }
ab2375f2
SZ		 609
610# ifdef CONFIG_BF54x
611 {
612 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
613
614 switch (uart->port.irq) {
615 case IRQ_UART3_RX:
616 uart_dma_ch_rx = CH_UART3_RX;
617 uart_dma_ch_tx = CH_UART3_TX;
618 break;
619 case IRQ_UART2_RX:
620 uart_dma_ch_rx = CH_UART2_RX;
621 uart_dma_ch_tx = CH_UART2_TX;
622 break;
623 default:
624 uart_dma_ch_rx = uart_dma_ch_tx = 0;
625 break;
626 };
627
628 if (uart_dma_ch_rx &&
629 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
630 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
631 free_irq(uart->port.irq, uart);
632 free_irq(uart->port.irq + 1, uart);
633 return -EBUSY;
634 }
635 if (uart_dma_ch_tx &&
636 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
637 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
638 free_dma(uart_dma_ch_rx);
639 free_irq(uart->port.irq, uart);
640 free_irq(uart->port.irq + 1, uart);
641 return -EBUSY;
642 }
643 }
644# endif
52e15f0e
SZ		 645#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
646 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
647 }
648# endif
194de561 649#endif
f4d640c9 650 UART_SET_IER(uart, ERBFI);
194de561
BW		 651 return 0;
652}
653
654static void bfin_serial_shutdown(struct uart_port *port)
655{
656 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
657
658#ifdef CONFIG_SERIAL_BFIN_DMA
659 disable_dma(uart->tx_dma_channel);
660 free_dma(uart->tx_dma_channel);
661 disable_dma(uart->rx_dma_channel);
662 free_dma(uart->rx_dma_channel);
663 del_timer(&(uart->rx_dma_timer));
75b780bd 664 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 665#else
ab2375f2
SZ		 666#ifdef CONFIG_BF54x
667 switch (uart->port.irq) {
668 case IRQ_UART3_RX:
669 free_dma(CH_UART3_RX);
670 free_dma(CH_UART3_TX);
671 break;
672 case IRQ_UART2_RX:
673 free_dma(CH_UART2_RX);
674 free_dma(CH_UART2_TX);
675 break;
676 default:
677 break;
678 };
474f1a66 679#endif
194de561
BW		 680 free_irq(uart->port.irq, uart);
681 free_irq(uart->port.irq+1, uart);
682#endif
683}
684
685static void
686bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
687 struct ktermios *old)
688{
689 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
690 unsigned long flags;
691 unsigned int baud, quot;
0c44a86d 692 unsigned short val, ier, lcr = 0;
194de561
BW		 693
694 switch (termios->c_cflag & CSIZE) {
695 case CS8:
696 lcr = WLS(8);
697 break;
698 case CS7:
699 lcr = WLS(7);
700 break;
701 case CS6:
702 lcr = WLS(6);
703 break;
704 case CS5:
705 lcr = WLS(5);
706 break;
707 default:
708 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 709 __func__);
194de561
BW		 710 }
711
712 if (termios->c_cflag & CSTOPB)
713 lcr |= STB;
19aa6382 714 if (termios->c_cflag & PARENB)
194de561 715 lcr |= PEN;
19aa6382
MF		 716 if (!(termios->c_cflag & PARODD))
717 lcr |= EPS;
718 if (termios->c_cflag & CMSPAR)
719 lcr |= STP;
194de561 720
2ac5ee47
MF		 721 port->read_status_mask = OE;
722 if (termios->c_iflag & INPCK)
723 port->read_status_mask |= (FE | PE);
724 if (termios->c_iflag & (BRKINT | PARMRK))
725 port->read_status_mask |= BI;
194de561 726
2ac5ee47
MF		 727 /*
728 * Characters to ignore
729 */
730 port->ignore_status_mask = 0;
731 if (termios->c_iflag & IGNPAR)
732 port->ignore_status_mask |= FE | PE;
733 if (termios->c_iflag & IGNBRK) {
734 port->ignore_status_mask |= BI;
735 /*
736 * If we're ignoring parity and break indicators,
737 * ignore overruns too (for real raw support).
738 */
739 if (termios->c_iflag & IGNPAR)
740 port->ignore_status_mask |= OE;
741 }
194de561
BW		 742
743 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
744 quot = uart_get_divisor(port, baud);
745 spin_lock_irqsave(&uart->port.lock, flags);
746
8851c71e
MF		 747 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
748
194de561
BW		 749 /* Disable UART */
750 ier = UART_GET_IER(uart);
1feaa51d 751 UART_DISABLE_INTS(uart);
194de561
BW		 752
753 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 754 UART_SET_DLAB(uart);
194de561
BW		 755
756 UART_PUT_DLL(uart, quot & 0xFF);
194de561
BW		 757 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
758 SSYNC();
759
760 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 761 UART_CLEAR_DLAB(uart);
194de561
BW		 762
763 UART_PUT_LCR(uart, lcr);
764
765 /* Enable UART */
1feaa51d 766 UART_ENABLE_INTS(uart, ier);
194de561
BW		 767
768 val = UART_GET_GCTL(uart);
769 val |= UCEN;
770 UART_PUT_GCTL(uart, val);
771
b3ef5aba
GY		 772 /* Port speed changed, update the per-port timeout. */
773 uart_update_timeout(port, termios->c_cflag, baud);
774
194de561
BW		 775 spin_unlock_irqrestore(&uart->port.lock, flags);
776}
777
778static const char *bfin_serial_type(struct uart_port *port)
779{
780 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
781
782 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
783}
784
785/*
786 * Release the memory region(s) being used by 'port'.
787 */
788static void bfin_serial_release_port(struct uart_port *port)
789{
790}
791
792/*
793 * Request the memory region(s) being used by 'port'.
794 */
795static int bfin_serial_request_port(struct uart_port *port)
796{
797 return 0;
798}
799
800/*
801 * Configure/autoconfigure the port.
802 */
803static void bfin_serial_config_port(struct uart_port *port, int flags)
804{
805 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
806
807 if (flags & UART_CONFIG_TYPE &&
808 bfin_serial_request_port(&uart->port) == 0)
809 uart->port.type = PORT_BFIN;
810}
811
812/*
813 * Verify the new serial_struct (for TIOCSSERIAL).
814 * The only change we allow are to the flags and type, and
815 * even then only between PORT_BFIN and PORT_UNKNOWN
816 */
817static int
818bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
819{
820 return 0;
821}
822
7d01b475
GY		 823/*
824 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
825 * In other cases, disable IrDA function.
826 */
3b8458a9 827static void bfin_serial_set_ldisc(struct uart_port *port)
7d01b475 828{
3b8458a9 829 int line = port->line;
7d01b475
GY		 830 unsigned short val;
831
a88487c7 832 if (line >= port->info->port.tty->driver->num)
7d01b475
GY		 833 return;
834
b1cbefe5 835 switch (port->info->port.tty->termios->c_line) {
7d01b475
GY		 836 case N_IRDA:
837 val = UART_GET_GCTL(&bfin_serial_ports[line]);
838 val |= (IREN | RPOLC);
839 UART_PUT_GCTL(&bfin_serial_ports[line], val);
840 break;
841 default:
842 val = UART_GET_GCTL(&bfin_serial_ports[line]);
843 val &= ~(IREN | RPOLC);
844 UART_PUT_GCTL(&bfin_serial_ports[line], val);
845 }
846}
847
52e15f0e
SZ		 848#ifdef CONFIG_CONSOLE_POLL
849static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
850{
851 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
852
853 while (!(UART_GET_LSR(uart) & THRE))
854 cpu_relax();
855
856 UART_CLEAR_DLAB(uart);
857 UART_PUT_CHAR(uart, (unsigned char)chr);
858}
859
860static int bfin_serial_poll_get_char(struct uart_port *port)
861{
862 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
863 unsigned char chr;
864
865 while (!(UART_GET_LSR(uart) & DR))
866 cpu_relax();
867
868 UART_CLEAR_DLAB(uart);
869 chr = UART_GET_CHAR(uart);
870
871 return chr;
872}
873#endif
874
875#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
876 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
877static void bfin_kgdboc_port_shutdown(struct uart_port *port)
878{
879 if (kgdboc_break_enabled) {
880 kgdboc_break_enabled = 0;
881 bfin_serial_shutdown(port);
882 }
883}
884
885static int bfin_kgdboc_port_startup(struct uart_port *port)
886{
887 kgdboc_port_line = port->line;
888 kgdboc_break_enabled = !bfin_serial_startup(port);
889 return 0;
890}
891#endif
892
194de561
BW		 893static struct uart_ops bfin_serial_pops = {
894 .tx_empty = bfin_serial_tx_empty,
895 .set_mctrl = bfin_serial_set_mctrl,
896 .get_mctrl = bfin_serial_get_mctrl,
897 .stop_tx = bfin_serial_stop_tx,
898 .start_tx = bfin_serial_start_tx,
899 .stop_rx = bfin_serial_stop_rx,
900 .enable_ms = bfin_serial_enable_ms,
901 .break_ctl = bfin_serial_break_ctl,
902 .startup = bfin_serial_startup,
903 .shutdown = bfin_serial_shutdown,
904 .set_termios = bfin_serial_set_termios,
3b8458a9 905 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 906 .type = bfin_serial_type,
907 .release_port = bfin_serial_release_port,
908 .request_port = bfin_serial_request_port,
909 .config_port = bfin_serial_config_port,
910 .verify_port = bfin_serial_verify_port,
52e15f0e
SZ		 911#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
912 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
913 .kgdboc_port_startup = bfin_kgdboc_port_startup,
914 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
915#endif
916#ifdef CONFIG_CONSOLE_POLL
917 .poll_put_char = bfin_serial_poll_put_char,
918 .poll_get_char = bfin_serial_poll_get_char,
919#endif
194de561
BW		 920};
921
922static void __init bfin_serial_init_ports(void)
923{
924 static int first = 1;
925 int i;
926
927 if (!first)
928 return;
929 first = 0;
930
c9607ecc 931 for (i = 0; i < nr_active_ports; i++) {
194de561 932 bfin_serial_ports[i].port.uartclk = get_sclk();
b3ef5aba 933 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
194de561
BW		 934 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
935 bfin_serial_ports[i].port.line = i;
936 bfin_serial_ports[i].port.iotype = UPIO_MEM;
937 bfin_serial_ports[i].port.membase =
938 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
939 bfin_serial_ports[i].port.mapbase =
940 bfin_serial_resource[i].uart_base_addr;
941 bfin_serial_ports[i].port.irq =
942 bfin_serial_resource[i].uart_irq;
943 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
944#ifdef CONFIG_SERIAL_BFIN_DMA
945 bfin_serial_ports[i].tx_done = 1;
946 bfin_serial_ports[i].tx_count = 0;
947 bfin_serial_ports[i].tx_dma_channel =
948 bfin_serial_resource[i].uart_tx_dma_channel;
949 bfin_serial_ports[i].rx_dma_channel =
950 bfin_serial_resource[i].uart_rx_dma_channel;
951 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561
BW		 952#endif
953#ifdef CONFIG_SERIAL_BFIN_CTSRTS
f30ac0ce 954 init_timer(&(bfin_serial_ports[i].cts_timer));
194de561
BW		 955 bfin_serial_ports[i].cts_pin =
956 bfin_serial_resource[i].uart_cts_pin;
957 bfin_serial_ports[i].rts_pin =
958 bfin_serial_resource[i].uart_rts_pin;
959#endif
960 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 961 }
f4d640c9 962
194de561
BW		 963}
964
965#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 966/*
967 * If the port was already initialised (eg, by a boot loader),
968 * try to determine the current setup.
969 */
970static void __init
971bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
972 int *parity, int *bits)
973{
974 unsigned short status;
975
976 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
977 if (status == (ERBFI | ETBEI)) {
978 /* ok, the port was enabled */
45828b81 979 u16 lcr, dlh, dll;
194de561
BW		 980
981 lcr = UART_GET_LCR(uart);
982
983 *parity = 'n';
984 if (lcr & PEN) {
985 if (lcr & EPS)
986 *parity = 'e';
987 else
988 *parity = 'o';
989 }
990 switch (lcr & 0x03) {
991 case 0: *bits = 5; break;
992 case 1: *bits = 6; break;
993 case 2: *bits = 7; break;
994 case 3: *bits = 8; break;
995 }
996 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 997 UART_SET_DLAB(uart);
194de561
BW		 998
999 dll = UART_GET_DLL(uart);
1000 dlh = UART_GET_DLH(uart);
1001
1002 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 1003 UART_CLEAR_DLAB(uart);
194de561
BW		 1004
1005 *baud = get_sclk() / (16*(dll | dlh << 8));
1006 }
71cc2c21 1007 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 1008}
0ae53640
RG		 1009#endif
1010
1011#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1012static struct uart_driver bfin_serial_reg;
194de561
BW		 1013
1014static int __init
1015bfin_serial_console_setup(struct console *co, char *options)
1016{
1017 struct bfin_serial_port *uart;
0ae53640 1018# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1019 int baud = 57600;
1020 int bits = 8;
1021 int parity = 'n';
0ae53640 1022# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1023 int flow = 'r';
0ae53640 1024# else
194de561 1025 int flow = 'n';
0ae53640
RG		 1026# endif
1027# endif
194de561
BW		 1028
1029 /*
1030 * Check whether an invalid uart number has been specified, and
1031 * if so, search for the first available port that does have
1032 * console support.
1033 */
c9607ecc 1034 if (co->index == -1 || co->index >= nr_active_ports)
194de561
BW		 1035 co->index = 0;
1036 uart = &bfin_serial_ports[co->index];
1037
0ae53640 1038# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1039 if (options)
1040 uart_parse_options(options, &baud, &parity, &bits, &flow);
1041 else
1042 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1043
1044 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1045# else
1046 return 0;
1047# endif
1048}
1049#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1050 defined (CONFIG_EARLY_PRINTK) */
1051
1052#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1053static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1054{
1055 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1056 while (!(UART_GET_LSR(uart) & THRE))
1057 barrier();
1058 UART_PUT_CHAR(uart, ch);
1059 SSYNC();
1060}
1061
1062/*
1063 * Interrupts are disabled on entering
1064 */
1065static void
1066bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1067{
1068 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1069 int flags = 0;
1070
1071 spin_lock_irqsave(&uart->port.lock, flags);
1072 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1073 spin_unlock_irqrestore(&uart->port.lock, flags);
1074
194de561
BW		 1075}
1076
194de561
BW		 1077static struct console bfin_serial_console = {
1078 .name = BFIN_SERIAL_NAME,
1079 .write = bfin_serial_console_write,
1080 .device = uart_console_device,
1081 .setup = bfin_serial_console_setup,
1082 .flags = CON_PRINTBUFFER,
1083 .index = -1,
1084 .data = &bfin_serial_reg,
1085};
1086
1087static int __init bfin_serial_rs_console_init(void)
1088{
1089 bfin_serial_init_ports();
1090 register_console(&bfin_serial_console);
52e15f0e 1091
194de561
BW		 1092 return 0;
1093}
1094console_initcall(bfin_serial_rs_console_init);
1095
1096#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1097#else
1098#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1099#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1100
1101
1102#ifdef CONFIG_EARLY_PRINTK
1103static __init void early_serial_putc(struct uart_port *port, int ch)
1104{
1105 unsigned timeout = 0xffff;
1106 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1107
1108 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1109 cpu_relax();
1110 UART_PUT_CHAR(uart, ch);
1111}
1112
1113static __init void early_serial_write(struct console *con, const char *s,
1114 unsigned int n)
1115{
1116 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1117 unsigned int i;
1118
1119 for (i = 0; i < n; i++, s++) {
1120 if (*s == '\n')
1121 early_serial_putc(&uart->port, '\r');
1122 early_serial_putc(&uart->port, *s);
1123 }
1124}
1125
c1113400 1126static struct __initdata console bfin_early_serial_console = {
0ae53640
RG		 1127 .name = "early_BFuart",
1128 .write = early_serial_write,
1129 .device = uart_console_device,
1130 .flags = CON_PRINTBUFFER,
1131 .setup = bfin_serial_console_setup,
1132 .index = -1,
1133 .data = &bfin_serial_reg,
1134};
1135
1136struct console __init *bfin_earlyserial_init(unsigned int port,
1137 unsigned int cflag)
1138{
1139 struct bfin_serial_port *uart;
1140 struct ktermios t;
1141
c9607ecc 1142 if (port == -1 || port >= nr_active_ports)
0ae53640
RG		 1143 port = 0;
1144 bfin_serial_init_ports();
1145 bfin_early_serial_console.index = port;
0ae53640
RG		 1146 uart = &bfin_serial_ports[port];
1147 t.c_cflag = cflag;
1148 t.c_iflag = 0;
1149 t.c_oflag = 0;
1150 t.c_lflag = ICANON;
1151 t.c_line = port;
1152 bfin_serial_set_termios(&uart->port, &t, &t);
1153 return &bfin_early_serial_console;
1154}
1155
1156#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW		 1157
1158static struct uart_driver bfin_serial_reg = {
1159 .owner = THIS_MODULE,
1160 .driver_name = "bfin-uart",
1161 .dev_name = BFIN_SERIAL_NAME,
1162 .major = BFIN_SERIAL_MAJOR,
1163 .minor = BFIN_SERIAL_MINOR,
2ade9729 1164 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1165 .cons = BFIN_SERIAL_CONSOLE,
1166};
1167
1168static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1169{
ccfbc3e1 1170 int i;
194de561 1171
c9607ecc 1172 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1173 if (bfin_serial_ports[i].port.dev != &dev->dev)
1174 continue;
1175 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1176 }
194de561
BW		 1177
1178 return 0;
1179}
1180
1181static int bfin_serial_resume(struct platform_device *dev)
1182{
ccfbc3e1 1183 int i;
194de561 1184
c9607ecc 1185 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1186 if (bfin_serial_ports[i].port.dev != &dev->dev)
1187 continue;
1188 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1189 }
194de561
BW		 1190
1191 return 0;
1192}
1193
1194static int bfin_serial_probe(struct platform_device *dev)
1195{
1196 struct resource *res = dev->resource;
1197 int i;
1198
1199 for (i = 0; i < dev->num_resources; i++, res++)
1200 if (res->flags & IORESOURCE_MEM)
1201 break;
1202
1203 if (i < dev->num_resources) {
c9607ecc 1204 for (i = 0; i < nr_active_ports; i++, res++) {
194de561
BW		 1205 if (bfin_serial_ports[i].port.mapbase != res->start)
1206 continue;
1207 bfin_serial_ports[i].port.dev = &dev->dev;
1208 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
194de561
BW		 1209 }
1210 }
1211
1212 return 0;
1213}
1214
ccfbc3e1 1215static int bfin_serial_remove(struct platform_device *dev)
194de561 1216{
ccfbc3e1 1217 int i;
194de561 1218
c9607ecc 1219 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1220 if (bfin_serial_ports[i].port.dev != &dev->dev)
1221 continue;
1222 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1223 bfin_serial_ports[i].port.dev = NULL;
194de561 1224#ifdef CONFIG_SERIAL_BFIN_CTSRTS
ccfbc3e1
SZ		 1225 gpio_free(bfin_serial_ports[i].cts_pin);
1226 gpio_free(bfin_serial_ports[i].rts_pin);
194de561 1227#endif
ccfbc3e1 1228 }
194de561
BW		 1229
1230 return 0;
1231}
1232
1233static struct platform_driver bfin_serial_driver = {
1234 .probe = bfin_serial_probe,
1235 .remove = bfin_serial_remove,
1236 .suspend = bfin_serial_suspend,
1237 .resume = bfin_serial_resume,
1238 .driver = {
1239 .name = "bfin-uart",
e169c139 1240 .owner = THIS_MODULE,
194de561
BW		 1241 },
1242};
1243
1244static int __init bfin_serial_init(void)
1245{
1246 int ret;
1247
1248 pr_info("Serial: Blackfin serial driver\n");
1249
1250 bfin_serial_init_ports();
1251
1252 ret = uart_register_driver(&bfin_serial_reg);
1253 if (ret == 0) {
1254 ret = platform_driver_register(&bfin_serial_driver);
1255 if (ret) {
1256 pr_debug("uart register failed\n");
1257 uart_unregister_driver(&bfin_serial_reg);
1258 }
1259 }
1260 return ret;
1261}
1262
1263static void __exit bfin_serial_exit(void)
1264{
1265 platform_driver_unregister(&bfin_serial_driver);
1266 uart_unregister_driver(&bfin_serial_reg);
1267}
1268
52e15f0e 1269
194de561
BW		 1270module_init(bfin_serial_init);
1271module_exit(bfin_serial_exit);
1272
1273MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1274MODULE_DESCRIPTION("Blackfin generic serial port driver");
1275MODULE_LICENSE("GPL");
1276MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1277MODULE_ALIAS("platform:bfin-uart");
Linux 6.x block layer and io_uring tree(s)