atmel_serial: split the interrupt handler
[linux-block.git] / drivers / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
93a3ddc2 36#include <linux/atmel_pdc.h>
fa3218d8 37#include <linux/atmel_serial.h>
1e6c9c28
AV
38
39#include <asm/io.h>
40
afefc415 41#include <asm/mach/serial_at91.h>
1e6c9c28 42#include <asm/arch/board.h>
93a3ddc2 43
acca9b83 44#ifdef CONFIG_ARM
c2f5ccfb 45#include <asm/arch/cpu.h>
20e65276 46#include <asm/arch/gpio.h>
acca9b83 47#endif
1e6c9c28 48
749c4e60 49#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
749c4e60 55#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
56
57/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
58 * should coexist with the 8250 driver, such as if we have an external 16C550
59 * UART. */
7192f92c 60#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 61#define MINOR_START 154
7192f92c 62#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
63
64#else
65
66/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
67 * name, but it is legally reserved for the 8250 driver. */
7192f92c 68#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 69#define MINOR_START 64
7192f92c 70#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
71
72#endif
73
7192f92c 74#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 75
b843aa21 76/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS
77#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
78#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
79#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
80#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
81#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
82#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
83#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
84#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
85#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
86#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
87#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
88#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
89
1e6c9c28 90 /* PDC registers */
544fc728
HS
91#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
92#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
93
94#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
95#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
96#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
97#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
98#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
99
100#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
101#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
1e6c9c28 102
71f2e2b8
HS
103static int (*atmel_open_hook)(struct uart_port *);
104static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 105
1ecc26bd
RB
106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
111#define ATMEL_SERIAL_RINGSIZE 1024
112
afefc415
AV
113/*
114 * We wrap our port structure around the generic uart_port.
115 */
7192f92c 116struct atmel_uart_port {
afefc415
AV
117 struct uart_port uart; /* uart */
118 struct clk *clk; /* uart clock */
119 unsigned short suspended; /* is port suspended? */
9e6077bd 120 int break_active; /* break being received */
1ecc26bd
RB
121
122 struct tasklet_struct tasklet;
123 unsigned int irq_status;
124 unsigned int irq_status_prev;
125
126 struct circ_buf rx_ring;
afefc415
AV
127};
128
7192f92c 129static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 130
1e6c9c28 131#ifdef SUPPORT_SYSRQ
7192f92c 132static struct console atmel_console;
1e6c9c28
AV
133#endif
134
135/*
136 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
137 */
7192f92c 138static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 139{
7192f92c 140 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
141}
142
143/*
144 * Set state of the modem control output lines
145 */
7192f92c 146static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
147{
148 unsigned int control = 0;
afefc415 149 unsigned int mode;
1e6c9c28 150
c2f5ccfb 151#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 152 if (cpu_is_at91rm9200()) {
afefc415 153 /*
b843aa21
RB
154 * AT91RM9200 Errata #39: RTS0 is not internally connected
155 * to PA21. We need to drive the pin manually.
afefc415 156 */
72729910 157 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 158 if (mctrl & TIOCM_RTS)
20e65276 159 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 160 else
20e65276 161 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 162 }
1e6c9c28 163 }
acca9b83 164#endif
1e6c9c28
AV
165
166 if (mctrl & TIOCM_RTS)
7192f92c 167 control |= ATMEL_US_RTSEN;
1e6c9c28 168 else
7192f92c 169 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
170
171 if (mctrl & TIOCM_DTR)
7192f92c 172 control |= ATMEL_US_DTREN;
1e6c9c28 173 else
7192f92c 174 control |= ATMEL_US_DTRDIS;
1e6c9c28 175
afefc415
AV
176 UART_PUT_CR(port, control);
177
178 /* Local loopback mode? */
7192f92c 179 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 180 if (mctrl & TIOCM_LOOP)
7192f92c 181 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 182 else
7192f92c 183 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 184 UART_PUT_MR(port, mode);
1e6c9c28
AV
185}
186
187/*
188 * Get state of the modem control input lines
189 */
7192f92c 190static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
191{
192 unsigned int status, ret = 0;
193
194 status = UART_GET_CSR(port);
195
196 /*
197 * The control signals are active low.
198 */
7192f92c 199 if (!(status & ATMEL_US_DCD))
1e6c9c28 200 ret |= TIOCM_CD;
7192f92c 201 if (!(status & ATMEL_US_CTS))
1e6c9c28 202 ret |= TIOCM_CTS;
7192f92c 203 if (!(status & ATMEL_US_DSR))
1e6c9c28 204 ret |= TIOCM_DSR;
7192f92c 205 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
206 ret |= TIOCM_RI;
207
208 return ret;
209}
210
211/*
212 * Stop transmitting.
213 */
7192f92c 214static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 215{
7192f92c 216 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
217}
218
219/*
220 * Start transmitting.
221 */
7192f92c 222static void atmel_start_tx(struct uart_port *port)
1e6c9c28 223{
7192f92c 224 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
225}
226
227/*
228 * Stop receiving - port is in process of being closed.
229 */
7192f92c 230static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 231{
7192f92c 232 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
233}
234
235/*
236 * Enable modem status interrupts
237 */
7192f92c 238static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 239{
b843aa21
RB
240 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
241 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
242}
243
244/*
245 * Control the transmission of a break signal
246 */
7192f92c 247static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
248{
249 if (break_state != 0)
7192f92c 250 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 251 else
7192f92c 252 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
253}
254
1ecc26bd
RB
255/*
256 * Stores the incoming character in the ring buffer
257 */
258static void
259atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
260 unsigned int ch)
261{
262 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
263 struct circ_buf *ring = &atmel_port->rx_ring;
264 struct atmel_uart_char *c;
265
266 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
267 /* Buffer overflow, ignore char */
268 return;
269
270 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
271 c->status = status;
272 c->ch = ch;
273
274 /* Make sure the character is stored before we update head. */
275 smp_wmb();
276
277 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
278}
279
1e6c9c28
AV
280/*
281 * Characters received (called from interrupt handler)
282 */
7d12e780 283static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 284{
b843aa21 285 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
1ecc26bd 286 unsigned int status, ch;
1e6c9c28 287
afefc415 288 status = UART_GET_CSR(port);
7192f92c 289 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
290 ch = UART_GET_CHAR(port);
291
1e6c9c28
AV
292 /*
293 * note that the error handling code is
294 * out of the main execution path
295 */
9e6077bd
HS
296 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
297 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
298 || atmel_port->break_active)) {
1ecc26bd 299
b843aa21
RB
300 /* clear error */
301 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 302
9e6077bd
HS
303 if (status & ATMEL_US_RXBRK
304 && !atmel_port->break_active) {
9e6077bd
HS
305 atmel_port->break_active = 1;
306 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS
307 } else {
308 /*
309 * This is either the end-of-break
310 * condition or we've received at
311 * least one character without RXBRK
312 * being set. In both cases, the next
313 * RXBRK will indicate start-of-break.
314 */
315 UART_PUT_IDR(port, ATMEL_US_RXBRK);
316 status &= ~ATMEL_US_RXBRK;
317 atmel_port->break_active = 0;
afefc415 318 }
1e6c9c28
AV
319 }
320
1ecc26bd 321 atmel_buffer_rx_char(port, status, ch);
afefc415 322 status = UART_GET_CSR(port);
1e6c9c28
AV
323 }
324
1ecc26bd 325 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV
326}
327
328/*
1ecc26bd
RB
329 * Transmit characters (called from tasklet with TXRDY interrupt
330 * disabled)
1e6c9c28 331 */
7192f92c 332static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
333{
334 struct circ_buf *xmit = &port->info->xmit;
335
1ecc26bd 336 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
337 UART_PUT_CHAR(port, port->x_char);
338 port->icount.tx++;
339 port->x_char = 0;
1e6c9c28 340 }
1ecc26bd 341 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 342 return;
1e6c9c28 343
7192f92c 344 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
345 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
346 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
347 port->icount.tx++;
348 if (uart_circ_empty(xmit))
349 break;
350 }
351
352 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
353 uart_write_wakeup(port);
354
1ecc26bd
RB
355 if (!uart_circ_empty(xmit))
356 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
357}
358
b843aa21
RB
359/*
360 * receive interrupt handler.
361 */
362static void
363atmel_handle_receive(struct uart_port *port, unsigned int pending)
364{
365 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
366
367 /* Interrupt receive */
368 if (pending & ATMEL_US_RXRDY)
369 atmel_rx_chars(port);
370 else if (pending & ATMEL_US_RXBRK) {
371 /*
372 * End of break detected. If it came along with a
373 * character, atmel_rx_chars will handle it.
374 */
375 UART_PUT_CR(port, ATMEL_US_RSTSTA);
376 UART_PUT_IDR(port, ATMEL_US_RXBRK);
377 atmel_port->break_active = 0;
378 }
379}
380
381/*
1ecc26bd 382 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB
383 */
384static void
385atmel_handle_transmit(struct uart_port *port, unsigned int pending)
386{
1ecc26bd
RB
387 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
388
b843aa21 389 /* Interrupt transmit */
1ecc26bd
RB
390 if (pending & ATMEL_US_TXRDY) {
391 UART_PUT_IDR(port, ATMEL_US_TXRDY);
392 tasklet_schedule(&atmel_port->tasklet);
393 }
b843aa21
RB
394}
395
396/*
397 * status flags interrupt handler.
398 */
399static void
400atmel_handle_status(struct uart_port *port, unsigned int pending,
401 unsigned int status)
402{
1ecc26bd
RB
403 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
404
b843aa21 405 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB
406 | ATMEL_US_CTSIC)) {
407 atmel_port->irq_status = status;
408 tasklet_schedule(&atmel_port->tasklet);
409 }
b843aa21
RB
410}
411
1e6c9c28
AV
412/*
413 * Interrupt handler
414 */
7d12e780 415static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
416{
417 struct uart_port *port = dev_id;
418 unsigned int status, pending, pass_counter = 0;
419
420 status = UART_GET_CSR(port);
afefc415
AV
421 pending = status & UART_GET_IMR(port);
422 while (pending) {
b843aa21
RB
423 atmel_handle_receive(port, pending);
424 atmel_handle_status(port, pending, status);
425 atmel_handle_transmit(port, pending);
afefc415 426
7192f92c 427 if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
afefc415 428 break;
1e6c9c28 429
afefc415
AV
430 status = UART_GET_CSR(port);
431 pending = status & UART_GET_IMR(port);
1e6c9c28
AV
432 }
433 return IRQ_HANDLED;
434}
435
1ecc26bd
RB
436static void atmel_rx_from_ring(struct uart_port *port)
437{
438 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
439 struct circ_buf *ring = &atmel_port->rx_ring;
440 unsigned int flg;
441 unsigned int status;
442
443 while (ring->head != ring->tail) {
444 struct atmel_uart_char c;
445
446 /* Make sure c is loaded after head. */
447 smp_rmb();
448
449 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
450
451 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
452
453 port->icount.rx++;
454 status = c.status;
455 flg = TTY_NORMAL;
456
457 /*
458 * note that the error handling code is
459 * out of the main execution path
460 */
461 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
462 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
463 if (status & ATMEL_US_RXBRK) {
464 /* ignore side-effect */
465 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
466
467 port->icount.brk++;
468 if (uart_handle_break(port))
469 continue;
470 }
471 if (status & ATMEL_US_PARE)
472 port->icount.parity++;
473 if (status & ATMEL_US_FRAME)
474 port->icount.frame++;
475 if (status & ATMEL_US_OVRE)
476 port->icount.overrun++;
477
478 status &= port->read_status_mask;
479
480 if (status & ATMEL_US_RXBRK)
481 flg = TTY_BREAK;
482 else if (status & ATMEL_US_PARE)
483 flg = TTY_PARITY;
484 else if (status & ATMEL_US_FRAME)
485 flg = TTY_FRAME;
486 }
487
488
489 if (uart_handle_sysrq_char(port, c.ch))
490 continue;
491
492 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
493 }
494
495 /*
496 * Drop the lock here since it might end up calling
497 * uart_start(), which takes the lock.
498 */
499 spin_unlock(&port->lock);
500 tty_flip_buffer_push(port->info->tty);
501 spin_lock(&port->lock);
502}
503
504/*
505 * tasklet handling tty stuff outside the interrupt handler.
506 */
507static void atmel_tasklet_func(unsigned long data)
508{
509 struct uart_port *port = (struct uart_port *)data;
510 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
511 unsigned int status;
512 unsigned int status_change;
513
514 /* The interrupt handler does not take the lock */
515 spin_lock(&port->lock);
516
517 atmel_tx_chars(port);
518
519 status = atmel_port->irq_status;
520 status_change = status ^ atmel_port->irq_status_prev;
521
522 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
523 | ATMEL_US_DCD | ATMEL_US_CTS)) {
524 /* TODO: All reads to CSR will clear these interrupts! */
525 if (status_change & ATMEL_US_RI)
526 port->icount.rng++;
527 if (status_change & ATMEL_US_DSR)
528 port->icount.dsr++;
529 if (status_change & ATMEL_US_DCD)
530 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
531 if (status_change & ATMEL_US_CTS)
532 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
533
534 wake_up_interruptible(&port->info->delta_msr_wait);
535
536 atmel_port->irq_status_prev = status;
537 }
538
539 atmel_rx_from_ring(port);
540
541 spin_unlock(&port->lock);
542}
543
1e6c9c28
AV
544/*
545 * Perform initialization and enable port for reception
546 */
7192f92c 547static int atmel_startup(struct uart_port *port)
1e6c9c28
AV
548{
549 int retval;
550
551 /*
552 * Ensure that no interrupts are enabled otherwise when
553 * request_irq() is called we could get stuck trying to
554 * handle an unexpected interrupt
555 */
556 UART_PUT_IDR(port, -1);
557
558 /*
559 * Allocate the IRQ
560 */
b843aa21
RB
561 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
562 "atmel_serial", port);
1e6c9c28 563 if (retval) {
7192f92c 564 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
565 return retval;
566 }
567
568 /*
569 * If there is a specific "open" function (to register
570 * control line interrupts)
571 */
71f2e2b8
HS
572 if (atmel_open_hook) {
573 retval = atmel_open_hook(port);
1e6c9c28
AV
574 if (retval) {
575 free_irq(port->irq, port);
576 return retval;
577 }
578 }
579
1e6c9c28
AV
580 /*
581 * Finally, enable the serial port
582 */
7192f92c 583 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB
584 /* enable xmit & rcvr */
585 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 586
b843aa21
RB
587 /* enable receive only */
588 UART_PUT_IER(port, ATMEL_US_RXRDY);
afefc415 589
1e6c9c28
AV
590 return 0;
591}
592
593/*
594 * Disable the port
595 */
7192f92c 596static void atmel_shutdown(struct uart_port *port)
1e6c9c28
AV
597{
598 /*
599 * Disable all interrupts, port and break condition.
600 */
7192f92c 601 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
602 UART_PUT_IDR(port, -1);
603
604 /*
605 * Free the interrupt
606 */
607 free_irq(port->irq, port);
608
609 /*
610 * If there is a specific "close" function (to unregister
611 * control line interrupts)
612 */
71f2e2b8
HS
613 if (atmel_close_hook)
614 atmel_close_hook(port);
1e6c9c28
AV
615}
616
617/*
618 * Power / Clock management.
619 */
b843aa21
RB
620static void atmel_serial_pm(struct uart_port *port, unsigned int state,
621 unsigned int oldstate)
1e6c9c28 622{
b843aa21 623 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415 624
1e6c9c28 625 switch (state) {
b843aa21
RB
626 case 0:
627 /*
628 * Enable the peripheral clock for this serial port.
629 * This is called on uart_open() or a resume event.
630 */
631 clk_enable(atmel_port->clk);
632 break;
633 case 3:
634 /*
635 * Disable the peripheral clock for this serial port.
636 * This is called on uart_close() or a suspend event.
637 */
638 clk_disable(atmel_port->clk);
639 break;
640 default:
641 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
642 }
643}
644
645/*
646 * Change the port parameters
647 */
b843aa21
RB
648static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
649 struct ktermios *old)
1e6c9c28
AV
650{
651 unsigned long flags;
652 unsigned int mode, imr, quot, baud;
653
03abeac0 654 /* Get current mode register */
b843aa21
RB
655 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
656 | ATMEL_US_NBSTOP | ATMEL_US_PAR);
03abeac0 657
b843aa21 658 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV
659 quot = uart_get_divisor(port, baud);
660
b843aa21 661 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV
662 quot /= 8;
663 mode |= ATMEL_US_USCLKS_MCK_DIV8;
664 }
1e6c9c28
AV
665
666 /* byte size */
667 switch (termios->c_cflag & CSIZE) {
668 case CS5:
7192f92c 669 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
670 break;
671 case CS6:
7192f92c 672 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
673 break;
674 case CS7:
7192f92c 675 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
676 break;
677 default:
7192f92c 678 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
679 break;
680 }
681
682 /* stop bits */
683 if (termios->c_cflag & CSTOPB)
7192f92c 684 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
685
686 /* parity */
687 if (termios->c_cflag & PARENB) {
b843aa21
RB
688 /* Mark or Space parity */
689 if (termios->c_cflag & CMSPAR) {
1e6c9c28 690 if (termios->c_cflag & PARODD)
7192f92c 691 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 692 else
7192f92c 693 mode |= ATMEL_US_PAR_SPACE;
b843aa21 694 } else if (termios->c_cflag & PARODD)
7192f92c 695 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 696 else
7192f92c 697 mode |= ATMEL_US_PAR_EVEN;
b843aa21 698 } else
7192f92c 699 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
700
701 spin_lock_irqsave(&port->lock, flags);
702
7192f92c 703 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 704 if (termios->c_iflag & INPCK)
7192f92c 705 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 706 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 707 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
708
709 /*
710 * Characters to ignore
711 */
712 port->ignore_status_mask = 0;
713 if (termios->c_iflag & IGNPAR)
7192f92c 714 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 715 if (termios->c_iflag & IGNBRK) {
7192f92c 716 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
717 /*
718 * If we're ignoring parity and break indicators,
719 * ignore overruns too (for real raw support).
720 */
721 if (termios->c_iflag & IGNPAR)
7192f92c 722 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 723 }
b843aa21 724 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV
725
726 /* update the per-port timeout */
727 uart_update_timeout(port, termios->c_cflag, baud);
728
b843aa21
RB
729 /* save/disable interrupts and drain transmitter */
730 imr = UART_GET_IMR(port);
731 UART_PUT_IDR(port, -1);
732 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
829dd811 733 cpu_relax();
1e6c9c28
AV
734
735 /* disable receiver and transmitter */
7192f92c 736 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
737
738 /* set the parity, stop bits and data size */
739 UART_PUT_MR(port, mode);
740
741 /* set the baud rate */
742 UART_PUT_BRGR(port, quot);
7192f92c
HS
743 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
744 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
745
746 /* restore interrupts */
747 UART_PUT_IER(port, imr);
748
749 /* CTS flow-control and modem-status interrupts */
750 if (UART_ENABLE_MS(port, termios->c_cflag))
751 port->ops->enable_ms(port);
752
753 spin_unlock_irqrestore(&port->lock, flags);
754}
755
756/*
757 * Return string describing the specified port
758 */
7192f92c 759static const char *atmel_type(struct uart_port *port)
1e6c9c28 760{
9ab4f88b 761 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
762}
763
764/*
765 * Release the memory region(s) being used by 'port'.
766 */
7192f92c 767static void atmel_release_port(struct uart_port *port)
1e6c9c28 768{
afefc415
AV
769 struct platform_device *pdev = to_platform_device(port->dev);
770 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
771
772 release_mem_region(port->mapbase, size);
773
774 if (port->flags & UPF_IOREMAP) {
775 iounmap(port->membase);
776 port->membase = NULL;
777 }
1e6c9c28
AV
778}
779
780/*
781 * Request the memory region(s) being used by 'port'.
782 */
7192f92c 783static int atmel_request_port(struct uart_port *port)
1e6c9c28 784{
afefc415
AV
785 struct platform_device *pdev = to_platform_device(port->dev);
786 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
787
7192f92c 788 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
789 return -EBUSY;
790
791 if (port->flags & UPF_IOREMAP) {
792 port->membase = ioremap(port->mapbase, size);
793 if (port->membase == NULL) {
794 release_mem_region(port->mapbase, size);
795 return -ENOMEM;
796 }
797 }
1e6c9c28 798
afefc415 799 return 0;
1e6c9c28
AV
800}
801
802/*
803 * Configure/autoconfigure the port.
804 */
7192f92c 805static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
806{
807 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 808 port->type = PORT_ATMEL;
7192f92c 809 atmel_request_port(port);
1e6c9c28
AV
810 }
811}
812
813/*
814 * Verify the new serial_struct (for TIOCSSERIAL).
815 */
7192f92c 816static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
817{
818 int ret = 0;
9ab4f88b 819 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
820 ret = -EINVAL;
821 if (port->irq != ser->irq)
822 ret = -EINVAL;
823 if (ser->io_type != SERIAL_IO_MEM)
824 ret = -EINVAL;
825 if (port->uartclk / 16 != ser->baud_base)
826 ret = -EINVAL;
827 if ((void *)port->mapbase != ser->iomem_base)
828 ret = -EINVAL;
829 if (port->iobase != ser->port)
830 ret = -EINVAL;
831 if (ser->hub6 != 0)
832 ret = -EINVAL;
833 return ret;
834}
835
7192f92c
HS
836static struct uart_ops atmel_pops = {
837 .tx_empty = atmel_tx_empty,
838 .set_mctrl = atmel_set_mctrl,
839 .get_mctrl = atmel_get_mctrl,
840 .stop_tx = atmel_stop_tx,
841 .start_tx = atmel_start_tx,
842 .stop_rx = atmel_stop_rx,
843 .enable_ms = atmel_enable_ms,
844 .break_ctl = atmel_break_ctl,
845 .startup = atmel_startup,
846 .shutdown = atmel_shutdown,
847 .set_termios = atmel_set_termios,
848 .type = atmel_type,
849 .release_port = atmel_release_port,
850 .request_port = atmel_request_port,
851 .config_port = atmel_config_port,
852 .verify_port = atmel_verify_port,
853 .pm = atmel_serial_pm,
1e6c9c28
AV
854};
855
afefc415
AV
856/*
857 * Configure the port from the platform device resource info.
858 */
b843aa21
RB
859static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
860 struct platform_device *pdev)
1e6c9c28 861{
7192f92c 862 struct uart_port *port = &atmel_port->uart;
73e2798b 863 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
864
865 port->iotype = UPIO_MEM;
a14d5273 866 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 867 port->ops = &atmel_pops;
a14d5273 868 port->fifosize = 1;
afefc415
AV
869 port->line = pdev->id;
870 port->dev = &pdev->dev;
871
872 port->mapbase = pdev->resource[0].start;
873 port->irq = pdev->resource[1].start;
874
1ecc26bd
RB
875 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
876 (unsigned long)port);
877
878 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
879
75d35213
HS
880 if (data->regs)
881 /* Already mapped by setup code */
882 port->membase = data->regs;
afefc415
AV
883 else {
884 port->flags |= UPF_IOREMAP;
885 port->membase = NULL;
886 }
1e6c9c28 887
b843aa21
RB
888 /* for console, the clock could already be configured */
889 if (!atmel_port->clk) {
7192f92c
HS
890 atmel_port->clk = clk_get(&pdev->dev, "usart");
891 clk_enable(atmel_port->clk);
892 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 893 }
1e6c9c28
AV
894}
895
afefc415
AV
896/*
897 * Register board-specific modem-control line handlers.
898 */
71f2e2b8 899void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
900{
901 if (fns->enable_ms)
7192f92c 902 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 903 if (fns->get_mctrl)
7192f92c 904 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 905 if (fns->set_mctrl)
7192f92c 906 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
907 atmel_open_hook = fns->open;
908 atmel_close_hook = fns->close;
7192f92c
HS
909 atmel_pops.pm = fns->pm;
910 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
911}
912
749c4e60 913#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 914static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 915{
7192f92c 916 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 917 cpu_relax();
d358788f
RK
918 UART_PUT_CHAR(port, ch);
919}
1e6c9c28
AV
920
921/*
922 * Interrupts are disabled on entering
923 */
7192f92c 924static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 925{
7192f92c 926 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 927 unsigned int status, imr;
1e6c9c28
AV
928
929 /*
b843aa21 930 * First, save IMR and then disable interrupts
1e6c9c28 931 */
b843aa21 932 imr = UART_GET_IMR(port);
7192f92c 933 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 934
7192f92c 935 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
936
937 /*
b843aa21
RB
938 * Finally, wait for transmitter to become empty
939 * and restore IMR
1e6c9c28
AV
940 */
941 do {
942 status = UART_GET_CSR(port);
7192f92c 943 } while (!(status & ATMEL_US_TXRDY));
b843aa21
RB
944 /* set interrupts back the way they were */
945 UART_PUT_IER(port, imr);
1e6c9c28
AV
946}
947
948/*
b843aa21
RB
949 * If the port was already initialised (eg, by a boot loader),
950 * try to determine the current setup.
1e6c9c28 951 */
b843aa21
RB
952static void __init atmel_console_get_options(struct uart_port *port, int *baud,
953 int *parity, int *bits)
1e6c9c28
AV
954{
955 unsigned int mr, quot;
956
1c0fd82f
HS
957 /*
958 * If the baud rate generator isn't running, the port wasn't
959 * initialized by the boot loader.
960 */
961 quot = UART_GET_BRGR(port);
962 if (!quot)
963 return;
1e6c9c28 964
7192f92c
HS
965 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
966 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
967 *bits = 8;
968 else
969 *bits = 7;
970
7192f92c
HS
971 mr = UART_GET_MR(port) & ATMEL_US_PAR;
972 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 973 *parity = 'e';
7192f92c 974 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
975 *parity = 'o';
976
4d5e392c
HS
977 /*
978 * The serial core only rounds down when matching this to a
979 * supported baud rate. Make sure we don't end up slightly
980 * lower than one of those, as it would make us fall through
981 * to a much lower baud rate than we really want.
982 */
4d5e392c 983 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
984}
985
7192f92c 986static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 987{
7192f92c 988 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
989 int baud = 115200;
990 int bits = 8;
991 int parity = 'n';
992 int flow = 'n';
993
b843aa21
RB
994 if (port->membase == NULL) {
995 /* Port not initialized yet - delay setup */
afefc415 996 return -ENODEV;
b843aa21 997 }
1e6c9c28 998
b843aa21 999 UART_PUT_IDR(port, -1);
7192f92c
HS
1000 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1001 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1002
1003 if (options)
1004 uart_parse_options(options, &baud, &parity, &bits, &flow);
1005 else
7192f92c 1006 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
1007
1008 return uart_set_options(port, co, baud, parity, bits, flow);
1009}
1010
7192f92c 1011static struct uart_driver atmel_uart;
1e6c9c28 1012
7192f92c
HS
1013static struct console atmel_console = {
1014 .name = ATMEL_DEVICENAME,
1015 .write = atmel_console_write,
1e6c9c28 1016 .device = uart_console_device,
7192f92c 1017 .setup = atmel_console_setup,
1e6c9c28
AV
1018 .flags = CON_PRINTBUFFER,
1019 .index = -1,
7192f92c 1020 .data = &atmel_uart,
1e6c9c28
AV
1021};
1022
7192f92c 1023#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 1024
afefc415
AV
1025/*
1026 * Early console initialization (before VM subsystem initialized).
1027 */
7192f92c 1028static int __init atmel_console_init(void)
1e6c9c28 1029{
73e2798b 1030 if (atmel_default_console_device) {
b843aa21
RB
1031 add_preferred_console(ATMEL_DEVICENAME,
1032 atmel_default_console_device->id, NULL);
1033 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1034 atmel_default_console_device);
7192f92c 1035 register_console(&atmel_console);
afefc415 1036 }
1e6c9c28 1037
1e6c9c28
AV
1038 return 0;
1039}
b843aa21 1040
7192f92c 1041console_initcall(atmel_console_init);
1e6c9c28 1042
afefc415
AV
1043/*
1044 * Late console initialization.
1045 */
7192f92c 1046static int __init atmel_late_console_init(void)
afefc415 1047{
b843aa21
RB
1048 if (atmel_default_console_device
1049 && !(atmel_console.flags & CON_ENABLED))
7192f92c 1050 register_console(&atmel_console);
afefc415
AV
1051
1052 return 0;
1053}
b843aa21 1054
7192f92c 1055core_initcall(atmel_late_console_init);
afefc415 1056
dfa7f343
HS
1057static inline bool atmel_is_console_port(struct uart_port *port)
1058{
1059 return port->cons && port->cons->index == port->line;
1060}
1061
1e6c9c28 1062#else
7192f92c 1063#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS
1064
1065static inline bool atmel_is_console_port(struct uart_port *port)
1066{
1067 return false;
1068}
1e6c9c28
AV
1069#endif
1070
7192f92c 1071static struct uart_driver atmel_uart = {
b843aa21
RB
1072 .owner = THIS_MODULE,
1073 .driver_name = "atmel_serial",
1074 .dev_name = ATMEL_DEVICENAME,
1075 .major = SERIAL_ATMEL_MAJOR,
1076 .minor = MINOR_START,
1077 .nr = ATMEL_MAX_UART,
1078 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
1079};
1080
afefc415 1081#ifdef CONFIG_PM
b843aa21
RB
1082static int atmel_serial_suspend(struct platform_device *pdev,
1083 pm_message_t state)
1e6c9c28 1084{
afefc415 1085 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1086 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415 1087
b843aa21
RB
1088 if (device_may_wakeup(&pdev->dev)
1089 && !at91_suspend_entering_slow_clock())
afefc415
AV
1090 enable_irq_wake(port->irq);
1091 else {
7192f92c
HS
1092 uart_suspend_port(&atmel_uart, port);
1093 atmel_port->suspended = 1;
afefc415 1094 }
1e6c9c28 1095
afefc415
AV
1096 return 0;
1097}
1e6c9c28 1098
7192f92c 1099static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
1100{
1101 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1102 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
1e6c9c28 1103
7192f92c
HS
1104 if (atmel_port->suspended) {
1105 uart_resume_port(&atmel_uart, port);
1106 atmel_port->suspended = 0;
b843aa21 1107 } else
9b938166 1108 disable_irq_wake(port->irq);
1e6c9c28
AV
1109
1110 return 0;
1111}
afefc415 1112#else
7192f92c
HS
1113#define atmel_serial_suspend NULL
1114#define atmel_serial_resume NULL
afefc415 1115#endif
1e6c9c28 1116
7192f92c 1117static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 1118{
7192f92c 1119 struct atmel_uart_port *port;
1ecc26bd 1120 void *data;
afefc415 1121 int ret;
1e6c9c28 1122
1ecc26bd
RB
1123 BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
1124
7192f92c
HS
1125 port = &atmel_ports[pdev->id];
1126 atmel_init_port(port, pdev);
1e6c9c28 1127
1ecc26bd
RB
1128 ret = -ENOMEM;
1129 data = kmalloc(ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
1130 if (!data)
1131 goto err_alloc_ring;
1132 port->rx_ring.buf = data;
1133
7192f92c 1134 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS
1135 if (ret)
1136 goto err_add_port;
1137
1138 device_init_wakeup(&pdev->dev, 1);
1139 platform_set_drvdata(pdev, port);
1140
1141 return 0;
1142
1143err_add_port:
1ecc26bd
RB
1144 kfree(port->rx_ring.buf);
1145 port->rx_ring.buf = NULL;
1146err_alloc_ring:
dfa7f343
HS
1147 if (!atmel_is_console_port(&port->uart)) {
1148 clk_disable(port->clk);
1149 clk_put(port->clk);
1150 port->clk = NULL;
afefc415
AV
1151 }
1152
1153 return ret;
1154}
1155
7192f92c 1156static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
1157{
1158 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1159 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415
AV
1160 int ret = 0;
1161
afefc415
AV
1162 device_init_wakeup(&pdev->dev, 0);
1163 platform_set_drvdata(pdev, NULL);
1164
dfa7f343
HS
1165 ret = uart_remove_one_port(&atmel_uart, port);
1166
1ecc26bd
RB
1167 tasklet_kill(&atmel_port->tasklet);
1168 kfree(atmel_port->rx_ring.buf);
1169
dfa7f343
HS
1170 /* "port" is allocated statically, so we shouldn't free it */
1171
1172 clk_disable(atmel_port->clk);
1173 clk_put(atmel_port->clk);
afefc415
AV
1174
1175 return ret;
1176}
1177
7192f92c
HS
1178static struct platform_driver atmel_serial_driver = {
1179 .probe = atmel_serial_probe,
1180 .remove = __devexit_p(atmel_serial_remove),
1181 .suspend = atmel_serial_suspend,
1182 .resume = atmel_serial_resume,
afefc415 1183 .driver = {
1e8ea802 1184 .name = "atmel_usart",
afefc415
AV
1185 .owner = THIS_MODULE,
1186 },
1187};
1188
7192f92c 1189static int __init atmel_serial_init(void)
afefc415
AV
1190{
1191 int ret;
1192
7192f92c 1193 ret = uart_register_driver(&atmel_uart);
afefc415
AV
1194 if (ret)
1195 return ret;
1196
7192f92c 1197 ret = platform_driver_register(&atmel_serial_driver);
afefc415 1198 if (ret)
7192f92c 1199 uart_unregister_driver(&atmel_uart);
afefc415
AV
1200
1201 return ret;
1202}
1203
7192f92c 1204static void __exit atmel_serial_exit(void)
afefc415 1205{
7192f92c
HS
1206 platform_driver_unregister(&atmel_serial_driver);
1207 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
1208}
1209
7192f92c
HS
1210module_init(atmel_serial_init);
1211module_exit(atmel_serial_exit);
1e6c9c28
AV
1212
1213MODULE_AUTHOR("Rick Bronson");
7192f92c 1214MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 1215MODULE_LICENSE("GPL");