Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250_pci.c | |
3 | * | |
4 | * Probe module for 8250/16550-type PCI serial ports. | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | * | |
14 | * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $ | |
15 | */ | |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/serial_core.h> | |
26 | #include <linux/8250_pci.h> | |
27 | #include <linux/bitops.h> | |
28 | ||
29 | #include <asm/byteorder.h> | |
30 | #include <asm/io.h> | |
31 | ||
32 | #include "8250.h" | |
33 | ||
34 | #undef SERIAL_DEBUG_PCI | |
35 | ||
36 | /* | |
37 | * Definitions for PCI support. | |
38 | */ | |
39 | #define FL_BASE_MASK 0x0007 | |
40 | #define FL_BASE0 0x0000 | |
41 | #define FL_BASE1 0x0001 | |
42 | #define FL_BASE2 0x0002 | |
43 | #define FL_BASE3 0x0003 | |
44 | #define FL_BASE4 0x0004 | |
45 | #define FL_GET_BASE(x) (x & FL_BASE_MASK) | |
46 | ||
47 | /* Use successive BARs (PCI base address registers), | |
48 | else use offset into some specified BAR */ | |
49 | #define FL_BASE_BARS 0x0008 | |
50 | ||
51 | /* do not assign an irq */ | |
52 | #define FL_NOIRQ 0x0080 | |
53 | ||
54 | /* Use the Base address register size to cap number of ports */ | |
55 | #define FL_REGION_SZ_CAP 0x0100 | |
56 | ||
1c7c1fe5 | 57 | struct pciserial_board { |
1da177e4 LT |
58 | unsigned int flags; |
59 | unsigned int num_ports; | |
60 | unsigned int base_baud; | |
61 | unsigned int uart_offset; | |
62 | unsigned int reg_shift; | |
63 | unsigned int first_offset; | |
64 | }; | |
65 | ||
70db3d91 RK |
66 | struct serial_private; |
67 | ||
1da177e4 LT |
68 | /* |
69 | * init function returns: | |
70 | * > 0 - number of ports | |
71 | * = 0 - use board->num_ports | |
72 | * < 0 - error | |
73 | */ | |
74 | struct pci_serial_quirk { | |
75 | u32 vendor; | |
76 | u32 device; | |
77 | u32 subvendor; | |
78 | u32 subdevice; | |
79 | int (*init)(struct pci_dev *dev); | |
70db3d91 | 80 | int (*setup)(struct serial_private *, struct pciserial_board *, |
1da177e4 LT |
81 | struct uart_port *port, int idx); |
82 | void (*exit)(struct pci_dev *dev); | |
83 | }; | |
84 | ||
85 | #define PCI_NUM_BAR_RESOURCES 6 | |
86 | ||
87 | struct serial_private { | |
70db3d91 | 88 | struct pci_dev *dev; |
1da177e4 LT |
89 | unsigned int nr; |
90 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; | |
91 | struct pci_serial_quirk *quirk; | |
92 | int line[0]; | |
93 | }; | |
94 | ||
95 | static void moan_device(const char *str, struct pci_dev *dev) | |
96 | { | |
97 | printk(KERN_WARNING "%s: %s\n" | |
98 | KERN_WARNING "Please send the output of lspci -vv, this\n" | |
99 | KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" | |
100 | KERN_WARNING "manufacturer and name of serial board or\n" | |
101 | KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n", | |
102 | pci_name(dev), str, dev->vendor, dev->device, | |
103 | dev->subsystem_vendor, dev->subsystem_device); | |
104 | } | |
105 | ||
106 | static int | |
70db3d91 | 107 | setup_port(struct serial_private *priv, struct uart_port *port, |
1da177e4 LT |
108 | int bar, int offset, int regshift) |
109 | { | |
70db3d91 | 110 | struct pci_dev *dev = priv->dev; |
1da177e4 LT |
111 | unsigned long base, len; |
112 | ||
113 | if (bar >= PCI_NUM_BAR_RESOURCES) | |
114 | return -EINVAL; | |
115 | ||
72ce9a83 RK |
116 | base = pci_resource_start(dev, bar); |
117 | ||
1da177e4 | 118 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { |
1da177e4 LT |
119 | len = pci_resource_len(dev, bar); |
120 | ||
121 | if (!priv->remapped_bar[bar]) | |
122 | priv->remapped_bar[bar] = ioremap(base, len); | |
123 | if (!priv->remapped_bar[bar]) | |
124 | return -ENOMEM; | |
125 | ||
126 | port->iotype = UPIO_MEM; | |
72ce9a83 | 127 | port->iobase = 0; |
1da177e4 LT |
128 | port->mapbase = base + offset; |
129 | port->membase = priv->remapped_bar[bar] + offset; | |
130 | port->regshift = regshift; | |
131 | } else { | |
1da177e4 | 132 | port->iotype = UPIO_PORT; |
72ce9a83 RK |
133 | port->iobase = base + offset; |
134 | port->mapbase = 0; | |
135 | port->membase = NULL; | |
136 | port->regshift = 0; | |
1da177e4 LT |
137 | } |
138 | return 0; | |
139 | } | |
140 | ||
141 | /* | |
142 | * AFAVLAB uses a different mixture of BARs and offsets | |
143 | * Not that ugly ;) -- HW | |
144 | */ | |
145 | static int | |
70db3d91 | 146 | afavlab_setup(struct serial_private *priv, struct pciserial_board *board, |
1da177e4 LT |
147 | struct uart_port *port, int idx) |
148 | { | |
149 | unsigned int bar, offset = board->first_offset; | |
150 | ||
151 | bar = FL_GET_BASE(board->flags); | |
152 | if (idx < 4) | |
153 | bar += idx; | |
154 | else { | |
155 | bar = 4; | |
156 | offset += (idx - 4) * board->uart_offset; | |
157 | } | |
158 | ||
70db3d91 | 159 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
160 | } |
161 | ||
162 | /* | |
163 | * HP's Remote Management Console. The Diva chip came in several | |
164 | * different versions. N-class, L2000 and A500 have two Diva chips, each | |
165 | * with 3 UARTs (the third UART on the second chip is unused). Superdome | |
166 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have | |
167 | * one Diva chip, but it has been expanded to 5 UARTs. | |
168 | */ | |
169 | static int __devinit pci_hp_diva_init(struct pci_dev *dev) | |
170 | { | |
171 | int rc = 0; | |
172 | ||
173 | switch (dev->subsystem_device) { | |
174 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: | |
175 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: | |
176 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: | |
177 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
178 | rc = 3; | |
179 | break; | |
180 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: | |
181 | rc = 2; | |
182 | break; | |
183 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | |
184 | rc = 4; | |
185 | break; | |
186 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: | |
187 | rc = 1; | |
188 | break; | |
189 | } | |
190 | ||
191 | return rc; | |
192 | } | |
193 | ||
194 | /* | |
195 | * HP's Diva chip puts the 4th/5th serial port further out, and | |
196 | * some serial ports are supposed to be hidden on certain models. | |
197 | */ | |
198 | static int | |
70db3d91 | 199 | pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board, |
1da177e4 LT |
200 | struct uart_port *port, int idx) |
201 | { | |
202 | unsigned int offset = board->first_offset; | |
203 | unsigned int bar = FL_GET_BASE(board->flags); | |
204 | ||
70db3d91 | 205 | switch (priv->dev->subsystem_device) { |
1da177e4 LT |
206 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
207 | if (idx == 3) | |
208 | idx++; | |
209 | break; | |
210 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
211 | if (idx > 0) | |
212 | idx++; | |
213 | if (idx > 2) | |
214 | idx++; | |
215 | break; | |
216 | } | |
217 | if (idx > 2) | |
218 | offset = 0x18; | |
219 | ||
220 | offset += idx * board->uart_offset; | |
221 | ||
70db3d91 | 222 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
223 | } |
224 | ||
225 | /* | |
226 | * Added for EKF Intel i960 serial boards | |
227 | */ | |
228 | static int __devinit pci_inteli960ni_init(struct pci_dev *dev) | |
229 | { | |
230 | unsigned long oldval; | |
231 | ||
232 | if (!(dev->subsystem_device & 0x1000)) | |
233 | return -ENODEV; | |
234 | ||
235 | /* is firmware started? */ | |
236 | pci_read_config_dword(dev, 0x44, (void*) &oldval); | |
237 | if (oldval == 0x00001000L) { /* RESET value */ | |
238 | printk(KERN_DEBUG "Local i960 firmware missing"); | |
239 | return -ENODEV; | |
240 | } | |
241 | return 0; | |
242 | } | |
243 | ||
244 | /* | |
245 | * Some PCI serial cards using the PLX 9050 PCI interface chip require | |
246 | * that the card interrupt be explicitly enabled or disabled. This | |
247 | * seems to be mainly needed on card using the PLX which also use I/O | |
248 | * mapped memory. | |
249 | */ | |
250 | static int __devinit pci_plx9050_init(struct pci_dev *dev) | |
251 | { | |
252 | u8 irq_config; | |
253 | void __iomem *p; | |
254 | ||
255 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { | |
256 | moan_device("no memory in bar 0", dev); | |
257 | return 0; | |
258 | } | |
259 | ||
260 | irq_config = 0x41; | |
261 | if (dev->vendor == PCI_VENDOR_ID_PANACOM) | |
262 | irq_config = 0x43; | |
263 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && | |
264 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) { | |
265 | /* | |
266 | * As the megawolf cards have the int pins active | |
267 | * high, and have 2 UART chips, both ints must be | |
268 | * enabled on the 9050. Also, the UARTS are set in | |
269 | * 16450 mode by default, so we have to enable the | |
270 | * 16C950 'enhanced' mode so that we can use the | |
271 | * deep FIFOs | |
272 | */ | |
273 | irq_config = 0x5b; | |
274 | } | |
275 | ||
276 | /* | |
277 | * enable/disable interrupts | |
278 | */ | |
279 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
280 | if (p == NULL) | |
281 | return -ENOMEM; | |
282 | writel(irq_config, p + 0x4c); | |
283 | ||
284 | /* | |
285 | * Read the register back to ensure that it took effect. | |
286 | */ | |
287 | readl(p + 0x4c); | |
288 | iounmap(p); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static void __devexit pci_plx9050_exit(struct pci_dev *dev) | |
294 | { | |
295 | u8 __iomem *p; | |
296 | ||
297 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) | |
298 | return; | |
299 | ||
300 | /* | |
301 | * disable interrupts | |
302 | */ | |
303 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
304 | if (p != NULL) { | |
305 | writel(0, p + 0x4c); | |
306 | ||
307 | /* | |
308 | * Read the register back to ensure that it took effect. | |
309 | */ | |
310 | readl(p + 0x4c); | |
311 | iounmap(p); | |
312 | } | |
313 | } | |
314 | ||
315 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ | |
316 | static int | |
70db3d91 | 317 | sbs_setup(struct serial_private *priv, struct pciserial_board *board, |
1da177e4 LT |
318 | struct uart_port *port, int idx) |
319 | { | |
320 | unsigned int bar, offset = board->first_offset; | |
321 | ||
322 | bar = 0; | |
323 | ||
324 | if (idx < 4) { | |
325 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ | |
326 | offset += idx * board->uart_offset; | |
327 | } else if (idx < 8) { | |
328 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ | |
329 | offset += idx * board->uart_offset + 0xC00; | |
330 | } else /* we have only 8 ports on PMC-OCTALPRO */ | |
331 | return 1; | |
332 | ||
70db3d91 | 333 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
334 | } |
335 | ||
336 | /* | |
337 | * This does initialization for PMC OCTALPRO cards: | |
338 | * maps the device memory, resets the UARTs (needed, bc | |
339 | * if the module is removed and inserted again, the card | |
340 | * is in the sleep mode) and enables global interrupt. | |
341 | */ | |
342 | ||
343 | /* global control register offset for SBS PMC-OctalPro */ | |
344 | #define OCT_REG_CR_OFF 0x500 | |
345 | ||
346 | static int __devinit sbs_init(struct pci_dev *dev) | |
347 | { | |
348 | u8 __iomem *p; | |
349 | ||
350 | p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0)); | |
351 | ||
352 | if (p == NULL) | |
353 | return -ENOMEM; | |
354 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ | |
355 | writeb(0x10,p + OCT_REG_CR_OFF); | |
356 | udelay(50); | |
357 | writeb(0x0,p + OCT_REG_CR_OFF); | |
358 | ||
359 | /* Set bit-2 (INTENABLE) of Control Register */ | |
360 | writeb(0x4, p + OCT_REG_CR_OFF); | |
361 | iounmap(p); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | /* | |
367 | * Disables the global interrupt of PMC-OctalPro | |
368 | */ | |
369 | ||
370 | static void __devexit sbs_exit(struct pci_dev *dev) | |
371 | { | |
372 | u8 __iomem *p; | |
373 | ||
374 | p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0)); | |
375 | if (p != NULL) { | |
376 | writeb(0, p + OCT_REG_CR_OFF); | |
377 | } | |
378 | iounmap(p); | |
379 | } | |
380 | ||
381 | /* | |
382 | * SIIG serial cards have an PCI interface chip which also controls | |
383 | * the UART clocking frequency. Each UART can be clocked independently | |
384 | * (except cards equiped with 4 UARTs) and initial clocking settings | |
385 | * are stored in the EEPROM chip. It can cause problems because this | |
386 | * version of serial driver doesn't support differently clocked UART's | |
387 | * on single PCI card. To prevent this, initialization functions set | |
388 | * high frequency clocking for all UART's on given card. It is safe (I | |
389 | * hope) because it doesn't touch EEPROM settings to prevent conflicts | |
390 | * with other OSes (like M$ DOS). | |
391 | * | |
392 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 | |
393 | * | |
394 | * There is two family of SIIG serial cards with different PCI | |
395 | * interface chip and different configuration methods: | |
396 | * - 10x cards have control registers in IO and/or memory space; | |
397 | * - 20x cards have control registers in standard PCI configuration space. | |
398 | * | |
67d74b87 RK |
399 | * Note: all 10x cards have PCI device ids 0x10.. |
400 | * all 20x cards have PCI device ids 0x20.. | |
401 | * | |
fbc0dc0d AP |
402 | * There are also Quartet Serial cards which use Oxford Semiconductor |
403 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. | |
404 | * | |
1da177e4 LT |
405 | * Note: some SIIG cards are probed by the parport_serial object. |
406 | */ | |
407 | ||
408 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) | |
409 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) | |
410 | ||
411 | static int pci_siig10x_init(struct pci_dev *dev) | |
412 | { | |
413 | u16 data; | |
414 | void __iomem *p; | |
415 | ||
416 | switch (dev->device & 0xfff8) { | |
417 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ | |
418 | data = 0xffdf; | |
419 | break; | |
420 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ | |
421 | data = 0xf7ff; | |
422 | break; | |
423 | default: /* 1S1P, 4S */ | |
424 | data = 0xfffb; | |
425 | break; | |
426 | } | |
427 | ||
428 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
429 | if (p == NULL) | |
430 | return -ENOMEM; | |
431 | ||
432 | writew(readw(p + 0x28) & data, p + 0x28); | |
433 | readw(p + 0x28); | |
434 | iounmap(p); | |
435 | return 0; | |
436 | } | |
437 | ||
438 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) | |
439 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) | |
440 | ||
441 | static int pci_siig20x_init(struct pci_dev *dev) | |
442 | { | |
443 | u8 data; | |
444 | ||
445 | /* Change clock frequency for the first UART. */ | |
446 | pci_read_config_byte(dev, 0x6f, &data); | |
447 | pci_write_config_byte(dev, 0x6f, data & 0xef); | |
448 | ||
449 | /* If this card has 2 UART, we have to do the same with second UART. */ | |
450 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || | |
451 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { | |
452 | pci_read_config_byte(dev, 0x73, &data); | |
453 | pci_write_config_byte(dev, 0x73, data & 0xef); | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
67d74b87 RK |
458 | static int pci_siig_init(struct pci_dev *dev) |
459 | { | |
460 | unsigned int type = dev->device & 0xff00; | |
461 | ||
462 | if (type == 0x1000) | |
463 | return pci_siig10x_init(dev); | |
464 | else if (type == 0x2000) | |
465 | return pci_siig20x_init(dev); | |
466 | ||
467 | moan_device("Unknown SIIG card", dev); | |
468 | return -ENODEV; | |
469 | } | |
470 | ||
1da177e4 LT |
471 | int pci_siig10x_fn(struct pci_dev *dev, int enable) |
472 | { | |
473 | int ret = 0; | |
474 | if (enable) | |
475 | ret = pci_siig10x_init(dev); | |
476 | return ret; | |
477 | } | |
478 | ||
479 | int pci_siig20x_fn(struct pci_dev *dev, int enable) | |
480 | { | |
481 | int ret = 0; | |
482 | if (enable) | |
483 | ret = pci_siig20x_init(dev); | |
484 | return ret; | |
485 | } | |
486 | ||
487 | EXPORT_SYMBOL(pci_siig10x_fn); | |
488 | EXPORT_SYMBOL(pci_siig20x_fn); | |
489 | ||
490 | /* | |
491 | * Timedia has an explosion of boards, and to avoid the PCI table from | |
492 | * growing *huge*, we use this function to collapse some 70 entries | |
493 | * in the PCI table into one, for sanity's and compactness's sake. | |
494 | */ | |
495 | static unsigned short timedia_single_port[] = { | |
496 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 | |
497 | }; | |
498 | ||
499 | static unsigned short timedia_dual_port[] = { | |
500 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, | |
501 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, | |
502 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, | |
503 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, | |
504 | 0xD079, 0 | |
505 | }; | |
506 | ||
507 | static unsigned short timedia_quad_port[] = { | |
508 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, | |
509 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, | |
510 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, | |
511 | 0xB157, 0 | |
512 | }; | |
513 | ||
514 | static unsigned short timedia_eight_port[] = { | |
515 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, | |
516 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 | |
517 | }; | |
518 | ||
519 | static struct timedia_struct { | |
520 | int num; | |
521 | unsigned short *ids; | |
522 | } timedia_data[] = { | |
523 | { 1, timedia_single_port }, | |
524 | { 2, timedia_dual_port }, | |
525 | { 4, timedia_quad_port }, | |
526 | { 8, timedia_eight_port }, | |
527 | { 0, NULL } | |
528 | }; | |
529 | ||
530 | static int __devinit pci_timedia_init(struct pci_dev *dev) | |
531 | { | |
532 | unsigned short *ids; | |
533 | int i, j; | |
534 | ||
535 | for (i = 0; timedia_data[i].num; i++) { | |
536 | ids = timedia_data[i].ids; | |
537 | for (j = 0; ids[j]; j++) | |
538 | if (dev->subsystem_device == ids[j]) | |
539 | return timedia_data[i].num; | |
540 | } | |
541 | return 0; | |
542 | } | |
543 | ||
544 | /* | |
545 | * Timedia/SUNIX uses a mixture of BARs and offsets | |
546 | * Ugh, this is ugly as all hell --- TYT | |
547 | */ | |
548 | static int | |
70db3d91 | 549 | pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board, |
1da177e4 LT |
550 | struct uart_port *port, int idx) |
551 | { | |
552 | unsigned int bar = 0, offset = board->first_offset; | |
553 | ||
554 | switch (idx) { | |
555 | case 0: | |
556 | bar = 0; | |
557 | break; | |
558 | case 1: | |
559 | offset = board->uart_offset; | |
560 | bar = 0; | |
561 | break; | |
562 | case 2: | |
563 | bar = 1; | |
564 | break; | |
565 | case 3: | |
566 | offset = board->uart_offset; | |
567 | bar = 1; | |
568 | case 4: /* BAR 2 */ | |
569 | case 5: /* BAR 3 */ | |
570 | case 6: /* BAR 4 */ | |
571 | case 7: /* BAR 5 */ | |
572 | bar = idx - 2; | |
573 | } | |
574 | ||
70db3d91 | 575 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
576 | } |
577 | ||
578 | /* | |
579 | * Some Titan cards are also a little weird | |
580 | */ | |
581 | static int | |
70db3d91 | 582 | titan_400l_800l_setup(struct serial_private *priv, |
1c7c1fe5 | 583 | struct pciserial_board *board, |
1da177e4 LT |
584 | struct uart_port *port, int idx) |
585 | { | |
586 | unsigned int bar, offset = board->first_offset; | |
587 | ||
588 | switch (idx) { | |
589 | case 0: | |
590 | bar = 1; | |
591 | break; | |
592 | case 1: | |
593 | bar = 2; | |
594 | break; | |
595 | default: | |
596 | bar = 4; | |
597 | offset = (idx - 2) * board->uart_offset; | |
598 | } | |
599 | ||
70db3d91 | 600 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
601 | } |
602 | ||
603 | static int __devinit pci_xircom_init(struct pci_dev *dev) | |
604 | { | |
605 | msleep(100); | |
606 | return 0; | |
607 | } | |
608 | ||
609 | static int __devinit pci_netmos_init(struct pci_dev *dev) | |
610 | { | |
611 | /* subdevice 0x00PS means <P> parallel, <S> serial */ | |
612 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
613 | ||
614 | if (num_serial == 0) | |
615 | return -ENODEV; | |
616 | return num_serial; | |
617 | } | |
618 | ||
619 | static int | |
70db3d91 | 620 | pci_default_setup(struct serial_private *priv, struct pciserial_board *board, |
1da177e4 LT |
621 | struct uart_port *port, int idx) |
622 | { | |
623 | unsigned int bar, offset = board->first_offset, maxnr; | |
624 | ||
625 | bar = FL_GET_BASE(board->flags); | |
626 | if (board->flags & FL_BASE_BARS) | |
627 | bar += idx; | |
628 | else | |
629 | offset += idx * board->uart_offset; | |
630 | ||
70db3d91 | 631 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) / |
1da177e4 LT |
632 | (8 << board->reg_shift); |
633 | ||
634 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | |
635 | return 1; | |
636 | ||
70db3d91 | 637 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
638 | } |
639 | ||
640 | /* This should be in linux/pci_ids.h */ | |
641 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B | |
642 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B | |
643 | #define PCI_DEVICE_ID_OCTPRO 0x0001 | |
644 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 | |
645 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 | |
646 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 | |
647 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 | |
648 | ||
649 | /* | |
650 | * Master list of serial port init/setup/exit quirks. | |
651 | * This does not describe the general nature of the port. | |
652 | * (ie, baud base, number and location of ports, etc) | |
653 | * | |
654 | * This list is ordered alphabetically by vendor then device. | |
655 | * Specific entries must come before more generic entries. | |
656 | */ | |
657 | static struct pci_serial_quirk pci_serial_quirks[] = { | |
658 | /* | |
659 | * AFAVLAB cards. | |
660 | * It is not clear whether this applies to all products. | |
661 | */ | |
662 | { | |
663 | .vendor = PCI_VENDOR_ID_AFAVLAB, | |
664 | .device = PCI_ANY_ID, | |
665 | .subvendor = PCI_ANY_ID, | |
666 | .subdevice = PCI_ANY_ID, | |
667 | .setup = afavlab_setup, | |
668 | }, | |
669 | /* | |
670 | * HP Diva | |
671 | */ | |
672 | { | |
673 | .vendor = PCI_VENDOR_ID_HP, | |
674 | .device = PCI_DEVICE_ID_HP_DIVA, | |
675 | .subvendor = PCI_ANY_ID, | |
676 | .subdevice = PCI_ANY_ID, | |
677 | .init = pci_hp_diva_init, | |
678 | .setup = pci_hp_diva_setup, | |
679 | }, | |
680 | /* | |
681 | * Intel | |
682 | */ | |
683 | { | |
684 | .vendor = PCI_VENDOR_ID_INTEL, | |
685 | .device = PCI_DEVICE_ID_INTEL_80960_RP, | |
686 | .subvendor = 0xe4bf, | |
687 | .subdevice = PCI_ANY_ID, | |
688 | .init = pci_inteli960ni_init, | |
689 | .setup = pci_default_setup, | |
690 | }, | |
691 | /* | |
692 | * Panacom | |
693 | */ | |
694 | { | |
695 | .vendor = PCI_VENDOR_ID_PANACOM, | |
696 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
697 | .subvendor = PCI_ANY_ID, | |
698 | .subdevice = PCI_ANY_ID, | |
699 | .init = pci_plx9050_init, | |
700 | .setup = pci_default_setup, | |
701 | .exit = __devexit_p(pci_plx9050_exit), | |
702 | }, | |
703 | { | |
704 | .vendor = PCI_VENDOR_ID_PANACOM, | |
705 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
706 | .subvendor = PCI_ANY_ID, | |
707 | .subdevice = PCI_ANY_ID, | |
708 | .init = pci_plx9050_init, | |
709 | .setup = pci_default_setup, | |
710 | .exit = __devexit_p(pci_plx9050_exit), | |
711 | }, | |
712 | /* | |
713 | * PLX | |
714 | */ | |
715 | { | |
716 | .vendor = PCI_VENDOR_ID_PLX, | |
717 | .device = PCI_DEVICE_ID_PLX_9050, | |
718 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, | |
719 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, | |
720 | .init = pci_plx9050_init, | |
721 | .setup = pci_default_setup, | |
722 | .exit = __devexit_p(pci_plx9050_exit), | |
723 | }, | |
724 | { | |
725 | .vendor = PCI_VENDOR_ID_PLX, | |
726 | .device = PCI_DEVICE_ID_PLX_ROMULUS, | |
727 | .subvendor = PCI_VENDOR_ID_PLX, | |
728 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, | |
729 | .init = pci_plx9050_init, | |
730 | .setup = pci_default_setup, | |
731 | .exit = __devexit_p(pci_plx9050_exit), | |
732 | }, | |
733 | /* | |
734 | * SBS Technologies, Inc., PMC-OCTALPRO 232 | |
735 | */ | |
736 | { | |
737 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
738 | .device = PCI_DEVICE_ID_OCTPRO, | |
739 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
740 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, | |
741 | .init = sbs_init, | |
742 | .setup = sbs_setup, | |
743 | .exit = __devexit_p(sbs_exit), | |
744 | }, | |
745 | /* | |
746 | * SBS Technologies, Inc., PMC-OCTALPRO 422 | |
747 | */ | |
748 | { | |
749 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
750 | .device = PCI_DEVICE_ID_OCTPRO, | |
751 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
752 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, | |
753 | .init = sbs_init, | |
754 | .setup = sbs_setup, | |
755 | .exit = __devexit_p(sbs_exit), | |
756 | }, | |
757 | /* | |
758 | * SBS Technologies, Inc., P-Octal 232 | |
759 | */ | |
760 | { | |
761 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
762 | .device = PCI_DEVICE_ID_OCTPRO, | |
763 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
764 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, | |
765 | .init = sbs_init, | |
766 | .setup = sbs_setup, | |
767 | .exit = __devexit_p(sbs_exit), | |
768 | }, | |
769 | /* | |
770 | * SBS Technologies, Inc., P-Octal 422 | |
771 | */ | |
772 | { | |
773 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
774 | .device = PCI_DEVICE_ID_OCTPRO, | |
775 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
776 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, | |
777 | .init = sbs_init, | |
778 | .setup = sbs_setup, | |
779 | .exit = __devexit_p(sbs_exit), | |
780 | }, | |
1da177e4 LT |
781 | /* |
782 | * SIIG cards. | |
1da177e4 LT |
783 | */ |
784 | { | |
785 | .vendor = PCI_VENDOR_ID_SIIG, | |
67d74b87 | 786 | .device = PCI_ANY_ID, |
1da177e4 LT |
787 | .subvendor = PCI_ANY_ID, |
788 | .subdevice = PCI_ANY_ID, | |
67d74b87 | 789 | .init = pci_siig_init, |
1da177e4 LT |
790 | .setup = pci_default_setup, |
791 | }, | |
792 | /* | |
793 | * Titan cards | |
794 | */ | |
795 | { | |
796 | .vendor = PCI_VENDOR_ID_TITAN, | |
797 | .device = PCI_DEVICE_ID_TITAN_400L, | |
798 | .subvendor = PCI_ANY_ID, | |
799 | .subdevice = PCI_ANY_ID, | |
800 | .setup = titan_400l_800l_setup, | |
801 | }, | |
802 | { | |
803 | .vendor = PCI_VENDOR_ID_TITAN, | |
804 | .device = PCI_DEVICE_ID_TITAN_800L, | |
805 | .subvendor = PCI_ANY_ID, | |
806 | .subdevice = PCI_ANY_ID, | |
807 | .setup = titan_400l_800l_setup, | |
808 | }, | |
809 | /* | |
810 | * Timedia cards | |
811 | */ | |
812 | { | |
813 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
814 | .device = PCI_DEVICE_ID_TIMEDIA_1889, | |
815 | .subvendor = PCI_VENDOR_ID_TIMEDIA, | |
816 | .subdevice = PCI_ANY_ID, | |
817 | .init = pci_timedia_init, | |
818 | .setup = pci_timedia_setup, | |
819 | }, | |
820 | { | |
821 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
822 | .device = PCI_ANY_ID, | |
823 | .subvendor = PCI_ANY_ID, | |
824 | .subdevice = PCI_ANY_ID, | |
825 | .setup = pci_timedia_setup, | |
826 | }, | |
827 | /* | |
828 | * Xircom cards | |
829 | */ | |
830 | { | |
831 | .vendor = PCI_VENDOR_ID_XIRCOM, | |
832 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
833 | .subvendor = PCI_ANY_ID, | |
834 | .subdevice = PCI_ANY_ID, | |
835 | .init = pci_xircom_init, | |
836 | .setup = pci_default_setup, | |
837 | }, | |
838 | /* | |
839 | * Netmos cards | |
840 | */ | |
841 | { | |
842 | .vendor = PCI_VENDOR_ID_NETMOS, | |
843 | .device = PCI_ANY_ID, | |
844 | .subvendor = PCI_ANY_ID, | |
845 | .subdevice = PCI_ANY_ID, | |
846 | .init = pci_netmos_init, | |
847 | .setup = pci_default_setup, | |
848 | }, | |
849 | /* | |
850 | * Default "match everything" terminator entry | |
851 | */ | |
852 | { | |
853 | .vendor = PCI_ANY_ID, | |
854 | .device = PCI_ANY_ID, | |
855 | .subvendor = PCI_ANY_ID, | |
856 | .subdevice = PCI_ANY_ID, | |
857 | .setup = pci_default_setup, | |
858 | } | |
859 | }; | |
860 | ||
861 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) | |
862 | { | |
863 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; | |
864 | } | |
865 | ||
866 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) | |
867 | { | |
868 | struct pci_serial_quirk *quirk; | |
869 | ||
870 | for (quirk = pci_serial_quirks; ; quirk++) | |
871 | if (quirk_id_matches(quirk->vendor, dev->vendor) && | |
872 | quirk_id_matches(quirk->device, dev->device) && | |
873 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && | |
874 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) | |
875 | break; | |
876 | return quirk; | |
877 | } | |
878 | ||
879 | static _INLINE_ int | |
72ce9a83 | 880 | get_pci_irq(struct pci_dev *dev, struct pciserial_board *board) |
1da177e4 LT |
881 | { |
882 | if (board->flags & FL_NOIRQ) | |
883 | return 0; | |
884 | else | |
885 | return dev->irq; | |
886 | } | |
887 | ||
888 | /* | |
889 | * This is the configuration table for all of the PCI serial boards | |
890 | * which we support. It is directly indexed by the pci_board_num_t enum | |
891 | * value, which is encoded in the pci_device_id PCI probe table's | |
892 | * driver_data member. | |
893 | * | |
894 | * The makeup of these names are: | |
895 | * pbn_bn{_bt}_n_baud | |
896 | * | |
897 | * bn = PCI BAR number | |
898 | * bt = Index using PCI BARs | |
899 | * n = number of serial ports | |
900 | * baud = baud rate | |
901 | * | |
f1690f37 RK |
902 | * This table is sorted by (in order): baud, bt, bn, n. |
903 | * | |
1da177e4 LT |
904 | * Please note: in theory if n = 1, _bt infix should make no difference. |
905 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 | |
906 | */ | |
907 | enum pci_board_num_t { | |
908 | pbn_default = 0, | |
909 | ||
910 | pbn_b0_1_115200, | |
911 | pbn_b0_2_115200, | |
912 | pbn_b0_4_115200, | |
913 | pbn_b0_5_115200, | |
914 | ||
915 | pbn_b0_1_921600, | |
916 | pbn_b0_2_921600, | |
917 | pbn_b0_4_921600, | |
918 | ||
fbc0dc0d AP |
919 | pbn_b0_4_1152000, |
920 | ||
1da177e4 LT |
921 | pbn_b0_bt_1_115200, |
922 | pbn_b0_bt_2_115200, | |
923 | pbn_b0_bt_8_115200, | |
924 | ||
925 | pbn_b0_bt_1_460800, | |
926 | pbn_b0_bt_2_460800, | |
927 | pbn_b0_bt_4_460800, | |
928 | ||
929 | pbn_b0_bt_1_921600, | |
930 | pbn_b0_bt_2_921600, | |
931 | pbn_b0_bt_4_921600, | |
932 | pbn_b0_bt_8_921600, | |
933 | ||
934 | pbn_b1_1_115200, | |
935 | pbn_b1_2_115200, | |
936 | pbn_b1_4_115200, | |
937 | pbn_b1_8_115200, | |
938 | ||
939 | pbn_b1_1_921600, | |
940 | pbn_b1_2_921600, | |
941 | pbn_b1_4_921600, | |
942 | pbn_b1_8_921600, | |
943 | ||
944 | pbn_b1_bt_2_921600, | |
945 | ||
946 | pbn_b1_1_1382400, | |
947 | pbn_b1_2_1382400, | |
948 | pbn_b1_4_1382400, | |
949 | pbn_b1_8_1382400, | |
950 | ||
951 | pbn_b2_1_115200, | |
952 | pbn_b2_8_115200, | |
953 | ||
954 | pbn_b2_1_460800, | |
955 | pbn_b2_4_460800, | |
956 | pbn_b2_8_460800, | |
957 | pbn_b2_16_460800, | |
958 | ||
959 | pbn_b2_1_921600, | |
960 | pbn_b2_4_921600, | |
961 | pbn_b2_8_921600, | |
962 | ||
963 | pbn_b2_bt_1_115200, | |
964 | pbn_b2_bt_2_115200, | |
965 | pbn_b2_bt_4_115200, | |
966 | ||
967 | pbn_b2_bt_2_921600, | |
968 | pbn_b2_bt_4_921600, | |
969 | ||
970 | pbn_b3_4_115200, | |
971 | pbn_b3_8_115200, | |
972 | ||
973 | /* | |
974 | * Board-specific versions. | |
975 | */ | |
976 | pbn_panacom, | |
977 | pbn_panacom2, | |
978 | pbn_panacom4, | |
979 | pbn_plx_romulus, | |
980 | pbn_oxsemi, | |
981 | pbn_intel_i960, | |
982 | pbn_sgi_ioc3, | |
983 | pbn_nec_nile4, | |
984 | pbn_computone_4, | |
985 | pbn_computone_6, | |
986 | pbn_computone_8, | |
987 | pbn_sbsxrsio, | |
988 | pbn_exar_XR17C152, | |
989 | pbn_exar_XR17C154, | |
990 | pbn_exar_XR17C158, | |
991 | }; | |
992 | ||
993 | /* | |
994 | * uart_offset - the space between channels | |
995 | * reg_shift - describes how the UART registers are mapped | |
996 | * to PCI memory by the card. | |
997 | * For example IER register on SBS, Inc. PMC-OctPro is located at | |
998 | * offset 0x10 from the UART base, while UART_IER is defined as 1 | |
999 | * in include/linux/serial_reg.h, | |
1000 | * see first lines of serial_in() and serial_out() in 8250.c | |
1001 | */ | |
1002 | ||
1c7c1fe5 | 1003 | static struct pciserial_board pci_boards[] __devinitdata = { |
1da177e4 LT |
1004 | [pbn_default] = { |
1005 | .flags = FL_BASE0, | |
1006 | .num_ports = 1, | |
1007 | .base_baud = 115200, | |
1008 | .uart_offset = 8, | |
1009 | }, | |
1010 | [pbn_b0_1_115200] = { | |
1011 | .flags = FL_BASE0, | |
1012 | .num_ports = 1, | |
1013 | .base_baud = 115200, | |
1014 | .uart_offset = 8, | |
1015 | }, | |
1016 | [pbn_b0_2_115200] = { | |
1017 | .flags = FL_BASE0, | |
1018 | .num_ports = 2, | |
1019 | .base_baud = 115200, | |
1020 | .uart_offset = 8, | |
1021 | }, | |
1022 | [pbn_b0_4_115200] = { | |
1023 | .flags = FL_BASE0, | |
1024 | .num_ports = 4, | |
1025 | .base_baud = 115200, | |
1026 | .uart_offset = 8, | |
1027 | }, | |
1028 | [pbn_b0_5_115200] = { | |
1029 | .flags = FL_BASE0, | |
1030 | .num_ports = 5, | |
1031 | .base_baud = 115200, | |
1032 | .uart_offset = 8, | |
1033 | }, | |
1034 | ||
1035 | [pbn_b0_1_921600] = { | |
1036 | .flags = FL_BASE0, | |
1037 | .num_ports = 1, | |
1038 | .base_baud = 921600, | |
1039 | .uart_offset = 8, | |
1040 | }, | |
1041 | [pbn_b0_2_921600] = { | |
1042 | .flags = FL_BASE0, | |
1043 | .num_ports = 2, | |
1044 | .base_baud = 921600, | |
1045 | .uart_offset = 8, | |
1046 | }, | |
1047 | [pbn_b0_4_921600] = { | |
1048 | .flags = FL_BASE0, | |
1049 | .num_ports = 4, | |
1050 | .base_baud = 921600, | |
1051 | .uart_offset = 8, | |
1052 | }, | |
fbc0dc0d AP |
1053 | [pbn_b0_4_1152000] = { |
1054 | .flags = FL_BASE0, | |
1055 | .num_ports = 4, | |
1056 | .base_baud = 1152000, | |
1057 | .uart_offset = 8, | |
1058 | }, | |
1da177e4 LT |
1059 | |
1060 | [pbn_b0_bt_1_115200] = { | |
1061 | .flags = FL_BASE0|FL_BASE_BARS, | |
1062 | .num_ports = 1, | |
1063 | .base_baud = 115200, | |
1064 | .uart_offset = 8, | |
1065 | }, | |
1066 | [pbn_b0_bt_2_115200] = { | |
1067 | .flags = FL_BASE0|FL_BASE_BARS, | |
1068 | .num_ports = 2, | |
1069 | .base_baud = 115200, | |
1070 | .uart_offset = 8, | |
1071 | }, | |
1072 | [pbn_b0_bt_8_115200] = { | |
1073 | .flags = FL_BASE0|FL_BASE_BARS, | |
1074 | .num_ports = 8, | |
1075 | .base_baud = 115200, | |
1076 | .uart_offset = 8, | |
1077 | }, | |
1078 | ||
1079 | [pbn_b0_bt_1_460800] = { | |
1080 | .flags = FL_BASE0|FL_BASE_BARS, | |
1081 | .num_ports = 1, | |
1082 | .base_baud = 460800, | |
1083 | .uart_offset = 8, | |
1084 | }, | |
1085 | [pbn_b0_bt_2_460800] = { | |
1086 | .flags = FL_BASE0|FL_BASE_BARS, | |
1087 | .num_ports = 2, | |
1088 | .base_baud = 460800, | |
1089 | .uart_offset = 8, | |
1090 | }, | |
1091 | [pbn_b0_bt_4_460800] = { | |
1092 | .flags = FL_BASE0|FL_BASE_BARS, | |
1093 | .num_ports = 4, | |
1094 | .base_baud = 460800, | |
1095 | .uart_offset = 8, | |
1096 | }, | |
1097 | ||
1098 | [pbn_b0_bt_1_921600] = { | |
1099 | .flags = FL_BASE0|FL_BASE_BARS, | |
1100 | .num_ports = 1, | |
1101 | .base_baud = 921600, | |
1102 | .uart_offset = 8, | |
1103 | }, | |
1104 | [pbn_b0_bt_2_921600] = { | |
1105 | .flags = FL_BASE0|FL_BASE_BARS, | |
1106 | .num_ports = 2, | |
1107 | .base_baud = 921600, | |
1108 | .uart_offset = 8, | |
1109 | }, | |
1110 | [pbn_b0_bt_4_921600] = { | |
1111 | .flags = FL_BASE0|FL_BASE_BARS, | |
1112 | .num_ports = 4, | |
1113 | .base_baud = 921600, | |
1114 | .uart_offset = 8, | |
1115 | }, | |
1116 | [pbn_b0_bt_8_921600] = { | |
1117 | .flags = FL_BASE0|FL_BASE_BARS, | |
1118 | .num_ports = 8, | |
1119 | .base_baud = 921600, | |
1120 | .uart_offset = 8, | |
1121 | }, | |
1122 | ||
1123 | [pbn_b1_1_115200] = { | |
1124 | .flags = FL_BASE1, | |
1125 | .num_ports = 1, | |
1126 | .base_baud = 115200, | |
1127 | .uart_offset = 8, | |
1128 | }, | |
1129 | [pbn_b1_2_115200] = { | |
1130 | .flags = FL_BASE1, | |
1131 | .num_ports = 2, | |
1132 | .base_baud = 115200, | |
1133 | .uart_offset = 8, | |
1134 | }, | |
1135 | [pbn_b1_4_115200] = { | |
1136 | .flags = FL_BASE1, | |
1137 | .num_ports = 4, | |
1138 | .base_baud = 115200, | |
1139 | .uart_offset = 8, | |
1140 | }, | |
1141 | [pbn_b1_8_115200] = { | |
1142 | .flags = FL_BASE1, | |
1143 | .num_ports = 8, | |
1144 | .base_baud = 115200, | |
1145 | .uart_offset = 8, | |
1146 | }, | |
1147 | ||
1148 | [pbn_b1_1_921600] = { | |
1149 | .flags = FL_BASE1, | |
1150 | .num_ports = 1, | |
1151 | .base_baud = 921600, | |
1152 | .uart_offset = 8, | |
1153 | }, | |
1154 | [pbn_b1_2_921600] = { | |
1155 | .flags = FL_BASE1, | |
1156 | .num_ports = 2, | |
1157 | .base_baud = 921600, | |
1158 | .uart_offset = 8, | |
1159 | }, | |
1160 | [pbn_b1_4_921600] = { | |
1161 | .flags = FL_BASE1, | |
1162 | .num_ports = 4, | |
1163 | .base_baud = 921600, | |
1164 | .uart_offset = 8, | |
1165 | }, | |
1166 | [pbn_b1_8_921600] = { | |
1167 | .flags = FL_BASE1, | |
1168 | .num_ports = 8, | |
1169 | .base_baud = 921600, | |
1170 | .uart_offset = 8, | |
1171 | }, | |
1172 | ||
1173 | [pbn_b1_bt_2_921600] = { | |
1174 | .flags = FL_BASE1|FL_BASE_BARS, | |
1175 | .num_ports = 2, | |
1176 | .base_baud = 921600, | |
1177 | .uart_offset = 8, | |
1178 | }, | |
1179 | ||
1180 | [pbn_b1_1_1382400] = { | |
1181 | .flags = FL_BASE1, | |
1182 | .num_ports = 1, | |
1183 | .base_baud = 1382400, | |
1184 | .uart_offset = 8, | |
1185 | }, | |
1186 | [pbn_b1_2_1382400] = { | |
1187 | .flags = FL_BASE1, | |
1188 | .num_ports = 2, | |
1189 | .base_baud = 1382400, | |
1190 | .uart_offset = 8, | |
1191 | }, | |
1192 | [pbn_b1_4_1382400] = { | |
1193 | .flags = FL_BASE1, | |
1194 | .num_ports = 4, | |
1195 | .base_baud = 1382400, | |
1196 | .uart_offset = 8, | |
1197 | }, | |
1198 | [pbn_b1_8_1382400] = { | |
1199 | .flags = FL_BASE1, | |
1200 | .num_ports = 8, | |
1201 | .base_baud = 1382400, | |
1202 | .uart_offset = 8, | |
1203 | }, | |
1204 | ||
1205 | [pbn_b2_1_115200] = { | |
1206 | .flags = FL_BASE2, | |
1207 | .num_ports = 1, | |
1208 | .base_baud = 115200, | |
1209 | .uart_offset = 8, | |
1210 | }, | |
1211 | [pbn_b2_8_115200] = { | |
1212 | .flags = FL_BASE2, | |
1213 | .num_ports = 8, | |
1214 | .base_baud = 115200, | |
1215 | .uart_offset = 8, | |
1216 | }, | |
1217 | ||
1218 | [pbn_b2_1_460800] = { | |
1219 | .flags = FL_BASE2, | |
1220 | .num_ports = 1, | |
1221 | .base_baud = 460800, | |
1222 | .uart_offset = 8, | |
1223 | }, | |
1224 | [pbn_b2_4_460800] = { | |
1225 | .flags = FL_BASE2, | |
1226 | .num_ports = 4, | |
1227 | .base_baud = 460800, | |
1228 | .uart_offset = 8, | |
1229 | }, | |
1230 | [pbn_b2_8_460800] = { | |
1231 | .flags = FL_BASE2, | |
1232 | .num_ports = 8, | |
1233 | .base_baud = 460800, | |
1234 | .uart_offset = 8, | |
1235 | }, | |
1236 | [pbn_b2_16_460800] = { | |
1237 | .flags = FL_BASE2, | |
1238 | .num_ports = 16, | |
1239 | .base_baud = 460800, | |
1240 | .uart_offset = 8, | |
1241 | }, | |
1242 | ||
1243 | [pbn_b2_1_921600] = { | |
1244 | .flags = FL_BASE2, | |
1245 | .num_ports = 1, | |
1246 | .base_baud = 921600, | |
1247 | .uart_offset = 8, | |
1248 | }, | |
1249 | [pbn_b2_4_921600] = { | |
1250 | .flags = FL_BASE2, | |
1251 | .num_ports = 4, | |
1252 | .base_baud = 921600, | |
1253 | .uart_offset = 8, | |
1254 | }, | |
1255 | [pbn_b2_8_921600] = { | |
1256 | .flags = FL_BASE2, | |
1257 | .num_ports = 8, | |
1258 | .base_baud = 921600, | |
1259 | .uart_offset = 8, | |
1260 | }, | |
1261 | ||
1262 | [pbn_b2_bt_1_115200] = { | |
1263 | .flags = FL_BASE2|FL_BASE_BARS, | |
1264 | .num_ports = 1, | |
1265 | .base_baud = 115200, | |
1266 | .uart_offset = 8, | |
1267 | }, | |
1268 | [pbn_b2_bt_2_115200] = { | |
1269 | .flags = FL_BASE2|FL_BASE_BARS, | |
1270 | .num_ports = 2, | |
1271 | .base_baud = 115200, | |
1272 | .uart_offset = 8, | |
1273 | }, | |
1274 | [pbn_b2_bt_4_115200] = { | |
1275 | .flags = FL_BASE2|FL_BASE_BARS, | |
1276 | .num_ports = 4, | |
1277 | .base_baud = 115200, | |
1278 | .uart_offset = 8, | |
1279 | }, | |
1280 | ||
1281 | [pbn_b2_bt_2_921600] = { | |
1282 | .flags = FL_BASE2|FL_BASE_BARS, | |
1283 | .num_ports = 2, | |
1284 | .base_baud = 921600, | |
1285 | .uart_offset = 8, | |
1286 | }, | |
1287 | [pbn_b2_bt_4_921600] = { | |
1288 | .flags = FL_BASE2|FL_BASE_BARS, | |
1289 | .num_ports = 4, | |
1290 | .base_baud = 921600, | |
1291 | .uart_offset = 8, | |
1292 | }, | |
1293 | ||
1294 | [pbn_b3_4_115200] = { | |
1295 | .flags = FL_BASE3, | |
1296 | .num_ports = 4, | |
1297 | .base_baud = 115200, | |
1298 | .uart_offset = 8, | |
1299 | }, | |
1300 | [pbn_b3_8_115200] = { | |
1301 | .flags = FL_BASE3, | |
1302 | .num_ports = 8, | |
1303 | .base_baud = 115200, | |
1304 | .uart_offset = 8, | |
1305 | }, | |
1306 | ||
1307 | /* | |
1308 | * Entries following this are board-specific. | |
1309 | */ | |
1310 | ||
1311 | /* | |
1312 | * Panacom - IOMEM | |
1313 | */ | |
1314 | [pbn_panacom] = { | |
1315 | .flags = FL_BASE2, | |
1316 | .num_ports = 2, | |
1317 | .base_baud = 921600, | |
1318 | .uart_offset = 0x400, | |
1319 | .reg_shift = 7, | |
1320 | }, | |
1321 | [pbn_panacom2] = { | |
1322 | .flags = FL_BASE2|FL_BASE_BARS, | |
1323 | .num_ports = 2, | |
1324 | .base_baud = 921600, | |
1325 | .uart_offset = 0x400, | |
1326 | .reg_shift = 7, | |
1327 | }, | |
1328 | [pbn_panacom4] = { | |
1329 | .flags = FL_BASE2|FL_BASE_BARS, | |
1330 | .num_ports = 4, | |
1331 | .base_baud = 921600, | |
1332 | .uart_offset = 0x400, | |
1333 | .reg_shift = 7, | |
1334 | }, | |
1335 | ||
1336 | /* I think this entry is broken - the first_offset looks wrong --rmk */ | |
1337 | [pbn_plx_romulus] = { | |
1338 | .flags = FL_BASE2, | |
1339 | .num_ports = 4, | |
1340 | .base_baud = 921600, | |
1341 | .uart_offset = 8 << 2, | |
1342 | .reg_shift = 2, | |
1343 | .first_offset = 0x03, | |
1344 | }, | |
1345 | ||
1346 | /* | |
1347 | * This board uses the size of PCI Base region 0 to | |
1348 | * signal now many ports are available | |
1349 | */ | |
1350 | [pbn_oxsemi] = { | |
1351 | .flags = FL_BASE0|FL_REGION_SZ_CAP, | |
1352 | .num_ports = 32, | |
1353 | .base_baud = 115200, | |
1354 | .uart_offset = 8, | |
1355 | }, | |
1356 | ||
1357 | /* | |
1358 | * EKF addition for i960 Boards form EKF with serial port. | |
1359 | * Max 256 ports. | |
1360 | */ | |
1361 | [pbn_intel_i960] = { | |
1362 | .flags = FL_BASE0, | |
1363 | .num_ports = 32, | |
1364 | .base_baud = 921600, | |
1365 | .uart_offset = 8 << 2, | |
1366 | .reg_shift = 2, | |
1367 | .first_offset = 0x10000, | |
1368 | }, | |
1369 | [pbn_sgi_ioc3] = { | |
1370 | .flags = FL_BASE0|FL_NOIRQ, | |
1371 | .num_ports = 1, | |
1372 | .base_baud = 458333, | |
1373 | .uart_offset = 8, | |
1374 | .reg_shift = 0, | |
1375 | .first_offset = 0x20178, | |
1376 | }, | |
1377 | ||
1378 | /* | |
1379 | * NEC Vrc-5074 (Nile 4) builtin UART. | |
1380 | */ | |
1381 | [pbn_nec_nile4] = { | |
1382 | .flags = FL_BASE0, | |
1383 | .num_ports = 1, | |
1384 | .base_baud = 520833, | |
1385 | .uart_offset = 8 << 3, | |
1386 | .reg_shift = 3, | |
1387 | .first_offset = 0x300, | |
1388 | }, | |
1389 | ||
1390 | /* | |
1391 | * Computone - uses IOMEM. | |
1392 | */ | |
1393 | [pbn_computone_4] = { | |
1394 | .flags = FL_BASE0, | |
1395 | .num_ports = 4, | |
1396 | .base_baud = 921600, | |
1397 | .uart_offset = 0x40, | |
1398 | .reg_shift = 2, | |
1399 | .first_offset = 0x200, | |
1400 | }, | |
1401 | [pbn_computone_6] = { | |
1402 | .flags = FL_BASE0, | |
1403 | .num_ports = 6, | |
1404 | .base_baud = 921600, | |
1405 | .uart_offset = 0x40, | |
1406 | .reg_shift = 2, | |
1407 | .first_offset = 0x200, | |
1408 | }, | |
1409 | [pbn_computone_8] = { | |
1410 | .flags = FL_BASE0, | |
1411 | .num_ports = 8, | |
1412 | .base_baud = 921600, | |
1413 | .uart_offset = 0x40, | |
1414 | .reg_shift = 2, | |
1415 | .first_offset = 0x200, | |
1416 | }, | |
1417 | [pbn_sbsxrsio] = { | |
1418 | .flags = FL_BASE0, | |
1419 | .num_ports = 8, | |
1420 | .base_baud = 460800, | |
1421 | .uart_offset = 256, | |
1422 | .reg_shift = 4, | |
1423 | }, | |
1424 | /* | |
1425 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | |
1426 | * Only basic 16550A support. | |
1427 | * XR17C15[24] are not tested, but they should work. | |
1428 | */ | |
1429 | [pbn_exar_XR17C152] = { | |
1430 | .flags = FL_BASE0, | |
1431 | .num_ports = 2, | |
1432 | .base_baud = 921600, | |
1433 | .uart_offset = 0x200, | |
1434 | }, | |
1435 | [pbn_exar_XR17C154] = { | |
1436 | .flags = FL_BASE0, | |
1437 | .num_ports = 4, | |
1438 | .base_baud = 921600, | |
1439 | .uart_offset = 0x200, | |
1440 | }, | |
1441 | [pbn_exar_XR17C158] = { | |
1442 | .flags = FL_BASE0, | |
1443 | .num_ports = 8, | |
1444 | .base_baud = 921600, | |
1445 | .uart_offset = 0x200, | |
1446 | }, | |
1447 | }; | |
1448 | ||
1449 | /* | |
1450 | * Given a complete unknown PCI device, try to use some heuristics to | |
1451 | * guess what the configuration might be, based on the pitiful PCI | |
1452 | * serial specs. Returns 0 on success, 1 on failure. | |
1453 | */ | |
1454 | static int __devinit | |
1c7c1fe5 | 1455 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) |
1da177e4 LT |
1456 | { |
1457 | int num_iomem, num_port, first_port = -1, i; | |
1458 | ||
1459 | /* | |
1460 | * If it is not a communications device or the programming | |
1461 | * interface is greater than 6, give up. | |
1462 | * | |
1463 | * (Should we try to make guesses for multiport serial devices | |
1464 | * later?) | |
1465 | */ | |
1466 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && | |
1467 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || | |
1468 | (dev->class & 0xff) > 6) | |
1469 | return -ENODEV; | |
1470 | ||
1471 | num_iomem = num_port = 0; | |
1472 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
1473 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { | |
1474 | num_port++; | |
1475 | if (first_port == -1) | |
1476 | first_port = i; | |
1477 | } | |
1478 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) | |
1479 | num_iomem++; | |
1480 | } | |
1481 | ||
1482 | /* | |
1483 | * If there is 1 or 0 iomem regions, and exactly one port, | |
1484 | * use it. We guess the number of ports based on the IO | |
1485 | * region size. | |
1486 | */ | |
1487 | if (num_iomem <= 1 && num_port == 1) { | |
1488 | board->flags = first_port; | |
1489 | board->num_ports = pci_resource_len(dev, first_port) / 8; | |
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | /* | |
1494 | * Now guess if we've got a board which indexes by BARs. | |
1495 | * Each IO BAR should be 8 bytes, and they should follow | |
1496 | * consecutively. | |
1497 | */ | |
1498 | first_port = -1; | |
1499 | num_port = 0; | |
1500 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
1501 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && | |
1502 | pci_resource_len(dev, i) == 8 && | |
1503 | (first_port == -1 || (first_port + num_port) == i)) { | |
1504 | num_port++; | |
1505 | if (first_port == -1) | |
1506 | first_port = i; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | if (num_port > 1) { | |
1511 | board->flags = first_port | FL_BASE_BARS; | |
1512 | board->num_ports = num_port; | |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | return -ENODEV; | |
1517 | } | |
1518 | ||
1519 | static inline int | |
1c7c1fe5 RK |
1520 | serial_pci_matches(struct pciserial_board *board, |
1521 | struct pciserial_board *guessed) | |
1da177e4 LT |
1522 | { |
1523 | return | |
1524 | board->num_ports == guessed->num_ports && | |
1525 | board->base_baud == guessed->base_baud && | |
1526 | board->uart_offset == guessed->uart_offset && | |
1527 | board->reg_shift == guessed->reg_shift && | |
1528 | board->first_offset == guessed->first_offset; | |
1529 | } | |
1530 | ||
1531 | /* | |
1532 | * Probe one serial board. Unfortunately, there is no rhyme nor reason | |
1533 | * to the arrangement of serial ports on a PCI card. | |
1534 | */ | |
1535 | static int __devinit | |
1536 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) | |
1537 | { | |
72ce9a83 | 1538 | struct uart_port serial_port; |
1da177e4 | 1539 | struct serial_private *priv; |
1c7c1fe5 | 1540 | struct pciserial_board *board, tmp; |
1da177e4 LT |
1541 | struct pci_serial_quirk *quirk; |
1542 | int rc, nr_ports, i; | |
1543 | ||
1544 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { | |
1545 | printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n", | |
1546 | ent->driver_data); | |
1547 | return -EINVAL; | |
1548 | } | |
1549 | ||
1550 | board = &pci_boards[ent->driver_data]; | |
1551 | ||
1552 | rc = pci_enable_device(dev); | |
1553 | if (rc) | |
1554 | return rc; | |
1555 | ||
1556 | if (ent->driver_data == pbn_default) { | |
1557 | /* | |
1558 | * Use a copy of the pci_board entry for this; | |
1559 | * avoid changing entries in the table. | |
1560 | */ | |
1c7c1fe5 | 1561 | memcpy(&tmp, board, sizeof(struct pciserial_board)); |
1da177e4 LT |
1562 | board = &tmp; |
1563 | ||
1564 | /* | |
1565 | * We matched one of our class entries. Try to | |
1566 | * determine the parameters of this board. | |
1567 | */ | |
1568 | rc = serial_pci_guess_board(dev, board); | |
1569 | if (rc) | |
1570 | goto disable; | |
1571 | } else { | |
1572 | /* | |
1573 | * We matched an explicit entry. If we are able to | |
1574 | * detect this boards settings with our heuristic, | |
1575 | * then we no longer need this entry. | |
1576 | */ | |
1c7c1fe5 RK |
1577 | memcpy(&tmp, &pci_boards[pbn_default], |
1578 | sizeof(struct pciserial_board)); | |
1da177e4 LT |
1579 | rc = serial_pci_guess_board(dev, &tmp); |
1580 | if (rc == 0 && serial_pci_matches(board, &tmp)) | |
1581 | moan_device("Redundant entry in serial pci_table.", | |
1582 | dev); | |
1583 | } | |
1584 | ||
1585 | nr_ports = board->num_ports; | |
1586 | ||
1587 | /* | |
1588 | * Find an init and setup quirks. | |
1589 | */ | |
1590 | quirk = find_quirk(dev); | |
1591 | ||
1592 | /* | |
1593 | * Run the new-style initialization function. | |
1594 | * The initialization function returns: | |
1595 | * <0 - error | |
1596 | * 0 - use board->num_ports | |
1597 | * >0 - number of ports | |
1598 | */ | |
1599 | if (quirk->init) { | |
1600 | rc = quirk->init(dev); | |
1601 | if (rc < 0) | |
1602 | goto disable; | |
1603 | if (rc) | |
1604 | nr_ports = rc; | |
1605 | } | |
1606 | ||
1607 | priv = kmalloc(sizeof(struct serial_private) + | |
1608 | sizeof(unsigned int) * nr_ports, | |
1609 | GFP_KERNEL); | |
1610 | if (!priv) { | |
1611 | rc = -ENOMEM; | |
1612 | goto deinit; | |
1613 | } | |
1614 | ||
1615 | memset(priv, 0, sizeof(struct serial_private) + | |
1616 | sizeof(unsigned int) * nr_ports); | |
1617 | ||
70db3d91 | 1618 | priv->dev = dev; |
1da177e4 LT |
1619 | priv->quirk = quirk; |
1620 | pci_set_drvdata(dev, priv); | |
1621 | ||
72ce9a83 RK |
1622 | memset(&serial_port, 0, sizeof(struct uart_port)); |
1623 | serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | |
1624 | serial_port.uartclk = board->base_baud * 16; | |
1625 | serial_port.irq = get_pci_irq(dev, board); | |
1626 | serial_port.dev = &dev->dev; | |
1627 | ||
1da177e4 | 1628 | for (i = 0; i < nr_ports; i++) { |
70db3d91 | 1629 | if (quirk->setup(priv, board, &serial_port, i)) |
1da177e4 | 1630 | break; |
72ce9a83 | 1631 | |
1da177e4 LT |
1632 | #ifdef SERIAL_DEBUG_PCI |
1633 | printk("Setup PCI port: port %x, irq %d, type %d\n", | |
1634 | serial_port.iobase, serial_port.irq, serial_port.iotype); | |
1635 | #endif | |
1636 | ||
1637 | priv->line[i] = serial8250_register_port(&serial_port); | |
1638 | if (priv->line[i] < 0) { | |
1639 | printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); | |
1640 | break; | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | priv->nr = i; | |
1645 | ||
1646 | return 0; | |
1647 | ||
1648 | deinit: | |
1649 | if (quirk->exit) | |
1650 | quirk->exit(dev); | |
1651 | disable: | |
1652 | pci_disable_device(dev); | |
1653 | return rc; | |
1654 | } | |
1655 | ||
1656 | static void __devexit pciserial_remove_one(struct pci_dev *dev) | |
1657 | { | |
1658 | struct serial_private *priv = pci_get_drvdata(dev); | |
056a8763 RK |
1659 | struct pci_serial_quirk *quirk; |
1660 | int i; | |
1da177e4 LT |
1661 | |
1662 | pci_set_drvdata(dev, NULL); | |
1663 | ||
056a8763 RK |
1664 | for (i = 0; i < priv->nr; i++) |
1665 | serial8250_unregister_port(priv->line[i]); | |
1da177e4 | 1666 | |
056a8763 RK |
1667 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
1668 | if (priv->remapped_bar[i]) | |
1669 | iounmap(priv->remapped_bar[i]); | |
1670 | priv->remapped_bar[i] = NULL; | |
1671 | } | |
1da177e4 | 1672 | |
056a8763 RK |
1673 | /* |
1674 | * Find the exit quirks. | |
1675 | */ | |
1676 | quirk = find_quirk(dev); | |
1677 | if (quirk->exit) | |
1678 | quirk->exit(dev); | |
1da177e4 | 1679 | |
056a8763 | 1680 | pci_disable_device(dev); |
1da177e4 | 1681 | |
056a8763 | 1682 | kfree(priv); |
1da177e4 LT |
1683 | } |
1684 | ||
1685 | static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) | |
1686 | { | |
1687 | struct serial_private *priv = pci_get_drvdata(dev); | |
1688 | ||
1689 | if (priv) { | |
1690 | int i; | |
1691 | ||
1692 | for (i = 0; i < priv->nr; i++) | |
1693 | serial8250_suspend_port(priv->line[i]); | |
1694 | } | |
1695 | pci_save_state(dev); | |
1696 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static int pciserial_resume_one(struct pci_dev *dev) | |
1701 | { | |
1702 | struct serial_private *priv = pci_get_drvdata(dev); | |
1703 | ||
1704 | pci_set_power_state(dev, PCI_D0); | |
1705 | pci_restore_state(dev); | |
1706 | ||
1707 | if (priv) { | |
1708 | int i; | |
1709 | ||
1710 | /* | |
1711 | * The device may have been disabled. Re-enable it. | |
1712 | */ | |
1713 | pci_enable_device(dev); | |
1714 | ||
1715 | /* | |
1716 | * Ensure that the board is correctly configured. | |
1717 | */ | |
1718 | if (priv->quirk->init) | |
1719 | priv->quirk->init(dev); | |
1720 | ||
1721 | for (i = 0; i < priv->nr; i++) | |
1722 | serial8250_resume_port(priv->line[i]); | |
1723 | } | |
1724 | return 0; | |
1725 | } | |
1726 | ||
1727 | static struct pci_device_id serial_pci_tbl[] = { | |
1728 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1729 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1730 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
1731 | pbn_b1_8_1382400 }, | |
1732 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1733 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1734 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
1735 | pbn_b1_4_1382400 }, | |
1736 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1737 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1738 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
1739 | pbn_b1_2_1382400 }, | |
1740 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1741 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1742 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
1743 | pbn_b1_8_1382400 }, | |
1744 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1745 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1746 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
1747 | pbn_b1_4_1382400 }, | |
1748 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1749 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1750 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
1751 | pbn_b1_2_1382400 }, | |
1752 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1753 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1754 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, | |
1755 | pbn_b1_8_921600 }, | |
1756 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1757 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1758 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, | |
1759 | pbn_b1_8_921600 }, | |
1760 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1761 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1762 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, | |
1763 | pbn_b1_4_921600 }, | |
1764 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1765 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1766 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, | |
1767 | pbn_b1_4_921600 }, | |
1768 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1769 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1770 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, | |
1771 | pbn_b1_2_921600 }, | |
1772 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1773 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1774 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, | |
1775 | pbn_b1_8_921600 }, | |
1776 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1777 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1778 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, | |
1779 | pbn_b1_8_921600 }, | |
1780 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1781 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1782 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, | |
1783 | pbn_b1_4_921600 }, | |
1784 | ||
1785 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, | |
1786 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1787 | pbn_b2_bt_1_115200 }, | |
1788 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, | |
1789 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1790 | pbn_b2_bt_2_115200 }, | |
1791 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, | |
1792 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1793 | pbn_b2_bt_4_115200 }, | |
1794 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, | |
1795 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1796 | pbn_b2_bt_2_115200 }, | |
1797 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, | |
1798 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1799 | pbn_b2_bt_4_115200 }, | |
1800 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, | |
1801 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1802 | pbn_b2_8_115200 }, | |
1803 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, | |
1804 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1805 | pbn_b2_8_115200 }, | |
1806 | ||
1807 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, | |
1808 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1809 | pbn_b2_bt_2_115200 }, | |
1810 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, | |
1811 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1812 | pbn_b2_bt_2_921600 }, | |
1813 | /* | |
1814 | * VScom SPCOM800, from sl@s.pl | |
1815 | */ | |
1816 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, | |
1817 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1818 | pbn_b2_8_921600 }, | |
1819 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, | |
1820 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1821 | pbn_b2_4_921600 }, | |
1822 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1823 | PCI_SUBVENDOR_ID_KEYSPAN, | |
1824 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, | |
1825 | pbn_panacom }, | |
1826 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
1827 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1828 | pbn_panacom4 }, | |
1829 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
1830 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1831 | pbn_panacom2 }, | |
1832 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1833 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1834 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, | |
1835 | pbn_b2_4_460800 }, | |
1836 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1837 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1838 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, | |
1839 | pbn_b2_8_460800 }, | |
1840 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1841 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1842 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, | |
1843 | pbn_b2_16_460800 }, | |
1844 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1845 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1846 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, | |
1847 | pbn_b2_16_460800 }, | |
1848 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1849 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
1850 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, | |
1851 | pbn_b2_4_460800 }, | |
1852 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1853 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
1854 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, | |
1855 | pbn_b2_8_460800 }, | |
1856 | /* | |
1857 | * Megawolf Romulus PCI Serial Card, from Mike Hudson | |
1858 | * (Exoray@isys.ca) | |
1859 | */ | |
1860 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, | |
1861 | 0x10b5, 0x106a, 0, 0, | |
1862 | pbn_plx_romulus }, | |
1863 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, | |
1864 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1865 | pbn_b1_4_115200 }, | |
1866 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, | |
1867 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1868 | pbn_b1_2_115200 }, | |
1869 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, | |
1870 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1871 | pbn_b1_8_115200 }, | |
1872 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, | |
1873 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1874 | pbn_b1_8_115200 }, | |
1875 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, | |
1876 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0, | |
1877 | pbn_b0_4_921600 }, | |
fbc0dc0d AP |
1878 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
1879 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0, | |
1880 | pbn_b0_4_1152000 }, | |
1da177e4 LT |
1881 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
1882 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1883 | pbn_b0_4_115200 }, | |
1884 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, | |
1885 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1886 | pbn_b0_bt_2_921600 }, | |
1887 | ||
1888 | /* | |
1889 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, | |
1890 | * from skokodyn@yahoo.com | |
1891 | */ | |
1892 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1893 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, | |
1894 | pbn_sbsxrsio }, | |
1895 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1896 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, | |
1897 | pbn_sbsxrsio }, | |
1898 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1899 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, | |
1900 | pbn_sbsxrsio }, | |
1901 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1902 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, | |
1903 | pbn_sbsxrsio }, | |
1904 | ||
1905 | /* | |
1906 | * Digitan DS560-558, from jimd@esoft.com | |
1907 | */ | |
1908 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, | |
1909 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1910 | pbn_b1_1_115200 }, | |
1911 | ||
1912 | /* | |
1913 | * Titan Electronic cards | |
1914 | * The 400L and 800L have a custom setup quirk. | |
1915 | */ | |
1916 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, | |
1917 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1918 | pbn_b0_1_921600 }, | |
1919 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, | |
1920 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1921 | pbn_b0_2_921600 }, | |
1922 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, | |
1923 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1924 | pbn_b0_4_921600 }, | |
1925 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, | |
1926 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1927 | pbn_b0_4_921600 }, | |
1928 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, | |
1929 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1930 | pbn_b1_1_921600 }, | |
1931 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, | |
1932 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1933 | pbn_b1_bt_2_921600 }, | |
1934 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, | |
1935 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1936 | pbn_b0_bt_4_921600 }, | |
1937 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, | |
1938 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1939 | pbn_b0_bt_8_921600 }, | |
1940 | ||
1941 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, | |
1942 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1943 | pbn_b2_1_460800 }, | |
1944 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, | |
1945 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1946 | pbn_b2_1_460800 }, | |
1947 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, | |
1948 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1949 | pbn_b2_1_460800 }, | |
1950 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, | |
1951 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1952 | pbn_b2_bt_2_921600 }, | |
1953 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, | |
1954 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1955 | pbn_b2_bt_2_921600 }, | |
1956 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, | |
1957 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1958 | pbn_b2_bt_2_921600 }, | |
1959 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, | |
1960 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1961 | pbn_b2_bt_4_921600 }, | |
1962 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, | |
1963 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1964 | pbn_b2_bt_4_921600 }, | |
1965 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, | |
1966 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1967 | pbn_b2_bt_4_921600 }, | |
1968 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, | |
1969 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1970 | pbn_b0_1_921600 }, | |
1971 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, | |
1972 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1973 | pbn_b0_1_921600 }, | |
1974 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, | |
1975 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1976 | pbn_b0_1_921600 }, | |
1977 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, | |
1978 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1979 | pbn_b0_bt_2_921600 }, | |
1980 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, | |
1981 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1982 | pbn_b0_bt_2_921600 }, | |
1983 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, | |
1984 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1985 | pbn_b0_bt_2_921600 }, | |
1986 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, | |
1987 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1988 | pbn_b0_bt_4_921600 }, | |
1989 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, | |
1990 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1991 | pbn_b0_bt_4_921600 }, | |
1992 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, | |
1993 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1994 | pbn_b0_bt_4_921600 }, | |
1995 | ||
1996 | /* | |
1997 | * Computone devices submitted by Doug McNash dmcnash@computone.com | |
1998 | */ | |
1999 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2000 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, | |
2001 | 0, 0, pbn_computone_4 }, | |
2002 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2003 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, | |
2004 | 0, 0, pbn_computone_8 }, | |
2005 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2006 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, | |
2007 | 0, 0, pbn_computone_6 }, | |
2008 | ||
2009 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, | |
2010 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2011 | pbn_oxsemi }, | |
2012 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, | |
2013 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, | |
2014 | pbn_b0_bt_1_921600 }, | |
2015 | ||
2016 | /* | |
2017 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> | |
2018 | */ | |
2019 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, | |
2020 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2021 | pbn_b0_bt_8_115200 }, | |
2022 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, | |
2023 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2024 | pbn_b0_bt_8_115200 }, | |
2025 | ||
2026 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, | |
2027 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2028 | pbn_b0_bt_2_115200 }, | |
2029 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, | |
2030 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2031 | pbn_b0_bt_2_115200 }, | |
2032 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, | |
2033 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2034 | pbn_b0_bt_2_115200 }, | |
2035 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, | |
2036 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2037 | pbn_b0_bt_4_460800 }, | |
2038 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, | |
2039 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2040 | pbn_b0_bt_4_460800 }, | |
2041 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, | |
2042 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2043 | pbn_b0_bt_2_460800 }, | |
2044 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, | |
2045 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2046 | pbn_b0_bt_2_460800 }, | |
2047 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, | |
2048 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2049 | pbn_b0_bt_2_460800 }, | |
2050 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, | |
2051 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2052 | pbn_b0_bt_1_115200 }, | |
2053 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, | |
2054 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2055 | pbn_b0_bt_1_460800 }, | |
2056 | ||
2057 | /* | |
2058 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com | |
2059 | */ | |
2060 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, | |
2061 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2062 | pbn_b1_1_1382400 }, | |
2063 | ||
2064 | /* | |
2065 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com | |
2066 | */ | |
2067 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, | |
2068 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2069 | pbn_b1_1_1382400 }, | |
2070 | ||
2071 | /* | |
2072 | * RAStel 2 port modem, gerg@moreton.com.au | |
2073 | */ | |
2074 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, | |
2075 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2076 | pbn_b2_bt_2_115200 }, | |
2077 | ||
2078 | /* | |
2079 | * EKF addition for i960 Boards form EKF with serial port | |
2080 | */ | |
2081 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, | |
2082 | 0xE4BF, PCI_ANY_ID, 0, 0, | |
2083 | pbn_intel_i960 }, | |
2084 | ||
2085 | /* | |
2086 | * Xircom Cardbus/Ethernet combos | |
2087 | */ | |
2088 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
2089 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2090 | pbn_b0_1_115200 }, | |
2091 | /* | |
2092 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) | |
2093 | */ | |
2094 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, | |
2095 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2096 | pbn_b0_1_115200 }, | |
2097 | ||
2098 | /* | |
2099 | * Untested PCI modems, sent in from various folks... | |
2100 | */ | |
2101 | ||
2102 | /* | |
2103 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> | |
2104 | */ | |
2105 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, | |
2106 | 0x1048, 0x1500, 0, 0, | |
2107 | pbn_b1_1_115200 }, | |
2108 | ||
2109 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, | |
2110 | 0xFF00, 0, 0, 0, | |
2111 | pbn_sgi_ioc3 }, | |
2112 | ||
2113 | /* | |
2114 | * HP Diva card | |
2115 | */ | |
2116 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
2117 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, | |
2118 | pbn_b1_1_115200 }, | |
2119 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
2120 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2121 | pbn_b0_5_115200 }, | |
2122 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, | |
2123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2124 | pbn_b2_1_115200 }, | |
2125 | ||
2126 | /* | |
2127 | * NEC Vrc-5074 (Nile 4) builtin UART. | |
2128 | */ | |
2129 | { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4, | |
2130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2131 | pbn_nec_nile4 }, | |
2132 | ||
2133 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, | |
2134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2135 | pbn_b3_4_115200 }, | |
2136 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, | |
2137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2138 | pbn_b3_8_115200 }, | |
2139 | ||
2140 | /* | |
2141 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | |
2142 | */ | |
2143 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | |
2144 | PCI_ANY_ID, PCI_ANY_ID, | |
2145 | 0, | |
2146 | 0, pbn_exar_XR17C152 }, | |
2147 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | |
2148 | PCI_ANY_ID, PCI_ANY_ID, | |
2149 | 0, | |
2150 | 0, pbn_exar_XR17C154 }, | |
2151 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | |
2152 | PCI_ANY_ID, PCI_ANY_ID, | |
2153 | 0, | |
2154 | 0, pbn_exar_XR17C158 }, | |
2155 | ||
2156 | /* | |
2157 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) | |
2158 | */ | |
2159 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, | |
2160 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2161 | pbn_b0_1_115200 }, | |
2162 | ||
2163 | /* | |
2164 | * These entries match devices with class COMMUNICATION_SERIAL, | |
2165 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL | |
2166 | */ | |
2167 | { PCI_ANY_ID, PCI_ANY_ID, | |
2168 | PCI_ANY_ID, PCI_ANY_ID, | |
2169 | PCI_CLASS_COMMUNICATION_SERIAL << 8, | |
2170 | 0xffff00, pbn_default }, | |
2171 | { PCI_ANY_ID, PCI_ANY_ID, | |
2172 | PCI_ANY_ID, PCI_ANY_ID, | |
2173 | PCI_CLASS_COMMUNICATION_MODEM << 8, | |
2174 | 0xffff00, pbn_default }, | |
2175 | { PCI_ANY_ID, PCI_ANY_ID, | |
2176 | PCI_ANY_ID, PCI_ANY_ID, | |
2177 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, | |
2178 | 0xffff00, pbn_default }, | |
2179 | { 0, } | |
2180 | }; | |
2181 | ||
2182 | static struct pci_driver serial_pci_driver = { | |
2183 | .name = "serial", | |
2184 | .probe = pciserial_init_one, | |
2185 | .remove = __devexit_p(pciserial_remove_one), | |
2186 | .suspend = pciserial_suspend_one, | |
2187 | .resume = pciserial_resume_one, | |
2188 | .id_table = serial_pci_tbl, | |
2189 | }; | |
2190 | ||
2191 | static int __init serial8250_pci_init(void) | |
2192 | { | |
2193 | return pci_register_driver(&serial_pci_driver); | |
2194 | } | |
2195 | ||
2196 | static void __exit serial8250_pci_exit(void) | |
2197 | { | |
2198 | pci_unregister_driver(&serial_pci_driver); | |
2199 | } | |
2200 | ||
2201 | module_init(serial8250_pci_init); | |
2202 | module_exit(serial8250_pci_exit); | |
2203 | ||
2204 | MODULE_LICENSE("GPL"); | |
2205 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); | |
2206 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); |