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Merge branch 'tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 256
85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
1da177e4
LT		 99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
a4ed1e41 109#include <asm/serial.h>
1da177e4
LT		 110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
cb3592be 119static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
026d02a2 123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
1da177e4 138 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 145 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
1da177e4
LT		 156
157 /*
158 * We provide a per-port pm hook.
159 */
160 void (*pm)(struct uart_port *port,
161 unsigned int state, unsigned int old);
162};
163
164struct irq_info {
25db8ad5
AC		 165 struct hlist_node node;
166 int irq;
167 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 168 struct list_head *head;
169};
170
25db8ad5
AC		 171#define NR_IRQ_HASH 32 /* Can be adjusted later */
172static struct hlist_head irq_lists[NR_IRQ_HASH];
173static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 174
175/*
176 * Here we define the default xmit fifo size used for each type of UART.
177 */
178static const struct serial8250_config uart_config[] = {
179 [PORT_UNKNOWN] = {
180 .name = "unknown",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_8250] = {
185 .name = "8250",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 },
189 [PORT_16450] = {
190 .name = "16450",
191 .fifo_size = 1,
192 .tx_loadsz = 1,
193 },
194 [PORT_16550] = {
195 .name = "16550",
196 .fifo_size = 1,
197 .tx_loadsz = 1,
198 },
199 [PORT_16550A] = {
200 .name = "16550A",
201 .fifo_size = 16,
202 .tx_loadsz = 16,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO,
205 },
206 [PORT_CIRRUS] = {
207 .name = "Cirrus",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16650] = {
212 .name = "ST16650",
213 .fifo_size = 1,
214 .tx_loadsz = 1,
215 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
216 },
217 [PORT_16650V2] = {
218 .name = "ST16650V2",
219 .fifo_size = 32,
220 .tx_loadsz = 16,
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 UART_FCR_T_TRIG_00,
223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 },
225 [PORT_16750] = {
226 .name = "TI16750",
227 .fifo_size = 64,
228 .tx_loadsz = 64,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
230 UART_FCR7_64BYTE,
231 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
232 },
233 [PORT_STARTECH] = {
234 .name = "Startech",
235 .fifo_size = 1,
236 .tx_loadsz = 1,
237 },
238 [PORT_16C950] = {
239 .name = "16C950/954",
240 .fifo_size = 128,
241 .tx_loadsz = 128,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO,
244 },
245 [PORT_16654] = {
246 .name = "ST16654",
247 .fifo_size = 64,
248 .tx_loadsz = 32,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
250 UART_FCR_T_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 },
253 [PORT_16850] = {
254 .name = "XR16850",
255 .fifo_size = 128,
256 .tx_loadsz = 128,
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 },
260 [PORT_RSA] = {
261 .name = "RSA",
262 .fifo_size = 2048,
263 .tx_loadsz = 2048,
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
265 .flags = UART_CAP_FIFO,
266 },
267 [PORT_NS16550A] = {
268 .name = "NS16550A",
269 .fifo_size = 16,
270 .tx_loadsz = 16,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 },
274 [PORT_XSCALE] = {
275 .name = "XScale",
276 .fifo_size = 32,
277 .tx_loadsz = 32,
278 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
279 .flags = UART_CAP_FIFO | UART_CAP_UUE,
280 },
bd71c182
TK		 281 [PORT_RM9000] = {
282 .name = "RM9000",
283 .fifo_size = 16,
284 .tx_loadsz = 16,
285 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 286 .flags = UART_CAP_FIFO,
287 },
288 [PORT_OCTEON] = {
289 .name = "OCTEON",
290 .fifo_size = 64,
291 .tx_loadsz = 64,
292 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 293 .flags = UART_CAP_FIFO,
294 },
08e0992f
FF		 295 [PORT_AR7] = {
296 .name = "AR7",
297 .fifo_size = 16,
298 .tx_loadsz = 16,
299 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
300 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 },
1da177e4
LT		 302};
303
bd71c182 304#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 305
306/* Au1x00 UART hardware has a weird register layout */
307static const u8 au_io_in_map[] = {
308 [UART_RX] = 0,
309 [UART_IER] = 2,
310 [UART_IIR] = 3,
311 [UART_LCR] = 5,
312 [UART_MCR] = 6,
313 [UART_LSR] = 7,
314 [UART_MSR] = 8,
315};
316
317static const u8 au_io_out_map[] = {
318 [UART_TX] = 1,
319 [UART_IER] = 2,
320 [UART_FCR] = 4,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323};
324
325/* sane hardware needs no mapping */
7d6a07d1 326static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 327{
7d6a07d1 328 if (p->iotype != UPIO_AU)
21c614a7
PA		 329 return offset;
330 return au_io_in_map[offset];
331}
332
7d6a07d1 333static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 334{
7d6a07d1 335 if (p->iotype != UPIO_AU)
21c614a7
PA		 336 return offset;
337 return au_io_out_map[offset];
338}
339
6f803cd0 340#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 341
342static const u8
343 regmap_in[8] = {
344 [UART_RX] = 0x00,
345 [UART_IER] = 0x0c,
346 [UART_IIR] = 0x14,
347 [UART_LCR] = 0x1c,
348 [UART_MCR] = 0x20,
349 [UART_LSR] = 0x24,
350 [UART_MSR] = 0x28,
351 [UART_SCR] = 0x2c
352 },
353 regmap_out[8] = {
354 [UART_TX] = 0x04,
355 [UART_IER] = 0x0c,
356 [UART_FCR] = 0x18,
357 [UART_LCR] = 0x1c,
358 [UART_MCR] = 0x20,
359 [UART_LSR] = 0x24,
360 [UART_MSR] = 0x28,
361 [UART_SCR] = 0x2c
362 };
363
7d6a07d1 364static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 365{
7d6a07d1 366 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 367 return offset;
368 return regmap_in[offset];
369}
370
7d6a07d1 371static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 372{
7d6a07d1 373 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 374 return offset;
375 return regmap_out[offset];
376}
377
21c614a7
PA		 378#else
379
380/* sane hardware needs no mapping */
381#define map_8250_in_reg(up, offset) (offset)
382#define map_8250_out_reg(up, offset) (offset)
383
384#endif
385
7d6a07d1 386static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 387{
7d6a07d1
DD		 388 offset = map_8250_in_reg(p, offset) << p->regshift;
389 outb(p->hub6 - 1 + offset, p->iobase);
390 return inb(p->iobase + 1);
391}
1da177e4 392
7d6a07d1
DD		 393static void hub6_serial_out(struct uart_port *p, int offset, int value)
394{
395 offset = map_8250_out_reg(p, offset) << p->regshift;
396 outb(p->hub6 - 1 + offset, p->iobase);
397 outb(value, p->iobase + 1);
398}
1da177e4 399
7d6a07d1
DD		 400static unsigned int mem_serial_in(struct uart_port *p, int offset)
401{
402 offset = map_8250_in_reg(p, offset) << p->regshift;
403 return readb(p->membase + offset);
404}
1da177e4 405
7d6a07d1
DD		 406static void mem_serial_out(struct uart_port *p, int offset, int value)
407{
408 offset = map_8250_out_reg(p, offset) << p->regshift;
409 writeb(value, p->membase + offset);
410}
411
412static void mem32_serial_out(struct uart_port *p, int offset, int value)
413{
414 offset = map_8250_out_reg(p, offset) << p->regshift;
415 writel(value, p->membase + offset);
416}
417
418static unsigned int mem32_serial_in(struct uart_port *p, int offset)
419{
420 offset = map_8250_in_reg(p, offset) << p->regshift;
421 return readl(p->membase + offset);
422}
1da177e4 423
21c614a7 424#ifdef CONFIG_SERIAL_8250_AU1X00
7d6a07d1
DD		 425static unsigned int au_serial_in(struct uart_port *p, int offset)
426{
427 offset = map_8250_in_reg(p, offset) << p->regshift;
428 return __raw_readl(p->membase + offset);
429}
430
431static void au_serial_out(struct uart_port *p, int offset, int value)
432{
433 offset = map_8250_out_reg(p, offset) << p->regshift;
434 __raw_writel(value, p->membase + offset);
435}
21c614a7
PA		 436#endif
437
7d6a07d1
DD		 438static unsigned int tsi_serial_in(struct uart_port *p, int offset)
439{
440 unsigned int tmp;
441 offset = map_8250_in_reg(p, offset) << p->regshift;
442 if (offset == UART_IIR) {
443 tmp = readl(p->membase + (UART_IIR & ~3));
444 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
445 } else
446 return readb(p->membase + offset);
447}
3be91ec7 448
7d6a07d1
DD		 449static void tsi_serial_out(struct uart_port *p, int offset, int value)
450{
451 offset = map_8250_out_reg(p, offset) << p->regshift;
452 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
453 writeb(value, p->membase + offset);
1da177e4
LT		 454}
455
7d6a07d1 456static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 457{
beab697a 458 int save_offset = offset;
7d6a07d1
DD		 459 offset = map_8250_out_reg(p, offset) << p->regshift;
460 /* Save the LCR value so it can be re-written when a
461 * Busy Detect interrupt occurs. */
462 if (save_offset == UART_LCR) {
463 struct uart_8250_port *up = (struct uart_8250_port *)p;
464 up->lcr = value;
465 }
466 writeb(value, p->membase + offset);
467 /* Read the IER to ensure any interrupt is cleared before
468 * returning from ISR. */
469 if (save_offset == UART_TX || save_offset == UART_IER)
470 value = p->serial_in(p, UART_IER);
471}
1da177e4 472
7d6a07d1
DD		 473static unsigned int io_serial_in(struct uart_port *p, int offset)
474{
475 offset = map_8250_in_reg(p, offset) << p->regshift;
476 return inb(p->iobase + offset);
477}
478
479static void io_serial_out(struct uart_port *p, int offset, int value)
480{
481 offset = map_8250_out_reg(p, offset) << p->regshift;
482 outb(value, p->iobase + offset);
483}
484
485static void set_io_from_upio(struct uart_port *p)
486{
b8e7e40a 487 struct uart_8250_port *up = (struct uart_8250_port *)p;
7d6a07d1 488 switch (p->iotype) {
1da177e4 489 case UPIO_HUB6:
7d6a07d1
DD		 490 p->serial_in = hub6_serial_in;
491 p->serial_out = hub6_serial_out;
1da177e4
LT		 492 break;
493
494 case UPIO_MEM:
7d6a07d1
DD		 495 p->serial_in = mem_serial_in;
496 p->serial_out = mem_serial_out;
1da177e4
LT		 497 break;
498
bd71c182 499 case UPIO_RM9000:
1da177e4 500 case UPIO_MEM32:
7d6a07d1
DD		 501 p->serial_in = mem32_serial_in;
502 p->serial_out = mem32_serial_out;
1da177e4
LT		 503 break;
504
21c614a7
PA		 505#ifdef CONFIG_SERIAL_8250_AU1X00
506 case UPIO_AU:
7d6a07d1
DD		 507 p->serial_in = au_serial_in;
508 p->serial_out = au_serial_out;
21c614a7
PA		 509 break;
510#endif
3be91ec7 511 case UPIO_TSI:
7d6a07d1
DD		 512 p->serial_in = tsi_serial_in;
513 p->serial_out = tsi_serial_out;
3be91ec7 514 break;
21c614a7 515
beab697a 516 case UPIO_DWAPB:
7d6a07d1
DD		 517 p->serial_in = mem_serial_in;
518 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 519 break;
520
1da177e4 521 default:
7d6a07d1
DD		 522 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out;
524 break;
1da177e4 525 }
b8e7e40a
AC		 526 /* Remember loaded iotype */
527 up->cur_iotype = p->iotype;
1da177e4
LT		 528}
529
40b36daa
AW		 530static void
531serial_out_sync(struct uart_8250_port *up, int offset, int value)
532{
7d6a07d1
DD		 533 struct uart_port *p = &up->port;
534 switch (p->iotype) {
40b36daa
AW		 535 case UPIO_MEM:
536 case UPIO_MEM32:
537#ifdef CONFIG_SERIAL_8250_AU1X00
538 case UPIO_AU:
539#endif
beab697a 540 case UPIO_DWAPB:
7d6a07d1
DD		 541 p->serial_out(p, offset, value);
542 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 543 break;
544 default:
7d6a07d1 545 p->serial_out(p, offset, value);
40b36daa
AW		 546 }
547}
548
7d6a07d1
DD		 549#define serial_in(up, offset) \
550 (up->port.serial_in(&(up)->port, (offset)))
551#define serial_out(up, offset, value) \
552 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 553/*
554 * We used to support using pause I/O for certain machines. We
555 * haven't supported this for a while, but just in case it's badly
556 * needed for certain old 386 machines, I've left these #define's
557 * in....
558 */
559#define serial_inp(up, offset) serial_in(up, offset)
560#define serial_outp(up, offset, value) serial_out(up, offset, value)
561
b32b19b8
JAH		 562/* Uart divisor latch read */
563static inline int _serial_dl_read(struct uart_8250_port *up)
564{
565 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
566}
567
568/* Uart divisor latch write */
569static inline void _serial_dl_write(struct uart_8250_port *up, int value)
570{
571 serial_outp(up, UART_DLL, value & 0xff);
572 serial_outp(up, UART_DLM, value >> 8 & 0xff);
573}
574
6f803cd0 575#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 576/* Au1x00 haven't got a standard divisor latch */
577static int serial_dl_read(struct uart_8250_port *up)
578{
579 if (up->port.iotype == UPIO_AU)
580 return __raw_readl(up->port.membase + 0x28);
581 else
582 return _serial_dl_read(up);
583}
584
585static void serial_dl_write(struct uart_8250_port *up, int value)
586{
587 if (up->port.iotype == UPIO_AU)
588 __raw_writel(value, up->port.membase + 0x28);
589 else
590 _serial_dl_write(up, value);
591}
6f803cd0 592#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 593static int serial_dl_read(struct uart_8250_port *up)
594{
595 return (up->port.iotype == UPIO_RM9000) ?
596 (((__raw_readl(up->port.membase + 0x10) << 8) |
597 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
598 _serial_dl_read(up);
599}
600
601static void serial_dl_write(struct uart_8250_port *up, int value)
602{
603 if (up->port.iotype == UPIO_RM9000) {
604 __raw_writel(value, up->port.membase + 0x08);
605 __raw_writel(value >> 8, up->port.membase + 0x10);
606 } else {
607 _serial_dl_write(up, value);
608 }
609}
b32b19b8
JAH		 610#else
611#define serial_dl_read(up) _serial_dl_read(up)
612#define serial_dl_write(up, value) _serial_dl_write(up, value)
613#endif
1da177e4
LT		 614
615/*
616 * For the 16C950
617 */
618static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
619{
620 serial_out(up, UART_SCR, offset);
621 serial_out(up, UART_ICR, value);
622}
623
624static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
625{
626 unsigned int value;
627
628 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
629 serial_out(up, UART_SCR, offset);
630 value = serial_in(up, UART_ICR);
631 serial_icr_write(up, UART_ACR, up->acr);
632
633 return value;
634}
635
636/*
637 * FIFO support.
638 */
b5d674ab 639static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 640{
641 if (p->capabilities & UART_CAP_FIFO) {
642 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
643 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
644 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
645 serial_outp(p, UART_FCR, 0);
646 }
647}
648
649/*
650 * IER sleep support. UARTs which have EFRs need the "extended
651 * capability" bit enabled. Note that on XR16C850s, we need to
652 * reset LCR to write to IER.
653 */
b5d674ab 654static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 655{
656 if (p->capabilities & UART_CAP_SLEEP) {
657 if (p->capabilities & UART_CAP_EFR) {
658 serial_outp(p, UART_LCR, 0xBF);
659 serial_outp(p, UART_EFR, UART_EFR_ECB);
660 serial_outp(p, UART_LCR, 0);
661 }
662 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
663 if (p->capabilities & UART_CAP_EFR) {
664 serial_outp(p, UART_LCR, 0xBF);
665 serial_outp(p, UART_EFR, 0);
666 serial_outp(p, UART_LCR, 0);
667 }
668 }
669}
670
671#ifdef CONFIG_SERIAL_8250_RSA
672/*
673 * Attempts to turn on the RSA FIFO. Returns zero on failure.
674 * We set the port uart clock rate if we succeed.
675 */
676static int __enable_rsa(struct uart_8250_port *up)
677{
678 unsigned char mode;
679 int result;
680
681 mode = serial_inp(up, UART_RSA_MSR);
682 result = mode & UART_RSA_MSR_FIFO;
683
684 if (!result) {
685 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
686 mode = serial_inp(up, UART_RSA_MSR);
687 result = mode & UART_RSA_MSR_FIFO;
688 }
689
690 if (result)
691 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
692
693 return result;
694}
695
696static void enable_rsa(struct uart_8250_port *up)
697{
698 if (up->port.type == PORT_RSA) {
699 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
700 spin_lock_irq(&up->port.lock);
701 __enable_rsa(up);
702 spin_unlock_irq(&up->port.lock);
703 }
704 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
705 serial_outp(up, UART_RSA_FRR, 0);
706 }
707}
708
709/*
710 * Attempts to turn off the RSA FIFO. Returns zero on failure.
711 * It is unknown why interrupts were disabled in here. However,
712 * the caller is expected to preserve this behaviour by grabbing
713 * the spinlock before calling this function.
714 */
715static void disable_rsa(struct uart_8250_port *up)
716{
717 unsigned char mode;
718 int result;
719
720 if (up->port.type == PORT_RSA &&
721 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
722 spin_lock_irq(&up->port.lock);
723
724 mode = serial_inp(up, UART_RSA_MSR);
725 result = !(mode & UART_RSA_MSR_FIFO);
726
727 if (!result) {
728 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
729 mode = serial_inp(up, UART_RSA_MSR);
730 result = !(mode & UART_RSA_MSR_FIFO);
731 }
732
733 if (result)
734 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
735 spin_unlock_irq(&up->port.lock);
736 }
737}
738#endif /* CONFIG_SERIAL_8250_RSA */
739
740/*
741 * This is a quickie test to see how big the FIFO is.
742 * It doesn't work at all the time, more's the pity.
743 */
744static int size_fifo(struct uart_8250_port *up)
745{
b32b19b8
JAH		 746 unsigned char old_fcr, old_mcr, old_lcr;
747 unsigned short old_dl;
1da177e4
LT		 748 int count;
749
750 old_lcr = serial_inp(up, UART_LCR);
751 serial_outp(up, UART_LCR, 0);
752 old_fcr = serial_inp(up, UART_FCR);
753 old_mcr = serial_inp(up, UART_MCR);
754 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
755 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
756 serial_outp(up, UART_MCR, UART_MCR_LOOP);
757 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 758 old_dl = serial_dl_read(up);
759 serial_dl_write(up, 0x0001);
1da177e4
LT		 760 serial_outp(up, UART_LCR, 0x03);
761 for (count = 0; count < 256; count++)
762 serial_outp(up, UART_TX, count);
763 mdelay(20);/* FIXME - schedule_timeout */
764 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
765 (count < 256); count++)
766 serial_inp(up, UART_RX);
767 serial_outp(up, UART_FCR, old_fcr);
768 serial_outp(up, UART_MCR, old_mcr);
769 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 770 serial_dl_write(up, old_dl);
1da177e4
LT		 771 serial_outp(up, UART_LCR, old_lcr);
772
773 return count;
774}
775
776/*
777 * Read UART ID using the divisor method - set DLL and DLM to zero
778 * and the revision will be in DLL and device type in DLM. We
779 * preserve the device state across this.
780 */
781static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
782{
783 unsigned char old_dll, old_dlm, old_lcr;
784 unsigned int id;
785
786 old_lcr = serial_inp(p, UART_LCR);
787 serial_outp(p, UART_LCR, UART_LCR_DLAB);
788
789 old_dll = serial_inp(p, UART_DLL);
790 old_dlm = serial_inp(p, UART_DLM);
791
792 serial_outp(p, UART_DLL, 0);
793 serial_outp(p, UART_DLM, 0);
794
795 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
796
797 serial_outp(p, UART_DLL, old_dll);
798 serial_outp(p, UART_DLM, old_dlm);
799 serial_outp(p, UART_LCR, old_lcr);
800
801 return id;
802}
803
804/*
805 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
806 * When this function is called we know it is at least a StarTech
807 * 16650 V2, but it might be one of several StarTech UARTs, or one of
808 * its clones. (We treat the broken original StarTech 16650 V1 as a
809 * 16550, and why not? Startech doesn't seem to even acknowledge its
810 * existence.)
bd71c182 811 *
1da177e4
LT		 812 * What evil have men's minds wrought...
813 */
814static void autoconfig_has_efr(struct uart_8250_port *up)
815{
816 unsigned int id1, id2, id3, rev;
817
818 /*
819 * Everything with an EFR has SLEEP
820 */
821 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
822
823 /*
824 * First we check to see if it's an Oxford Semiconductor UART.
825 *
826 * If we have to do this here because some non-National
827 * Semiconductor clone chips lock up if you try writing to the
828 * LSR register (which serial_icr_read does)
829 */
830
831 /*
832 * Check for Oxford Semiconductor 16C950.
833 *
834 * EFR [4] must be set else this test fails.
835 *
836 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
837 * claims that it's needed for 952 dual UART's (which are not
838 * recommended for new designs).
839 */
840 up->acr = 0;
841 serial_out(up, UART_LCR, 0xBF);
842 serial_out(up, UART_EFR, UART_EFR_ECB);
843 serial_out(up, UART_LCR, 0x00);
844 id1 = serial_icr_read(up, UART_ID1);
845 id2 = serial_icr_read(up, UART_ID2);
846 id3 = serial_icr_read(up, UART_ID3);
847 rev = serial_icr_read(up, UART_REV);
848
849 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
850
851 if (id1 == 0x16 && id2 == 0xC9 &&
852 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
853 up->port.type = PORT_16C950;
4ba5e35d
RK		 854
855 /*
856 * Enable work around for the Oxford Semiconductor 952 rev B
857 * chip which causes it to seriously miscalculate baud rates
858 * when DLL is 0.
859 */
860 if (id3 == 0x52 && rev == 0x01)
861 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 862 return;
863 }
bd71c182 864
1da177e4
LT		 865 /*
866 * We check for a XR16C850 by setting DLL and DLM to 0, and then
867 * reading back DLL and DLM. The chip type depends on the DLM
868 * value read back:
869 * 0x10 - XR16C850 and the DLL contains the chip revision.
870 * 0x12 - XR16C2850.
871 * 0x14 - XR16C854.
872 */
873 id1 = autoconfig_read_divisor_id(up);
874 DEBUG_AUTOCONF("850id=%04x ", id1);
875
876 id2 = id1 >> 8;
877 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 878 up->port.type = PORT_16850;
879 return;
880 }
881
882 /*
883 * It wasn't an XR16C850.
884 *
885 * We distinguish between the '654 and the '650 by counting
886 * how many bytes are in the FIFO. I'm using this for now,
887 * since that's the technique that was sent to me in the
888 * serial driver update, but I'm not convinced this works.
889 * I've had problems doing this in the past. -TYT
890 */
891 if (size_fifo(up) == 64)
892 up->port.type = PORT_16654;
893 else
894 up->port.type = PORT_16650V2;
895}
896
897/*
898 * We detected a chip without a FIFO. Only two fall into
899 * this category - the original 8250 and the 16450. The
900 * 16450 has a scratch register (accessible with LCR=0)
901 */
902static void autoconfig_8250(struct uart_8250_port *up)
903{
904 unsigned char scratch, status1, status2;
905
906 up->port.type = PORT_8250;
907
908 scratch = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, 0xa5);
910 status1 = serial_in(up, UART_SCR);
911 serial_outp(up, UART_SCR, 0x5a);
912 status2 = serial_in(up, UART_SCR);
913 serial_outp(up, UART_SCR, scratch);
914
915 if (status1 == 0xa5 && status2 == 0x5a)
916 up->port.type = PORT_16450;
917}
918
919static int broken_efr(struct uart_8250_port *up)
920{
921 /*
922 * Exar ST16C2550 "A2" devices incorrectly detect as
923 * having an EFR, and report an ID of 0x0201. See
924 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
925 */
926 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
927 return 1;
928
929 return 0;
930}
931
932/*
933 * We know that the chip has FIFOs. Does it have an EFR? The
934 * EFR is located in the same register position as the IIR and
935 * we know the top two bits of the IIR are currently set. The
936 * EFR should contain zero. Try to read the EFR.
937 */
938static void autoconfig_16550a(struct uart_8250_port *up)
939{
940 unsigned char status1, status2;
941 unsigned int iersave;
942
943 up->port.type = PORT_16550A;
944 up->capabilities |= UART_CAP_FIFO;
945
946 /*
947 * Check for presence of the EFR when DLAB is set.
948 * Only ST16C650V1 UARTs pass this test.
949 */
950 serial_outp(up, UART_LCR, UART_LCR_DLAB);
951 if (serial_in(up, UART_EFR) == 0) {
952 serial_outp(up, UART_EFR, 0xA8);
953 if (serial_in(up, UART_EFR) != 0) {
954 DEBUG_AUTOCONF("EFRv1 ");
955 up->port.type = PORT_16650;
956 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
957 } else {
958 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
959 }
960 serial_outp(up, UART_EFR, 0);
961 return;
962 }
963
964 /*
965 * Maybe it requires 0xbf to be written to the LCR.
966 * (other ST16C650V2 UARTs, TI16C752A, etc)
967 */
968 serial_outp(up, UART_LCR, 0xBF);
969 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
970 DEBUG_AUTOCONF("EFRv2 ");
971 autoconfig_has_efr(up);
972 return;
973 }
974
975 /*
976 * Check for a National Semiconductor SuperIO chip.
977 * Attempt to switch to bank 2, read the value of the LOOP bit
978 * from EXCR1. Switch back to bank 0, change it in MCR. Then
979 * switch back to bank 2, read it from EXCR1 again and check
980 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 981 */
982 serial_outp(up, UART_LCR, 0);
983 status1 = serial_in(up, UART_MCR);
984 serial_outp(up, UART_LCR, 0xE0);
985 status2 = serial_in(up, 0x02); /* EXCR1 */
986
987 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
988 serial_outp(up, UART_LCR, 0);
989 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
990 serial_outp(up, UART_LCR, 0xE0);
991 status2 = serial_in(up, 0x02); /* EXCR1 */
992 serial_outp(up, UART_LCR, 0);
993 serial_outp(up, UART_MCR, status1);
994
995 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 996 unsigned short quot;
997
1da177e4 998 serial_outp(up, UART_LCR, 0xE0);
857dde2e 999
b32b19b8 1000 quot = serial_dl_read(up);
857dde2e
DW		 1001 quot <<= 3;
1002
b5b82df6 1003 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 1004 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1005 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1006 serial_outp(up, 0x04, status1);
bd71c182 1007
b32b19b8 1008 serial_dl_write(up, quot);
857dde2e 1009
1da177e4 1010 serial_outp(up, UART_LCR, 0);
1da177e4 1011
857dde2e 1012 up->port.uartclk = 921600*16;
1da177e4
LT		 1013 up->port.type = PORT_NS16550A;
1014 up->capabilities |= UART_NATSEMI;
1015 return;
1016 }
1017 }
1018
1019 /*
1020 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1021 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1022 * Try setting it with and without DLAB set. Cheap clones
1023 * set bit 5 without DLAB set.
1024 */
1025 serial_outp(up, UART_LCR, 0);
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1027 status1 = serial_in(up, UART_IIR) >> 5;
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1029 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1030 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1031 status2 = serial_in(up, UART_IIR) >> 5;
1032 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1033 serial_outp(up, UART_LCR, 0);
1034
1035 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1036
1037 if (status1 == 6 && status2 == 7) {
1038 up->port.type = PORT_16750;
1039 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1040 return;
1041 }
1042
1043 /*
1044 * Try writing and reading the UART_IER_UUE bit (b6).
1045 * If it works, this is probably one of the Xscale platform's
1046 * internal UARTs.
1047 * We're going to explicitly set the UUE bit to 0 before
1048 * trying to write and read a 1 just to make sure it's not
1049 * already a 1 and maybe locked there before we even start start.
1050 */
1051 iersave = serial_in(up, UART_IER);
1052 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1053 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1054 /*
1055 * OK it's in a known zero state, try writing and reading
1056 * without disturbing the current state of the other bits.
1057 */
1058 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1059 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1060 /*
1061 * It's an Xscale.
1062 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1063 */
1064 DEBUG_AUTOCONF("Xscale ");
1065 up->port.type = PORT_XSCALE;
1066 up->capabilities |= UART_CAP_UUE;
1067 return;
1068 }
1069 } else {
1070 /*
1071 * If we got here we couldn't force the IER_UUE bit to 0.
1072 * Log it and continue.
1073 */
1074 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1075 }
1076 serial_outp(up, UART_IER, iersave);
1077}
1078
1079/*
1080 * This routine is called by rs_init() to initialize a specific serial
1081 * port. It determines what type of UART chip this serial port is
1082 * using: 8250, 16450, 16550, 16550A. The important question is
1083 * whether or not this UART is a 16550A or not, since this will
1084 * determine whether or not we can use its FIFO features or not.
1085 */
1086static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1087{
1088 unsigned char status1, scratch, scratch2, scratch3;
1089 unsigned char save_lcr, save_mcr;
1090 unsigned long flags;
1091
1092 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1093 return;
1094
80647b95 1095 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1096 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1097
1098 /*
1099 * We really do need global IRQs disabled here - we're going to
1100 * be frobbing the chips IRQ enable register to see if it exists.
1101 */
1102 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1103
1104 up->capabilities = 0;
4ba5e35d 1105 up->bugs = 0;
1da177e4
LT		 1106
1107 if (!(up->port.flags & UPF_BUGGY_UART)) {
1108 /*
1109 * Do a simple existence test first; if we fail this,
1110 * there's no point trying anything else.
bd71c182 1111 *
1da177e4
LT		 1112 * 0x80 is used as a nonsense port to prevent against
1113 * false positives due to ISA bus float. The
1114 * assumption is that 0x80 is a non-existent port;
1115 * which should be safe since include/asm/io.h also
1116 * makes this assumption.
1117 *
1118 * Note: this is safe as long as MCR bit 4 is clear
1119 * and the device is in "PC" mode.
1120 */
1121 scratch = serial_inp(up, UART_IER);
1122 serial_outp(up, UART_IER, 0);
1123#ifdef __i386__
1124 outb(0xff, 0x080);
1125#endif
48212008
TH		 1126 /*
1127 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1128 * 16C754B) allow only to modify them if an EFR bit is set.
1129 */
1130 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1131 serial_outp(up, UART_IER, 0x0F);
1132#ifdef __i386__
1133 outb(0, 0x080);
1134#endif
48212008 1135 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1136 serial_outp(up, UART_IER, scratch);
1137 if (scratch2 != 0 || scratch3 != 0x0F) {
1138 /*
1139 * We failed; there's nothing here
1140 */
1141 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1142 scratch2, scratch3);
1143 goto out;
1144 }
1145 }
1146
1147 save_mcr = serial_in(up, UART_MCR);
1148 save_lcr = serial_in(up, UART_LCR);
1149
bd71c182 1150 /*
1da177e4
LT		 1151 * Check to see if a UART is really there. Certain broken
1152 * internal modems based on the Rockwell chipset fail this
1153 * test, because they apparently don't implement the loopback
1154 * test mode. So this test is skipped on the COM 1 through
1155 * COM 4 ports. This *should* be safe, since no board
1156 * manufacturer would be stupid enough to design a board
1157 * that conflicts with COM 1-4 --- we hope!
1158 */
1159 if (!(up->port.flags & UPF_SKIP_TEST)) {
1160 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1161 status1 = serial_inp(up, UART_MSR) & 0xF0;
1162 serial_outp(up, UART_MCR, save_mcr);
1163 if (status1 != 0x90) {
1164 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1165 status1);
1166 goto out;
1167 }
1168 }
1169
1170 /*
1171 * We're pretty sure there's a port here. Lets find out what
1172 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1173 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1174 * determines what we test for next.
1175 *
1176 * We also initialise the EFR (if any) to zero for later. The
1177 * EFR occupies the same register location as the FCR and IIR.
1178 */
1179 serial_outp(up, UART_LCR, 0xBF);
1180 serial_outp(up, UART_EFR, 0);
1181 serial_outp(up, UART_LCR, 0);
1182
1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1184 scratch = serial_in(up, UART_IIR) >> 6;
1185
1186 DEBUG_AUTOCONF("iir=%d ", scratch);
1187
1188 switch (scratch) {
1189 case 0:
1190 autoconfig_8250(up);
1191 break;
1192 case 1:
1193 up->port.type = PORT_UNKNOWN;
1194 break;
1195 case 2:
1196 up->port.type = PORT_16550;
1197 break;
1198 case 3:
1199 autoconfig_16550a(up);
1200 break;
1201 }
1202
1203#ifdef CONFIG_SERIAL_8250_RSA
1204 /*
1205 * Only probe for RSA ports if we got the region.
1206 */
1207 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1208 int i;
1209
1210 for (i = 0 ; i < probe_rsa_count; ++i) {
1211 if (probe_rsa[i] == up->port.iobase &&
1212 __enable_rsa(up)) {
1213 up->port.type = PORT_RSA;
1214 break;
1215 }
1216 }
1217 }
1218#endif
21c614a7
PA		 1219
1220#ifdef CONFIG_SERIAL_8250_AU1X00
1221 /* if access method is AU, it is a 16550 with a quirk */
1222 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1223 up->bugs |= UART_BUG_NOMSR;
1224#endif
1225
1da177e4
LT		 1226 serial_outp(up, UART_LCR, save_lcr);
1227
1228 if (up->capabilities != uart_config[up->port.type].flags) {
1229 printk(KERN_WARNING
1230 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1231 serial_index(&up->port), up->capabilities,
1232 uart_config[up->port.type].flags);
1da177e4
LT		 1233 }
1234
1235 up->port.fifosize = uart_config[up->port.type].fifo_size;
1236 up->capabilities = uart_config[up->port.type].flags;
1237 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1238
1239 if (up->port.type == PORT_UNKNOWN)
1240 goto out;
1241
1242 /*
1243 * Reset the UART.
1244 */
1245#ifdef CONFIG_SERIAL_8250_RSA
1246 if (up->port.type == PORT_RSA)
1247 serial_outp(up, UART_RSA_FRR, 0);
1248#endif
1249 serial_outp(up, UART_MCR, save_mcr);
1250 serial8250_clear_fifos(up);
40b36daa 1251 serial_in(up, UART_RX);
5c8c755c
LB		 1252 if (up->capabilities & UART_CAP_UUE)
1253 serial_outp(up, UART_IER, UART_IER_UUE);
1254 else
1255 serial_outp(up, UART_IER, 0);
1da177e4 1256
bd71c182 1257 out:
1da177e4 1258 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1259 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1260}
1261
1262static void autoconfig_irq(struct uart_8250_port *up)
1263{
1264 unsigned char save_mcr, save_ier;
1265 unsigned char save_ICP = 0;
1266 unsigned int ICP = 0;
1267 unsigned long irqs;
1268 int irq;
1269
1270 if (up->port.flags & UPF_FOURPORT) {
1271 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1272 save_ICP = inb_p(ICP);
1273 outb_p(0x80, ICP);
1274 (void) inb_p(ICP);
1275 }
1276
1277 /* forget possible initially masked and pending IRQ */
1278 probe_irq_off(probe_irq_on());
1279 save_mcr = serial_inp(up, UART_MCR);
1280 save_ier = serial_inp(up, UART_IER);
1281 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1282
1da177e4
LT		 1283 irqs = probe_irq_on();
1284 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1285 udelay(10);
1286 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1287 serial_outp(up, UART_MCR,
1288 UART_MCR_DTR | UART_MCR_RTS);
1289 } else {
1290 serial_outp(up, UART_MCR,
1291 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1292 }
1293 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1294 (void)serial_inp(up, UART_LSR);
1295 (void)serial_inp(up, UART_RX);
1296 (void)serial_inp(up, UART_IIR);
1297 (void)serial_inp(up, UART_MSR);
1298 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1299 udelay(20);
1da177e4
LT		 1300 irq = probe_irq_off(irqs);
1301
1302 serial_outp(up, UART_MCR, save_mcr);
1303 serial_outp(up, UART_IER, save_ier);
1304
1305 if (up->port.flags & UPF_FOURPORT)
1306 outb_p(save_ICP, ICP);
1307
1308 up->port.irq = (irq > 0) ? irq : 0;
1309}
1310
e763b90c
RK		 1311static inline void __stop_tx(struct uart_8250_port *p)
1312{
1313 if (p->ier & UART_IER_THRI) {
1314 p->ier &= ~UART_IER_THRI;
1315 serial_out(p, UART_IER, p->ier);
1316 }
1317}
1318
b129a8cc 1319static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1320{
1321 struct uart_8250_port *up = (struct uart_8250_port *)port;
1322
e763b90c 1323 __stop_tx(up);
1da177e4
LT		 1324
1325 /*
e763b90c 1326 * We really want to stop the transmitter from sending.
1da177e4 1327 */
e763b90c 1328 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1329 up->acr |= UART_ACR_TXDIS;
1330 serial_icr_write(up, UART_ACR, up->acr);
1331 }
1332}
1333
55d3b282
RK		 1334static void transmit_chars(struct uart_8250_port *up);
1335
b129a8cc 1336static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1337{
1338 struct uart_8250_port *up = (struct uart_8250_port *)port;
1339
1340 if (!(up->ier & UART_IER_THRI)) {
1341 up->ier |= UART_IER_THRI;
1342 serial_out(up, UART_IER, up->ier);
55d3b282 1343
67f7654e 1344 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1345 unsigned char lsr;
55d3b282 1346 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1347 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1348 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1349 (lsr & UART_LSR_THRE) :
1350 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1351 transmit_chars(up);
1352 }
1da177e4 1353 }
e763b90c 1354
1da177e4 1355 /*
e763b90c 1356 * Re-enable the transmitter if we disabled it.
1da177e4 1357 */
e763b90c 1358 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1359 up->acr &= ~UART_ACR_TXDIS;
1360 serial_icr_write(up, UART_ACR, up->acr);
1361 }
1362}
1363
1364static void serial8250_stop_rx(struct uart_port *port)
1365{
1366 struct uart_8250_port *up = (struct uart_8250_port *)port;
1367
1368 up->ier &= ~UART_IER_RLSI;
1369 up->port.read_status_mask &= ~UART_LSR_DR;
1370 serial_out(up, UART_IER, up->ier);
1371}
1372
1373static void serial8250_enable_ms(struct uart_port *port)
1374{
1375 struct uart_8250_port *up = (struct uart_8250_port *)port;
1376
21c614a7
PA		 1377 /* no MSR capabilities */
1378 if (up->bugs & UART_BUG_NOMSR)
1379 return;
1380
1da177e4
LT		 1381 up->ier |= UART_IER_MSI;
1382 serial_out(up, UART_IER, up->ier);
1383}
1384
ea8874dc 1385static void
cc79aa9d 1386receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1387{
ebd2c8f6 1388 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1389 unsigned char ch, lsr = *status;
1390 int max_count = 256;
1391 char flag;
1392
1393 do {
7500b1f6
AR		 1394 if (likely(lsr & UART_LSR_DR))
1395 ch = serial_inp(up, UART_RX);
1396 else
1397 /*
1398 * Intel 82571 has a Serial Over Lan device that will
1399 * set UART_LSR_BI without setting UART_LSR_DR when
1400 * it receives a break. To avoid reading from the
1401 * receive buffer without UART_LSR_DR bit set, we
1402 * just force the read character to be 0
1403 */
1404 ch = 0;
1405
1da177e4
LT		 1406 flag = TTY_NORMAL;
1407 up->port.icount.rx++;
1408
ad4c2aa6
CM		 1409 lsr |= up->lsr_saved_flags;
1410 up->lsr_saved_flags = 0;
1da177e4 1411
ad4c2aa6 1412 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1413 /*
1414 * For statistics only
1415 */
1416 if (lsr & UART_LSR_BI) {
1417 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1418 up->port.icount.brk++;
1419 /*
1420 * We do the SysRQ and SAK checking
1421 * here because otherwise the break
1422 * may get masked by ignore_status_mask
1423 * or read_status_mask.
1424 */
1425 if (uart_handle_break(&up->port))
1426 goto ignore_char;
1427 } else if (lsr & UART_LSR_PE)
1428 up->port.icount.parity++;
1429 else if (lsr & UART_LSR_FE)
1430 up->port.icount.frame++;
1431 if (lsr & UART_LSR_OE)
1432 up->port.icount.overrun++;
1433
1434 /*
23907eb8 1435 * Mask off conditions which should be ignored.
1da177e4
LT		 1436 */
1437 lsr &= up->port.read_status_mask;
1438
1439 if (lsr & UART_LSR_BI) {
1440 DEBUG_INTR("handling break....");
1441 flag = TTY_BREAK;
1442 } else if (lsr & UART_LSR_PE)
1443 flag = TTY_PARITY;
1444 else if (lsr & UART_LSR_FE)
1445 flag = TTY_FRAME;
1446 }
7d12e780 1447 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1448 goto ignore_char;
05ab3014
RK		 1449
1450 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1451
6f803cd0 1452ignore_char:
1da177e4 1453 lsr = serial_inp(up, UART_LSR);
7500b1f6 1454 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1455 spin_unlock(&up->port.lock);
1456 tty_flip_buffer_push(tty);
1457 spin_lock(&up->port.lock);
1458 *status = lsr;
1459}
1460
ea8874dc 1461static void transmit_chars(struct uart_8250_port *up)
1da177e4 1462{
ebd2c8f6 1463 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1464 int count;
1465
1466 if (up->port.x_char) {
1467 serial_outp(up, UART_TX, up->port.x_char);
1468 up->port.icount.tx++;
1469 up->port.x_char = 0;
1470 return;
1471 }
b129a8cc
RK		 1472 if (uart_tx_stopped(&up->port)) {
1473 serial8250_stop_tx(&up->port);
1474 return;
1475 }
1476 if (uart_circ_empty(xmit)) {
e763b90c 1477 __stop_tx(up);
1da177e4
LT		 1478 return;
1479 }
1480
1481 count = up->tx_loadsz;
1482 do {
1483 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1485 up->port.icount.tx++;
1486 if (uart_circ_empty(xmit))
1487 break;
1488 } while (--count > 0);
1489
1490 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1491 uart_write_wakeup(&up->port);
1492
1493 DEBUG_INTR("THRE...");
1494
1495 if (uart_circ_empty(xmit))
e763b90c 1496 __stop_tx(up);
1da177e4
LT		 1497}
1498
2af7cd68 1499static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1500{
2af7cd68
RK		 1501 unsigned int status = serial_in(up, UART_MSR);
1502
ad4c2aa6
CM		 1503 status |= up->msr_saved_flags;
1504 up->msr_saved_flags = 0;
fdc30b3d 1505 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1506 up->port.state != NULL) {
2af7cd68
RK		 1507 if (status & UART_MSR_TERI)
1508 up->port.icount.rng++;
1509 if (status & UART_MSR_DDSR)
1510 up->port.icount.dsr++;
1511 if (status & UART_MSR_DDCD)
1512 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1513 if (status & UART_MSR_DCTS)
1514 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1515
bdc04e31 1516 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1517 }
1da177e4 1518
2af7cd68 1519 return status;
1da177e4
LT		 1520}
1521
1522/*
1523 * This handles the interrupt from one port.
1524 */
b5d674ab 1525static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1526{
45e24601 1527 unsigned int status;
4bf3631c 1528 unsigned long flags;
45e24601 1529
4bf3631c 1530 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1531
1532 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1533
1534 DEBUG_INTR("status = %x...", status);
1535
7500b1f6 1536 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1537 receive_chars(up, &status);
1da177e4
LT		 1538 check_modem_status(up);
1539 if (status & UART_LSR_THRE)
1540 transmit_chars(up);
45e24601 1541
4bf3631c 1542 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1543}
1544
1545/*
1546 * This is the serial driver's interrupt routine.
1547 *
1548 * Arjan thinks the old way was overly complex, so it got simplified.
1549 * Alan disagrees, saying that need the complexity to handle the weird
1550 * nature of ISA shared interrupts. (This is a special exception.)
1551 *
1552 * In order to handle ISA shared interrupts properly, we need to check
1553 * that all ports have been serviced, and therefore the ISA interrupt
1554 * line has been de-asserted.
1555 *
1556 * This means we need to loop through all ports. checking that they
1557 * don't have an interrupt pending.
1558 */
7d12e780 1559static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1560{
1561 struct irq_info *i = dev_id;
1562 struct list_head *l, *end = NULL;
1563 int pass_counter = 0, handled = 0;
1564
1565 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1566
1567 spin_lock(&i->lock);
1568
1569 l = i->head;
1570 do {
1571 struct uart_8250_port *up;
1572 unsigned int iir;
1573
1574 up = list_entry(l, struct uart_8250_port, list);
1575
1576 iir = serial_in(up, UART_IIR);
1577 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1578 serial8250_handle_port(up);
1da177e4
LT		 1579
1580 handled = 1;
1581
beab697a
MSJ		 1582 end = NULL;
1583 } else if (up->port.iotype == UPIO_DWAPB &&
1584 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1585 /* The DesignWare APB UART has an Busy Detect (0x07)
1586 * interrupt meaning an LCR write attempt occured while the
1587 * UART was busy. The interrupt must be cleared by reading
1588 * the UART status register (USR) and the LCR re-written. */
1589 unsigned int status;
1590 status = *(volatile u32 *)up->port.private_data;
1591 serial_out(up, UART_LCR, up->lcr);
1592
1593 handled = 1;
1594
1da177e4
LT		 1595 end = NULL;
1596 } else if (end == NULL)
1597 end = l;
1598
1599 l = l->next;
1600
1601 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1602 /* If we hit this, we're dead. */
1603 printk(KERN_ERR "serial8250: too much work for "
1604 "irq%d\n", irq);
1605 break;
1606 }
1607 } while (l != end);
1608
1609 spin_unlock(&i->lock);
1610
1611 DEBUG_INTR("end.\n");
1612
1613 return IRQ_RETVAL(handled);
1614}
1615
1616/*
1617 * To support ISA shared interrupts, we need to have one interrupt
1618 * handler that ensures that the IRQ line has been deasserted
1619 * before returning. Failing to do this will result in the IRQ
1620 * line being stuck active, and, since ISA irqs are edge triggered,
1621 * no more IRQs will be seen.
1622 */
1623static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1624{
1625 spin_lock_irq(&i->lock);
1626
1627 if (!list_empty(i->head)) {
1628 if (i->head == &up->list)
1629 i->head = i->head->next;
1630 list_del(&up->list);
1631 } else {
1632 BUG_ON(i->head != &up->list);
1633 i->head = NULL;
1634 }
1da177e4 1635 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1636 /* List empty so throw away the hash node */
1637 if (i->head == NULL) {
1638 hlist_del(&i->node);
1639 kfree(i);
1640 }
1da177e4
LT		 1641}
1642
1643static int serial_link_irq_chain(struct uart_8250_port *up)
1644{
25db8ad5
AC		 1645 struct hlist_head *h;
1646 struct hlist_node *n;
1647 struct irq_info *i;
40663cc7 1648 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1649
25db8ad5
AC		 1650 mutex_lock(&hash_mutex);
1651
1652 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1653
1654 hlist_for_each(n, h) {
1655 i = hlist_entry(n, struct irq_info, node);
1656 if (i->irq == up->port.irq)
1657 break;
1658 }
1659
1660 if (n == NULL) {
1661 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1662 if (i == NULL) {
1663 mutex_unlock(&hash_mutex);
1664 return -ENOMEM;
1665 }
1666 spin_lock_init(&i->lock);
1667 i->irq = up->port.irq;
1668 hlist_add_head(&i->node, h);
1669 }
1670 mutex_unlock(&hash_mutex);
1671
1da177e4
LT		 1672 spin_lock_irq(&i->lock);
1673
1674 if (i->head) {
1675 list_add(&up->list, i->head);
1676 spin_unlock_irq(&i->lock);
1677
1678 ret = 0;
1679 } else {
1680 INIT_LIST_HEAD(&up->list);
1681 i->head = &up->list;
1682 spin_unlock_irq(&i->lock);
1c2f0493 1683 irq_flags |= up->port.irqflags;
1da177e4
LT		 1684 ret = request_irq(up->port.irq, serial8250_interrupt,
1685 irq_flags, "serial", i);
1686 if (ret < 0)
1687 serial_do_unlink(i, up);
1688 }
1689
1690 return ret;
1691}
1692
1693static void serial_unlink_irq_chain(struct uart_8250_port *up)
1694{
25db8ad5
AC		 1695 struct irq_info *i;
1696 struct hlist_node *n;
1697 struct hlist_head *h;
1da177e4 1698
25db8ad5
AC		 1699 mutex_lock(&hash_mutex);
1700
1701 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1702
1703 hlist_for_each(n, h) {
1704 i = hlist_entry(n, struct irq_info, node);
1705 if (i->irq == up->port.irq)
1706 break;
1707 }
1708
1709 BUG_ON(n == NULL);
1da177e4
LT		 1710 BUG_ON(i->head == NULL);
1711
1712 if (list_empty(i->head))
1713 free_irq(up->port.irq, i);
1714
1715 serial_do_unlink(i, up);
25db8ad5 1716 mutex_unlock(&hash_mutex);
1da177e4
LT		 1717}
1718
40b36daa
AW		 1719/* Base timer interval for polling */
1720static inline int poll_timeout(int timeout)
1721{
1722 return timeout > 6 ? (timeout / 2 - 2) : 1;
1723}
1724
1da177e4
LT		 1725/*
1726 * This function is used to handle ports that do not have an
1727 * interrupt. This doesn't work very well for 16450's, but gives
1728 * barely passable results for a 16550A. (Although at the expense
1729 * of much CPU overhead).
1730 */
1731static void serial8250_timeout(unsigned long data)
1732{
1733 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1734 unsigned int iir;
1735
1736 iir = serial_in(up, UART_IIR);
45e24601 1737 if (!(iir & UART_IIR_NO_INT))
7d12e780 1738 serial8250_handle_port(up);
40b36daa
AW		 1739 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1740}
1741
1742static void serial8250_backup_timeout(unsigned long data)
1743{
1744 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1745 unsigned int iir, ier = 0, lsr;
1746 unsigned long flags;
40b36daa
AW		 1747
1748 /*
1749 * Must disable interrupts or else we risk racing with the interrupt
1750 * based handler.
1751 */
1752 if (is_real_interrupt(up->port.irq)) {
1753 ier = serial_in(up, UART_IER);
1754 serial_out(up, UART_IER, 0);
1755 }
1da177e4 1756
40b36daa
AW		 1757 iir = serial_in(up, UART_IIR);
1758
1759 /*
1760 * This should be a safe test for anyone who doesn't trust the
1761 * IIR bits on their UART, but it's specifically designed for
1762 * the "Diva" UART used on the management processor on many HP
1763 * ia64 and parisc boxes.
1764 */
ad4c2aa6
CM		 1765 spin_lock_irqsave(&up->port.lock, flags);
1766 lsr = serial_in(up, UART_LSR);
1767 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1768 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1769 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1770 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1771 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1772 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1773 iir |= UART_IIR_THRI;
1774 }
1775
1776 if (!(iir & UART_IIR_NO_INT))
1777 serial8250_handle_port(up);
1778
1779 if (is_real_interrupt(up->port.irq))
1780 serial_out(up, UART_IER, ier);
1781
1782 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1783 mod_timer(&up->timer,
1784 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1785}
1786
1787static unsigned int serial8250_tx_empty(struct uart_port *port)
1788{
1789 struct uart_8250_port *up = (struct uart_8250_port *)port;
1790 unsigned long flags;
ad4c2aa6 1791 unsigned int lsr;
1da177e4
LT		 1792
1793 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1794 lsr = serial_in(up, UART_LSR);
1795 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1796 spin_unlock_irqrestore(&up->port.lock, flags);
1797
bca47613 1798 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1799}
1800
1801static unsigned int serial8250_get_mctrl(struct uart_port *port)
1802{
1803 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1804 unsigned int status;
1da177e4
LT		 1805 unsigned int ret;
1806
2af7cd68 1807 status = check_modem_status(up);
1da177e4
LT		 1808
1809 ret = 0;
1810 if (status & UART_MSR_DCD)
1811 ret |= TIOCM_CAR;
1812 if (status & UART_MSR_RI)
1813 ret |= TIOCM_RNG;
1814 if (status & UART_MSR_DSR)
1815 ret |= TIOCM_DSR;
1816 if (status & UART_MSR_CTS)
1817 ret |= TIOCM_CTS;
1818 return ret;
1819}
1820
1821static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1822{
1823 struct uart_8250_port *up = (struct uart_8250_port *)port;
1824 unsigned char mcr = 0;
1825
1826 if (mctrl & TIOCM_RTS)
1827 mcr |= UART_MCR_RTS;
1828 if (mctrl & TIOCM_DTR)
1829 mcr |= UART_MCR_DTR;
1830 if (mctrl & TIOCM_OUT1)
1831 mcr |= UART_MCR_OUT1;
1832 if (mctrl & TIOCM_OUT2)
1833 mcr |= UART_MCR_OUT2;
1834 if (mctrl & TIOCM_LOOP)
1835 mcr |= UART_MCR_LOOP;
1836
1837 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1838
1839 serial_out(up, UART_MCR, mcr);
1840}
1841
1842static void serial8250_break_ctl(struct uart_port *port, int break_state)
1843{
1844 struct uart_8250_port *up = (struct uart_8250_port *)port;
1845 unsigned long flags;
1846
1847 spin_lock_irqsave(&up->port.lock, flags);
1848 if (break_state == -1)
1849 up->lcr |= UART_LCR_SBC;
1850 else
1851 up->lcr &= ~UART_LCR_SBC;
1852 serial_out(up, UART_LCR, up->lcr);
1853 spin_unlock_irqrestore(&up->port.lock, flags);
1854}
1855
40b36daa
AW		 1856/*
1857 * Wait for transmitter & holding register to empty
1858 */
b5d674ab 1859static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1860{
1861 unsigned int status, tmout = 10000;
1862
1863 /* Wait up to 10ms for the character(s) to be sent. */
1864 do {
1865 status = serial_in(up, UART_LSR);
1866
ad4c2aa6 1867 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1868
1869 if (--tmout == 0)
1870 break;
1871 udelay(1);
1872 } while ((status & bits) != bits);
1873
1874 /* Wait up to 1s for flow control if necessary */
1875 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1876 unsigned int tmout;
1877 for (tmout = 1000000; tmout; tmout--) {
1878 unsigned int msr = serial_in(up, UART_MSR);
1879 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1880 if (msr & UART_MSR_CTS)
1881 break;
40b36daa
AW		 1882 udelay(1);
1883 touch_nmi_watchdog();
1884 }
1885 }
1886}
1887
f2d937f3
JW		 1888#ifdef CONFIG_CONSOLE_POLL
1889/*
1890 * Console polling routines for writing and reading from the uart while
1891 * in an interrupt or debug context.
1892 */
1893
1894static int serial8250_get_poll_char(struct uart_port *port)
1895{
1896 struct uart_8250_port *up = (struct uart_8250_port *)port;
1897 unsigned char lsr = serial_inp(up, UART_LSR);
1898
1899 while (!(lsr & UART_LSR_DR))
1900 lsr = serial_inp(up, UART_LSR);
1901
1902 return serial_inp(up, UART_RX);
1903}
1904
1905
1906static void serial8250_put_poll_char(struct uart_port *port,
1907 unsigned char c)
1908{
1909 unsigned int ier;
1910 struct uart_8250_port *up = (struct uart_8250_port *)port;
1911
1912 /*
1913 * First save the IER then disable the interrupts
1914 */
1915 ier = serial_in(up, UART_IER);
1916 if (up->capabilities & UART_CAP_UUE)
1917 serial_out(up, UART_IER, UART_IER_UUE);
1918 else
1919 serial_out(up, UART_IER, 0);
1920
1921 wait_for_xmitr(up, BOTH_EMPTY);
1922 /*
1923 * Send the character out.
1924 * If a LF, also do CR...
1925 */
1926 serial_out(up, UART_TX, c);
1927 if (c == 10) {
1928 wait_for_xmitr(up, BOTH_EMPTY);
1929 serial_out(up, UART_TX, 13);
1930 }
1931
1932 /*
1933 * Finally, wait for transmitter to become empty
1934 * and restore the IER
1935 */
1936 wait_for_xmitr(up, BOTH_EMPTY);
1937 serial_out(up, UART_IER, ier);
1938}
1939
1940#endif /* CONFIG_CONSOLE_POLL */
1941
1da177e4
LT		 1942static int serial8250_startup(struct uart_port *port)
1943{
1944 struct uart_8250_port *up = (struct uart_8250_port *)port;
1945 unsigned long flags;
55d3b282 1946 unsigned char lsr, iir;
1da177e4
LT		 1947 int retval;
1948
1949 up->capabilities = uart_config[up->port.type].flags;
1950 up->mcr = 0;
1951
b8e7e40a
AC		 1952 if (up->port.iotype != up->cur_iotype)
1953 set_io_from_upio(port);
1954
1da177e4
LT		 1955 if (up->port.type == PORT_16C950) {
1956 /* Wake up and initialize UART */
1957 up->acr = 0;
1958 serial_outp(up, UART_LCR, 0xBF);
1959 serial_outp(up, UART_EFR, UART_EFR_ECB);
1960 serial_outp(up, UART_IER, 0);
1961 serial_outp(up, UART_LCR, 0);
1962 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1963 serial_outp(up, UART_LCR, 0xBF);
1964 serial_outp(up, UART_EFR, UART_EFR_ECB);
1965 serial_outp(up, UART_LCR, 0);
1966 }
1967
1968#ifdef CONFIG_SERIAL_8250_RSA
1969 /*
1970 * If this is an RSA port, see if we can kick it up to the
1971 * higher speed clock.
1972 */
1973 enable_rsa(up);
1974#endif
1975
1976 /*
1977 * Clear the FIFO buffers and disable them.
7f927fcc 1978 * (they will be reenabled in set_termios())
1da177e4
LT		 1979 */
1980 serial8250_clear_fifos(up);
1981
1982 /*
1983 * Clear the interrupt registers.
1984 */
1985 (void) serial_inp(up, UART_LSR);
1986 (void) serial_inp(up, UART_RX);
1987 (void) serial_inp(up, UART_IIR);
1988 (void) serial_inp(up, UART_MSR);
1989
1990 /*
1991 * At this point, there's no way the LSR could still be 0xff;
1992 * if it is, then bail out, because there's likely no UART
1993 * here.
1994 */
1995 if (!(up->port.flags & UPF_BUGGY_UART) &&
1996 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1997 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1998 serial_index(&up->port));
1da177e4
LT		 1999 return -ENODEV;
2000 }
2001
2002 /*
2003 * For a XR16C850, we need to set the trigger levels
2004 */
2005 if (up->port.type == PORT_16850) {
2006 unsigned char fctr;
2007
2008 serial_outp(up, UART_LCR, 0xbf);
2009
2010 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2011 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2012 serial_outp(up, UART_TRG, UART_TRG_96);
2013 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2014 serial_outp(up, UART_TRG, UART_TRG_96);
2015
2016 serial_outp(up, UART_LCR, 0);
2017 }
2018
40b36daa 2019 if (is_real_interrupt(up->port.irq)) {
01c194d9 2020 unsigned char iir1;
40b36daa
AW		 2021 /*
2022 * Test for UARTs that do not reassert THRE when the
2023 * transmitter is idle and the interrupt has already
2024 * been cleared. Real 16550s should always reassert
2025 * this interrupt whenever the transmitter is idle and
2026 * the interrupt is enabled. Delays are necessary to
2027 * allow register changes to become visible.
2028 */
c389d27b 2029 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2030 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2031 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2032
2033 wait_for_xmitr(up, UART_LSR_THRE);
2034 serial_out_sync(up, UART_IER, UART_IER_THRI);
2035 udelay(1); /* allow THRE to set */
01c194d9 2036 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2037 serial_out(up, UART_IER, 0);
2038 serial_out_sync(up, UART_IER, UART_IER_THRI);
2039 udelay(1); /* allow a working UART time to re-assert THRE */
2040 iir = serial_in(up, UART_IIR);
2041 serial_out(up, UART_IER, 0);
2042
1c2f0493 2043 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2044 enable_irq(up->port.irq);
c389d27b 2045 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2046
2047 /*
2048 * If the interrupt is not reasserted, setup a timer to
2049 * kick the UART on a regular basis.
2050 */
01c194d9 2051 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2052 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2053 pr_debug("ttyS%d - using backup timer\n",
2054 serial_index(port));
40b36daa
AW		 2055 }
2056 }
2057
363f66fe
WN		 2058 /*
2059 * The above check will only give an accurate result the first time
2060 * the port is opened so this value needs to be preserved.
2061 */
2062 if (up->bugs & UART_BUG_THRE) {
2063 up->timer.function = serial8250_backup_timeout;
2064 up->timer.data = (unsigned long)up;
2065 mod_timer(&up->timer, jiffies +
2066 poll_timeout(up->port.timeout) + HZ / 5);
2067 }
2068
1da177e4
LT		 2069 /*
2070 * If the "interrupt" for this port doesn't correspond with any
2071 * hardware interrupt, we use a timer-based system. The original
2072 * driver used to do this with IRQ0.
2073 */
2074 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2075 up->timer.data = (unsigned long)up;
40b36daa 2076 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 2077 } else {
2078 retval = serial_link_irq_chain(up);
2079 if (retval)
2080 return retval;
2081 }
2082
2083 /*
2084 * Now, initialize the UART
2085 */
2086 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2087
2088 spin_lock_irqsave(&up->port.lock, flags);
2089 if (up->port.flags & UPF_FOURPORT) {
2090 if (!is_real_interrupt(up->port.irq))
2091 up->port.mctrl |= TIOCM_OUT1;
2092 } else
2093 /*
2094 * Most PC uarts need OUT2 raised to enable interrupts.
2095 */
2096 if (is_real_interrupt(up->port.irq))
2097 up->port.mctrl |= TIOCM_OUT2;
2098
2099 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2100
b6adea33
MCC		 2101 /* Serial over Lan (SoL) hack:
2102 Intel 8257x Gigabit ethernet chips have a
2103 16550 emulation, to be used for Serial Over Lan.
2104 Those chips take a longer time than a normal
2105 serial device to signalize that a transmission
2106 data was queued. Due to that, the above test generally
2107 fails. One solution would be to delay the reading of
2108 iir. However, this is not reliable, since the timeout
2109 is variable. So, let's just don't test if we receive
2110 TX irq. This way, we'll never enable UART_BUG_TXEN.
2111 */
d41a4b51 2112 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2113 goto dont_test_tx_en;
2114
55d3b282
RK		 2115 /*
2116 * Do a quick test to see if we receive an
2117 * interrupt when we enable the TX irq.
2118 */
2119 serial_outp(up, UART_IER, UART_IER_THRI);
2120 lsr = serial_in(up, UART_LSR);
2121 iir = serial_in(up, UART_IIR);
2122 serial_outp(up, UART_IER, 0);
2123
2124 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2125 if (!(up->bugs & UART_BUG_TXEN)) {
2126 up->bugs |= UART_BUG_TXEN;
55d3b282 2127 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2128 serial_index(port));
55d3b282
RK		 2129 }
2130 } else {
67f7654e 2131 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2132 }
2133
b6adea33 2134dont_test_tx_en:
1da177e4
LT		 2135 spin_unlock_irqrestore(&up->port.lock, flags);
2136
ad4c2aa6
CM		 2137 /*
2138 * Clear the interrupt registers again for luck, and clear the
2139 * saved flags to avoid getting false values from polling
2140 * routines or the previous session.
2141 */
2142 serial_inp(up, UART_LSR);
2143 serial_inp(up, UART_RX);
2144 serial_inp(up, UART_IIR);
2145 serial_inp(up, UART_MSR);
2146 up->lsr_saved_flags = 0;
2147 up->msr_saved_flags = 0;
2148
1da177e4
LT		 2149 /*
2150 * Finally, enable interrupts. Note: Modem status interrupts
2151 * are set via set_termios(), which will be occurring imminently
2152 * anyway, so we don't enable them here.
2153 */
2154 up->ier = UART_IER_RLSI | UART_IER_RDI;
2155 serial_outp(up, UART_IER, up->ier);
2156
2157 if (up->port.flags & UPF_FOURPORT) {
2158 unsigned int icp;
2159 /*
2160 * Enable interrupts on the AST Fourport board
2161 */
2162 icp = (up->port.iobase & 0xfe0) | 0x01f;
2163 outb_p(0x80, icp);
2164 (void) inb_p(icp);
2165 }
2166
1da177e4
LT		 2167 return 0;
2168}
2169
2170static void serial8250_shutdown(struct uart_port *port)
2171{
2172 struct uart_8250_port *up = (struct uart_8250_port *)port;
2173 unsigned long flags;
2174
2175 /*
2176 * Disable interrupts from this port
2177 */
2178 up->ier = 0;
2179 serial_outp(up, UART_IER, 0);
2180
2181 spin_lock_irqsave(&up->port.lock, flags);
2182 if (up->port.flags & UPF_FOURPORT) {
2183 /* reset interrupts on the AST Fourport board */
2184 inb((up->port.iobase & 0xfe0) | 0x1f);
2185 up->port.mctrl |= TIOCM_OUT1;
2186 } else
2187 up->port.mctrl &= ~TIOCM_OUT2;
2188
2189 serial8250_set_mctrl(&up->port, up->port.mctrl);
2190 spin_unlock_irqrestore(&up->port.lock, flags);
2191
2192 /*
2193 * Disable break condition and FIFOs
2194 */
2195 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2196 serial8250_clear_fifos(up);
2197
2198#ifdef CONFIG_SERIAL_8250_RSA
2199 /*
2200 * Reset the RSA board back to 115kbps compat mode.
2201 */
2202 disable_rsa(up);
2203#endif
2204
2205 /*
2206 * Read data port to reset things, and then unlink from
2207 * the IRQ chain.
2208 */
2209 (void) serial_in(up, UART_RX);
2210
40b36daa
AW		 2211 del_timer_sync(&up->timer);
2212 up->timer.function = serial8250_timeout;
2213 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2214 serial_unlink_irq_chain(up);
2215}
2216
2217static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2218{
2219 unsigned int quot;
2220
2221 /*
2222 * Handle magic divisors for baud rates above baud_base on
2223 * SMSC SuperIO chips.
2224 */
2225 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2226 baud == (port->uartclk/4))
2227 quot = 0x8001;
2228 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2229 baud == (port->uartclk/8))
2230 quot = 0x8002;
2231 else
2232 quot = uart_get_divisor(port, baud);
2233
2234 return quot;
2235}
2236
2237static void
606d099c
AC		 2238serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2239 struct ktermios *old)
1da177e4
LT		 2240{
2241 struct uart_8250_port *up = (struct uart_8250_port *)port;
2242 unsigned char cval, fcr = 0;
2243 unsigned long flags;
2244 unsigned int baud, quot;
2245
2246 switch (termios->c_cflag & CSIZE) {
2247 case CS5:
0a8b80c5 2248 cval = UART_LCR_WLEN5;
1da177e4
LT		 2249 break;
2250 case CS6:
0a8b80c5 2251 cval = UART_LCR_WLEN6;
1da177e4
LT		 2252 break;
2253 case CS7:
0a8b80c5 2254 cval = UART_LCR_WLEN7;
1da177e4
LT		 2255 break;
2256 default:
2257 case CS8:
0a8b80c5 2258 cval = UART_LCR_WLEN8;
1da177e4
LT		 2259 break;
2260 }
2261
2262 if (termios->c_cflag & CSTOPB)
0a8b80c5 2263 cval |= UART_LCR_STOP;
1da177e4
LT		 2264 if (termios->c_cflag & PARENB)
2265 cval |= UART_LCR_PARITY;
2266 if (!(termios->c_cflag & PARODD))
2267 cval |= UART_LCR_EPAR;
2268#ifdef CMSPAR
2269 if (termios->c_cflag & CMSPAR)
2270 cval |= UART_LCR_SPAR;
2271#endif
2272
2273 /*
2274 * Ask the core to calculate the divisor for us.
2275 */
24d481ec
AV		 2276 baud = uart_get_baud_rate(port, termios, old,
2277 port->uartclk / 16 / 0xffff,
2278 port->uartclk / 16);
1da177e4
LT		 2279 quot = serial8250_get_divisor(port, baud);
2280
2281 /*
4ba5e35d 2282 * Oxford Semi 952 rev B workaround
1da177e4 2283 */
4ba5e35d 2284 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2285 quot++;
1da177e4
LT		 2286
2287 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2288 if (baud < 2400)
2289 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2290 else
2291 fcr = uart_config[up->port.type].fcr;
2292 }
2293
2294 /*
2295 * MCR-based auto flow control. When AFE is enabled, RTS will be
2296 * deasserted when the receive FIFO contains more characters than
2297 * the trigger, or the MCR RTS bit is cleared. In the case where
2298 * the remote UART is not using CTS auto flow control, we must
2299 * have sufficient FIFO entries for the latency of the remote
2300 * UART to respond. IOW, at least 32 bytes of FIFO.
2301 */
2302 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2303 up->mcr &= ~UART_MCR_AFE;
2304 if (termios->c_cflag & CRTSCTS)
2305 up->mcr |= UART_MCR_AFE;
2306 }
2307
2308 /*
2309 * Ok, we're now changing the port state. Do it with
2310 * interrupts disabled.
2311 */
2312 spin_lock_irqsave(&up->port.lock, flags);
2313
2314 /*
2315 * Update the per-port timeout.
2316 */
2317 uart_update_timeout(port, termios->c_cflag, baud);
2318
2319 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2320 if (termios->c_iflag & INPCK)
2321 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2322 if (termios->c_iflag & (BRKINT | PARMRK))
2323 up->port.read_status_mask |= UART_LSR_BI;
2324
2325 /*
2326 * Characteres to ignore
2327 */
2328 up->port.ignore_status_mask = 0;
2329 if (termios->c_iflag & IGNPAR)
2330 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2331 if (termios->c_iflag & IGNBRK) {
2332 up->port.ignore_status_mask |= UART_LSR_BI;
2333 /*
2334 * If we're ignoring parity and break indicators,
2335 * ignore overruns too (for real raw support).
2336 */
2337 if (termios->c_iflag & IGNPAR)
2338 up->port.ignore_status_mask |= UART_LSR_OE;
2339 }
2340
2341 /*
2342 * ignore all characters if CREAD is not set
2343 */
2344 if ((termios->c_cflag & CREAD) == 0)
2345 up->port.ignore_status_mask |= UART_LSR_DR;
2346
2347 /*
2348 * CTS flow control flag and modem status interrupts
2349 */
2350 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2351 if (!(up->bugs & UART_BUG_NOMSR) &&
2352 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2353 up->ier |= UART_IER_MSI;
2354 if (up->capabilities & UART_CAP_UUE)
2355 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2356
2357 serial_out(up, UART_IER, up->ier);
2358
2359 if (up->capabilities & UART_CAP_EFR) {
2360 unsigned char efr = 0;
2361 /*
2362 * TI16C752/Startech hardware flow control. FIXME:
2363 * - TI16C752 requires control thresholds to be set.
2364 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2365 */
2366 if (termios->c_cflag & CRTSCTS)
2367 efr |= UART_EFR_CTS;
2368
2369 serial_outp(up, UART_LCR, 0xBF);
2370 serial_outp(up, UART_EFR, efr);
2371 }
2372
f2eda27d 2373#ifdef CONFIG_ARCH_OMAP
255341c6 2374 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2375 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2376 if (baud == 115200) {
2377 quot = 1;
2378 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2379 } else
2380 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2381 }
2382#endif
2383
1da177e4
LT		 2384 if (up->capabilities & UART_NATSEMI) {
2385 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2386 serial_outp(up, UART_LCR, 0xe0);
2387 } else {
2388 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2389 }
2390
b32b19b8 2391 serial_dl_write(up, quot);
1da177e4
LT		 2392
2393 /*
2394 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2395 * is written without DLAB set, this mode will be disabled.
2396 */
2397 if (up->port.type == PORT_16750)
2398 serial_outp(up, UART_FCR, fcr);
2399
2400 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2401 up->lcr = cval; /* Save LCR */
2402 if (up->port.type != PORT_16750) {
2403 if (fcr & UART_FCR_ENABLE_FIFO) {
2404 /* emulated UARTs (Lucent Venus 167x) need two steps */
2405 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2406 }
2407 serial_outp(up, UART_FCR, fcr); /* set fcr */
2408 }
2409 serial8250_set_mctrl(&up->port, up->port.mctrl);
2410 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2411 /* Don't rewrite B0 */
2412 if (tty_termios_baud_rate(termios))
2413 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2414}
2415
2416static void
2417serial8250_pm(struct uart_port *port, unsigned int state,
2418 unsigned int oldstate)
2419{
2420 struct uart_8250_port *p = (struct uart_8250_port *)port;
2421
2422 serial8250_set_sleep(p, state != 0);
2423
2424 if (p->pm)
2425 p->pm(port, state, oldstate);
2426}
2427
f2eda27d
RK		 2428static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2429{
2430 if (pt->port.iotype == UPIO_AU)
2431 return 0x100000;
2432#ifdef CONFIG_ARCH_OMAP
2433 if (is_omap_port(pt))
2434 return 0x16 << pt->port.regshift;
2435#endif
2436 return 8 << pt->port.regshift;
2437}
2438
1da177e4
LT		 2439/*
2440 * Resource handling.
2441 */
2442static int serial8250_request_std_resource(struct uart_8250_port *up)
2443{
f2eda27d 2444 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2445 int ret = 0;
2446
2447 switch (up->port.iotype) {
85835f44 2448 case UPIO_AU:
0b30d668
SS		 2449 case UPIO_TSI:
2450 case UPIO_MEM32:
1da177e4 2451 case UPIO_MEM:
beab697a 2452 case UPIO_DWAPB:
1da177e4
LT		 2453 if (!up->port.mapbase)
2454 break;
2455
2456 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2457 ret = -EBUSY;
2458 break;
2459 }
2460
2461 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2462 up->port.membase = ioremap_nocache(up->port.mapbase,
2463 size);
1da177e4
LT		 2464 if (!up->port.membase) {
2465 release_mem_region(up->port.mapbase, size);
2466 ret = -ENOMEM;
2467 }
2468 }
2469 break;
2470
2471 case UPIO_HUB6:
2472 case UPIO_PORT:
2473 if (!request_region(up->port.iobase, size, "serial"))
2474 ret = -EBUSY;
2475 break;
2476 }
2477 return ret;
2478}
2479
2480static void serial8250_release_std_resource(struct uart_8250_port *up)
2481{
f2eda27d 2482 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2483
2484 switch (up->port.iotype) {
85835f44 2485 case UPIO_AU:
0b30d668
SS		 2486 case UPIO_TSI:
2487 case UPIO_MEM32:
1da177e4 2488 case UPIO_MEM:
beab697a 2489 case UPIO_DWAPB:
1da177e4
LT		 2490 if (!up->port.mapbase)
2491 break;
2492
2493 if (up->port.flags & UPF_IOREMAP) {
2494 iounmap(up->port.membase);
2495 up->port.membase = NULL;
2496 }
2497
2498 release_mem_region(up->port.mapbase, size);
2499 break;
2500
2501 case UPIO_HUB6:
2502 case UPIO_PORT:
2503 release_region(up->port.iobase, size);
2504 break;
2505 }
2506}
2507
2508static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2509{
2510 unsigned long start = UART_RSA_BASE << up->port.regshift;
2511 unsigned int size = 8 << up->port.regshift;
0b30d668 2512 int ret = -EINVAL;
1da177e4
LT		 2513
2514 switch (up->port.iotype) {
1da177e4
LT		 2515 case UPIO_HUB6:
2516 case UPIO_PORT:
2517 start += up->port.iobase;
0b30d668
SS		 2518 if (request_region(start, size, "serial-rsa"))
2519 ret = 0;
2520 else
1da177e4
LT		 2521 ret = -EBUSY;
2522 break;
2523 }
2524
2525 return ret;
2526}
2527
2528static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2529{
2530 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2531 unsigned int size = 8 << up->port.regshift;
2532
2533 switch (up->port.iotype) {
1da177e4
LT		 2534 case UPIO_HUB6:
2535 case UPIO_PORT:
2536 release_region(up->port.iobase + offset, size);
2537 break;
2538 }
2539}
2540
2541static void serial8250_release_port(struct uart_port *port)
2542{
2543 struct uart_8250_port *up = (struct uart_8250_port *)port;
2544
2545 serial8250_release_std_resource(up);
2546 if (up->port.type == PORT_RSA)
2547 serial8250_release_rsa_resource(up);
2548}
2549
2550static int serial8250_request_port(struct uart_port *port)
2551{
2552 struct uart_8250_port *up = (struct uart_8250_port *)port;
2553 int ret = 0;
2554
2555 ret = serial8250_request_std_resource(up);
2556 if (ret == 0 && up->port.type == PORT_RSA) {
2557 ret = serial8250_request_rsa_resource(up);
2558 if (ret < 0)
2559 serial8250_release_std_resource(up);
2560 }
2561
2562 return ret;
2563}
2564
2565static void serial8250_config_port(struct uart_port *port, int flags)
2566{
2567 struct uart_8250_port *up = (struct uart_8250_port *)port;
2568 int probeflags = PROBE_ANY;
2569 int ret;
2570
1da177e4
LT		 2571 /*
2572 * Find the region that we can probe for. This in turn
2573 * tells us whether we can probe for the type of port.
2574 */
2575 ret = serial8250_request_std_resource(up);
2576 if (ret < 0)
2577 return;
2578
2579 ret = serial8250_request_rsa_resource(up);
2580 if (ret < 0)
2581 probeflags &= ~PROBE_RSA;
2582
b8e7e40a
AC		 2583 if (up->port.iotype != up->cur_iotype)
2584 set_io_from_upio(port);
2585
1da177e4
LT		 2586 if (flags & UART_CONFIG_TYPE)
2587 autoconfig(up, probeflags);
2588 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2589 autoconfig_irq(up);
2590
2591 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2592 serial8250_release_rsa_resource(up);
2593 if (up->port.type == PORT_UNKNOWN)
2594 serial8250_release_std_resource(up);
2595}
2596
2597static int
2598serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2599{
a62c4133 2600 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2601 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2602 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2603 ser->type == PORT_STARTECH)
2604 return -EINVAL;
2605 return 0;
2606}
2607
2608static const char *
2609serial8250_type(struct uart_port *port)
2610{
2611 int type = port->type;
2612
2613 if (type >= ARRAY_SIZE(uart_config))
2614 type = 0;
2615 return uart_config[type].name;
2616}
2617
2618static struct uart_ops serial8250_pops = {
2619 .tx_empty = serial8250_tx_empty,
2620 .set_mctrl = serial8250_set_mctrl,
2621 .get_mctrl = serial8250_get_mctrl,
2622 .stop_tx = serial8250_stop_tx,
2623 .start_tx = serial8250_start_tx,
2624 .stop_rx = serial8250_stop_rx,
2625 .enable_ms = serial8250_enable_ms,
2626 .break_ctl = serial8250_break_ctl,
2627 .startup = serial8250_startup,
2628 .shutdown = serial8250_shutdown,
2629 .set_termios = serial8250_set_termios,
2630 .pm = serial8250_pm,
2631 .type = serial8250_type,
2632 .release_port = serial8250_release_port,
2633 .request_port = serial8250_request_port,
2634 .config_port = serial8250_config_port,
2635 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2636#ifdef CONFIG_CONSOLE_POLL
2637 .poll_get_char = serial8250_get_poll_char,
2638 .poll_put_char = serial8250_put_poll_char,
2639#endif
1da177e4
LT		 2640};
2641
2642static struct uart_8250_port serial8250_ports[UART_NR];
2643
2644static void __init serial8250_isa_init_ports(void)
2645{
2646 struct uart_8250_port *up;
2647 static int first = 1;
4c0ebb80 2648 int i, irqflag = 0;
1da177e4
LT		 2649
2650 if (!first)
2651 return;
2652 first = 0;
2653
a61c2d78 2654 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2655 struct uart_8250_port *up = &serial8250_ports[i];
2656
2657 up->port.line = i;
2658 spin_lock_init(&up->port.lock);
2659
2660 init_timer(&up->timer);
2661 up->timer.function = serial8250_timeout;
2662
2663 /*
2664 * ALPHA_KLUDGE_MCR needs to be killed.
2665 */
2666 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2667 up->mcr_force = ALPHA_KLUDGE_MCR;
2668
2669 up->port.ops = &serial8250_pops;
2670 }
2671
4c0ebb80
AGR		 2672 if (share_irqs)
2673 irqflag = IRQF_SHARED;
2674
44454bcd 2675 for (i = 0, up = serial8250_ports;
a61c2d78 2676 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2677 i++, up++) {
2678 up->port.iobase = old_serial_port[i].port;
2679 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2680 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2681 up->port.uartclk = old_serial_port[i].baud_base * 16;
2682 up->port.flags = old_serial_port[i].flags;
2683 up->port.hub6 = old_serial_port[i].hub6;
2684 up->port.membase = old_serial_port[i].iomem_base;
2685 up->port.iotype = old_serial_port[i].io_type;
2686 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2687 set_io_from_upio(&up->port);
4c0ebb80 2688 up->port.irqflags |= irqflag;
1da177e4
LT		 2689 }
2690}
2691
2692static void __init
2693serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2694{
2695 int i;
2696
b8e7e40a
AC		 2697 for (i = 0; i < nr_uarts; i++) {
2698 struct uart_8250_port *up = &serial8250_ports[i];
2699 up->cur_iotype = 0xFF;
2700 }
2701
1da177e4
LT		 2702 serial8250_isa_init_ports();
2703
a61c2d78 2704 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2705 struct uart_8250_port *up = &serial8250_ports[i];
2706
2707 up->port.dev = dev;
2708 uart_add_one_port(drv, &up->port);
2709 }
2710}
2711
2712#ifdef CONFIG_SERIAL_8250_CONSOLE
2713
d358788f
RK		 2714static void serial8250_console_putchar(struct uart_port *port, int ch)
2715{
2716 struct uart_8250_port *up = (struct uart_8250_port *)port;
2717
2718 wait_for_xmitr(up, UART_LSR_THRE);
2719 serial_out(up, UART_TX, ch);
2720}
2721
1da177e4
LT		 2722/*
2723 * Print a string to the serial port trying not to disturb
2724 * any possible real use of the port...
2725 *
2726 * The console_lock must be held when we get here.
2727 */
2728static void
2729serial8250_console_write(struct console *co, const char *s, unsigned int count)
2730{
2731 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2732 unsigned long flags;
1da177e4 2733 unsigned int ier;
d8a5a8d7 2734 int locked = 1;
1da177e4 2735
78512ece
AM		 2736 touch_nmi_watchdog();
2737
68aa2c0d
AM		 2738 local_irq_save(flags);
2739 if (up->port.sysrq) {
2740 /* serial8250_handle_port() already took the lock */
2741 locked = 0;
2742 } else if (oops_in_progress) {
2743 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2744 } else
68aa2c0d 2745 spin_lock(&up->port.lock);
d8a5a8d7 2746
1da177e4 2747 /*
dc7bf130 2748 * First save the IER then disable the interrupts
1da177e4
LT		 2749 */
2750 ier = serial_in(up, UART_IER);
2751
2752 if (up->capabilities & UART_CAP_UUE)
2753 serial_out(up, UART_IER, UART_IER_UUE);
2754 else
2755 serial_out(up, UART_IER, 0);
2756
d358788f 2757 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2758
2759 /*
2760 * Finally, wait for transmitter to become empty
2761 * and restore the IER
2762 */
f91a3715 2763 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2764 serial_out(up, UART_IER, ier);
d8a5a8d7 2765
ad4c2aa6
CM		 2766 /*
2767 * The receive handling will happen properly because the
2768 * receive ready bit will still be set; it is not cleared
2769 * on read. However, modem control will not, we must
2770 * call it if we have saved something in the saved flags
2771 * while processing with interrupts off.
2772 */
2773 if (up->msr_saved_flags)
2774 check_modem_status(up);
2775
d8a5a8d7 2776 if (locked)
68aa2c0d
AM		 2777 spin_unlock(&up->port.lock);
2778 local_irq_restore(flags);
1da177e4
LT		 2779}
2780
118c0ace 2781static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2782{
2783 struct uart_port *port;
2784 int baud = 9600;
2785 int bits = 8;
2786 int parity = 'n';
2787 int flow = 'n';
2788
2789 /*
2790 * Check whether an invalid uart number has been specified, and
2791 * if so, search for the first available port that does have
2792 * console support.
2793 */
a61c2d78 2794 if (co->index >= nr_uarts)
1da177e4
LT		 2795 co->index = 0;
2796 port = &serial8250_ports[co->index].port;
2797 if (!port->iobase && !port->membase)
2798 return -ENODEV;
2799
2800 if (options)
2801 uart_parse_options(options, &baud, &parity, &bits, &flow);
2802
2803 return uart_set_options(port, co, baud, parity, bits, flow);
2804}
2805
b6b1d877 2806static int serial8250_console_early_setup(void)
18a8bd94
YL		 2807{
2808 return serial8250_find_port_for_earlycon();
2809}
2810
1da177e4
LT		 2811static struct console serial8250_console = {
2812 .name = "ttyS",
2813 .write = serial8250_console_write,
2814 .device = uart_console_device,
2815 .setup = serial8250_console_setup,
18a8bd94 2816 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2817 .flags = CON_PRINTBUFFER,
2818 .index = -1,
2819 .data = &serial8250_reg,
2820};
2821
2822static int __init serial8250_console_init(void)
2823{
05d81d22
EB		 2824 if (nr_uarts > UART_NR)
2825 nr_uarts = UART_NR;
2826
1da177e4
LT		 2827 serial8250_isa_init_ports();
2828 register_console(&serial8250_console);
2829 return 0;
2830}
2831console_initcall(serial8250_console_init);
2832
18a8bd94 2833int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2834{
2835 int line;
2836 struct uart_port *port;
2837
a61c2d78 2838 for (line = 0; line < nr_uarts; line++) {
1da177e4 2839 port = &serial8250_ports[line].port;
50aec3b5 2840 if (uart_match_port(p, port))
1da177e4
LT		 2841 return line;
2842 }
2843 return -ENODEV;
2844}
2845
1da177e4
LT		 2846#define SERIAL8250_CONSOLE &serial8250_console
2847#else
2848#define SERIAL8250_CONSOLE NULL
2849#endif
2850
2851static struct uart_driver serial8250_reg = {
2852 .owner = THIS_MODULE,
2853 .driver_name = "serial",
1da177e4
LT		 2854 .dev_name = "ttyS",
2855 .major = TTY_MAJOR,
2856 .minor = 64,
1da177e4
LT		 2857 .cons = SERIAL8250_CONSOLE,
2858};
2859
d856c666
RK		 2860/*
2861 * early_serial_setup - early registration for 8250 ports
2862 *
2863 * Setup an 8250 port structure prior to console initialisation. Use
2864 * after console initialisation will cause undefined behaviour.
2865 */
1da177e4
LT		 2866int __init early_serial_setup(struct uart_port *port)
2867{
b430428a
DD		 2868 struct uart_port *p;
2869
1da177e4
LT		 2870 if (port->line >= ARRAY_SIZE(serial8250_ports))
2871 return -ENODEV;
2872
2873 serial8250_isa_init_ports();
b430428a
DD		 2874 p = &serial8250_ports[port->line].port;
2875 p->iobase = port->iobase;
2876 p->membase = port->membase;
2877 p->irq = port->irq;
1c2f0493 2878 p->irqflags = port->irqflags;
b430428a
DD		 2879 p->uartclk = port->uartclk;
2880 p->fifosize = port->fifosize;
2881 p->regshift = port->regshift;
2882 p->iotype = port->iotype;
2883 p->flags = port->flags;
2884 p->mapbase = port->mapbase;
2885 p->private_data = port->private_data;
125c97d8
HD		 2886 p->type = port->type;
2887 p->line = port->line;
7d6a07d1
DD		 2888
2889 set_io_from_upio(p);
2890 if (port->serial_in)
2891 p->serial_in = port->serial_in;
2892 if (port->serial_out)
2893 p->serial_out = port->serial_out;
2894
1da177e4
LT		 2895 return 0;
2896}
2897
2898/**
2899 * serial8250_suspend_port - suspend one serial port
2900 * @line: serial line number
1da177e4
LT		 2901 *
2902 * Suspend one serial port.
2903 */
2904void serial8250_suspend_port(int line)
2905{
2906 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2907}
2908
2909/**
2910 * serial8250_resume_port - resume one serial port
2911 * @line: serial line number
1da177e4
LT		 2912 *
2913 * Resume one serial port.
2914 */
2915void serial8250_resume_port(int line)
2916{
b5b82df6
DW		 2917 struct uart_8250_port *up = &serial8250_ports[line];
2918
2919 if (up->capabilities & UART_NATSEMI) {
2920 unsigned char tmp;
2921
2922 /* Ensure it's still in high speed mode */
2923 serial_outp(up, UART_LCR, 0xE0);
2924
2925 tmp = serial_in(up, 0x04); /* EXCR2 */
2926 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2927 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2928 serial_outp(up, 0x04, tmp);
2929
2930 serial_outp(up, UART_LCR, 0);
2931 }
2932 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2933}
2934
2935/*
2936 * Register a set of serial devices attached to a platform device. The
2937 * list is terminated with a zero flags entry, which means we expect
2938 * all entries to have at least UPF_BOOT_AUTOCONF set.
2939 */
3ae5eaec 2940static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2941{
3ae5eaec 2942 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2943 struct uart_port port;
4c0ebb80 2944 int ret, i, irqflag = 0;
1da177e4
LT		 2945
2946 memset(&port, 0, sizeof(struct uart_port));
2947
4c0ebb80
AGR		 2948 if (share_irqs)
2949 irqflag = IRQF_SHARED;
2950
ec9f47cd 2951 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2952 port.iobase = p->iobase;
2953 port.membase = p->membase;
2954 port.irq = p->irq;
1c2f0493 2955 port.irqflags = p->irqflags;
74a19741
WN		 2956 port.uartclk = p->uartclk;
2957 port.regshift = p->regshift;
2958 port.iotype = p->iotype;
2959 port.flags = p->flags;
2960 port.mapbase = p->mapbase;
2961 port.hub6 = p->hub6;
2962 port.private_data = p->private_data;
8e23fcc8 2963 port.type = p->type;
7d6a07d1
DD		 2964 port.serial_in = p->serial_in;
2965 port.serial_out = p->serial_out;
74a19741 2966 port.dev = &dev->dev;
4c0ebb80 2967 port.irqflags |= irqflag;
ec9f47cd
RK		 2968 ret = serial8250_register_port(&port);
2969 if (ret < 0) {
3ae5eaec 2970 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2971 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2972 p->iobase, (unsigned long long)p->mapbase,
2973 p->irq, ret);
ec9f47cd 2974 }
1da177e4
LT		 2975 }
2976 return 0;
2977}
2978
2979/*
2980 * Remove serial ports registered against a platform device.
2981 */
3ae5eaec 2982static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2983{
2984 int i;
2985
a61c2d78 2986 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2987 struct uart_8250_port *up = &serial8250_ports[i];
2988
3ae5eaec 2989 if (up->port.dev == &dev->dev)
1da177e4
LT		 2990 serial8250_unregister_port(i);
2991 }
2992 return 0;
2993}
2994
3ae5eaec 2995static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2996{
2997 int i;
2998
1da177e4
LT		 2999 for (i = 0; i < UART_NR; i++) {
3000 struct uart_8250_port *up = &serial8250_ports[i];
3001
3ae5eaec 3002 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3003 uart_suspend_port(&serial8250_reg, &up->port);
3004 }
3005
3006 return 0;
3007}
3008
3ae5eaec 3009static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3010{
3011 int i;
3012
1da177e4
LT		 3013 for (i = 0; i < UART_NR; i++) {
3014 struct uart_8250_port *up = &serial8250_ports[i];
3015
3ae5eaec 3016 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3017 serial8250_resume_port(i);
1da177e4
LT		 3018 }
3019
3020 return 0;
3021}
3022
3ae5eaec 3023static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3024 .probe = serial8250_probe,
3025 .remove = __devexit_p(serial8250_remove),
3026 .suspend = serial8250_suspend,
3027 .resume = serial8250_resume,
3ae5eaec
RK		 3028 .driver = {
3029 .name = "serial8250",
7493a314 3030 .owner = THIS_MODULE,
3ae5eaec 3031 },
1da177e4
LT		 3032};
3033
3034/*
3035 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3036 * in the table in include/asm/serial.h
3037 */
3038static struct platform_device *serial8250_isa_devs;
3039
3040/*
3041 * serial8250_register_port and serial8250_unregister_port allows for
3042 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3043 * modems and PCI multiport cards.
3044 */
f392ecfa 3045static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3046
3047static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3048{
3049 int i;
3050
3051 /*
3052 * First, find a port entry which matches.
3053 */
a61c2d78 3054 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3055 if (uart_match_port(&serial8250_ports[i].port, port))
3056 return &serial8250_ports[i];
3057
3058 /*
3059 * We didn't find a matching entry, so look for the first
3060 * free entry. We look for one which hasn't been previously
3061 * used (indicated by zero iobase).
3062 */
a61c2d78 3063 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3064 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3065 serial8250_ports[i].port.iobase == 0)
3066 return &serial8250_ports[i];
3067
3068 /*
3069 * That also failed. Last resort is to find any entry which
3070 * doesn't have a real port associated with it.
3071 */
a61c2d78 3072 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3073 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3074 return &serial8250_ports[i];
3075
3076 return NULL;
3077}
3078
3079/**
3080 * serial8250_register_port - register a serial port
3081 * @port: serial port template
3082 *
3083 * Configure the serial port specified by the request. If the
3084 * port exists and is in use, it is hung up and unregistered
3085 * first.
3086 *
3087 * The port is then probed and if necessary the IRQ is autodetected
3088 * If this fails an error is returned.
3089 *
3090 * On success the port is ready to use and the line number is returned.
3091 */
3092int serial8250_register_port(struct uart_port *port)
3093{
3094 struct uart_8250_port *uart;
3095 int ret = -ENOSPC;
3096
3097 if (port->uartclk == 0)
3098 return -EINVAL;
3099
f392ecfa 3100 mutex_lock(&serial_mutex);
1da177e4
LT		 3101
3102 uart = serial8250_find_match_or_unused(port);
3103 if (uart) {
3104 uart_remove_one_port(&serial8250_reg, &uart->port);
3105
74a19741
WN		 3106 uart->port.iobase = port->iobase;
3107 uart->port.membase = port->membase;
3108 uart->port.irq = port->irq;
1c2f0493 3109 uart->port.irqflags = port->irqflags;
74a19741
WN		 3110 uart->port.uartclk = port->uartclk;
3111 uart->port.fifosize = port->fifosize;
3112 uart->port.regshift = port->regshift;
3113 uart->port.iotype = port->iotype;
3114 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3115 uart->port.mapbase = port->mapbase;
3116 uart->port.private_data = port->private_data;
1da177e4
LT		 3117 if (port->dev)
3118 uart->port.dev = port->dev;
8e23fcc8
DD		 3119
3120 if (port->flags & UPF_FIXED_TYPE) {
3121 uart->port.type = port->type;
3122 uart->port.fifosize = uart_config[port->type].fifo_size;
3123 uart->capabilities = uart_config[port->type].flags;
3124 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3125 }
3126
7d6a07d1
DD		 3127 set_io_from_upio(&uart->port);
3128 /* Possibly override default I/O functions. */
3129 if (port->serial_in)
3130 uart->port.serial_in = port->serial_in;
3131 if (port->serial_out)
3132 uart->port.serial_out = port->serial_out;
1da177e4
LT		 3133
3134 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3135 if (ret == 0)
3136 ret = uart->port.line;
3137 }
f392ecfa 3138 mutex_unlock(&serial_mutex);
1da177e4
LT		 3139
3140 return ret;
3141}
3142EXPORT_SYMBOL(serial8250_register_port);
3143
3144/**
3145 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3146 * @line: serial line number
3147 *
3148 * Remove one serial port. This may not be called from interrupt
3149 * context. We hand the port back to the our control.
3150 */
3151void serial8250_unregister_port(int line)
3152{
3153 struct uart_8250_port *uart = &serial8250_ports[line];
3154
f392ecfa 3155 mutex_lock(&serial_mutex);
1da177e4
LT		 3156 uart_remove_one_port(&serial8250_reg, &uart->port);
3157 if (serial8250_isa_devs) {
3158 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3159 uart->port.type = PORT_UNKNOWN;
3160 uart->port.dev = &serial8250_isa_devs->dev;
3161 uart_add_one_port(&serial8250_reg, &uart->port);
3162 } else {
3163 uart->port.dev = NULL;
3164 }
f392ecfa 3165 mutex_unlock(&serial_mutex);
1da177e4
LT		 3166}
3167EXPORT_SYMBOL(serial8250_unregister_port);
3168
3169static int __init serial8250_init(void)
3170{
25db8ad5 3171 int ret;
1da177e4 3172
a61c2d78
DJ		 3173 if (nr_uarts > UART_NR)
3174 nr_uarts = UART_NR;
3175
f1fb9bb8 3176 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3177 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3178 share_irqs ? "en" : "dis");
3179
b70ac771
DM		 3180#ifdef CONFIG_SPARC
3181 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3182#else
3183 serial8250_reg.nr = UART_NR;
1da177e4 3184 ret = uart_register_driver(&serial8250_reg);
b70ac771 3185#endif
1da177e4
LT		 3186 if (ret)
3187 goto out;
3188
7493a314
DT		 3189 serial8250_isa_devs = platform_device_alloc("serial8250",
3190 PLAT8250_DEV_LEGACY);
3191 if (!serial8250_isa_devs) {
3192 ret = -ENOMEM;
bc965a7f 3193 goto unreg_uart_drv;
1da177e4
LT		 3194 }
3195
7493a314
DT		 3196 ret = platform_device_add(serial8250_isa_devs);
3197 if (ret)
3198 goto put_dev;
3199
1da177e4
LT		 3200 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3201
bc965a7f
RK		 3202 ret = platform_driver_register(&serial8250_isa_driver);
3203 if (ret == 0)
3204 goto out;
1da177e4 3205
bc965a7f 3206 platform_device_del(serial8250_isa_devs);
25db8ad5 3207put_dev:
7493a314 3208 platform_device_put(serial8250_isa_devs);
25db8ad5 3209unreg_uart_drv:
b70ac771
DM		 3210#ifdef CONFIG_SPARC
3211 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3212#else
1da177e4 3213 uart_unregister_driver(&serial8250_reg);
b70ac771 3214#endif
25db8ad5 3215out:
1da177e4
LT		 3216 return ret;
3217}
3218
3219static void __exit serial8250_exit(void)
3220{
3221 struct platform_device *isa_dev = serial8250_isa_devs;
3222
3223 /*
3224 * This tells serial8250_unregister_port() not to re-register
3225 * the ports (thereby making serial8250_isa_driver permanently
3226 * in use.)
3227 */
3228 serial8250_isa_devs = NULL;
3229
3ae5eaec 3230 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3231 platform_device_unregister(isa_dev);
3232
b70ac771
DM		 3233#ifdef CONFIG_SPARC
3234 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3235#else
1da177e4 3236 uart_unregister_driver(&serial8250_reg);
b70ac771 3237#endif
1da177e4
LT		 3238}
3239
3240module_init(serial8250_init);
3241module_exit(serial8250_exit);
3242
3243EXPORT_SYMBOL(serial8250_suspend_port);
3244EXPORT_SYMBOL(serial8250_resume_port);
3245
3246MODULE_LICENSE("GPL");
d87a6d95 3247MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3248
3249module_param(share_irqs, uint, 0644);
3250MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3251 " (unsafe)");
3252
a61c2d78
DJ		 3253module_param(nr_uarts, uint, 0644);
3254MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3255
d41a4b51
CE		 3256module_param(skip_txen_test, uint, 0644);
3257MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3258
1da177e4
LT		 3259#ifdef CONFIG_SERIAL_8250_RSA
3260module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3261MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3262#endif
3263MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux 6.x block layer and io_uring tree(s)