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[PATCH] Serial: Split 8250 port table (part 2)
[linux-2.6-block.git] / drivers / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
1da177e4
LT		 80#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
81#define CONFIG_SERIAL_DETECT_IRQ 1
82#endif
1da177e4
LT		 83#ifdef CONFIG_SERIAL_8250_MANY_PORTS
84#define CONFIG_SERIAL_MANY_PORTS 1
85#endif
86
87/*
88 * HUB6 is always on. This will be removed once the header
89 * files have been cleaned.
90 */
91#define CONFIG_HUB6 1
92
93#include <asm/serial.h>
94
95/*
96 * SERIAL_PORT_DFNS tells us about built-in ports that have no
97 * standard enumeration mechanism. Platforms that can find all
98 * serial ports via mechanisms like ACPI or PCI need not supply it.
99 */
100#ifndef SERIAL_PORT_DFNS
101#define SERIAL_PORT_DFNS
102#endif
103
104static struct old_serial_port old_serial_port[] = {
105 SERIAL_PORT_DFNS /* defined in asm/serial.h */
106};
107
026d02a2 108#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 109
110#ifdef CONFIG_SERIAL_8250_RSA
111
112#define PORT_RSA_MAX 4
113static unsigned long probe_rsa[PORT_RSA_MAX];
114static unsigned int probe_rsa_count;
115#endif /* CONFIG_SERIAL_8250_RSA */
116
117struct uart_8250_port {
118 struct uart_port port;
119 struct timer_list timer; /* "no irq" timer */
120 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 121 unsigned short capabilities; /* port capabilities */
122 unsigned short bugs; /* port bugs */
1da177e4 123 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 124 unsigned char acr;
125 unsigned char ier;
126 unsigned char lcr;
127 unsigned char mcr;
128 unsigned char mcr_mask; /* mask of user bits */
129 unsigned char mcr_force; /* mask of forced bits */
130 unsigned char lsr_break_flag;
131
132 /*
133 * We provide a per-port pm hook.
134 */
135 void (*pm)(struct uart_port *port,
136 unsigned int state, unsigned int old);
137};
138
139struct irq_info {
140 spinlock_t lock;
141 struct list_head *head;
142};
143
144static struct irq_info irq_lists[NR_IRQS];
145
146/*
147 * Here we define the default xmit fifo size used for each type of UART.
148 */
149static const struct serial8250_config uart_config[] = {
150 [PORT_UNKNOWN] = {
151 .name = "unknown",
152 .fifo_size = 1,
153 .tx_loadsz = 1,
154 },
155 [PORT_8250] = {
156 .name = "8250",
157 .fifo_size = 1,
158 .tx_loadsz = 1,
159 },
160 [PORT_16450] = {
161 .name = "16450",
162 .fifo_size = 1,
163 .tx_loadsz = 1,
164 },
165 [PORT_16550] = {
166 .name = "16550",
167 .fifo_size = 1,
168 .tx_loadsz = 1,
169 },
170 [PORT_16550A] = {
171 .name = "16550A",
172 .fifo_size = 16,
173 .tx_loadsz = 16,
174 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 .flags = UART_CAP_FIFO,
176 },
177 [PORT_CIRRUS] = {
178 .name = "Cirrus",
179 .fifo_size = 1,
180 .tx_loadsz = 1,
181 },
182 [PORT_16650] = {
183 .name = "ST16650",
184 .fifo_size = 1,
185 .tx_loadsz = 1,
186 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
187 },
188 [PORT_16650V2] = {
189 .name = "ST16650V2",
190 .fifo_size = 32,
191 .tx_loadsz = 16,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 UART_FCR_T_TRIG_00,
194 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
195 },
196 [PORT_16750] = {
197 .name = "TI16750",
198 .fifo_size = 64,
199 .tx_loadsz = 64,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
201 UART_FCR7_64BYTE,
202 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
203 },
204 [PORT_STARTECH] = {
205 .name = "Startech",
206 .fifo_size = 1,
207 .tx_loadsz = 1,
208 },
209 [PORT_16C950] = {
210 .name = "16C950/954",
211 .fifo_size = 128,
212 .tx_loadsz = 128,
213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
214 .flags = UART_CAP_FIFO,
215 },
216 [PORT_16654] = {
217 .name = "ST16654",
218 .fifo_size = 64,
219 .tx_loadsz = 32,
220 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
221 UART_FCR_T_TRIG_10,
222 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 },
224 [PORT_16850] = {
225 .name = "XR16850",
226 .fifo_size = 128,
227 .tx_loadsz = 128,
228 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
229 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
230 },
231 [PORT_RSA] = {
232 .name = "RSA",
233 .fifo_size = 2048,
234 .tx_loadsz = 2048,
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
236 .flags = UART_CAP_FIFO,
237 },
238 [PORT_NS16550A] = {
239 .name = "NS16550A",
240 .fifo_size = 16,
241 .tx_loadsz = 16,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_NATSEMI,
244 },
245 [PORT_XSCALE] = {
246 .name = "XScale",
247 .fifo_size = 32,
248 .tx_loadsz = 32,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .flags = UART_CAP_FIFO | UART_CAP_UUE,
251 },
252};
253
254static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
255{
256 offset <<= up->port.regshift;
257
258 switch (up->port.iotype) {
259 case UPIO_HUB6:
260 outb(up->port.hub6 - 1 + offset, up->port.iobase);
261 return inb(up->port.iobase + 1);
262
263 case UPIO_MEM:
264 return readb(up->port.membase + offset);
265
266 case UPIO_MEM32:
267 return readl(up->port.membase + offset);
268
269 default:
270 return inb(up->port.iobase + offset);
271 }
272}
273
274static _INLINE_ void
275serial_out(struct uart_8250_port *up, int offset, int value)
276{
277 offset <<= up->port.regshift;
278
279 switch (up->port.iotype) {
280 case UPIO_HUB6:
281 outb(up->port.hub6 - 1 + offset, up->port.iobase);
282 outb(value, up->port.iobase + 1);
283 break;
284
285 case UPIO_MEM:
286 writeb(value, up->port.membase + offset);
287 break;
288
289 case UPIO_MEM32:
290 writel(value, up->port.membase + offset);
291 break;
292
293 default:
294 outb(value, up->port.iobase + offset);
295 }
296}
297
298/*
299 * We used to support using pause I/O for certain machines. We
300 * haven't supported this for a while, but just in case it's badly
301 * needed for certain old 386 machines, I've left these #define's
302 * in....
303 */
304#define serial_inp(up, offset) serial_in(up, offset)
305#define serial_outp(up, offset, value) serial_out(up, offset, value)
306
307
308/*
309 * For the 16C950
310 */
311static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
312{
313 serial_out(up, UART_SCR, offset);
314 serial_out(up, UART_ICR, value);
315}
316
317static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
318{
319 unsigned int value;
320
321 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
322 serial_out(up, UART_SCR, offset);
323 value = serial_in(up, UART_ICR);
324 serial_icr_write(up, UART_ACR, up->acr);
325
326 return value;
327}
328
329/*
330 * FIFO support.
331 */
332static inline void serial8250_clear_fifos(struct uart_8250_port *p)
333{
334 if (p->capabilities & UART_CAP_FIFO) {
335 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
336 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
337 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
338 serial_outp(p, UART_FCR, 0);
339 }
340}
341
342/*
343 * IER sleep support. UARTs which have EFRs need the "extended
344 * capability" bit enabled. Note that on XR16C850s, we need to
345 * reset LCR to write to IER.
346 */
347static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
348{
349 if (p->capabilities & UART_CAP_SLEEP) {
350 if (p->capabilities & UART_CAP_EFR) {
351 serial_outp(p, UART_LCR, 0xBF);
352 serial_outp(p, UART_EFR, UART_EFR_ECB);
353 serial_outp(p, UART_LCR, 0);
354 }
355 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
356 if (p->capabilities & UART_CAP_EFR) {
357 serial_outp(p, UART_LCR, 0xBF);
358 serial_outp(p, UART_EFR, 0);
359 serial_outp(p, UART_LCR, 0);
360 }
361 }
362}
363
364#ifdef CONFIG_SERIAL_8250_RSA
365/*
366 * Attempts to turn on the RSA FIFO. Returns zero on failure.
367 * We set the port uart clock rate if we succeed.
368 */
369static int __enable_rsa(struct uart_8250_port *up)
370{
371 unsigned char mode;
372 int result;
373
374 mode = serial_inp(up, UART_RSA_MSR);
375 result = mode & UART_RSA_MSR_FIFO;
376
377 if (!result) {
378 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
379 mode = serial_inp(up, UART_RSA_MSR);
380 result = mode & UART_RSA_MSR_FIFO;
381 }
382
383 if (result)
384 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
385
386 return result;
387}
388
389static void enable_rsa(struct uart_8250_port *up)
390{
391 if (up->port.type == PORT_RSA) {
392 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
393 spin_lock_irq(&up->port.lock);
394 __enable_rsa(up);
395 spin_unlock_irq(&up->port.lock);
396 }
397 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
398 serial_outp(up, UART_RSA_FRR, 0);
399 }
400}
401
402/*
403 * Attempts to turn off the RSA FIFO. Returns zero on failure.
404 * It is unknown why interrupts were disabled in here. However,
405 * the caller is expected to preserve this behaviour by grabbing
406 * the spinlock before calling this function.
407 */
408static void disable_rsa(struct uart_8250_port *up)
409{
410 unsigned char mode;
411 int result;
412
413 if (up->port.type == PORT_RSA &&
414 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
415 spin_lock_irq(&up->port.lock);
416
417 mode = serial_inp(up, UART_RSA_MSR);
418 result = !(mode & UART_RSA_MSR_FIFO);
419
420 if (!result) {
421 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
422 mode = serial_inp(up, UART_RSA_MSR);
423 result = !(mode & UART_RSA_MSR_FIFO);
424 }
425
426 if (result)
427 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
428 spin_unlock_irq(&up->port.lock);
429 }
430}
431#endif /* CONFIG_SERIAL_8250_RSA */
432
433/*
434 * This is a quickie test to see how big the FIFO is.
435 * It doesn't work at all the time, more's the pity.
436 */
437static int size_fifo(struct uart_8250_port *up)
438{
439 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
440 int count;
441
442 old_lcr = serial_inp(up, UART_LCR);
443 serial_outp(up, UART_LCR, 0);
444 old_fcr = serial_inp(up, UART_FCR);
445 old_mcr = serial_inp(up, UART_MCR);
446 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
447 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
448 serial_outp(up, UART_MCR, UART_MCR_LOOP);
449 serial_outp(up, UART_LCR, UART_LCR_DLAB);
450 old_dll = serial_inp(up, UART_DLL);
451 old_dlm = serial_inp(up, UART_DLM);
452 serial_outp(up, UART_DLL, 0x01);
453 serial_outp(up, UART_DLM, 0x00);
454 serial_outp(up, UART_LCR, 0x03);
455 for (count = 0; count < 256; count++)
456 serial_outp(up, UART_TX, count);
457 mdelay(20);/* FIXME - schedule_timeout */
458 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
459 (count < 256); count++)
460 serial_inp(up, UART_RX);
461 serial_outp(up, UART_FCR, old_fcr);
462 serial_outp(up, UART_MCR, old_mcr);
463 serial_outp(up, UART_LCR, UART_LCR_DLAB);
464 serial_outp(up, UART_DLL, old_dll);
465 serial_outp(up, UART_DLM, old_dlm);
466 serial_outp(up, UART_LCR, old_lcr);
467
468 return count;
469}
470
471/*
472 * Read UART ID using the divisor method - set DLL and DLM to zero
473 * and the revision will be in DLL and device type in DLM. We
474 * preserve the device state across this.
475 */
476static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
477{
478 unsigned char old_dll, old_dlm, old_lcr;
479 unsigned int id;
480
481 old_lcr = serial_inp(p, UART_LCR);
482 serial_outp(p, UART_LCR, UART_LCR_DLAB);
483
484 old_dll = serial_inp(p, UART_DLL);
485 old_dlm = serial_inp(p, UART_DLM);
486
487 serial_outp(p, UART_DLL, 0);
488 serial_outp(p, UART_DLM, 0);
489
490 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
491
492 serial_outp(p, UART_DLL, old_dll);
493 serial_outp(p, UART_DLM, old_dlm);
494 serial_outp(p, UART_LCR, old_lcr);
495
496 return id;
497}
498
499/*
500 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
501 * When this function is called we know it is at least a StarTech
502 * 16650 V2, but it might be one of several StarTech UARTs, or one of
503 * its clones. (We treat the broken original StarTech 16650 V1 as a
504 * 16550, and why not? Startech doesn't seem to even acknowledge its
505 * existence.)
506 *
507 * What evil have men's minds wrought...
508 */
509static void autoconfig_has_efr(struct uart_8250_port *up)
510{
511 unsigned int id1, id2, id3, rev;
512
513 /*
514 * Everything with an EFR has SLEEP
515 */
516 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
517
518 /*
519 * First we check to see if it's an Oxford Semiconductor UART.
520 *
521 * If we have to do this here because some non-National
522 * Semiconductor clone chips lock up if you try writing to the
523 * LSR register (which serial_icr_read does)
524 */
525
526 /*
527 * Check for Oxford Semiconductor 16C950.
528 *
529 * EFR [4] must be set else this test fails.
530 *
531 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
532 * claims that it's needed for 952 dual UART's (which are not
533 * recommended for new designs).
534 */
535 up->acr = 0;
536 serial_out(up, UART_LCR, 0xBF);
537 serial_out(up, UART_EFR, UART_EFR_ECB);
538 serial_out(up, UART_LCR, 0x00);
539 id1 = serial_icr_read(up, UART_ID1);
540 id2 = serial_icr_read(up, UART_ID2);
541 id3 = serial_icr_read(up, UART_ID3);
542 rev = serial_icr_read(up, UART_REV);
543
544 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
545
546 if (id1 == 0x16 && id2 == 0xC9 &&
547 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
548 up->port.type = PORT_16C950;
4ba5e35d
RK		 549
550 /*
551 * Enable work around for the Oxford Semiconductor 952 rev B
552 * chip which causes it to seriously miscalculate baud rates
553 * when DLL is 0.
554 */
555 if (id3 == 0x52 && rev == 0x01)
556 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 557 return;
558 }
559
560 /*
561 * We check for a XR16C850 by setting DLL and DLM to 0, and then
562 * reading back DLL and DLM. The chip type depends on the DLM
563 * value read back:
564 * 0x10 - XR16C850 and the DLL contains the chip revision.
565 * 0x12 - XR16C2850.
566 * 0x14 - XR16C854.
567 */
568 id1 = autoconfig_read_divisor_id(up);
569 DEBUG_AUTOCONF("850id=%04x ", id1);
570
571 id2 = id1 >> 8;
572 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 573 up->port.type = PORT_16850;
574 return;
575 }
576
577 /*
578 * It wasn't an XR16C850.
579 *
580 * We distinguish between the '654 and the '650 by counting
581 * how many bytes are in the FIFO. I'm using this for now,
582 * since that's the technique that was sent to me in the
583 * serial driver update, but I'm not convinced this works.
584 * I've had problems doing this in the past. -TYT
585 */
586 if (size_fifo(up) == 64)
587 up->port.type = PORT_16654;
588 else
589 up->port.type = PORT_16650V2;
590}
591
592/*
593 * We detected a chip without a FIFO. Only two fall into
594 * this category - the original 8250 and the 16450. The
595 * 16450 has a scratch register (accessible with LCR=0)
596 */
597static void autoconfig_8250(struct uart_8250_port *up)
598{
599 unsigned char scratch, status1, status2;
600
601 up->port.type = PORT_8250;
602
603 scratch = serial_in(up, UART_SCR);
604 serial_outp(up, UART_SCR, 0xa5);
605 status1 = serial_in(up, UART_SCR);
606 serial_outp(up, UART_SCR, 0x5a);
607 status2 = serial_in(up, UART_SCR);
608 serial_outp(up, UART_SCR, scratch);
609
610 if (status1 == 0xa5 && status2 == 0x5a)
611 up->port.type = PORT_16450;
612}
613
614static int broken_efr(struct uart_8250_port *up)
615{
616 /*
617 * Exar ST16C2550 "A2" devices incorrectly detect as
618 * having an EFR, and report an ID of 0x0201. See
619 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
620 */
621 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
622 return 1;
623
624 return 0;
625}
626
627/*
628 * We know that the chip has FIFOs. Does it have an EFR? The
629 * EFR is located in the same register position as the IIR and
630 * we know the top two bits of the IIR are currently set. The
631 * EFR should contain zero. Try to read the EFR.
632 */
633static void autoconfig_16550a(struct uart_8250_port *up)
634{
635 unsigned char status1, status2;
636 unsigned int iersave;
637
638 up->port.type = PORT_16550A;
639 up->capabilities |= UART_CAP_FIFO;
640
641 /*
642 * Check for presence of the EFR when DLAB is set.
643 * Only ST16C650V1 UARTs pass this test.
644 */
645 serial_outp(up, UART_LCR, UART_LCR_DLAB);
646 if (serial_in(up, UART_EFR) == 0) {
647 serial_outp(up, UART_EFR, 0xA8);
648 if (serial_in(up, UART_EFR) != 0) {
649 DEBUG_AUTOCONF("EFRv1 ");
650 up->port.type = PORT_16650;
651 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
652 } else {
653 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
654 }
655 serial_outp(up, UART_EFR, 0);
656 return;
657 }
658
659 /*
660 * Maybe it requires 0xbf to be written to the LCR.
661 * (other ST16C650V2 UARTs, TI16C752A, etc)
662 */
663 serial_outp(up, UART_LCR, 0xBF);
664 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
665 DEBUG_AUTOCONF("EFRv2 ");
666 autoconfig_has_efr(up);
667 return;
668 }
669
670 /*
671 * Check for a National Semiconductor SuperIO chip.
672 * Attempt to switch to bank 2, read the value of the LOOP bit
673 * from EXCR1. Switch back to bank 0, change it in MCR. Then
674 * switch back to bank 2, read it from EXCR1 again and check
675 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 676 */
677 serial_outp(up, UART_LCR, 0);
678 status1 = serial_in(up, UART_MCR);
679 serial_outp(up, UART_LCR, 0xE0);
680 status2 = serial_in(up, 0x02); /* EXCR1 */
681
682 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
683 serial_outp(up, UART_LCR, 0);
684 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
685 serial_outp(up, UART_LCR, 0xE0);
686 status2 = serial_in(up, 0x02); /* EXCR1 */
687 serial_outp(up, UART_LCR, 0);
688 serial_outp(up, UART_MCR, status1);
689
690 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 691 unsigned short quot;
692
1da177e4 693 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 694
695 quot = serial_inp(up, UART_DLM) << 8;
696 quot += serial_inp(up, UART_DLL);
697 quot <<= 3;
698
1da177e4
LT		 699 status1 = serial_in(up, 0x04); /* EXCR1 */
700 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
701 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
702 serial_outp(up, 0x04, status1);
857dde2e
DW		 703
704 serial_outp(up, UART_DLL, quot & 0xff);
705 serial_outp(up, UART_DLM, quot >> 8);
706
1da177e4 707 serial_outp(up, UART_LCR, 0);
1da177e4 708
857dde2e 709 up->port.uartclk = 921600*16;
1da177e4
LT		 710 up->port.type = PORT_NS16550A;
711 up->capabilities |= UART_NATSEMI;
712 return;
713 }
714 }
715
716 /*
717 * No EFR. Try to detect a TI16750, which only sets bit 5 of
718 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
719 * Try setting it with and without DLAB set. Cheap clones
720 * set bit 5 without DLAB set.
721 */
722 serial_outp(up, UART_LCR, 0);
723 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
724 status1 = serial_in(up, UART_IIR) >> 5;
725 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
726 serial_outp(up, UART_LCR, UART_LCR_DLAB);
727 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
728 status2 = serial_in(up, UART_IIR) >> 5;
729 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
730 serial_outp(up, UART_LCR, 0);
731
732 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
733
734 if (status1 == 6 && status2 == 7) {
735 up->port.type = PORT_16750;
736 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
737 return;
738 }
739
740 /*
741 * Try writing and reading the UART_IER_UUE bit (b6).
742 * If it works, this is probably one of the Xscale platform's
743 * internal UARTs.
744 * We're going to explicitly set the UUE bit to 0 before
745 * trying to write and read a 1 just to make sure it's not
746 * already a 1 and maybe locked there before we even start start.
747 */
748 iersave = serial_in(up, UART_IER);
749 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
750 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
751 /*
752 * OK it's in a known zero state, try writing and reading
753 * without disturbing the current state of the other bits.
754 */
755 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
756 if (serial_in(up, UART_IER) & UART_IER_UUE) {
757 /*
758 * It's an Xscale.
759 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
760 */
761 DEBUG_AUTOCONF("Xscale ");
762 up->port.type = PORT_XSCALE;
763 up->capabilities |= UART_CAP_UUE;
764 return;
765 }
766 } else {
767 /*
768 * If we got here we couldn't force the IER_UUE bit to 0.
769 * Log it and continue.
770 */
771 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
772 }
773 serial_outp(up, UART_IER, iersave);
774}
775
776/*
777 * This routine is called by rs_init() to initialize a specific serial
778 * port. It determines what type of UART chip this serial port is
779 * using: 8250, 16450, 16550, 16550A. The important question is
780 * whether or not this UART is a 16550A or not, since this will
781 * determine whether or not we can use its FIFO features or not.
782 */
783static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
784{
785 unsigned char status1, scratch, scratch2, scratch3;
786 unsigned char save_lcr, save_mcr;
787 unsigned long flags;
788
789 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
790 return;
791
792 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
793 up->port.line, up->port.iobase, up->port.membase);
794
795 /*
796 * We really do need global IRQs disabled here - we're going to
797 * be frobbing the chips IRQ enable register to see if it exists.
798 */
799 spin_lock_irqsave(&up->port.lock, flags);
800// save_flags(flags); cli();
801
802 up->capabilities = 0;
4ba5e35d 803 up->bugs = 0;
1da177e4
LT		 804
805 if (!(up->port.flags & UPF_BUGGY_UART)) {
806 /*
807 * Do a simple existence test first; if we fail this,
808 * there's no point trying anything else.
809 *
810 * 0x80 is used as a nonsense port to prevent against
811 * false positives due to ISA bus float. The
812 * assumption is that 0x80 is a non-existent port;
813 * which should be safe since include/asm/io.h also
814 * makes this assumption.
815 *
816 * Note: this is safe as long as MCR bit 4 is clear
817 * and the device is in "PC" mode.
818 */
819 scratch = serial_inp(up, UART_IER);
820 serial_outp(up, UART_IER, 0);
821#ifdef __i386__
822 outb(0xff, 0x080);
823#endif
824 scratch2 = serial_inp(up, UART_IER);
825 serial_outp(up, UART_IER, 0x0F);
826#ifdef __i386__
827 outb(0, 0x080);
828#endif
829 scratch3 = serial_inp(up, UART_IER);
830 serial_outp(up, UART_IER, scratch);
831 if (scratch2 != 0 || scratch3 != 0x0F) {
832 /*
833 * We failed; there's nothing here
834 */
835 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
836 scratch2, scratch3);
837 goto out;
838 }
839 }
840
841 save_mcr = serial_in(up, UART_MCR);
842 save_lcr = serial_in(up, UART_LCR);
843
844 /*
845 * Check to see if a UART is really there. Certain broken
846 * internal modems based on the Rockwell chipset fail this
847 * test, because they apparently don't implement the loopback
848 * test mode. So this test is skipped on the COM 1 through
849 * COM 4 ports. This *should* be safe, since no board
850 * manufacturer would be stupid enough to design a board
851 * that conflicts with COM 1-4 --- we hope!
852 */
853 if (!(up->port.flags & UPF_SKIP_TEST)) {
854 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
855 status1 = serial_inp(up, UART_MSR) & 0xF0;
856 serial_outp(up, UART_MCR, save_mcr);
857 if (status1 != 0x90) {
858 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
859 status1);
860 goto out;
861 }
862 }
863
864 /*
865 * We're pretty sure there's a port here. Lets find out what
866 * type of port it is. The IIR top two bits allows us to find
867 * out if its 8250 or 16450, 16550, 16550A or later. This
868 * determines what we test for next.
869 *
870 * We also initialise the EFR (if any) to zero for later. The
871 * EFR occupies the same register location as the FCR and IIR.
872 */
873 serial_outp(up, UART_LCR, 0xBF);
874 serial_outp(up, UART_EFR, 0);
875 serial_outp(up, UART_LCR, 0);
876
877 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
878 scratch = serial_in(up, UART_IIR) >> 6;
879
880 DEBUG_AUTOCONF("iir=%d ", scratch);
881
882 switch (scratch) {
883 case 0:
884 autoconfig_8250(up);
885 break;
886 case 1:
887 up->port.type = PORT_UNKNOWN;
888 break;
889 case 2:
890 up->port.type = PORT_16550;
891 break;
892 case 3:
893 autoconfig_16550a(up);
894 break;
895 }
896
897#ifdef CONFIG_SERIAL_8250_RSA
898 /*
899 * Only probe for RSA ports if we got the region.
900 */
901 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
902 int i;
903
904 for (i = 0 ; i < probe_rsa_count; ++i) {
905 if (probe_rsa[i] == up->port.iobase &&
906 __enable_rsa(up)) {
907 up->port.type = PORT_RSA;
908 break;
909 }
910 }
911 }
912#endif
913 serial_outp(up, UART_LCR, save_lcr);
914
915 if (up->capabilities != uart_config[up->port.type].flags) {
916 printk(KERN_WARNING
917 "ttyS%d: detected caps %08x should be %08x\n",
918 up->port.line, up->capabilities,
919 uart_config[up->port.type].flags);
920 }
921
922 up->port.fifosize = uart_config[up->port.type].fifo_size;
923 up->capabilities = uart_config[up->port.type].flags;
924 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
925
926 if (up->port.type == PORT_UNKNOWN)
927 goto out;
928
929 /*
930 * Reset the UART.
931 */
932#ifdef CONFIG_SERIAL_8250_RSA
933 if (up->port.type == PORT_RSA)
934 serial_outp(up, UART_RSA_FRR, 0);
935#endif
936 serial_outp(up, UART_MCR, save_mcr);
937 serial8250_clear_fifos(up);
938 (void)serial_in(up, UART_RX);
939 serial_outp(up, UART_IER, 0);
940
941 out:
942 spin_unlock_irqrestore(&up->port.lock, flags);
943// restore_flags(flags);
944 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
945}
946
947static void autoconfig_irq(struct uart_8250_port *up)
948{
949 unsigned char save_mcr, save_ier;
950 unsigned char save_ICP = 0;
951 unsigned int ICP = 0;
952 unsigned long irqs;
953 int irq;
954
955 if (up->port.flags & UPF_FOURPORT) {
956 ICP = (up->port.iobase & 0xfe0) | 0x1f;
957 save_ICP = inb_p(ICP);
958 outb_p(0x80, ICP);
959 (void) inb_p(ICP);
960 }
961
962 /* forget possible initially masked and pending IRQ */
963 probe_irq_off(probe_irq_on());
964 save_mcr = serial_inp(up, UART_MCR);
965 save_ier = serial_inp(up, UART_IER);
966 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
967
968 irqs = probe_irq_on();
969 serial_outp(up, UART_MCR, 0);
970 udelay (10);
971 if (up->port.flags & UPF_FOURPORT) {
972 serial_outp(up, UART_MCR,
973 UART_MCR_DTR | UART_MCR_RTS);
974 } else {
975 serial_outp(up, UART_MCR,
976 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
977 }
978 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
979 (void)serial_inp(up, UART_LSR);
980 (void)serial_inp(up, UART_RX);
981 (void)serial_inp(up, UART_IIR);
982 (void)serial_inp(up, UART_MSR);
983 serial_outp(up, UART_TX, 0xFF);
984 udelay (20);
985 irq = probe_irq_off(irqs);
986
987 serial_outp(up, UART_MCR, save_mcr);
988 serial_outp(up, UART_IER, save_ier);
989
990 if (up->port.flags & UPF_FOURPORT)
991 outb_p(save_ICP, ICP);
992
993 up->port.irq = (irq > 0) ? irq : 0;
994}
995
e763b90c
RK		 996static inline void __stop_tx(struct uart_8250_port *p)
997{
998 if (p->ier & UART_IER_THRI) {
999 p->ier &= ~UART_IER_THRI;
1000 serial_out(p, UART_IER, p->ier);
1001 }
1002}
1003
1da177e4
LT		 1004static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
1005{
1006 struct uart_8250_port *up = (struct uart_8250_port *)port;
1007
e763b90c 1008 __stop_tx(up);
1da177e4
LT		 1009
1010 /*
e763b90c 1011 * We really want to stop the transmitter from sending.
1da177e4 1012 */
e763b90c 1013 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1014 up->acr |= UART_ACR_TXDIS;
1015 serial_icr_write(up, UART_ACR, up->acr);
1016 }
1017}
1018
55d3b282
RK		 1019static void transmit_chars(struct uart_8250_port *up);
1020
1da177e4
LT		 1021static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
1022{
1023 struct uart_8250_port *up = (struct uart_8250_port *)port;
1024
1025 if (!(up->ier & UART_IER_THRI)) {
1026 up->ier |= UART_IER_THRI;
1027 serial_out(up, UART_IER, up->ier);
55d3b282 1028
67f7654e 1029 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1030 unsigned char lsr, iir;
1031 lsr = serial_in(up, UART_LSR);
1032 iir = serial_in(up, UART_IIR);
1033 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1034 transmit_chars(up);
1035 }
1da177e4 1036 }
e763b90c 1037
1da177e4 1038 /*
e763b90c 1039 * Re-enable the transmitter if we disabled it.
1da177e4 1040 */
e763b90c 1041 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1042 up->acr &= ~UART_ACR_TXDIS;
1043 serial_icr_write(up, UART_ACR, up->acr);
1044 }
1045}
1046
1047static void serial8250_stop_rx(struct uart_port *port)
1048{
1049 struct uart_8250_port *up = (struct uart_8250_port *)port;
1050
1051 up->ier &= ~UART_IER_RLSI;
1052 up->port.read_status_mask &= ~UART_LSR_DR;
1053 serial_out(up, UART_IER, up->ier);
1054}
1055
1056static void serial8250_enable_ms(struct uart_port *port)
1057{
1058 struct uart_8250_port *up = (struct uart_8250_port *)port;
1059
1060 up->ier |= UART_IER_MSI;
1061 serial_out(up, UART_IER, up->ier);
1062}
1063
1064static _INLINE_ void
1065receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1066{
1067 struct tty_struct *tty = up->port.info->tty;
1068 unsigned char ch, lsr = *status;
1069 int max_count = 256;
1070 char flag;
1071
1072 do {
1073 /* The following is not allowed by the tty layer and
1074 unsafe. It should be fixed ASAP */
1075 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1076 if (tty->low_latency) {
1077 spin_unlock(&up->port.lock);
1078 tty_flip_buffer_push(tty);
1079 spin_lock(&up->port.lock);
1080 }
23907eb8
RK		 1081 /*
1082 * If this failed then we will throw away the
1083 * bytes but must do so to clear interrupts
1084 */
1da177e4
LT		 1085 }
1086 ch = serial_inp(up, UART_RX);
1087 flag = TTY_NORMAL;
1088 up->port.icount.rx++;
1089
1090#ifdef CONFIG_SERIAL_8250_CONSOLE
1091 /*
1092 * Recover the break flag from console xmit
1093 */
1094 if (up->port.line == up->port.cons->index) {
1095 lsr |= up->lsr_break_flag;
1096 up->lsr_break_flag = 0;
1097 }
1098#endif
1099
1100 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1101 UART_LSR_FE | UART_LSR_OE))) {
1102 /*
1103 * For statistics only
1104 */
1105 if (lsr & UART_LSR_BI) {
1106 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1107 up->port.icount.brk++;
1108 /*
1109 * We do the SysRQ and SAK checking
1110 * here because otherwise the break
1111 * may get masked by ignore_status_mask
1112 * or read_status_mask.
1113 */
1114 if (uart_handle_break(&up->port))
1115 goto ignore_char;
1116 } else if (lsr & UART_LSR_PE)
1117 up->port.icount.parity++;
1118 else if (lsr & UART_LSR_FE)
1119 up->port.icount.frame++;
1120 if (lsr & UART_LSR_OE)
1121 up->port.icount.overrun++;
1122
1123 /*
23907eb8 1124 * Mask off conditions which should be ignored.
1da177e4
LT		 1125 */
1126 lsr &= up->port.read_status_mask;
1127
1128 if (lsr & UART_LSR_BI) {
1129 DEBUG_INTR("handling break....");
1130 flag = TTY_BREAK;
1131 } else if (lsr & UART_LSR_PE)
1132 flag = TTY_PARITY;
1133 else if (lsr & UART_LSR_FE)
1134 flag = TTY_FRAME;
1135 }
1136 if (uart_handle_sysrq_char(&up->port, ch, regs))
1137 goto ignore_char;
05ab3014
RK		 1138
1139 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1140
1da177e4
LT		 1141 ignore_char:
1142 lsr = serial_inp(up, UART_LSR);
1143 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1144 spin_unlock(&up->port.lock);
1145 tty_flip_buffer_push(tty);
1146 spin_lock(&up->port.lock);
1147 *status = lsr;
1148}
1149
1150static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1151{
1152 struct circ_buf *xmit = &up->port.info->xmit;
1153 int count;
1154
1155 if (up->port.x_char) {
1156 serial_outp(up, UART_TX, up->port.x_char);
1157 up->port.icount.tx++;
1158 up->port.x_char = 0;
1159 return;
1160 }
1161 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
e763b90c 1162 __stop_tx(up);
1da177e4
LT		 1163 return;
1164 }
1165
1166 count = up->tx_loadsz;
1167 do {
1168 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1169 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1170 up->port.icount.tx++;
1171 if (uart_circ_empty(xmit))
1172 break;
1173 } while (--count > 0);
1174
1175 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1176 uart_write_wakeup(&up->port);
1177
1178 DEBUG_INTR("THRE...");
1179
1180 if (uart_circ_empty(xmit))
e763b90c 1181 __stop_tx(up);
1da177e4
LT		 1182}
1183
1184static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1185{
1186 int status;
1187
1188 status = serial_in(up, UART_MSR);
1189
1190 if ((status & UART_MSR_ANY_DELTA) == 0)
1191 return;
1192
1193 if (status & UART_MSR_TERI)
1194 up->port.icount.rng++;
1195 if (status & UART_MSR_DDSR)
1196 up->port.icount.dsr++;
1197 if (status & UART_MSR_DDCD)
1198 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1199 if (status & UART_MSR_DCTS)
1200 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1201
1202 wake_up_interruptible(&up->port.info->delta_msr_wait);
1203}
1204
1205/*
1206 * This handles the interrupt from one port.
1207 */
1208static inline void
1209serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1210{
1211 unsigned int status = serial_inp(up, UART_LSR);
1212
1213 DEBUG_INTR("status = %x...", status);
1214
1215 if (status & UART_LSR_DR)
1216 receive_chars(up, &status, regs);
1217 check_modem_status(up);
1218 if (status & UART_LSR_THRE)
1219 transmit_chars(up);
1220}
1221
1222/*
1223 * This is the serial driver's interrupt routine.
1224 *
1225 * Arjan thinks the old way was overly complex, so it got simplified.
1226 * Alan disagrees, saying that need the complexity to handle the weird
1227 * nature of ISA shared interrupts. (This is a special exception.)
1228 *
1229 * In order to handle ISA shared interrupts properly, we need to check
1230 * that all ports have been serviced, and therefore the ISA interrupt
1231 * line has been de-asserted.
1232 *
1233 * This means we need to loop through all ports. checking that they
1234 * don't have an interrupt pending.
1235 */
1236static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1237{
1238 struct irq_info *i = dev_id;
1239 struct list_head *l, *end = NULL;
1240 int pass_counter = 0, handled = 0;
1241
1242 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1243
1244 spin_lock(&i->lock);
1245
1246 l = i->head;
1247 do {
1248 struct uart_8250_port *up;
1249 unsigned int iir;
1250
1251 up = list_entry(l, struct uart_8250_port, list);
1252
1253 iir = serial_in(up, UART_IIR);
1254 if (!(iir & UART_IIR_NO_INT)) {
1255 spin_lock(&up->port.lock);
1256 serial8250_handle_port(up, regs);
1257 spin_unlock(&up->port.lock);
1258
1259 handled = 1;
1260
1261 end = NULL;
1262 } else if (end == NULL)
1263 end = l;
1264
1265 l = l->next;
1266
1267 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1268 /* If we hit this, we're dead. */
1269 printk(KERN_ERR "serial8250: too much work for "
1270 "irq%d\n", irq);
1271 break;
1272 }
1273 } while (l != end);
1274
1275 spin_unlock(&i->lock);
1276
1277 DEBUG_INTR("end.\n");
1278
1279 return IRQ_RETVAL(handled);
1280}
1281
1282/*
1283 * To support ISA shared interrupts, we need to have one interrupt
1284 * handler that ensures that the IRQ line has been deasserted
1285 * before returning. Failing to do this will result in the IRQ
1286 * line being stuck active, and, since ISA irqs are edge triggered,
1287 * no more IRQs will be seen.
1288 */
1289static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1290{
1291 spin_lock_irq(&i->lock);
1292
1293 if (!list_empty(i->head)) {
1294 if (i->head == &up->list)
1295 i->head = i->head->next;
1296 list_del(&up->list);
1297 } else {
1298 BUG_ON(i->head != &up->list);
1299 i->head = NULL;
1300 }
1301
1302 spin_unlock_irq(&i->lock);
1303}
1304
1305static int serial_link_irq_chain(struct uart_8250_port *up)
1306{
1307 struct irq_info *i = irq_lists + up->port.irq;
1308 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1309
1310 spin_lock_irq(&i->lock);
1311
1312 if (i->head) {
1313 list_add(&up->list, i->head);
1314 spin_unlock_irq(&i->lock);
1315
1316 ret = 0;
1317 } else {
1318 INIT_LIST_HEAD(&up->list);
1319 i->head = &up->list;
1320 spin_unlock_irq(&i->lock);
1321
1322 ret = request_irq(up->port.irq, serial8250_interrupt,
1323 irq_flags, "serial", i);
1324 if (ret < 0)
1325 serial_do_unlink(i, up);
1326 }
1327
1328 return ret;
1329}
1330
1331static void serial_unlink_irq_chain(struct uart_8250_port *up)
1332{
1333 struct irq_info *i = irq_lists + up->port.irq;
1334
1335 BUG_ON(i->head == NULL);
1336
1337 if (list_empty(i->head))
1338 free_irq(up->port.irq, i);
1339
1340 serial_do_unlink(i, up);
1341}
1342
1343/*
1344 * This function is used to handle ports that do not have an
1345 * interrupt. This doesn't work very well for 16450's, but gives
1346 * barely passable results for a 16550A. (Although at the expense
1347 * of much CPU overhead).
1348 */
1349static void serial8250_timeout(unsigned long data)
1350{
1351 struct uart_8250_port *up = (struct uart_8250_port *)data;
1352 unsigned int timeout;
1353 unsigned int iir;
1354
1355 iir = serial_in(up, UART_IIR);
1356 if (!(iir & UART_IIR_NO_INT)) {
1357 spin_lock(&up->port.lock);
1358 serial8250_handle_port(up, NULL);
1359 spin_unlock(&up->port.lock);
1360 }
1361
1362 timeout = up->port.timeout;
1363 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1364 mod_timer(&up->timer, jiffies + timeout);
1365}
1366
1367static unsigned int serial8250_tx_empty(struct uart_port *port)
1368{
1369 struct uart_8250_port *up = (struct uart_8250_port *)port;
1370 unsigned long flags;
1371 unsigned int ret;
1372
1373 spin_lock_irqsave(&up->port.lock, flags);
1374 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1375 spin_unlock_irqrestore(&up->port.lock, flags);
1376
1377 return ret;
1378}
1379
1380static unsigned int serial8250_get_mctrl(struct uart_port *port)
1381{
1382 struct uart_8250_port *up = (struct uart_8250_port *)port;
1da177e4
LT		 1383 unsigned char status;
1384 unsigned int ret;
1385
1da177e4 1386 status = serial_in(up, UART_MSR);
1da177e4
LT		 1387
1388 ret = 0;
1389 if (status & UART_MSR_DCD)
1390 ret |= TIOCM_CAR;
1391 if (status & UART_MSR_RI)
1392 ret |= TIOCM_RNG;
1393 if (status & UART_MSR_DSR)
1394 ret |= TIOCM_DSR;
1395 if (status & UART_MSR_CTS)
1396 ret |= TIOCM_CTS;
1397 return ret;
1398}
1399
1400static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1401{
1402 struct uart_8250_port *up = (struct uart_8250_port *)port;
1403 unsigned char mcr = 0;
1404
1405 if (mctrl & TIOCM_RTS)
1406 mcr |= UART_MCR_RTS;
1407 if (mctrl & TIOCM_DTR)
1408 mcr |= UART_MCR_DTR;
1409 if (mctrl & TIOCM_OUT1)
1410 mcr |= UART_MCR_OUT1;
1411 if (mctrl & TIOCM_OUT2)
1412 mcr |= UART_MCR_OUT2;
1413 if (mctrl & TIOCM_LOOP)
1414 mcr |= UART_MCR_LOOP;
1415
1416 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1417
1418 serial_out(up, UART_MCR, mcr);
1419}
1420
1421static void serial8250_break_ctl(struct uart_port *port, int break_state)
1422{
1423 struct uart_8250_port *up = (struct uart_8250_port *)port;
1424 unsigned long flags;
1425
1426 spin_lock_irqsave(&up->port.lock, flags);
1427 if (break_state == -1)
1428 up->lcr |= UART_LCR_SBC;
1429 else
1430 up->lcr &= ~UART_LCR_SBC;
1431 serial_out(up, UART_LCR, up->lcr);
1432 spin_unlock_irqrestore(&up->port.lock, flags);
1433}
1434
1435static int serial8250_startup(struct uart_port *port)
1436{
1437 struct uart_8250_port *up = (struct uart_8250_port *)port;
1438 unsigned long flags;
55d3b282 1439 unsigned char lsr, iir;
1da177e4
LT		 1440 int retval;
1441
1442 up->capabilities = uart_config[up->port.type].flags;
1443 up->mcr = 0;
1444
1445 if (up->port.type == PORT_16C950) {
1446 /* Wake up and initialize UART */
1447 up->acr = 0;
1448 serial_outp(up, UART_LCR, 0xBF);
1449 serial_outp(up, UART_EFR, UART_EFR_ECB);
1450 serial_outp(up, UART_IER, 0);
1451 serial_outp(up, UART_LCR, 0);
1452 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1453 serial_outp(up, UART_LCR, 0xBF);
1454 serial_outp(up, UART_EFR, UART_EFR_ECB);
1455 serial_outp(up, UART_LCR, 0);
1456 }
1457
1458#ifdef CONFIG_SERIAL_8250_RSA
1459 /*
1460 * If this is an RSA port, see if we can kick it up to the
1461 * higher speed clock.
1462 */
1463 enable_rsa(up);
1464#endif
1465
1466 /*
1467 * Clear the FIFO buffers and disable them.
1468 * (they will be reeanbled in set_termios())
1469 */
1470 serial8250_clear_fifos(up);
1471
1472 /*
1473 * Clear the interrupt registers.
1474 */
1475 (void) serial_inp(up, UART_LSR);
1476 (void) serial_inp(up, UART_RX);
1477 (void) serial_inp(up, UART_IIR);
1478 (void) serial_inp(up, UART_MSR);
1479
1480 /*
1481 * At this point, there's no way the LSR could still be 0xff;
1482 * if it is, then bail out, because there's likely no UART
1483 * here.
1484 */
1485 if (!(up->port.flags & UPF_BUGGY_UART) &&
1486 (serial_inp(up, UART_LSR) == 0xff)) {
1487 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1488 return -ENODEV;
1489 }
1490
1491 /*
1492 * For a XR16C850, we need to set the trigger levels
1493 */
1494 if (up->port.type == PORT_16850) {
1495 unsigned char fctr;
1496
1497 serial_outp(up, UART_LCR, 0xbf);
1498
1499 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1500 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1501 serial_outp(up, UART_TRG, UART_TRG_96);
1502 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1503 serial_outp(up, UART_TRG, UART_TRG_96);
1504
1505 serial_outp(up, UART_LCR, 0);
1506 }
1507
1508 /*
1509 * If the "interrupt" for this port doesn't correspond with any
1510 * hardware interrupt, we use a timer-based system. The original
1511 * driver used to do this with IRQ0.
1512 */
1513 if (!is_real_interrupt(up->port.irq)) {
1514 unsigned int timeout = up->port.timeout;
1515
1516 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1517
1518 up->timer.data = (unsigned long)up;
1519 mod_timer(&up->timer, jiffies + timeout);
1520 } else {
1521 retval = serial_link_irq_chain(up);
1522 if (retval)
1523 return retval;
1524 }
1525
1526 /*
1527 * Now, initialize the UART
1528 */
1529 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1530
1531 spin_lock_irqsave(&up->port.lock, flags);
1532 if (up->port.flags & UPF_FOURPORT) {
1533 if (!is_real_interrupt(up->port.irq))
1534 up->port.mctrl |= TIOCM_OUT1;
1535 } else
1536 /*
1537 * Most PC uarts need OUT2 raised to enable interrupts.
1538 */
1539 if (is_real_interrupt(up->port.irq))
1540 up->port.mctrl |= TIOCM_OUT2;
1541
1542 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1543
1544 /*
1545 * Do a quick test to see if we receive an
1546 * interrupt when we enable the TX irq.
1547 */
1548 serial_outp(up, UART_IER, UART_IER_THRI);
1549 lsr = serial_in(up, UART_LSR);
1550 iir = serial_in(up, UART_IIR);
1551 serial_outp(up, UART_IER, 0);
1552
1553 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1554 if (!(up->bugs & UART_BUG_TXEN)) {
1555 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1556 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1557 port->line);
1558 }
1559 } else {
67f7654e 1560 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1561 }
1562
1da177e4
LT		 1563 spin_unlock_irqrestore(&up->port.lock, flags);
1564
1565 /*
1566 * Finally, enable interrupts. Note: Modem status interrupts
1567 * are set via set_termios(), which will be occurring imminently
1568 * anyway, so we don't enable them here.
1569 */
1570 up->ier = UART_IER_RLSI | UART_IER_RDI;
1571 serial_outp(up, UART_IER, up->ier);
1572
1573 if (up->port.flags & UPF_FOURPORT) {
1574 unsigned int icp;
1575 /*
1576 * Enable interrupts on the AST Fourport board
1577 */
1578 icp = (up->port.iobase & 0xfe0) | 0x01f;
1579 outb_p(0x80, icp);
1580 (void) inb_p(icp);
1581 }
1582
1583 /*
1584 * And clear the interrupt registers again for luck.
1585 */
1586 (void) serial_inp(up, UART_LSR);
1587 (void) serial_inp(up, UART_RX);
1588 (void) serial_inp(up, UART_IIR);
1589 (void) serial_inp(up, UART_MSR);
1590
1591 return 0;
1592}
1593
1594static void serial8250_shutdown(struct uart_port *port)
1595{
1596 struct uart_8250_port *up = (struct uart_8250_port *)port;
1597 unsigned long flags;
1598
1599 /*
1600 * Disable interrupts from this port
1601 */
1602 up->ier = 0;
1603 serial_outp(up, UART_IER, 0);
1604
1605 spin_lock_irqsave(&up->port.lock, flags);
1606 if (up->port.flags & UPF_FOURPORT) {
1607 /* reset interrupts on the AST Fourport board */
1608 inb((up->port.iobase & 0xfe0) | 0x1f);
1609 up->port.mctrl |= TIOCM_OUT1;
1610 } else
1611 up->port.mctrl &= ~TIOCM_OUT2;
1612
1613 serial8250_set_mctrl(&up->port, up->port.mctrl);
1614 spin_unlock_irqrestore(&up->port.lock, flags);
1615
1616 /*
1617 * Disable break condition and FIFOs
1618 */
1619 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1620 serial8250_clear_fifos(up);
1621
1622#ifdef CONFIG_SERIAL_8250_RSA
1623 /*
1624 * Reset the RSA board back to 115kbps compat mode.
1625 */
1626 disable_rsa(up);
1627#endif
1628
1629 /*
1630 * Read data port to reset things, and then unlink from
1631 * the IRQ chain.
1632 */
1633 (void) serial_in(up, UART_RX);
1634
1635 if (!is_real_interrupt(up->port.irq))
1636 del_timer_sync(&up->timer);
1637 else
1638 serial_unlink_irq_chain(up);
1639}
1640
1641static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1642{
1643 unsigned int quot;
1644
1645 /*
1646 * Handle magic divisors for baud rates above baud_base on
1647 * SMSC SuperIO chips.
1648 */
1649 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1650 baud == (port->uartclk/4))
1651 quot = 0x8001;
1652 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1653 baud == (port->uartclk/8))
1654 quot = 0x8002;
1655 else
1656 quot = uart_get_divisor(port, baud);
1657
1658 return quot;
1659}
1660
1661static void
1662serial8250_set_termios(struct uart_port *port, struct termios *termios,
1663 struct termios *old)
1664{
1665 struct uart_8250_port *up = (struct uart_8250_port *)port;
1666 unsigned char cval, fcr = 0;
1667 unsigned long flags;
1668 unsigned int baud, quot;
1669
1670 switch (termios->c_cflag & CSIZE) {
1671 case CS5:
0a8b80c5 1672 cval = UART_LCR_WLEN5;
1da177e4
LT		 1673 break;
1674 case CS6:
0a8b80c5 1675 cval = UART_LCR_WLEN6;
1da177e4
LT		 1676 break;
1677 case CS7:
0a8b80c5 1678 cval = UART_LCR_WLEN7;
1da177e4
LT		 1679 break;
1680 default:
1681 case CS8:
0a8b80c5 1682 cval = UART_LCR_WLEN8;
1da177e4
LT		 1683 break;
1684 }
1685
1686 if (termios->c_cflag & CSTOPB)
0a8b80c5 1687 cval |= UART_LCR_STOP;
1da177e4
LT		 1688 if (termios->c_cflag & PARENB)
1689 cval |= UART_LCR_PARITY;
1690 if (!(termios->c_cflag & PARODD))
1691 cval |= UART_LCR_EPAR;
1692#ifdef CMSPAR
1693 if (termios->c_cflag & CMSPAR)
1694 cval |= UART_LCR_SPAR;
1695#endif
1696
1697 /*
1698 * Ask the core to calculate the divisor for us.
1699 */
1700 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1701 quot = serial8250_get_divisor(port, baud);
1702
1703 /*
4ba5e35d 1704 * Oxford Semi 952 rev B workaround
1da177e4 1705 */
4ba5e35d 1706 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1707 quot ++;
1708
1709 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1710 if (baud < 2400)
1711 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1712 else
1713 fcr = uart_config[up->port.type].fcr;
1714 }
1715
1716 /*
1717 * MCR-based auto flow control. When AFE is enabled, RTS will be
1718 * deasserted when the receive FIFO contains more characters than
1719 * the trigger, or the MCR RTS bit is cleared. In the case where
1720 * the remote UART is not using CTS auto flow control, we must
1721 * have sufficient FIFO entries for the latency of the remote
1722 * UART to respond. IOW, at least 32 bytes of FIFO.
1723 */
1724 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1725 up->mcr &= ~UART_MCR_AFE;
1726 if (termios->c_cflag & CRTSCTS)
1727 up->mcr |= UART_MCR_AFE;
1728 }
1729
1730 /*
1731 * Ok, we're now changing the port state. Do it with
1732 * interrupts disabled.
1733 */
1734 spin_lock_irqsave(&up->port.lock, flags);
1735
1736 /*
1737 * Update the per-port timeout.
1738 */
1739 uart_update_timeout(port, termios->c_cflag, baud);
1740
1741 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1742 if (termios->c_iflag & INPCK)
1743 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1744 if (termios->c_iflag & (BRKINT | PARMRK))
1745 up->port.read_status_mask |= UART_LSR_BI;
1746
1747 /*
1748 * Characteres to ignore
1749 */
1750 up->port.ignore_status_mask = 0;
1751 if (termios->c_iflag & IGNPAR)
1752 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1753 if (termios->c_iflag & IGNBRK) {
1754 up->port.ignore_status_mask |= UART_LSR_BI;
1755 /*
1756 * If we're ignoring parity and break indicators,
1757 * ignore overruns too (for real raw support).
1758 */
1759 if (termios->c_iflag & IGNPAR)
1760 up->port.ignore_status_mask |= UART_LSR_OE;
1761 }
1762
1763 /*
1764 * ignore all characters if CREAD is not set
1765 */
1766 if ((termios->c_cflag & CREAD) == 0)
1767 up->port.ignore_status_mask |= UART_LSR_DR;
1768
1769 /*
1770 * CTS flow control flag and modem status interrupts
1771 */
1772 up->ier &= ~UART_IER_MSI;
1773 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1774 up->ier |= UART_IER_MSI;
1775 if (up->capabilities & UART_CAP_UUE)
1776 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1777
1778 serial_out(up, UART_IER, up->ier);
1779
1780 if (up->capabilities & UART_CAP_EFR) {
1781 unsigned char efr = 0;
1782 /*
1783 * TI16C752/Startech hardware flow control. FIXME:
1784 * - TI16C752 requires control thresholds to be set.
1785 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1786 */
1787 if (termios->c_cflag & CRTSCTS)
1788 efr |= UART_EFR_CTS;
1789
1790 serial_outp(up, UART_LCR, 0xBF);
1791 serial_outp(up, UART_EFR, efr);
1792 }
1793
1794 if (up->capabilities & UART_NATSEMI) {
1795 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1796 serial_outp(up, UART_LCR, 0xe0);
1797 } else {
1798 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1799 }
1800
1801 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1802 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1803
1804 /*
1805 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1806 * is written without DLAB set, this mode will be disabled.
1807 */
1808 if (up->port.type == PORT_16750)
1809 serial_outp(up, UART_FCR, fcr);
1810
1811 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1812 up->lcr = cval; /* Save LCR */
1813 if (up->port.type != PORT_16750) {
1814 if (fcr & UART_FCR_ENABLE_FIFO) {
1815 /* emulated UARTs (Lucent Venus 167x) need two steps */
1816 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1817 }
1818 serial_outp(up, UART_FCR, fcr); /* set fcr */
1819 }
1820 serial8250_set_mctrl(&up->port, up->port.mctrl);
1821 spin_unlock_irqrestore(&up->port.lock, flags);
1822}
1823
1824static void
1825serial8250_pm(struct uart_port *port, unsigned int state,
1826 unsigned int oldstate)
1827{
1828 struct uart_8250_port *p = (struct uart_8250_port *)port;
1829
1830 serial8250_set_sleep(p, state != 0);
1831
1832 if (p->pm)
1833 p->pm(port, state, oldstate);
1834}
1835
1836/*
1837 * Resource handling.
1838 */
1839static int serial8250_request_std_resource(struct uart_8250_port *up)
1840{
1841 unsigned int size = 8 << up->port.regshift;
1842 int ret = 0;
1843
1844 switch (up->port.iotype) {
1845 case UPIO_MEM:
1846 if (!up->port.mapbase)
1847 break;
1848
1849 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1850 ret = -EBUSY;
1851 break;
1852 }
1853
1854 if (up->port.flags & UPF_IOREMAP) {
1855 up->port.membase = ioremap(up->port.mapbase, size);
1856 if (!up->port.membase) {
1857 release_mem_region(up->port.mapbase, size);
1858 ret = -ENOMEM;
1859 }
1860 }
1861 break;
1862
1863 case UPIO_HUB6:
1864 case UPIO_PORT:
1865 if (!request_region(up->port.iobase, size, "serial"))
1866 ret = -EBUSY;
1867 break;
1868 }
1869 return ret;
1870}
1871
1872static void serial8250_release_std_resource(struct uart_8250_port *up)
1873{
1874 unsigned int size = 8 << up->port.regshift;
1875
1876 switch (up->port.iotype) {
1877 case UPIO_MEM:
1878 if (!up->port.mapbase)
1879 break;
1880
1881 if (up->port.flags & UPF_IOREMAP) {
1882 iounmap(up->port.membase);
1883 up->port.membase = NULL;
1884 }
1885
1886 release_mem_region(up->port.mapbase, size);
1887 break;
1888
1889 case UPIO_HUB6:
1890 case UPIO_PORT:
1891 release_region(up->port.iobase, size);
1892 break;
1893 }
1894}
1895
1896static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1897{
1898 unsigned long start = UART_RSA_BASE << up->port.regshift;
1899 unsigned int size = 8 << up->port.regshift;
1900 int ret = 0;
1901
1902 switch (up->port.iotype) {
1903 case UPIO_MEM:
1904 ret = -EINVAL;
1905 break;
1906
1907 case UPIO_HUB6:
1908 case UPIO_PORT:
1909 start += up->port.iobase;
1910 if (!request_region(start, size, "serial-rsa"))
1911 ret = -EBUSY;
1912 break;
1913 }
1914
1915 return ret;
1916}
1917
1918static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1919{
1920 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1921 unsigned int size = 8 << up->port.regshift;
1922
1923 switch (up->port.iotype) {
1924 case UPIO_MEM:
1925 break;
1926
1927 case UPIO_HUB6:
1928 case UPIO_PORT:
1929 release_region(up->port.iobase + offset, size);
1930 break;
1931 }
1932}
1933
1934static void serial8250_release_port(struct uart_port *port)
1935{
1936 struct uart_8250_port *up = (struct uart_8250_port *)port;
1937
1938 serial8250_release_std_resource(up);
1939 if (up->port.type == PORT_RSA)
1940 serial8250_release_rsa_resource(up);
1941}
1942
1943static int serial8250_request_port(struct uart_port *port)
1944{
1945 struct uart_8250_port *up = (struct uart_8250_port *)port;
1946 int ret = 0;
1947
1948 ret = serial8250_request_std_resource(up);
1949 if (ret == 0 && up->port.type == PORT_RSA) {
1950 ret = serial8250_request_rsa_resource(up);
1951 if (ret < 0)
1952 serial8250_release_std_resource(up);
1953 }
1954
1955 return ret;
1956}
1957
1958static void serial8250_config_port(struct uart_port *port, int flags)
1959{
1960 struct uart_8250_port *up = (struct uart_8250_port *)port;
1961 int probeflags = PROBE_ANY;
1962 int ret;
1963
1964 /*
1965 * Don't probe for MCA ports on non-MCA machines.
1966 */
1967 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
1968 return;
1969
1970 /*
1971 * Find the region that we can probe for. This in turn
1972 * tells us whether we can probe for the type of port.
1973 */
1974 ret = serial8250_request_std_resource(up);
1975 if (ret < 0)
1976 return;
1977
1978 ret = serial8250_request_rsa_resource(up);
1979 if (ret < 0)
1980 probeflags &= ~PROBE_RSA;
1981
1982 if (flags & UART_CONFIG_TYPE)
1983 autoconfig(up, probeflags);
1984 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1985 autoconfig_irq(up);
1986
1987 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
1988 serial8250_release_rsa_resource(up);
1989 if (up->port.type == PORT_UNKNOWN)
1990 serial8250_release_std_resource(up);
1991}
1992
1993static int
1994serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
1995{
1996 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
1997 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
1998 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
1999 ser->type == PORT_STARTECH)
2000 return -EINVAL;
2001 return 0;
2002}
2003
2004static const char *
2005serial8250_type(struct uart_port *port)
2006{
2007 int type = port->type;
2008
2009 if (type >= ARRAY_SIZE(uart_config))
2010 type = 0;
2011 return uart_config[type].name;
2012}
2013
2014static struct uart_ops serial8250_pops = {
2015 .tx_empty = serial8250_tx_empty,
2016 .set_mctrl = serial8250_set_mctrl,
2017 .get_mctrl = serial8250_get_mctrl,
2018 .stop_tx = serial8250_stop_tx,
2019 .start_tx = serial8250_start_tx,
2020 .stop_rx = serial8250_stop_rx,
2021 .enable_ms = serial8250_enable_ms,
2022 .break_ctl = serial8250_break_ctl,
2023 .startup = serial8250_startup,
2024 .shutdown = serial8250_shutdown,
2025 .set_termios = serial8250_set_termios,
2026 .pm = serial8250_pm,
2027 .type = serial8250_type,
2028 .release_port = serial8250_release_port,
2029 .request_port = serial8250_request_port,
2030 .config_port = serial8250_config_port,
2031 .verify_port = serial8250_verify_port,
2032};
2033
2034static struct uart_8250_port serial8250_ports[UART_NR];
2035
2036static void __init serial8250_isa_init_ports(void)
2037{
2038 struct uart_8250_port *up;
2039 static int first = 1;
2040 int i;
2041
2042 if (!first)
2043 return;
2044 first = 0;
2045
2046 for (i = 0; i < UART_NR; i++) {
2047 struct uart_8250_port *up = &serial8250_ports[i];
2048
2049 up->port.line = i;
2050 spin_lock_init(&up->port.lock);
2051
2052 init_timer(&up->timer);
2053 up->timer.function = serial8250_timeout;
2054
2055 /*
2056 * ALPHA_KLUDGE_MCR needs to be killed.
2057 */
2058 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2059 up->mcr_force = ALPHA_KLUDGE_MCR;
2060
2061 up->port.ops = &serial8250_pops;
2062 }
2063
2064 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
2065 i++, up++) {
2066 up->port.iobase = old_serial_port[i].port;
2067 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2068 up->port.uartclk = old_serial_port[i].baud_base * 16;
2069 up->port.flags = old_serial_port[i].flags;
2070 up->port.hub6 = old_serial_port[i].hub6;
2071 up->port.membase = old_serial_port[i].iomem_base;
2072 up->port.iotype = old_serial_port[i].io_type;
2073 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2074 if (share_irqs)
2075 up->port.flags |= UPF_SHARE_IRQ;
2076 }
2077}
2078
2079static void __init
2080serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2081{
2082 int i;
2083
2084 serial8250_isa_init_ports();
2085
2086 for (i = 0; i < UART_NR; i++) {
2087 struct uart_8250_port *up = &serial8250_ports[i];
2088
2089 up->port.dev = dev;
2090 uart_add_one_port(drv, &up->port);
2091 }
2092}
2093
2094#ifdef CONFIG_SERIAL_8250_CONSOLE
2095
2096#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2097
2098/*
2099 * Wait for transmitter & holding register to empty
2100 */
2101static inline void wait_for_xmitr(struct uart_8250_port *up)
2102{
2103 unsigned int status, tmout = 10000;
2104
2105 /* Wait up to 10ms for the character(s) to be sent. */
2106 do {
2107 status = serial_in(up, UART_LSR);
2108
2109 if (status & UART_LSR_BI)
2110 up->lsr_break_flag = UART_LSR_BI;
2111
2112 if (--tmout == 0)
2113 break;
2114 udelay(1);
2115 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2116
2117 /* Wait up to 1s for flow control if necessary */
2118 if (up->port.flags & UPF_CONS_FLOW) {
2119 tmout = 1000000;
2120 while (--tmout &&
2121 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2122 udelay(1);
2123 }
2124}
2125
2126/*
2127 * Print a string to the serial port trying not to disturb
2128 * any possible real use of the port...
2129 *
2130 * The console_lock must be held when we get here.
2131 */
2132static void
2133serial8250_console_write(struct console *co, const char *s, unsigned int count)
2134{
2135 struct uart_8250_port *up = &serial8250_ports[co->index];
2136 unsigned int ier;
2137 int i;
2138
2139 /*
2140 * First save the UER then disable the interrupts
2141 */
2142 ier = serial_in(up, UART_IER);
2143
2144 if (up->capabilities & UART_CAP_UUE)
2145 serial_out(up, UART_IER, UART_IER_UUE);
2146 else
2147 serial_out(up, UART_IER, 0);
2148
2149 /*
2150 * Now, do each character
2151 */
2152 for (i = 0; i < count; i++, s++) {
2153 wait_for_xmitr(up);
2154
2155 /*
2156 * Send the character out.
2157 * If a LF, also do CR...
2158 */
2159 serial_out(up, UART_TX, *s);
2160 if (*s == 10) {
2161 wait_for_xmitr(up);
2162 serial_out(up, UART_TX, 13);
2163 }
2164 }
2165
2166 /*
2167 * Finally, wait for transmitter to become empty
2168 * and restore the IER
2169 */
2170 wait_for_xmitr(up);
2171 serial_out(up, UART_IER, ier);
2172}
2173
2174static int serial8250_console_setup(struct console *co, char *options)
2175{
2176 struct uart_port *port;
2177 int baud = 9600;
2178 int bits = 8;
2179 int parity = 'n';
2180 int flow = 'n';
2181
2182 /*
2183 * Check whether an invalid uart number has been specified, and
2184 * if so, search for the first available port that does have
2185 * console support.
2186 */
2187 if (co->index >= UART_NR)
2188 co->index = 0;
2189 port = &serial8250_ports[co->index].port;
2190 if (!port->iobase && !port->membase)
2191 return -ENODEV;
2192
2193 if (options)
2194 uart_parse_options(options, &baud, &parity, &bits, &flow);
2195
2196 return uart_set_options(port, co, baud, parity, bits, flow);
2197}
2198
2199static struct uart_driver serial8250_reg;
2200static struct console serial8250_console = {
2201 .name = "ttyS",
2202 .write = serial8250_console_write,
2203 .device = uart_console_device,
2204 .setup = serial8250_console_setup,
2205 .flags = CON_PRINTBUFFER,
2206 .index = -1,
2207 .data = &serial8250_reg,
2208};
2209
2210static int __init serial8250_console_init(void)
2211{
2212 serial8250_isa_init_ports();
2213 register_console(&serial8250_console);
2214 return 0;
2215}
2216console_initcall(serial8250_console_init);
2217
2218static int __init find_port(struct uart_port *p)
2219{
2220 int line;
2221 struct uart_port *port;
2222
2223 for (line = 0; line < UART_NR; line++) {
2224 port = &serial8250_ports[line].port;
2225 if (p->iotype == port->iotype &&
2226 p->iobase == port->iobase &&
2227 p->membase == port->membase)
2228 return line;
2229 }
2230 return -ENODEV;
2231}
2232
2233int __init serial8250_start_console(struct uart_port *port, char *options)
2234{
2235 int line;
2236
2237 line = find_port(port);
2238 if (line < 0)
2239 return -ENODEV;
2240
2241 add_preferred_console("ttyS", line, options);
2242 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2243 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2244 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2245 (unsigned long) port->iobase, options);
2246 if (!(serial8250_console.flags & CON_ENABLED)) {
2247 serial8250_console.flags &= ~CON_PRINTBUFFER;
2248 register_console(&serial8250_console);
2249 }
2250 return line;
2251}
2252
2253#define SERIAL8250_CONSOLE &serial8250_console
2254#else
2255#define SERIAL8250_CONSOLE NULL
2256#endif
2257
2258static struct uart_driver serial8250_reg = {
2259 .owner = THIS_MODULE,
2260 .driver_name = "serial",
2261 .devfs_name = "tts/",
2262 .dev_name = "ttyS",
2263 .major = TTY_MAJOR,
2264 .minor = 64,
2265 .nr = UART_NR,
2266 .cons = SERIAL8250_CONSOLE,
2267};
2268
2269int __init early_serial_setup(struct uart_port *port)
2270{
2271 if (port->line >= ARRAY_SIZE(serial8250_ports))
2272 return -ENODEV;
2273
2274 serial8250_isa_init_ports();
2275 serial8250_ports[port->line].port = *port;
2276 serial8250_ports[port->line].port.ops = &serial8250_pops;
2277 return 0;
2278}
2279
2280/**
2281 * serial8250_suspend_port - suspend one serial port
2282 * @line: serial line number
2283 * @level: the level of port suspension, as per uart_suspend_port
2284 *
2285 * Suspend one serial port.
2286 */
2287void serial8250_suspend_port(int line)
2288{
2289 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2290}
2291
2292/**
2293 * serial8250_resume_port - resume one serial port
2294 * @line: serial line number
2295 * @level: the level of port resumption, as per uart_resume_port
2296 *
2297 * Resume one serial port.
2298 */
2299void serial8250_resume_port(int line)
2300{
2301 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2302}
2303
2304/*
2305 * Register a set of serial devices attached to a platform device. The
2306 * list is terminated with a zero flags entry, which means we expect
2307 * all entries to have at least UPF_BOOT_AUTOCONF set.
2308 */
2309static int __devinit serial8250_probe(struct device *dev)
2310{
2311 struct plat_serial8250_port *p = dev->platform_data;
2312 struct uart_port port;
ec9f47cd 2313 int ret, i;
1da177e4
LT		 2314
2315 memset(&port, 0, sizeof(struct uart_port));
2316
ec9f47cd 2317 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2318 port.iobase = p->iobase;
2319 port.membase = p->membase;
2320 port.irq = p->irq;
2321 port.uartclk = p->uartclk;
2322 port.regshift = p->regshift;
2323 port.iotype = p->iotype;
2324 port.flags = p->flags;
2325 port.mapbase = p->mapbase;
ec9f47cd 2326 port.hub6 = p->hub6;
1da177e4
LT		 2327 port.dev = dev;
2328 if (share_irqs)
2329 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2330 ret = serial8250_register_port(&port);
2331 if (ret < 0) {
2332 dev_err(dev, "unable to register port at index %d "
2333 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2334 p->iobase, p->mapbase, p->irq, ret);
2335 }
1da177e4
LT		 2336 }
2337 return 0;
2338}
2339
2340/*
2341 * Remove serial ports registered against a platform device.
2342 */
2343static int __devexit serial8250_remove(struct device *dev)
2344{
2345 int i;
2346
2347 for (i = 0; i < UART_NR; i++) {
2348 struct uart_8250_port *up = &serial8250_ports[i];
2349
2350 if (up->port.dev == dev)
2351 serial8250_unregister_port(i);
2352 }
2353 return 0;
2354}
2355
2356static int serial8250_suspend(struct device *dev, pm_message_t state, u32 level)
2357{
2358 int i;
2359
2360 if (level != SUSPEND_DISABLE)
2361 return 0;
2362
2363 for (i = 0; i < UART_NR; i++) {
2364 struct uart_8250_port *up = &serial8250_ports[i];
2365
2366 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2367 uart_suspend_port(&serial8250_reg, &up->port);
2368 }
2369
2370 return 0;
2371}
2372
2373static int serial8250_resume(struct device *dev, u32 level)
2374{
2375 int i;
2376
2377 if (level != RESUME_ENABLE)
2378 return 0;
2379
2380 for (i = 0; i < UART_NR; i++) {
2381 struct uart_8250_port *up = &serial8250_ports[i];
2382
2383 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2384 uart_resume_port(&serial8250_reg, &up->port);
2385 }
2386
2387 return 0;
2388}
2389
2390static struct device_driver serial8250_isa_driver = {
2391 .name = "serial8250",
2392 .bus = &platform_bus_type,
2393 .probe = serial8250_probe,
2394 .remove = __devexit_p(serial8250_remove),
2395 .suspend = serial8250_suspend,
2396 .resume = serial8250_resume,
2397};
2398
2399/*
2400 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2401 * in the table in include/asm/serial.h
2402 */
2403static struct platform_device *serial8250_isa_devs;
2404
2405/*
2406 * serial8250_register_port and serial8250_unregister_port allows for
2407 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2408 * modems and PCI multiport cards.
2409 */
2410static DECLARE_MUTEX(serial_sem);
2411
2412static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2413{
2414 int i;
2415
2416 /*
2417 * First, find a port entry which matches.
2418 */
2419 for (i = 0; i < UART_NR; i++)
2420 if (uart_match_port(&serial8250_ports[i].port, port))
2421 return &serial8250_ports[i];
2422
2423 /*
2424 * We didn't find a matching entry, so look for the first
2425 * free entry. We look for one which hasn't been previously
2426 * used (indicated by zero iobase).
2427 */
2428 for (i = 0; i < UART_NR; i++)
2429 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2430 serial8250_ports[i].port.iobase == 0)
2431 return &serial8250_ports[i];
2432
2433 /*
2434 * That also failed. Last resort is to find any entry which
2435 * doesn't have a real port associated with it.
2436 */
2437 for (i = 0; i < UART_NR; i++)
2438 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2439 return &serial8250_ports[i];
2440
2441 return NULL;
2442}
2443
2444/**
2445 * serial8250_register_port - register a serial port
2446 * @port: serial port template
2447 *
2448 * Configure the serial port specified by the request. If the
2449 * port exists and is in use, it is hung up and unregistered
2450 * first.
2451 *
2452 * The port is then probed and if necessary the IRQ is autodetected
2453 * If this fails an error is returned.
2454 *
2455 * On success the port is ready to use and the line number is returned.
2456 */
2457int serial8250_register_port(struct uart_port *port)
2458{
2459 struct uart_8250_port *uart;
2460 int ret = -ENOSPC;
2461
2462 if (port->uartclk == 0)
2463 return -EINVAL;
2464
2465 down(&serial_sem);
2466
2467 uart = serial8250_find_match_or_unused(port);
2468 if (uart) {
2469 uart_remove_one_port(&serial8250_reg, &uart->port);
2470
2471 uart->port.iobase = port->iobase;
2472 uart->port.membase = port->membase;
2473 uart->port.irq = port->irq;
2474 uart->port.uartclk = port->uartclk;
2475 uart->port.fifosize = port->fifosize;
2476 uart->port.regshift = port->regshift;
2477 uart->port.iotype = port->iotype;
2478 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2479 uart->port.mapbase = port->mapbase;
2480 if (port->dev)
2481 uart->port.dev = port->dev;
2482
2483 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2484 if (ret == 0)
2485 ret = uart->port.line;
2486 }
2487 up(&serial_sem);
2488
2489 return ret;
2490}
2491EXPORT_SYMBOL(serial8250_register_port);
2492
2493/**
2494 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2495 * @line: serial line number
2496 *
2497 * Remove one serial port. This may not be called from interrupt
2498 * context. We hand the port back to the our control.
2499 */
2500void serial8250_unregister_port(int line)
2501{
2502 struct uart_8250_port *uart = &serial8250_ports[line];
2503
2504 down(&serial_sem);
2505 uart_remove_one_port(&serial8250_reg, &uart->port);
2506 if (serial8250_isa_devs) {
2507 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2508 uart->port.type = PORT_UNKNOWN;
2509 uart->port.dev = &serial8250_isa_devs->dev;
2510 uart_add_one_port(&serial8250_reg, &uart->port);
2511 } else {
2512 uart->port.dev = NULL;
2513 }
2514 up(&serial_sem);
2515}
2516EXPORT_SYMBOL(serial8250_unregister_port);
2517
2518static int __init serial8250_init(void)
2519{
2520 int ret, i;
2521
2522 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2523 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2524 share_irqs ? "en" : "dis");
2525
2526 for (i = 0; i < NR_IRQS; i++)
2527 spin_lock_init(&irq_lists[i].lock);
2528
2529 ret = uart_register_driver(&serial8250_reg);
2530 if (ret)
2531 goto out;
2532
2533 serial8250_isa_devs = platform_device_register_simple("serial8250",
2534 -1, NULL, 0);
2535 if (IS_ERR(serial8250_isa_devs)) {
2536 ret = PTR_ERR(serial8250_isa_devs);
2537 goto unreg;
2538 }
2539
2540 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2541
2542 ret = driver_register(&serial8250_isa_driver);
2543 if (ret == 0)
2544 goto out;
2545
2546 platform_device_unregister(serial8250_isa_devs);
2547 unreg:
2548 uart_unregister_driver(&serial8250_reg);
2549 out:
2550 return ret;
2551}
2552
2553static void __exit serial8250_exit(void)
2554{
2555 struct platform_device *isa_dev = serial8250_isa_devs;
2556
2557 /*
2558 * This tells serial8250_unregister_port() not to re-register
2559 * the ports (thereby making serial8250_isa_driver permanently
2560 * in use.)
2561 */
2562 serial8250_isa_devs = NULL;
2563
2564 driver_unregister(&serial8250_isa_driver);
2565 platform_device_unregister(isa_dev);
2566
2567 uart_unregister_driver(&serial8250_reg);
2568}
2569
2570module_init(serial8250_init);
2571module_exit(serial8250_exit);
2572
2573EXPORT_SYMBOL(serial8250_suspend_port);
2574EXPORT_SYMBOL(serial8250_resume_port);
2575
2576MODULE_LICENSE("GPL");
2577MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2578
2579module_param(share_irqs, uint, 0644);
2580MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2581 " (unsafe)");
2582
2583#ifdef CONFIG_SERIAL_8250_RSA
2584module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2585MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2586#endif
2587MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2588
2589/**
2590 * register_serial - configure a 16x50 serial port at runtime
2591 * @req: request structure
2592 *
2593 * Configure the serial port specified by the request. If the
2594 * port exists and is in use an error is returned. If the port
2595 * is not currently in the table it is added.
2596 *
2597 * The port is then probed and if necessary the IRQ is autodetected
2598 * If this fails an error is returned.
2599 *
2600 * On success the port is ready to use and the line number is returned.
23907eb8
RK		 2601 *
2602 * Note: this function is deprecated - use serial8250_register_port
2603 * instead.
1da177e4
LT		 2604 */
2605int register_serial(struct serial_struct *req)
2606{
2607 struct uart_port port;
2608
2609 port.iobase = req->port;
2610 port.membase = req->iomem_base;
2611 port.irq = req->irq;
2612 port.uartclk = req->baud_base * 16;
2613 port.fifosize = req->xmit_fifo_size;
2614 port.regshift = req->iomem_reg_shift;
2615 port.iotype = req->io_type;
2616 port.flags = req->flags | UPF_BOOT_AUTOCONF;
2617 port.mapbase = req->iomap_base;
2618 port.dev = NULL;
2619
2620 if (share_irqs)
2621 port.flags |= UPF_SHARE_IRQ;
2622
2623 if (HIGH_BITS_OFFSET)
2624 port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET;
2625
2626 /*
2627 * If a clock rate wasn't specified by the low level driver, then
2628 * default to the standard clock rate. This should be 115200 (*16)
2629 * and should not depend on the architecture's BASE_BAUD definition.
2630 * However, since this API will be deprecated, it's probably a
2631 * better idea to convert the drivers to use the new API
2632 * (serial8250_register_port and serial8250_unregister_port).
2633 */
2634 if (port.uartclk == 0) {
2635 printk(KERN_WARNING
2636 "Serial: registering port at [%08x,%08lx,%p] irq %d with zero baud_base\n",
2637 port.iobase, port.mapbase, port.membase, port.irq);
2638 printk(KERN_WARNING "Serial: see %s:%d for more information\n",
2639 __FILE__, __LINE__);
2640 dump_stack();
2641
2642 /*
2643 * Fix it up for now, but this is only a temporary measure.
2644 */
2645 port.uartclk = BASE_BAUD * 16;
2646 }
2647
2648 return serial8250_register_port(&port);
2649}
2650EXPORT_SYMBOL(register_serial);
2651
2652/**
2653 * unregister_serial - remove a 16x50 serial port at runtime
2654 * @line: serial line number
2655 *
2656 * Remove one serial port. This may not be called from interrupt
2657 * context. We hand the port back to our local PM control.
23907eb8
RK		 2658 *
2659 * Note: this function is deprecated - use serial8250_unregister_port
2660 * instead.
1da177e4
LT		 2661 */
2662void unregister_serial(int line)
2663{
2664 serial8250_unregister_port(line);
2665}
2666EXPORT_SYMBOL(unregister_serial);
Linux 6.x block layer and io_uring tree(s)