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[DRIVER MODEL] Add platform_driver
[linux-2.6-block.git] / drivers / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
1da177e4
LT		 37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
78512ece 43#include <linux/nmi.h>
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 56
57/*
58 * Debugging.
59 */
60#if 0
61#define DEBUG_AUTOCONF(fmt...) printk(fmt)
62#else
63#define DEBUG_AUTOCONF(fmt...) do { } while (0)
64#endif
65
66#if 0
67#define DEBUG_INTR(fmt...) printk(fmt)
68#else
69#define DEBUG_INTR(fmt...) do { } while (0)
70#endif
71
72#define PASS_LIMIT 256
73
74/*
75 * We default to IRQ0 for the "no irq" hack. Some
76 * machine types want others as well - they're free
77 * to redefine this in their header file.
78 */
79#define is_real_interrupt(irq) ((irq) != 0)
80
1da177e4
LT		 81#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
82#define CONFIG_SERIAL_DETECT_IRQ 1
83#endif
1da177e4
LT		 84#ifdef CONFIG_SERIAL_8250_MANY_PORTS
85#define CONFIG_SERIAL_MANY_PORTS 1
86#endif
87
88/*
89 * HUB6 is always on. This will be removed once the header
90 * files have been cleaned.
91 */
92#define CONFIG_HUB6 1
93
94#include <asm/serial.h>
95
96/*
97 * SERIAL_PORT_DFNS tells us about built-in ports that have no
98 * standard enumeration mechanism. Platforms that can find all
99 * serial ports via mechanisms like ACPI or PCI need not supply it.
100 */
101#ifndef SERIAL_PORT_DFNS
102#define SERIAL_PORT_DFNS
103#endif
104
105static struct old_serial_port old_serial_port[] = {
106 SERIAL_PORT_DFNS /* defined in asm/serial.h */
107};
108
026d02a2 109#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 110
111#ifdef CONFIG_SERIAL_8250_RSA
112
113#define PORT_RSA_MAX 4
114static unsigned long probe_rsa[PORT_RSA_MAX];
115static unsigned int probe_rsa_count;
116#endif /* CONFIG_SERIAL_8250_RSA */
117
118struct uart_8250_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 122 unsigned short capabilities; /* port capabilities */
123 unsigned short bugs; /* port bugs */
1da177e4 124 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 125 unsigned char acr;
126 unsigned char ier;
127 unsigned char lcr;
128 unsigned char mcr;
129 unsigned char mcr_mask; /* mask of user bits */
130 unsigned char mcr_force; /* mask of forced bits */
131 unsigned char lsr_break_flag;
132
133 /*
134 * We provide a per-port pm hook.
135 */
136 void (*pm)(struct uart_port *port,
137 unsigned int state, unsigned int old);
138};
139
140struct irq_info {
141 spinlock_t lock;
142 struct list_head *head;
143};
144
145static struct irq_info irq_lists[NR_IRQS];
146
147/*
148 * Here we define the default xmit fifo size used for each type of UART.
149 */
150static const struct serial8250_config uart_config[] = {
151 [PORT_UNKNOWN] = {
152 .name = "unknown",
153 .fifo_size = 1,
154 .tx_loadsz = 1,
155 },
156 [PORT_8250] = {
157 .name = "8250",
158 .fifo_size = 1,
159 .tx_loadsz = 1,
160 },
161 [PORT_16450] = {
162 .name = "16450",
163 .fifo_size = 1,
164 .tx_loadsz = 1,
165 },
166 [PORT_16550] = {
167 .name = "16550",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16550A] = {
172 .name = "16550A",
173 .fifo_size = 16,
174 .tx_loadsz = 16,
175 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
176 .flags = UART_CAP_FIFO,
177 },
178 [PORT_CIRRUS] = {
179 .name = "Cirrus",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16650] = {
184 .name = "ST16650",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
188 },
189 [PORT_16650V2] = {
190 .name = "ST16650V2",
191 .fifo_size = 32,
192 .tx_loadsz = 16,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 UART_FCR_T_TRIG_00,
195 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
196 },
197 [PORT_16750] = {
198 .name = "TI16750",
199 .fifo_size = 64,
200 .tx_loadsz = 64,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
202 UART_FCR7_64BYTE,
203 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
204 },
205 [PORT_STARTECH] = {
206 .name = "Startech",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 },
210 [PORT_16C950] = {
211 .name = "16C950/954",
212 .fifo_size = 128,
213 .tx_loadsz = 128,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
215 .flags = UART_CAP_FIFO,
216 },
217 [PORT_16654] = {
218 .name = "ST16654",
219 .fifo_size = 64,
220 .tx_loadsz = 32,
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 UART_FCR_T_TRIG_10,
223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 },
225 [PORT_16850] = {
226 .name = "XR16850",
227 .fifo_size = 128,
228 .tx_loadsz = 128,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
230 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
231 },
232 [PORT_RSA] = {
233 .name = "RSA",
234 .fifo_size = 2048,
235 .tx_loadsz = 2048,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_NS16550A] = {
240 .name = "NS16550A",
241 .fifo_size = 16,
242 .tx_loadsz = 16,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_NATSEMI,
245 },
246 [PORT_XSCALE] = {
247 .name = "XScale",
248 .fifo_size = 32,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_UUE,
252 },
253};
254
21c614a7
PA		 255#ifdef CONFIG_SERIAL_8250_AU1X00
256
257/* Au1x00 UART hardware has a weird register layout */
258static const u8 au_io_in_map[] = {
259 [UART_RX] = 0,
260 [UART_IER] = 2,
261 [UART_IIR] = 3,
262 [UART_LCR] = 5,
263 [UART_MCR] = 6,
264 [UART_LSR] = 7,
265 [UART_MSR] = 8,
266};
267
268static const u8 au_io_out_map[] = {
269 [UART_TX] = 1,
270 [UART_IER] = 2,
271 [UART_FCR] = 4,
272 [UART_LCR] = 5,
273 [UART_MCR] = 6,
274};
275
276/* sane hardware needs no mapping */
277static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
278{
279 if (up->port.iotype != UPIO_AU)
280 return offset;
281 return au_io_in_map[offset];
282}
283
284static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
285{
286 if (up->port.iotype != UPIO_AU)
287 return offset;
288 return au_io_out_map[offset];
289}
290
291#else
292
293/* sane hardware needs no mapping */
294#define map_8250_in_reg(up, offset) (offset)
295#define map_8250_out_reg(up, offset) (offset)
296
297#endif
298
1da177e4
LT		 299static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
300{
21c614a7 301 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 302
303 switch (up->port.iotype) {
304 case UPIO_HUB6:
305 outb(up->port.hub6 - 1 + offset, up->port.iobase);
306 return inb(up->port.iobase + 1);
307
308 case UPIO_MEM:
309 return readb(up->port.membase + offset);
310
311 case UPIO_MEM32:
312 return readl(up->port.membase + offset);
313
21c614a7
PA		 314#ifdef CONFIG_SERIAL_8250_AU1X00
315 case UPIO_AU:
316 return __raw_readl(up->port.membase + offset);
317#endif
318
1da177e4
LT		 319 default:
320 return inb(up->port.iobase + offset);
321 }
322}
323
324static _INLINE_ void
325serial_out(struct uart_8250_port *up, int offset, int value)
326{
21c614a7 327 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 328
329 switch (up->port.iotype) {
330 case UPIO_HUB6:
331 outb(up->port.hub6 - 1 + offset, up->port.iobase);
332 outb(value, up->port.iobase + 1);
333 break;
334
335 case UPIO_MEM:
336 writeb(value, up->port.membase + offset);
337 break;
338
339 case UPIO_MEM32:
340 writel(value, up->port.membase + offset);
341 break;
342
21c614a7
PA		 343#ifdef CONFIG_SERIAL_8250_AU1X00
344 case UPIO_AU:
345 __raw_writel(value, up->port.membase + offset);
346 break;
347#endif
348
1da177e4
LT		 349 default:
350 outb(value, up->port.iobase + offset);
351 }
352}
353
354/*
355 * We used to support using pause I/O for certain machines. We
356 * haven't supported this for a while, but just in case it's badly
357 * needed for certain old 386 machines, I've left these #define's
358 * in....
359 */
360#define serial_inp(up, offset) serial_in(up, offset)
361#define serial_outp(up, offset, value) serial_out(up, offset, value)
362
363
364/*
365 * For the 16C950
366 */
367static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
368{
369 serial_out(up, UART_SCR, offset);
370 serial_out(up, UART_ICR, value);
371}
372
373static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
374{
375 unsigned int value;
376
377 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
378 serial_out(up, UART_SCR, offset);
379 value = serial_in(up, UART_ICR);
380 serial_icr_write(up, UART_ACR, up->acr);
381
382 return value;
383}
384
385/*
386 * FIFO support.
387 */
388static inline void serial8250_clear_fifos(struct uart_8250_port *p)
389{
390 if (p->capabilities & UART_CAP_FIFO) {
391 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
392 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
393 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
394 serial_outp(p, UART_FCR, 0);
395 }
396}
397
398/*
399 * IER sleep support. UARTs which have EFRs need the "extended
400 * capability" bit enabled. Note that on XR16C850s, we need to
401 * reset LCR to write to IER.
402 */
403static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
404{
405 if (p->capabilities & UART_CAP_SLEEP) {
406 if (p->capabilities & UART_CAP_EFR) {
407 serial_outp(p, UART_LCR, 0xBF);
408 serial_outp(p, UART_EFR, UART_EFR_ECB);
409 serial_outp(p, UART_LCR, 0);
410 }
411 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
412 if (p->capabilities & UART_CAP_EFR) {
413 serial_outp(p, UART_LCR, 0xBF);
414 serial_outp(p, UART_EFR, 0);
415 serial_outp(p, UART_LCR, 0);
416 }
417 }
418}
419
420#ifdef CONFIG_SERIAL_8250_RSA
421/*
422 * Attempts to turn on the RSA FIFO. Returns zero on failure.
423 * We set the port uart clock rate if we succeed.
424 */
425static int __enable_rsa(struct uart_8250_port *up)
426{
427 unsigned char mode;
428 int result;
429
430 mode = serial_inp(up, UART_RSA_MSR);
431 result = mode & UART_RSA_MSR_FIFO;
432
433 if (!result) {
434 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
435 mode = serial_inp(up, UART_RSA_MSR);
436 result = mode & UART_RSA_MSR_FIFO;
437 }
438
439 if (result)
440 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
441
442 return result;
443}
444
445static void enable_rsa(struct uart_8250_port *up)
446{
447 if (up->port.type == PORT_RSA) {
448 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
449 spin_lock_irq(&up->port.lock);
450 __enable_rsa(up);
451 spin_unlock_irq(&up->port.lock);
452 }
453 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
454 serial_outp(up, UART_RSA_FRR, 0);
455 }
456}
457
458/*
459 * Attempts to turn off the RSA FIFO. Returns zero on failure.
460 * It is unknown why interrupts were disabled in here. However,
461 * the caller is expected to preserve this behaviour by grabbing
462 * the spinlock before calling this function.
463 */
464static void disable_rsa(struct uart_8250_port *up)
465{
466 unsigned char mode;
467 int result;
468
469 if (up->port.type == PORT_RSA &&
470 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
471 spin_lock_irq(&up->port.lock);
472
473 mode = serial_inp(up, UART_RSA_MSR);
474 result = !(mode & UART_RSA_MSR_FIFO);
475
476 if (!result) {
477 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
478 mode = serial_inp(up, UART_RSA_MSR);
479 result = !(mode & UART_RSA_MSR_FIFO);
480 }
481
482 if (result)
483 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
484 spin_unlock_irq(&up->port.lock);
485 }
486}
487#endif /* CONFIG_SERIAL_8250_RSA */
488
489/*
490 * This is a quickie test to see how big the FIFO is.
491 * It doesn't work at all the time, more's the pity.
492 */
493static int size_fifo(struct uart_8250_port *up)
494{
495 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
496 int count;
497
498 old_lcr = serial_inp(up, UART_LCR);
499 serial_outp(up, UART_LCR, 0);
500 old_fcr = serial_inp(up, UART_FCR);
501 old_mcr = serial_inp(up, UART_MCR);
502 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
503 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
504 serial_outp(up, UART_MCR, UART_MCR_LOOP);
505 serial_outp(up, UART_LCR, UART_LCR_DLAB);
506 old_dll = serial_inp(up, UART_DLL);
507 old_dlm = serial_inp(up, UART_DLM);
508 serial_outp(up, UART_DLL, 0x01);
509 serial_outp(up, UART_DLM, 0x00);
510 serial_outp(up, UART_LCR, 0x03);
511 for (count = 0; count < 256; count++)
512 serial_outp(up, UART_TX, count);
513 mdelay(20);/* FIXME - schedule_timeout */
514 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
515 (count < 256); count++)
516 serial_inp(up, UART_RX);
517 serial_outp(up, UART_FCR, old_fcr);
518 serial_outp(up, UART_MCR, old_mcr);
519 serial_outp(up, UART_LCR, UART_LCR_DLAB);
520 serial_outp(up, UART_DLL, old_dll);
521 serial_outp(up, UART_DLM, old_dlm);
522 serial_outp(up, UART_LCR, old_lcr);
523
524 return count;
525}
526
527/*
528 * Read UART ID using the divisor method - set DLL and DLM to zero
529 * and the revision will be in DLL and device type in DLM. We
530 * preserve the device state across this.
531 */
532static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
533{
534 unsigned char old_dll, old_dlm, old_lcr;
535 unsigned int id;
536
537 old_lcr = serial_inp(p, UART_LCR);
538 serial_outp(p, UART_LCR, UART_LCR_DLAB);
539
540 old_dll = serial_inp(p, UART_DLL);
541 old_dlm = serial_inp(p, UART_DLM);
542
543 serial_outp(p, UART_DLL, 0);
544 serial_outp(p, UART_DLM, 0);
545
546 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
547
548 serial_outp(p, UART_DLL, old_dll);
549 serial_outp(p, UART_DLM, old_dlm);
550 serial_outp(p, UART_LCR, old_lcr);
551
552 return id;
553}
554
555/*
556 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
557 * When this function is called we know it is at least a StarTech
558 * 16650 V2, but it might be one of several StarTech UARTs, or one of
559 * its clones. (We treat the broken original StarTech 16650 V1 as a
560 * 16550, and why not? Startech doesn't seem to even acknowledge its
561 * existence.)
562 *
563 * What evil have men's minds wrought...
564 */
565static void autoconfig_has_efr(struct uart_8250_port *up)
566{
567 unsigned int id1, id2, id3, rev;
568
569 /*
570 * Everything with an EFR has SLEEP
571 */
572 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
573
574 /*
575 * First we check to see if it's an Oxford Semiconductor UART.
576 *
577 * If we have to do this here because some non-National
578 * Semiconductor clone chips lock up if you try writing to the
579 * LSR register (which serial_icr_read does)
580 */
581
582 /*
583 * Check for Oxford Semiconductor 16C950.
584 *
585 * EFR [4] must be set else this test fails.
586 *
587 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
588 * claims that it's needed for 952 dual UART's (which are not
589 * recommended for new designs).
590 */
591 up->acr = 0;
592 serial_out(up, UART_LCR, 0xBF);
593 serial_out(up, UART_EFR, UART_EFR_ECB);
594 serial_out(up, UART_LCR, 0x00);
595 id1 = serial_icr_read(up, UART_ID1);
596 id2 = serial_icr_read(up, UART_ID2);
597 id3 = serial_icr_read(up, UART_ID3);
598 rev = serial_icr_read(up, UART_REV);
599
600 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
601
602 if (id1 == 0x16 && id2 == 0xC9 &&
603 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
604 up->port.type = PORT_16C950;
4ba5e35d
RK		 605
606 /*
607 * Enable work around for the Oxford Semiconductor 952 rev B
608 * chip which causes it to seriously miscalculate baud rates
609 * when DLL is 0.
610 */
611 if (id3 == 0x52 && rev == 0x01)
612 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 613 return;
614 }
615
616 /*
617 * We check for a XR16C850 by setting DLL and DLM to 0, and then
618 * reading back DLL and DLM. The chip type depends on the DLM
619 * value read back:
620 * 0x10 - XR16C850 and the DLL contains the chip revision.
621 * 0x12 - XR16C2850.
622 * 0x14 - XR16C854.
623 */
624 id1 = autoconfig_read_divisor_id(up);
625 DEBUG_AUTOCONF("850id=%04x ", id1);
626
627 id2 = id1 >> 8;
628 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 629 up->port.type = PORT_16850;
630 return;
631 }
632
633 /*
634 * It wasn't an XR16C850.
635 *
636 * We distinguish between the '654 and the '650 by counting
637 * how many bytes are in the FIFO. I'm using this for now,
638 * since that's the technique that was sent to me in the
639 * serial driver update, but I'm not convinced this works.
640 * I've had problems doing this in the past. -TYT
641 */
642 if (size_fifo(up) == 64)
643 up->port.type = PORT_16654;
644 else
645 up->port.type = PORT_16650V2;
646}
647
648/*
649 * We detected a chip without a FIFO. Only two fall into
650 * this category - the original 8250 and the 16450. The
651 * 16450 has a scratch register (accessible with LCR=0)
652 */
653static void autoconfig_8250(struct uart_8250_port *up)
654{
655 unsigned char scratch, status1, status2;
656
657 up->port.type = PORT_8250;
658
659 scratch = serial_in(up, UART_SCR);
660 serial_outp(up, UART_SCR, 0xa5);
661 status1 = serial_in(up, UART_SCR);
662 serial_outp(up, UART_SCR, 0x5a);
663 status2 = serial_in(up, UART_SCR);
664 serial_outp(up, UART_SCR, scratch);
665
666 if (status1 == 0xa5 && status2 == 0x5a)
667 up->port.type = PORT_16450;
668}
669
670static int broken_efr(struct uart_8250_port *up)
671{
672 /*
673 * Exar ST16C2550 "A2" devices incorrectly detect as
674 * having an EFR, and report an ID of 0x0201. See
675 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
676 */
677 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
678 return 1;
679
680 return 0;
681}
682
683/*
684 * We know that the chip has FIFOs. Does it have an EFR? The
685 * EFR is located in the same register position as the IIR and
686 * we know the top two bits of the IIR are currently set. The
687 * EFR should contain zero. Try to read the EFR.
688 */
689static void autoconfig_16550a(struct uart_8250_port *up)
690{
691 unsigned char status1, status2;
692 unsigned int iersave;
693
694 up->port.type = PORT_16550A;
695 up->capabilities |= UART_CAP_FIFO;
696
697 /*
698 * Check for presence of the EFR when DLAB is set.
699 * Only ST16C650V1 UARTs pass this test.
700 */
701 serial_outp(up, UART_LCR, UART_LCR_DLAB);
702 if (serial_in(up, UART_EFR) == 0) {
703 serial_outp(up, UART_EFR, 0xA8);
704 if (serial_in(up, UART_EFR) != 0) {
705 DEBUG_AUTOCONF("EFRv1 ");
706 up->port.type = PORT_16650;
707 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
708 } else {
709 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
710 }
711 serial_outp(up, UART_EFR, 0);
712 return;
713 }
714
715 /*
716 * Maybe it requires 0xbf to be written to the LCR.
717 * (other ST16C650V2 UARTs, TI16C752A, etc)
718 */
719 serial_outp(up, UART_LCR, 0xBF);
720 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
721 DEBUG_AUTOCONF("EFRv2 ");
722 autoconfig_has_efr(up);
723 return;
724 }
725
726 /*
727 * Check for a National Semiconductor SuperIO chip.
728 * Attempt to switch to bank 2, read the value of the LOOP bit
729 * from EXCR1. Switch back to bank 0, change it in MCR. Then
730 * switch back to bank 2, read it from EXCR1 again and check
731 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 732 */
733 serial_outp(up, UART_LCR, 0);
734 status1 = serial_in(up, UART_MCR);
735 serial_outp(up, UART_LCR, 0xE0);
736 status2 = serial_in(up, 0x02); /* EXCR1 */
737
738 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
739 serial_outp(up, UART_LCR, 0);
740 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
741 serial_outp(up, UART_LCR, 0xE0);
742 status2 = serial_in(up, 0x02); /* EXCR1 */
743 serial_outp(up, UART_LCR, 0);
744 serial_outp(up, UART_MCR, status1);
745
746 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 747 unsigned short quot;
748
1da177e4 749 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 750
751 quot = serial_inp(up, UART_DLM) << 8;
752 quot += serial_inp(up, UART_DLL);
753 quot <<= 3;
754
1da177e4
LT		 755 status1 = serial_in(up, 0x04); /* EXCR1 */
756 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
757 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
758 serial_outp(up, 0x04, status1);
857dde2e
DW		 759
760 serial_outp(up, UART_DLL, quot & 0xff);
761 serial_outp(up, UART_DLM, quot >> 8);
762
1da177e4 763 serial_outp(up, UART_LCR, 0);
1da177e4 764
857dde2e 765 up->port.uartclk = 921600*16;
1da177e4
LT		 766 up->port.type = PORT_NS16550A;
767 up->capabilities |= UART_NATSEMI;
768 return;
769 }
770 }
771
772 /*
773 * No EFR. Try to detect a TI16750, which only sets bit 5 of
774 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
775 * Try setting it with and without DLAB set. Cheap clones
776 * set bit 5 without DLAB set.
777 */
778 serial_outp(up, UART_LCR, 0);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
780 status1 = serial_in(up, UART_IIR) >> 5;
781 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
782 serial_outp(up, UART_LCR, UART_LCR_DLAB);
783 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
784 status2 = serial_in(up, UART_IIR) >> 5;
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
786 serial_outp(up, UART_LCR, 0);
787
788 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
789
790 if (status1 == 6 && status2 == 7) {
791 up->port.type = PORT_16750;
792 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
793 return;
794 }
795
796 /*
797 * Try writing and reading the UART_IER_UUE bit (b6).
798 * If it works, this is probably one of the Xscale platform's
799 * internal UARTs.
800 * We're going to explicitly set the UUE bit to 0 before
801 * trying to write and read a 1 just to make sure it's not
802 * already a 1 and maybe locked there before we even start start.
803 */
804 iersave = serial_in(up, UART_IER);
805 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
806 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
807 /*
808 * OK it's in a known zero state, try writing and reading
809 * without disturbing the current state of the other bits.
810 */
811 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
812 if (serial_in(up, UART_IER) & UART_IER_UUE) {
813 /*
814 * It's an Xscale.
815 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
816 */
817 DEBUG_AUTOCONF("Xscale ");
818 up->port.type = PORT_XSCALE;
819 up->capabilities |= UART_CAP_UUE;
820 return;
821 }
822 } else {
823 /*
824 * If we got here we couldn't force the IER_UUE bit to 0.
825 * Log it and continue.
826 */
827 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
828 }
829 serial_outp(up, UART_IER, iersave);
830}
831
832/*
833 * This routine is called by rs_init() to initialize a specific serial
834 * port. It determines what type of UART chip this serial port is
835 * using: 8250, 16450, 16550, 16550A. The important question is
836 * whether or not this UART is a 16550A or not, since this will
837 * determine whether or not we can use its FIFO features or not.
838 */
839static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
840{
841 unsigned char status1, scratch, scratch2, scratch3;
842 unsigned char save_lcr, save_mcr;
843 unsigned long flags;
844
845 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
846 return;
847
848 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
849 up->port.line, up->port.iobase, up->port.membase);
850
851 /*
852 * We really do need global IRQs disabled here - we're going to
853 * be frobbing the chips IRQ enable register to see if it exists.
854 */
855 spin_lock_irqsave(&up->port.lock, flags);
856// save_flags(flags); cli();
857
858 up->capabilities = 0;
4ba5e35d 859 up->bugs = 0;
1da177e4
LT		 860
861 if (!(up->port.flags & UPF_BUGGY_UART)) {
862 /*
863 * Do a simple existence test first; if we fail this,
864 * there's no point trying anything else.
865 *
866 * 0x80 is used as a nonsense port to prevent against
867 * false positives due to ISA bus float. The
868 * assumption is that 0x80 is a non-existent port;
869 * which should be safe since include/asm/io.h also
870 * makes this assumption.
871 *
872 * Note: this is safe as long as MCR bit 4 is clear
873 * and the device is in "PC" mode.
874 */
875 scratch = serial_inp(up, UART_IER);
876 serial_outp(up, UART_IER, 0);
877#ifdef __i386__
878 outb(0xff, 0x080);
879#endif
880 scratch2 = serial_inp(up, UART_IER);
881 serial_outp(up, UART_IER, 0x0F);
882#ifdef __i386__
883 outb(0, 0x080);
884#endif
885 scratch3 = serial_inp(up, UART_IER);
886 serial_outp(up, UART_IER, scratch);
887 if (scratch2 != 0 || scratch3 != 0x0F) {
888 /*
889 * We failed; there's nothing here
890 */
891 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
892 scratch2, scratch3);
893 goto out;
894 }
895 }
896
897 save_mcr = serial_in(up, UART_MCR);
898 save_lcr = serial_in(up, UART_LCR);
899
900 /*
901 * Check to see if a UART is really there. Certain broken
902 * internal modems based on the Rockwell chipset fail this
903 * test, because they apparently don't implement the loopback
904 * test mode. So this test is skipped on the COM 1 through
905 * COM 4 ports. This *should* be safe, since no board
906 * manufacturer would be stupid enough to design a board
907 * that conflicts with COM 1-4 --- we hope!
908 */
909 if (!(up->port.flags & UPF_SKIP_TEST)) {
910 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
911 status1 = serial_inp(up, UART_MSR) & 0xF0;
912 serial_outp(up, UART_MCR, save_mcr);
913 if (status1 != 0x90) {
914 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
915 status1);
916 goto out;
917 }
918 }
919
920 /*
921 * We're pretty sure there's a port here. Lets find out what
922 * type of port it is. The IIR top two bits allows us to find
6f0d618f 923 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 924 * determines what we test for next.
925 *
926 * We also initialise the EFR (if any) to zero for later. The
927 * EFR occupies the same register location as the FCR and IIR.
928 */
929 serial_outp(up, UART_LCR, 0xBF);
930 serial_outp(up, UART_EFR, 0);
931 serial_outp(up, UART_LCR, 0);
932
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
934 scratch = serial_in(up, UART_IIR) >> 6;
935
936 DEBUG_AUTOCONF("iir=%d ", scratch);
937
938 switch (scratch) {
939 case 0:
940 autoconfig_8250(up);
941 break;
942 case 1:
943 up->port.type = PORT_UNKNOWN;
944 break;
945 case 2:
946 up->port.type = PORT_16550;
947 break;
948 case 3:
949 autoconfig_16550a(up);
950 break;
951 }
952
953#ifdef CONFIG_SERIAL_8250_RSA
954 /*
955 * Only probe for RSA ports if we got the region.
956 */
957 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
958 int i;
959
960 for (i = 0 ; i < probe_rsa_count; ++i) {
961 if (probe_rsa[i] == up->port.iobase &&
962 __enable_rsa(up)) {
963 up->port.type = PORT_RSA;
964 break;
965 }
966 }
967 }
968#endif
21c614a7
PA		 969
970#ifdef CONFIG_SERIAL_8250_AU1X00
971 /* if access method is AU, it is a 16550 with a quirk */
972 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
973 up->bugs |= UART_BUG_NOMSR;
974#endif
975
1da177e4
LT		 976 serial_outp(up, UART_LCR, save_lcr);
977
978 if (up->capabilities != uart_config[up->port.type].flags) {
979 printk(KERN_WARNING
980 "ttyS%d: detected caps %08x should be %08x\n",
981 up->port.line, up->capabilities,
982 uart_config[up->port.type].flags);
983 }
984
985 up->port.fifosize = uart_config[up->port.type].fifo_size;
986 up->capabilities = uart_config[up->port.type].flags;
987 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
988
989 if (up->port.type == PORT_UNKNOWN)
990 goto out;
991
992 /*
993 * Reset the UART.
994 */
995#ifdef CONFIG_SERIAL_8250_RSA
996 if (up->port.type == PORT_RSA)
997 serial_outp(up, UART_RSA_FRR, 0);
998#endif
999 serial_outp(up, UART_MCR, save_mcr);
1000 serial8250_clear_fifos(up);
1001 (void)serial_in(up, UART_RX);
1002 serial_outp(up, UART_IER, 0);
1003
1004 out:
1005 spin_unlock_irqrestore(&up->port.lock, flags);
1006// restore_flags(flags);
1007 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1008}
1009
1010static void autoconfig_irq(struct uart_8250_port *up)
1011{
1012 unsigned char save_mcr, save_ier;
1013 unsigned char save_ICP = 0;
1014 unsigned int ICP = 0;
1015 unsigned long irqs;
1016 int irq;
1017
1018 if (up->port.flags & UPF_FOURPORT) {
1019 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1020 save_ICP = inb_p(ICP);
1021 outb_p(0x80, ICP);
1022 (void) inb_p(ICP);
1023 }
1024
1025 /* forget possible initially masked and pending IRQ */
1026 probe_irq_off(probe_irq_on());
1027 save_mcr = serial_inp(up, UART_MCR);
1028 save_ier = serial_inp(up, UART_IER);
1029 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1030
1031 irqs = probe_irq_on();
1032 serial_outp(up, UART_MCR, 0);
1033 udelay (10);
1034 if (up->port.flags & UPF_FOURPORT) {
1035 serial_outp(up, UART_MCR,
1036 UART_MCR_DTR | UART_MCR_RTS);
1037 } else {
1038 serial_outp(up, UART_MCR,
1039 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1040 }
1041 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1042 (void)serial_inp(up, UART_LSR);
1043 (void)serial_inp(up, UART_RX);
1044 (void)serial_inp(up, UART_IIR);
1045 (void)serial_inp(up, UART_MSR);
1046 serial_outp(up, UART_TX, 0xFF);
1047 udelay (20);
1048 irq = probe_irq_off(irqs);
1049
1050 serial_outp(up, UART_MCR, save_mcr);
1051 serial_outp(up, UART_IER, save_ier);
1052
1053 if (up->port.flags & UPF_FOURPORT)
1054 outb_p(save_ICP, ICP);
1055
1056 up->port.irq = (irq > 0) ? irq : 0;
1057}
1058
e763b90c
RK		 1059static inline void __stop_tx(struct uart_8250_port *p)
1060{
1061 if (p->ier & UART_IER_THRI) {
1062 p->ier &= ~UART_IER_THRI;
1063 serial_out(p, UART_IER, p->ier);
1064 }
1065}
1066
b129a8cc 1067static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1068{
1069 struct uart_8250_port *up = (struct uart_8250_port *)port;
1070
e763b90c 1071 __stop_tx(up);
1da177e4
LT		 1072
1073 /*
e763b90c 1074 * We really want to stop the transmitter from sending.
1da177e4 1075 */
e763b90c 1076 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1077 up->acr |= UART_ACR_TXDIS;
1078 serial_icr_write(up, UART_ACR, up->acr);
1079 }
1080}
1081
55d3b282
RK		 1082static void transmit_chars(struct uart_8250_port *up);
1083
b129a8cc 1084static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1085{
1086 struct uart_8250_port *up = (struct uart_8250_port *)port;
1087
1088 if (!(up->ier & UART_IER_THRI)) {
1089 up->ier |= UART_IER_THRI;
1090 serial_out(up, UART_IER, up->ier);
55d3b282 1091
67f7654e 1092 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1093 unsigned char lsr, iir;
1094 lsr = serial_in(up, UART_LSR);
1095 iir = serial_in(up, UART_IIR);
1096 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1097 transmit_chars(up);
1098 }
1da177e4 1099 }
e763b90c 1100
1da177e4 1101 /*
e763b90c 1102 * Re-enable the transmitter if we disabled it.
1da177e4 1103 */
e763b90c 1104 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1105 up->acr &= ~UART_ACR_TXDIS;
1106 serial_icr_write(up, UART_ACR, up->acr);
1107 }
1108}
1109
1110static void serial8250_stop_rx(struct uart_port *port)
1111{
1112 struct uart_8250_port *up = (struct uart_8250_port *)port;
1113
1114 up->ier &= ~UART_IER_RLSI;
1115 up->port.read_status_mask &= ~UART_LSR_DR;
1116 serial_out(up, UART_IER, up->ier);
1117}
1118
1119static void serial8250_enable_ms(struct uart_port *port)
1120{
1121 struct uart_8250_port *up = (struct uart_8250_port *)port;
1122
21c614a7
PA		 1123 /* no MSR capabilities */
1124 if (up->bugs & UART_BUG_NOMSR)
1125 return;
1126
1da177e4
LT		 1127 up->ier |= UART_IER_MSI;
1128 serial_out(up, UART_IER, up->ier);
1129}
1130
1131static _INLINE_ void
1132receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1133{
1134 struct tty_struct *tty = up->port.info->tty;
1135 unsigned char ch, lsr = *status;
1136 int max_count = 256;
1137 char flag;
1138
1139 do {
1140 /* The following is not allowed by the tty layer and
1141 unsafe. It should be fixed ASAP */
1142 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1143 if (tty->low_latency) {
1144 spin_unlock(&up->port.lock);
1145 tty_flip_buffer_push(tty);
1146 spin_lock(&up->port.lock);
1147 }
23907eb8
RK		 1148 /*
1149 * If this failed then we will throw away the
1150 * bytes but must do so to clear interrupts
1151 */
1da177e4
LT		 1152 }
1153 ch = serial_inp(up, UART_RX);
1154 flag = TTY_NORMAL;
1155 up->port.icount.rx++;
1156
1157#ifdef CONFIG_SERIAL_8250_CONSOLE
1158 /*
1159 * Recover the break flag from console xmit
1160 */
1161 if (up->port.line == up->port.cons->index) {
1162 lsr |= up->lsr_break_flag;
1163 up->lsr_break_flag = 0;
1164 }
1165#endif
1166
1167 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1168 UART_LSR_FE | UART_LSR_OE))) {
1169 /*
1170 * For statistics only
1171 */
1172 if (lsr & UART_LSR_BI) {
1173 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1174 up->port.icount.brk++;
1175 /*
1176 * We do the SysRQ and SAK checking
1177 * here because otherwise the break
1178 * may get masked by ignore_status_mask
1179 * or read_status_mask.
1180 */
1181 if (uart_handle_break(&up->port))
1182 goto ignore_char;
1183 } else if (lsr & UART_LSR_PE)
1184 up->port.icount.parity++;
1185 else if (lsr & UART_LSR_FE)
1186 up->port.icount.frame++;
1187 if (lsr & UART_LSR_OE)
1188 up->port.icount.overrun++;
1189
1190 /*
23907eb8 1191 * Mask off conditions which should be ignored.
1da177e4
LT		 1192 */
1193 lsr &= up->port.read_status_mask;
1194
1195 if (lsr & UART_LSR_BI) {
1196 DEBUG_INTR("handling break....");
1197 flag = TTY_BREAK;
1198 } else if (lsr & UART_LSR_PE)
1199 flag = TTY_PARITY;
1200 else if (lsr & UART_LSR_FE)
1201 flag = TTY_FRAME;
1202 }
1203 if (uart_handle_sysrq_char(&up->port, ch, regs))
1204 goto ignore_char;
05ab3014
RK		 1205
1206 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1207
1da177e4
LT		 1208 ignore_char:
1209 lsr = serial_inp(up, UART_LSR);
1210 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1211 spin_unlock(&up->port.lock);
1212 tty_flip_buffer_push(tty);
1213 spin_lock(&up->port.lock);
1214 *status = lsr;
1215}
1216
1217static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1218{
1219 struct circ_buf *xmit = &up->port.info->xmit;
1220 int count;
1221
1222 if (up->port.x_char) {
1223 serial_outp(up, UART_TX, up->port.x_char);
1224 up->port.icount.tx++;
1225 up->port.x_char = 0;
1226 return;
1227 }
b129a8cc
RK		 1228 if (uart_tx_stopped(&up->port)) {
1229 serial8250_stop_tx(&up->port);
1230 return;
1231 }
1232 if (uart_circ_empty(xmit)) {
e763b90c 1233 __stop_tx(up);
1da177e4
LT		 1234 return;
1235 }
1236
1237 count = up->tx_loadsz;
1238 do {
1239 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1240 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1241 up->port.icount.tx++;
1242 if (uart_circ_empty(xmit))
1243 break;
1244 } while (--count > 0);
1245
1246 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1247 uart_write_wakeup(&up->port);
1248
1249 DEBUG_INTR("THRE...");
1250
1251 if (uart_circ_empty(xmit))
e763b90c 1252 __stop_tx(up);
1da177e4
LT		 1253}
1254
1255static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1256{
1257 int status;
1258
1259 status = serial_in(up, UART_MSR);
1260
1261 if ((status & UART_MSR_ANY_DELTA) == 0)
1262 return;
1263
1264 if (status & UART_MSR_TERI)
1265 up->port.icount.rng++;
1266 if (status & UART_MSR_DDSR)
1267 up->port.icount.dsr++;
1268 if (status & UART_MSR_DDCD)
1269 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1270 if (status & UART_MSR_DCTS)
1271 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1272
1273 wake_up_interruptible(&up->port.info->delta_msr_wait);
1274}
1275
1276/*
1277 * This handles the interrupt from one port.
1278 */
1279static inline void
1280serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1281{
1282 unsigned int status = serial_inp(up, UART_LSR);
1283
1284 DEBUG_INTR("status = %x...", status);
1285
1286 if (status & UART_LSR_DR)
1287 receive_chars(up, &status, regs);
1288 check_modem_status(up);
1289 if (status & UART_LSR_THRE)
1290 transmit_chars(up);
1291}
1292
1293/*
1294 * This is the serial driver's interrupt routine.
1295 *
1296 * Arjan thinks the old way was overly complex, so it got simplified.
1297 * Alan disagrees, saying that need the complexity to handle the weird
1298 * nature of ISA shared interrupts. (This is a special exception.)
1299 *
1300 * In order to handle ISA shared interrupts properly, we need to check
1301 * that all ports have been serviced, and therefore the ISA interrupt
1302 * line has been de-asserted.
1303 *
1304 * This means we need to loop through all ports. checking that they
1305 * don't have an interrupt pending.
1306 */
1307static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1308{
1309 struct irq_info *i = dev_id;
1310 struct list_head *l, *end = NULL;
1311 int pass_counter = 0, handled = 0;
1312
1313 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1314
1315 spin_lock(&i->lock);
1316
1317 l = i->head;
1318 do {
1319 struct uart_8250_port *up;
1320 unsigned int iir;
1321
1322 up = list_entry(l, struct uart_8250_port, list);
1323
1324 iir = serial_in(up, UART_IIR);
1325 if (!(iir & UART_IIR_NO_INT)) {
1326 spin_lock(&up->port.lock);
1327 serial8250_handle_port(up, regs);
1328 spin_unlock(&up->port.lock);
1329
1330 handled = 1;
1331
1332 end = NULL;
1333 } else if (end == NULL)
1334 end = l;
1335
1336 l = l->next;
1337
1338 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1339 /* If we hit this, we're dead. */
1340 printk(KERN_ERR "serial8250: too much work for "
1341 "irq%d\n", irq);
1342 break;
1343 }
1344 } while (l != end);
1345
1346 spin_unlock(&i->lock);
1347
1348 DEBUG_INTR("end.\n");
1349
1350 return IRQ_RETVAL(handled);
1351}
1352
1353/*
1354 * To support ISA shared interrupts, we need to have one interrupt
1355 * handler that ensures that the IRQ line has been deasserted
1356 * before returning. Failing to do this will result in the IRQ
1357 * line being stuck active, and, since ISA irqs are edge triggered,
1358 * no more IRQs will be seen.
1359 */
1360static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1361{
1362 spin_lock_irq(&i->lock);
1363
1364 if (!list_empty(i->head)) {
1365 if (i->head == &up->list)
1366 i->head = i->head->next;
1367 list_del(&up->list);
1368 } else {
1369 BUG_ON(i->head != &up->list);
1370 i->head = NULL;
1371 }
1372
1373 spin_unlock_irq(&i->lock);
1374}
1375
1376static int serial_link_irq_chain(struct uart_8250_port *up)
1377{
1378 struct irq_info *i = irq_lists + up->port.irq;
1379 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1380
1381 spin_lock_irq(&i->lock);
1382
1383 if (i->head) {
1384 list_add(&up->list, i->head);
1385 spin_unlock_irq(&i->lock);
1386
1387 ret = 0;
1388 } else {
1389 INIT_LIST_HEAD(&up->list);
1390 i->head = &up->list;
1391 spin_unlock_irq(&i->lock);
1392
1393 ret = request_irq(up->port.irq, serial8250_interrupt,
1394 irq_flags, "serial", i);
1395 if (ret < 0)
1396 serial_do_unlink(i, up);
1397 }
1398
1399 return ret;
1400}
1401
1402static void serial_unlink_irq_chain(struct uart_8250_port *up)
1403{
1404 struct irq_info *i = irq_lists + up->port.irq;
1405
1406 BUG_ON(i->head == NULL);
1407
1408 if (list_empty(i->head))
1409 free_irq(up->port.irq, i);
1410
1411 serial_do_unlink(i, up);
1412}
1413
1414/*
1415 * This function is used to handle ports that do not have an
1416 * interrupt. This doesn't work very well for 16450's, but gives
1417 * barely passable results for a 16550A. (Although at the expense
1418 * of much CPU overhead).
1419 */
1420static void serial8250_timeout(unsigned long data)
1421{
1422 struct uart_8250_port *up = (struct uart_8250_port *)data;
1423 unsigned int timeout;
1424 unsigned int iir;
1425
1426 iir = serial_in(up, UART_IIR);
1427 if (!(iir & UART_IIR_NO_INT)) {
1428 spin_lock(&up->port.lock);
1429 serial8250_handle_port(up, NULL);
1430 spin_unlock(&up->port.lock);
1431 }
1432
1433 timeout = up->port.timeout;
1434 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1435 mod_timer(&up->timer, jiffies + timeout);
1436}
1437
1438static unsigned int serial8250_tx_empty(struct uart_port *port)
1439{
1440 struct uart_8250_port *up = (struct uart_8250_port *)port;
1441 unsigned long flags;
1442 unsigned int ret;
1443
1444 spin_lock_irqsave(&up->port.lock, flags);
1445 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1446 spin_unlock_irqrestore(&up->port.lock, flags);
1447
1448 return ret;
1449}
1450
1451static unsigned int serial8250_get_mctrl(struct uart_port *port)
1452{
1453 struct uart_8250_port *up = (struct uart_8250_port *)port;
1da177e4
LT		 1454 unsigned char status;
1455 unsigned int ret;
1456
1da177e4 1457 status = serial_in(up, UART_MSR);
1da177e4
LT		 1458
1459 ret = 0;
1460 if (status & UART_MSR_DCD)
1461 ret |= TIOCM_CAR;
1462 if (status & UART_MSR_RI)
1463 ret |= TIOCM_RNG;
1464 if (status & UART_MSR_DSR)
1465 ret |= TIOCM_DSR;
1466 if (status & UART_MSR_CTS)
1467 ret |= TIOCM_CTS;
1468 return ret;
1469}
1470
1471static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1472{
1473 struct uart_8250_port *up = (struct uart_8250_port *)port;
1474 unsigned char mcr = 0;
1475
1476 if (mctrl & TIOCM_RTS)
1477 mcr |= UART_MCR_RTS;
1478 if (mctrl & TIOCM_DTR)
1479 mcr |= UART_MCR_DTR;
1480 if (mctrl & TIOCM_OUT1)
1481 mcr |= UART_MCR_OUT1;
1482 if (mctrl & TIOCM_OUT2)
1483 mcr |= UART_MCR_OUT2;
1484 if (mctrl & TIOCM_LOOP)
1485 mcr |= UART_MCR_LOOP;
1486
1487 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1488
1489 serial_out(up, UART_MCR, mcr);
1490}
1491
1492static void serial8250_break_ctl(struct uart_port *port, int break_state)
1493{
1494 struct uart_8250_port *up = (struct uart_8250_port *)port;
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&up->port.lock, flags);
1498 if (break_state == -1)
1499 up->lcr |= UART_LCR_SBC;
1500 else
1501 up->lcr &= ~UART_LCR_SBC;
1502 serial_out(up, UART_LCR, up->lcr);
1503 spin_unlock_irqrestore(&up->port.lock, flags);
1504}
1505
1506static int serial8250_startup(struct uart_port *port)
1507{
1508 struct uart_8250_port *up = (struct uart_8250_port *)port;
1509 unsigned long flags;
55d3b282 1510 unsigned char lsr, iir;
1da177e4
LT		 1511 int retval;
1512
1513 up->capabilities = uart_config[up->port.type].flags;
1514 up->mcr = 0;
1515
1516 if (up->port.type == PORT_16C950) {
1517 /* Wake up and initialize UART */
1518 up->acr = 0;
1519 serial_outp(up, UART_LCR, 0xBF);
1520 serial_outp(up, UART_EFR, UART_EFR_ECB);
1521 serial_outp(up, UART_IER, 0);
1522 serial_outp(up, UART_LCR, 0);
1523 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1524 serial_outp(up, UART_LCR, 0xBF);
1525 serial_outp(up, UART_EFR, UART_EFR_ECB);
1526 serial_outp(up, UART_LCR, 0);
1527 }
1528
1529#ifdef CONFIG_SERIAL_8250_RSA
1530 /*
1531 * If this is an RSA port, see if we can kick it up to the
1532 * higher speed clock.
1533 */
1534 enable_rsa(up);
1535#endif
1536
1537 /*
1538 * Clear the FIFO buffers and disable them.
1539 * (they will be reeanbled in set_termios())
1540 */
1541 serial8250_clear_fifos(up);
1542
1543 /*
1544 * Clear the interrupt registers.
1545 */
1546 (void) serial_inp(up, UART_LSR);
1547 (void) serial_inp(up, UART_RX);
1548 (void) serial_inp(up, UART_IIR);
1549 (void) serial_inp(up, UART_MSR);
1550
1551 /*
1552 * At this point, there's no way the LSR could still be 0xff;
1553 * if it is, then bail out, because there's likely no UART
1554 * here.
1555 */
1556 if (!(up->port.flags & UPF_BUGGY_UART) &&
1557 (serial_inp(up, UART_LSR) == 0xff)) {
1558 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1559 return -ENODEV;
1560 }
1561
1562 /*
1563 * For a XR16C850, we need to set the trigger levels
1564 */
1565 if (up->port.type == PORT_16850) {
1566 unsigned char fctr;
1567
1568 serial_outp(up, UART_LCR, 0xbf);
1569
1570 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1571 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1572 serial_outp(up, UART_TRG, UART_TRG_96);
1573 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1574 serial_outp(up, UART_TRG, UART_TRG_96);
1575
1576 serial_outp(up, UART_LCR, 0);
1577 }
1578
1579 /*
1580 * If the "interrupt" for this port doesn't correspond with any
1581 * hardware interrupt, we use a timer-based system. The original
1582 * driver used to do this with IRQ0.
1583 */
1584 if (!is_real_interrupt(up->port.irq)) {
1585 unsigned int timeout = up->port.timeout;
1586
1587 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1588
1589 up->timer.data = (unsigned long)up;
1590 mod_timer(&up->timer, jiffies + timeout);
1591 } else {
1592 retval = serial_link_irq_chain(up);
1593 if (retval)
1594 return retval;
1595 }
1596
1597 /*
1598 * Now, initialize the UART
1599 */
1600 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1601
1602 spin_lock_irqsave(&up->port.lock, flags);
1603 if (up->port.flags & UPF_FOURPORT) {
1604 if (!is_real_interrupt(up->port.irq))
1605 up->port.mctrl |= TIOCM_OUT1;
1606 } else
1607 /*
1608 * Most PC uarts need OUT2 raised to enable interrupts.
1609 */
1610 if (is_real_interrupt(up->port.irq))
1611 up->port.mctrl |= TIOCM_OUT2;
1612
1613 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1614
1615 /*
1616 * Do a quick test to see if we receive an
1617 * interrupt when we enable the TX irq.
1618 */
1619 serial_outp(up, UART_IER, UART_IER_THRI);
1620 lsr = serial_in(up, UART_LSR);
1621 iir = serial_in(up, UART_IIR);
1622 serial_outp(up, UART_IER, 0);
1623
1624 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1625 if (!(up->bugs & UART_BUG_TXEN)) {
1626 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1627 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1628 port->line);
1629 }
1630 } else {
67f7654e 1631 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1632 }
1633
1da177e4
LT		 1634 spin_unlock_irqrestore(&up->port.lock, flags);
1635
1636 /*
1637 * Finally, enable interrupts. Note: Modem status interrupts
1638 * are set via set_termios(), which will be occurring imminently
1639 * anyway, so we don't enable them here.
1640 */
1641 up->ier = UART_IER_RLSI | UART_IER_RDI;
1642 serial_outp(up, UART_IER, up->ier);
1643
1644 if (up->port.flags & UPF_FOURPORT) {
1645 unsigned int icp;
1646 /*
1647 * Enable interrupts on the AST Fourport board
1648 */
1649 icp = (up->port.iobase & 0xfe0) | 0x01f;
1650 outb_p(0x80, icp);
1651 (void) inb_p(icp);
1652 }
1653
1654 /*
1655 * And clear the interrupt registers again for luck.
1656 */
1657 (void) serial_inp(up, UART_LSR);
1658 (void) serial_inp(up, UART_RX);
1659 (void) serial_inp(up, UART_IIR);
1660 (void) serial_inp(up, UART_MSR);
1661
1662 return 0;
1663}
1664
1665static void serial8250_shutdown(struct uart_port *port)
1666{
1667 struct uart_8250_port *up = (struct uart_8250_port *)port;
1668 unsigned long flags;
1669
1670 /*
1671 * Disable interrupts from this port
1672 */
1673 up->ier = 0;
1674 serial_outp(up, UART_IER, 0);
1675
1676 spin_lock_irqsave(&up->port.lock, flags);
1677 if (up->port.flags & UPF_FOURPORT) {
1678 /* reset interrupts on the AST Fourport board */
1679 inb((up->port.iobase & 0xfe0) | 0x1f);
1680 up->port.mctrl |= TIOCM_OUT1;
1681 } else
1682 up->port.mctrl &= ~TIOCM_OUT2;
1683
1684 serial8250_set_mctrl(&up->port, up->port.mctrl);
1685 spin_unlock_irqrestore(&up->port.lock, flags);
1686
1687 /*
1688 * Disable break condition and FIFOs
1689 */
1690 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1691 serial8250_clear_fifos(up);
1692
1693#ifdef CONFIG_SERIAL_8250_RSA
1694 /*
1695 * Reset the RSA board back to 115kbps compat mode.
1696 */
1697 disable_rsa(up);
1698#endif
1699
1700 /*
1701 * Read data port to reset things, and then unlink from
1702 * the IRQ chain.
1703 */
1704 (void) serial_in(up, UART_RX);
1705
1706 if (!is_real_interrupt(up->port.irq))
1707 del_timer_sync(&up->timer);
1708 else
1709 serial_unlink_irq_chain(up);
1710}
1711
1712static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1713{
1714 unsigned int quot;
1715
1716 /*
1717 * Handle magic divisors for baud rates above baud_base on
1718 * SMSC SuperIO chips.
1719 */
1720 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1721 baud == (port->uartclk/4))
1722 quot = 0x8001;
1723 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1724 baud == (port->uartclk/8))
1725 quot = 0x8002;
1726 else
1727 quot = uart_get_divisor(port, baud);
1728
1729 return quot;
1730}
1731
1732static void
1733serial8250_set_termios(struct uart_port *port, struct termios *termios,
1734 struct termios *old)
1735{
1736 struct uart_8250_port *up = (struct uart_8250_port *)port;
1737 unsigned char cval, fcr = 0;
1738 unsigned long flags;
1739 unsigned int baud, quot;
1740
1741 switch (termios->c_cflag & CSIZE) {
1742 case CS5:
0a8b80c5 1743 cval = UART_LCR_WLEN5;
1da177e4
LT		 1744 break;
1745 case CS6:
0a8b80c5 1746 cval = UART_LCR_WLEN6;
1da177e4
LT		 1747 break;
1748 case CS7:
0a8b80c5 1749 cval = UART_LCR_WLEN7;
1da177e4
LT		 1750 break;
1751 default:
1752 case CS8:
0a8b80c5 1753 cval = UART_LCR_WLEN8;
1da177e4
LT		 1754 break;
1755 }
1756
1757 if (termios->c_cflag & CSTOPB)
0a8b80c5 1758 cval |= UART_LCR_STOP;
1da177e4
LT		 1759 if (termios->c_cflag & PARENB)
1760 cval |= UART_LCR_PARITY;
1761 if (!(termios->c_cflag & PARODD))
1762 cval |= UART_LCR_EPAR;
1763#ifdef CMSPAR
1764 if (termios->c_cflag & CMSPAR)
1765 cval |= UART_LCR_SPAR;
1766#endif
1767
1768 /*
1769 * Ask the core to calculate the divisor for us.
1770 */
1771 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1772 quot = serial8250_get_divisor(port, baud);
1773
1774 /*
4ba5e35d 1775 * Oxford Semi 952 rev B workaround
1da177e4 1776 */
4ba5e35d 1777 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1778 quot ++;
1779
1780 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1781 if (baud < 2400)
1782 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1783 else
1784 fcr = uart_config[up->port.type].fcr;
1785 }
1786
1787 /*
1788 * MCR-based auto flow control. When AFE is enabled, RTS will be
1789 * deasserted when the receive FIFO contains more characters than
1790 * the trigger, or the MCR RTS bit is cleared. In the case where
1791 * the remote UART is not using CTS auto flow control, we must
1792 * have sufficient FIFO entries for the latency of the remote
1793 * UART to respond. IOW, at least 32 bytes of FIFO.
1794 */
1795 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1796 up->mcr &= ~UART_MCR_AFE;
1797 if (termios->c_cflag & CRTSCTS)
1798 up->mcr |= UART_MCR_AFE;
1799 }
1800
1801 /*
1802 * Ok, we're now changing the port state. Do it with
1803 * interrupts disabled.
1804 */
1805 spin_lock_irqsave(&up->port.lock, flags);
1806
1807 /*
1808 * Update the per-port timeout.
1809 */
1810 uart_update_timeout(port, termios->c_cflag, baud);
1811
1812 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1813 if (termios->c_iflag & INPCK)
1814 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1815 if (termios->c_iflag & (BRKINT | PARMRK))
1816 up->port.read_status_mask |= UART_LSR_BI;
1817
1818 /*
1819 * Characteres to ignore
1820 */
1821 up->port.ignore_status_mask = 0;
1822 if (termios->c_iflag & IGNPAR)
1823 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1824 if (termios->c_iflag & IGNBRK) {
1825 up->port.ignore_status_mask |= UART_LSR_BI;
1826 /*
1827 * If we're ignoring parity and break indicators,
1828 * ignore overruns too (for real raw support).
1829 */
1830 if (termios->c_iflag & IGNPAR)
1831 up->port.ignore_status_mask |= UART_LSR_OE;
1832 }
1833
1834 /*
1835 * ignore all characters if CREAD is not set
1836 */
1837 if ((termios->c_cflag & CREAD) == 0)
1838 up->port.ignore_status_mask |= UART_LSR_DR;
1839
1840 /*
1841 * CTS flow control flag and modem status interrupts
1842 */
1843 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1844 if (!(up->bugs & UART_BUG_NOMSR) &&
1845 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1846 up->ier |= UART_IER_MSI;
1847 if (up->capabilities & UART_CAP_UUE)
1848 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1849
1850 serial_out(up, UART_IER, up->ier);
1851
1852 if (up->capabilities & UART_CAP_EFR) {
1853 unsigned char efr = 0;
1854 /*
1855 * TI16C752/Startech hardware flow control. FIXME:
1856 * - TI16C752 requires control thresholds to be set.
1857 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1858 */
1859 if (termios->c_cflag & CRTSCTS)
1860 efr |= UART_EFR_CTS;
1861
1862 serial_outp(up, UART_LCR, 0xBF);
1863 serial_outp(up, UART_EFR, efr);
1864 }
1865
1866 if (up->capabilities & UART_NATSEMI) {
1867 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1868 serial_outp(up, UART_LCR, 0xe0);
1869 } else {
1870 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1871 }
1872
1873 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1874 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1875
1876 /*
1877 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1878 * is written without DLAB set, this mode will be disabled.
1879 */
1880 if (up->port.type == PORT_16750)
1881 serial_outp(up, UART_FCR, fcr);
1882
1883 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1884 up->lcr = cval; /* Save LCR */
1885 if (up->port.type != PORT_16750) {
1886 if (fcr & UART_FCR_ENABLE_FIFO) {
1887 /* emulated UARTs (Lucent Venus 167x) need two steps */
1888 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1889 }
1890 serial_outp(up, UART_FCR, fcr); /* set fcr */
1891 }
1892 serial8250_set_mctrl(&up->port, up->port.mctrl);
1893 spin_unlock_irqrestore(&up->port.lock, flags);
1894}
1895
1896static void
1897serial8250_pm(struct uart_port *port, unsigned int state,
1898 unsigned int oldstate)
1899{
1900 struct uart_8250_port *p = (struct uart_8250_port *)port;
1901
1902 serial8250_set_sleep(p, state != 0);
1903
1904 if (p->pm)
1905 p->pm(port, state, oldstate);
1906}
1907
1908/*
1909 * Resource handling.
1910 */
1911static int serial8250_request_std_resource(struct uart_8250_port *up)
1912{
1913 unsigned int size = 8 << up->port.regshift;
1914 int ret = 0;
1915
1916 switch (up->port.iotype) {
1917 case UPIO_MEM:
1918 if (!up->port.mapbase)
1919 break;
1920
1921 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1922 ret = -EBUSY;
1923 break;
1924 }
1925
1926 if (up->port.flags & UPF_IOREMAP) {
1927 up->port.membase = ioremap(up->port.mapbase, size);
1928 if (!up->port.membase) {
1929 release_mem_region(up->port.mapbase, size);
1930 ret = -ENOMEM;
1931 }
1932 }
1933 break;
1934
1935 case UPIO_HUB6:
1936 case UPIO_PORT:
1937 if (!request_region(up->port.iobase, size, "serial"))
1938 ret = -EBUSY;
1939 break;
1940 }
1941 return ret;
1942}
1943
1944static void serial8250_release_std_resource(struct uart_8250_port *up)
1945{
1946 unsigned int size = 8 << up->port.regshift;
1947
1948 switch (up->port.iotype) {
1949 case UPIO_MEM:
1950 if (!up->port.mapbase)
1951 break;
1952
1953 if (up->port.flags & UPF_IOREMAP) {
1954 iounmap(up->port.membase);
1955 up->port.membase = NULL;
1956 }
1957
1958 release_mem_region(up->port.mapbase, size);
1959 break;
1960
1961 case UPIO_HUB6:
1962 case UPIO_PORT:
1963 release_region(up->port.iobase, size);
1964 break;
1965 }
1966}
1967
1968static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1969{
1970 unsigned long start = UART_RSA_BASE << up->port.regshift;
1971 unsigned int size = 8 << up->port.regshift;
1972 int ret = 0;
1973
1974 switch (up->port.iotype) {
1975 case UPIO_MEM:
1976 ret = -EINVAL;
1977 break;
1978
1979 case UPIO_HUB6:
1980 case UPIO_PORT:
1981 start += up->port.iobase;
1982 if (!request_region(start, size, "serial-rsa"))
1983 ret = -EBUSY;
1984 break;
1985 }
1986
1987 return ret;
1988}
1989
1990static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1991{
1992 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1993 unsigned int size = 8 << up->port.regshift;
1994
1995 switch (up->port.iotype) {
1996 case UPIO_MEM:
1997 break;
1998
1999 case UPIO_HUB6:
2000 case UPIO_PORT:
2001 release_region(up->port.iobase + offset, size);
2002 break;
2003 }
2004}
2005
2006static void serial8250_release_port(struct uart_port *port)
2007{
2008 struct uart_8250_port *up = (struct uart_8250_port *)port;
2009
2010 serial8250_release_std_resource(up);
2011 if (up->port.type == PORT_RSA)
2012 serial8250_release_rsa_resource(up);
2013}
2014
2015static int serial8250_request_port(struct uart_port *port)
2016{
2017 struct uart_8250_port *up = (struct uart_8250_port *)port;
2018 int ret = 0;
2019
2020 ret = serial8250_request_std_resource(up);
2021 if (ret == 0 && up->port.type == PORT_RSA) {
2022 ret = serial8250_request_rsa_resource(up);
2023 if (ret < 0)
2024 serial8250_release_std_resource(up);
2025 }
2026
2027 return ret;
2028}
2029
2030static void serial8250_config_port(struct uart_port *port, int flags)
2031{
2032 struct uart_8250_port *up = (struct uart_8250_port *)port;
2033 int probeflags = PROBE_ANY;
2034 int ret;
2035
2036 /*
2037 * Don't probe for MCA ports on non-MCA machines.
2038 */
2039 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
2040 return;
2041
2042 /*
2043 * Find the region that we can probe for. This in turn
2044 * tells us whether we can probe for the type of port.
2045 */
2046 ret = serial8250_request_std_resource(up);
2047 if (ret < 0)
2048 return;
2049
2050 ret = serial8250_request_rsa_resource(up);
2051 if (ret < 0)
2052 probeflags &= ~PROBE_RSA;
2053
2054 if (flags & UART_CONFIG_TYPE)
2055 autoconfig(up, probeflags);
2056 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2057 autoconfig_irq(up);
2058
2059 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2060 serial8250_release_rsa_resource(up);
2061 if (up->port.type == PORT_UNKNOWN)
2062 serial8250_release_std_resource(up);
2063}
2064
2065static int
2066serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2067{
2068 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2069 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2070 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2071 ser->type == PORT_STARTECH)
2072 return -EINVAL;
2073 return 0;
2074}
2075
2076static const char *
2077serial8250_type(struct uart_port *port)
2078{
2079 int type = port->type;
2080
2081 if (type >= ARRAY_SIZE(uart_config))
2082 type = 0;
2083 return uart_config[type].name;
2084}
2085
2086static struct uart_ops serial8250_pops = {
2087 .tx_empty = serial8250_tx_empty,
2088 .set_mctrl = serial8250_set_mctrl,
2089 .get_mctrl = serial8250_get_mctrl,
2090 .stop_tx = serial8250_stop_tx,
2091 .start_tx = serial8250_start_tx,
2092 .stop_rx = serial8250_stop_rx,
2093 .enable_ms = serial8250_enable_ms,
2094 .break_ctl = serial8250_break_ctl,
2095 .startup = serial8250_startup,
2096 .shutdown = serial8250_shutdown,
2097 .set_termios = serial8250_set_termios,
2098 .pm = serial8250_pm,
2099 .type = serial8250_type,
2100 .release_port = serial8250_release_port,
2101 .request_port = serial8250_request_port,
2102 .config_port = serial8250_config_port,
2103 .verify_port = serial8250_verify_port,
2104};
2105
2106static struct uart_8250_port serial8250_ports[UART_NR];
2107
2108static void __init serial8250_isa_init_ports(void)
2109{
2110 struct uart_8250_port *up;
2111 static int first = 1;
2112 int i;
2113
2114 if (!first)
2115 return;
2116 first = 0;
2117
2118 for (i = 0; i < UART_NR; i++) {
2119 struct uart_8250_port *up = &serial8250_ports[i];
2120
2121 up->port.line = i;
2122 spin_lock_init(&up->port.lock);
2123
2124 init_timer(&up->timer);
2125 up->timer.function = serial8250_timeout;
2126
2127 /*
2128 * ALPHA_KLUDGE_MCR needs to be killed.
2129 */
2130 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2131 up->mcr_force = ALPHA_KLUDGE_MCR;
2132
2133 up->port.ops = &serial8250_pops;
2134 }
2135
44454bcd
RK		 2136 for (i = 0, up = serial8250_ports;
2137 i < ARRAY_SIZE(old_serial_port) && i < UART_NR;
1da177e4
LT		 2138 i++, up++) {
2139 up->port.iobase = old_serial_port[i].port;
2140 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2141 up->port.uartclk = old_serial_port[i].baud_base * 16;
2142 up->port.flags = old_serial_port[i].flags;
2143 up->port.hub6 = old_serial_port[i].hub6;
2144 up->port.membase = old_serial_port[i].iomem_base;
2145 up->port.iotype = old_serial_port[i].io_type;
2146 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2147 if (share_irqs)
2148 up->port.flags |= UPF_SHARE_IRQ;
2149 }
2150}
2151
2152static void __init
2153serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2154{
2155 int i;
2156
2157 serial8250_isa_init_ports();
2158
2159 for (i = 0; i < UART_NR; i++) {
2160 struct uart_8250_port *up = &serial8250_ports[i];
2161
2162 up->port.dev = dev;
2163 uart_add_one_port(drv, &up->port);
2164 }
2165}
2166
2167#ifdef CONFIG_SERIAL_8250_CONSOLE
2168
2169#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2170
2171/*
2172 * Wait for transmitter & holding register to empty
2173 */
2174static inline void wait_for_xmitr(struct uart_8250_port *up)
2175{
2176 unsigned int status, tmout = 10000;
2177
2178 /* Wait up to 10ms for the character(s) to be sent. */
2179 do {
2180 status = serial_in(up, UART_LSR);
2181
2182 if (status & UART_LSR_BI)
2183 up->lsr_break_flag = UART_LSR_BI;
2184
2185 if (--tmout == 0)
2186 break;
2187 udelay(1);
2188 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2189
2190 /* Wait up to 1s for flow control if necessary */
2191 if (up->port.flags & UPF_CONS_FLOW) {
2192 tmout = 1000000;
2193 while (--tmout &&
2194 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2195 udelay(1);
2196 }
2197}
2198
2199/*
2200 * Print a string to the serial port trying not to disturb
2201 * any possible real use of the port...
2202 *
2203 * The console_lock must be held when we get here.
2204 */
2205static void
2206serial8250_console_write(struct console *co, const char *s, unsigned int count)
2207{
2208 struct uart_8250_port *up = &serial8250_ports[co->index];
2209 unsigned int ier;
2210 int i;
2211
78512ece
AM		 2212 touch_nmi_watchdog();
2213
1da177e4
LT		 2214 /*
2215 * First save the UER then disable the interrupts
2216 */
2217 ier = serial_in(up, UART_IER);
2218
2219 if (up->capabilities & UART_CAP_UUE)
2220 serial_out(up, UART_IER, UART_IER_UUE);
2221 else
2222 serial_out(up, UART_IER, 0);
2223
2224 /*
2225 * Now, do each character
2226 */
2227 for (i = 0; i < count; i++, s++) {
2228 wait_for_xmitr(up);
2229
2230 /*
2231 * Send the character out.
2232 * If a LF, also do CR...
2233 */
2234 serial_out(up, UART_TX, *s);
2235 if (*s == 10) {
2236 wait_for_xmitr(up);
2237 serial_out(up, UART_TX, 13);
2238 }
2239 }
2240
2241 /*
2242 * Finally, wait for transmitter to become empty
2243 * and restore the IER
2244 */
2245 wait_for_xmitr(up);
2246 serial_out(up, UART_IER, ier);
2247}
2248
2249static int serial8250_console_setup(struct console *co, char *options)
2250{
2251 struct uart_port *port;
2252 int baud = 9600;
2253 int bits = 8;
2254 int parity = 'n';
2255 int flow = 'n';
2256
2257 /*
2258 * Check whether an invalid uart number has been specified, and
2259 * if so, search for the first available port that does have
2260 * console support.
2261 */
2262 if (co->index >= UART_NR)
2263 co->index = 0;
2264 port = &serial8250_ports[co->index].port;
2265 if (!port->iobase && !port->membase)
2266 return -ENODEV;
2267
2268 if (options)
2269 uart_parse_options(options, &baud, &parity, &bits, &flow);
2270
2271 return uart_set_options(port, co, baud, parity, bits, flow);
2272}
2273
2274static struct uart_driver serial8250_reg;
2275static struct console serial8250_console = {
2276 .name = "ttyS",
2277 .write = serial8250_console_write,
2278 .device = uart_console_device,
2279 .setup = serial8250_console_setup,
2280 .flags = CON_PRINTBUFFER,
2281 .index = -1,
2282 .data = &serial8250_reg,
2283};
2284
2285static int __init serial8250_console_init(void)
2286{
2287 serial8250_isa_init_ports();
2288 register_console(&serial8250_console);
2289 return 0;
2290}
2291console_initcall(serial8250_console_init);
2292
2293static int __init find_port(struct uart_port *p)
2294{
2295 int line;
2296 struct uart_port *port;
2297
2298 for (line = 0; line < UART_NR; line++) {
2299 port = &serial8250_ports[line].port;
2300 if (p->iotype == port->iotype &&
2301 p->iobase == port->iobase &&
2302 p->membase == port->membase)
2303 return line;
2304 }
2305 return -ENODEV;
2306}
2307
2308int __init serial8250_start_console(struct uart_port *port, char *options)
2309{
2310 int line;
2311
2312 line = find_port(port);
2313 if (line < 0)
2314 return -ENODEV;
2315
2316 add_preferred_console("ttyS", line, options);
2317 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2318 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2319 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2320 (unsigned long) port->iobase, options);
2321 if (!(serial8250_console.flags & CON_ENABLED)) {
2322 serial8250_console.flags &= ~CON_PRINTBUFFER;
2323 register_console(&serial8250_console);
2324 }
2325 return line;
2326}
2327
2328#define SERIAL8250_CONSOLE &serial8250_console
2329#else
2330#define SERIAL8250_CONSOLE NULL
2331#endif
2332
2333static struct uart_driver serial8250_reg = {
2334 .owner = THIS_MODULE,
2335 .driver_name = "serial",
2336 .devfs_name = "tts/",
2337 .dev_name = "ttyS",
2338 .major = TTY_MAJOR,
2339 .minor = 64,
2340 .nr = UART_NR,
2341 .cons = SERIAL8250_CONSOLE,
2342};
2343
2344int __init early_serial_setup(struct uart_port *port)
2345{
2346 if (port->line >= ARRAY_SIZE(serial8250_ports))
2347 return -ENODEV;
2348
2349 serial8250_isa_init_ports();
2350 serial8250_ports[port->line].port = *port;
2351 serial8250_ports[port->line].port.ops = &serial8250_pops;
2352 return 0;
2353}
2354
2355/**
2356 * serial8250_suspend_port - suspend one serial port
2357 * @line: serial line number
2358 * @level: the level of port suspension, as per uart_suspend_port
2359 *
2360 * Suspend one serial port.
2361 */
2362void serial8250_suspend_port(int line)
2363{
2364 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2365}
2366
2367/**
2368 * serial8250_resume_port - resume one serial port
2369 * @line: serial line number
2370 * @level: the level of port resumption, as per uart_resume_port
2371 *
2372 * Resume one serial port.
2373 */
2374void serial8250_resume_port(int line)
2375{
2376 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2377}
2378
2379/*
2380 * Register a set of serial devices attached to a platform device. The
2381 * list is terminated with a zero flags entry, which means we expect
2382 * all entries to have at least UPF_BOOT_AUTOCONF set.
2383 */
2384static int __devinit serial8250_probe(struct device *dev)
2385{
2386 struct plat_serial8250_port *p = dev->platform_data;
2387 struct uart_port port;
ec9f47cd 2388 int ret, i;
1da177e4
LT		 2389
2390 memset(&port, 0, sizeof(struct uart_port));
2391
ec9f47cd 2392 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2393 port.iobase = p->iobase;
2394 port.membase = p->membase;
2395 port.irq = p->irq;
2396 port.uartclk = p->uartclk;
2397 port.regshift = p->regshift;
2398 port.iotype = p->iotype;
2399 port.flags = p->flags;
2400 port.mapbase = p->mapbase;
ec9f47cd 2401 port.hub6 = p->hub6;
1da177e4
LT		 2402 port.dev = dev;
2403 if (share_irqs)
2404 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2405 ret = serial8250_register_port(&port);
2406 if (ret < 0) {
2407 dev_err(dev, "unable to register port at index %d "
2408 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2409 p->iobase, p->mapbase, p->irq, ret);
2410 }
1da177e4
LT		 2411 }
2412 return 0;
2413}
2414
2415/*
2416 * Remove serial ports registered against a platform device.
2417 */
2418static int __devexit serial8250_remove(struct device *dev)
2419{
2420 int i;
2421
2422 for (i = 0; i < UART_NR; i++) {
2423 struct uart_8250_port *up = &serial8250_ports[i];
2424
2425 if (up->port.dev == dev)
2426 serial8250_unregister_port(i);
2427 }
2428 return 0;
2429}
2430
9480e307 2431static int serial8250_suspend(struct device *dev, pm_message_t state)
1da177e4
LT		 2432{
2433 int i;
2434
1da177e4
LT		 2435 for (i = 0; i < UART_NR; i++) {
2436 struct uart_8250_port *up = &serial8250_ports[i];
2437
2438 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2439 uart_suspend_port(&serial8250_reg, &up->port);
2440 }
2441
2442 return 0;
2443}
2444
9480e307 2445static int serial8250_resume(struct device *dev)
1da177e4
LT		 2446{
2447 int i;
2448
1da177e4
LT		 2449 for (i = 0; i < UART_NR; i++) {
2450 struct uart_8250_port *up = &serial8250_ports[i];
2451
2452 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2453 uart_resume_port(&serial8250_reg, &up->port);
2454 }
2455
2456 return 0;
2457}
2458
2459static struct device_driver serial8250_isa_driver = {
2460 .name = "serial8250",
2461 .bus = &platform_bus_type,
2462 .probe = serial8250_probe,
2463 .remove = __devexit_p(serial8250_remove),
2464 .suspend = serial8250_suspend,
2465 .resume = serial8250_resume,
2466};
2467
2468/*
2469 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2470 * in the table in include/asm/serial.h
2471 */
2472static struct platform_device *serial8250_isa_devs;
2473
2474/*
2475 * serial8250_register_port and serial8250_unregister_port allows for
2476 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2477 * modems and PCI multiport cards.
2478 */
2479static DECLARE_MUTEX(serial_sem);
2480
2481static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2482{
2483 int i;
2484
2485 /*
2486 * First, find a port entry which matches.
2487 */
2488 for (i = 0; i < UART_NR; i++)
2489 if (uart_match_port(&serial8250_ports[i].port, port))
2490 return &serial8250_ports[i];
2491
2492 /*
2493 * We didn't find a matching entry, so look for the first
2494 * free entry. We look for one which hasn't been previously
2495 * used (indicated by zero iobase).
2496 */
2497 for (i = 0; i < UART_NR; i++)
2498 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2499 serial8250_ports[i].port.iobase == 0)
2500 return &serial8250_ports[i];
2501
2502 /*
2503 * That also failed. Last resort is to find any entry which
2504 * doesn't have a real port associated with it.
2505 */
2506 for (i = 0; i < UART_NR; i++)
2507 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2508 return &serial8250_ports[i];
2509
2510 return NULL;
2511}
2512
2513/**
2514 * serial8250_register_port - register a serial port
2515 * @port: serial port template
2516 *
2517 * Configure the serial port specified by the request. If the
2518 * port exists and is in use, it is hung up and unregistered
2519 * first.
2520 *
2521 * The port is then probed and if necessary the IRQ is autodetected
2522 * If this fails an error is returned.
2523 *
2524 * On success the port is ready to use and the line number is returned.
2525 */
2526int serial8250_register_port(struct uart_port *port)
2527{
2528 struct uart_8250_port *uart;
2529 int ret = -ENOSPC;
2530
2531 if (port->uartclk == 0)
2532 return -EINVAL;
2533
2534 down(&serial_sem);
2535
2536 uart = serial8250_find_match_or_unused(port);
2537 if (uart) {
2538 uart_remove_one_port(&serial8250_reg, &uart->port);
2539
2540 uart->port.iobase = port->iobase;
2541 uart->port.membase = port->membase;
2542 uart->port.irq = port->irq;
2543 uart->port.uartclk = port->uartclk;
2544 uart->port.fifosize = port->fifosize;
2545 uart->port.regshift = port->regshift;
2546 uart->port.iotype = port->iotype;
2547 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2548 uart->port.mapbase = port->mapbase;
2549 if (port->dev)
2550 uart->port.dev = port->dev;
2551
2552 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2553 if (ret == 0)
2554 ret = uart->port.line;
2555 }
2556 up(&serial_sem);
2557
2558 return ret;
2559}
2560EXPORT_SYMBOL(serial8250_register_port);
2561
2562/**
2563 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2564 * @line: serial line number
2565 *
2566 * Remove one serial port. This may not be called from interrupt
2567 * context. We hand the port back to the our control.
2568 */
2569void serial8250_unregister_port(int line)
2570{
2571 struct uart_8250_port *uart = &serial8250_ports[line];
2572
2573 down(&serial_sem);
2574 uart_remove_one_port(&serial8250_reg, &uart->port);
2575 if (serial8250_isa_devs) {
2576 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2577 uart->port.type = PORT_UNKNOWN;
2578 uart->port.dev = &serial8250_isa_devs->dev;
2579 uart_add_one_port(&serial8250_reg, &uart->port);
2580 } else {
2581 uart->port.dev = NULL;
2582 }
2583 up(&serial_sem);
2584}
2585EXPORT_SYMBOL(serial8250_unregister_port);
2586
2587static int __init serial8250_init(void)
2588{
2589 int ret, i;
2590
2591 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2592 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2593 share_irqs ? "en" : "dis");
2594
2595 for (i = 0; i < NR_IRQS; i++)
2596 spin_lock_init(&irq_lists[i].lock);
2597
2598 ret = uart_register_driver(&serial8250_reg);
2599 if (ret)
2600 goto out;
2601
2602 serial8250_isa_devs = platform_device_register_simple("serial8250",
6df29deb 2603 PLAT8250_DEV_LEGACY, NULL, 0);
1da177e4
LT		 2604 if (IS_ERR(serial8250_isa_devs)) {
2605 ret = PTR_ERR(serial8250_isa_devs);
2606 goto unreg;
2607 }
2608
2609 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2610
2611 ret = driver_register(&serial8250_isa_driver);
2612 if (ret == 0)
2613 goto out;
2614
2615 platform_device_unregister(serial8250_isa_devs);
2616 unreg:
2617 uart_unregister_driver(&serial8250_reg);
2618 out:
2619 return ret;
2620}
2621
2622static void __exit serial8250_exit(void)
2623{
2624 struct platform_device *isa_dev = serial8250_isa_devs;
2625
2626 /*
2627 * This tells serial8250_unregister_port() not to re-register
2628 * the ports (thereby making serial8250_isa_driver permanently
2629 * in use.)
2630 */
2631 serial8250_isa_devs = NULL;
2632
2633 driver_unregister(&serial8250_isa_driver);
2634 platform_device_unregister(isa_dev);
2635
2636 uart_unregister_driver(&serial8250_reg);
2637}
2638
2639module_init(serial8250_init);
2640module_exit(serial8250_exit);
2641
2642EXPORT_SYMBOL(serial8250_suspend_port);
2643EXPORT_SYMBOL(serial8250_resume_port);
2644
2645MODULE_LICENSE("GPL");
2646MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2647
2648module_param(share_irqs, uint, 0644);
2649MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2650 " (unsafe)");
2651
2652#ifdef CONFIG_SERIAL_8250_RSA
2653module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2654MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2655#endif
2656MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux 6.x block layer and io_uring tree(s)