[linux-2.6-block.git] / drivers / scsi / wd33c93.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *    wd33c93.h -  Linux device driver definitions for the
 *                 Commodore Amiga A2091/590 SCSI controller card
 *
 *    IMPORTANT: This file is for version 1.25 - 09/Jul/1997
 *
 * Copyright (c) 1996 John Shifflett, GeoLog Consulting
 *    john@geolog.com
 *    jshiffle@netcom.com
 */
#ifndef WD33C93_H
#define WD33C93_H


#define PROC_INTERFACE     /* add code for /proc/scsi/wd33c93/xxx interface */
#ifdef  PROC_INTERFACE
#define PROC_STATISTICS    /* add code for keeping various real time stats */
#endif

#define SYNC_DEBUG         /* extra info on sync negotiation printed */
#define DEBUGGING_ON       /* enable command-line debugging bitmask */
#define DEBUG_DEFAULTS 0   /* default debugging bitmask */


#ifdef DEBUGGING_ON
#define DB(f,a) if (hostdata->args & (f)) a;
#else
#define DB(f,a)
#endif

#define uchar unsigned char


/* wd register names */
#define WD_OWN_ID    0x00
#define WD_CONTROL      0x01
#define WD_TIMEOUT_PERIOD  0x02
#define WD_CDB_1     0x03
#define WD_CDB_2     0x04
#define WD_CDB_3     0x05
#define WD_CDB_4     0x06
#define WD_CDB_5     0x07
#define WD_CDB_6     0x08
#define WD_CDB_7     0x09
#define WD_CDB_8     0x0a
#define WD_CDB_9     0x0b
#define WD_CDB_10    0x0c
#define WD_CDB_11    0x0d
#define WD_CDB_12    0x0e
#define WD_TARGET_LUN      0x0f
#define WD_COMMAND_PHASE   0x10
#define WD_SYNCHRONOUS_TRANSFER 0x11
#define WD_TRANSFER_COUNT_MSB 0x12
#define WD_TRANSFER_COUNT  0x13
#define WD_TRANSFER_COUNT_LSB 0x14
#define WD_DESTINATION_ID  0x15
#define WD_SOURCE_ID    0x16
#define WD_SCSI_STATUS     0x17
#define WD_COMMAND      0x18
#define WD_DATA      0x19
#define WD_QUEUE_TAG    0x1a
#define WD_AUXILIARY_STATUS   0x1f

/* WD commands */
#define WD_CMD_RESET    0x00
#define WD_CMD_ABORT    0x01
#define WD_CMD_ASSERT_ATN  0x02
#define WD_CMD_NEGATE_ACK  0x03
#define WD_CMD_DISCONNECT  0x04
#define WD_CMD_RESELECT    0x05
#define WD_CMD_SEL_ATN     0x06
#define WD_CMD_SEL      0x07
#define WD_CMD_SEL_ATN_XFER   0x08
#define WD_CMD_SEL_XFER    0x09
#define WD_CMD_RESEL_RECEIVE  0x0a
#define WD_CMD_RESEL_SEND  0x0b
#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
#define WD_CMD_TRANS_ADDR  0x18
#define WD_CMD_TRANS_INFO  0x20
#define WD_CMD_TRANSFER_PAD   0x21
#define WD_CMD_SBT_MODE    0x80

/* ASR register */
#define ASR_INT         (0x80)
#define ASR_LCI         (0x40)
#define ASR_BSY         (0x20)
#define ASR_CIP         (0x10)
#define ASR_PE          (0x02)
#define ASR_DBR         (0x01)

/* SCSI Bus Phases */
#define PHS_DATA_OUT    0x00
#define PHS_DATA_IN     0x01
#define PHS_COMMAND     0x02
#define PHS_STATUS      0x03
#define PHS_MESS_OUT    0x06
#define PHS_MESS_IN     0x07

/* Command Status Register definitions */

  /* reset state interrupts */
#define CSR_RESET    0x00
#define CSR_RESET_AF    0x01

  /* successful completion interrupts */
#define CSR_RESELECT    0x10
#define CSR_SELECT      0x11
#define CSR_SEL_XFER_DONE  0x16
#define CSR_XFER_DONE      0x18

  /* paused or aborted interrupts */
#define CSR_MSGIN    0x20
#define CSR_SDP         0x21
#define CSR_SEL_ABORT      0x22
#define CSR_RESEL_ABORT    0x25
#define CSR_RESEL_ABORT_AM 0x27
#define CSR_ABORT    0x28

  /* terminated interrupts */
#define CSR_INVALID     0x40
#define CSR_UNEXP_DISC     0x41
#define CSR_TIMEOUT     0x42
#define CSR_PARITY      0x43
#define CSR_PARITY_ATN     0x44
#define CSR_BAD_STATUS     0x45
#define CSR_UNEXP    0x48

  /* service required interrupts */
#define CSR_RESEL    0x80
#define CSR_RESEL_AM    0x81
#define CSR_DISC     0x85
#define CSR_SRV_REQ     0x88

   /* Own ID/CDB Size register */
#define OWNID_EAF    0x08
#define OWNID_EHP    0x10
#define OWNID_RAF    0x20
#define OWNID_FS_8   0x00
#define OWNID_FS_12  0x40
#define OWNID_FS_16  0x80

   /* define these so we don't have to change a2091.c, etc. */
#define WD33C93_FS_8_10  OWNID_FS_8
#define WD33C93_FS_12_15 OWNID_FS_12
#define WD33C93_FS_16_20 OWNID_FS_16

   /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
#define WD33C93_FS_MHZ(mhz) (mhz)

   /* Control register */
#define CTRL_HSP     0x01
#define CTRL_HA      0x02
#define CTRL_IDI     0x04
#define CTRL_EDI     0x08
#define CTRL_HHP     0x10
#define CTRL_POLLED  0x00
#define CTRL_BURST   0x20
#define CTRL_BUS     0x40
#define CTRL_DMA     0x80

   /* Timeout Period register */
#define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */

   /* Synchronous Transfer Register */
#define STR_FSS      0x80

   /* Destination ID register */
#define DSTID_DPD    0x40
#define DATA_OUT_DIR 0
#define DATA_IN_DIR  1
#define DSTID_SCC    0x80

   /* Source ID register */
#define SRCID_MASK   0x07
#define SRCID_SIV    0x08
#define SRCID_DSP    0x20
#define SRCID_ES     0x40
#define SRCID_ER     0x80

   /* This is what the 3393 chip looks like to us */
typedef struct {
#ifdef CONFIG_WD33C93_PIO
   unsigned int   SASR;
   unsigned int   SCMD;
#else
   volatile unsigned char  *SASR;
   volatile unsigned char  *SCMD;
#endif
} wd33c93_regs;


typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
typedef void (*dma_stop_t) (struct Scsi_Host *instance,
		struct scsi_cmnd *SCpnt, int status);


#define ILLEGAL_STATUS_BYTE   0xff

#define DEFAULT_SX_PER   376     /* (ns) fairly safe */
#define DEFAULT_SX_OFF   0       /* aka async */

#define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
#define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */

struct sx_period {
   unsigned int   period_ns;
   uchar          reg_value;
   };

/* FEF: defines for hostdata->dma_buffer_pool */

#define BUF_CHIP_ALLOCED 0
#define BUF_SCSI_ALLOCED 1

struct WD33C93_hostdata {
    struct Scsi_Host *next;
    wd33c93_regs     regs;
    spinlock_t       lock;
    uchar            clock_freq;
    uchar            chip;             /* what kind of wd33c93? */
    uchar            microcode;        /* microcode rev */
    uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
    int              dma_dir;          /* data transfer dir. */
    dma_setup_t      dma_setup;
    dma_stop_t       dma_stop;
    unsigned int     dma_xfer_mask;
    uchar            *dma_bounce_buffer;
    unsigned int     dma_bounce_len;
    volatile uchar   busy[8];          /* index = target, bit = lun */
    volatile struct scsi_cmnd *input_Q;       /* commands waiting to be started */
    volatile struct scsi_cmnd *selecting;     /* trying to select this command */
    volatile struct scsi_cmnd *connected;     /* currently connected command */
    volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
    uchar            state;            /* what we are currently doing */
    uchar            dma;              /* current state of DMA (on/off) */
    uchar            level2;           /* extent to which Level-2 commands are used */
    uchar            disconnect;       /* disconnect/reselect policy */
    unsigned int     args;             /* set from command-line argument */
    uchar            incoming_msg[8];  /* filled during message_in phase */
    int              incoming_ptr;     /* mainly used with EXTENDED messages */
    uchar            outgoing_msg[8];  /* send this during next message_out */
    int              outgoing_len;     /* length of outgoing message */
    unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
    uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
    uchar            sync_stat[8];     /* status of sync negotiation per target */
    uchar            no_sync;          /* bitmask: don't do sync on these targets */
    uchar            no_dma;           /* set this flag to disable DMA */
    uchar            dma_mode;         /* DMA Burst Mode or Single Byte DMA */
    uchar            fast;             /* set this flag to enable Fast SCSI */
    struct sx_period sx_table[9];      /* transfer periods for actual DTC-setting */
#ifdef PROC_INTERFACE
    uchar            proc;             /* bitmask: what's in proc output */
#ifdef PROC_STATISTICS
    unsigned long    cmd_cnt[8];       /* # of commands issued per target */
    unsigned long    int_cnt;          /* # of interrupts serviced */
    unsigned long    pio_cnt;          /* # of pio data transfers */
    unsigned long    dma_cnt;          /* # of DMA data transfers */
    unsigned long    disc_allowed_cnt[8]; /* # of disconnects allowed per target */
    unsigned long    disc_done_cnt[8]; /* # of disconnects done per target*/
#endif
#endif
    };


/* defines for hostdata->chip */

#define C_WD33C93       0
#define C_WD33C93A      1
#define C_WD33C93B      2
#define C_UNKNOWN_CHIP  100

/* defines for hostdata->state */

#define S_UNCONNECTED         0
#define S_SELECTING           1
#define S_RUNNING_LEVEL2      2
#define S_CONNECTED           3
#define S_PRE_TMP_DISC        4
#define S_PRE_CMP_DISC        5

/* defines for hostdata->dma */

#define D_DMA_OFF          0
#define D_DMA_RUNNING      1

/* defines for hostdata->level2 */
/* NOTE: only the first 3 are implemented so far */

#define L2_NONE      1  /* no combination commands - we get lots of ints */
#define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
#define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
#define L2_DATA      4  /* resume after DATA_IN/OUT ints */
#define L2_MOST      5  /* resume after anything except a RESELECT int */
#define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
#define L2_ALL       7  /* always resume */

/* defines for hostdata->disconnect */

#define DIS_NEVER    0
#define DIS_ADAPTIVE 1
#define DIS_ALWAYS   2

/* defines for hostdata->args */

#define DB_TEST1              1<<0
#define DB_TEST2              1<<1
#define DB_QUEUE_COMMAND      1<<2
#define DB_EXECUTE            1<<3
#define DB_INTR               1<<4
#define DB_TRANSFER           1<<5
#define DB_MASK               0x3f

/* defines for hostdata->sync_stat[] */

#define SS_UNSET     0
#define SS_FIRST     1
#define SS_WAITING   2
#define SS_SET       3

/* defines for hostdata->proc */

#define PR_VERSION   1<<0
#define PR_INFO      1<<1
#define PR_STATISTICS 1<<2
#define PR_CONNECTED 1<<3
#define PR_INPUTQ    1<<4
#define PR_DISCQ     1<<5
#define PR_TEST      1<<6
#define PR_STOP      1<<7


void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
         dma_setup_t setup, dma_stop_t stop, int clock_freq);
int wd33c93_abort (struct scsi_cmnd *cmd);
int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
void wd33c93_intr (struct Scsi_Host *instance);
int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
int wd33c93_write_info(struct Scsi_Host *, char *, int);
int wd33c93_host_reset (struct scsi_cmnd *);

#endif /* WD33C93_H */
Commit	Line	Data
3e0a4e85	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* wd33c93.h - Linux device driver definitions for the
	4	* Commodore Amiga A2091/590 SCSI controller card
	5	*
	6	* IMPORTANT: This file is for version 1.25 - 09/Jul/1997
	7	*
	8	* Copyright (c) 1996 John Shifflett, GeoLog Consulting
	9	* john@geolog.com
	10	* jshiffle@netcom.com
1da177e4 LT	11	*/
	12	#ifndef WD33C93_H
	13	#define WD33C93_H
	14
1da177e4 LT	15
	16	#define PROC_INTERFACE /* add code for /proc/scsi/wd33c93/xxx interface */
	17	#ifdef PROC_INTERFACE
	18	#define PROC_STATISTICS /* add code for keeping various real time stats */
	19	#endif
	20
	21	#define SYNC_DEBUG /* extra info on sync negotiation printed */
	22	#define DEBUGGING_ON /* enable command-line debugging bitmask */
	23	#define DEBUG_DEFAULTS 0 /* default debugging bitmask */
	24
	25
	26	#ifdef DEBUGGING_ON
	27	#define DB(f,a) if (hostdata->args & (f)) a;
	28	#else
	29	#define DB(f,a)
	30	#endif
	31
	32	#define uchar unsigned char
	33
	34
	35	/* wd register names */
	36	#define WD_OWN_ID 0x00
	37	#define WD_CONTROL 0x01
	38	#define WD_TIMEOUT_PERIOD 0x02
	39	#define WD_CDB_1 0x03
	40	#define WD_CDB_2 0x04
	41	#define WD_CDB_3 0x05
	42	#define WD_CDB_4 0x06
	43	#define WD_CDB_5 0x07
	44	#define WD_CDB_6 0x08
	45	#define WD_CDB_7 0x09
	46	#define WD_CDB_8 0x0a
	47	#define WD_CDB_9 0x0b
	48	#define WD_CDB_10 0x0c
	49	#define WD_CDB_11 0x0d
	50	#define WD_CDB_12 0x0e
	51	#define WD_TARGET_LUN 0x0f
	52	#define WD_COMMAND_PHASE 0x10
	53	#define WD_SYNCHRONOUS_TRANSFER 0x11
	54	#define WD_TRANSFER_COUNT_MSB 0x12
	55	#define WD_TRANSFER_COUNT 0x13
	56	#define WD_TRANSFER_COUNT_LSB 0x14
	57	#define WD_DESTINATION_ID 0x15
	58	#define WD_SOURCE_ID 0x16
	59	#define WD_SCSI_STATUS 0x17
	60	#define WD_COMMAND 0x18
	61	#define WD_DATA 0x19
	62	#define WD_QUEUE_TAG 0x1a
	63	#define WD_AUXILIARY_STATUS 0x1f
	64
	65	/* WD commands */
	66	#define WD_CMD_RESET 0x00
	67	#define WD_CMD_ABORT 0x01
	68	#define WD_CMD_ASSERT_ATN 0x02
	69	#define WD_CMD_NEGATE_ACK 0x03
	70	#define WD_CMD_DISCONNECT 0x04
	71	#define WD_CMD_RESELECT 0x05
	72	#define WD_CMD_SEL_ATN 0x06
	73	#define WD_CMD_SEL 0x07
	74	#define WD_CMD_SEL_ATN_XFER 0x08
	75	#define WD_CMD_SEL_XFER 0x09
	76	#define WD_CMD_RESEL_RECEIVE 0x0a
	77	#define WD_CMD_RESEL_SEND 0x0b
	78	#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
79	#define WD_CMD_TRANS_ADDR 0x18
80	#define WD_CMD_TRANS_INFO 0x20
81	#define WD_CMD_TRANSFER_PAD 0x21
82	#define WD_CMD_SBT_MODE 0x80
83
84	/* ASR register */
85	#define ASR_INT (0x80)
86	#define ASR_LCI (0x40)
87	#define ASR_BSY (0x20)
88	#define ASR_CIP (0x10)
89	#define ASR_PE (0x02)
90	#define ASR_DBR (0x01)
91
92	/* SCSI Bus Phases */
93	#define PHS_DATA_OUT 0x00
94	#define PHS_DATA_IN 0x01
95	#define PHS_COMMAND 0x02
96	#define PHS_STATUS 0x03
97	#define PHS_MESS_OUT 0x06
98	#define PHS_MESS_IN 0x07
99
100	/* Command Status Register definitions */
101
102	/* reset state interrupts */
103	#define CSR_RESET 0x00
104	#define CSR_RESET_AF 0x01
105
106	/* successful completion interrupts */
107	#define CSR_RESELECT 0x10
108	#define CSR_SELECT 0x11
109	#define CSR_SEL_XFER_DONE 0x16
110	#define CSR_XFER_DONE 0x18
111
112	/* paused or aborted interrupts */
113	#define CSR_MSGIN 0x20
114	#define CSR_SDP 0x21
115	#define CSR_SEL_ABORT 0x22
116	#define CSR_RESEL_ABORT 0x25
117	#define CSR_RESEL_ABORT_AM 0x27
118	#define CSR_ABORT 0x28
119
120	/* terminated interrupts */
121	#define CSR_INVALID 0x40
122	#define CSR_UNEXP_DISC 0x41
123	#define CSR_TIMEOUT 0x42
124	#define CSR_PARITY 0x43
125	#define CSR_PARITY_ATN 0x44
126	#define CSR_BAD_STATUS 0x45
127	#define CSR_UNEXP 0x48
128
129	/* service required interrupts */
130	#define CSR_RESEL 0x80
131	#define CSR_RESEL_AM 0x81
132	#define CSR_DISC 0x85
133	#define CSR_SRV_REQ 0x88
134
135	/* Own ID/CDB Size register */
136	#define OWNID_EAF 0x08
137	#define OWNID_EHP 0x10
138	#define OWNID_RAF 0x20
139	#define OWNID_FS_8 0x00
140	#define OWNID_FS_12 0x40
141	#define OWNID_FS_16 0x80
142
143	/* define these so we don't have to change a2091.c, etc. */
144	#define WD33C93_FS_8_10 OWNID_FS_8
145	#define WD33C93_FS_12_15 OWNID_FS_12
146	#define WD33C93_FS_16_20 OWNID_FS_16
147
c03983ac	148	/* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
a5d8421b	149	#define WD33C93_FS_MHZ(mhz) (mhz)
a5d8421b	150
1da177e4 LT	151	/* Control register */
	152	#define CTRL_HSP 0x01
	153	#define CTRL_HA 0x02
	154	#define CTRL_IDI 0x04
	155	#define CTRL_EDI 0x08
	156	#define CTRL_HHP 0x10
	157	#define CTRL_POLLED 0x00
	158	#define CTRL_BURST 0x20
	159	#define CTRL_BUS 0x40
	160	#define CTRL_DMA 0x80
	161
	162	/* Timeout Period register */
	163	#define TIMEOUT_PERIOD_VALUE 20 /* 20 = 200 ms */
	164
	165	/* Synchronous Transfer Register */
	166	#define STR_FSS 0x80
	167
	168	/* Destination ID register */
	169	#define DSTID_DPD 0x40
	170	#define DATA_OUT_DIR 0
	171	#define DATA_IN_DIR 1
	172	#define DSTID_SCC 0x80
	173
	174	/* Source ID register */
	175	#define SRCID_MASK 0x07
	176	#define SRCID_SIV 0x08
	177	#define SRCID_DSP 0x20
	178	#define SRCID_ES 0x40
	179	#define SRCID_ER 0x80
	180
	181	/* This is what the 3393 chip looks like to us */
	182	typedef struct {
	183	#ifdef CONFIG_WD33C93_PIO
	184	unsigned int SASR;
	185	unsigned int SCMD;
	186	#else
	187	volatile unsigned char *SASR;
	188	volatile unsigned char *SCMD;
	189	#endif
	190	} wd33c93_regs;
	191
	192
	193	typedef int (dma_setup_t) (struct scsi_cmnd SCpnt, int dir_in);
	194	typedef void (dma_stop_t) (struct Scsi_Host instance,
	195	struct scsi_cmnd *SCpnt, int status);
	196
	197
	198	#define ILLEGAL_STATUS_BYTE 0xff
	199
	200	#define DEFAULT_SX_PER 376 /* (ns) fairly safe */
	201	#define DEFAULT_SX_OFF 0 /* aka async */
	202
	203	#define OPTIMUM_SX_PER 252 /* (ns) best we can do (mult-of-4) */
	204	#define OPTIMUM_SX_OFF 12 /* size of wd3393 fifo */
	205
	206	struct sx_period {
	207	unsigned int period_ns;
	208	uchar reg_value;
	209	};
	210
	211	/* FEF: defines for hostdata->dma_buffer_pool */
	212
	213	#define BUF_CHIP_ALLOCED 0
	214	#define BUF_SCSI_ALLOCED 1
215
216	struct WD33C93_hostdata {
217	struct Scsi_Host *next;
218	wd33c93_regs regs;
219	spinlock_t lock;
220	uchar clock_freq;
221	uchar chip; /* what kind of wd33c93? */
222	uchar microcode; /* microcode rev */
223	uchar dma_buffer_pool; /* FEF: buffer from chip_ram? */
224	int dma_dir; /* data transfer dir. */
225	dma_setup_t dma_setup;
226	dma_stop_t dma_stop;
227	unsigned int dma_xfer_mask;
228	uchar *dma_bounce_buffer;
229	unsigned int dma_bounce_len;
230	volatile uchar busy[8]; /* index = target, bit = lun */
231	volatile struct scsi_cmnd input_Q; / commands waiting to be started */
232	volatile struct scsi_cmnd selecting; / trying to select this command */
233	volatile struct scsi_cmnd connected; / currently connected command */
234	volatile struct scsi_cmnd disconnected_Q;/ commands waiting for reconnect */
235	uchar state; /* what we are currently doing */
236	uchar dma; /* current state of DMA (on/off) */
237	uchar level2; /* extent to which Level-2 commands are used */
238	uchar disconnect; /* disconnect/reselect policy */
239	unsigned int args; /* set from command-line argument */
240	uchar incoming_msg[8]; /* filled during message_in phase */
241	int incoming_ptr; /* mainly used with EXTENDED messages */
242	uchar outgoing_msg[8]; /* send this during next message_out */
243	int outgoing_len; /* length of outgoing message */
244	unsigned int default_sx_per; /* default transfer period for SCSI bus */
245	uchar sync_xfer[8]; /* sync_xfer reg settings per target */
246	uchar sync_stat[8]; /* status of sync negotiation per target */
247	uchar no_sync; /* bitmask: don't do sync on these targets */
248	uchar no_dma; /* set this flag to disable DMA */
a5d8421b	249	uchar dma_mode; /* DMA Burst Mode or Single Byte DMA */
	250	uchar fast; /* set this flag to enable Fast SCSI */
	251	struct sx_period sx_table[9]; /* transfer periods for actual DTC-setting */
1da177e4 LT	252	#ifdef PROC_INTERFACE
	253	uchar proc; /* bitmask: what's in proc output */
	254	#ifdef PROC_STATISTICS
	255	unsigned long cmd_cnt[8]; /* # of commands issued per target */
	256	unsigned long int_cnt; /* # of interrupts serviced */
	257	unsigned long pio_cnt; /* # of pio data transfers */
	258	unsigned long dma_cnt; /* # of DMA data transfers */
	259	unsigned long disc_allowed_cnt[8]; /* # of disconnects allowed per target */
	260	unsigned long disc_done_cnt[8]; /* # of disconnects done per target*/
	261	#endif
	262	#endif
	263	};
	264
	265
	266	/* defines for hostdata->chip */
	267
	268	#define C_WD33C93 0
	269	#define C_WD33C93A 1
	270	#define C_WD33C93B 2
	271	#define C_UNKNOWN_CHIP 100
	272
	273	/* defines for hostdata->state */
	274
	275	#define S_UNCONNECTED 0
	276	#define S_SELECTING 1
	277	#define S_RUNNING_LEVEL2 2
	278	#define S_CONNECTED 3
	279	#define S_PRE_TMP_DISC 4
	280	#define S_PRE_CMP_DISC 5
	281
	282	/* defines for hostdata->dma */
	283
	284	#define D_DMA_OFF 0
	285	#define D_DMA_RUNNING 1
	286
	287	/* defines for hostdata->level2 */
	288	/* NOTE: only the first 3 are implemented so far */
	289
	290	#define L2_NONE 1 /* no combination commands - we get lots of ints */
	291	#define L2_SELECT 2 /* start with SEL_ATN_XFER, but never resume it */
	292	#define L2_BASIC 3 /* resume after STATUS ints & RDP messages */
	293	#define L2_DATA 4 /* resume after DATA_IN/OUT ints */
	294	#define L2_MOST 5 /* resume after anything except a RESELECT int */
	295	#define L2_RESELECT 6 /* resume after everything, including RESELECT ints */
	296	#define L2_ALL 7 /* always resume */
	297
	298	/* defines for hostdata->disconnect */
	299
	300	#define DIS_NEVER 0
	301	#define DIS_ADAPTIVE 1
	302	#define DIS_ALWAYS 2
	303
	304	/* defines for hostdata->args */
	305
	306	#define DB_TEST1 1<<0
	307	#define DB_TEST2 1<<1
	308	#define DB_QUEUE_COMMAND 1<<2
	309	#define DB_EXECUTE 1<<3
	310	#define DB_INTR 1<<4
	311	#define DB_TRANSFER 1<<5
	312	#define DB_MASK 0x3f
	313
	314	/* defines for hostdata->sync_stat[] */
	315
316	#define SS_UNSET 0
317	#define SS_FIRST 1
318	#define SS_WAITING 2
319	#define SS_SET 3
320
321	/* defines for hostdata->proc */
322
323	#define PR_VERSION 1<<0
324	#define PR_INFO 1<<1
325	#define PR_STATISTICS 1<<2
326	#define PR_CONNECTED 1<<3
327	#define PR_INPUTQ 1<<4
328	#define PR_DISCQ 1<<5
329	#define PR_TEST 1<<6
330	#define PR_STOP 1<<7
331
332
333	void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
334	dma_setup_t setup, dma_stop_t stop, int clock_freq);
335	int wd33c93_abort (struct scsi_cmnd *cmd);
f281233d	336	int wd33c93_queuecommand (struct Scsi_Host h, struct scsi_cmnd cmd);
1da177e4	337	void wd33c93_intr (struct Scsi_Host *instance);
408bb25b AV	338	int wd33c93_show_info(struct seq_file , struct Scsi_Host );
408bb25b AV	339	int wd33c93_write_info(struct Scsi_Host , char , int);
1da177e4	340	int wd33c93_host_reset (struct scsi_cmnd *);
1da177e4 LT	341
1da177e4 LT	342	#endif /* WD33C93_H */