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e0eca63e VH |
1 | /* |
2 | * Universal Flash Storage Host controller driver | |
3 | * | |
4 | * This code is based on drivers/scsi/ufs/ufshcd.h | |
5 | * Copyright (C) 2011-2013 Samsung India Software Operations | |
dc3c8d3a | 6 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
e0eca63e VH |
7 | * |
8 | * Authors: | |
9 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
10 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version 2 | |
15 | * of the License, or (at your option) any later version. | |
16 | * See the COPYING file in the top-level directory or visit | |
17 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * This program is provided "AS IS" and "WITH ALL FAULTS" and | |
25 | * without warranty of any kind. You are solely responsible for | |
26 | * determining the appropriateness of using and distributing | |
27 | * the program and assume all risks associated with your exercise | |
28 | * of rights with respect to the program, including but not limited | |
29 | * to infringement of third party rights, the risks and costs of | |
30 | * program errors, damage to or loss of data, programs or equipment, | |
31 | * and unavailability or interruption of operations. Under no | |
32 | * circumstances will the contributor of this Program be liable for | |
33 | * any damages of any kind arising from your use or distribution of | |
34 | * this program. | |
35 | */ | |
36 | ||
37 | #ifndef _UFSHCD_H | |
38 | #define _UFSHCD_H | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/io.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/slab.h> | |
47 | #include <linux/spinlock.h> | |
48 | #include <linux/workqueue.h> | |
49 | #include <linux/errno.h> | |
50 | #include <linux/types.h> | |
51 | #include <linux/wait.h> | |
52 | #include <linux/bitops.h> | |
53 | #include <linux/pm_runtime.h> | |
54 | #include <linux/clk.h> | |
6ccf44fe | 55 | #include <linux/completion.h> |
aa497613 | 56 | #include <linux/regulator/consumer.h> |
f37aabcf | 57 | #include "unipro.h" |
e0eca63e VH |
58 | |
59 | #include <asm/irq.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <scsi/scsi.h> | |
62 | #include <scsi/scsi_cmnd.h> | |
63 | #include <scsi/scsi_host.h> | |
64 | #include <scsi/scsi_tcq.h> | |
65 | #include <scsi/scsi_dbg.h> | |
66 | #include <scsi/scsi_eh.h> | |
67 | ||
68 | #include "ufs.h" | |
69 | #include "ufshci.h" | |
70 | ||
71 | #define UFSHCD "ufshcd" | |
72 | #define UFSHCD_DRIVER_VERSION "0.2" | |
73 | ||
5c0c28a8 SRT |
74 | struct ufs_hba; |
75 | ||
5a0b0cb9 SRT |
76 | enum dev_cmd_type { |
77 | DEV_CMD_TYPE_NOP = 0x0, | |
68078d5c | 78 | DEV_CMD_TYPE_QUERY = 0x1, |
5a0b0cb9 SRT |
79 | }; |
80 | ||
e0eca63e VH |
81 | /** |
82 | * struct uic_command - UIC command structure | |
83 | * @command: UIC command | |
84 | * @argument1: UIC command argument 1 | |
85 | * @argument2: UIC command argument 2 | |
86 | * @argument3: UIC command argument 3 | |
87 | * @cmd_active: Indicate if UIC command is outstanding | |
88 | * @result: UIC command result | |
6ccf44fe | 89 | * @done: UIC command completion |
e0eca63e VH |
90 | */ |
91 | struct uic_command { | |
92 | u32 command; | |
93 | u32 argument1; | |
94 | u32 argument2; | |
95 | u32 argument3; | |
96 | int cmd_active; | |
97 | int result; | |
6ccf44fe | 98 | struct completion done; |
e0eca63e VH |
99 | }; |
100 | ||
57d104c1 SJ |
101 | /* Used to differentiate the power management options */ |
102 | enum ufs_pm_op { | |
103 | UFS_RUNTIME_PM, | |
104 | UFS_SYSTEM_PM, | |
105 | UFS_SHUTDOWN_PM, | |
106 | }; | |
107 | ||
108 | #define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM) | |
109 | #define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM) | |
110 | #define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM) | |
111 | ||
112 | /* Host <-> Device UniPro Link state */ | |
113 | enum uic_link_state { | |
114 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ | |
115 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ | |
116 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ | |
117 | }; | |
118 | ||
119 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) | |
120 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ | |
121 | UIC_LINK_ACTIVE_STATE) | |
122 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ | |
123 | UIC_LINK_HIBERN8_STATE) | |
124 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) | |
125 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ | |
126 | UIC_LINK_ACTIVE_STATE) | |
127 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ | |
128 | UIC_LINK_HIBERN8_STATE) | |
129 | ||
130 | /* | |
131 | * UFS Power management levels. | |
132 | * Each level is in increasing order of power savings. | |
133 | */ | |
134 | enum ufs_pm_level { | |
135 | UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
136 | UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
137 | UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
138 | UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
139 | UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
140 | UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */ | |
141 | UFS_PM_LVL_MAX | |
142 | }; | |
143 | ||
144 | struct ufs_pm_lvl_states { | |
145 | enum ufs_dev_pwr_mode dev_state; | |
146 | enum uic_link_state link_state; | |
147 | }; | |
148 | ||
e0eca63e VH |
149 | /** |
150 | * struct ufshcd_lrb - local reference block | |
151 | * @utr_descriptor_ptr: UTRD address of the command | |
5a0b0cb9 | 152 | * @ucd_req_ptr: UCD address of the command |
e0eca63e VH |
153 | * @ucd_rsp_ptr: Response UPIU address for this command |
154 | * @ucd_prdt_ptr: PRDT address of the command | |
155 | * @cmd: pointer to SCSI command | |
156 | * @sense_buffer: pointer to sense buffer address of the SCSI command | |
157 | * @sense_bufflen: Length of the sense buffer | |
158 | * @scsi_status: SCSI status of the command | |
159 | * @command_type: SCSI, UFS, Query. | |
160 | * @task_tag: Task tag of the command | |
161 | * @lun: LUN of the command | |
5a0b0cb9 | 162 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
e0eca63e VH |
163 | */ |
164 | struct ufshcd_lrb { | |
165 | struct utp_transfer_req_desc *utr_descriptor_ptr; | |
5a0b0cb9 | 166 | struct utp_upiu_req *ucd_req_ptr; |
e0eca63e VH |
167 | struct utp_upiu_rsp *ucd_rsp_ptr; |
168 | struct ufshcd_sg_entry *ucd_prdt_ptr; | |
169 | ||
170 | struct scsi_cmnd *cmd; | |
171 | u8 *sense_buffer; | |
172 | unsigned int sense_bufflen; | |
173 | int scsi_status; | |
174 | ||
175 | int command_type; | |
176 | int task_tag; | |
0ce147d4 | 177 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
5a0b0cb9 | 178 | bool intr_cmd; |
e0eca63e VH |
179 | }; |
180 | ||
68078d5c | 181 | /** |
a230c2f6 | 182 | * struct ufs_query - holds relevant data structures for query request |
68078d5c DR |
183 | * @request: request upiu and function |
184 | * @descriptor: buffer for sending/receiving descriptor | |
185 | * @response: response upiu and response | |
186 | */ | |
187 | struct ufs_query { | |
188 | struct ufs_query_req request; | |
189 | u8 *descriptor; | |
190 | struct ufs_query_res response; | |
191 | }; | |
192 | ||
5a0b0cb9 SRT |
193 | /** |
194 | * struct ufs_dev_cmd - all assosiated fields with device management commands | |
195 | * @type: device management command type - Query, NOP OUT | |
196 | * @lock: lock to allow one command at a time | |
197 | * @complete: internal commands completion | |
198 | * @tag_wq: wait queue until free command slot is available | |
199 | */ | |
200 | struct ufs_dev_cmd { | |
201 | enum dev_cmd_type type; | |
202 | struct mutex lock; | |
203 | struct completion *complete; | |
204 | wait_queue_head_t tag_wq; | |
68078d5c | 205 | struct ufs_query query; |
5a0b0cb9 | 206 | }; |
e0eca63e | 207 | |
c6e79dac SRT |
208 | /** |
209 | * struct ufs_clk_info - UFS clock related info | |
210 | * @list: list headed by hba->clk_list_head | |
211 | * @clk: clock node | |
212 | * @name: clock name | |
213 | * @max_freq: maximum frequency supported by the clock | |
4cff6d99 | 214 | * @min_freq: min frequency that can be used for clock scaling |
856b3483 | 215 | * @curr_freq: indicates the current frequency that it is set to |
c6e79dac SRT |
216 | * @enabled: variable to check against multiple enable/disable |
217 | */ | |
218 | struct ufs_clk_info { | |
219 | struct list_head list; | |
220 | struct clk *clk; | |
221 | const char *name; | |
222 | u32 max_freq; | |
4cff6d99 | 223 | u32 min_freq; |
856b3483 | 224 | u32 curr_freq; |
c6e79dac SRT |
225 | bool enabled; |
226 | }; | |
227 | ||
f06fcc71 YG |
228 | enum ufs_notify_change_status { |
229 | PRE_CHANGE, | |
230 | POST_CHANGE, | |
231 | }; | |
7eb584db DR |
232 | |
233 | struct ufs_pa_layer_attr { | |
234 | u32 gear_rx; | |
235 | u32 gear_tx; | |
236 | u32 lane_rx; | |
237 | u32 lane_tx; | |
238 | u32 pwr_rx; | |
239 | u32 pwr_tx; | |
240 | u32 hs_rate; | |
241 | }; | |
242 | ||
243 | struct ufs_pwr_mode_info { | |
244 | bool is_valid; | |
245 | struct ufs_pa_layer_attr info; | |
246 | }; | |
247 | ||
5c0c28a8 SRT |
248 | /** |
249 | * struct ufs_hba_variant_ops - variant specific callbacks | |
250 | * @name: variant name | |
251 | * @init: called when the driver is initialized | |
252 | * @exit: called to cleanup everything done in init | |
9949e702 | 253 | * @get_ufs_hci_version: called to get UFS HCI version |
856b3483 | 254 | * @clk_scale_notify: notifies that clks are scaled up/down |
5c0c28a8 SRT |
255 | * @setup_clocks: called before touching any of the controller registers |
256 | * @setup_regulators: called before accessing the host controller | |
257 | * @hce_enable_notify: called before and after HCE enable bit is set to allow | |
258 | * variant specific Uni-Pro initialization. | |
259 | * @link_startup_notify: called before and after Link startup is carried out | |
260 | * to allow variant specific Uni-Pro initialization. | |
7eb584db DR |
261 | * @pwr_change_notify: called before and after a power mode change |
262 | * is carried out to allow vendor spesific capabilities | |
263 | * to be set. | |
0e675efa KK |
264 | * @setup_xfer_req: called before any transfer request is issued |
265 | * to set some things | |
d2877be4 KK |
266 | * @setup_task_mgmt: called before any task management request is issued |
267 | * to set some things | |
ee32c909 KK |
268 | * @hibern8_notify: called around hibern8 enter/exit |
269 | * to configure some things | |
57d104c1 SJ |
270 | * @suspend: called during host controller PM callback |
271 | * @resume: called during host controller PM callback | |
6e3fd44d | 272 | * @dbg_register_dump: used to dump controller debug information |
4b9ffb5a | 273 | * @phy_initialization: used to initialize phys |
5c0c28a8 SRT |
274 | */ |
275 | struct ufs_hba_variant_ops { | |
276 | const char *name; | |
277 | int (*init)(struct ufs_hba *); | |
278 | void (*exit)(struct ufs_hba *); | |
9949e702 | 279 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
f06fcc71 YG |
280 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
281 | enum ufs_notify_change_status); | |
1e879e8f SJ |
282 | int (*setup_clocks)(struct ufs_hba *, bool, |
283 | enum ufs_notify_change_status); | |
5c0c28a8 | 284 | int (*setup_regulators)(struct ufs_hba *, bool); |
f06fcc71 YG |
285 | int (*hce_enable_notify)(struct ufs_hba *, |
286 | enum ufs_notify_change_status); | |
287 | int (*link_startup_notify)(struct ufs_hba *, | |
288 | enum ufs_notify_change_status); | |
7eb584db | 289 | int (*pwr_change_notify)(struct ufs_hba *, |
f06fcc71 YG |
290 | enum ufs_notify_change_status status, |
291 | struct ufs_pa_layer_attr *, | |
7eb584db | 292 | struct ufs_pa_layer_attr *); |
0e675efa | 293 | void (*setup_xfer_req)(struct ufs_hba *, int, bool); |
d2877be4 | 294 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
ee32c909 KK |
295 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
296 | enum ufs_notify_change_status); | |
57d104c1 SJ |
297 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op); |
298 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); | |
6e3fd44d | 299 | void (*dbg_register_dump)(struct ufs_hba *hba); |
4b9ffb5a | 300 | int (*phy_initialization)(struct ufs_hba *); |
5c0c28a8 SRT |
301 | }; |
302 | ||
1ab27c9c ST |
303 | /* clock gating state */ |
304 | enum clk_gating_state { | |
305 | CLKS_OFF, | |
306 | CLKS_ON, | |
307 | REQ_CLKS_OFF, | |
308 | REQ_CLKS_ON, | |
309 | }; | |
310 | ||
311 | /** | |
312 | * struct ufs_clk_gating - UFS clock gating related info | |
313 | * @gate_work: worker to turn off clocks after some delay as specified in | |
314 | * delay_ms | |
315 | * @ungate_work: worker to turn on clocks that will be used in case of | |
316 | * interrupt context | |
317 | * @state: the current clocks state | |
318 | * @delay_ms: gating delay in ms | |
319 | * @is_suspended: clk gating is suspended when set to 1 which can be used | |
320 | * during suspend/resume | |
321 | * @delay_attr: sysfs attribute to control delay_attr | |
322 | * @active_reqs: number of requests that are pending and should be waited for | |
323 | * completion before gating clocks. | |
324 | */ | |
325 | struct ufs_clk_gating { | |
326 | struct delayed_work gate_work; | |
327 | struct work_struct ungate_work; | |
328 | enum clk_gating_state state; | |
329 | unsigned long delay_ms; | |
330 | bool is_suspended; | |
331 | struct device_attribute delay_attr; | |
332 | int active_reqs; | |
333 | }; | |
334 | ||
856b3483 ST |
335 | struct ufs_clk_scaling { |
336 | ktime_t busy_start_t; | |
337 | bool is_busy_started; | |
338 | unsigned long tot_busy_t; | |
339 | unsigned long window_start_t; | |
340 | }; | |
341 | ||
3a4bf06d YG |
342 | /** |
343 | * struct ufs_init_prefetch - contains data that is pre-fetched once during | |
344 | * initialization | |
345 | * @icc_level: icc level which was read during initialization | |
346 | */ | |
347 | struct ufs_init_prefetch { | |
348 | u32 icc_level; | |
349 | }; | |
350 | ||
e0eca63e VH |
351 | /** |
352 | * struct ufs_hba - per adapter private structure | |
353 | * @mmio_base: UFSHCI base register address | |
354 | * @ucdl_base_addr: UFS Command Descriptor base address | |
355 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address | |
356 | * @utmrdl_base_addr: UTP Task Management Descriptor base address | |
357 | * @ucdl_dma_addr: UFS Command Descriptor DMA address | |
358 | * @utrdl_dma_addr: UTRDL DMA address | |
359 | * @utmrdl_dma_addr: UTMRDL DMA address | |
360 | * @host: Scsi_Host instance of the driver | |
361 | * @dev: device handle | |
362 | * @lrb: local reference block | |
5a0b0cb9 | 363 | * @lrb_in_use: lrb in use |
e0eca63e VH |
364 | * @outstanding_tasks: Bits representing outstanding task requests |
365 | * @outstanding_reqs: Bits representing outstanding transfer requests | |
366 | * @capabilities: UFS Controller Capabilities | |
367 | * @nutrs: Transfer Request Queue depth supported by controller | |
368 | * @nutmrs: Task Management Queue depth supported by controller | |
369 | * @ufs_version: UFS Version to which controller complies | |
5c0c28a8 SRT |
370 | * @vops: pointer to variant specific operations |
371 | * @priv: pointer to variant specific private data | |
e0eca63e VH |
372 | * @irq: Irq number of the controller |
373 | * @active_uic_cmd: handle of active UIC command | |
6ccf44fe | 374 | * @uic_cmd_mutex: mutex for uic command |
e2933132 SRT |
375 | * @tm_wq: wait queue for task management |
376 | * @tm_tag_wq: wait queue for free task management slots | |
377 | * @tm_slots_in_use: bit map of task management request slots in use | |
53b3d9c3 | 378 | * @pwr_done: completion for power mode change |
e0eca63e VH |
379 | * @tm_condition: condition variable for task management |
380 | * @ufshcd_state: UFSHCD states | |
3441da7d | 381 | * @eh_flags: Error handling flags |
2fbd009b | 382 | * @intr_mask: Interrupt Mask Bits |
66ec6d59 | 383 | * @ee_ctrl_mask: Exception event control mask |
1d337ec2 | 384 | * @is_powered: flag to check if HBA is powered |
3a4bf06d YG |
385 | * @is_init_prefetch: flag to check if data was pre-fetched in initialization |
386 | * @init_prefetch_data: data pre-fetched during initialization | |
e8e7f271 | 387 | * @eh_work: Worker to handle UFS errors that require s/w attention |
66ec6d59 | 388 | * @eeh_work: Worker to handle exception events |
e0eca63e | 389 | * @errors: HBA errors |
e8e7f271 SRT |
390 | * @uic_error: UFS interconnect layer error status |
391 | * @saved_err: sticky error mask | |
392 | * @saved_uic_err: sticky UIC error mask | |
5a0b0cb9 | 393 | * @dev_cmd: ufs device management command information |
cad2e03d | 394 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
66ec6d59 | 395 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
aa497613 | 396 | * @vreg_info: UFS device voltage regulator information |
c6e79dac | 397 | * @clk_list_head: UFS host controller clocks list node head |
7eb584db DR |
398 | * @pwr_info: holds current power mode |
399 | * @max_pwr_info: keeps the device max valid pwm | |
afdfff59 YG |
400 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
401 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for | |
402 | * device is known or not. | |
e0eca63e VH |
403 | */ |
404 | struct ufs_hba { | |
405 | void __iomem *mmio_base; | |
406 | ||
407 | /* Virtual memory reference */ | |
408 | struct utp_transfer_cmd_desc *ucdl_base_addr; | |
409 | struct utp_transfer_req_desc *utrdl_base_addr; | |
410 | struct utp_task_req_desc *utmrdl_base_addr; | |
411 | ||
412 | /* DMA memory reference */ | |
413 | dma_addr_t ucdl_dma_addr; | |
414 | dma_addr_t utrdl_dma_addr; | |
415 | dma_addr_t utmrdl_dma_addr; | |
416 | ||
417 | struct Scsi_Host *host; | |
418 | struct device *dev; | |
2a8fa600 SJ |
419 | /* |
420 | * This field is to keep a reference to "scsi_device" corresponding to | |
421 | * "UFS device" W-LU. | |
422 | */ | |
423 | struct scsi_device *sdev_ufs_device; | |
e0eca63e | 424 | |
57d104c1 SJ |
425 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
426 | enum uic_link_state uic_link_state; | |
427 | /* Desired UFS power management level during runtime PM */ | |
428 | enum ufs_pm_level rpm_lvl; | |
429 | /* Desired UFS power management level during system PM */ | |
430 | enum ufs_pm_level spm_lvl; | |
431 | int pm_op_in_progress; | |
432 | ||
e0eca63e | 433 | struct ufshcd_lrb *lrb; |
5a0b0cb9 | 434 | unsigned long lrb_in_use; |
e0eca63e VH |
435 | |
436 | unsigned long outstanding_tasks; | |
437 | unsigned long outstanding_reqs; | |
438 | ||
439 | u32 capabilities; | |
440 | int nutrs; | |
441 | int nutmrs; | |
442 | u32 ufs_version; | |
5c0c28a8 SRT |
443 | struct ufs_hba_variant_ops *vops; |
444 | void *priv; | |
e0eca63e | 445 | unsigned int irq; |
57d104c1 | 446 | bool is_irq_enabled; |
e0eca63e | 447 | |
b852190e YG |
448 | /* Interrupt aggregation support is broken */ |
449 | #define UFSHCD_QUIRK_BROKEN_INTR_AGGR UFS_BIT(0) | |
450 | ||
cad2e03d YG |
451 | /* |
452 | * delay before each dme command is required as the unipro | |
453 | * layer has shown instabilities | |
454 | */ | |
b852190e YG |
455 | #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS UFS_BIT(1) |
456 | ||
7ca38cf3 YG |
457 | /* |
458 | * If UFS host controller is having issue in processing LCC (Line | |
459 | * Control Command) coming from device then enable this quirk. | |
460 | * When this quirk is enabled, host controller driver should disable | |
461 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE | |
462 | * attribute of device to 0). | |
463 | */ | |
464 | #define UFSHCD_QUIRK_BROKEN_LCC UFS_BIT(2) | |
cad2e03d | 465 | |
c3a2f9ee YG |
466 | /* |
467 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the | |
468 | * inbound Link supports unterminated line in HS mode. Setting this | |
469 | * attribute to 1 fixes moving to HS gear. | |
470 | */ | |
471 | #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP UFS_BIT(3) | |
472 | ||
874237f7 YG |
473 | /* |
474 | * This quirk needs to be enabled if the host contoller only allows | |
475 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or | |
476 | * SLOW AUTO). | |
477 | */ | |
478 | #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE UFS_BIT(4) | |
479 | ||
9949e702 YG |
480 | /* |
481 | * This quirk needs to be enabled if the host contoller doesn't | |
482 | * advertise the correct version in UFS_VER register. If this quirk | |
483 | * is enabled, standard UFS host driver will call the vendor specific | |
484 | * ops (get_ufs_hci_version) to get the correct version. | |
485 | */ | |
486 | #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5) | |
487 | ||
cad2e03d | 488 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
6ccf44fe | 489 | |
c58ab7aa YG |
490 | /* Device deviations from standard UFS device spec. */ |
491 | unsigned int dev_quirks; | |
492 | ||
e2933132 SRT |
493 | wait_queue_head_t tm_wq; |
494 | wait_queue_head_t tm_tag_wq; | |
e0eca63e | 495 | unsigned long tm_condition; |
e2933132 | 496 | unsigned long tm_slots_in_use; |
e0eca63e | 497 | |
57d104c1 SJ |
498 | struct uic_command *active_uic_cmd; |
499 | struct mutex uic_cmd_mutex; | |
500 | struct completion *uic_async_done; | |
53b3d9c3 | 501 | |
e0eca63e | 502 | u32 ufshcd_state; |
3441da7d | 503 | u32 eh_flags; |
2fbd009b | 504 | u32 intr_mask; |
66ec6d59 | 505 | u16 ee_ctrl_mask; |
1d337ec2 | 506 | bool is_powered; |
3a4bf06d YG |
507 | bool is_init_prefetch; |
508 | struct ufs_init_prefetch init_prefetch_data; | |
e0eca63e VH |
509 | |
510 | /* Work Queues */ | |
e8e7f271 | 511 | struct work_struct eh_work; |
66ec6d59 | 512 | struct work_struct eeh_work; |
e0eca63e VH |
513 | |
514 | /* HBA Errors */ | |
515 | u32 errors; | |
e8e7f271 SRT |
516 | u32 uic_error; |
517 | u32 saved_err; | |
518 | u32 saved_uic_err; | |
5a0b0cb9 SRT |
519 | |
520 | /* Device management request data */ | |
521 | struct ufs_dev_cmd dev_cmd; | |
cad2e03d | 522 | ktime_t last_dme_cmd_tstamp; |
66ec6d59 | 523 | |
57d104c1 SJ |
524 | /* Keeps information of the UFS device connected to this host */ |
525 | struct ufs_dev_info dev_info; | |
66ec6d59 | 526 | bool auto_bkops_enabled; |
aa497613 | 527 | struct ufs_vreg_info vreg_info; |
c6e79dac | 528 | struct list_head clk_list_head; |
57d104c1 SJ |
529 | |
530 | bool wlun_dev_clr_ua; | |
7eb584db | 531 | |
54b879b7 YG |
532 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
533 | u32 lanes_per_direction; | |
7eb584db DR |
534 | struct ufs_pa_layer_attr pwr_info; |
535 | struct ufs_pwr_mode_info max_pwr_info; | |
1ab27c9c ST |
536 | |
537 | struct ufs_clk_gating clk_gating; | |
538 | /* Control to enable/disable host capabilities */ | |
539 | u32 caps; | |
540 | /* Allow dynamic clk gating */ | |
541 | #define UFSHCD_CAP_CLK_GATING (1 << 0) | |
542 | /* Allow hiberb8 with clk gating */ | |
543 | #define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1) | |
856b3483 ST |
544 | /* Allow dynamic clk scaling */ |
545 | #define UFSHCD_CAP_CLK_SCALING (1 << 2) | |
374a246e SJ |
546 | /* Allow auto bkops to enabled during runtime suspend */ |
547 | #define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3) | |
b852190e YG |
548 | /* |
549 | * This capability allows host controller driver to use the UFS HCI's | |
550 | * interrupt aggregation capability. | |
551 | * CAUTION: Enabling this might reduce overall UFS throughput. | |
552 | */ | |
553 | #define UFSHCD_CAP_INTR_AGGR (1 << 4) | |
856b3483 ST |
554 | |
555 | struct devfreq *devfreq; | |
556 | struct ufs_clk_scaling clk_scaling; | |
e785060e | 557 | bool is_sys_suspended; |
afdfff59 YG |
558 | |
559 | enum bkops_status urgent_bkops_lvl; | |
560 | bool is_urgent_bkops_lvl_checked; | |
e0eca63e VH |
561 | }; |
562 | ||
1ab27c9c ST |
563 | /* Returns true if clocks can be gated. Otherwise false */ |
564 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) | |
565 | { | |
566 | return hba->caps & UFSHCD_CAP_CLK_GATING; | |
567 | } | |
568 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) | |
569 | { | |
570 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; | |
571 | } | |
856b3483 ST |
572 | static inline int ufshcd_is_clkscaling_enabled(struct ufs_hba *hba) |
573 | { | |
574 | return hba->caps & UFSHCD_CAP_CLK_SCALING; | |
575 | } | |
374a246e SJ |
576 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
577 | { | |
578 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
579 | } | |
580 | ||
b852190e YG |
581 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
582 | { | |
4b9ffb5a JP |
583 | /* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/ |
584 | #ifndef CONFIG_SCSI_UFS_DWC | |
b852190e YG |
585 | if ((hba->caps & UFSHCD_CAP_INTR_AGGR) && |
586 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR)) | |
587 | return true; | |
588 | else | |
589 | return false; | |
4b9ffb5a JP |
590 | #else |
591 | return true; | |
592 | #endif | |
b852190e YG |
593 | } |
594 | ||
b873a275 SJ |
595 | #define ufshcd_writel(hba, val, reg) \ |
596 | writel((val), (hba)->mmio_base + (reg)) | |
597 | #define ufshcd_readl(hba, reg) \ | |
598 | readl((hba)->mmio_base + (reg)) | |
599 | ||
e785060e DR |
600 | /** |
601 | * ufshcd_rmwl - read modify write into a register | |
602 | * @hba - per adapter instance | |
603 | * @mask - mask to apply on read value | |
604 | * @val - actual value to write | |
605 | * @reg - register address | |
606 | */ | |
607 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) | |
608 | { | |
609 | u32 tmp; | |
610 | ||
611 | tmp = ufshcd_readl(hba, reg); | |
612 | tmp &= ~mask; | |
613 | tmp |= (val & mask); | |
614 | ufshcd_writel(hba, tmp, reg); | |
615 | } | |
616 | ||
5c0c28a8 | 617 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
47555a5c | 618 | void ufshcd_dealloc_host(struct ufs_hba *); |
5c0c28a8 | 619 | int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int); |
e0eca63e | 620 | void ufshcd_remove(struct ufs_hba *); |
596585a2 YG |
621 | int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, |
622 | u32 val, unsigned long interval_us, | |
623 | unsigned long timeout_ms, bool can_sleep); | |
e0eca63e | 624 | |
68078d5c DR |
625 | static inline void check_upiu_size(void) |
626 | { | |
627 | BUILD_BUG_ON(ALIGNED_UPIU_SIZE < | |
628 | GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); | |
629 | } | |
630 | ||
1ce5898a YG |
631 | /** |
632 | * ufshcd_set_variant - set variant specific data to the hba | |
633 | * @hba - per adapter instance | |
634 | * @variant - pointer to variant specific data | |
635 | */ | |
636 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) | |
637 | { | |
638 | BUG_ON(!hba); | |
639 | hba->priv = variant; | |
640 | } | |
641 | ||
642 | /** | |
643 | * ufshcd_get_variant - get variant specific data from the hba | |
644 | * @hba - per adapter instance | |
645 | */ | |
646 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) | |
647 | { | |
648 | BUG_ON(!hba); | |
649 | return hba->priv; | |
650 | } | |
651 | ||
66ec6d59 SRT |
652 | extern int ufshcd_runtime_suspend(struct ufs_hba *hba); |
653 | extern int ufshcd_runtime_resume(struct ufs_hba *hba); | |
654 | extern int ufshcd_runtime_idle(struct ufs_hba *hba); | |
57d104c1 SJ |
655 | extern int ufshcd_system_suspend(struct ufs_hba *hba); |
656 | extern int ufshcd_system_resume(struct ufs_hba *hba); | |
657 | extern int ufshcd_shutdown(struct ufs_hba *hba); | |
12b4fdb4 SJ |
658 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
659 | u8 attr_set, u32 mib_val, u8 peer); | |
660 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
661 | u32 *mib_val, u8 peer); | |
662 | ||
663 | /* UIC command interfaces for DME primitives */ | |
664 | #define DME_LOCAL 0 | |
665 | #define DME_PEER 1 | |
666 | #define ATTR_SET_NOR 0 /* NORMAL */ | |
667 | #define ATTR_SET_ST 1 /* STATIC */ | |
668 | ||
669 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, | |
670 | u32 mib_val) | |
671 | { | |
672 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
673 | mib_val, DME_LOCAL); | |
674 | } | |
675 | ||
676 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, | |
677 | u32 mib_val) | |
678 | { | |
679 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
680 | mib_val, DME_LOCAL); | |
681 | } | |
682 | ||
683 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, | |
684 | u32 mib_val) | |
685 | { | |
686 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
687 | mib_val, DME_PEER); | |
688 | } | |
689 | ||
690 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, | |
691 | u32 mib_val) | |
692 | { | |
693 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
694 | mib_val, DME_PEER); | |
695 | } | |
696 | ||
697 | static inline int ufshcd_dme_get(struct ufs_hba *hba, | |
698 | u32 attr_sel, u32 *mib_val) | |
699 | { | |
700 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); | |
701 | } | |
702 | ||
703 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, | |
704 | u32 attr_sel, u32 *mib_val) | |
705 | { | |
706 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); | |
707 | } | |
708 | ||
b573d484 YG |
709 | int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size); |
710 | ||
f37aabcf YG |
711 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
712 | { | |
713 | return (pwr_info->pwr_rx == FAST_MODE || | |
714 | pwr_info->pwr_rx == FASTAUTO_MODE) && | |
715 | (pwr_info->pwr_tx == FAST_MODE || | |
716 | pwr_info->pwr_tx == FASTAUTO_MODE); | |
717 | } | |
718 | ||
b573d484 YG |
719 | #define ASCII_STD true |
720 | ||
721 | int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf, | |
722 | u32 size, bool ascii); | |
723 | ||
dc3c8d3a YG |
724 | /* Expose Query-Request API */ |
725 | int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, | |
726 | enum flag_idn idn, bool *flag_res); | |
1ab27c9c ST |
727 | int ufshcd_hold(struct ufs_hba *hba, bool async); |
728 | void ufshcd_release(struct ufs_hba *hba); | |
37113106 | 729 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
0263bcd0 YG |
730 | |
731 | /* Wrapper functions for safely calling variant operations */ | |
732 | static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) | |
733 | { | |
734 | if (hba->vops) | |
735 | return hba->vops->name; | |
736 | return ""; | |
737 | } | |
738 | ||
739 | static inline int ufshcd_vops_init(struct ufs_hba *hba) | |
740 | { | |
741 | if (hba->vops && hba->vops->init) | |
742 | return hba->vops->init(hba); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static inline void ufshcd_vops_exit(struct ufs_hba *hba) | |
748 | { | |
749 | if (hba->vops && hba->vops->exit) | |
750 | return hba->vops->exit(hba); | |
751 | } | |
752 | ||
753 | static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) | |
754 | { | |
755 | if (hba->vops && hba->vops->get_ufs_hci_version) | |
756 | return hba->vops->get_ufs_hci_version(hba); | |
757 | ||
758 | return ufshcd_readl(hba, REG_UFS_VERSION); | |
759 | } | |
760 | ||
f06fcc71 YG |
761 | static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, |
762 | bool up, enum ufs_notify_change_status status) | |
0263bcd0 YG |
763 | { |
764 | if (hba->vops && hba->vops->clk_scale_notify) | |
f06fcc71 YG |
765 | return hba->vops->clk_scale_notify(hba, up, status); |
766 | return 0; | |
0263bcd0 YG |
767 | } |
768 | ||
1e879e8f SJ |
769 | static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on, |
770 | enum ufs_notify_change_status status) | |
0263bcd0 YG |
771 | { |
772 | if (hba->vops && hba->vops->setup_clocks) | |
1e879e8f | 773 | return hba->vops->setup_clocks(hba, on, status); |
0263bcd0 YG |
774 | return 0; |
775 | } | |
776 | ||
777 | static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status) | |
778 | { | |
779 | if (hba->vops && hba->vops->setup_regulators) | |
780 | return hba->vops->setup_regulators(hba, status); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba, | |
786 | bool status) | |
787 | { | |
788 | if (hba->vops && hba->vops->hce_enable_notify) | |
789 | return hba->vops->hce_enable_notify(hba, status); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, | |
794 | bool status) | |
795 | { | |
796 | if (hba->vops && hba->vops->link_startup_notify) | |
797 | return hba->vops->link_startup_notify(hba, status); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, | |
803 | bool status, | |
804 | struct ufs_pa_layer_attr *dev_max_params, | |
805 | struct ufs_pa_layer_attr *dev_req_params) | |
806 | { | |
807 | if (hba->vops && hba->vops->pwr_change_notify) | |
808 | return hba->vops->pwr_change_notify(hba, status, | |
809 | dev_max_params, dev_req_params); | |
810 | ||
811 | return -ENOTSUPP; | |
812 | } | |
813 | ||
0e675efa KK |
814 | static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag, |
815 | bool is_scsi_cmd) | |
816 | { | |
817 | if (hba->vops && hba->vops->setup_xfer_req) | |
818 | return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd); | |
819 | } | |
820 | ||
d2877be4 KK |
821 | static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba, |
822 | int tag, u8 tm_function) | |
823 | { | |
824 | if (hba->vops && hba->vops->setup_task_mgmt) | |
825 | return hba->vops->setup_task_mgmt(hba, tag, tm_function); | |
826 | } | |
827 | ||
ee32c909 KK |
828 | static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba, |
829 | enum uic_cmd_dme cmd, | |
830 | enum ufs_notify_change_status status) | |
831 | { | |
832 | if (hba->vops && hba->vops->hibern8_notify) | |
833 | return hba->vops->hibern8_notify(hba, cmd, status); | |
834 | } | |
835 | ||
0263bcd0 YG |
836 | static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) |
837 | { | |
838 | if (hba->vops && hba->vops->suspend) | |
839 | return hba->vops->suspend(hba, op); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op) | |
845 | { | |
846 | if (hba->vops && hba->vops->resume) | |
847 | return hba->vops->resume(hba, op); | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
6e3fd44d YG |
852 | static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba) |
853 | { | |
854 | if (hba->vops && hba->vops->dbg_register_dump) | |
855 | hba->vops->dbg_register_dump(hba); | |
856 | } | |
857 | ||
e0eca63e | 858 | #endif /* End of Header */ |