scsi: ufs: Fix potential NULL pointer access during memcpy
[linux-block.git] / drivers / scsi / ufs / ufshcd.h
CommitLineData
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1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
dc3c8d3a 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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7 *
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
35 */
36
37#ifndef _UFSHCD_H
38#define _UFSHCD_H
39
40#include <linux/module.h>
41#include <linux/kernel.h>
42#include <linux/init.h>
43#include <linux/interrupt.h>
44#include <linux/io.h>
45#include <linux/delay.h>
46#include <linux/slab.h>
47#include <linux/spinlock.h>
a3cd5ec5 48#include <linux/rwsem.h>
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49#include <linux/workqueue.h>
50#include <linux/errno.h>
51#include <linux/types.h>
52#include <linux/wait.h>
53#include <linux/bitops.h>
54#include <linux/pm_runtime.h>
55#include <linux/clk.h>
6ccf44fe 56#include <linux/completion.h>
aa497613 57#include <linux/regulator/consumer.h>
5a244e0e 58#include <linux/bitfield.h>
2c75f9a5 59#include <linux/devfreq.h>
f37aabcf 60#include "unipro.h"
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61
62#include <asm/irq.h>
63#include <asm/byteorder.h>
64#include <scsi/scsi.h>
65#include <scsi/scsi_cmnd.h>
66#include <scsi/scsi_host.h>
67#include <scsi/scsi_tcq.h>
68#include <scsi/scsi_dbg.h>
69#include <scsi/scsi_eh.h>
70
71#include "ufs.h"
c28c00ba 72#include "ufs_quirks.h"
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73#include "ufshci.h"
74
75#define UFSHCD "ufshcd"
76#define UFSHCD_DRIVER_VERSION "0.2"
77
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78struct ufs_hba;
79
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80enum dev_cmd_type {
81 DEV_CMD_TYPE_NOP = 0x0,
68078d5c 82 DEV_CMD_TYPE_QUERY = 0x1,
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83};
84
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85/**
86 * struct uic_command - UIC command structure
87 * @command: UIC command
88 * @argument1: UIC command argument 1
89 * @argument2: UIC command argument 2
90 * @argument3: UIC command argument 3
91 * @cmd_active: Indicate if UIC command is outstanding
92 * @result: UIC command result
6ccf44fe 93 * @done: UIC command completion
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94 */
95struct uic_command {
96 u32 command;
97 u32 argument1;
98 u32 argument2;
99 u32 argument3;
100 int cmd_active;
101 int result;
6ccf44fe 102 struct completion done;
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103};
104
57d104c1
SJ
105/* Used to differentiate the power management options */
106enum ufs_pm_op {
107 UFS_RUNTIME_PM,
108 UFS_SYSTEM_PM,
109 UFS_SHUTDOWN_PM,
110};
111
112#define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
113#define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
114#define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
115
116/* Host <-> Device UniPro Link state */
117enum uic_link_state {
118 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
119 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
120 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
121};
122
123#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
124#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
125 UIC_LINK_ACTIVE_STATE)
126#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
127 UIC_LINK_HIBERN8_STATE)
128#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
129#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
130 UIC_LINK_ACTIVE_STATE)
131#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
132 UIC_LINK_HIBERN8_STATE)
133
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134#define ufshcd_set_ufs_dev_active(h) \
135 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
136#define ufshcd_set_ufs_dev_sleep(h) \
137 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
138#define ufshcd_set_ufs_dev_poweroff(h) \
139 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
140#define ufshcd_is_ufs_dev_active(h) \
141 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
142#define ufshcd_is_ufs_dev_sleep(h) \
143 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
144#define ufshcd_is_ufs_dev_poweroff(h) \
145 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
146
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147/*
148 * UFS Power management levels.
149 * Each level is in increasing order of power savings.
150 */
151enum ufs_pm_level {
152 UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
153 UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
154 UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
155 UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
156 UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
157 UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
158 UFS_PM_LVL_MAX
159};
160
161struct ufs_pm_lvl_states {
162 enum ufs_dev_pwr_mode dev_state;
163 enum uic_link_state link_state;
164};
165
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166/**
167 * struct ufshcd_lrb - local reference block
168 * @utr_descriptor_ptr: UTRD address of the command
5a0b0cb9 169 * @ucd_req_ptr: UCD address of the command
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170 * @ucd_rsp_ptr: Response UPIU address for this command
171 * @ucd_prdt_ptr: PRDT address of the command
ff8e20c6
DR
172 * @utrd_dma_addr: UTRD dma address for debug
173 * @ucd_prdt_dma_addr: PRDT dma address for debug
174 * @ucd_rsp_dma_addr: UPIU response dma address for debug
175 * @ucd_req_dma_addr: UPIU request dma address for debug
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176 * @cmd: pointer to SCSI command
177 * @sense_buffer: pointer to sense buffer address of the SCSI command
178 * @sense_bufflen: Length of the sense buffer
179 * @scsi_status: SCSI status of the command
180 * @command_type: SCSI, UFS, Query.
181 * @task_tag: Task tag of the command
182 * @lun: LUN of the command
5a0b0cb9 183 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
ff8e20c6 184 * @issue_time_stamp: time stamp for debug purposes
09017188 185 * @compl_time_stamp: time stamp for statistics
e0b299e3 186 * @req_abort_skip: skip request abort task flag
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187 */
188struct ufshcd_lrb {
189 struct utp_transfer_req_desc *utr_descriptor_ptr;
5a0b0cb9 190 struct utp_upiu_req *ucd_req_ptr;
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191 struct utp_upiu_rsp *ucd_rsp_ptr;
192 struct ufshcd_sg_entry *ucd_prdt_ptr;
193
ff8e20c6
DR
194 dma_addr_t utrd_dma_addr;
195 dma_addr_t ucd_req_dma_addr;
196 dma_addr_t ucd_rsp_dma_addr;
197 dma_addr_t ucd_prdt_dma_addr;
198
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199 struct scsi_cmnd *cmd;
200 u8 *sense_buffer;
201 unsigned int sense_bufflen;
202 int scsi_status;
203
204 int command_type;
205 int task_tag;
0ce147d4 206 u8 lun; /* UPIU LUN id field is only 8-bit wide */
5a0b0cb9 207 bool intr_cmd;
ff8e20c6 208 ktime_t issue_time_stamp;
09017188 209 ktime_t compl_time_stamp;
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210
211 bool req_abort_skip;
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212};
213
68078d5c 214/**
a230c2f6 215 * struct ufs_query - holds relevant data structures for query request
68078d5c
DR
216 * @request: request upiu and function
217 * @descriptor: buffer for sending/receiving descriptor
218 * @response: response upiu and response
219 */
220struct ufs_query {
221 struct ufs_query_req request;
222 u8 *descriptor;
223 struct ufs_query_res response;
224};
225
5a0b0cb9
SRT
226/**
227 * struct ufs_dev_cmd - all assosiated fields with device management commands
228 * @type: device management command type - Query, NOP OUT
229 * @lock: lock to allow one command at a time
230 * @complete: internal commands completion
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231 */
232struct ufs_dev_cmd {
233 enum dev_cmd_type type;
234 struct mutex lock;
235 struct completion *complete;
68078d5c 236 struct ufs_query query;
5a0b0cb9 237};
e0eca63e 238
a4b0e8a4
PM
239struct ufs_desc_size {
240 int dev_desc;
241 int pwr_desc;
242 int geom_desc;
243 int interc_desc;
244 int unit_desc;
245 int conf_desc;
c648c2d2 246 int hlth_desc;
a4b0e8a4
PM
247};
248
c6e79dac
SRT
249/**
250 * struct ufs_clk_info - UFS clock related info
251 * @list: list headed by hba->clk_list_head
252 * @clk: clock node
253 * @name: clock name
254 * @max_freq: maximum frequency supported by the clock
4cff6d99 255 * @min_freq: min frequency that can be used for clock scaling
856b3483 256 * @curr_freq: indicates the current frequency that it is set to
c6e79dac
SRT
257 * @enabled: variable to check against multiple enable/disable
258 */
259struct ufs_clk_info {
260 struct list_head list;
261 struct clk *clk;
262 const char *name;
263 u32 max_freq;
4cff6d99 264 u32 min_freq;
856b3483 265 u32 curr_freq;
c6e79dac
SRT
266 bool enabled;
267};
268
f06fcc71
YG
269enum ufs_notify_change_status {
270 PRE_CHANGE,
271 POST_CHANGE,
272};
7eb584db
DR
273
274struct ufs_pa_layer_attr {
275 u32 gear_rx;
276 u32 gear_tx;
277 u32 lane_rx;
278 u32 lane_tx;
279 u32 pwr_rx;
280 u32 pwr_tx;
281 u32 hs_rate;
282};
283
284struct ufs_pwr_mode_info {
285 bool is_valid;
286 struct ufs_pa_layer_attr info;
287};
288
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SRT
289/**
290 * struct ufs_hba_variant_ops - variant specific callbacks
291 * @name: variant name
292 * @init: called when the driver is initialized
293 * @exit: called to cleanup everything done in init
9949e702 294 * @get_ufs_hci_version: called to get UFS HCI version
856b3483 295 * @clk_scale_notify: notifies that clks are scaled up/down
5c0c28a8
SRT
296 * @setup_clocks: called before touching any of the controller registers
297 * @setup_regulators: called before accessing the host controller
298 * @hce_enable_notify: called before and after HCE enable bit is set to allow
299 * variant specific Uni-Pro initialization.
300 * @link_startup_notify: called before and after Link startup is carried out
301 * to allow variant specific Uni-Pro initialization.
7eb584db
DR
302 * @pwr_change_notify: called before and after a power mode change
303 * is carried out to allow vendor spesific capabilities
304 * to be set.
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KK
305 * @setup_xfer_req: called before any transfer request is issued
306 * to set some things
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307 * @setup_task_mgmt: called before any task management request is issued
308 * to set some things
ee32c909 309 * @hibern8_notify: called around hibern8 enter/exit
56d4a186 310 * @apply_dev_quirks: called to apply device specific quirks
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311 * @suspend: called during host controller PM callback
312 * @resume: called during host controller PM callback
6e3fd44d 313 * @dbg_register_dump: used to dump controller debug information
4b9ffb5a 314 * @phy_initialization: used to initialize phys
d8d9f793 315 * @device_reset: called to issue a reset pulse on the UFS device
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SRT
316 */
317struct ufs_hba_variant_ops {
318 const char *name;
319 int (*init)(struct ufs_hba *);
320 void (*exit)(struct ufs_hba *);
9949e702 321 u32 (*get_ufs_hci_version)(struct ufs_hba *);
f06fcc71
YG
322 int (*clk_scale_notify)(struct ufs_hba *, bool,
323 enum ufs_notify_change_status);
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SJ
324 int (*setup_clocks)(struct ufs_hba *, bool,
325 enum ufs_notify_change_status);
5c0c28a8 326 int (*setup_regulators)(struct ufs_hba *, bool);
f06fcc71
YG
327 int (*hce_enable_notify)(struct ufs_hba *,
328 enum ufs_notify_change_status);
329 int (*link_startup_notify)(struct ufs_hba *,
330 enum ufs_notify_change_status);
7eb584db 331 int (*pwr_change_notify)(struct ufs_hba *,
f06fcc71
YG
332 enum ufs_notify_change_status status,
333 struct ufs_pa_layer_attr *,
7eb584db 334 struct ufs_pa_layer_attr *);
0e675efa 335 void (*setup_xfer_req)(struct ufs_hba *, int, bool);
d2877be4 336 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
ee32c909 337 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
56d4a186 338 enum ufs_notify_change_status);
09750066 339 int (*apply_dev_quirks)(struct ufs_hba *hba);
c28c00ba 340 void (*fixup_dev_quirks)(struct ufs_hba *hba);
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SJ
341 int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
342 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
6e3fd44d 343 void (*dbg_register_dump)(struct ufs_hba *hba);
4b9ffb5a 344 int (*phy_initialization)(struct ufs_hba *);
d8d9f793 345 void (*device_reset)(struct ufs_hba *hba);
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AD
346 void (*config_scaling_param)(struct ufs_hba *hba,
347 struct devfreq_dev_profile *profile,
348 void *data);
5c0c28a8
SRT
349};
350
1ab27c9c
ST
351/* clock gating state */
352enum clk_gating_state {
353 CLKS_OFF,
354 CLKS_ON,
355 REQ_CLKS_OFF,
356 REQ_CLKS_ON,
357};
358
359/**
360 * struct ufs_clk_gating - UFS clock gating related info
361 * @gate_work: worker to turn off clocks after some delay as specified in
362 * delay_ms
363 * @ungate_work: worker to turn on clocks that will be used in case of
364 * interrupt context
365 * @state: the current clocks state
366 * @delay_ms: gating delay in ms
367 * @is_suspended: clk gating is suspended when set to 1 which can be used
368 * during suspend/resume
369 * @delay_attr: sysfs attribute to control delay_attr
b427411a
ST
370 * @enable_attr: sysfs attribute to enable/disable clock gating
371 * @is_enabled: Indicates the current status of clock gating
1ab27c9c
ST
372 * @active_reqs: number of requests that are pending and should be waited for
373 * completion before gating clocks.
374 */
375struct ufs_clk_gating {
376 struct delayed_work gate_work;
377 struct work_struct ungate_work;
378 enum clk_gating_state state;
379 unsigned long delay_ms;
380 bool is_suspended;
381 struct device_attribute delay_attr;
b427411a
ST
382 struct device_attribute enable_attr;
383 bool is_enabled;
1ab27c9c 384 int active_reqs;
10e5e375 385 struct workqueue_struct *clk_gating_workq;
1ab27c9c
ST
386};
387
a3cd5ec5 388struct ufs_saved_pwr_info {
389 struct ufs_pa_layer_attr info;
390 bool is_valid;
391};
392
401f1e44 393/**
394 * struct ufs_clk_scaling - UFS clock scaling related data
395 * @active_reqs: number of requests that are pending. If this is zero when
396 * devfreq ->target() function is called then schedule "suspend_work" to
397 * suspend devfreq.
398 * @tot_busy_t: Total busy time in current polling window
399 * @window_start_t: Start time (in jiffies) of the current polling window
400 * @busy_start_t: Start time of current busy period
401 * @enable_attr: sysfs attribute to enable/disable clock scaling
402 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
403 * one keeps track of previous power mode.
404 * @workq: workqueue to schedule devfreq suspend/resume work
405 * @suspend_work: worker to suspend devfreq
406 * @resume_work: worker to resume devfreq
407 * @is_allowed: tracks if scaling is currently allowed or not
408 * @is_busy_started: tracks if busy period has started or not
409 * @is_suspended: tracks if devfreq is suspended or not
410 */
856b3483 411struct ufs_clk_scaling {
401f1e44 412 int active_reqs;
413 unsigned long tot_busy_t;
856b3483 414 unsigned long window_start_t;
401f1e44 415 ktime_t busy_start_t;
fcb0c4b0 416 struct device_attribute enable_attr;
a3cd5ec5 417 struct ufs_saved_pwr_info saved_pwr_info;
401f1e44 418 struct workqueue_struct *workq;
419 struct work_struct suspend_work;
420 struct work_struct resume_work;
421 bool is_allowed;
422 bool is_busy_started;
423 bool is_suspended;
856b3483
ST
424};
425
48d5b973 426#define UFS_ERR_REG_HIST_LENGTH 8
ff8e20c6 427/**
d3c615bf 428 * struct ufs_err_reg_hist - keeps history of errors
ff8e20c6
DR
429 * @pos: index to indicate cyclic buffer position
430 * @reg: cyclic buffer for registers value
431 * @tstamp: cyclic buffer for time stamp
432 */
48d5b973 433struct ufs_err_reg_hist {
ff8e20c6 434 int pos;
48d5b973
SC
435 u32 reg[UFS_ERR_REG_HIST_LENGTH];
436 ktime_t tstamp[UFS_ERR_REG_HIST_LENGTH];
ff8e20c6
DR
437};
438
439/**
440 * struct ufs_stats - keeps usage/err statistics
441 * @hibern8_exit_cnt: Counter to keep track of number of exits,
442 * reset this after link-startup.
443 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
444 * Clear after the first successful command completion.
445 * @pa_err: tracks pa-uic errors
446 * @dl_err: tracks dl-uic errors
447 * @nl_err: tracks nl-uic errors
448 * @tl_err: tracks tl-uic errors
449 * @dme_err: tracks dme errors
d3c615bf 450 * @auto_hibern8_err: tracks auto-hibernate errors
8808b4e9
SC
451 * @fatal_err: tracks fatal errors
452 * @linkup_err: tracks link-startup errors
453 * @resume_err: tracks resume errors
454 * @suspend_err: tracks suspend errors
455 * @dev_reset: tracks device reset events
456 * @host_reset: tracks host reset events
457 * @tsk_abort: tracks task abort events
ff8e20c6
DR
458 */
459struct ufs_stats {
460 u32 hibern8_exit_cnt;
461 ktime_t last_hibern8_exit_tstamp;
d3c615bf
SC
462
463 /* uic specific errors */
48d5b973
SC
464 struct ufs_err_reg_hist pa_err;
465 struct ufs_err_reg_hist dl_err;
466 struct ufs_err_reg_hist nl_err;
467 struct ufs_err_reg_hist tl_err;
468 struct ufs_err_reg_hist dme_err;
d3c615bf
SC
469
470 /* fatal errors */
d3c615bf 471 struct ufs_err_reg_hist auto_hibern8_err;
8808b4e9
SC
472 struct ufs_err_reg_hist fatal_err;
473 struct ufs_err_reg_hist link_startup_err;
474 struct ufs_err_reg_hist resume_err;
475 struct ufs_err_reg_hist suspend_err;
476
477 /* abnormal events */
478 struct ufs_err_reg_hist dev_reset;
479 struct ufs_err_reg_hist host_reset;
480 struct ufs_err_reg_hist task_abort;
ff8e20c6
DR
481};
482
c3f7d1fc
CH
483enum ufshcd_quirks {
484 /* Interrupt aggregation support is broken */
485 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
486
487 /*
488 * delay before each dme command is required as the unipro
489 * layer has shown instabilities
490 */
491 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
492
493 /*
494 * If UFS host controller is having issue in processing LCC (Line
495 * Control Command) coming from device then enable this quirk.
496 * When this quirk is enabled, host controller driver should disable
497 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
498 * attribute of device to 0).
499 */
500 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
501
502 /*
503 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
504 * inbound Link supports unterminated line in HS mode. Setting this
505 * attribute to 1 fixes moving to HS gear.
506 */
507 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
508
509 /*
510 * This quirk needs to be enabled if the host controller only allows
511 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
512 * SLOW AUTO).
513 */
514 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
515
516 /*
517 * This quirk needs to be enabled if the host controller doesn't
518 * advertise the correct version in UFS_VER register. If this quirk
519 * is enabled, standard UFS host driver will call the vendor specific
520 * ops (get_ufs_hci_version) to get the correct version.
521 */
522 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
87183841
AA
523
524 /*
525 * Clear handling for transfer/task request list is just opposite.
526 */
527 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
b638b5eb
AA
528
529 /*
530 * This quirk needs to be enabled if host controller doesn't allow
531 * that the interrupt aggregation timer and counter are reset by s/w.
532 */
533 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
39bf2d83
AA
534
535 /*
536 * This quirks needs to be enabled if host controller cannot be
537 * enabled via HCE register.
538 */
539 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
26f968d7
AA
540
541 /*
542 * This quirk needs to be enabled if the host controller regards
543 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
544 */
545 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
d779a6e9
KK
546
547 /*
548 * This quirk needs to be enabled if the host controller reports
549 * OCS FATAL ERROR with device error through sense data
550 */
551 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
c3f7d1fc
CH
552};
553
c2014682
SC
554enum ufshcd_caps {
555 /* Allow dynamic clk gating */
556 UFSHCD_CAP_CLK_GATING = 1 << 0,
557
558 /* Allow hiberb8 with clk gating */
559 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
560
561 /* Allow dynamic clk scaling */
562 UFSHCD_CAP_CLK_SCALING = 1 << 2,
563
564 /* Allow auto bkops to enabled during runtime suspend */
565 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
566
567 /*
568 * This capability allows host controller driver to use the UFS HCI's
569 * interrupt aggregation capability.
570 * CAUTION: Enabling this might reduce overall UFS throughput.
571 */
572 UFSHCD_CAP_INTR_AGGR = 1 << 4,
573
574 /*
575 * This capability allows the device auto-bkops to be always enabled
576 * except during suspend (both runtime and suspend).
577 * Enabling this capability means that device will always be allowed
578 * to do background operation when it's active but it might degrade
579 * the performance of ongoing read/write operations.
580 */
581 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
582
583 /*
584 * This capability allows host controller driver to automatically
585 * enable runtime power management by itself instead of waiting
586 * for userspace to control the power management.
587 */
588 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
3d17b9b5
AD
589
590 /*
591 * This capability allows the host controller driver to turn-on
592 * WriteBooster, if the underlying device supports it and is
593 * provisioned to be used. This would increase the write performance.
594 */
595 UFSHCD_CAP_WB_EN = 1 << 7,
c2014682
SC
596};
597
90b8491c
SC
598struct ufs_hba_variant_params {
599 struct devfreq_dev_profile devfreq_profile;
600 struct devfreq_simple_ondemand_data ondemand_data;
601 u16 hba_enable_delay_us;
d14734ae 602 u32 wb_flush_threshold;
90b8491c
SC
603};
604
e0eca63e
VH
605/**
606 * struct ufs_hba - per adapter private structure
607 * @mmio_base: UFSHCI base register address
608 * @ucdl_base_addr: UFS Command Descriptor base address
609 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
610 * @utmrdl_base_addr: UTP Task Management Descriptor base address
611 * @ucdl_dma_addr: UFS Command Descriptor DMA address
612 * @utrdl_dma_addr: UTRDL DMA address
613 * @utmrdl_dma_addr: UTMRDL DMA address
614 * @host: Scsi_Host instance of the driver
615 * @dev: device handle
616 * @lrb: local reference block
7252a360 617 * @cmd_queue: Used to allocate command tags from hba->host->tag_set.
e0eca63e
VH
618 * @outstanding_tasks: Bits representing outstanding task requests
619 * @outstanding_reqs: Bits representing outstanding transfer requests
620 * @capabilities: UFS Controller Capabilities
621 * @nutrs: Transfer Request Queue depth supported by controller
622 * @nutmrs: Task Management Queue depth supported by controller
623 * @ufs_version: UFS Version to which controller complies
5c0c28a8
SRT
624 * @vops: pointer to variant specific operations
625 * @priv: pointer to variant specific private data
e0eca63e
VH
626 * @irq: Irq number of the controller
627 * @active_uic_cmd: handle of active UIC command
6ccf44fe 628 * @uic_cmd_mutex: mutex for uic command
69a6c269
BVA
629 * @tmf_tag_set: TMF tag set.
630 * @tmf_queue: Used to allocate TMF tags.
53b3d9c3 631 * @pwr_done: completion for power mode change
e0eca63e 632 * @ufshcd_state: UFSHCD states
3441da7d 633 * @eh_flags: Error handling flags
2fbd009b 634 * @intr_mask: Interrupt Mask Bits
66ec6d59 635 * @ee_ctrl_mask: Exception event control mask
1d337ec2 636 * @is_powered: flag to check if HBA is powered
e8e7f271 637 * @eh_work: Worker to handle UFS errors that require s/w attention
66ec6d59 638 * @eeh_work: Worker to handle exception events
e0eca63e 639 * @errors: HBA errors
e8e7f271
SRT
640 * @uic_error: UFS interconnect layer error status
641 * @saved_err: sticky error mask
642 * @saved_uic_err: sticky UIC error mask
2df74b69 643 * @silence_err_logs: flag to silence error logs
5a0b0cb9 644 * @dev_cmd: ufs device management command information
cad2e03d 645 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
66ec6d59 646 * @auto_bkops_enabled: to track whether bkops is enabled in device
aa497613 647 * @vreg_info: UFS device voltage regulator information
c6e79dac 648 * @clk_list_head: UFS host controller clocks list node head
7eb584db
DR
649 * @pwr_info: holds current power mode
650 * @max_pwr_info: keeps the device max valid pwm
a4b0e8a4 651 * @desc_size: descriptor sizes reported by device
afdfff59
YG
652 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
653 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
654 * device is known or not.
38135535 655 * @scsi_block_reqs_cnt: reference counting for scsi block requests
e0eca63e
VH
656 */
657struct ufs_hba {
658 void __iomem *mmio_base;
659
660 /* Virtual memory reference */
661 struct utp_transfer_cmd_desc *ucdl_base_addr;
662 struct utp_transfer_req_desc *utrdl_base_addr;
663 struct utp_task_req_desc *utmrdl_base_addr;
664
665 /* DMA memory reference */
666 dma_addr_t ucdl_dma_addr;
667 dma_addr_t utrdl_dma_addr;
668 dma_addr_t utmrdl_dma_addr;
669
670 struct Scsi_Host *host;
671 struct device *dev;
7252a360 672 struct request_queue *cmd_queue;
2a8fa600
SJ
673 /*
674 * This field is to keep a reference to "scsi_device" corresponding to
675 * "UFS device" W-LU.
676 */
677 struct scsi_device *sdev_ufs_device;
e0eca63e 678
57d104c1
SJ
679 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
680 enum uic_link_state uic_link_state;
681 /* Desired UFS power management level during runtime PM */
682 enum ufs_pm_level rpm_lvl;
683 /* Desired UFS power management level during system PM */
684 enum ufs_pm_level spm_lvl;
09690d5a 685 struct device_attribute rpm_lvl_attr;
686 struct device_attribute spm_lvl_attr;
57d104c1
SJ
687 int pm_op_in_progress;
688
ad448378
AH
689 /* Auto-Hibernate Idle Timer register value */
690 u32 ahit;
691
e0eca63e
VH
692 struct ufshcd_lrb *lrb;
693
694 unsigned long outstanding_tasks;
695 unsigned long outstanding_reqs;
696
697 u32 capabilities;
698 int nutrs;
699 int nutmrs;
700 u32 ufs_version;
176eb927 701 const struct ufs_hba_variant_ops *vops;
90b8491c 702 struct ufs_hba_variant_params *vps;
5c0c28a8 703 void *priv;
e0eca63e 704 unsigned int irq;
57d104c1 705 bool is_irq_enabled;
9e1e8a75 706 enum ufs_ref_clk_freq dev_ref_clk_freq;
e0eca63e 707
cad2e03d 708 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
6ccf44fe 709
c58ab7aa
YG
710 /* Device deviations from standard UFS device spec. */
711 unsigned int dev_quirks;
712
69a6c269
BVA
713 struct blk_mq_tag_set tmf_tag_set;
714 struct request_queue *tmf_queue;
e0eca63e 715
57d104c1
SJ
716 struct uic_command *active_uic_cmd;
717 struct mutex uic_cmd_mutex;
718 struct completion *uic_async_done;
53b3d9c3 719
e0eca63e 720 u32 ufshcd_state;
3441da7d 721 u32 eh_flags;
2fbd009b 722 u32 intr_mask;
66ec6d59 723 u16 ee_ctrl_mask;
1d337ec2 724 bool is_powered;
e0eca63e
VH
725
726 /* Work Queues */
e8e7f271 727 struct work_struct eh_work;
66ec6d59 728 struct work_struct eeh_work;
e0eca63e
VH
729
730 /* HBA Errors */
731 u32 errors;
e8e7f271
SRT
732 u32 uic_error;
733 u32 saved_err;
734 u32 saved_uic_err;
ff8e20c6 735 struct ufs_stats ufs_stats;
2df74b69 736 bool silence_err_logs;
5a0b0cb9
SRT
737
738 /* Device management request data */
739 struct ufs_dev_cmd dev_cmd;
cad2e03d 740 ktime_t last_dme_cmd_tstamp;
66ec6d59 741
57d104c1
SJ
742 /* Keeps information of the UFS device connected to this host */
743 struct ufs_dev_info dev_info;
66ec6d59 744 bool auto_bkops_enabled;
aa497613 745 struct ufs_vreg_info vreg_info;
c6e79dac 746 struct list_head clk_list_head;
57d104c1
SJ
747
748 bool wlun_dev_clr_ua;
7eb584db 749
7fabb77b
GB
750 /* Number of requests aborts */
751 int req_abort_count;
752
54b879b7
YG
753 /* Number of lanes available (1 or 2) for Rx/Tx */
754 u32 lanes_per_direction;
7eb584db
DR
755 struct ufs_pa_layer_attr pwr_info;
756 struct ufs_pwr_mode_info max_pwr_info;
1ab27c9c
ST
757
758 struct ufs_clk_gating clk_gating;
759 /* Control to enable/disable host capabilities */
760 u32 caps;
856b3483
ST
761
762 struct devfreq *devfreq;
763 struct ufs_clk_scaling clk_scaling;
e785060e 764 bool is_sys_suspended;
afdfff59
YG
765
766 enum bkops_status urgent_bkops_lvl;
767 bool is_urgent_bkops_lvl_checked;
a3cd5ec5 768
769 struct rw_semaphore clk_scaling_lock;
a4b0e8a4 770 struct ufs_desc_size desc_size;
38135535 771 atomic_t scsi_block_reqs_cnt;
df032bf2
AA
772
773 struct device bsg_dev;
774 struct request_queue *bsg_queue;
3d17b9b5
AD
775 bool wb_buf_flush_enabled;
776 bool wb_enabled;
51dd905b 777 struct delayed_work rpm_dev_flush_recheck_work;
e0eca63e
VH
778};
779
1ab27c9c
ST
780/* Returns true if clocks can be gated. Otherwise false */
781static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
782{
783 return hba->caps & UFSHCD_CAP_CLK_GATING;
784}
785static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
786{
787 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
788}
fcb0c4b0 789static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
856b3483
ST
790{
791 return hba->caps & UFSHCD_CAP_CLK_SCALING;
792}
374a246e
SJ
793static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
794{
795 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
796}
49615ba1
SC
797static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
798{
799 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
800}
374a246e 801
b852190e
YG
802static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
803{
4b9ffb5a
JP
804/* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
805#ifndef CONFIG_SCSI_UFS_DWC
b852190e
YG
806 if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
807 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
808 return true;
809 else
810 return false;
4b9ffb5a
JP
811#else
812return true;
813#endif
b852190e
YG
814}
815
ee5f1042
SC
816static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
817{
818 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT);
819}
820
5a244e0e
SC
821static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
822{
823 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit) ? true : false;
824}
825
3d17b9b5
AD
826static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
827{
828 return hba->caps & UFSHCD_CAP_WB_EN;
829}
830
b873a275
SJ
831#define ufshcd_writel(hba, val, reg) \
832 writel((val), (hba)->mmio_base + (reg))
833#define ufshcd_readl(hba, reg) \
834 readl((hba)->mmio_base + (reg))
835
e785060e
DR
836/**
837 * ufshcd_rmwl - read modify write into a register
838 * @hba - per adapter instance
839 * @mask - mask to apply on read value
840 * @val - actual value to write
841 * @reg - register address
842 */
843static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
844{
845 u32 tmp;
846
847 tmp = ufshcd_readl(hba, reg);
848 tmp &= ~mask;
849 tmp |= (val & mask);
850 ufshcd_writel(hba, tmp, reg);
851}
852
5c0c28a8 853int ufshcd_alloc_host(struct device *, struct ufs_hba **);
47555a5c 854void ufshcd_dealloc_host(struct ufs_hba *);
9d19bf7a 855int ufshcd_hba_enable(struct ufs_hba *hba);
5c0c28a8 856int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
087c5efa 857int ufshcd_link_recovery(struct ufs_hba *hba);
9d19bf7a 858int ufshcd_make_hba_operational(struct ufs_hba *hba);
e0eca63e 859void ufshcd_remove(struct ufs_hba *);
9d19bf7a 860int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
5c955c10 861void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
596585a2
YG
862int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
863 u32 val, unsigned long interval_us,
5cac1095 864 unsigned long timeout_ms);
9e1e8a75 865void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
a5fe372d
SC
866void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
867 u32 reg);
e0eca63e 868
68078d5c
DR
869static inline void check_upiu_size(void)
870{
871 BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
872 GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
873}
874
1ce5898a
YG
875/**
876 * ufshcd_set_variant - set variant specific data to the hba
877 * @hba - per adapter instance
878 * @variant - pointer to variant specific data
879 */
880static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
881{
882 BUG_ON(!hba);
883 hba->priv = variant;
884}
885
886/**
887 * ufshcd_get_variant - get variant specific data from the hba
888 * @hba - per adapter instance
889 */
890static inline void *ufshcd_get_variant(struct ufs_hba *hba)
891{
892 BUG_ON(!hba);
893 return hba->priv;
894}
4e768e76 895static inline bool ufshcd_keep_autobkops_enabled_except_suspend(
896 struct ufs_hba *hba)
897{
898 return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND;
899}
1ce5898a 900
e31011ab 901static inline u8 ufshcd_wb_get_query_index(struct ufs_hba *hba)
6f8d5a6a
SC
902{
903 if (hba->dev_info.b_wb_buffer_type == WB_BUF_MODE_LU_DEDICATED)
904 return hba->dev_info.wb_dedicated_lu;
905 return 0;
906}
907
66ec6d59
SRT
908extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
909extern int ufshcd_runtime_resume(struct ufs_hba *hba);
910extern int ufshcd_runtime_idle(struct ufs_hba *hba);
57d104c1
SJ
911extern int ufshcd_system_suspend(struct ufs_hba *hba);
912extern int ufshcd_system_resume(struct ufs_hba *hba);
913extern int ufshcd_shutdown(struct ufs_hba *hba);
12b4fdb4
SJ
914extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
915 u8 attr_set, u32 mib_val, u8 peer);
916extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
917 u32 *mib_val, u8 peer);
0d846e70
AA
918extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
919 struct ufs_pa_layer_attr *desired_pwr_mode);
12b4fdb4
SJ
920
921/* UIC command interfaces for DME primitives */
922#define DME_LOCAL 0
923#define DME_PEER 1
924#define ATTR_SET_NOR 0 /* NORMAL */
925#define ATTR_SET_ST 1 /* STATIC */
926
927static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
928 u32 mib_val)
929{
930 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
931 mib_val, DME_LOCAL);
932}
933
934static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
935 u32 mib_val)
936{
937 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
938 mib_val, DME_LOCAL);
939}
940
941static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
942 u32 mib_val)
943{
944 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
945 mib_val, DME_PEER);
946}
947
948static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
949 u32 mib_val)
950{
951 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
952 mib_val, DME_PEER);
953}
954
955static inline int ufshcd_dme_get(struct ufs_hba *hba,
956 u32 attr_sel, u32 *mib_val)
957{
958 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
959}
960
961static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
962 u32 attr_sel, u32 *mib_val)
963{
964 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
965}
966
f37aabcf
YG
967static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
968{
969 return (pwr_info->pwr_rx == FAST_MODE ||
970 pwr_info->pwr_rx == FASTAUTO_MODE) &&
971 (pwr_info->pwr_tx == FAST_MODE ||
972 pwr_info->pwr_tx == FASTAUTO_MODE);
973}
974
984eaac1
SC
975static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
976{
977 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
978}
979
dc3c8d3a 980/* Expose Query-Request API */
2238d31c
SN
981int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
982 enum query_opcode opcode,
983 enum desc_idn idn, u8 index,
984 u8 selector,
985 u8 *desc_buf, int *buf_len);
45bced87
SN
986int ufshcd_read_desc_param(struct ufs_hba *hba,
987 enum desc_idn desc_id,
988 int desc_index,
989 u8 param_offset,
990 u8 *param_read_buf,
991 u8 param_size);
ec92b59c
SN
992int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
993 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val);
dc3c8d3a 994int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 995 enum flag_idn idn, u8 index, bool *flag_res);
4b828fe1 996
71d848b8 997void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
ba7af5ec 998void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
8db269a5 999void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups);
4b828fe1
TW
1000#define SD_ASCII_STD true
1001#define SD_RAW false
1002int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1003 u8 **buf, bool ascii);
2238d31c 1004
1ab27c9c
ST
1005int ufshcd_hold(struct ufs_hba *hba, bool async);
1006void ufshcd_release(struct ufs_hba *hba);
a4b0e8a4
PM
1007
1008int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1009 int *desc_length);
1010
37113106 1011u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
0263bcd0 1012
e77044c5
AA
1013int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1014
5e0a86ee
AA
1015int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
1016 struct utp_upiu_req *req_upiu,
1017 struct utp_upiu_req *rsp_upiu,
1018 int msgcode,
1019 u8 *desc_buff, int *buff_len,
1020 enum query_opcode desc_op);
1021
0263bcd0
YG
1022/* Wrapper functions for safely calling variant operations */
1023static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
1024{
1025 if (hba->vops)
1026 return hba->vops->name;
1027 return "";
1028}
1029
1030static inline int ufshcd_vops_init(struct ufs_hba *hba)
1031{
1032 if (hba->vops && hba->vops->init)
1033 return hba->vops->init(hba);
1034
1035 return 0;
1036}
1037
1038static inline void ufshcd_vops_exit(struct ufs_hba *hba)
1039{
1040 if (hba->vops && hba->vops->exit)
1041 return hba->vops->exit(hba);
1042}
1043
1044static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba)
1045{
1046 if (hba->vops && hba->vops->get_ufs_hci_version)
1047 return hba->vops->get_ufs_hci_version(hba);
1048
1049 return ufshcd_readl(hba, REG_UFS_VERSION);
1050}
1051
f06fcc71
YG
1052static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba,
1053 bool up, enum ufs_notify_change_status status)
0263bcd0
YG
1054{
1055 if (hba->vops && hba->vops->clk_scale_notify)
f06fcc71
YG
1056 return hba->vops->clk_scale_notify(hba, up, status);
1057 return 0;
0263bcd0
YG
1058}
1059
1e879e8f
SJ
1060static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on,
1061 enum ufs_notify_change_status status)
0263bcd0
YG
1062{
1063 if (hba->vops && hba->vops->setup_clocks)
1e879e8f 1064 return hba->vops->setup_clocks(hba, on, status);
0263bcd0
YG
1065 return 0;
1066}
1067
1068static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status)
1069{
1070 if (hba->vops && hba->vops->setup_regulators)
1071 return hba->vops->setup_regulators(hba, status);
1072
1073 return 0;
1074}
1075
1076static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba,
1077 bool status)
1078{
1079 if (hba->vops && hba->vops->hce_enable_notify)
1080 return hba->vops->hce_enable_notify(hba, status);
1081
1082 return 0;
1083}
1084static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba,
1085 bool status)
1086{
1087 if (hba->vops && hba->vops->link_startup_notify)
1088 return hba->vops->link_startup_notify(hba, status);
1089
1090 return 0;
1091}
1092
1093static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba,
1094 bool status,
1095 struct ufs_pa_layer_attr *dev_max_params,
1096 struct ufs_pa_layer_attr *dev_req_params)
1097{
1098 if (hba->vops && hba->vops->pwr_change_notify)
1099 return hba->vops->pwr_change_notify(hba, status,
1100 dev_max_params, dev_req_params);
1101
1102 return -ENOTSUPP;
1103}
1104
0e675efa
KK
1105static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag,
1106 bool is_scsi_cmd)
1107{
1108 if (hba->vops && hba->vops->setup_xfer_req)
1109 return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd);
1110}
1111
d2877be4
KK
1112static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba,
1113 int tag, u8 tm_function)
1114{
1115 if (hba->vops && hba->vops->setup_task_mgmt)
1116 return hba->vops->setup_task_mgmt(hba, tag, tm_function);
1117}
1118
ee32c909
KK
1119static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
1120 enum uic_cmd_dme cmd,
1121 enum ufs_notify_change_status status)
1122{
1123 if (hba->vops && hba->vops->hibern8_notify)
1124 return hba->vops->hibern8_notify(hba, cmd, status);
1125}
1126
09750066 1127static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba)
56d4a186
SJ
1128{
1129 if (hba->vops && hba->vops->apply_dev_quirks)
09750066 1130 return hba->vops->apply_dev_quirks(hba);
56d4a186
SJ
1131 return 0;
1132}
1133
c28c00ba
SC
1134static inline void ufshcd_vops_fixup_dev_quirks(struct ufs_hba *hba)
1135{
1136 if (hba->vops && hba->vops->fixup_dev_quirks)
1137 hba->vops->fixup_dev_quirks(hba);
1138}
1139
0263bcd0
YG
1140static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op)
1141{
1142 if (hba->vops && hba->vops->suspend)
1143 return hba->vops->suspend(hba, op);
1144
1145 return 0;
1146}
1147
1148static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op)
1149{
1150 if (hba->vops && hba->vops->resume)
1151 return hba->vops->resume(hba, op);
1152
1153 return 0;
1154}
1155
6e3fd44d
YG
1156static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
1157{
1158 if (hba->vops && hba->vops->dbg_register_dump)
1159 hba->vops->dbg_register_dump(hba);
1160}
1161
d8d9f793
BA
1162static inline void ufshcd_vops_device_reset(struct ufs_hba *hba)
1163{
a5fe372d 1164 if (hba->vops && hba->vops->device_reset) {
d8d9f793 1165 hba->vops->device_reset(hba);
1764fa2a 1166 ufshcd_set_ufs_dev_active(hba);
a5fe372d
SC
1167 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, 0);
1168 }
d8d9f793
BA
1169}
1170
2c75f9a5
AD
1171static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba,
1172 struct devfreq_dev_profile
1173 *profile, void *data)
1174{
1175 if (hba->vops && hba->vops->config_scaling_param)
1176 hba->vops->config_scaling_param(hba, profile, data);
1177}
1178
cbb6813e
SN
1179extern struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1180
d829fc8a
SN
1181/*
1182 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1183 * @scsi_lun: scsi LUN id
1184 *
1185 * Returns UPIU LUN id
1186 */
1187static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1188{
1189 if (scsi_is_wlun(scsi_lun))
1190 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1191 | UFS_UPIU_WLUN_ID;
1192 else
1193 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1194}
1195
ba80917d
TW
1196int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1197 const char *prefix);
1198
e0eca63e 1199#endif /* End of Header */