scsi: esp_scsi: Add support for FSC chip
[linux-block.git] / drivers / scsi / ufs / ufshcd.h
CommitLineData
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1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
dc3c8d3a 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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7 *
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
35 */
36
37#ifndef _UFSHCD_H
38#define _UFSHCD_H
39
40#include <linux/module.h>
41#include <linux/kernel.h>
42#include <linux/init.h>
43#include <linux/interrupt.h>
44#include <linux/io.h>
45#include <linux/delay.h>
46#include <linux/slab.h>
47#include <linux/spinlock.h>
a3cd5ec5 48#include <linux/rwsem.h>
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49#include <linux/workqueue.h>
50#include <linux/errno.h>
51#include <linux/types.h>
52#include <linux/wait.h>
53#include <linux/bitops.h>
54#include <linux/pm_runtime.h>
55#include <linux/clk.h>
6ccf44fe 56#include <linux/completion.h>
aa497613 57#include <linux/regulator/consumer.h>
f37aabcf 58#include "unipro.h"
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59
60#include <asm/irq.h>
61#include <asm/byteorder.h>
62#include <scsi/scsi.h>
63#include <scsi/scsi_cmnd.h>
64#include <scsi/scsi_host.h>
65#include <scsi/scsi_tcq.h>
66#include <scsi/scsi_dbg.h>
67#include <scsi/scsi_eh.h>
68
69#include "ufs.h"
70#include "ufshci.h"
71
72#define UFSHCD "ufshcd"
73#define UFSHCD_DRIVER_VERSION "0.2"
74
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75struct ufs_hba;
76
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77enum dev_cmd_type {
78 DEV_CMD_TYPE_NOP = 0x0,
68078d5c 79 DEV_CMD_TYPE_QUERY = 0x1,
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80};
81
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82/**
83 * struct uic_command - UIC command structure
84 * @command: UIC command
85 * @argument1: UIC command argument 1
86 * @argument2: UIC command argument 2
87 * @argument3: UIC command argument 3
88 * @cmd_active: Indicate if UIC command is outstanding
89 * @result: UIC command result
6ccf44fe 90 * @done: UIC command completion
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91 */
92struct uic_command {
93 u32 command;
94 u32 argument1;
95 u32 argument2;
96 u32 argument3;
97 int cmd_active;
98 int result;
6ccf44fe 99 struct completion done;
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100};
101
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102/* Used to differentiate the power management options */
103enum ufs_pm_op {
104 UFS_RUNTIME_PM,
105 UFS_SYSTEM_PM,
106 UFS_SHUTDOWN_PM,
107};
108
109#define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
110#define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
111#define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
112
113/* Host <-> Device UniPro Link state */
114enum uic_link_state {
115 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
116 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
117 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
118};
119
120#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
121#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
122 UIC_LINK_ACTIVE_STATE)
123#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
124 UIC_LINK_HIBERN8_STATE)
125#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
126#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
127 UIC_LINK_ACTIVE_STATE)
128#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
129 UIC_LINK_HIBERN8_STATE)
130
131/*
132 * UFS Power management levels.
133 * Each level is in increasing order of power savings.
134 */
135enum ufs_pm_level {
136 UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
137 UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
138 UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
139 UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
140 UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
141 UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
142 UFS_PM_LVL_MAX
143};
144
145struct ufs_pm_lvl_states {
146 enum ufs_dev_pwr_mode dev_state;
147 enum uic_link_state link_state;
148};
149
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150/**
151 * struct ufshcd_lrb - local reference block
152 * @utr_descriptor_ptr: UTRD address of the command
5a0b0cb9 153 * @ucd_req_ptr: UCD address of the command
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154 * @ucd_rsp_ptr: Response UPIU address for this command
155 * @ucd_prdt_ptr: PRDT address of the command
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DR
156 * @utrd_dma_addr: UTRD dma address for debug
157 * @ucd_prdt_dma_addr: PRDT dma address for debug
158 * @ucd_rsp_dma_addr: UPIU response dma address for debug
159 * @ucd_req_dma_addr: UPIU request dma address for debug
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160 * @cmd: pointer to SCSI command
161 * @sense_buffer: pointer to sense buffer address of the SCSI command
162 * @sense_bufflen: Length of the sense buffer
163 * @scsi_status: SCSI status of the command
164 * @command_type: SCSI, UFS, Query.
165 * @task_tag: Task tag of the command
166 * @lun: LUN of the command
5a0b0cb9 167 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
ff8e20c6 168 * @issue_time_stamp: time stamp for debug purposes
09017188 169 * @compl_time_stamp: time stamp for statistics
e0b299e3 170 * @req_abort_skip: skip request abort task flag
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171 */
172struct ufshcd_lrb {
173 struct utp_transfer_req_desc *utr_descriptor_ptr;
5a0b0cb9 174 struct utp_upiu_req *ucd_req_ptr;
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175 struct utp_upiu_rsp *ucd_rsp_ptr;
176 struct ufshcd_sg_entry *ucd_prdt_ptr;
177
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178 dma_addr_t utrd_dma_addr;
179 dma_addr_t ucd_req_dma_addr;
180 dma_addr_t ucd_rsp_dma_addr;
181 dma_addr_t ucd_prdt_dma_addr;
182
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183 struct scsi_cmnd *cmd;
184 u8 *sense_buffer;
185 unsigned int sense_bufflen;
186 int scsi_status;
187
188 int command_type;
189 int task_tag;
0ce147d4 190 u8 lun; /* UPIU LUN id field is only 8-bit wide */
5a0b0cb9 191 bool intr_cmd;
ff8e20c6 192 ktime_t issue_time_stamp;
09017188 193 ktime_t compl_time_stamp;
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194
195 bool req_abort_skip;
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196};
197
68078d5c 198/**
a230c2f6 199 * struct ufs_query - holds relevant data structures for query request
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200 * @request: request upiu and function
201 * @descriptor: buffer for sending/receiving descriptor
202 * @response: response upiu and response
203 */
204struct ufs_query {
205 struct ufs_query_req request;
206 u8 *descriptor;
207 struct ufs_query_res response;
208};
209
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210/**
211 * struct ufs_dev_cmd - all assosiated fields with device management commands
212 * @type: device management command type - Query, NOP OUT
213 * @lock: lock to allow one command at a time
214 * @complete: internal commands completion
215 * @tag_wq: wait queue until free command slot is available
216 */
217struct ufs_dev_cmd {
218 enum dev_cmd_type type;
219 struct mutex lock;
220 struct completion *complete;
221 wait_queue_head_t tag_wq;
68078d5c 222 struct ufs_query query;
5a0b0cb9 223};
e0eca63e 224
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PM
225struct ufs_desc_size {
226 int dev_desc;
227 int pwr_desc;
228 int geom_desc;
229 int interc_desc;
230 int unit_desc;
231 int conf_desc;
c648c2d2 232 int hlth_desc;
a4b0e8a4
PM
233};
234
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235/**
236 * struct ufs_clk_info - UFS clock related info
237 * @list: list headed by hba->clk_list_head
238 * @clk: clock node
239 * @name: clock name
240 * @max_freq: maximum frequency supported by the clock
4cff6d99 241 * @min_freq: min frequency that can be used for clock scaling
856b3483 242 * @curr_freq: indicates the current frequency that it is set to
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243 * @enabled: variable to check against multiple enable/disable
244 */
245struct ufs_clk_info {
246 struct list_head list;
247 struct clk *clk;
248 const char *name;
249 u32 max_freq;
4cff6d99 250 u32 min_freq;
856b3483 251 u32 curr_freq;
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252 bool enabled;
253};
254
f06fcc71
YG
255enum ufs_notify_change_status {
256 PRE_CHANGE,
257 POST_CHANGE,
258};
7eb584db
DR
259
260struct ufs_pa_layer_attr {
261 u32 gear_rx;
262 u32 gear_tx;
263 u32 lane_rx;
264 u32 lane_tx;
265 u32 pwr_rx;
266 u32 pwr_tx;
267 u32 hs_rate;
268};
269
270struct ufs_pwr_mode_info {
271 bool is_valid;
272 struct ufs_pa_layer_attr info;
273};
274
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275/**
276 * struct ufs_hba_variant_ops - variant specific callbacks
277 * @name: variant name
278 * @init: called when the driver is initialized
279 * @exit: called to cleanup everything done in init
9949e702 280 * @get_ufs_hci_version: called to get UFS HCI version
856b3483 281 * @clk_scale_notify: notifies that clks are scaled up/down
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SRT
282 * @setup_clocks: called before touching any of the controller registers
283 * @setup_regulators: called before accessing the host controller
284 * @hce_enable_notify: called before and after HCE enable bit is set to allow
285 * variant specific Uni-Pro initialization.
286 * @link_startup_notify: called before and after Link startup is carried out
287 * to allow variant specific Uni-Pro initialization.
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288 * @pwr_change_notify: called before and after a power mode change
289 * is carried out to allow vendor spesific capabilities
290 * to be set.
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291 * @setup_xfer_req: called before any transfer request is issued
292 * to set some things
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293 * @setup_task_mgmt: called before any task management request is issued
294 * to set some things
ee32c909 295 * @hibern8_notify: called around hibern8 enter/exit
56d4a186 296 * @apply_dev_quirks: called to apply device specific quirks
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297 * @suspend: called during host controller PM callback
298 * @resume: called during host controller PM callback
6e3fd44d 299 * @dbg_register_dump: used to dump controller debug information
4b9ffb5a 300 * @phy_initialization: used to initialize phys
d8d9f793 301 * @device_reset: called to issue a reset pulse on the UFS device
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302 */
303struct ufs_hba_variant_ops {
304 const char *name;
305 int (*init)(struct ufs_hba *);
306 void (*exit)(struct ufs_hba *);
9949e702 307 u32 (*get_ufs_hci_version)(struct ufs_hba *);
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308 int (*clk_scale_notify)(struct ufs_hba *, bool,
309 enum ufs_notify_change_status);
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310 int (*setup_clocks)(struct ufs_hba *, bool,
311 enum ufs_notify_change_status);
5c0c28a8 312 int (*setup_regulators)(struct ufs_hba *, bool);
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313 int (*hce_enable_notify)(struct ufs_hba *,
314 enum ufs_notify_change_status);
315 int (*link_startup_notify)(struct ufs_hba *,
316 enum ufs_notify_change_status);
7eb584db 317 int (*pwr_change_notify)(struct ufs_hba *,
f06fcc71
YG
318 enum ufs_notify_change_status status,
319 struct ufs_pa_layer_attr *,
7eb584db 320 struct ufs_pa_layer_attr *);
0e675efa 321 void (*setup_xfer_req)(struct ufs_hba *, int, bool);
d2877be4 322 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
ee32c909 323 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
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324 enum ufs_notify_change_status);
325 int (*apply_dev_quirks)(struct ufs_hba *);
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326 int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
327 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
6e3fd44d 328 void (*dbg_register_dump)(struct ufs_hba *hba);
4b9ffb5a 329 int (*phy_initialization)(struct ufs_hba *);
d8d9f793 330 void (*device_reset)(struct ufs_hba *hba);
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331};
332
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333/* clock gating state */
334enum clk_gating_state {
335 CLKS_OFF,
336 CLKS_ON,
337 REQ_CLKS_OFF,
338 REQ_CLKS_ON,
339};
340
341/**
342 * struct ufs_clk_gating - UFS clock gating related info
343 * @gate_work: worker to turn off clocks after some delay as specified in
344 * delay_ms
345 * @ungate_work: worker to turn on clocks that will be used in case of
346 * interrupt context
347 * @state: the current clocks state
348 * @delay_ms: gating delay in ms
349 * @is_suspended: clk gating is suspended when set to 1 which can be used
350 * during suspend/resume
351 * @delay_attr: sysfs attribute to control delay_attr
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352 * @enable_attr: sysfs attribute to enable/disable clock gating
353 * @is_enabled: Indicates the current status of clock gating
1ab27c9c
ST
354 * @active_reqs: number of requests that are pending and should be waited for
355 * completion before gating clocks.
356 */
357struct ufs_clk_gating {
358 struct delayed_work gate_work;
359 struct work_struct ungate_work;
360 enum clk_gating_state state;
361 unsigned long delay_ms;
362 bool is_suspended;
363 struct device_attribute delay_attr;
b427411a
ST
364 struct device_attribute enable_attr;
365 bool is_enabled;
1ab27c9c 366 int active_reqs;
10e5e375 367 struct workqueue_struct *clk_gating_workq;
1ab27c9c
ST
368};
369
a3cd5ec5 370struct ufs_saved_pwr_info {
371 struct ufs_pa_layer_attr info;
372 bool is_valid;
373};
374
401f1e44 375/**
376 * struct ufs_clk_scaling - UFS clock scaling related data
377 * @active_reqs: number of requests that are pending. If this is zero when
378 * devfreq ->target() function is called then schedule "suspend_work" to
379 * suspend devfreq.
380 * @tot_busy_t: Total busy time in current polling window
381 * @window_start_t: Start time (in jiffies) of the current polling window
382 * @busy_start_t: Start time of current busy period
383 * @enable_attr: sysfs attribute to enable/disable clock scaling
384 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
385 * one keeps track of previous power mode.
386 * @workq: workqueue to schedule devfreq suspend/resume work
387 * @suspend_work: worker to suspend devfreq
388 * @resume_work: worker to resume devfreq
389 * @is_allowed: tracks if scaling is currently allowed or not
390 * @is_busy_started: tracks if busy period has started or not
391 * @is_suspended: tracks if devfreq is suspended or not
392 */
856b3483 393struct ufs_clk_scaling {
401f1e44 394 int active_reqs;
395 unsigned long tot_busy_t;
856b3483 396 unsigned long window_start_t;
401f1e44 397 ktime_t busy_start_t;
fcb0c4b0 398 struct device_attribute enable_attr;
a3cd5ec5 399 struct ufs_saved_pwr_info saved_pwr_info;
401f1e44 400 struct workqueue_struct *workq;
401 struct work_struct suspend_work;
402 struct work_struct resume_work;
403 bool is_allowed;
404 bool is_busy_started;
405 bool is_suspended;
856b3483
ST
406};
407
3a4bf06d
YG
408/**
409 * struct ufs_init_prefetch - contains data that is pre-fetched once during
410 * initialization
411 * @icc_level: icc level which was read during initialization
412 */
413struct ufs_init_prefetch {
414 u32 icc_level;
415};
416
48d5b973 417#define UFS_ERR_REG_HIST_LENGTH 8
ff8e20c6 418/**
d3c615bf 419 * struct ufs_err_reg_hist - keeps history of errors
ff8e20c6
DR
420 * @pos: index to indicate cyclic buffer position
421 * @reg: cyclic buffer for registers value
422 * @tstamp: cyclic buffer for time stamp
423 */
48d5b973 424struct ufs_err_reg_hist {
ff8e20c6 425 int pos;
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426 u32 reg[UFS_ERR_REG_HIST_LENGTH];
427 ktime_t tstamp[UFS_ERR_REG_HIST_LENGTH];
ff8e20c6
DR
428};
429
430/**
431 * struct ufs_stats - keeps usage/err statistics
432 * @hibern8_exit_cnt: Counter to keep track of number of exits,
433 * reset this after link-startup.
434 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
435 * Clear after the first successful command completion.
436 * @pa_err: tracks pa-uic errors
437 * @dl_err: tracks dl-uic errors
438 * @nl_err: tracks nl-uic errors
439 * @tl_err: tracks tl-uic errors
440 * @dme_err: tracks dme errors
d3c615bf 441 * @auto_hibern8_err: tracks auto-hibernate errors
8808b4e9
SC
442 * @fatal_err: tracks fatal errors
443 * @linkup_err: tracks link-startup errors
444 * @resume_err: tracks resume errors
445 * @suspend_err: tracks suspend errors
446 * @dev_reset: tracks device reset events
447 * @host_reset: tracks host reset events
448 * @tsk_abort: tracks task abort events
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DR
449 */
450struct ufs_stats {
451 u32 hibern8_exit_cnt;
452 ktime_t last_hibern8_exit_tstamp;
d3c615bf
SC
453
454 /* uic specific errors */
48d5b973
SC
455 struct ufs_err_reg_hist pa_err;
456 struct ufs_err_reg_hist dl_err;
457 struct ufs_err_reg_hist nl_err;
458 struct ufs_err_reg_hist tl_err;
459 struct ufs_err_reg_hist dme_err;
d3c615bf
SC
460
461 /* fatal errors */
d3c615bf 462 struct ufs_err_reg_hist auto_hibern8_err;
8808b4e9
SC
463 struct ufs_err_reg_hist fatal_err;
464 struct ufs_err_reg_hist link_startup_err;
465 struct ufs_err_reg_hist resume_err;
466 struct ufs_err_reg_hist suspend_err;
467
468 /* abnormal events */
469 struct ufs_err_reg_hist dev_reset;
470 struct ufs_err_reg_hist host_reset;
471 struct ufs_err_reg_hist task_abort;
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DR
472};
473
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474/**
475 * struct ufs_hba - per adapter private structure
476 * @mmio_base: UFSHCI base register address
477 * @ucdl_base_addr: UFS Command Descriptor base address
478 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
479 * @utmrdl_base_addr: UTP Task Management Descriptor base address
480 * @ucdl_dma_addr: UFS Command Descriptor DMA address
481 * @utrdl_dma_addr: UTRDL DMA address
482 * @utmrdl_dma_addr: UTMRDL DMA address
483 * @host: Scsi_Host instance of the driver
484 * @dev: device handle
485 * @lrb: local reference block
5a0b0cb9 486 * @lrb_in_use: lrb in use
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487 * @outstanding_tasks: Bits representing outstanding task requests
488 * @outstanding_reqs: Bits representing outstanding transfer requests
489 * @capabilities: UFS Controller Capabilities
490 * @nutrs: Transfer Request Queue depth supported by controller
491 * @nutmrs: Task Management Queue depth supported by controller
492 * @ufs_version: UFS Version to which controller complies
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SRT
493 * @vops: pointer to variant specific operations
494 * @priv: pointer to variant specific private data
e0eca63e
VH
495 * @irq: Irq number of the controller
496 * @active_uic_cmd: handle of active UIC command
6ccf44fe 497 * @uic_cmd_mutex: mutex for uic command
e2933132
SRT
498 * @tm_wq: wait queue for task management
499 * @tm_tag_wq: wait queue for free task management slots
500 * @tm_slots_in_use: bit map of task management request slots in use
53b3d9c3 501 * @pwr_done: completion for power mode change
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VH
502 * @tm_condition: condition variable for task management
503 * @ufshcd_state: UFSHCD states
3441da7d 504 * @eh_flags: Error handling flags
2fbd009b 505 * @intr_mask: Interrupt Mask Bits
66ec6d59 506 * @ee_ctrl_mask: Exception event control mask
1d337ec2 507 * @is_powered: flag to check if HBA is powered
3a4bf06d
YG
508 * @is_init_prefetch: flag to check if data was pre-fetched in initialization
509 * @init_prefetch_data: data pre-fetched during initialization
e8e7f271 510 * @eh_work: Worker to handle UFS errors that require s/w attention
66ec6d59 511 * @eeh_work: Worker to handle exception events
e0eca63e 512 * @errors: HBA errors
e8e7f271
SRT
513 * @uic_error: UFS interconnect layer error status
514 * @saved_err: sticky error mask
515 * @saved_uic_err: sticky UIC error mask
5a0b0cb9 516 * @dev_cmd: ufs device management command information
cad2e03d 517 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
66ec6d59 518 * @auto_bkops_enabled: to track whether bkops is enabled in device
aa497613 519 * @vreg_info: UFS device voltage regulator information
c6e79dac 520 * @clk_list_head: UFS host controller clocks list node head
7eb584db
DR
521 * @pwr_info: holds current power mode
522 * @max_pwr_info: keeps the device max valid pwm
a4b0e8a4 523 * @desc_size: descriptor sizes reported by device
afdfff59
YG
524 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
525 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
526 * device is known or not.
38135535 527 * @scsi_block_reqs_cnt: reference counting for scsi block requests
e0eca63e
VH
528 */
529struct ufs_hba {
530 void __iomem *mmio_base;
531
532 /* Virtual memory reference */
533 struct utp_transfer_cmd_desc *ucdl_base_addr;
534 struct utp_transfer_req_desc *utrdl_base_addr;
535 struct utp_task_req_desc *utmrdl_base_addr;
536
537 /* DMA memory reference */
538 dma_addr_t ucdl_dma_addr;
539 dma_addr_t utrdl_dma_addr;
540 dma_addr_t utmrdl_dma_addr;
541
542 struct Scsi_Host *host;
543 struct device *dev;
2a8fa600
SJ
544 /*
545 * This field is to keep a reference to "scsi_device" corresponding to
546 * "UFS device" W-LU.
547 */
548 struct scsi_device *sdev_ufs_device;
e0eca63e 549
57d104c1
SJ
550 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
551 enum uic_link_state uic_link_state;
552 /* Desired UFS power management level during runtime PM */
553 enum ufs_pm_level rpm_lvl;
554 /* Desired UFS power management level during system PM */
555 enum ufs_pm_level spm_lvl;
09690d5a 556 struct device_attribute rpm_lvl_attr;
557 struct device_attribute spm_lvl_attr;
57d104c1
SJ
558 int pm_op_in_progress;
559
ad448378
AH
560 /* Auto-Hibernate Idle Timer register value */
561 u32 ahit;
562
e0eca63e 563 struct ufshcd_lrb *lrb;
5a0b0cb9 564 unsigned long lrb_in_use;
e0eca63e
VH
565
566 unsigned long outstanding_tasks;
567 unsigned long outstanding_reqs;
568
569 u32 capabilities;
570 int nutrs;
571 int nutmrs;
572 u32 ufs_version;
176eb927 573 const struct ufs_hba_variant_ops *vops;
5c0c28a8 574 void *priv;
e0eca63e 575 unsigned int irq;
57d104c1 576 bool is_irq_enabled;
9e1e8a75 577 enum ufs_ref_clk_freq dev_ref_clk_freq;
e0eca63e 578
b852190e 579 /* Interrupt aggregation support is broken */
cc81641a 580 #define UFSHCD_QUIRK_BROKEN_INTR_AGGR 0x1
b852190e 581
cad2e03d
YG
582 /*
583 * delay before each dme command is required as the unipro
584 * layer has shown instabilities
585 */
cc81641a 586 #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 0x2
b852190e 587
7ca38cf3
YG
588 /*
589 * If UFS host controller is having issue in processing LCC (Line
590 * Control Command) coming from device then enable this quirk.
591 * When this quirk is enabled, host controller driver should disable
592 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
593 * attribute of device to 0).
594 */
cc81641a 595 #define UFSHCD_QUIRK_BROKEN_LCC 0x4
cad2e03d 596
c3a2f9ee
YG
597 /*
598 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
599 * inbound Link supports unterminated line in HS mode. Setting this
600 * attribute to 1 fixes moving to HS gear.
601 */
cc81641a 602 #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 0x8
c3a2f9ee 603
874237f7
YG
604 /*
605 * This quirk needs to be enabled if the host contoller only allows
606 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
607 * SLOW AUTO).
608 */
cc81641a 609 #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 0x10
874237f7 610
9949e702
YG
611 /*
612 * This quirk needs to be enabled if the host contoller doesn't
613 * advertise the correct version in UFS_VER register. If this quirk
614 * is enabled, standard UFS host driver will call the vendor specific
615 * ops (get_ufs_hci_version) to get the correct version.
616 */
cc81641a 617 #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION 0x20
9949e702 618
75b1cc4a
KK
619 /*
620 * This quirk needs to be enabled if the host contoller regards
621 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
622 */
cc81641a 623 #define UFSHCD_QUIRK_PRDT_BYTE_GRAN 0x80
75b1cc4a 624
1399c5b0
AA
625 /*
626 * Clear handling for transfer/task request list is just opposite.
627 */
628 #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR 0x100
629
5ac6abc9
AA
630 /*
631 * This quirk needs to be enabled if host controller doesn't allow
632 * that the interrupt aggregation timer and counter are reset by s/w.
633 */
634 #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR 0x200
635
4404c5de
AA
636 /*
637 * This quirks needs to be enabled if host controller cannot be
638 * enabled via HCE register.
639 */
640 #define UFSHCI_QUIRK_BROKEN_HCE 0x400
cad2e03d 641 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
6ccf44fe 642
c58ab7aa
YG
643 /* Device deviations from standard UFS device spec. */
644 unsigned int dev_quirks;
645
e2933132
SRT
646 wait_queue_head_t tm_wq;
647 wait_queue_head_t tm_tag_wq;
e0eca63e 648 unsigned long tm_condition;
e2933132 649 unsigned long tm_slots_in_use;
e0eca63e 650
57d104c1
SJ
651 struct uic_command *active_uic_cmd;
652 struct mutex uic_cmd_mutex;
653 struct completion *uic_async_done;
53b3d9c3 654
e0eca63e 655 u32 ufshcd_state;
3441da7d 656 u32 eh_flags;
2fbd009b 657 u32 intr_mask;
66ec6d59 658 u16 ee_ctrl_mask;
1d337ec2 659 bool is_powered;
3a4bf06d
YG
660 bool is_init_prefetch;
661 struct ufs_init_prefetch init_prefetch_data;
e0eca63e
VH
662
663 /* Work Queues */
e8e7f271 664 struct work_struct eh_work;
66ec6d59 665 struct work_struct eeh_work;
e0eca63e
VH
666
667 /* HBA Errors */
668 u32 errors;
e8e7f271
SRT
669 u32 uic_error;
670 u32 saved_err;
671 u32 saved_uic_err;
ff8e20c6 672 struct ufs_stats ufs_stats;
5a0b0cb9
SRT
673
674 /* Device management request data */
675 struct ufs_dev_cmd dev_cmd;
cad2e03d 676 ktime_t last_dme_cmd_tstamp;
66ec6d59 677
57d104c1
SJ
678 /* Keeps information of the UFS device connected to this host */
679 struct ufs_dev_info dev_info;
66ec6d59 680 bool auto_bkops_enabled;
aa497613 681 struct ufs_vreg_info vreg_info;
c6e79dac 682 struct list_head clk_list_head;
57d104c1
SJ
683
684 bool wlun_dev_clr_ua;
7eb584db 685
7fabb77b
GB
686 /* Number of requests aborts */
687 int req_abort_count;
688
54b879b7
YG
689 /* Number of lanes available (1 or 2) for Rx/Tx */
690 u32 lanes_per_direction;
7eb584db
DR
691 struct ufs_pa_layer_attr pwr_info;
692 struct ufs_pwr_mode_info max_pwr_info;
1ab27c9c
ST
693
694 struct ufs_clk_gating clk_gating;
695 /* Control to enable/disable host capabilities */
696 u32 caps;
697 /* Allow dynamic clk gating */
698#define UFSHCD_CAP_CLK_GATING (1 << 0)
699 /* Allow hiberb8 with clk gating */
700#define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1)
856b3483
ST
701 /* Allow dynamic clk scaling */
702#define UFSHCD_CAP_CLK_SCALING (1 << 2)
374a246e
SJ
703 /* Allow auto bkops to enabled during runtime suspend */
704#define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3)
b852190e
YG
705 /*
706 * This capability allows host controller driver to use the UFS HCI's
707 * interrupt aggregation capability.
708 * CAUTION: Enabling this might reduce overall UFS throughput.
709 */
710#define UFSHCD_CAP_INTR_AGGR (1 << 4)
4e768e76 711 /*
712 * This capability allows the device auto-bkops to be always enabled
713 * except during suspend (both runtime and suspend).
714 * Enabling this capability means that device will always be allowed
715 * to do background operation when it's active but it might degrade
716 * the performance of ongoing read/write operations.
717 */
718#define UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND (1 << 5)
49615ba1
SC
719 /*
720 * This capability allows host controller driver to automatically
721 * enable runtime power management by itself instead of waiting
722 * for userspace to control the power management.
723 */
724#define UFSHCD_CAP_RPM_AUTOSUSPEND (1 << 6)
856b3483
ST
725
726 struct devfreq *devfreq;
727 struct ufs_clk_scaling clk_scaling;
e785060e 728 bool is_sys_suspended;
afdfff59
YG
729
730 enum bkops_status urgent_bkops_lvl;
731 bool is_urgent_bkops_lvl_checked;
a3cd5ec5 732
733 struct rw_semaphore clk_scaling_lock;
a4b0e8a4 734 struct ufs_desc_size desc_size;
38135535 735 atomic_t scsi_block_reqs_cnt;
df032bf2
AA
736
737 struct device bsg_dev;
738 struct request_queue *bsg_queue;
e0eca63e
VH
739};
740
1ab27c9c
ST
741/* Returns true if clocks can be gated. Otherwise false */
742static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
743{
744 return hba->caps & UFSHCD_CAP_CLK_GATING;
745}
746static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
747{
748 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
749}
fcb0c4b0 750static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
856b3483
ST
751{
752 return hba->caps & UFSHCD_CAP_CLK_SCALING;
753}
374a246e
SJ
754static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
755{
756 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
757}
49615ba1
SC
758static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
759{
760 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
761}
374a246e 762
b852190e
YG
763static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
764{
4b9ffb5a
JP
765/* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
766#ifndef CONFIG_SCSI_UFS_DWC
b852190e
YG
767 if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
768 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
769 return true;
770 else
771 return false;
4b9ffb5a
JP
772#else
773return true;
774#endif
b852190e
YG
775}
776
ee5f1042
SC
777static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
778{
779 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT);
780}
781
b873a275
SJ
782#define ufshcd_writel(hba, val, reg) \
783 writel((val), (hba)->mmio_base + (reg))
784#define ufshcd_readl(hba, reg) \
785 readl((hba)->mmio_base + (reg))
786
e785060e
DR
787/**
788 * ufshcd_rmwl - read modify write into a register
789 * @hba - per adapter instance
790 * @mask - mask to apply on read value
791 * @val - actual value to write
792 * @reg - register address
793 */
794static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
795{
796 u32 tmp;
797
798 tmp = ufshcd_readl(hba, reg);
799 tmp &= ~mask;
800 tmp |= (val & mask);
801 ufshcd_writel(hba, tmp, reg);
802}
803
5c0c28a8 804int ufshcd_alloc_host(struct device *, struct ufs_hba **);
47555a5c 805void ufshcd_dealloc_host(struct ufs_hba *);
5c0c28a8 806int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
e0eca63e 807void ufshcd_remove(struct ufs_hba *);
596585a2
YG
808int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
809 u32 val, unsigned long interval_us,
810 unsigned long timeout_ms, bool can_sleep);
9e1e8a75 811void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
e0eca63e 812
68078d5c
DR
813static inline void check_upiu_size(void)
814{
815 BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
816 GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
817}
818
1ce5898a
YG
819/**
820 * ufshcd_set_variant - set variant specific data to the hba
821 * @hba - per adapter instance
822 * @variant - pointer to variant specific data
823 */
824static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
825{
826 BUG_ON(!hba);
827 hba->priv = variant;
828}
829
830/**
831 * ufshcd_get_variant - get variant specific data from the hba
832 * @hba - per adapter instance
833 */
834static inline void *ufshcd_get_variant(struct ufs_hba *hba)
835{
836 BUG_ON(!hba);
837 return hba->priv;
838}
4e768e76 839static inline bool ufshcd_keep_autobkops_enabled_except_suspend(
840 struct ufs_hba *hba)
841{
842 return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND;
843}
1ce5898a 844
66ec6d59
SRT
845extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
846extern int ufshcd_runtime_resume(struct ufs_hba *hba);
847extern int ufshcd_runtime_idle(struct ufs_hba *hba);
57d104c1
SJ
848extern int ufshcd_system_suspend(struct ufs_hba *hba);
849extern int ufshcd_system_resume(struct ufs_hba *hba);
850extern int ufshcd_shutdown(struct ufs_hba *hba);
12b4fdb4
SJ
851extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
852 u8 attr_set, u32 mib_val, u8 peer);
853extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
854 u32 *mib_val, u8 peer);
0d846e70
AA
855extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
856 struct ufs_pa_layer_attr *desired_pwr_mode);
12b4fdb4
SJ
857
858/* UIC command interfaces for DME primitives */
859#define DME_LOCAL 0
860#define DME_PEER 1
861#define ATTR_SET_NOR 0 /* NORMAL */
862#define ATTR_SET_ST 1 /* STATIC */
863
864static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
865 u32 mib_val)
866{
867 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
868 mib_val, DME_LOCAL);
869}
870
871static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
872 u32 mib_val)
873{
874 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
875 mib_val, DME_LOCAL);
876}
877
878static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
879 u32 mib_val)
880{
881 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
882 mib_val, DME_PEER);
883}
884
885static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
886 u32 mib_val)
887{
888 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
889 mib_val, DME_PEER);
890}
891
892static inline int ufshcd_dme_get(struct ufs_hba *hba,
893 u32 attr_sel, u32 *mib_val)
894{
895 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
896}
897
898static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
899 u32 attr_sel, u32 *mib_val)
900{
901 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
902}
903
f37aabcf
YG
904static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
905{
906 return (pwr_info->pwr_rx == FAST_MODE ||
907 pwr_info->pwr_rx == FASTAUTO_MODE) &&
908 (pwr_info->pwr_tx == FAST_MODE ||
909 pwr_info->pwr_tx == FASTAUTO_MODE);
910}
911
dc3c8d3a 912/* Expose Query-Request API */
2238d31c
SN
913int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
914 enum query_opcode opcode,
915 enum desc_idn idn, u8 index,
916 u8 selector,
917 u8 *desc_buf, int *buf_len);
45bced87
SN
918int ufshcd_read_desc_param(struct ufs_hba *hba,
919 enum desc_idn desc_id,
920 int desc_index,
921 u8 param_offset,
922 u8 *param_read_buf,
923 u8 param_size);
ec92b59c
SN
924int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
925 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val);
dc3c8d3a
YG
926int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
927 enum flag_idn idn, bool *flag_res);
4b828fe1 928
71d848b8
CG
929void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
930
4b828fe1
TW
931#define SD_ASCII_STD true
932#define SD_RAW false
933int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
934 u8 **buf, bool ascii);
2238d31c 935
1ab27c9c
ST
936int ufshcd_hold(struct ufs_hba *hba, bool async);
937void ufshcd_release(struct ufs_hba *hba);
a4b0e8a4
PM
938
939int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
940 int *desc_length);
941
37113106 942u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
0263bcd0 943
e77044c5
AA
944int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
945
5e0a86ee
AA
946int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
947 struct utp_upiu_req *req_upiu,
948 struct utp_upiu_req *rsp_upiu,
949 int msgcode,
950 u8 *desc_buff, int *buff_len,
951 enum query_opcode desc_op);
952
0263bcd0
YG
953/* Wrapper functions for safely calling variant operations */
954static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
955{
956 if (hba->vops)
957 return hba->vops->name;
958 return "";
959}
960
961static inline int ufshcd_vops_init(struct ufs_hba *hba)
962{
963 if (hba->vops && hba->vops->init)
964 return hba->vops->init(hba);
965
966 return 0;
967}
968
969static inline void ufshcd_vops_exit(struct ufs_hba *hba)
970{
971 if (hba->vops && hba->vops->exit)
972 return hba->vops->exit(hba);
973}
974
975static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba)
976{
977 if (hba->vops && hba->vops->get_ufs_hci_version)
978 return hba->vops->get_ufs_hci_version(hba);
979
980 return ufshcd_readl(hba, REG_UFS_VERSION);
981}
982
f06fcc71
YG
983static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba,
984 bool up, enum ufs_notify_change_status status)
0263bcd0
YG
985{
986 if (hba->vops && hba->vops->clk_scale_notify)
f06fcc71
YG
987 return hba->vops->clk_scale_notify(hba, up, status);
988 return 0;
0263bcd0
YG
989}
990
1e879e8f
SJ
991static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on,
992 enum ufs_notify_change_status status)
0263bcd0
YG
993{
994 if (hba->vops && hba->vops->setup_clocks)
1e879e8f 995 return hba->vops->setup_clocks(hba, on, status);
0263bcd0
YG
996 return 0;
997}
998
999static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status)
1000{
1001 if (hba->vops && hba->vops->setup_regulators)
1002 return hba->vops->setup_regulators(hba, status);
1003
1004 return 0;
1005}
1006
1007static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba,
1008 bool status)
1009{
1010 if (hba->vops && hba->vops->hce_enable_notify)
1011 return hba->vops->hce_enable_notify(hba, status);
1012
1013 return 0;
1014}
1015static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba,
1016 bool status)
1017{
1018 if (hba->vops && hba->vops->link_startup_notify)
1019 return hba->vops->link_startup_notify(hba, status);
1020
1021 return 0;
1022}
1023
1024static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba,
1025 bool status,
1026 struct ufs_pa_layer_attr *dev_max_params,
1027 struct ufs_pa_layer_attr *dev_req_params)
1028{
1029 if (hba->vops && hba->vops->pwr_change_notify)
1030 return hba->vops->pwr_change_notify(hba, status,
1031 dev_max_params, dev_req_params);
1032
1033 return -ENOTSUPP;
1034}
1035
0e675efa
KK
1036static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag,
1037 bool is_scsi_cmd)
1038{
1039 if (hba->vops && hba->vops->setup_xfer_req)
1040 return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd);
1041}
1042
d2877be4
KK
1043static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba,
1044 int tag, u8 tm_function)
1045{
1046 if (hba->vops && hba->vops->setup_task_mgmt)
1047 return hba->vops->setup_task_mgmt(hba, tag, tm_function);
1048}
1049
ee32c909
KK
1050static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
1051 enum uic_cmd_dme cmd,
1052 enum ufs_notify_change_status status)
1053{
1054 if (hba->vops && hba->vops->hibern8_notify)
1055 return hba->vops->hibern8_notify(hba, cmd, status);
1056}
1057
56d4a186
SJ
1058static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba)
1059{
1060 if (hba->vops && hba->vops->apply_dev_quirks)
1061 return hba->vops->apply_dev_quirks(hba);
1062 return 0;
1063}
1064
0263bcd0
YG
1065static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op)
1066{
1067 if (hba->vops && hba->vops->suspend)
1068 return hba->vops->suspend(hba, op);
1069
1070 return 0;
1071}
1072
1073static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op)
1074{
1075 if (hba->vops && hba->vops->resume)
1076 return hba->vops->resume(hba, op);
1077
1078 return 0;
1079}
1080
6e3fd44d
YG
1081static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
1082{
1083 if (hba->vops && hba->vops->dbg_register_dump)
1084 hba->vops->dbg_register_dump(hba);
1085}
1086
d8d9f793
BA
1087static inline void ufshcd_vops_device_reset(struct ufs_hba *hba)
1088{
1089 if (hba->vops && hba->vops->device_reset)
1090 hba->vops->device_reset(hba);
1091}
1092
cbb6813e
SN
1093extern struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1094
d829fc8a
SN
1095/*
1096 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1097 * @scsi_lun: scsi LUN id
1098 *
1099 * Returns UPIU LUN id
1100 */
1101static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1102{
1103 if (scsi_is_wlun(scsi_lun))
1104 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1105 | UFS_UPIU_WLUN_ID;
1106 else
1107 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1108}
1109
ba80917d
TW
1110int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1111 const char *prefix);
1112
e0eca63e 1113#endif /* End of Header */