scsi: ufs: Fix a duplicate dev quirk number
[linux-block.git] / drivers / scsi / ufs / ufshcd.h
CommitLineData
67351119 1/* SPDX-License-Identifier: GPL-2.0-or-later */
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2/*
3 * Universal Flash Storage Host controller driver
e0eca63e 4 * Copyright (C) 2011-2013 Samsung India Software Operations
dc3c8d3a 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
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10 */
11
12#ifndef _UFSHCD_H
13#define _UFSHCD_H
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
a3cd5ec5 23#include <linux/rwsem.h>
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24#include <linux/workqueue.h>
25#include <linux/errno.h>
26#include <linux/types.h>
27#include <linux/wait.h>
28#include <linux/bitops.h>
29#include <linux/pm_runtime.h>
30#include <linux/clk.h>
6ccf44fe 31#include <linux/completion.h>
aa497613 32#include <linux/regulator/consumer.h>
5a244e0e 33#include <linux/bitfield.h>
2c75f9a5 34#include <linux/devfreq.h>
70297a8a 35#include <linux/keyslot-manager.h>
f37aabcf 36#include "unipro.h"
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37
38#include <asm/irq.h>
39#include <asm/byteorder.h>
40#include <scsi/scsi.h>
41#include <scsi/scsi_cmnd.h>
42#include <scsi/scsi_host.h>
43#include <scsi/scsi_tcq.h>
44#include <scsi/scsi_dbg.h>
45#include <scsi/scsi_eh.h>
46
47#include "ufs.h"
c28c00ba 48#include "ufs_quirks.h"
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49#include "ufshci.h"
50
51#define UFSHCD "ufshcd"
52#define UFSHCD_DRIVER_VERSION "0.2"
53
5c0c28a8
SRT
54struct ufs_hba;
55
5a0b0cb9
SRT
56enum dev_cmd_type {
57 DEV_CMD_TYPE_NOP = 0x0,
68078d5c 58 DEV_CMD_TYPE_QUERY = 0x1,
5a0b0cb9
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59};
60
e965e5e0
SC
61enum ufs_event_type {
62 /* uic specific errors */
63 UFS_EVT_PA_ERR = 0,
64 UFS_EVT_DL_ERR,
65 UFS_EVT_NL_ERR,
66 UFS_EVT_TL_ERR,
67 UFS_EVT_DME_ERR,
68
69 /* fatal errors */
70 UFS_EVT_AUTO_HIBERN8_ERR,
71 UFS_EVT_FATAL_ERR,
72 UFS_EVT_LINK_STARTUP_FAIL,
73 UFS_EVT_RESUME_ERR,
74 UFS_EVT_SUSPEND_ERR,
75
76 /* abnormal events */
77 UFS_EVT_DEV_RESET,
78 UFS_EVT_HOST_RESET,
79 UFS_EVT_ABORT,
80
81 UFS_EVT_CNT,
82};
83
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84/**
85 * struct uic_command - UIC command structure
86 * @command: UIC command
87 * @argument1: UIC command argument 1
88 * @argument2: UIC command argument 2
89 * @argument3: UIC command argument 3
0f52fcb9 90 * @cmd_active: Indicate if UIC command is outstanding
6ccf44fe 91 * @done: UIC command completion
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92 */
93struct uic_command {
94 u32 command;
95 u32 argument1;
96 u32 argument2;
97 u32 argument3;
0f52fcb9 98 int cmd_active;
6ccf44fe 99 struct completion done;
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100};
101
57d104c1
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102/* Used to differentiate the power management options */
103enum ufs_pm_op {
104 UFS_RUNTIME_PM,
105 UFS_SYSTEM_PM,
106 UFS_SHUTDOWN_PM,
107};
108
109#define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
110#define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
111#define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
112
113/* Host <-> Device UniPro Link state */
114enum uic_link_state {
115 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
116 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
117 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
4db7a236 118 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
57d104c1
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119};
120
121#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
122#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
123 UIC_LINK_ACTIVE_STATE)
124#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
125 UIC_LINK_HIBERN8_STATE)
4db7a236
CG
126#define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
127 UIC_LINK_BROKEN_STATE)
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128#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
129#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
130 UIC_LINK_ACTIVE_STATE)
131#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
132 UIC_LINK_HIBERN8_STATE)
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133#define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
134 UIC_LINK_BROKEN_STATE)
57d104c1 135
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SC
136#define ufshcd_set_ufs_dev_active(h) \
137 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
138#define ufshcd_set_ufs_dev_sleep(h) \
139 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
140#define ufshcd_set_ufs_dev_poweroff(h) \
141 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
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142#define ufshcd_set_ufs_dev_deepsleep(h) \
143 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
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SC
144#define ufshcd_is_ufs_dev_active(h) \
145 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
146#define ufshcd_is_ufs_dev_sleep(h) \
147 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
148#define ufshcd_is_ufs_dev_poweroff(h) \
149 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
fe1d4c2e
AH
150#define ufshcd_is_ufs_dev_deepsleep(h) \
151 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
1764fa2a 152
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153/*
154 * UFS Power management levels.
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AH
155 * Each level is in increasing order of power savings, except DeepSleep
156 * which is lower than PowerDown with power on but not PowerDown with
157 * power off.
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158 */
159enum ufs_pm_level {
160 UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
161 UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
162 UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
163 UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
164 UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
165 UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
fe1d4c2e 166 UFS_PM_LVL_6, /* UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE */
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167 UFS_PM_LVL_MAX
168};
169
170struct ufs_pm_lvl_states {
171 enum ufs_dev_pwr_mode dev_state;
172 enum uic_link_state link_state;
173};
174
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175/**
176 * struct ufshcd_lrb - local reference block
177 * @utr_descriptor_ptr: UTRD address of the command
5a0b0cb9 178 * @ucd_req_ptr: UCD address of the command
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179 * @ucd_rsp_ptr: Response UPIU address for this command
180 * @ucd_prdt_ptr: PRDT address of the command
ff8e20c6
DR
181 * @utrd_dma_addr: UTRD dma address for debug
182 * @ucd_prdt_dma_addr: PRDT dma address for debug
183 * @ucd_rsp_dma_addr: UPIU response dma address for debug
184 * @ucd_req_dma_addr: UPIU request dma address for debug
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185 * @cmd: pointer to SCSI command
186 * @sense_buffer: pointer to sense buffer address of the SCSI command
187 * @sense_bufflen: Length of the sense buffer
188 * @scsi_status: SCSI status of the command
189 * @command_type: SCSI, UFS, Query.
190 * @task_tag: Task tag of the command
191 * @lun: LUN of the command
5a0b0cb9 192 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
ff8e20c6 193 * @issue_time_stamp: time stamp for debug purposes
09017188 194 * @compl_time_stamp: time stamp for statistics
df043c74
ST
195 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
196 * @data_unit_num: the data unit number for the first block for inline crypto
e0b299e3 197 * @req_abort_skip: skip request abort task flag
7a7e66c6 198 * @in_use: indicates that this lrb is still in use
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199 */
200struct ufshcd_lrb {
201 struct utp_transfer_req_desc *utr_descriptor_ptr;
5a0b0cb9 202 struct utp_upiu_req *ucd_req_ptr;
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203 struct utp_upiu_rsp *ucd_rsp_ptr;
204 struct ufshcd_sg_entry *ucd_prdt_ptr;
205
ff8e20c6
DR
206 dma_addr_t utrd_dma_addr;
207 dma_addr_t ucd_req_dma_addr;
208 dma_addr_t ucd_rsp_dma_addr;
209 dma_addr_t ucd_prdt_dma_addr;
210
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211 struct scsi_cmnd *cmd;
212 u8 *sense_buffer;
213 unsigned int sense_bufflen;
214 int scsi_status;
215
216 int command_type;
217 int task_tag;
0ce147d4 218 u8 lun; /* UPIU LUN id field is only 8-bit wide */
5a0b0cb9 219 bool intr_cmd;
ff8e20c6 220 ktime_t issue_time_stamp;
09017188 221 ktime_t compl_time_stamp;
df043c74
ST
222#ifdef CONFIG_SCSI_UFS_CRYPTO
223 int crypto_key_slot;
224 u64 data_unit_num;
225#endif
e0b299e3
GB
226
227 bool req_abort_skip;
7a7e66c6 228 bool in_use;
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229};
230
68078d5c 231/**
a230c2f6 232 * struct ufs_query - holds relevant data structures for query request
68078d5c
DR
233 * @request: request upiu and function
234 * @descriptor: buffer for sending/receiving descriptor
235 * @response: response upiu and response
236 */
237struct ufs_query {
238 struct ufs_query_req request;
239 u8 *descriptor;
240 struct ufs_query_res response;
241};
242
5a0b0cb9
SRT
243/**
244 * struct ufs_dev_cmd - all assosiated fields with device management commands
245 * @type: device management command type - Query, NOP OUT
246 * @lock: lock to allow one command at a time
247 * @complete: internal commands completion
5a0b0cb9
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248 */
249struct ufs_dev_cmd {
250 enum dev_cmd_type type;
251 struct mutex lock;
252 struct completion *complete;
68078d5c 253 struct ufs_query query;
5a0b0cb9 254};
e0eca63e 255
c6e79dac
SRT
256/**
257 * struct ufs_clk_info - UFS clock related info
258 * @list: list headed by hba->clk_list_head
259 * @clk: clock node
260 * @name: clock name
261 * @max_freq: maximum frequency supported by the clock
4cff6d99 262 * @min_freq: min frequency that can be used for clock scaling
856b3483 263 * @curr_freq: indicates the current frequency that it is set to
81309c24
CG
264 * @keep_link_active: indicates that the clk should not be disabled if
265 link is active
c6e79dac
SRT
266 * @enabled: variable to check against multiple enable/disable
267 */
268struct ufs_clk_info {
269 struct list_head list;
270 struct clk *clk;
271 const char *name;
272 u32 max_freq;
4cff6d99 273 u32 min_freq;
856b3483 274 u32 curr_freq;
81309c24 275 bool keep_link_active;
c6e79dac
SRT
276 bool enabled;
277};
278
f06fcc71
YG
279enum ufs_notify_change_status {
280 PRE_CHANGE,
281 POST_CHANGE,
282};
7eb584db
DR
283
284struct ufs_pa_layer_attr {
285 u32 gear_rx;
286 u32 gear_tx;
287 u32 lane_rx;
288 u32 lane_tx;
289 u32 pwr_rx;
290 u32 pwr_tx;
291 u32 hs_rate;
292};
293
294struct ufs_pwr_mode_info {
295 bool is_valid;
296 struct ufs_pa_layer_attr info;
297};
298
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SRT
299/**
300 * struct ufs_hba_variant_ops - variant specific callbacks
301 * @name: variant name
302 * @init: called when the driver is initialized
303 * @exit: called to cleanup everything done in init
9949e702 304 * @get_ufs_hci_version: called to get UFS HCI version
856b3483 305 * @clk_scale_notify: notifies that clks are scaled up/down
5c0c28a8 306 * @setup_clocks: called before touching any of the controller registers
5c0c28a8
SRT
307 * @hce_enable_notify: called before and after HCE enable bit is set to allow
308 * variant specific Uni-Pro initialization.
309 * @link_startup_notify: called before and after Link startup is carried out
310 * to allow variant specific Uni-Pro initialization.
7eb584db
DR
311 * @pwr_change_notify: called before and after a power mode change
312 * is carried out to allow vendor spesific capabilities
313 * to be set.
0e675efa
KK
314 * @setup_xfer_req: called before any transfer request is issued
315 * to set some things
d2877be4
KK
316 * @setup_task_mgmt: called before any task management request is issued
317 * to set some things
ee32c909 318 * @hibern8_notify: called around hibern8 enter/exit
56d4a186 319 * @apply_dev_quirks: called to apply device specific quirks
57d104c1
SJ
320 * @suspend: called during host controller PM callback
321 * @resume: called during host controller PM callback
6e3fd44d 322 * @dbg_register_dump: used to dump controller debug information
4b9ffb5a 323 * @phy_initialization: used to initialize phys
d8d9f793 324 * @device_reset: called to issue a reset pulse on the UFS device
1bc726e2 325 * @program_key: program or evict an inline encryption key
172614a9 326 * @event_notify: called to notify important events
5c0c28a8
SRT
327 */
328struct ufs_hba_variant_ops {
329 const char *name;
330 int (*init)(struct ufs_hba *);
331 void (*exit)(struct ufs_hba *);
9949e702 332 u32 (*get_ufs_hci_version)(struct ufs_hba *);
f06fcc71
YG
333 int (*clk_scale_notify)(struct ufs_hba *, bool,
334 enum ufs_notify_change_status);
1e879e8f
SJ
335 int (*setup_clocks)(struct ufs_hba *, bool,
336 enum ufs_notify_change_status);
f06fcc71
YG
337 int (*hce_enable_notify)(struct ufs_hba *,
338 enum ufs_notify_change_status);
339 int (*link_startup_notify)(struct ufs_hba *,
340 enum ufs_notify_change_status);
7eb584db 341 int (*pwr_change_notify)(struct ufs_hba *,
f06fcc71
YG
342 enum ufs_notify_change_status status,
343 struct ufs_pa_layer_attr *,
7eb584db 344 struct ufs_pa_layer_attr *);
0e675efa 345 void (*setup_xfer_req)(struct ufs_hba *, int, bool);
d2877be4 346 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
ee32c909 347 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
56d4a186 348 enum ufs_notify_change_status);
09750066 349 int (*apply_dev_quirks)(struct ufs_hba *hba);
c28c00ba 350 void (*fixup_dev_quirks)(struct ufs_hba *hba);
57d104c1
SJ
351 int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
352 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
6e3fd44d 353 void (*dbg_register_dump)(struct ufs_hba *hba);
4b9ffb5a 354 int (*phy_initialization)(struct ufs_hba *);
151f1b66 355 int (*device_reset)(struct ufs_hba *hba);
2c75f9a5
AD
356 void (*config_scaling_param)(struct ufs_hba *hba,
357 struct devfreq_dev_profile *profile,
358 void *data);
1bc726e2
EB
359 int (*program_key)(struct ufs_hba *hba,
360 const union ufs_crypto_cfg_entry *cfg, int slot);
172614a9
SC
361 void (*event_notify)(struct ufs_hba *hba,
362 enum ufs_event_type evt, void *data);
5c0c28a8
SRT
363};
364
1ab27c9c
ST
365/* clock gating state */
366enum clk_gating_state {
367 CLKS_OFF,
368 CLKS_ON,
369 REQ_CLKS_OFF,
370 REQ_CLKS_ON,
371};
372
373/**
374 * struct ufs_clk_gating - UFS clock gating related info
375 * @gate_work: worker to turn off clocks after some delay as specified in
376 * delay_ms
377 * @ungate_work: worker to turn on clocks that will be used in case of
378 * interrupt context
379 * @state: the current clocks state
380 * @delay_ms: gating delay in ms
381 * @is_suspended: clk gating is suspended when set to 1 which can be used
382 * during suspend/resume
383 * @delay_attr: sysfs attribute to control delay_attr
b427411a
ST
384 * @enable_attr: sysfs attribute to enable/disable clock gating
385 * @is_enabled: Indicates the current status of clock gating
4543d9d7 386 * @is_initialized: Indicates whether clock gating is initialized or not
1ab27c9c
ST
387 * @active_reqs: number of requests that are pending and should be waited for
388 * completion before gating clocks.
389 */
390struct ufs_clk_gating {
391 struct delayed_work gate_work;
392 struct work_struct ungate_work;
393 enum clk_gating_state state;
394 unsigned long delay_ms;
395 bool is_suspended;
396 struct device_attribute delay_attr;
b427411a
ST
397 struct device_attribute enable_attr;
398 bool is_enabled;
4543d9d7 399 bool is_initialized;
1ab27c9c 400 int active_reqs;
10e5e375 401 struct workqueue_struct *clk_gating_workq;
1ab27c9c
ST
402};
403
a3cd5ec5 404struct ufs_saved_pwr_info {
405 struct ufs_pa_layer_attr info;
406 bool is_valid;
407};
408
401f1e44 409/**
410 * struct ufs_clk_scaling - UFS clock scaling related data
411 * @active_reqs: number of requests that are pending. If this is zero when
412 * devfreq ->target() function is called then schedule "suspend_work" to
413 * suspend devfreq.
414 * @tot_busy_t: Total busy time in current polling window
415 * @window_start_t: Start time (in jiffies) of the current polling window
416 * @busy_start_t: Start time of current busy period
417 * @enable_attr: sysfs attribute to enable/disable clock scaling
418 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
419 * one keeps track of previous power mode.
420 * @workq: workqueue to schedule devfreq suspend/resume work
421 * @suspend_work: worker to suspend devfreq
422 * @resume_work: worker to resume devfreq
29b87e92 423 * @min_gear: lowest HS gear to scale down to
0e9d4ca4
CG
424 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
425 clkscale_enable sysfs node
426 * @is_allowed: tracks if scaling is currently allowed or not, used to block
427 clock scaling which is not invoked from devfreq governor
4543d9d7 428 * @is_initialized: Indicates whether clock scaling is initialized or not
401f1e44 429 * @is_busy_started: tracks if busy period has started or not
430 * @is_suspended: tracks if devfreq is suspended or not
431 */
856b3483 432struct ufs_clk_scaling {
401f1e44 433 int active_reqs;
434 unsigned long tot_busy_t;
b1bf66d1 435 ktime_t window_start_t;
401f1e44 436 ktime_t busy_start_t;
fcb0c4b0 437 struct device_attribute enable_attr;
a3cd5ec5 438 struct ufs_saved_pwr_info saved_pwr_info;
401f1e44 439 struct workqueue_struct *workq;
440 struct work_struct suspend_work;
441 struct work_struct resume_work;
29b87e92 442 u32 min_gear;
0e9d4ca4 443 bool is_enabled;
401f1e44 444 bool is_allowed;
4543d9d7 445 bool is_initialized;
401f1e44 446 bool is_busy_started;
447 bool is_suspended;
856b3483
ST
448};
449
e965e5e0 450#define UFS_EVENT_HIST_LENGTH 8
ff8e20c6 451/**
e965e5e0 452 * struct ufs_event_hist - keeps history of errors
ff8e20c6
DR
453 * @pos: index to indicate cyclic buffer position
454 * @reg: cyclic buffer for registers value
455 * @tstamp: cyclic buffer for time stamp
b6cacaf2 456 * @cnt: error counter
ff8e20c6 457 */
e965e5e0 458struct ufs_event_hist {
ff8e20c6 459 int pos;
e965e5e0
SC
460 u32 val[UFS_EVENT_HIST_LENGTH];
461 ktime_t tstamp[UFS_EVENT_HIST_LENGTH];
b6cacaf2 462 unsigned long long cnt;
ff8e20c6
DR
463};
464
465/**
466 * struct ufs_stats - keeps usage/err statistics
3f8af604
CG
467 * @last_intr_status: record the last interrupt status.
468 * @last_intr_ts: record the last interrupt timestamp.
ff8e20c6
DR
469 * @hibern8_exit_cnt: Counter to keep track of number of exits,
470 * reset this after link-startup.
471 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
472 * Clear after the first successful command completion.
ff8e20c6
DR
473 */
474struct ufs_stats {
3f8af604
CG
475 u32 last_intr_status;
476 ktime_t last_intr_ts;
477
ff8e20c6
DR
478 u32 hibern8_exit_cnt;
479 ktime_t last_hibern8_exit_tstamp;
e965e5e0 480 struct ufs_event_hist event[UFS_EVT_CNT];
ff8e20c6
DR
481};
482
c3f7d1fc
CH
483enum ufshcd_quirks {
484 /* Interrupt aggregation support is broken */
485 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
486
487 /*
488 * delay before each dme command is required as the unipro
489 * layer has shown instabilities
490 */
491 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
492
493 /*
494 * If UFS host controller is having issue in processing LCC (Line
495 * Control Command) coming from device then enable this quirk.
496 * When this quirk is enabled, host controller driver should disable
497 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
498 * attribute of device to 0).
499 */
500 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
501
502 /*
503 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
504 * inbound Link supports unterminated line in HS mode. Setting this
505 * attribute to 1 fixes moving to HS gear.
506 */
507 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
508
509 /*
510 * This quirk needs to be enabled if the host controller only allows
511 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
512 * SLOW AUTO).
513 */
514 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
515
516 /*
517 * This quirk needs to be enabled if the host controller doesn't
518 * advertise the correct version in UFS_VER register. If this quirk
519 * is enabled, standard UFS host driver will call the vendor specific
520 * ops (get_ufs_hci_version) to get the correct version.
521 */
522 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
87183841
AA
523
524 /*
525 * Clear handling for transfer/task request list is just opposite.
526 */
527 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
b638b5eb
AA
528
529 /*
530 * This quirk needs to be enabled if host controller doesn't allow
531 * that the interrupt aggregation timer and counter are reset by s/w.
532 */
533 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
39bf2d83
AA
534
535 /*
536 * This quirks needs to be enabled if host controller cannot be
537 * enabled via HCE register.
538 */
539 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
26f968d7
AA
540
541 /*
542 * This quirk needs to be enabled if the host controller regards
543 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
544 */
545 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
d779a6e9
KK
546
547 /*
548 * This quirk needs to be enabled if the host controller reports
549 * OCS FATAL ERROR with device error through sense data
550 */
551 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
5df6f2de 552
8da76f71
AH
553 /*
554 * This quirk needs to be enabled if the host controller has
555 * auto-hibernate capability but it doesn't work.
556 */
557 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
02f74150 558
5df6f2de
KK
559 /*
560 * This quirk needs to disable manual flush for write booster
561 */
02f74150
MP
562 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
563
b1d0d2eb
KK
564 /*
565 * This quirk needs to disable unipro timeout values
566 * before power mode change
567 */
568 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
569
2b2bfc8a
KK
570 /*
571 * This quirk allows only sg entries aligned with page size.
572 */
9599a1cf 573 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14,
c3f7d1fc
CH
574};
575
c2014682
SC
576enum ufshcd_caps {
577 /* Allow dynamic clk gating */
578 UFSHCD_CAP_CLK_GATING = 1 << 0,
579
580 /* Allow hiberb8 with clk gating */
581 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
582
583 /* Allow dynamic clk scaling */
584 UFSHCD_CAP_CLK_SCALING = 1 << 2,
585
586 /* Allow auto bkops to enabled during runtime suspend */
587 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
588
589 /*
590 * This capability allows host controller driver to use the UFS HCI's
591 * interrupt aggregation capability.
592 * CAUTION: Enabling this might reduce overall UFS throughput.
593 */
594 UFSHCD_CAP_INTR_AGGR = 1 << 4,
595
596 /*
597 * This capability allows the device auto-bkops to be always enabled
598 * except during suspend (both runtime and suspend).
599 * Enabling this capability means that device will always be allowed
600 * to do background operation when it's active but it might degrade
601 * the performance of ongoing read/write operations.
602 */
603 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
604
605 /*
606 * This capability allows host controller driver to automatically
607 * enable runtime power management by itself instead of waiting
608 * for userspace to control the power management.
609 */
610 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
3d17b9b5
AD
611
612 /*
613 * This capability allows the host controller driver to turn-on
614 * WriteBooster, if the underlying device supports it and is
615 * provisioned to be used. This would increase the write performance.
616 */
617 UFSHCD_CAP_WB_EN = 1 << 7,
5e7341e1
ST
618
619 /*
620 * This capability allows the host controller driver to use the
621 * inline crypto engine, if it is present
622 */
623 UFSHCD_CAP_CRYPTO = 1 << 8,
dd7143e2
CG
624
625 /*
626 * This capability allows the controller regulators to be put into
627 * lpm mode aggressively during clock gating.
628 * This would increase power savings.
629 */
630 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
fe1d4c2e
AH
631
632 /*
633 * This capability allows the host controller driver to use DeepSleep,
634 * if it is supported by the UFS device. The host controller driver must
635 * support device hardware reset via the hba->device_reset() callback,
636 * in order to exit DeepSleep state.
637 */
638 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
c2014682
SC
639};
640
90b8491c
SC
641struct ufs_hba_variant_params {
642 struct devfreq_dev_profile devfreq_profile;
643 struct devfreq_simple_ondemand_data ondemand_data;
644 u16 hba_enable_delay_us;
d14734ae 645 u32 wb_flush_threshold;
90b8491c
SC
646};
647
e0eca63e
VH
648/**
649 * struct ufs_hba - per adapter private structure
650 * @mmio_base: UFSHCI base register address
651 * @ucdl_base_addr: UFS Command Descriptor base address
652 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
653 * @utmrdl_base_addr: UTP Task Management Descriptor base address
654 * @ucdl_dma_addr: UFS Command Descriptor DMA address
655 * @utrdl_dma_addr: UTRDL DMA address
656 * @utmrdl_dma_addr: UTMRDL DMA address
657 * @host: Scsi_Host instance of the driver
658 * @dev: device handle
659 * @lrb: local reference block
7252a360 660 * @cmd_queue: Used to allocate command tags from hba->host->tag_set.
e0eca63e
VH
661 * @outstanding_tasks: Bits representing outstanding task requests
662 * @outstanding_reqs: Bits representing outstanding transfer requests
663 * @capabilities: UFS Controller Capabilities
664 * @nutrs: Transfer Request Queue depth supported by controller
665 * @nutmrs: Task Management Queue depth supported by controller
666 * @ufs_version: UFS Version to which controller complies
5c0c28a8
SRT
667 * @vops: pointer to variant specific operations
668 * @priv: pointer to variant specific private data
e0eca63e
VH
669 * @irq: Irq number of the controller
670 * @active_uic_cmd: handle of active UIC command
6ccf44fe 671 * @uic_cmd_mutex: mutex for uic command
69a6c269
BVA
672 * @tmf_tag_set: TMF tag set.
673 * @tmf_queue: Used to allocate TMF tags.
53b3d9c3 674 * @pwr_done: completion for power mode change
e0eca63e 675 * @ufshcd_state: UFSHCD states
3441da7d 676 * @eh_flags: Error handling flags
2fbd009b 677 * @intr_mask: Interrupt Mask Bits
66ec6d59 678 * @ee_ctrl_mask: Exception event control mask
1d337ec2 679 * @is_powered: flag to check if HBA is powered
9cd20d3f
CG
680 * @shutting_down: flag to check if shutdown has been invoked
681 * @host_sem: semaphore used to serialize concurrent contexts
4db7a236 682 * @eh_wq: Workqueue that eh_work works on
e8e7f271 683 * @eh_work: Worker to handle UFS errors that require s/w attention
66ec6d59 684 * @eeh_work: Worker to handle exception events
e0eca63e 685 * @errors: HBA errors
e8e7f271
SRT
686 * @uic_error: UFS interconnect layer error status
687 * @saved_err: sticky error mask
688 * @saved_uic_err: sticky UIC error mask
4db7a236 689 * @force_reset: flag to force eh_work perform a full reset
2355b66e 690 * @force_pmc: flag to force a power mode change
2df74b69 691 * @silence_err_logs: flag to silence error logs
5a0b0cb9 692 * @dev_cmd: ufs device management command information
cad2e03d 693 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
66ec6d59 694 * @auto_bkops_enabled: to track whether bkops is enabled in device
aa497613 695 * @vreg_info: UFS device voltage regulator information
c6e79dac 696 * @clk_list_head: UFS host controller clocks list node head
7eb584db
DR
697 * @pwr_info: holds current power mode
698 * @max_pwr_info: keeps the device max valid pwm
a4b0e8a4 699 * @desc_size: descriptor sizes reported by device
afdfff59
YG
700 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
701 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
702 * device is known or not.
38135535 703 * @scsi_block_reqs_cnt: reference counting for scsi block requests
70297a8a
ST
704 * @crypto_capabilities: Content of crypto capabilities register (0x100)
705 * @crypto_cap_array: Array of crypto capabilities
706 * @crypto_cfg_register: Start of the crypto cfg array
707 * @ksm: the keyslot manager tied to this hba
e0eca63e
VH
708 */
709struct ufs_hba {
710 void __iomem *mmio_base;
711
712 /* Virtual memory reference */
713 struct utp_transfer_cmd_desc *ucdl_base_addr;
714 struct utp_transfer_req_desc *utrdl_base_addr;
715 struct utp_task_req_desc *utmrdl_base_addr;
716
717 /* DMA memory reference */
718 dma_addr_t ucdl_dma_addr;
719 dma_addr_t utrdl_dma_addr;
720 dma_addr_t utmrdl_dma_addr;
721
722 struct Scsi_Host *host;
723 struct device *dev;
7252a360 724 struct request_queue *cmd_queue;
2a8fa600
SJ
725 /*
726 * This field is to keep a reference to "scsi_device" corresponding to
727 * "UFS device" W-LU.
728 */
729 struct scsi_device *sdev_ufs_device;
4f3e900b 730 struct scsi_device *sdev_rpmb;
e0eca63e 731
57d104c1
SJ
732 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
733 enum uic_link_state uic_link_state;
734 /* Desired UFS power management level during runtime PM */
735 enum ufs_pm_level rpm_lvl;
736 /* Desired UFS power management level during system PM */
737 enum ufs_pm_level spm_lvl;
09690d5a 738 struct device_attribute rpm_lvl_attr;
739 struct device_attribute spm_lvl_attr;
57d104c1
SJ
740 int pm_op_in_progress;
741
ad448378
AH
742 /* Auto-Hibernate Idle Timer register value */
743 u32 ahit;
744
e0eca63e
VH
745 struct ufshcd_lrb *lrb;
746
747 unsigned long outstanding_tasks;
748 unsigned long outstanding_reqs;
749
750 u32 capabilities;
751 int nutrs;
752 int nutmrs;
753 u32 ufs_version;
176eb927 754 const struct ufs_hba_variant_ops *vops;
90b8491c 755 struct ufs_hba_variant_params *vps;
5c0c28a8 756 void *priv;
e0eca63e 757 unsigned int irq;
57d104c1 758 bool is_irq_enabled;
9e1e8a75 759 enum ufs_ref_clk_freq dev_ref_clk_freq;
e0eca63e 760
cad2e03d 761 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
6ccf44fe 762
c58ab7aa
YG
763 /* Device deviations from standard UFS device spec. */
764 unsigned int dev_quirks;
765
69a6c269
BVA
766 struct blk_mq_tag_set tmf_tag_set;
767 struct request_queue *tmf_queue;
e0eca63e 768
57d104c1
SJ
769 struct uic_command *active_uic_cmd;
770 struct mutex uic_cmd_mutex;
771 struct completion *uic_async_done;
53b3d9c3 772
e0eca63e 773 u32 ufshcd_state;
3441da7d 774 u32 eh_flags;
2fbd009b 775 u32 intr_mask;
66ec6d59 776 u16 ee_ctrl_mask;
1d337ec2 777 bool is_powered;
9cd20d3f
CG
778 bool shutting_down;
779 struct semaphore host_sem;
e0eca63e
VH
780
781 /* Work Queues */
4db7a236 782 struct workqueue_struct *eh_wq;
e8e7f271 783 struct work_struct eh_work;
66ec6d59 784 struct work_struct eeh_work;
e0eca63e
VH
785
786 /* HBA Errors */
787 u32 errors;
e8e7f271
SRT
788 u32 uic_error;
789 u32 saved_err;
790 u32 saved_uic_err;
ff8e20c6 791 struct ufs_stats ufs_stats;
4db7a236 792 bool force_reset;
2355b66e 793 bool force_pmc;
2df74b69 794 bool silence_err_logs;
5a0b0cb9
SRT
795
796 /* Device management request data */
797 struct ufs_dev_cmd dev_cmd;
cad2e03d 798 ktime_t last_dme_cmd_tstamp;
66ec6d59 799
57d104c1
SJ
800 /* Keeps information of the UFS device connected to this host */
801 struct ufs_dev_info dev_info;
66ec6d59 802 bool auto_bkops_enabled;
aa497613 803 struct ufs_vreg_info vreg_info;
c6e79dac 804 struct list_head clk_list_head;
57d104c1
SJ
805
806 bool wlun_dev_clr_ua;
7eb584db 807
7fabb77b
GB
808 /* Number of requests aborts */
809 int req_abort_count;
810
54b879b7
YG
811 /* Number of lanes available (1 or 2) for Rx/Tx */
812 u32 lanes_per_direction;
7eb584db
DR
813 struct ufs_pa_layer_attr pwr_info;
814 struct ufs_pwr_mode_info max_pwr_info;
1ab27c9c
ST
815
816 struct ufs_clk_gating clk_gating;
817 /* Control to enable/disable host capabilities */
818 u32 caps;
856b3483
ST
819
820 struct devfreq *devfreq;
821 struct ufs_clk_scaling clk_scaling;
e785060e 822 bool is_sys_suspended;
afdfff59
YG
823
824 enum bkops_status urgent_bkops_lvl;
825 bool is_urgent_bkops_lvl_checked;
a3cd5ec5 826
827 struct rw_semaphore clk_scaling_lock;
7a0bf85b 828 unsigned char desc_size[QUERY_DESC_IDN_MAX];
38135535 829 atomic_t scsi_block_reqs_cnt;
df032bf2
AA
830
831 struct device bsg_dev;
832 struct request_queue *bsg_queue;
51dd905b 833 struct delayed_work rpm_dev_flush_recheck_work;
70297a8a
ST
834
835#ifdef CONFIG_SCSI_UFS_CRYPTO
836 union ufs_crypto_capabilities crypto_capabilities;
837 union ufs_crypto_cap_entry *crypto_cap_array;
838 u32 crypto_cfg_register;
839 struct blk_keyslot_manager ksm;
840#endif
b6cacaf2
AH
841#ifdef CONFIG_DEBUG_FS
842 struct dentry *debugfs_root;
843#endif
e0eca63e
VH
844};
845
1ab27c9c
ST
846/* Returns true if clocks can be gated. Otherwise false */
847static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
848{
849 return hba->caps & UFSHCD_CAP_CLK_GATING;
850}
851static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
852{
853 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
854}
fcb0c4b0 855static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
856b3483
ST
856{
857 return hba->caps & UFSHCD_CAP_CLK_SCALING;
858}
374a246e
SJ
859static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
860{
861 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
862}
49615ba1
SC
863static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
864{
865 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
866}
374a246e 867
b852190e
YG
868static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
869{
4b9ffb5a
JP
870/* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
871#ifndef CONFIG_SCSI_UFS_DWC
b852190e
YG
872 if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
873 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
874 return true;
875 else
876 return false;
4b9ffb5a
JP
877#else
878return true;
879#endif
b852190e
YG
880}
881
dd7143e2
CG
882static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
883{
884 return !!(ufshcd_is_link_hibern8(hba) &&
885 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
886}
887
ee5f1042
SC
888static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
889{
8da76f71
AH
890 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
891 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
ee5f1042
SC
892}
893
5a244e0e
SC
894static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
895{
896 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit) ? true : false;
897}
898
3d17b9b5
AD
899static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
900{
901 return hba->caps & UFSHCD_CAP_WB_EN;
902}
903
9cd20d3f
CG
904static inline bool ufshcd_is_user_access_allowed(struct ufs_hba *hba)
905{
906 return !hba->shutting_down;
907}
908
b873a275
SJ
909#define ufshcd_writel(hba, val, reg) \
910 writel((val), (hba)->mmio_base + (reg))
911#define ufshcd_readl(hba, reg) \
912 readl((hba)->mmio_base + (reg))
913
e785060e
DR
914/**
915 * ufshcd_rmwl - read modify write into a register
916 * @hba - per adapter instance
917 * @mask - mask to apply on read value
918 * @val - actual value to write
919 * @reg - register address
920 */
921static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
922{
923 u32 tmp;
924
925 tmp = ufshcd_readl(hba, reg);
926 tmp &= ~mask;
927 tmp |= (val & mask);
928 ufshcd_writel(hba, tmp, reg);
929}
930
5c0c28a8 931int ufshcd_alloc_host(struct device *, struct ufs_hba **);
47555a5c 932void ufshcd_dealloc_host(struct ufs_hba *);
9d19bf7a 933int ufshcd_hba_enable(struct ufs_hba *hba);
5c0c28a8 934int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
087c5efa 935int ufshcd_link_recovery(struct ufs_hba *hba);
9d19bf7a 936int ufshcd_make_hba_operational(struct ufs_hba *hba);
e0eca63e 937void ufshcd_remove(struct ufs_hba *);
9d19bf7a 938int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
5c955c10 939void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
596585a2
YG
940int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
941 u32 val, unsigned long interval_us,
5cac1095 942 unsigned long timeout_ms);
9e1e8a75 943void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
e965e5e0 944void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
e0eca63e 945
68078d5c
DR
946static inline void check_upiu_size(void)
947{
948 BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
949 GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
950}
951
1ce5898a
YG
952/**
953 * ufshcd_set_variant - set variant specific data to the hba
954 * @hba - per adapter instance
955 * @variant - pointer to variant specific data
956 */
957static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
958{
959 BUG_ON(!hba);
960 hba->priv = variant;
961}
962
963/**
964 * ufshcd_get_variant - get variant specific data from the hba
965 * @hba - per adapter instance
966 */
967static inline void *ufshcd_get_variant(struct ufs_hba *hba)
968{
969 BUG_ON(!hba);
970 return hba->priv;
971}
4e768e76 972static inline bool ufshcd_keep_autobkops_enabled_except_suspend(
973 struct ufs_hba *hba)
974{
975 return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND;
976}
1ce5898a 977
e31011ab 978static inline u8 ufshcd_wb_get_query_index(struct ufs_hba *hba)
6f8d5a6a 979{
4cd48995 980 if (hba->dev_info.wb_buffer_type == WB_BUF_MODE_LU_DEDICATED)
6f8d5a6a
SC
981 return hba->dev_info.wb_dedicated_lu;
982 return 0;
983}
984
66ec6d59
SRT
985extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
986extern int ufshcd_runtime_resume(struct ufs_hba *hba);
987extern int ufshcd_runtime_idle(struct ufs_hba *hba);
57d104c1
SJ
988extern int ufshcd_system_suspend(struct ufs_hba *hba);
989extern int ufshcd_system_resume(struct ufs_hba *hba);
990extern int ufshcd_shutdown(struct ufs_hba *hba);
fc85a74e
SC
991extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
992 int agreed_gear,
993 int adapt_val);
12b4fdb4
SJ
994extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
995 u8 attr_set, u32 mib_val, u8 peer);
996extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
997 u32 *mib_val, u8 peer);
0d846e70
AA
998extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
999 struct ufs_pa_layer_attr *desired_pwr_mode);
12b4fdb4
SJ
1000
1001/* UIC command interfaces for DME primitives */
1002#define DME_LOCAL 0
1003#define DME_PEER 1
1004#define ATTR_SET_NOR 0 /* NORMAL */
1005#define ATTR_SET_ST 1 /* STATIC */
1006
1007static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1008 u32 mib_val)
1009{
1010 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1011 mib_val, DME_LOCAL);
1012}
1013
1014static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1015 u32 mib_val)
1016{
1017 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1018 mib_val, DME_LOCAL);
1019}
1020
1021static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1022 u32 mib_val)
1023{
1024 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1025 mib_val, DME_PEER);
1026}
1027
1028static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1029 u32 mib_val)
1030{
1031 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1032 mib_val, DME_PEER);
1033}
1034
1035static inline int ufshcd_dme_get(struct ufs_hba *hba,
1036 u32 attr_sel, u32 *mib_val)
1037{
1038 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1039}
1040
1041static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1042 u32 attr_sel, u32 *mib_val)
1043{
1044 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1045}
1046
f37aabcf
YG
1047static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1048{
1049 return (pwr_info->pwr_rx == FAST_MODE ||
1050 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1051 (pwr_info->pwr_tx == FAST_MODE ||
1052 pwr_info->pwr_tx == FASTAUTO_MODE);
1053}
1054
984eaac1
SC
1055static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1056{
1057 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1058}
1059
dc3c8d3a 1060/* Expose Query-Request API */
2238d31c
SN
1061int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
1062 enum query_opcode opcode,
1063 enum desc_idn idn, u8 index,
1064 u8 selector,
1065 u8 *desc_buf, int *buf_len);
45bced87
SN
1066int ufshcd_read_desc_param(struct ufs_hba *hba,
1067 enum desc_idn desc_id,
1068 int desc_index,
1069 u8 param_offset,
1070 u8 *param_read_buf,
1071 u8 param_size);
ec92b59c
SN
1072int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
1073 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val);
dc3c8d3a 1074int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 1075 enum flag_idn idn, u8 index, bool *flag_res);
4b828fe1 1076
71d848b8 1077void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
ba7af5ec 1078void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
8db269a5 1079void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups);
4b828fe1
TW
1080#define SD_ASCII_STD true
1081#define SD_RAW false
1082int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1083 u8 **buf, bool ascii);
2238d31c 1084
1ab27c9c
ST
1085int ufshcd_hold(struct ufs_hba *hba, bool async);
1086void ufshcd_release(struct ufs_hba *hba);
a4b0e8a4 1087
7a0bf85b
BH
1088void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1089 int *desc_length);
a4b0e8a4 1090
37113106 1091u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
0263bcd0 1092
e77044c5
AA
1093int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1094
5e0a86ee
AA
1095int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
1096 struct utp_upiu_req *req_upiu,
1097 struct utp_upiu_req *rsp_upiu,
1098 int msgcode,
1099 u8 *desc_buff, int *buff_len,
1100 enum query_opcode desc_op);
1101
8e834ca5
BH
1102int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable);
1103
0263bcd0
YG
1104/* Wrapper functions for safely calling variant operations */
1105static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
1106{
1107 if (hba->vops)
1108 return hba->vops->name;
1109 return "";
1110}
1111
1112static inline int ufshcd_vops_init(struct ufs_hba *hba)
1113{
1114 if (hba->vops && hba->vops->init)
1115 return hba->vops->init(hba);
1116
1117 return 0;
1118}
1119
1120static inline void ufshcd_vops_exit(struct ufs_hba *hba)
1121{
1122 if (hba->vops && hba->vops->exit)
1123 return hba->vops->exit(hba);
1124}
1125
1126static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba)
1127{
1128 if (hba->vops && hba->vops->get_ufs_hci_version)
1129 return hba->vops->get_ufs_hci_version(hba);
1130
1131 return ufshcd_readl(hba, REG_UFS_VERSION);
1132}
1133
f06fcc71
YG
1134static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba,
1135 bool up, enum ufs_notify_change_status status)
0263bcd0
YG
1136{
1137 if (hba->vops && hba->vops->clk_scale_notify)
f06fcc71
YG
1138 return hba->vops->clk_scale_notify(hba, up, status);
1139 return 0;
0263bcd0
YG
1140}
1141
172614a9
SC
1142static inline void ufshcd_vops_event_notify(struct ufs_hba *hba,
1143 enum ufs_event_type evt,
1144 void *data)
1145{
1146 if (hba->vops && hba->vops->event_notify)
1147 hba->vops->event_notify(hba, evt, data);
1148}
1149
1e879e8f
SJ
1150static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on,
1151 enum ufs_notify_change_status status)
0263bcd0
YG
1152{
1153 if (hba->vops && hba->vops->setup_clocks)
1e879e8f 1154 return hba->vops->setup_clocks(hba, on, status);
0263bcd0
YG
1155 return 0;
1156}
1157
0263bcd0
YG
1158static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba,
1159 bool status)
1160{
1161 if (hba->vops && hba->vops->hce_enable_notify)
1162 return hba->vops->hce_enable_notify(hba, status);
1163
1164 return 0;
1165}
1166static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba,
1167 bool status)
1168{
1169 if (hba->vops && hba->vops->link_startup_notify)
1170 return hba->vops->link_startup_notify(hba, status);
1171
1172 return 0;
1173}
1174
92bcebe4
SC
1175static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1176{
1177 if (hba->vops && hba->vops->phy_initialization)
1178 return hba->vops->phy_initialization(hba);
1179
1180 return 0;
1181}
1182
0263bcd0
YG
1183static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba,
1184 bool status,
1185 struct ufs_pa_layer_attr *dev_max_params,
1186 struct ufs_pa_layer_attr *dev_req_params)
1187{
1188 if (hba->vops && hba->vops->pwr_change_notify)
1189 return hba->vops->pwr_change_notify(hba, status,
1190 dev_max_params, dev_req_params);
1191
1192 return -ENOTSUPP;
1193}
1194
0e675efa
KK
1195static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag,
1196 bool is_scsi_cmd)
1197{
1198 if (hba->vops && hba->vops->setup_xfer_req)
1199 return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd);
1200}
1201
d2877be4
KK
1202static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba,
1203 int tag, u8 tm_function)
1204{
1205 if (hba->vops && hba->vops->setup_task_mgmt)
1206 return hba->vops->setup_task_mgmt(hba, tag, tm_function);
1207}
1208
ee32c909
KK
1209static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
1210 enum uic_cmd_dme cmd,
1211 enum ufs_notify_change_status status)
1212{
1213 if (hba->vops && hba->vops->hibern8_notify)
1214 return hba->vops->hibern8_notify(hba, cmd, status);
1215}
1216
09750066 1217static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba)
56d4a186
SJ
1218{
1219 if (hba->vops && hba->vops->apply_dev_quirks)
09750066 1220 return hba->vops->apply_dev_quirks(hba);
56d4a186
SJ
1221 return 0;
1222}
1223
c28c00ba
SC
1224static inline void ufshcd_vops_fixup_dev_quirks(struct ufs_hba *hba)
1225{
1226 if (hba->vops && hba->vops->fixup_dev_quirks)
1227 hba->vops->fixup_dev_quirks(hba);
1228}
1229
0263bcd0
YG
1230static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op)
1231{
1232 if (hba->vops && hba->vops->suspend)
1233 return hba->vops->suspend(hba, op);
1234
1235 return 0;
1236}
1237
1238static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op)
1239{
1240 if (hba->vops && hba->vops->resume)
1241 return hba->vops->resume(hba, op);
1242
1243 return 0;
1244}
1245
6e3fd44d
YG
1246static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
1247{
1248 if (hba->vops && hba->vops->dbg_register_dump)
1249 hba->vops->dbg_register_dump(hba);
1250}
1251
31a5d9ca 1252static inline int ufshcd_vops_device_reset(struct ufs_hba *hba)
d8d9f793 1253{
31a5d9ca
SC
1254 if (hba->vops && hba->vops->device_reset)
1255 return hba->vops->device_reset(hba);
1256
1257 return -EOPNOTSUPP;
d8d9f793
BA
1258}
1259
2c75f9a5
AD
1260static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba,
1261 struct devfreq_dev_profile
1262 *profile, void *data)
1263{
1264 if (hba->vops && hba->vops->config_scaling_param)
1265 hba->vops->config_scaling_param(hba, profile, data);
1266}
1267
cbb6813e
SN
1268extern struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1269
d829fc8a
SN
1270/*
1271 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1272 * @scsi_lun: scsi LUN id
1273 *
1274 * Returns UPIU LUN id
1275 */
1276static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1277{
1278 if (scsi_is_wlun(scsi_lun))
1279 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1280 | UFS_UPIU_WLUN_ID;
1281 else
1282 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1283}
1284
ba80917d
TW
1285int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1286 const char *prefix);
1287
e0eca63e 1288#endif /* End of Header */