scsi: ufs: introduce UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE quirk
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.h
CommitLineData
e0eca63e
VH
1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 * See the COPYING file in the top-level directory or visit
16 * <http://www.gnu.org/licenses/gpl-2.0.html>
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
24 * without warranty of any kind. You are solely responsible for
25 * determining the appropriateness of using and distributing
26 * the program and assume all risks associated with your exercise
27 * of rights with respect to the program, including but not limited
28 * to infringement of third party rights, the risks and costs of
29 * program errors, damage to or loss of data, programs or equipment,
30 * and unavailability or interruption of operations. Under no
31 * circumstances will the contributor of this Program be liable for
32 * any damages of any kind arising from your use or distribution of
33 * this program.
34 */
35
36#ifndef _UFSHCD_H
37#define _UFSHCD_H
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/init.h>
42#include <linux/interrupt.h>
43#include <linux/io.h>
44#include <linux/delay.h>
45#include <linux/slab.h>
46#include <linux/spinlock.h>
47#include <linux/workqueue.h>
48#include <linux/errno.h>
49#include <linux/types.h>
50#include <linux/wait.h>
51#include <linux/bitops.h>
52#include <linux/pm_runtime.h>
53#include <linux/clk.h>
6ccf44fe 54#include <linux/completion.h>
aa497613 55#include <linux/regulator/consumer.h>
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56
57#include <asm/irq.h>
58#include <asm/byteorder.h>
59#include <scsi/scsi.h>
60#include <scsi/scsi_cmnd.h>
61#include <scsi/scsi_host.h>
62#include <scsi/scsi_tcq.h>
63#include <scsi/scsi_dbg.h>
64#include <scsi/scsi_eh.h>
65
66#include "ufs.h"
67#include "ufshci.h"
68
69#define UFSHCD "ufshcd"
70#define UFSHCD_DRIVER_VERSION "0.2"
71
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72struct ufs_hba;
73
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SRT
74enum dev_cmd_type {
75 DEV_CMD_TYPE_NOP = 0x0,
68078d5c 76 DEV_CMD_TYPE_QUERY = 0x1,
5a0b0cb9
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77};
78
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79/**
80 * struct uic_command - UIC command structure
81 * @command: UIC command
82 * @argument1: UIC command argument 1
83 * @argument2: UIC command argument 2
84 * @argument3: UIC command argument 3
85 * @cmd_active: Indicate if UIC command is outstanding
86 * @result: UIC command result
6ccf44fe 87 * @done: UIC command completion
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88 */
89struct uic_command {
90 u32 command;
91 u32 argument1;
92 u32 argument2;
93 u32 argument3;
94 int cmd_active;
95 int result;
6ccf44fe 96 struct completion done;
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VH
97};
98
57d104c1
SJ
99/* Used to differentiate the power management options */
100enum ufs_pm_op {
101 UFS_RUNTIME_PM,
102 UFS_SYSTEM_PM,
103 UFS_SHUTDOWN_PM,
104};
105
106#define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
107#define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
108#define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
109
110/* Host <-> Device UniPro Link state */
111enum uic_link_state {
112 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
113 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
114 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
115};
116
117#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
118#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
119 UIC_LINK_ACTIVE_STATE)
120#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
121 UIC_LINK_HIBERN8_STATE)
122#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
123#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
124 UIC_LINK_ACTIVE_STATE)
125#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
126 UIC_LINK_HIBERN8_STATE)
127
128/*
129 * UFS Power management levels.
130 * Each level is in increasing order of power savings.
131 */
132enum ufs_pm_level {
133 UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
134 UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
135 UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
136 UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
137 UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
138 UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
139 UFS_PM_LVL_MAX
140};
141
142struct ufs_pm_lvl_states {
143 enum ufs_dev_pwr_mode dev_state;
144 enum uic_link_state link_state;
145};
146
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147/**
148 * struct ufshcd_lrb - local reference block
149 * @utr_descriptor_ptr: UTRD address of the command
5a0b0cb9 150 * @ucd_req_ptr: UCD address of the command
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151 * @ucd_rsp_ptr: Response UPIU address for this command
152 * @ucd_prdt_ptr: PRDT address of the command
153 * @cmd: pointer to SCSI command
154 * @sense_buffer: pointer to sense buffer address of the SCSI command
155 * @sense_bufflen: Length of the sense buffer
156 * @scsi_status: SCSI status of the command
157 * @command_type: SCSI, UFS, Query.
158 * @task_tag: Task tag of the command
159 * @lun: LUN of the command
5a0b0cb9 160 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
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161 */
162struct ufshcd_lrb {
163 struct utp_transfer_req_desc *utr_descriptor_ptr;
5a0b0cb9 164 struct utp_upiu_req *ucd_req_ptr;
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165 struct utp_upiu_rsp *ucd_rsp_ptr;
166 struct ufshcd_sg_entry *ucd_prdt_ptr;
167
168 struct scsi_cmnd *cmd;
169 u8 *sense_buffer;
170 unsigned int sense_bufflen;
171 int scsi_status;
172
173 int command_type;
174 int task_tag;
0ce147d4 175 u8 lun; /* UPIU LUN id field is only 8-bit wide */
5a0b0cb9 176 bool intr_cmd;
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177};
178
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DR
179/**
180 * struct ufs_query - holds relevent data structures for query request
181 * @request: request upiu and function
182 * @descriptor: buffer for sending/receiving descriptor
183 * @response: response upiu and response
184 */
185struct ufs_query {
186 struct ufs_query_req request;
187 u8 *descriptor;
188 struct ufs_query_res response;
189};
190
5a0b0cb9
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191/**
192 * struct ufs_dev_cmd - all assosiated fields with device management commands
193 * @type: device management command type - Query, NOP OUT
194 * @lock: lock to allow one command at a time
195 * @complete: internal commands completion
196 * @tag_wq: wait queue until free command slot is available
197 */
198struct ufs_dev_cmd {
199 enum dev_cmd_type type;
200 struct mutex lock;
201 struct completion *complete;
202 wait_queue_head_t tag_wq;
68078d5c 203 struct ufs_query query;
5a0b0cb9 204};
e0eca63e 205
c6e79dac
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206/**
207 * struct ufs_clk_info - UFS clock related info
208 * @list: list headed by hba->clk_list_head
209 * @clk: clock node
210 * @name: clock name
211 * @max_freq: maximum frequency supported by the clock
4cff6d99 212 * @min_freq: min frequency that can be used for clock scaling
856b3483 213 * @curr_freq: indicates the current frequency that it is set to
c6e79dac
SRT
214 * @enabled: variable to check against multiple enable/disable
215 */
216struct ufs_clk_info {
217 struct list_head list;
218 struct clk *clk;
219 const char *name;
220 u32 max_freq;
4cff6d99 221 u32 min_freq;
856b3483 222 u32 curr_freq;
c6e79dac
SRT
223 bool enabled;
224};
225
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SRT
226#define PRE_CHANGE 0
227#define POST_CHANGE 1
7eb584db
DR
228
229struct ufs_pa_layer_attr {
230 u32 gear_rx;
231 u32 gear_tx;
232 u32 lane_rx;
233 u32 lane_tx;
234 u32 pwr_rx;
235 u32 pwr_tx;
236 u32 hs_rate;
237};
238
239struct ufs_pwr_mode_info {
240 bool is_valid;
241 struct ufs_pa_layer_attr info;
242};
243
5c0c28a8
SRT
244/**
245 * struct ufs_hba_variant_ops - variant specific callbacks
246 * @name: variant name
247 * @init: called when the driver is initialized
248 * @exit: called to cleanup everything done in init
856b3483 249 * @clk_scale_notify: notifies that clks are scaled up/down
5c0c28a8
SRT
250 * @setup_clocks: called before touching any of the controller registers
251 * @setup_regulators: called before accessing the host controller
252 * @hce_enable_notify: called before and after HCE enable bit is set to allow
253 * variant specific Uni-Pro initialization.
254 * @link_startup_notify: called before and after Link startup is carried out
255 * to allow variant specific Uni-Pro initialization.
7eb584db
DR
256 * @pwr_change_notify: called before and after a power mode change
257 * is carried out to allow vendor spesific capabilities
258 * to be set.
57d104c1
SJ
259 * @suspend: called during host controller PM callback
260 * @resume: called during host controller PM callback
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261 */
262struct ufs_hba_variant_ops {
263 const char *name;
264 int (*init)(struct ufs_hba *);
265 void (*exit)(struct ufs_hba *);
856b3483 266 void (*clk_scale_notify)(struct ufs_hba *);
5c0c28a8
SRT
267 int (*setup_clocks)(struct ufs_hba *, bool);
268 int (*setup_regulators)(struct ufs_hba *, bool);
269 int (*hce_enable_notify)(struct ufs_hba *, bool);
270 int (*link_startup_notify)(struct ufs_hba *, bool);
7eb584db
DR
271 int (*pwr_change_notify)(struct ufs_hba *,
272 bool, struct ufs_pa_layer_attr *,
273 struct ufs_pa_layer_attr *);
57d104c1
SJ
274 int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
275 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
5c0c28a8
SRT
276};
277
1ab27c9c
ST
278/* clock gating state */
279enum clk_gating_state {
280 CLKS_OFF,
281 CLKS_ON,
282 REQ_CLKS_OFF,
283 REQ_CLKS_ON,
284};
285
286/**
287 * struct ufs_clk_gating - UFS clock gating related info
288 * @gate_work: worker to turn off clocks after some delay as specified in
289 * delay_ms
290 * @ungate_work: worker to turn on clocks that will be used in case of
291 * interrupt context
292 * @state: the current clocks state
293 * @delay_ms: gating delay in ms
294 * @is_suspended: clk gating is suspended when set to 1 which can be used
295 * during suspend/resume
296 * @delay_attr: sysfs attribute to control delay_attr
297 * @active_reqs: number of requests that are pending and should be waited for
298 * completion before gating clocks.
299 */
300struct ufs_clk_gating {
301 struct delayed_work gate_work;
302 struct work_struct ungate_work;
303 enum clk_gating_state state;
304 unsigned long delay_ms;
305 bool is_suspended;
306 struct device_attribute delay_attr;
307 int active_reqs;
308};
309
856b3483
ST
310struct ufs_clk_scaling {
311 ktime_t busy_start_t;
312 bool is_busy_started;
313 unsigned long tot_busy_t;
314 unsigned long window_start_t;
315};
316
3a4bf06d
YG
317/**
318 * struct ufs_init_prefetch - contains data that is pre-fetched once during
319 * initialization
320 * @icc_level: icc level which was read during initialization
321 */
322struct ufs_init_prefetch {
323 u32 icc_level;
324};
325
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VH
326/**
327 * struct ufs_hba - per adapter private structure
328 * @mmio_base: UFSHCI base register address
329 * @ucdl_base_addr: UFS Command Descriptor base address
330 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
331 * @utmrdl_base_addr: UTP Task Management Descriptor base address
332 * @ucdl_dma_addr: UFS Command Descriptor DMA address
333 * @utrdl_dma_addr: UTRDL DMA address
334 * @utmrdl_dma_addr: UTMRDL DMA address
335 * @host: Scsi_Host instance of the driver
336 * @dev: device handle
337 * @lrb: local reference block
5a0b0cb9 338 * @lrb_in_use: lrb in use
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339 * @outstanding_tasks: Bits representing outstanding task requests
340 * @outstanding_reqs: Bits representing outstanding transfer requests
341 * @capabilities: UFS Controller Capabilities
342 * @nutrs: Transfer Request Queue depth supported by controller
343 * @nutmrs: Task Management Queue depth supported by controller
344 * @ufs_version: UFS Version to which controller complies
5c0c28a8
SRT
345 * @vops: pointer to variant specific operations
346 * @priv: pointer to variant specific private data
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347 * @irq: Irq number of the controller
348 * @active_uic_cmd: handle of active UIC command
6ccf44fe 349 * @uic_cmd_mutex: mutex for uic command
e2933132
SRT
350 * @tm_wq: wait queue for task management
351 * @tm_tag_wq: wait queue for free task management slots
352 * @tm_slots_in_use: bit map of task management request slots in use
53b3d9c3 353 * @pwr_done: completion for power mode change
e0eca63e
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354 * @tm_condition: condition variable for task management
355 * @ufshcd_state: UFSHCD states
3441da7d 356 * @eh_flags: Error handling flags
2fbd009b 357 * @intr_mask: Interrupt Mask Bits
66ec6d59 358 * @ee_ctrl_mask: Exception event control mask
1d337ec2 359 * @is_powered: flag to check if HBA is powered
3a4bf06d
YG
360 * @is_init_prefetch: flag to check if data was pre-fetched in initialization
361 * @init_prefetch_data: data pre-fetched during initialization
e8e7f271 362 * @eh_work: Worker to handle UFS errors that require s/w attention
66ec6d59 363 * @eeh_work: Worker to handle exception events
e0eca63e 364 * @errors: HBA errors
e8e7f271
SRT
365 * @uic_error: UFS interconnect layer error status
366 * @saved_err: sticky error mask
367 * @saved_uic_err: sticky UIC error mask
5a0b0cb9 368 * @dev_cmd: ufs device management command information
cad2e03d 369 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
66ec6d59 370 * @auto_bkops_enabled: to track whether bkops is enabled in device
aa497613 371 * @vreg_info: UFS device voltage regulator information
c6e79dac 372 * @clk_list_head: UFS host controller clocks list node head
7eb584db
DR
373 * @pwr_info: holds current power mode
374 * @max_pwr_info: keeps the device max valid pwm
e0eca63e
VH
375 */
376struct ufs_hba {
377 void __iomem *mmio_base;
378
379 /* Virtual memory reference */
380 struct utp_transfer_cmd_desc *ucdl_base_addr;
381 struct utp_transfer_req_desc *utrdl_base_addr;
382 struct utp_task_req_desc *utmrdl_base_addr;
383
384 /* DMA memory reference */
385 dma_addr_t ucdl_dma_addr;
386 dma_addr_t utrdl_dma_addr;
387 dma_addr_t utmrdl_dma_addr;
388
389 struct Scsi_Host *host;
390 struct device *dev;
2a8fa600
SJ
391 /*
392 * This field is to keep a reference to "scsi_device" corresponding to
393 * "UFS device" W-LU.
394 */
395 struct scsi_device *sdev_ufs_device;
e0eca63e 396
57d104c1
SJ
397 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
398 enum uic_link_state uic_link_state;
399 /* Desired UFS power management level during runtime PM */
400 enum ufs_pm_level rpm_lvl;
401 /* Desired UFS power management level during system PM */
402 enum ufs_pm_level spm_lvl;
403 int pm_op_in_progress;
404
e0eca63e 405 struct ufshcd_lrb *lrb;
5a0b0cb9 406 unsigned long lrb_in_use;
e0eca63e
VH
407
408 unsigned long outstanding_tasks;
409 unsigned long outstanding_reqs;
410
411 u32 capabilities;
412 int nutrs;
413 int nutmrs;
414 u32 ufs_version;
5c0c28a8
SRT
415 struct ufs_hba_variant_ops *vops;
416 void *priv;
e0eca63e 417 unsigned int irq;
57d104c1 418 bool is_irq_enabled;
e0eca63e 419
b852190e
YG
420 /* Interrupt aggregation support is broken */
421 #define UFSHCD_QUIRK_BROKEN_INTR_AGGR UFS_BIT(0)
422
cad2e03d
YG
423 /*
424 * delay before each dme command is required as the unipro
425 * layer has shown instabilities
426 */
b852190e
YG
427 #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS UFS_BIT(1)
428
7ca38cf3
YG
429 /*
430 * If UFS host controller is having issue in processing LCC (Line
431 * Control Command) coming from device then enable this quirk.
432 * When this quirk is enabled, host controller driver should disable
433 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
434 * attribute of device to 0).
435 */
436 #define UFSHCD_QUIRK_BROKEN_LCC UFS_BIT(2)
cad2e03d 437
c3a2f9ee
YG
438 /*
439 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
440 * inbound Link supports unterminated line in HS mode. Setting this
441 * attribute to 1 fixes moving to HS gear.
442 */
443 #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP UFS_BIT(3)
444
874237f7
YG
445 /*
446 * This quirk needs to be enabled if the host contoller only allows
447 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
448 * SLOW AUTO).
449 */
450 #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE UFS_BIT(4)
451
cad2e03d 452 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
6ccf44fe 453
e2933132
SRT
454 wait_queue_head_t tm_wq;
455 wait_queue_head_t tm_tag_wq;
e0eca63e 456 unsigned long tm_condition;
e2933132 457 unsigned long tm_slots_in_use;
e0eca63e 458
57d104c1
SJ
459 struct uic_command *active_uic_cmd;
460 struct mutex uic_cmd_mutex;
461 struct completion *uic_async_done;
53b3d9c3 462
e0eca63e 463 u32 ufshcd_state;
3441da7d 464 u32 eh_flags;
2fbd009b 465 u32 intr_mask;
66ec6d59 466 u16 ee_ctrl_mask;
1d337ec2 467 bool is_powered;
3a4bf06d
YG
468 bool is_init_prefetch;
469 struct ufs_init_prefetch init_prefetch_data;
e0eca63e
VH
470
471 /* Work Queues */
e8e7f271 472 struct work_struct eh_work;
66ec6d59 473 struct work_struct eeh_work;
e0eca63e
VH
474
475 /* HBA Errors */
476 u32 errors;
e8e7f271
SRT
477 u32 uic_error;
478 u32 saved_err;
479 u32 saved_uic_err;
5a0b0cb9
SRT
480
481 /* Device management request data */
482 struct ufs_dev_cmd dev_cmd;
cad2e03d 483 ktime_t last_dme_cmd_tstamp;
66ec6d59 484
57d104c1
SJ
485 /* Keeps information of the UFS device connected to this host */
486 struct ufs_dev_info dev_info;
66ec6d59 487 bool auto_bkops_enabled;
aa497613 488 struct ufs_vreg_info vreg_info;
c6e79dac 489 struct list_head clk_list_head;
57d104c1
SJ
490
491 bool wlun_dev_clr_ua;
7eb584db
DR
492
493 struct ufs_pa_layer_attr pwr_info;
494 struct ufs_pwr_mode_info max_pwr_info;
1ab27c9c
ST
495
496 struct ufs_clk_gating clk_gating;
497 /* Control to enable/disable host capabilities */
498 u32 caps;
499 /* Allow dynamic clk gating */
500#define UFSHCD_CAP_CLK_GATING (1 << 0)
501 /* Allow hiberb8 with clk gating */
502#define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1)
856b3483
ST
503 /* Allow dynamic clk scaling */
504#define UFSHCD_CAP_CLK_SCALING (1 << 2)
374a246e
SJ
505 /* Allow auto bkops to enabled during runtime suspend */
506#define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3)
b852190e
YG
507 /*
508 * This capability allows host controller driver to use the UFS HCI's
509 * interrupt aggregation capability.
510 * CAUTION: Enabling this might reduce overall UFS throughput.
511 */
512#define UFSHCD_CAP_INTR_AGGR (1 << 4)
856b3483
ST
513
514 struct devfreq *devfreq;
515 struct ufs_clk_scaling clk_scaling;
e785060e 516 bool is_sys_suspended;
e0eca63e
VH
517};
518
1ab27c9c
ST
519/* Returns true if clocks can be gated. Otherwise false */
520static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
521{
522 return hba->caps & UFSHCD_CAP_CLK_GATING;
523}
524static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
525{
526 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
527}
856b3483
ST
528static inline int ufshcd_is_clkscaling_enabled(struct ufs_hba *hba)
529{
530 return hba->caps & UFSHCD_CAP_CLK_SCALING;
531}
374a246e
SJ
532static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
533{
534 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
535}
536
b852190e
YG
537static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
538{
539 if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
540 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
541 return true;
542 else
543 return false;
544}
545
b873a275
SJ
546#define ufshcd_writel(hba, val, reg) \
547 writel((val), (hba)->mmio_base + (reg))
548#define ufshcd_readl(hba, reg) \
549 readl((hba)->mmio_base + (reg))
550
e785060e
DR
551/**
552 * ufshcd_rmwl - read modify write into a register
553 * @hba - per adapter instance
554 * @mask - mask to apply on read value
555 * @val - actual value to write
556 * @reg - register address
557 */
558static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
559{
560 u32 tmp;
561
562 tmp = ufshcd_readl(hba, reg);
563 tmp &= ~mask;
564 tmp |= (val & mask);
565 ufshcd_writel(hba, tmp, reg);
566}
567
5c0c28a8
SRT
568int ufshcd_alloc_host(struct device *, struct ufs_hba **);
569int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
e0eca63e
VH
570void ufshcd_remove(struct ufs_hba *);
571
572/**
573 * ufshcd_hba_stop - Send controller to reset state
574 * @hba: per adapter instance
575 */
576static inline void ufshcd_hba_stop(struct ufs_hba *hba)
577{
b873a275 578 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
e0eca63e
VH
579}
580
68078d5c
DR
581static inline void check_upiu_size(void)
582{
583 BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
584 GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
585}
586
66ec6d59
SRT
587extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
588extern int ufshcd_runtime_resume(struct ufs_hba *hba);
589extern int ufshcd_runtime_idle(struct ufs_hba *hba);
57d104c1
SJ
590extern int ufshcd_system_suspend(struct ufs_hba *hba);
591extern int ufshcd_system_resume(struct ufs_hba *hba);
592extern int ufshcd_shutdown(struct ufs_hba *hba);
12b4fdb4
SJ
593extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
594 u8 attr_set, u32 mib_val, u8 peer);
595extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
596 u32 *mib_val, u8 peer);
597
598/* UIC command interfaces for DME primitives */
599#define DME_LOCAL 0
600#define DME_PEER 1
601#define ATTR_SET_NOR 0 /* NORMAL */
602#define ATTR_SET_ST 1 /* STATIC */
603
604static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
605 u32 mib_val)
606{
607 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
608 mib_val, DME_LOCAL);
609}
610
611static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
612 u32 mib_val)
613{
614 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
615 mib_val, DME_LOCAL);
616}
617
618static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
619 u32 mib_val)
620{
621 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
622 mib_val, DME_PEER);
623}
624
625static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
626 u32 mib_val)
627{
628 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
629 mib_val, DME_PEER);
630}
631
632static inline int ufshcd_dme_get(struct ufs_hba *hba,
633 u32 attr_sel, u32 *mib_val)
634{
635 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
636}
637
638static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
639 u32 attr_sel, u32 *mib_val)
640{
641 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
642}
643
1ab27c9c
ST
644int ufshcd_hold(struct ufs_hba *hba, bool async);
645void ufshcd_release(struct ufs_hba *hba);
e0eca63e 646#endif /* End of Header */