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e0eca63e VH |
1 | /* |
2 | * Universal Flash Storage Host controller driver | |
3 | * | |
4 | * This code is based on drivers/scsi/ufs/ufshcd.h | |
5 | * Copyright (C) 2011-2013 Samsung India Software Operations | |
dc3c8d3a | 6 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
e0eca63e VH |
7 | * |
8 | * Authors: | |
9 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
10 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version 2 | |
15 | * of the License, or (at your option) any later version. | |
16 | * See the COPYING file in the top-level directory or visit | |
17 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * This program is provided "AS IS" and "WITH ALL FAULTS" and | |
25 | * without warranty of any kind. You are solely responsible for | |
26 | * determining the appropriateness of using and distributing | |
27 | * the program and assume all risks associated with your exercise | |
28 | * of rights with respect to the program, including but not limited | |
29 | * to infringement of third party rights, the risks and costs of | |
30 | * program errors, damage to or loss of data, programs or equipment, | |
31 | * and unavailability or interruption of operations. Under no | |
32 | * circumstances will the contributor of this Program be liable for | |
33 | * any damages of any kind arising from your use or distribution of | |
34 | * this program. | |
35 | */ | |
36 | ||
37 | #ifndef _UFSHCD_H | |
38 | #define _UFSHCD_H | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/io.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/slab.h> | |
47 | #include <linux/spinlock.h> | |
a3cd5ec5 | 48 | #include <linux/rwsem.h> |
e0eca63e VH |
49 | #include <linux/workqueue.h> |
50 | #include <linux/errno.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/wait.h> | |
53 | #include <linux/bitops.h> | |
54 | #include <linux/pm_runtime.h> | |
55 | #include <linux/clk.h> | |
6ccf44fe | 56 | #include <linux/completion.h> |
aa497613 | 57 | #include <linux/regulator/consumer.h> |
f37aabcf | 58 | #include "unipro.h" |
e0eca63e VH |
59 | |
60 | #include <asm/irq.h> | |
61 | #include <asm/byteorder.h> | |
62 | #include <scsi/scsi.h> | |
63 | #include <scsi/scsi_cmnd.h> | |
64 | #include <scsi/scsi_host.h> | |
65 | #include <scsi/scsi_tcq.h> | |
66 | #include <scsi/scsi_dbg.h> | |
67 | #include <scsi/scsi_eh.h> | |
68 | ||
69 | #include "ufs.h" | |
70 | #include "ufshci.h" | |
71 | ||
72 | #define UFSHCD "ufshcd" | |
73 | #define UFSHCD_DRIVER_VERSION "0.2" | |
74 | ||
5c0c28a8 SRT |
75 | struct ufs_hba; |
76 | ||
5a0b0cb9 SRT |
77 | enum dev_cmd_type { |
78 | DEV_CMD_TYPE_NOP = 0x0, | |
68078d5c | 79 | DEV_CMD_TYPE_QUERY = 0x1, |
5a0b0cb9 SRT |
80 | }; |
81 | ||
e0eca63e VH |
82 | /** |
83 | * struct uic_command - UIC command structure | |
84 | * @command: UIC command | |
85 | * @argument1: UIC command argument 1 | |
86 | * @argument2: UIC command argument 2 | |
87 | * @argument3: UIC command argument 3 | |
88 | * @cmd_active: Indicate if UIC command is outstanding | |
89 | * @result: UIC command result | |
6ccf44fe | 90 | * @done: UIC command completion |
e0eca63e VH |
91 | */ |
92 | struct uic_command { | |
93 | u32 command; | |
94 | u32 argument1; | |
95 | u32 argument2; | |
96 | u32 argument3; | |
97 | int cmd_active; | |
98 | int result; | |
6ccf44fe | 99 | struct completion done; |
e0eca63e VH |
100 | }; |
101 | ||
57d104c1 SJ |
102 | /* Used to differentiate the power management options */ |
103 | enum ufs_pm_op { | |
104 | UFS_RUNTIME_PM, | |
105 | UFS_SYSTEM_PM, | |
106 | UFS_SHUTDOWN_PM, | |
107 | }; | |
108 | ||
109 | #define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM) | |
110 | #define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM) | |
111 | #define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM) | |
112 | ||
113 | /* Host <-> Device UniPro Link state */ | |
114 | enum uic_link_state { | |
115 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ | |
116 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ | |
117 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ | |
118 | }; | |
119 | ||
120 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) | |
121 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ | |
122 | UIC_LINK_ACTIVE_STATE) | |
123 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ | |
124 | UIC_LINK_HIBERN8_STATE) | |
125 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) | |
126 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ | |
127 | UIC_LINK_ACTIVE_STATE) | |
128 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ | |
129 | UIC_LINK_HIBERN8_STATE) | |
130 | ||
131 | /* | |
132 | * UFS Power management levels. | |
133 | * Each level is in increasing order of power savings. | |
134 | */ | |
135 | enum ufs_pm_level { | |
136 | UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
137 | UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
138 | UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
139 | UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
140 | UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
141 | UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */ | |
142 | UFS_PM_LVL_MAX | |
143 | }; | |
144 | ||
145 | struct ufs_pm_lvl_states { | |
146 | enum ufs_dev_pwr_mode dev_state; | |
147 | enum uic_link_state link_state; | |
148 | }; | |
149 | ||
e0eca63e VH |
150 | /** |
151 | * struct ufshcd_lrb - local reference block | |
152 | * @utr_descriptor_ptr: UTRD address of the command | |
5a0b0cb9 | 153 | * @ucd_req_ptr: UCD address of the command |
e0eca63e VH |
154 | * @ucd_rsp_ptr: Response UPIU address for this command |
155 | * @ucd_prdt_ptr: PRDT address of the command | |
ff8e20c6 DR |
156 | * @utrd_dma_addr: UTRD dma address for debug |
157 | * @ucd_prdt_dma_addr: PRDT dma address for debug | |
158 | * @ucd_rsp_dma_addr: UPIU response dma address for debug | |
159 | * @ucd_req_dma_addr: UPIU request dma address for debug | |
e0eca63e VH |
160 | * @cmd: pointer to SCSI command |
161 | * @sense_buffer: pointer to sense buffer address of the SCSI command | |
162 | * @sense_bufflen: Length of the sense buffer | |
163 | * @scsi_status: SCSI status of the command | |
164 | * @command_type: SCSI, UFS, Query. | |
165 | * @task_tag: Task tag of the command | |
166 | * @lun: LUN of the command | |
5a0b0cb9 | 167 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
ff8e20c6 | 168 | * @issue_time_stamp: time stamp for debug purposes |
09017188 | 169 | * @compl_time_stamp: time stamp for statistics |
e0b299e3 | 170 | * @req_abort_skip: skip request abort task flag |
e0eca63e VH |
171 | */ |
172 | struct ufshcd_lrb { | |
173 | struct utp_transfer_req_desc *utr_descriptor_ptr; | |
5a0b0cb9 | 174 | struct utp_upiu_req *ucd_req_ptr; |
e0eca63e VH |
175 | struct utp_upiu_rsp *ucd_rsp_ptr; |
176 | struct ufshcd_sg_entry *ucd_prdt_ptr; | |
177 | ||
ff8e20c6 DR |
178 | dma_addr_t utrd_dma_addr; |
179 | dma_addr_t ucd_req_dma_addr; | |
180 | dma_addr_t ucd_rsp_dma_addr; | |
181 | dma_addr_t ucd_prdt_dma_addr; | |
182 | ||
e0eca63e VH |
183 | struct scsi_cmnd *cmd; |
184 | u8 *sense_buffer; | |
185 | unsigned int sense_bufflen; | |
186 | int scsi_status; | |
187 | ||
188 | int command_type; | |
189 | int task_tag; | |
0ce147d4 | 190 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
5a0b0cb9 | 191 | bool intr_cmd; |
ff8e20c6 | 192 | ktime_t issue_time_stamp; |
09017188 | 193 | ktime_t compl_time_stamp; |
e0b299e3 GB |
194 | |
195 | bool req_abort_skip; | |
e0eca63e VH |
196 | }; |
197 | ||
68078d5c | 198 | /** |
a230c2f6 | 199 | * struct ufs_query - holds relevant data structures for query request |
68078d5c DR |
200 | * @request: request upiu and function |
201 | * @descriptor: buffer for sending/receiving descriptor | |
202 | * @response: response upiu and response | |
203 | */ | |
204 | struct ufs_query { | |
205 | struct ufs_query_req request; | |
206 | u8 *descriptor; | |
207 | struct ufs_query_res response; | |
208 | }; | |
209 | ||
5a0b0cb9 SRT |
210 | /** |
211 | * struct ufs_dev_cmd - all assosiated fields with device management commands | |
212 | * @type: device management command type - Query, NOP OUT | |
213 | * @lock: lock to allow one command at a time | |
214 | * @complete: internal commands completion | |
215 | * @tag_wq: wait queue until free command slot is available | |
216 | */ | |
217 | struct ufs_dev_cmd { | |
218 | enum dev_cmd_type type; | |
219 | struct mutex lock; | |
220 | struct completion *complete; | |
221 | wait_queue_head_t tag_wq; | |
68078d5c | 222 | struct ufs_query query; |
5a0b0cb9 | 223 | }; |
e0eca63e | 224 | |
a4b0e8a4 PM |
225 | struct ufs_desc_size { |
226 | int dev_desc; | |
227 | int pwr_desc; | |
228 | int geom_desc; | |
229 | int interc_desc; | |
230 | int unit_desc; | |
231 | int conf_desc; | |
c648c2d2 | 232 | int hlth_desc; |
a4b0e8a4 PM |
233 | }; |
234 | ||
c6e79dac SRT |
235 | /** |
236 | * struct ufs_clk_info - UFS clock related info | |
237 | * @list: list headed by hba->clk_list_head | |
238 | * @clk: clock node | |
239 | * @name: clock name | |
240 | * @max_freq: maximum frequency supported by the clock | |
4cff6d99 | 241 | * @min_freq: min frequency that can be used for clock scaling |
856b3483 | 242 | * @curr_freq: indicates the current frequency that it is set to |
c6e79dac SRT |
243 | * @enabled: variable to check against multiple enable/disable |
244 | */ | |
245 | struct ufs_clk_info { | |
246 | struct list_head list; | |
247 | struct clk *clk; | |
248 | const char *name; | |
249 | u32 max_freq; | |
4cff6d99 | 250 | u32 min_freq; |
856b3483 | 251 | u32 curr_freq; |
c6e79dac SRT |
252 | bool enabled; |
253 | }; | |
254 | ||
f06fcc71 YG |
255 | enum ufs_notify_change_status { |
256 | PRE_CHANGE, | |
257 | POST_CHANGE, | |
258 | }; | |
7eb584db DR |
259 | |
260 | struct ufs_pa_layer_attr { | |
261 | u32 gear_rx; | |
262 | u32 gear_tx; | |
263 | u32 lane_rx; | |
264 | u32 lane_tx; | |
265 | u32 pwr_rx; | |
266 | u32 pwr_tx; | |
267 | u32 hs_rate; | |
268 | }; | |
269 | ||
270 | struct ufs_pwr_mode_info { | |
271 | bool is_valid; | |
272 | struct ufs_pa_layer_attr info; | |
273 | }; | |
274 | ||
5c0c28a8 SRT |
275 | /** |
276 | * struct ufs_hba_variant_ops - variant specific callbacks | |
277 | * @name: variant name | |
278 | * @init: called when the driver is initialized | |
279 | * @exit: called to cleanup everything done in init | |
9949e702 | 280 | * @get_ufs_hci_version: called to get UFS HCI version |
856b3483 | 281 | * @clk_scale_notify: notifies that clks are scaled up/down |
5c0c28a8 SRT |
282 | * @setup_clocks: called before touching any of the controller registers |
283 | * @setup_regulators: called before accessing the host controller | |
284 | * @hce_enable_notify: called before and after HCE enable bit is set to allow | |
285 | * variant specific Uni-Pro initialization. | |
286 | * @link_startup_notify: called before and after Link startup is carried out | |
287 | * to allow variant specific Uni-Pro initialization. | |
7eb584db DR |
288 | * @pwr_change_notify: called before and after a power mode change |
289 | * is carried out to allow vendor spesific capabilities | |
290 | * to be set. | |
0e675efa KK |
291 | * @setup_xfer_req: called before any transfer request is issued |
292 | * to set some things | |
d2877be4 KK |
293 | * @setup_task_mgmt: called before any task management request is issued |
294 | * to set some things | |
ee32c909 | 295 | * @hibern8_notify: called around hibern8 enter/exit |
56d4a186 | 296 | * @apply_dev_quirks: called to apply device specific quirks |
57d104c1 SJ |
297 | * @suspend: called during host controller PM callback |
298 | * @resume: called during host controller PM callback | |
6e3fd44d | 299 | * @dbg_register_dump: used to dump controller debug information |
4b9ffb5a | 300 | * @phy_initialization: used to initialize phys |
5c0c28a8 SRT |
301 | */ |
302 | struct ufs_hba_variant_ops { | |
303 | const char *name; | |
304 | int (*init)(struct ufs_hba *); | |
305 | void (*exit)(struct ufs_hba *); | |
9949e702 | 306 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
f06fcc71 YG |
307 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
308 | enum ufs_notify_change_status); | |
1e879e8f SJ |
309 | int (*setup_clocks)(struct ufs_hba *, bool, |
310 | enum ufs_notify_change_status); | |
5c0c28a8 | 311 | int (*setup_regulators)(struct ufs_hba *, bool); |
f06fcc71 YG |
312 | int (*hce_enable_notify)(struct ufs_hba *, |
313 | enum ufs_notify_change_status); | |
314 | int (*link_startup_notify)(struct ufs_hba *, | |
315 | enum ufs_notify_change_status); | |
7eb584db | 316 | int (*pwr_change_notify)(struct ufs_hba *, |
f06fcc71 YG |
317 | enum ufs_notify_change_status status, |
318 | struct ufs_pa_layer_attr *, | |
7eb584db | 319 | struct ufs_pa_layer_attr *); |
0e675efa | 320 | void (*setup_xfer_req)(struct ufs_hba *, int, bool); |
d2877be4 | 321 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
ee32c909 | 322 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
56d4a186 SJ |
323 | enum ufs_notify_change_status); |
324 | int (*apply_dev_quirks)(struct ufs_hba *); | |
57d104c1 SJ |
325 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op); |
326 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); | |
6e3fd44d | 327 | void (*dbg_register_dump)(struct ufs_hba *hba); |
4b9ffb5a | 328 | int (*phy_initialization)(struct ufs_hba *); |
5c0c28a8 SRT |
329 | }; |
330 | ||
1ab27c9c ST |
331 | /* clock gating state */ |
332 | enum clk_gating_state { | |
333 | CLKS_OFF, | |
334 | CLKS_ON, | |
335 | REQ_CLKS_OFF, | |
336 | REQ_CLKS_ON, | |
337 | }; | |
338 | ||
339 | /** | |
340 | * struct ufs_clk_gating - UFS clock gating related info | |
341 | * @gate_work: worker to turn off clocks after some delay as specified in | |
342 | * delay_ms | |
343 | * @ungate_work: worker to turn on clocks that will be used in case of | |
344 | * interrupt context | |
345 | * @state: the current clocks state | |
346 | * @delay_ms: gating delay in ms | |
347 | * @is_suspended: clk gating is suspended when set to 1 which can be used | |
348 | * during suspend/resume | |
349 | * @delay_attr: sysfs attribute to control delay_attr | |
b427411a ST |
350 | * @enable_attr: sysfs attribute to enable/disable clock gating |
351 | * @is_enabled: Indicates the current status of clock gating | |
1ab27c9c ST |
352 | * @active_reqs: number of requests that are pending and should be waited for |
353 | * completion before gating clocks. | |
354 | */ | |
355 | struct ufs_clk_gating { | |
356 | struct delayed_work gate_work; | |
357 | struct work_struct ungate_work; | |
358 | enum clk_gating_state state; | |
359 | unsigned long delay_ms; | |
360 | bool is_suspended; | |
361 | struct device_attribute delay_attr; | |
b427411a ST |
362 | struct device_attribute enable_attr; |
363 | bool is_enabled; | |
1ab27c9c | 364 | int active_reqs; |
10e5e375 | 365 | struct workqueue_struct *clk_gating_workq; |
1ab27c9c ST |
366 | }; |
367 | ||
a3cd5ec5 | 368 | struct ufs_saved_pwr_info { |
369 | struct ufs_pa_layer_attr info; | |
370 | bool is_valid; | |
371 | }; | |
372 | ||
401f1e44 | 373 | /** |
374 | * struct ufs_clk_scaling - UFS clock scaling related data | |
375 | * @active_reqs: number of requests that are pending. If this is zero when | |
376 | * devfreq ->target() function is called then schedule "suspend_work" to | |
377 | * suspend devfreq. | |
378 | * @tot_busy_t: Total busy time in current polling window | |
379 | * @window_start_t: Start time (in jiffies) of the current polling window | |
380 | * @busy_start_t: Start time of current busy period | |
381 | * @enable_attr: sysfs attribute to enable/disable clock scaling | |
382 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this | |
383 | * one keeps track of previous power mode. | |
384 | * @workq: workqueue to schedule devfreq suspend/resume work | |
385 | * @suspend_work: worker to suspend devfreq | |
386 | * @resume_work: worker to resume devfreq | |
387 | * @is_allowed: tracks if scaling is currently allowed or not | |
388 | * @is_busy_started: tracks if busy period has started or not | |
389 | * @is_suspended: tracks if devfreq is suspended or not | |
390 | */ | |
856b3483 | 391 | struct ufs_clk_scaling { |
401f1e44 | 392 | int active_reqs; |
393 | unsigned long tot_busy_t; | |
856b3483 | 394 | unsigned long window_start_t; |
401f1e44 | 395 | ktime_t busy_start_t; |
fcb0c4b0 | 396 | struct device_attribute enable_attr; |
a3cd5ec5 | 397 | struct ufs_saved_pwr_info saved_pwr_info; |
401f1e44 | 398 | struct workqueue_struct *workq; |
399 | struct work_struct suspend_work; | |
400 | struct work_struct resume_work; | |
401 | bool is_allowed; | |
402 | bool is_busy_started; | |
403 | bool is_suspended; | |
856b3483 ST |
404 | }; |
405 | ||
3a4bf06d YG |
406 | /** |
407 | * struct ufs_init_prefetch - contains data that is pre-fetched once during | |
408 | * initialization | |
409 | * @icc_level: icc level which was read during initialization | |
410 | */ | |
411 | struct ufs_init_prefetch { | |
412 | u32 icc_level; | |
413 | }; | |
414 | ||
ff8e20c6 DR |
415 | #define UIC_ERR_REG_HIST_LENGTH 8 |
416 | /** | |
417 | * struct ufs_uic_err_reg_hist - keeps history of uic errors | |
418 | * @pos: index to indicate cyclic buffer position | |
419 | * @reg: cyclic buffer for registers value | |
420 | * @tstamp: cyclic buffer for time stamp | |
421 | */ | |
422 | struct ufs_uic_err_reg_hist { | |
423 | int pos; | |
424 | u32 reg[UIC_ERR_REG_HIST_LENGTH]; | |
425 | ktime_t tstamp[UIC_ERR_REG_HIST_LENGTH]; | |
426 | }; | |
427 | ||
428 | /** | |
429 | * struct ufs_stats - keeps usage/err statistics | |
430 | * @hibern8_exit_cnt: Counter to keep track of number of exits, | |
431 | * reset this after link-startup. | |
432 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. | |
433 | * Clear after the first successful command completion. | |
434 | * @pa_err: tracks pa-uic errors | |
435 | * @dl_err: tracks dl-uic errors | |
436 | * @nl_err: tracks nl-uic errors | |
437 | * @tl_err: tracks tl-uic errors | |
438 | * @dme_err: tracks dme errors | |
439 | */ | |
440 | struct ufs_stats { | |
441 | u32 hibern8_exit_cnt; | |
442 | ktime_t last_hibern8_exit_tstamp; | |
443 | struct ufs_uic_err_reg_hist pa_err; | |
444 | struct ufs_uic_err_reg_hist dl_err; | |
445 | struct ufs_uic_err_reg_hist nl_err; | |
446 | struct ufs_uic_err_reg_hist tl_err; | |
447 | struct ufs_uic_err_reg_hist dme_err; | |
448 | }; | |
449 | ||
e0eca63e VH |
450 | /** |
451 | * struct ufs_hba - per adapter private structure | |
452 | * @mmio_base: UFSHCI base register address | |
453 | * @ucdl_base_addr: UFS Command Descriptor base address | |
454 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address | |
455 | * @utmrdl_base_addr: UTP Task Management Descriptor base address | |
456 | * @ucdl_dma_addr: UFS Command Descriptor DMA address | |
457 | * @utrdl_dma_addr: UTRDL DMA address | |
458 | * @utmrdl_dma_addr: UTMRDL DMA address | |
459 | * @host: Scsi_Host instance of the driver | |
460 | * @dev: device handle | |
461 | * @lrb: local reference block | |
5a0b0cb9 | 462 | * @lrb_in_use: lrb in use |
e0eca63e VH |
463 | * @outstanding_tasks: Bits representing outstanding task requests |
464 | * @outstanding_reqs: Bits representing outstanding transfer requests | |
465 | * @capabilities: UFS Controller Capabilities | |
466 | * @nutrs: Transfer Request Queue depth supported by controller | |
467 | * @nutmrs: Task Management Queue depth supported by controller | |
468 | * @ufs_version: UFS Version to which controller complies | |
5c0c28a8 SRT |
469 | * @vops: pointer to variant specific operations |
470 | * @priv: pointer to variant specific private data | |
e0eca63e VH |
471 | * @irq: Irq number of the controller |
472 | * @active_uic_cmd: handle of active UIC command | |
6ccf44fe | 473 | * @uic_cmd_mutex: mutex for uic command |
e2933132 SRT |
474 | * @tm_wq: wait queue for task management |
475 | * @tm_tag_wq: wait queue for free task management slots | |
476 | * @tm_slots_in_use: bit map of task management request slots in use | |
53b3d9c3 | 477 | * @pwr_done: completion for power mode change |
e0eca63e VH |
478 | * @tm_condition: condition variable for task management |
479 | * @ufshcd_state: UFSHCD states | |
3441da7d | 480 | * @eh_flags: Error handling flags |
2fbd009b | 481 | * @intr_mask: Interrupt Mask Bits |
66ec6d59 | 482 | * @ee_ctrl_mask: Exception event control mask |
1d337ec2 | 483 | * @is_powered: flag to check if HBA is powered |
3a4bf06d YG |
484 | * @is_init_prefetch: flag to check if data was pre-fetched in initialization |
485 | * @init_prefetch_data: data pre-fetched during initialization | |
e8e7f271 | 486 | * @eh_work: Worker to handle UFS errors that require s/w attention |
66ec6d59 | 487 | * @eeh_work: Worker to handle exception events |
e0eca63e | 488 | * @errors: HBA errors |
e8e7f271 SRT |
489 | * @uic_error: UFS interconnect layer error status |
490 | * @saved_err: sticky error mask | |
491 | * @saved_uic_err: sticky UIC error mask | |
5a0b0cb9 | 492 | * @dev_cmd: ufs device management command information |
cad2e03d | 493 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
66ec6d59 | 494 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
aa497613 | 495 | * @vreg_info: UFS device voltage regulator information |
c6e79dac | 496 | * @clk_list_head: UFS host controller clocks list node head |
7eb584db DR |
497 | * @pwr_info: holds current power mode |
498 | * @max_pwr_info: keeps the device max valid pwm | |
a4b0e8a4 | 499 | * @desc_size: descriptor sizes reported by device |
afdfff59 YG |
500 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
501 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for | |
502 | * device is known or not. | |
38135535 | 503 | * @scsi_block_reqs_cnt: reference counting for scsi block requests |
e0eca63e VH |
504 | */ |
505 | struct ufs_hba { | |
506 | void __iomem *mmio_base; | |
507 | ||
508 | /* Virtual memory reference */ | |
509 | struct utp_transfer_cmd_desc *ucdl_base_addr; | |
510 | struct utp_transfer_req_desc *utrdl_base_addr; | |
511 | struct utp_task_req_desc *utmrdl_base_addr; | |
512 | ||
513 | /* DMA memory reference */ | |
514 | dma_addr_t ucdl_dma_addr; | |
515 | dma_addr_t utrdl_dma_addr; | |
516 | dma_addr_t utmrdl_dma_addr; | |
517 | ||
518 | struct Scsi_Host *host; | |
519 | struct device *dev; | |
2a8fa600 SJ |
520 | /* |
521 | * This field is to keep a reference to "scsi_device" corresponding to | |
522 | * "UFS device" W-LU. | |
523 | */ | |
524 | struct scsi_device *sdev_ufs_device; | |
e0eca63e | 525 | |
57d104c1 SJ |
526 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
527 | enum uic_link_state uic_link_state; | |
528 | /* Desired UFS power management level during runtime PM */ | |
529 | enum ufs_pm_level rpm_lvl; | |
530 | /* Desired UFS power management level during system PM */ | |
531 | enum ufs_pm_level spm_lvl; | |
09690d5a | 532 | struct device_attribute rpm_lvl_attr; |
533 | struct device_attribute spm_lvl_attr; | |
57d104c1 SJ |
534 | int pm_op_in_progress; |
535 | ||
ad448378 AH |
536 | /* Auto-Hibernate Idle Timer register value */ |
537 | u32 ahit; | |
538 | ||
e0eca63e | 539 | struct ufshcd_lrb *lrb; |
5a0b0cb9 | 540 | unsigned long lrb_in_use; |
e0eca63e VH |
541 | |
542 | unsigned long outstanding_tasks; | |
543 | unsigned long outstanding_reqs; | |
544 | ||
545 | u32 capabilities; | |
546 | int nutrs; | |
547 | int nutmrs; | |
548 | u32 ufs_version; | |
5c0c28a8 SRT |
549 | struct ufs_hba_variant_ops *vops; |
550 | void *priv; | |
e0eca63e | 551 | unsigned int irq; |
57d104c1 | 552 | bool is_irq_enabled; |
e0eca63e | 553 | |
b852190e | 554 | /* Interrupt aggregation support is broken */ |
cc81641a | 555 | #define UFSHCD_QUIRK_BROKEN_INTR_AGGR 0x1 |
b852190e | 556 | |
cad2e03d YG |
557 | /* |
558 | * delay before each dme command is required as the unipro | |
559 | * layer has shown instabilities | |
560 | */ | |
cc81641a | 561 | #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 0x2 |
b852190e | 562 | |
7ca38cf3 YG |
563 | /* |
564 | * If UFS host controller is having issue in processing LCC (Line | |
565 | * Control Command) coming from device then enable this quirk. | |
566 | * When this quirk is enabled, host controller driver should disable | |
567 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE | |
568 | * attribute of device to 0). | |
569 | */ | |
cc81641a | 570 | #define UFSHCD_QUIRK_BROKEN_LCC 0x4 |
cad2e03d | 571 | |
c3a2f9ee YG |
572 | /* |
573 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the | |
574 | * inbound Link supports unterminated line in HS mode. Setting this | |
575 | * attribute to 1 fixes moving to HS gear. | |
576 | */ | |
cc81641a | 577 | #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 0x8 |
c3a2f9ee | 578 | |
874237f7 YG |
579 | /* |
580 | * This quirk needs to be enabled if the host contoller only allows | |
581 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or | |
582 | * SLOW AUTO). | |
583 | */ | |
cc81641a | 584 | #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 0x10 |
874237f7 | 585 | |
9949e702 YG |
586 | /* |
587 | * This quirk needs to be enabled if the host contoller doesn't | |
588 | * advertise the correct version in UFS_VER register. If this quirk | |
589 | * is enabled, standard UFS host driver will call the vendor specific | |
590 | * ops (get_ufs_hci_version) to get the correct version. | |
591 | */ | |
cc81641a | 592 | #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION 0x20 |
9949e702 | 593 | |
75b1cc4a KK |
594 | /* |
595 | * This quirk needs to be enabled if the host contoller regards | |
596 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. | |
597 | */ | |
cc81641a | 598 | #define UFSHCD_QUIRK_PRDT_BYTE_GRAN 0x80 |
75b1cc4a | 599 | |
1399c5b0 AA |
600 | /* |
601 | * Clear handling for transfer/task request list is just opposite. | |
602 | */ | |
603 | #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR 0x100 | |
604 | ||
5ac6abc9 AA |
605 | /* |
606 | * This quirk needs to be enabled if host controller doesn't allow | |
607 | * that the interrupt aggregation timer and counter are reset by s/w. | |
608 | */ | |
609 | #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR 0x200 | |
610 | ||
4404c5de AA |
611 | /* |
612 | * This quirks needs to be enabled if host controller cannot be | |
613 | * enabled via HCE register. | |
614 | */ | |
615 | #define UFSHCI_QUIRK_BROKEN_HCE 0x400 | |
cad2e03d | 616 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
6ccf44fe | 617 | |
c58ab7aa YG |
618 | /* Device deviations from standard UFS device spec. */ |
619 | unsigned int dev_quirks; | |
620 | ||
e2933132 SRT |
621 | wait_queue_head_t tm_wq; |
622 | wait_queue_head_t tm_tag_wq; | |
e0eca63e | 623 | unsigned long tm_condition; |
e2933132 | 624 | unsigned long tm_slots_in_use; |
e0eca63e | 625 | |
57d104c1 SJ |
626 | struct uic_command *active_uic_cmd; |
627 | struct mutex uic_cmd_mutex; | |
628 | struct completion *uic_async_done; | |
53b3d9c3 | 629 | |
e0eca63e | 630 | u32 ufshcd_state; |
3441da7d | 631 | u32 eh_flags; |
2fbd009b | 632 | u32 intr_mask; |
66ec6d59 | 633 | u16 ee_ctrl_mask; |
1d337ec2 | 634 | bool is_powered; |
3a4bf06d YG |
635 | bool is_init_prefetch; |
636 | struct ufs_init_prefetch init_prefetch_data; | |
e0eca63e VH |
637 | |
638 | /* Work Queues */ | |
e8e7f271 | 639 | struct work_struct eh_work; |
66ec6d59 | 640 | struct work_struct eeh_work; |
e0eca63e VH |
641 | |
642 | /* HBA Errors */ | |
643 | u32 errors; | |
e8e7f271 SRT |
644 | u32 uic_error; |
645 | u32 saved_err; | |
646 | u32 saved_uic_err; | |
ff8e20c6 | 647 | struct ufs_stats ufs_stats; |
5a0b0cb9 SRT |
648 | |
649 | /* Device management request data */ | |
650 | struct ufs_dev_cmd dev_cmd; | |
cad2e03d | 651 | ktime_t last_dme_cmd_tstamp; |
66ec6d59 | 652 | |
57d104c1 SJ |
653 | /* Keeps information of the UFS device connected to this host */ |
654 | struct ufs_dev_info dev_info; | |
66ec6d59 | 655 | bool auto_bkops_enabled; |
aa497613 | 656 | struct ufs_vreg_info vreg_info; |
c6e79dac | 657 | struct list_head clk_list_head; |
57d104c1 SJ |
658 | |
659 | bool wlun_dev_clr_ua; | |
7eb584db | 660 | |
7fabb77b GB |
661 | /* Number of requests aborts */ |
662 | int req_abort_count; | |
663 | ||
54b879b7 YG |
664 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
665 | u32 lanes_per_direction; | |
7eb584db DR |
666 | struct ufs_pa_layer_attr pwr_info; |
667 | struct ufs_pwr_mode_info max_pwr_info; | |
1ab27c9c ST |
668 | |
669 | struct ufs_clk_gating clk_gating; | |
670 | /* Control to enable/disable host capabilities */ | |
671 | u32 caps; | |
672 | /* Allow dynamic clk gating */ | |
673 | #define UFSHCD_CAP_CLK_GATING (1 << 0) | |
674 | /* Allow hiberb8 with clk gating */ | |
675 | #define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1) | |
856b3483 ST |
676 | /* Allow dynamic clk scaling */ |
677 | #define UFSHCD_CAP_CLK_SCALING (1 << 2) | |
374a246e SJ |
678 | /* Allow auto bkops to enabled during runtime suspend */ |
679 | #define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3) | |
b852190e YG |
680 | /* |
681 | * This capability allows host controller driver to use the UFS HCI's | |
682 | * interrupt aggregation capability. | |
683 | * CAUTION: Enabling this might reduce overall UFS throughput. | |
684 | */ | |
685 | #define UFSHCD_CAP_INTR_AGGR (1 << 4) | |
4e768e76 | 686 | /* |
687 | * This capability allows the device auto-bkops to be always enabled | |
688 | * except during suspend (both runtime and suspend). | |
689 | * Enabling this capability means that device will always be allowed | |
690 | * to do background operation when it's active but it might degrade | |
691 | * the performance of ongoing read/write operations. | |
692 | */ | |
693 | #define UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND (1 << 5) | |
856b3483 ST |
694 | |
695 | struct devfreq *devfreq; | |
696 | struct ufs_clk_scaling clk_scaling; | |
e785060e | 697 | bool is_sys_suspended; |
afdfff59 YG |
698 | |
699 | enum bkops_status urgent_bkops_lvl; | |
700 | bool is_urgent_bkops_lvl_checked; | |
a3cd5ec5 | 701 | |
702 | struct rw_semaphore clk_scaling_lock; | |
a4b0e8a4 | 703 | struct ufs_desc_size desc_size; |
38135535 | 704 | atomic_t scsi_block_reqs_cnt; |
df032bf2 AA |
705 | |
706 | struct device bsg_dev; | |
707 | struct request_queue *bsg_queue; | |
e0eca63e VH |
708 | }; |
709 | ||
1ab27c9c ST |
710 | /* Returns true if clocks can be gated. Otherwise false */ |
711 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) | |
712 | { | |
713 | return hba->caps & UFSHCD_CAP_CLK_GATING; | |
714 | } | |
715 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) | |
716 | { | |
717 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; | |
718 | } | |
fcb0c4b0 | 719 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
856b3483 ST |
720 | { |
721 | return hba->caps & UFSHCD_CAP_CLK_SCALING; | |
722 | } | |
374a246e SJ |
723 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
724 | { | |
725 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
726 | } | |
727 | ||
b852190e YG |
728 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
729 | { | |
4b9ffb5a JP |
730 | /* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/ |
731 | #ifndef CONFIG_SCSI_UFS_DWC | |
b852190e YG |
732 | if ((hba->caps & UFSHCD_CAP_INTR_AGGR) && |
733 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR)) | |
734 | return true; | |
735 | else | |
736 | return false; | |
4b9ffb5a JP |
737 | #else |
738 | return true; | |
739 | #endif | |
b852190e YG |
740 | } |
741 | ||
b873a275 SJ |
742 | #define ufshcd_writel(hba, val, reg) \ |
743 | writel((val), (hba)->mmio_base + (reg)) | |
744 | #define ufshcd_readl(hba, reg) \ | |
745 | readl((hba)->mmio_base + (reg)) | |
746 | ||
e785060e DR |
747 | /** |
748 | * ufshcd_rmwl - read modify write into a register | |
749 | * @hba - per adapter instance | |
750 | * @mask - mask to apply on read value | |
751 | * @val - actual value to write | |
752 | * @reg - register address | |
753 | */ | |
754 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) | |
755 | { | |
756 | u32 tmp; | |
757 | ||
758 | tmp = ufshcd_readl(hba, reg); | |
759 | tmp &= ~mask; | |
760 | tmp |= (val & mask); | |
761 | ufshcd_writel(hba, tmp, reg); | |
762 | } | |
763 | ||
5c0c28a8 | 764 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
47555a5c | 765 | void ufshcd_dealloc_host(struct ufs_hba *); |
5c0c28a8 | 766 | int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int); |
e0eca63e | 767 | void ufshcd_remove(struct ufs_hba *); |
596585a2 YG |
768 | int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, |
769 | u32 val, unsigned long interval_us, | |
770 | unsigned long timeout_ms, bool can_sleep); | |
e0eca63e | 771 | |
68078d5c DR |
772 | static inline void check_upiu_size(void) |
773 | { | |
774 | BUILD_BUG_ON(ALIGNED_UPIU_SIZE < | |
775 | GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); | |
776 | } | |
777 | ||
1ce5898a YG |
778 | /** |
779 | * ufshcd_set_variant - set variant specific data to the hba | |
780 | * @hba - per adapter instance | |
781 | * @variant - pointer to variant specific data | |
782 | */ | |
783 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) | |
784 | { | |
785 | BUG_ON(!hba); | |
786 | hba->priv = variant; | |
787 | } | |
788 | ||
789 | /** | |
790 | * ufshcd_get_variant - get variant specific data from the hba | |
791 | * @hba - per adapter instance | |
792 | */ | |
793 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) | |
794 | { | |
795 | BUG_ON(!hba); | |
796 | return hba->priv; | |
797 | } | |
4e768e76 | 798 | static inline bool ufshcd_keep_autobkops_enabled_except_suspend( |
799 | struct ufs_hba *hba) | |
800 | { | |
801 | return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND; | |
802 | } | |
1ce5898a | 803 | |
66ec6d59 SRT |
804 | extern int ufshcd_runtime_suspend(struct ufs_hba *hba); |
805 | extern int ufshcd_runtime_resume(struct ufs_hba *hba); | |
806 | extern int ufshcd_runtime_idle(struct ufs_hba *hba); | |
57d104c1 SJ |
807 | extern int ufshcd_system_suspend(struct ufs_hba *hba); |
808 | extern int ufshcd_system_resume(struct ufs_hba *hba); | |
809 | extern int ufshcd_shutdown(struct ufs_hba *hba); | |
12b4fdb4 SJ |
810 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
811 | u8 attr_set, u32 mib_val, u8 peer); | |
812 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
813 | u32 *mib_val, u8 peer); | |
0d846e70 AA |
814 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
815 | struct ufs_pa_layer_attr *desired_pwr_mode); | |
12b4fdb4 SJ |
816 | |
817 | /* UIC command interfaces for DME primitives */ | |
818 | #define DME_LOCAL 0 | |
819 | #define DME_PEER 1 | |
820 | #define ATTR_SET_NOR 0 /* NORMAL */ | |
821 | #define ATTR_SET_ST 1 /* STATIC */ | |
822 | ||
823 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, | |
824 | u32 mib_val) | |
825 | { | |
826 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
827 | mib_val, DME_LOCAL); | |
828 | } | |
829 | ||
830 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, | |
831 | u32 mib_val) | |
832 | { | |
833 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
834 | mib_val, DME_LOCAL); | |
835 | } | |
836 | ||
837 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, | |
838 | u32 mib_val) | |
839 | { | |
840 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
841 | mib_val, DME_PEER); | |
842 | } | |
843 | ||
844 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, | |
845 | u32 mib_val) | |
846 | { | |
847 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
848 | mib_val, DME_PEER); | |
849 | } | |
850 | ||
851 | static inline int ufshcd_dme_get(struct ufs_hba *hba, | |
852 | u32 attr_sel, u32 *mib_val) | |
853 | { | |
854 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); | |
855 | } | |
856 | ||
857 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, | |
858 | u32 attr_sel, u32 *mib_val) | |
859 | { | |
860 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); | |
861 | } | |
862 | ||
f37aabcf YG |
863 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
864 | { | |
865 | return (pwr_info->pwr_rx == FAST_MODE || | |
866 | pwr_info->pwr_rx == FASTAUTO_MODE) && | |
867 | (pwr_info->pwr_tx == FAST_MODE || | |
868 | pwr_info->pwr_tx == FASTAUTO_MODE); | |
869 | } | |
870 | ||
dc3c8d3a | 871 | /* Expose Query-Request API */ |
2238d31c SN |
872 | int ufshcd_query_descriptor_retry(struct ufs_hba *hba, |
873 | enum query_opcode opcode, | |
874 | enum desc_idn idn, u8 index, | |
875 | u8 selector, | |
876 | u8 *desc_buf, int *buf_len); | |
45bced87 SN |
877 | int ufshcd_read_desc_param(struct ufs_hba *hba, |
878 | enum desc_idn desc_id, | |
879 | int desc_index, | |
880 | u8 param_offset, | |
881 | u8 *param_read_buf, | |
882 | u8 param_size); | |
ec92b59c SN |
883 | int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, |
884 | enum attr_idn idn, u8 index, u8 selector, u32 *attr_val); | |
dc3c8d3a YG |
885 | int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, |
886 | enum flag_idn idn, bool *flag_res); | |
2238d31c SN |
887 | int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, |
888 | u8 *buf, u32 size, bool ascii); | |
889 | ||
1ab27c9c ST |
890 | int ufshcd_hold(struct ufs_hba *hba, bool async); |
891 | void ufshcd_release(struct ufs_hba *hba); | |
a4b0e8a4 PM |
892 | |
893 | int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, | |
894 | int *desc_length); | |
895 | ||
37113106 | 896 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
0263bcd0 | 897 | |
e77044c5 AA |
898 | int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); |
899 | ||
5e0a86ee AA |
900 | int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, |
901 | struct utp_upiu_req *req_upiu, | |
902 | struct utp_upiu_req *rsp_upiu, | |
903 | int msgcode, | |
904 | u8 *desc_buff, int *buff_len, | |
905 | enum query_opcode desc_op); | |
906 | ||
0263bcd0 YG |
907 | /* Wrapper functions for safely calling variant operations */ |
908 | static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) | |
909 | { | |
910 | if (hba->vops) | |
911 | return hba->vops->name; | |
912 | return ""; | |
913 | } | |
914 | ||
915 | static inline int ufshcd_vops_init(struct ufs_hba *hba) | |
916 | { | |
917 | if (hba->vops && hba->vops->init) | |
918 | return hba->vops->init(hba); | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
923 | static inline void ufshcd_vops_exit(struct ufs_hba *hba) | |
924 | { | |
925 | if (hba->vops && hba->vops->exit) | |
926 | return hba->vops->exit(hba); | |
927 | } | |
928 | ||
929 | static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) | |
930 | { | |
931 | if (hba->vops && hba->vops->get_ufs_hci_version) | |
932 | return hba->vops->get_ufs_hci_version(hba); | |
933 | ||
934 | return ufshcd_readl(hba, REG_UFS_VERSION); | |
935 | } | |
936 | ||
f06fcc71 YG |
937 | static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, |
938 | bool up, enum ufs_notify_change_status status) | |
0263bcd0 YG |
939 | { |
940 | if (hba->vops && hba->vops->clk_scale_notify) | |
f06fcc71 YG |
941 | return hba->vops->clk_scale_notify(hba, up, status); |
942 | return 0; | |
0263bcd0 YG |
943 | } |
944 | ||
1e879e8f SJ |
945 | static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on, |
946 | enum ufs_notify_change_status status) | |
0263bcd0 YG |
947 | { |
948 | if (hba->vops && hba->vops->setup_clocks) | |
1e879e8f | 949 | return hba->vops->setup_clocks(hba, on, status); |
0263bcd0 YG |
950 | return 0; |
951 | } | |
952 | ||
953 | static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status) | |
954 | { | |
955 | if (hba->vops && hba->vops->setup_regulators) | |
956 | return hba->vops->setup_regulators(hba, status); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba, | |
962 | bool status) | |
963 | { | |
964 | if (hba->vops && hba->vops->hce_enable_notify) | |
965 | return hba->vops->hce_enable_notify(hba, status); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, | |
970 | bool status) | |
971 | { | |
972 | if (hba->vops && hba->vops->link_startup_notify) | |
973 | return hba->vops->link_startup_notify(hba, status); | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, | |
979 | bool status, | |
980 | struct ufs_pa_layer_attr *dev_max_params, | |
981 | struct ufs_pa_layer_attr *dev_req_params) | |
982 | { | |
983 | if (hba->vops && hba->vops->pwr_change_notify) | |
984 | return hba->vops->pwr_change_notify(hba, status, | |
985 | dev_max_params, dev_req_params); | |
986 | ||
987 | return -ENOTSUPP; | |
988 | } | |
989 | ||
0e675efa KK |
990 | static inline void ufshcd_vops_setup_xfer_req(struct ufs_hba *hba, int tag, |
991 | bool is_scsi_cmd) | |
992 | { | |
993 | if (hba->vops && hba->vops->setup_xfer_req) | |
994 | return hba->vops->setup_xfer_req(hba, tag, is_scsi_cmd); | |
995 | } | |
996 | ||
d2877be4 KK |
997 | static inline void ufshcd_vops_setup_task_mgmt(struct ufs_hba *hba, |
998 | int tag, u8 tm_function) | |
999 | { | |
1000 | if (hba->vops && hba->vops->setup_task_mgmt) | |
1001 | return hba->vops->setup_task_mgmt(hba, tag, tm_function); | |
1002 | } | |
1003 | ||
ee32c909 KK |
1004 | static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba, |
1005 | enum uic_cmd_dme cmd, | |
1006 | enum ufs_notify_change_status status) | |
1007 | { | |
1008 | if (hba->vops && hba->vops->hibern8_notify) | |
1009 | return hba->vops->hibern8_notify(hba, cmd, status); | |
1010 | } | |
1011 | ||
56d4a186 SJ |
1012 | static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba) |
1013 | { | |
1014 | if (hba->vops && hba->vops->apply_dev_quirks) | |
1015 | return hba->vops->apply_dev_quirks(hba); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
0263bcd0 YG |
1019 | static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) |
1020 | { | |
1021 | if (hba->vops && hba->vops->suspend) | |
1022 | return hba->vops->suspend(hba, op); | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op) | |
1028 | { | |
1029 | if (hba->vops && hba->vops->resume) | |
1030 | return hba->vops->resume(hba, op); | |
1031 | ||
1032 | return 0; | |
1033 | } | |
1034 | ||
6e3fd44d YG |
1035 | static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba) |
1036 | { | |
1037 | if (hba->vops && hba->vops->dbg_register_dump) | |
1038 | hba->vops->dbg_register_dump(hba); | |
1039 | } | |
1040 | ||
cbb6813e SN |
1041 | extern struct ufs_pm_lvl_states ufs_pm_lvl_states[]; |
1042 | ||
d829fc8a SN |
1043 | /* |
1044 | * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN | |
1045 | * @scsi_lun: scsi LUN id | |
1046 | * | |
1047 | * Returns UPIU LUN id | |
1048 | */ | |
1049 | static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun) | |
1050 | { | |
1051 | if (scsi_is_wlun(scsi_lun)) | |
1052 | return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID) | |
1053 | | UFS_UPIU_WLUN_ID; | |
1054 | else | |
1055 | return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID; | |
1056 | } | |
1057 | ||
ba80917d TW |
1058 | int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, |
1059 | const char *prefix); | |
1060 | ||
e0eca63e | 1061 | #endif /* End of Header */ |