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scsi: qla2xxx: Timeouts occur on surprise removal of QLogic adapter
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
e0eca63e 45#include "ufshcd.h"
c58ab7aa 46#include "ufs_quirks.h"
53b3d9c3 47#include "unipro.h"
cbb6813e 48#include "ufs-sysfs.h"
df032bf2 49#include "ufs_bsg.h"
7a3e97b0 50
7ff5ab47 51#define CREATE_TRACE_POINTS
52#include <trace/events/ufs.h>
53
dcea0bfb
GB		 54#define UFSHCD_REQ_SENSE_SIZE 18
55
2fbd009b
SJ		 56#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
57 UTP_TASK_REQ_COMPL |\
58 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 59/* UIC command timeout, unit: ms */
60#define UIC_CMD_TIMEOUT 500
2fbd009b 61
5a0b0cb9
SRT		 62/* NOP OUT retries waiting for NOP IN response */
63#define NOP_OUT_RETRIES 10
64/* Timeout after 30 msecs if NOP OUT hangs without response */
65#define NOP_OUT_TIMEOUT 30 /* msecs */
66
68078d5c 67/* Query request retries */
10fe5888 68#define QUERY_REQ_RETRIES 3
68078d5c 69/* Query request timeout */
10fe5888 70#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 71
e2933132
SRT		 72/* Task management command timeout */
73#define TM_CMD_TIMEOUT 100 /* msecs */
74
64238fbd
YG		 75/* maximum number of retries for a general UIC command */
76#define UFS_UIC_COMMAND_RETRIES 3
77
1d337ec2
SRT		 78/* maximum number of link-startup retries */
79#define DME_LINKSTARTUP_RETRIES 3
80
87d0b4a6
YG		 81/* Maximum retries for Hibern8 enter */
82#define UIC_HIBERN8_ENTER_RETRIES 3
83
1d337ec2
SRT		 84/* maximum number of reset retries before giving up */
85#define MAX_HOST_RESET_RETRIES 5
86
68078d5c
DR		 87/* Expose the flag value from utp_upiu_query.value */
88#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
89
7d568652
SJ		 90/* Interrupt aggregation default timeout, unit: 40us */
91#define INT_AGGR_DEF_TO 0x02
92
aa497613
SRT		 93#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
94 ({ \
95 int _ret; \
96 if (_on) \
97 _ret = ufshcd_enable_vreg(_dev, _vreg); \
98 else \
99 _ret = ufshcd_disable_vreg(_dev, _vreg); \
100 _ret; \
101 })
102
ba80917d
TW		 103#define ufshcd_hex_dump(prefix_str, buf, len) do { \
104 size_t __len = (len); \
105 print_hex_dump(KERN_ERR, prefix_str, \
106 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
107 16, 4, buf, __len, false); \
108} while (0)
109
110int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
111 const char *prefix)
112{
113 u8 *regs;
114
115 regs = kzalloc(len, GFP_KERNEL);
116 if (!regs)
117 return -ENOMEM;
118
119 memcpy_fromio(regs, hba->mmio_base + offset, len);
120 ufshcd_hex_dump(prefix, regs, len);
121 kfree(regs);
122
123 return 0;
124}
125EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 126
7a3e97b0
SY		 127enum {
128 UFSHCD_MAX_CHANNEL = 0,
129 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 130 UFSHCD_CMD_PER_LUN = 32,
131 UFSHCD_CAN_QUEUE = 32,
132};
133
134/* UFSHCD states */
135enum {
7a3e97b0
SY		 136 UFSHCD_STATE_RESET,
137 UFSHCD_STATE_ERROR,
3441da7d 138 UFSHCD_STATE_OPERATIONAL,
141f8165 139 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 140};
141
142/* UFSHCD error handling flags */
143enum {
144 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 145};
146
e8e7f271
SRT		 147/* UFSHCD UIC layer error flags */
148enum {
149 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 150 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
151 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
152 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
153 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
154 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 155};
156
3441da7d 157#define ufshcd_set_eh_in_progress(h) \
9c490d2d 158 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 159#define ufshcd_eh_in_progress(h) \
9c490d2d 160 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 161#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 162 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 163
57d104c1
SJ		 164#define ufshcd_set_ufs_dev_active(h) \
165 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
166#define ufshcd_set_ufs_dev_sleep(h) \
167 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
168#define ufshcd_set_ufs_dev_poweroff(h) \
169 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
170#define ufshcd_is_ufs_dev_active(h) \
171 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
172#define ufshcd_is_ufs_dev_sleep(h) \
173 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
174#define ufshcd_is_ufs_dev_poweroff(h) \
175 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
176
cbb6813e 177struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 178 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
179 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
180 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
181 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
182 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
183 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
184};
185
186static inline enum ufs_dev_pwr_mode
187ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
188{
189 return ufs_pm_lvl_states[lvl].dev_state;
190}
191
192static inline enum uic_link_state
193ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
194{
195 return ufs_pm_lvl_states[lvl].link_state;
196}
197
0c8f7586 198static inline enum ufs_pm_level
199ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
200 enum uic_link_state link_state)
201{
202 enum ufs_pm_level lvl;
203
204 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
205 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
206 (ufs_pm_lvl_states[lvl].link_state == link_state))
207 return lvl;
208 }
209
210 /* if no match found, return the level 0 */
211 return UFS_PM_LVL_0;
212}
213
56d4a186
SJ		 214static struct ufs_dev_fix ufs_fixups[] = {
215 /* UFS cards deviations table */
216 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
217 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
218 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
219 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
220 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
221 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
222 UFS_DEVICE_NO_FASTAUTO),
223 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
224 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
225 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
226 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
227 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
228 UFS_DEVICE_QUIRK_PA_TACTIVATE),
229 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
230 UFS_DEVICE_QUIRK_PA_TACTIVATE),
231 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
232 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
233 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
234
235 END_FIX
236};
237
3441da7d
SRT		 238static void ufshcd_tmc_handler(struct ufs_hba *hba);
239static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 240static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 241static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 242static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 243static void ufshcd_hba_exit(struct ufs_hba *hba);
244static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 245static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
246 bool skip_ref_clk);
247static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 248static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 249static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
250static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 251static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 252static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 253static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
254static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 255static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 256static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 257static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 258static int ufshcd_change_power_mode(struct ufs_hba *hba,
259 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 260static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
261{
262 return tag >= 0 && tag < hba->nutrs;
263}
57d104c1
SJ		 264
265static inline int ufshcd_enable_irq(struct ufs_hba *hba)
266{
267 int ret = 0;
268
269 if (!hba->is_irq_enabled) {
270 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
271 hba);
272 if (ret)
273 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
274 __func__, ret);
275 hba->is_irq_enabled = true;
276 }
277
278 return ret;
279}
280
281static inline void ufshcd_disable_irq(struct ufs_hba *hba)
282{
283 if (hba->is_irq_enabled) {
284 free_irq(hba->irq, hba);
285 hba->is_irq_enabled = false;
286 }
287}
3441da7d 288
38135535
SJ		 289static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
290{
291 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
292 scsi_unblock_requests(hba->host);
293}
294
295static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
296{
297 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
298 scsi_block_requests(hba->host);
299}
300
b573d484
YG		 301/* replace non-printable or non-ASCII characters with spaces */
302static inline void ufshcd_remove_non_printable(char *val)
303{
304 if (!val)
305 return;
306
307 if (*val < 0x20 || *val > 0x7e)
308 *val = ' ';
309}
310
6667e6d9
OS		 311static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
312 const char *str)
313{
314 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
315
316 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
317}
318
319static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
320 const char *str)
321{
322 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
323
324 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
325}
326
327static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
328 const char *str)
329{
6667e6d9 330 int off = (int)tag - hba->nutrs;
391e388f 331 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 332
391e388f
CH		 333 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
334 &descp->input_param1);
6667e6d9
OS		 335}
336
1a07f2d9
LS		 337static void ufshcd_add_command_trace(struct ufs_hba *hba,
338 unsigned int tag, const char *str)
339{
340 sector_t lba = -1;
341 u8 opcode = 0;
342 u32 intr, doorbell;
e7c3b379 343 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
1a07f2d9
LS		 344 int transfer_len = -1;
345
e7c3b379
OS		 346 if (!trace_ufshcd_command_enabled()) {
347 /* trace UPIU W/O tracing command */
348 if (lrbp->cmd)
349 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 350 return;
e7c3b379 351 }
1a07f2d9
LS		 352
353 if (lrbp->cmd) { /* data phase exists */
e7c3b379
OS		 354 /* trace UPIU also */
355 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9
LS		 356 opcode = (u8)(*lrbp->cmd->cmnd);
357 if ((opcode == READ_10) || (opcode == WRITE_10)) {
358 /*
359 * Currently we only fully trace read(10) and write(10)
360 * commands
361 */
362 if (lrbp->cmd->request && lrbp->cmd->request->bio)
363 lba =
364 lrbp->cmd->request->bio->bi_iter.bi_sector;
365 transfer_len = be32_to_cpu(
366 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
367 }
368 }
369
370 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
371 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
372 trace_ufshcd_command(dev_name(hba->dev), str, tag,
373 doorbell, transfer_len, intr, lba, opcode);
374}
375
ff8e20c6
DR		 376static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
377{
378 struct ufs_clk_info *clki;
379 struct list_head *head = &hba->clk_list_head;
380
566ec9ad 381 if (list_empty(head))
ff8e20c6
DR		 382 return;
383
384 list_for_each_entry(clki, head, list) {
385 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
386 clki->max_freq)
387 dev_err(hba->dev, "clk: %s, rate: %u\n",
388 clki->name, clki->curr_freq);
389 }
390}
391
392static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
393 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
394{
395 int i;
396
397 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
398 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
399
400 if (err_hist->reg[p] == 0)
401 continue;
402 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
403 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
404 }
405}
406
66cc820f
DR		 407static void ufshcd_print_host_regs(struct ufs_hba *hba)
408{
ba80917d 409 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 410 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
411 hba->ufs_version, hba->capabilities);
412 dev_err(hba->dev,
413 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
414 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 415 dev_err(hba->dev,
416 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
417 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
418 hba->ufs_stats.hibern8_exit_cnt);
419
420 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
421 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
422 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
423 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
424 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
425
426 ufshcd_print_clk_freqs(hba);
427
428 if (hba->vops && hba->vops->dbg_register_dump)
429 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 430}
431
432static
433void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
434{
435 struct ufshcd_lrb *lrbp;
7fabb77b 436 int prdt_length;
66cc820f
DR		 437 int tag;
438
439 for_each_set_bit(tag, &bitmap, hba->nutrs) {
440 lrbp = &hba->lrb[tag];
441
ff8e20c6
DR		 442 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
443 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 444 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
445 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 446 dev_err(hba->dev,
447 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
448 tag, (u64)lrbp->utrd_dma_addr);
449
66cc820f
DR		 450 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
451 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 452 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
453 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 454 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
455 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 456 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
457 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 458 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
459 sizeof(struct utp_upiu_rsp));
66cc820f 460
7fabb77b
GB		 461 prdt_length = le16_to_cpu(
462 lrbp->utr_descriptor_ptr->prd_table_length);
463 dev_err(hba->dev,
464 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
465 tag, prdt_length,
466 (u64)lrbp->ucd_prdt_dma_addr);
467
468 if (pr_prdt)
66cc820f 469 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 470 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 471 }
472}
473
474static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
475{
66cc820f
DR		 476 int tag;
477
478 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 479 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
480
66cc820f 481 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 482 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 483 }
484}
485
6ba65588
GB		 486static void ufshcd_print_host_state(struct ufs_hba *hba)
487{
488 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
489 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 490 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 491 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
492 hba->saved_err, hba->saved_uic_err);
493 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
494 hba->curr_dev_pwr_mode, hba->uic_link_state);
495 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
496 hba->pm_op_in_progress, hba->is_sys_suspended);
497 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
498 hba->auto_bkops_enabled, hba->host->host_self_blocked);
499 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
500 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
501 hba->eh_flags, hba->req_abort_count);
502 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
503 hba->capabilities, hba->caps);
504 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
505 hba->dev_quirks);
506}
507
ff8e20c6
DR		 508/**
509 * ufshcd_print_pwr_info - print power params as saved in hba
510 * power info
511 * @hba: per-adapter instance
512 */
513static void ufshcd_print_pwr_info(struct ufs_hba *hba)
514{
515 static const char * const names[] = {
516 "INVALID MODE",
517 "FAST MODE",
518 "SLOW_MODE",
519 "INVALID MODE",
520 "FASTAUTO_MODE",
521 "SLOWAUTO_MODE",
522 "INVALID MODE",
523 };
524
525 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
526 __func__,
527 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
528 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
529 names[hba->pwr_info.pwr_rx],
530 names[hba->pwr_info.pwr_tx],
531 hba->pwr_info.hs_rate);
532}
533
5a0b0cb9
SRT		 534/*
535 * ufshcd_wait_for_register - wait for register value to change
536 * @hba - per-adapter interface
537 * @reg - mmio register offset
538 * @mask - mask to apply to read register value
539 * @val - wait condition
540 * @interval_us - polling interval in microsecs
541 * @timeout_ms - timeout in millisecs
596585a2 542 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 543 *
544 * Returns -ETIMEDOUT on error, zero on success
545 */
596585a2
YG		 546int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
547 u32 val, unsigned long interval_us,
548 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 549{
550 int err = 0;
551 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
552
553 /* ignore bits that we don't intend to wait on */
554 val = val & mask;
555
556 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 557 if (can_sleep)
558 usleep_range(interval_us, interval_us + 50);
559 else
560 udelay(interval_us);
5a0b0cb9
SRT		 561 if (time_after(jiffies, timeout)) {
562 if ((ufshcd_readl(hba, reg) & mask) != val)
563 err = -ETIMEDOUT;
564 break;
565 }
566 }
567
568 return err;
569}
570
2fbd009b
SJ		 571/**
572 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 573 * @hba: Pointer to adapter instance
2fbd009b
SJ		 574 *
575 * Returns interrupt bit mask per version
576 */
577static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
578{
c01848c6
YG		 579 u32 intr_mask = 0;
580
581 switch (hba->ufs_version) {
582 case UFSHCI_VERSION_10:
583 intr_mask = INTERRUPT_MASK_ALL_VER_10;
584 break;
c01848c6
YG		 585 case UFSHCI_VERSION_11:
586 case UFSHCI_VERSION_20:
587 intr_mask = INTERRUPT_MASK_ALL_VER_11;
588 break;
c01848c6
YG		 589 case UFSHCI_VERSION_21:
590 default:
591 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 592 break;
c01848c6
YG		 593 }
594
595 return intr_mask;
2fbd009b
SJ		 596}
597
7a3e97b0
SY		 598/**
599 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 600 * @hba: Pointer to adapter instance
7a3e97b0
SY		 601 *
602 * Returns UFSHCI version supported by the controller
603 */
604static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
605{
0263bcd0
YG		 606 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
607 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 608
b873a275 609 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 610}
611
612/**
613 * ufshcd_is_device_present - Check if any device connected to
614 * the host controller
5c0c28a8 615 * @hba: pointer to adapter instance
7a3e97b0 616 *
c9e6010b 617 * Returns true if device present, false if no device detected
7a3e97b0 618 */
c9e6010b 619static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 620{
5c0c28a8 621 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 622 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 623}
624
625/**
626 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 627 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 628 *
629 * This function is used to get the OCS field from UTRD
630 * Returns the OCS field in the UTRD
631 */
632static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
633{
e8c8e82a 634 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 635}
636
7a3e97b0
SY		 637/**
638 * ufshcd_get_tm_free_slot - get a free slot for task management request
639 * @hba: per adapter instance
e2933132 640 * @free_slot: pointer to variable with available slot value
7a3e97b0 641 *
e2933132
SRT		 642 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
643 * Returns 0 if free slot is not available, else return 1 with tag value
644 * in @free_slot.
7a3e97b0 645 */
e2933132 646static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 647{
e2933132
SRT		 648 int tag;
649 bool ret = false;
650
651 if (!free_slot)
652 goto out;
653
654 do {
655 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
656 if (tag >= hba->nutmrs)
657 goto out;
658 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
659
660 *free_slot = tag;
661 ret = true;
662out:
663 return ret;
664}
665
666static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
667{
668 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 669}
670
671/**
672 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
673 * @hba: per adapter instance
674 * @pos: position of the bit to be cleared
675 */
676static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
677{
1399c5b0
AA		 678 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
679 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
680 else
681 ufshcd_writel(hba, ~(1 << pos),
682 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
683}
684
685/**
686 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
687 * @hba: per adapter instance
688 * @pos: position of the bit to be cleared
689 */
690static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
691{
692 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
693 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
694 else
695 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 696}
697
a48353f6
YG		 698/**
699 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
700 * @hba: per adapter instance
701 * @tag: position of the bit to be cleared
702 */
703static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
704{
705 __clear_bit(tag, &hba->outstanding_reqs);
706}
707
7a3e97b0
SY		 708/**
709 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
710 * @reg: Register value of host controller status
711 *
712 * Returns integer, 0 on Success and positive value if failed
713 */
714static inline int ufshcd_get_lists_status(u32 reg)
715{
6cf16115 716 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 717}
718
719/**
720 * ufshcd_get_uic_cmd_result - Get the UIC command result
721 * @hba: Pointer to adapter instance
722 *
723 * This function gets the result of UIC command completion
724 * Returns 0 on success, non zero value on error
725 */
726static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
727{
b873a275 728 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 729 MASK_UIC_COMMAND_RESULT;
730}
731
12b4fdb4
SJ		 732/**
733 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
734 * @hba: Pointer to adapter instance
735 *
736 * This function gets UIC command argument3
737 * Returns 0 on success, non zero value on error
738 */
739static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
740{
741 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
742}
743
7a3e97b0 744/**
5a0b0cb9 745 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 746 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 747 */
748static inline int
5a0b0cb9 749ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 750{
5a0b0cb9 751 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 752}
753
754/**
755 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
756 * @ucd_rsp_ptr: pointer to response UPIU
757 *
758 * This function gets the response status and scsi_status from response UPIU
759 * Returns the response result code.
760 */
761static inline int
762ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
763{
764 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
765}
766
1c2623c5
SJ		 767/*
768 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
769 * from response UPIU
770 * @ucd_rsp_ptr: pointer to response UPIU
771 *
772 * Return the data segment length.
773 */
774static inline unsigned int
775ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
776{
777 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
778 MASK_RSP_UPIU_DATA_SEG_LEN;
779}
780
66ec6d59
SRT		 781/**
782 * ufshcd_is_exception_event - Check if the device raised an exception event
783 * @ucd_rsp_ptr: pointer to response UPIU
784 *
785 * The function checks if the device raised an exception event indicated in
786 * the Device Information field of response UPIU.
787 *
788 * Returns true if exception is raised, false otherwise.
789 */
790static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
791{
792 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
793 MASK_RSP_EXCEPTION_EVENT ? true : false;
794}
795
7a3e97b0 796/**
7d568652 797 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 798 * @hba: per adapter instance
7a3e97b0
SY		 799 */
800static inline void
7d568652 801ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 802{
7d568652
SJ		 803 ufshcd_writel(hba, INT_AGGR_ENABLE |
804 INT_AGGR_COUNTER_AND_TIMER_RESET,
805 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
806}
807
808/**
809 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
810 * @hba: per adapter instance
811 * @cnt: Interrupt aggregation counter threshold
812 * @tmout: Interrupt aggregation timeout value
813 */
814static inline void
815ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
816{
817 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
818 INT_AGGR_COUNTER_THLD_VAL(cnt) |
819 INT_AGGR_TIMEOUT_VAL(tmout),
820 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 821}
822
b852190e
YG		 823/**
824 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
825 * @hba: per adapter instance
826 */
827static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
828{
829 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
830}
831
7a3e97b0
SY		 832/**
833 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
834 * When run-stop registers are set to 1, it indicates the
835 * host controller that it can process the requests
836 * @hba: per adapter instance
837 */
838static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
839{
b873a275
SJ		 840 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
841 REG_UTP_TASK_REQ_LIST_RUN_STOP);
842 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
843 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 844}
845
7a3e97b0
SY		 846/**
847 * ufshcd_hba_start - Start controller initialization sequence
848 * @hba: per adapter instance
849 */
850static inline void ufshcd_hba_start(struct ufs_hba *hba)
851{
b873a275 852 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 853}
854
855/**
856 * ufshcd_is_hba_active - Get controller state
857 * @hba: per adapter instance
858 *
c9e6010b 859 * Returns false if controller is active, true otherwise
7a3e97b0 860 */
c9e6010b 861static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 862{
4a8eec2b
TK		 863 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
864 ? false : true;
7a3e97b0
SY		 865}
866
37113106
YG		 867u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
868{
869 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
870 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
871 (hba->ufs_version == UFSHCI_VERSION_11))
872 return UFS_UNIPRO_VER_1_41;
873 else
874 return UFS_UNIPRO_VER_1_6;
875}
876EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
877
878static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
879{
880 /*
881 * If both host and device support UniPro ver1.6 or later, PA layer
882 * parameters tuning happens during link startup itself.
883 *
884 * We can manually tune PA layer parameters if either host or device
885 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
886 * logic simple, we will only do manual tuning if local unipro version
887 * doesn't support ver1.6 or later.
888 */
889 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
890 return true;
891 else
892 return false;
893}
894
a3cd5ec5 895static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
896{
897 int ret = 0;
898 struct ufs_clk_info *clki;
899 struct list_head *head = &hba->clk_list_head;
900 ktime_t start = ktime_get();
901 bool clk_state_changed = false;
902
566ec9ad 903 if (list_empty(head))
a3cd5ec5 904 goto out;
905
906 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
907 if (ret)
908 return ret;
909
910 list_for_each_entry(clki, head, list) {
911 if (!IS_ERR_OR_NULL(clki->clk)) {
912 if (scale_up && clki->max_freq) {
913 if (clki->curr_freq == clki->max_freq)
914 continue;
915
916 clk_state_changed = true;
917 ret = clk_set_rate(clki->clk, clki->max_freq);
918 if (ret) {
919 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
920 __func__, clki->name,
921 clki->max_freq, ret);
922 break;
923 }
924 trace_ufshcd_clk_scaling(dev_name(hba->dev),
925 "scaled up", clki->name,
926 clki->curr_freq,
927 clki->max_freq);
928
929 clki->curr_freq = clki->max_freq;
930
931 } else if (!scale_up && clki->min_freq) {
932 if (clki->curr_freq == clki->min_freq)
933 continue;
934
935 clk_state_changed = true;
936 ret = clk_set_rate(clki->clk, clki->min_freq);
937 if (ret) {
938 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
939 __func__, clki->name,
940 clki->min_freq, ret);
941 break;
942 }
943 trace_ufshcd_clk_scaling(dev_name(hba->dev),
944 "scaled down", clki->name,
945 clki->curr_freq,
946 clki->min_freq);
947 clki->curr_freq = clki->min_freq;
948 }
949 }
950 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
951 clki->name, clk_get_rate(clki->clk));
952 }
953
954 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
955
956out:
957 if (clk_state_changed)
958 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
959 (scale_up ? "up" : "down"),
960 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
961 return ret;
962}
963
964/**
965 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
966 * @hba: per adapter instance
967 * @scale_up: True if scaling up and false if scaling down
968 *
969 * Returns true if scaling is required, false otherwise.
970 */
971static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
972 bool scale_up)
973{
974 struct ufs_clk_info *clki;
975 struct list_head *head = &hba->clk_list_head;
976
566ec9ad 977 if (list_empty(head))
a3cd5ec5 978 return false;
979
980 list_for_each_entry(clki, head, list) {
981 if (!IS_ERR_OR_NULL(clki->clk)) {
982 if (scale_up && clki->max_freq) {
983 if (clki->curr_freq == clki->max_freq)
984 continue;
985 return true;
986 } else if (!scale_up && clki->min_freq) {
987 if (clki->curr_freq == clki->min_freq)
988 continue;
989 return true;
990 }
991 }
992 }
993
994 return false;
995}
996
997static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
998 u64 wait_timeout_us)
999{
1000 unsigned long flags;
1001 int ret = 0;
1002 u32 tm_doorbell;
1003 u32 tr_doorbell;
1004 bool timeout = false, do_last_check = false;
1005 ktime_t start;
1006
1007 ufshcd_hold(hba, false);
1008 spin_lock_irqsave(hba->host->host_lock, flags);
1009 /*
1010 * Wait for all the outstanding tasks/transfer requests.
1011 * Verify by checking the doorbell registers are clear.
1012 */
1013 start = ktime_get();
1014 do {
1015 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1016 ret = -EBUSY;
1017 goto out;
1018 }
1019
1020 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1021 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1022 if (!tm_doorbell && !tr_doorbell) {
1023 timeout = false;
1024 break;
1025 } else if (do_last_check) {
1026 break;
1027 }
1028
1029 spin_unlock_irqrestore(hba->host->host_lock, flags);
1030 schedule();
1031 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1032 wait_timeout_us) {
1033 timeout = true;
1034 /*
1035 * We might have scheduled out for long time so make
1036 * sure to check if doorbells are cleared by this time
1037 * or not.
1038 */
1039 do_last_check = true;
1040 }
1041 spin_lock_irqsave(hba->host->host_lock, flags);
1042 } while (tm_doorbell || tr_doorbell);
1043
1044 if (timeout) {
1045 dev_err(hba->dev,
1046 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1047 __func__, tm_doorbell, tr_doorbell);
1048 ret = -EBUSY;
1049 }
1050out:
1051 spin_unlock_irqrestore(hba->host->host_lock, flags);
1052 ufshcd_release(hba);
1053 return ret;
1054}
1055
1056/**
1057 * ufshcd_scale_gear - scale up/down UFS gear
1058 * @hba: per adapter instance
1059 * @scale_up: True for scaling up gear and false for scaling down
1060 *
1061 * Returns 0 for success,
1062 * Returns -EBUSY if scaling can't happen at this time
1063 * Returns non-zero for any other errors
1064 */
1065static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1066{
1067 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1068 int ret = 0;
1069 struct ufs_pa_layer_attr new_pwr_info;
1070
1071 if (scale_up) {
1072 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1073 sizeof(struct ufs_pa_layer_attr));
1074 } else {
1075 memcpy(&new_pwr_info, &hba->pwr_info,
1076 sizeof(struct ufs_pa_layer_attr));
1077
1078 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1079 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1080 /* save the current power mode */
1081 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1082 &hba->pwr_info,
1083 sizeof(struct ufs_pa_layer_attr));
1084
1085 /* scale down gear */
1086 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1087 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1088 }
1089 }
1090
1091 /* check if the power mode needs to be changed or not? */
1092 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1093
1094 if (ret)
1095 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1096 __func__, ret,
1097 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1098 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1099
1100 return ret;
1101}
1102
1103static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1104{
1105 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1106 int ret = 0;
1107 /*
1108 * make sure that there are no outstanding requests when
1109 * clock scaling is in progress
1110 */
38135535 1111 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1112 down_write(&hba->clk_scaling_lock);
1113 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1114 ret = -EBUSY;
1115 up_write(&hba->clk_scaling_lock);
38135535 1116 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1117 }
1118
1119 return ret;
1120}
1121
1122static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1123{
1124 up_write(&hba->clk_scaling_lock);
38135535 1125 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1126}
1127
1128/**
1129 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1130 * @hba: per adapter instance
1131 * @scale_up: True for scaling up and false for scalin down
1132 *
1133 * Returns 0 for success,
1134 * Returns -EBUSY if scaling can't happen at this time
1135 * Returns non-zero for any other errors
1136 */
1137static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1138{
1139 int ret = 0;
1140
401f1e44 1141 /* let's not get into low power until clock scaling is completed */
1142 ufshcd_hold(hba, false);
1143
a3cd5ec5 1144 ret = ufshcd_clock_scaling_prepare(hba);
1145 if (ret)
1146 return ret;
1147
1148 /* scale down the gear before scaling down clocks */
1149 if (!scale_up) {
1150 ret = ufshcd_scale_gear(hba, false);
1151 if (ret)
1152 goto out;
1153 }
1154
1155 ret = ufshcd_scale_clks(hba, scale_up);
1156 if (ret) {
1157 if (!scale_up)
1158 ufshcd_scale_gear(hba, true);
1159 goto out;
1160 }
1161
1162 /* scale up the gear after scaling up clocks */
1163 if (scale_up) {
1164 ret = ufshcd_scale_gear(hba, true);
1165 if (ret) {
1166 ufshcd_scale_clks(hba, false);
1167 goto out;
1168 }
1169 }
1170
1171 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1172
1173out:
1174 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1175 ufshcd_release(hba);
a3cd5ec5 1176 return ret;
1177}
1178
401f1e44 1179static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1180{
1181 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1182 clk_scaling.suspend_work);
1183 unsigned long irq_flags;
1184
1185 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1186 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1187 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1188 return;
1189 }
1190 hba->clk_scaling.is_suspended = true;
1191 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1192
1193 __ufshcd_suspend_clkscaling(hba);
1194}
1195
1196static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1197{
1198 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1199 clk_scaling.resume_work);
1200 unsigned long irq_flags;
1201
1202 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1203 if (!hba->clk_scaling.is_suspended) {
1204 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1205 return;
1206 }
1207 hba->clk_scaling.is_suspended = false;
1208 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1209
1210 devfreq_resume_device(hba->devfreq);
1211}
1212
a3cd5ec5 1213static int ufshcd_devfreq_target(struct device *dev,
1214 unsigned long *freq, u32 flags)
1215{
1216 int ret = 0;
1217 struct ufs_hba *hba = dev_get_drvdata(dev);
1218 ktime_t start;
401f1e44 1219 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1220 struct list_head *clk_list = &hba->clk_list_head;
1221 struct ufs_clk_info *clki;
a3cd5ec5 1222 unsigned long irq_flags;
1223
1224 if (!ufshcd_is_clkscaling_supported(hba))
1225 return -EINVAL;
1226
a3cd5ec5 1227 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1228 if (ufshcd_eh_in_progress(hba)) {
1229 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1230 return 0;
1231 }
1232
401f1e44 1233 if (!hba->clk_scaling.active_reqs)
1234 sched_clk_scaling_suspend_work = true;
1235
092b4558
BA		 1236 if (list_empty(clk_list)) {
1237 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1238 goto out;
1239 }
1240
1241 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1242 scale_up = (*freq == clki->max_freq) ? true : false;
401f1e44 1243 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1244 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1245 ret = 0;
1246 goto out; /* no state change required */
a3cd5ec5 1247 }
1248 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1249
1250 start = ktime_get();
a3cd5ec5 1251 ret = ufshcd_devfreq_scale(hba, scale_up);
1252
a3cd5ec5 1253 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1254 (scale_up ? "up" : "down"),
1255 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1256
401f1e44 1257out:
1258 if (sched_clk_scaling_suspend_work)
1259 queue_work(hba->clk_scaling.workq,
1260 &hba->clk_scaling.suspend_work);
1261
a3cd5ec5 1262 return ret;
1263}
1264
1265
1266static int ufshcd_devfreq_get_dev_status(struct device *dev,
1267 struct devfreq_dev_status *stat)
1268{
1269 struct ufs_hba *hba = dev_get_drvdata(dev);
1270 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1271 unsigned long flags;
1272
1273 if (!ufshcd_is_clkscaling_supported(hba))
1274 return -EINVAL;
1275
1276 memset(stat, 0, sizeof(*stat));
1277
1278 spin_lock_irqsave(hba->host->host_lock, flags);
1279 if (!scaling->window_start_t)
1280 goto start_window;
1281
1282 if (scaling->is_busy_started)
1283 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1284 scaling->busy_start_t));
1285
1286 stat->total_time = jiffies_to_usecs((long)jiffies -
1287 (long)scaling->window_start_t);
1288 stat->busy_time = scaling->tot_busy_t;
1289start_window:
1290 scaling->window_start_t = jiffies;
1291 scaling->tot_busy_t = 0;
1292
1293 if (hba->outstanding_reqs) {
1294 scaling->busy_start_t = ktime_get();
1295 scaling->is_busy_started = true;
1296 } else {
1297 scaling->busy_start_t = 0;
1298 scaling->is_busy_started = false;
1299 }
1300 spin_unlock_irqrestore(hba->host->host_lock, flags);
1301 return 0;
1302}
1303
1304static struct devfreq_dev_profile ufs_devfreq_profile = {
1305 .polling_ms = 100,
1306 .target = ufshcd_devfreq_target,
1307 .get_dev_status = ufshcd_devfreq_get_dev_status,
1308};
1309
deac444f
BA		 1310static int ufshcd_devfreq_init(struct ufs_hba *hba)
1311{
092b4558
BA		 1312 struct list_head *clk_list = &hba->clk_list_head;
1313 struct ufs_clk_info *clki;
deac444f
BA		 1314 struct devfreq *devfreq;
1315 int ret;
1316
092b4558
BA		 1317 /* Skip devfreq if we don't have any clocks in the list */
1318 if (list_empty(clk_list))
1319 return 0;
1320
1321 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1322 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1323 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1324
1325 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1326 &ufs_devfreq_profile,
1327 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1328 NULL);
1329 if (IS_ERR(devfreq)) {
1330 ret = PTR_ERR(devfreq);
1331 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1332
1333 dev_pm_opp_remove(hba->dev, clki->min_freq);
1334 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1335 return ret;
1336 }
1337
1338 hba->devfreq = devfreq;
1339
1340 return 0;
1341}
1342
092b4558
BA		 1343static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1344{
1345 struct list_head *clk_list = &hba->clk_list_head;
1346 struct ufs_clk_info *clki;
1347
1348 if (!hba->devfreq)
1349 return;
1350
1351 devfreq_remove_device(hba->devfreq);
1352 hba->devfreq = NULL;
1353
1354 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1355 dev_pm_opp_remove(hba->dev, clki->min_freq);
1356 dev_pm_opp_remove(hba->dev, clki->max_freq);
1357}
1358
401f1e44 1359static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1360{
1361 unsigned long flags;
1362
1363 devfreq_suspend_device(hba->devfreq);
1364 spin_lock_irqsave(hba->host->host_lock, flags);
1365 hba->clk_scaling.window_start_t = 0;
1366 spin_unlock_irqrestore(hba->host->host_lock, flags);
1367}
a3cd5ec5 1368
a508253d
GB		 1369static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1370{
401f1e44 1371 unsigned long flags;
1372 bool suspend = false;
1373
fcb0c4b0
ST		 1374 if (!ufshcd_is_clkscaling_supported(hba))
1375 return;
1376
401f1e44 1377 spin_lock_irqsave(hba->host->host_lock, flags);
1378 if (!hba->clk_scaling.is_suspended) {
1379 suspend = true;
1380 hba->clk_scaling.is_suspended = true;
1381 }
1382 spin_unlock_irqrestore(hba->host->host_lock, flags);
1383
1384 if (suspend)
1385 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1386}
1387
1388static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1389{
401f1e44 1390 unsigned long flags;
1391 bool resume = false;
1392
1393 if (!ufshcd_is_clkscaling_supported(hba))
1394 return;
1395
1396 spin_lock_irqsave(hba->host->host_lock, flags);
1397 if (hba->clk_scaling.is_suspended) {
1398 resume = true;
1399 hba->clk_scaling.is_suspended = false;
1400 }
1401 spin_unlock_irqrestore(hba->host->host_lock, flags);
1402
1403 if (resume)
1404 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1405}
1406
1407static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1408 struct device_attribute *attr, char *buf)
1409{
1410 struct ufs_hba *hba = dev_get_drvdata(dev);
1411
1412 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1413}
1414
1415static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1416 struct device_attribute *attr, const char *buf, size_t count)
1417{
1418 struct ufs_hba *hba = dev_get_drvdata(dev);
1419 u32 value;
1420 int err;
1421
1422 if (kstrtou32(buf, 0, &value))
1423 return -EINVAL;
1424
1425 value = !!value;
1426 if (value == hba->clk_scaling.is_allowed)
1427 goto out;
1428
1429 pm_runtime_get_sync(hba->dev);
1430 ufshcd_hold(hba, false);
1431
401f1e44 1432 cancel_work_sync(&hba->clk_scaling.suspend_work);
1433 cancel_work_sync(&hba->clk_scaling.resume_work);
1434
1435 hba->clk_scaling.is_allowed = value;
1436
fcb0c4b0
ST		 1437 if (value) {
1438 ufshcd_resume_clkscaling(hba);
1439 } else {
1440 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1441 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1442 if (err)
1443 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1444 __func__, err);
1445 }
fcb0c4b0
ST		 1446
1447 ufshcd_release(hba);
1448 pm_runtime_put_sync(hba->dev);
1449out:
1450 return count;
a508253d
GB		 1451}
1452
a3cd5ec5 1453static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1454{
1455 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1456 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1457 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1458 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1459 hba->clk_scaling.enable_attr.attr.mode = 0644;
1460 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1461 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1462}
1463
1ab27c9c
ST		 1464static void ufshcd_ungate_work(struct work_struct *work)
1465{
1466 int ret;
1467 unsigned long flags;
1468 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1469 clk_gating.ungate_work);
1470
1471 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1472
1473 spin_lock_irqsave(hba->host->host_lock, flags);
1474 if (hba->clk_gating.state == CLKS_ON) {
1475 spin_unlock_irqrestore(hba->host->host_lock, flags);
1476 goto unblock_reqs;
1477 }
1478
1479 spin_unlock_irqrestore(hba->host->host_lock, flags);
1480 ufshcd_setup_clocks(hba, true);
1481
1482 /* Exit from hibern8 */
1483 if (ufshcd_can_hibern8_during_gating(hba)) {
1484 /* Prevent gating in this path */
1485 hba->clk_gating.is_suspended = true;
1486 if (ufshcd_is_link_hibern8(hba)) {
1487 ret = ufshcd_uic_hibern8_exit(hba);
1488 if (ret)
1489 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1490 __func__, ret);
1491 else
1492 ufshcd_set_link_active(hba);
1493 }
1494 hba->clk_gating.is_suspended = false;
1495 }
1496unblock_reqs:
38135535 1497 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1498}
1499
1500/**
1501 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1502 * Also, exit from hibern8 mode and set the link as active.
1503 * @hba: per adapter instance
1504 * @async: This indicates whether caller should ungate clocks asynchronously.
1505 */
1506int ufshcd_hold(struct ufs_hba *hba, bool async)
1507{
1508 int rc = 0;
1509 unsigned long flags;
1510
1511 if (!ufshcd_is_clkgating_allowed(hba))
1512 goto out;
1ab27c9c
ST		 1513 spin_lock_irqsave(hba->host->host_lock, flags);
1514 hba->clk_gating.active_reqs++;
1515
53c12d0e
YG		 1516 if (ufshcd_eh_in_progress(hba)) {
1517 spin_unlock_irqrestore(hba->host->host_lock, flags);
1518 return 0;
1519 }
1520
856b3483 1521start:
1ab27c9c
ST		 1522 switch (hba->clk_gating.state) {
1523 case CLKS_ON:
f2a785ac
VG		 1524 /*
1525 * Wait for the ungate work to complete if in progress.
1526 * Though the clocks may be in ON state, the link could
1527 * still be in hibner8 state if hibern8 is allowed
1528 * during clock gating.
1529 * Make sure we exit hibern8 state also in addition to
1530 * clocks being ON.
1531 */
1532 if (ufshcd_can_hibern8_during_gating(hba) &&
1533 ufshcd_is_link_hibern8(hba)) {
1534 spin_unlock_irqrestore(hba->host->host_lock, flags);
1535 flush_work(&hba->clk_gating.ungate_work);
1536 spin_lock_irqsave(hba->host->host_lock, flags);
1537 goto start;
1538 }
1ab27c9c
ST		 1539 break;
1540 case REQ_CLKS_OFF:
1541 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1542 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1543 trace_ufshcd_clk_gating(dev_name(hba->dev),
1544 hba->clk_gating.state);
1ab27c9c
ST		 1545 break;
1546 }
1547 /*
9c490d2d 1548 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1549 * currently running. Hence, fall through to cancel gating
1550 * work and to enable clocks.
1551 */
1552 case CLKS_OFF:
38135535 1553 ufshcd_scsi_block_requests(hba);
1ab27c9c 1554 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1555 trace_ufshcd_clk_gating(dev_name(hba->dev),
1556 hba->clk_gating.state);
10e5e375
VV		 1557 queue_work(hba->clk_gating.clk_gating_workq,
1558 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1559 /*
1560 * fall through to check if we should wait for this
1561 * work to be done or not.
1562 */
1563 case REQ_CLKS_ON:
1564 if (async) {
1565 rc = -EAGAIN;
1566 hba->clk_gating.active_reqs--;
1567 break;
1568 }
1569
1570 spin_unlock_irqrestore(hba->host->host_lock, flags);
1571 flush_work(&hba->clk_gating.ungate_work);
1572 /* Make sure state is CLKS_ON before returning */
856b3483 1573 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1574 goto start;
1575 default:
1576 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1577 __func__, hba->clk_gating.state);
1578 break;
1579 }
1580 spin_unlock_irqrestore(hba->host->host_lock, flags);
1581out:
1582 return rc;
1583}
6e3fd44d 1584EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1585
1586static void ufshcd_gate_work(struct work_struct *work)
1587{
1588 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1589 clk_gating.gate_work.work);
1590 unsigned long flags;
1591
1592 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1593 /*
1594 * In case you are here to cancel this work the gating state
1595 * would be marked as REQ_CLKS_ON. In this case save time by
1596 * skipping the gating work and exit after changing the clock
1597 * state to CLKS_ON.
1598 */
1599 if (hba->clk_gating.is_suspended ||
1600 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1601 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1602 trace_ufshcd_clk_gating(dev_name(hba->dev),
1603 hba->clk_gating.state);
1ab27c9c
ST		 1604 goto rel_lock;
1605 }
1606
1607 if (hba->clk_gating.active_reqs
1608 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1609 || hba->lrb_in_use || hba->outstanding_tasks
1610 || hba->active_uic_cmd || hba->uic_async_done)
1611 goto rel_lock;
1612
1613 spin_unlock_irqrestore(hba->host->host_lock, flags);
1614
1615 /* put the link into hibern8 mode before turning off clocks */
1616 if (ufshcd_can_hibern8_during_gating(hba)) {
1617 if (ufshcd_uic_hibern8_enter(hba)) {
1618 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1619 trace_ufshcd_clk_gating(dev_name(hba->dev),
1620 hba->clk_gating.state);
1ab27c9c
ST		 1621 goto out;
1622 }
1623 ufshcd_set_link_hibern8(hba);
1624 }
1625
1626 if (!ufshcd_is_link_active(hba))
1627 ufshcd_setup_clocks(hba, false);
1628 else
1629 /* If link is active, device ref_clk can't be switched off */
1630 __ufshcd_setup_clocks(hba, false, true);
1631
1632 /*
1633 * In case you are here to cancel this work the gating state
1634 * would be marked as REQ_CLKS_ON. In this case keep the state
1635 * as REQ_CLKS_ON which would anyway imply that clocks are off
1636 * and a request to turn them on is pending. By doing this way,
1637 * we keep the state machine in tact and this would ultimately
1638 * prevent from doing cancel work multiple times when there are
1639 * new requests arriving before the current cancel work is done.
1640 */
1641 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1642 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1643 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1644 trace_ufshcd_clk_gating(dev_name(hba->dev),
1645 hba->clk_gating.state);
1646 }
1ab27c9c
ST		 1647rel_lock:
1648 spin_unlock_irqrestore(hba->host->host_lock, flags);
1649out:
1650 return;
1651}
1652
1653/* host lock must be held before calling this variant */
1654static void __ufshcd_release(struct ufs_hba *hba)
1655{
1656 if (!ufshcd_is_clkgating_allowed(hba))
1657 return;
1658
1659 hba->clk_gating.active_reqs--;
1660
1661 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1662 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1663 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1664 || hba->active_uic_cmd || hba->uic_async_done
1665 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1666 return;
1667
1668 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1669 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1670 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1671 &hba->clk_gating.gate_work,
1672 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1673}
1674
1675void ufshcd_release(struct ufs_hba *hba)
1676{
1677 unsigned long flags;
1678
1679 spin_lock_irqsave(hba->host->host_lock, flags);
1680 __ufshcd_release(hba);
1681 spin_unlock_irqrestore(hba->host->host_lock, flags);
1682}
6e3fd44d 1683EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1684
1685static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1686 struct device_attribute *attr, char *buf)
1687{
1688 struct ufs_hba *hba = dev_get_drvdata(dev);
1689
1690 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1691}
1692
1693static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1694 struct device_attribute *attr, const char *buf, size_t count)
1695{
1696 struct ufs_hba *hba = dev_get_drvdata(dev);
1697 unsigned long flags, value;
1698
1699 if (kstrtoul(buf, 0, &value))
1700 return -EINVAL;
1701
1702 spin_lock_irqsave(hba->host->host_lock, flags);
1703 hba->clk_gating.delay_ms = value;
1704 spin_unlock_irqrestore(hba->host->host_lock, flags);
1705 return count;
1706}
1707
b427411a
ST		 1708static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1709 struct device_attribute *attr, char *buf)
1710{
1711 struct ufs_hba *hba = dev_get_drvdata(dev);
1712
1713 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1714}
1715
1716static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1717 struct device_attribute *attr, const char *buf, size_t count)
1718{
1719 struct ufs_hba *hba = dev_get_drvdata(dev);
1720 unsigned long flags;
1721 u32 value;
1722
1723 if (kstrtou32(buf, 0, &value))
1724 return -EINVAL;
1725
1726 value = !!value;
1727 if (value == hba->clk_gating.is_enabled)
1728 goto out;
1729
1730 if (value) {
1731 ufshcd_release(hba);
1732 } else {
1733 spin_lock_irqsave(hba->host->host_lock, flags);
1734 hba->clk_gating.active_reqs++;
1735 spin_unlock_irqrestore(hba->host->host_lock, flags);
1736 }
1737
1738 hba->clk_gating.is_enabled = value;
1739out:
1740 return count;
1741}
1742
eebcc196
VG		 1743static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1744{
1745 char wq_name[sizeof("ufs_clkscaling_00")];
1746
1747 if (!ufshcd_is_clkscaling_supported(hba))
1748 return;
1749
1750 INIT_WORK(&hba->clk_scaling.suspend_work,
1751 ufshcd_clk_scaling_suspend_work);
1752 INIT_WORK(&hba->clk_scaling.resume_work,
1753 ufshcd_clk_scaling_resume_work);
1754
1755 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1756 hba->host->host_no);
1757 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1758
1759 ufshcd_clkscaling_init_sysfs(hba);
1760}
1761
1762static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1763{
1764 if (!ufshcd_is_clkscaling_supported(hba))
1765 return;
1766
1767 destroy_workqueue(hba->clk_scaling.workq);
1768 ufshcd_devfreq_remove(hba);
1769}
1770
1ab27c9c
ST		 1771static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1772{
10e5e375
VV		 1773 char wq_name[sizeof("ufs_clk_gating_00")];
1774
1ab27c9c
ST		 1775 if (!ufshcd_is_clkgating_allowed(hba))
1776 return;
1777
1778 hba->clk_gating.delay_ms = 150;
1779 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1780 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1781
10e5e375
VV		 1782 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1783 hba->host->host_no);
1784 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1785 WQ_MEM_RECLAIM);
1786
b427411a
ST		 1787 hba->clk_gating.is_enabled = true;
1788
1ab27c9c
ST		 1789 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1790 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1791 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1792 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1793 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1794 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1795 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1796
1797 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1798 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1799 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1800 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1801 hba->clk_gating.enable_attr.attr.mode = 0644;
1802 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1803 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1804}
1805
1806static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1807{
1808 if (!ufshcd_is_clkgating_allowed(hba))
1809 return;
1810 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1811 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1812 cancel_work_sync(&hba->clk_gating.ungate_work);
1813 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1814 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1815}
1816
856b3483
ST		 1817/* Must be called with host lock acquired */
1818static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1819{
401f1e44 1820 bool queue_resume_work = false;
1821
fcb0c4b0 1822 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1823 return;
1824
401f1e44 1825 if (!hba->clk_scaling.active_reqs++)
1826 queue_resume_work = true;
1827
1828 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1829 return;
1830
1831 if (queue_resume_work)
1832 queue_work(hba->clk_scaling.workq,
1833 &hba->clk_scaling.resume_work);
1834
1835 if (!hba->clk_scaling.window_start_t) {
1836 hba->clk_scaling.window_start_t = jiffies;
1837 hba->clk_scaling.tot_busy_t = 0;
1838 hba->clk_scaling.is_busy_started = false;
1839 }
1840
856b3483
ST		 1841 if (!hba->clk_scaling.is_busy_started) {
1842 hba->clk_scaling.busy_start_t = ktime_get();
1843 hba->clk_scaling.is_busy_started = true;
1844 }
1845}
1846
1847static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1848{
1849 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1850
fcb0c4b0 1851 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1852 return;
1853
1854 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1855 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1856 scaling->busy_start_t));
8b0e1953 1857 scaling->busy_start_t = 0;
856b3483
ST		 1858 scaling->is_busy_started = false;
1859 }
1860}
7a3e97b0
SY		 1861/**
1862 * ufshcd_send_command - Send SCSI or device management commands
1863 * @hba: per adapter instance
1864 * @task_tag: Task tag of the command
1865 */
1866static inline
1867void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1868{
ff8e20c6 1869 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1870 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
856b3483 1871 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1872 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1873 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1874 /* Make sure that doorbell is committed immediately */
1875 wmb();
1a07f2d9 1876 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1877}
1878
1879/**
1880 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1881 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1882 */
1883static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1884{
1885 int len;
1c2623c5
SJ		 1886 if (lrbp->sense_buffer &&
1887 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1888 int len_to_copy;
1889
5a0b0cb9 1890 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1891 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1892
7a3e97b0 1893 memcpy(lrbp->sense_buffer,
5a0b0cb9 1894 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1895 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1896 }
1897}
1898
68078d5c
DR		 1899/**
1900 * ufshcd_copy_query_response() - Copy the Query Response and the data
1901 * descriptor
1902 * @hba: per adapter instance
8aa29f19 1903 * @lrbp: pointer to local reference block
68078d5c
DR		 1904 */
1905static
c6d4a831 1906int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1907{
1908 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1909
68078d5c 1910 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1911
68078d5c
DR		 1912 /* Get the descriptor */
1913 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1914 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1915 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1916 u16 resp_len;
1917 u16 buf_len;
68078d5c
DR		 1918
1919 /* data segment length */
c6d4a831 1920 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1921 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1922 buf_len = be16_to_cpu(
1923 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1924 if (likely(buf_len >= resp_len)) {
1925 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1926 } else {
1927 dev_warn(hba->dev,
1928 "%s: Response size is bigger than buffer",
1929 __func__);
1930 return -EINVAL;
1931 }
68078d5c 1932 }
c6d4a831
DR		 1933
1934 return 0;
68078d5c
DR		 1935}
1936
7a3e97b0
SY		 1937/**
1938 * ufshcd_hba_capabilities - Read controller capabilities
1939 * @hba: per adapter instance
1940 */
1941static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1942{
b873a275 1943 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1944
1945 /* nutrs and nutmrs are 0 based values */
1946 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1947 hba->nutmrs =
1948 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1949}
1950
1951/**
6ccf44fe
SJ		 1952 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1953 * to accept UIC commands
7a3e97b0 1954 * @hba: per adapter instance
6ccf44fe
SJ		 1955 * Return true on success, else false
1956 */
1957static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1958{
1959 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1960 return true;
1961 else
1962 return false;
1963}
1964
53b3d9c3
SJ		 1965/**
1966 * ufshcd_get_upmcrs - Get the power mode change request status
1967 * @hba: Pointer to adapter instance
1968 *
1969 * This function gets the UPMCRS field of HCS register
1970 * Returns value of UPMCRS field
1971 */
1972static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1973{
1974 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1975}
1976
6ccf44fe
SJ		 1977/**
1978 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1979 * @hba: per adapter instance
1980 * @uic_cmd: UIC command
1981 *
1982 * Mutex must be held.
7a3e97b0
SY		 1983 */
1984static inline void
6ccf44fe 1985ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1986{
6ccf44fe
SJ		 1987 WARN_ON(hba->active_uic_cmd);
1988
1989 hba->active_uic_cmd = uic_cmd;
1990
7a3e97b0 1991 /* Write Args */
6ccf44fe
SJ		 1992 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1993 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1994 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1995
1996 /* Write UIC Cmd */
6ccf44fe 1997 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1998 REG_UIC_COMMAND);
7a3e97b0
SY		 1999}
2000
6ccf44fe
SJ		 2001/**
2002 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2003 * @hba: per adapter instance
8aa29f19 2004 * @uic_cmd: UIC command
6ccf44fe
SJ		 2005 *
2006 * Must be called with mutex held.
2007 * Returns 0 only if success.
2008 */
2009static int
2010ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2011{
2012 int ret;
2013 unsigned long flags;
2014
2015 if (wait_for_completion_timeout(&uic_cmd->done,
2016 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2017 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2018 else
2019 ret = -ETIMEDOUT;
2020
2021 spin_lock_irqsave(hba->host->host_lock, flags);
2022 hba->active_uic_cmd = NULL;
2023 spin_unlock_irqrestore(hba->host->host_lock, flags);
2024
2025 return ret;
2026}
2027
2028/**
2029 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2030 * @hba: per adapter instance
2031 * @uic_cmd: UIC command
d75f7fe4 2032 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2033 *
2034 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2035 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2036 * Returns 0 only if success.
2037 */
2038static int
d75f7fe4
YG		 2039__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2040 bool completion)
6ccf44fe 2041{
6ccf44fe
SJ		 2042 if (!ufshcd_ready_for_uic_cmd(hba)) {
2043 dev_err(hba->dev,
2044 "Controller not ready to accept UIC commands\n");
2045 return -EIO;
2046 }
2047
d75f7fe4
YG		 2048 if (completion)
2049 init_completion(&uic_cmd->done);
6ccf44fe 2050
6ccf44fe 2051 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2052
57d104c1 2053 return 0;
6ccf44fe
SJ		 2054}
2055
2056/**
2057 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2058 * @hba: per adapter instance
2059 * @uic_cmd: UIC command
2060 *
2061 * Returns 0 only if success.
2062 */
e77044c5 2063int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2064{
2065 int ret;
57d104c1 2066 unsigned long flags;
6ccf44fe 2067
1ab27c9c 2068 ufshcd_hold(hba, false);
6ccf44fe 2069 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2070 ufshcd_add_delay_before_dme_cmd(hba);
2071
57d104c1 2072 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2073 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2074 spin_unlock_irqrestore(hba->host->host_lock, flags);
2075 if (!ret)
2076 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2077
6ccf44fe
SJ		 2078 mutex_unlock(&hba->uic_cmd_mutex);
2079
1ab27c9c 2080 ufshcd_release(hba);
6ccf44fe
SJ		 2081 return ret;
2082}
2083
7a3e97b0
SY		 2084/**
2085 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2086 * @hba: per adapter instance
2087 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2088 *
2089 * Returns 0 in case of success, non-zero value in case of failure
2090 */
75b1cc4a 2091static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2092{
2093 struct ufshcd_sg_entry *prd_table;
2094 struct scatterlist *sg;
2095 struct scsi_cmnd *cmd;
2096 int sg_segments;
2097 int i;
2098
2099 cmd = lrbp->cmd;
2100 sg_segments = scsi_dma_map(cmd);
2101 if (sg_segments < 0)
2102 return sg_segments;
2103
2104 if (sg_segments) {
75b1cc4a
KK		 2105 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2106 lrbp->utr_descriptor_ptr->prd_table_length =
2107 cpu_to_le16((u16)(sg_segments *
2108 sizeof(struct ufshcd_sg_entry)));
2109 else
2110 lrbp->utr_descriptor_ptr->prd_table_length =
2111 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2112
2113 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2114
2115 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2116 prd_table[i].size =
2117 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2118 prd_table[i].base_addr =
2119 cpu_to_le32(lower_32_bits(sg->dma_address));
2120 prd_table[i].upper_addr =
2121 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2122 prd_table[i].reserved = 0;
7a3e97b0
SY		 2123 }
2124 } else {
2125 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2126 }
2127
2128 return 0;
2129}
2130
2131/**
2fbd009b 2132 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2133 * @hba: per adapter instance
2fbd009b 2134 * @intrs: interrupt bits
7a3e97b0 2135 */
2fbd009b 2136static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2137{
2fbd009b
SJ		 2138 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2139
2140 if (hba->ufs_version == UFSHCI_VERSION_10) {
2141 u32 rw;
2142 rw = set & INTERRUPT_MASK_RW_VER_10;
2143 set = rw | ((set ^ intrs) & intrs);
2144 } else {
2145 set |= intrs;
2146 }
2147
2148 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2149}
2150
2151/**
2152 * ufshcd_disable_intr - disable interrupts
2153 * @hba: per adapter instance
2154 * @intrs: interrupt bits
2155 */
2156static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2157{
2158 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2159
2160 if (hba->ufs_version == UFSHCI_VERSION_10) {
2161 u32 rw;
2162 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2163 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2164 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2165
2166 } else {
2167 set &= ~intrs;
7a3e97b0 2168 }
2fbd009b
SJ		 2169
2170 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2171}
2172
5a0b0cb9
SRT		 2173/**
2174 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2175 * descriptor according to request
2176 * @lrbp: pointer to local reference block
2177 * @upiu_flags: flags required in the header
2178 * @cmd_dir: requests data direction
2179 */
2180static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2181 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2182{
2183 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2184 u32 data_direction;
2185 u32 dword_0;
2186
2187 if (cmd_dir == DMA_FROM_DEVICE) {
2188 data_direction = UTP_DEVICE_TO_HOST;
2189 *upiu_flags = UPIU_CMD_FLAGS_READ;
2190 } else if (cmd_dir == DMA_TO_DEVICE) {
2191 data_direction = UTP_HOST_TO_DEVICE;
2192 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2193 } else {
2194 data_direction = UTP_NO_DATA_TRANSFER;
2195 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2196 }
2197
2198 dword_0 = data_direction | (lrbp->command_type
2199 << UPIU_COMMAND_TYPE_OFFSET);
2200 if (lrbp->intr_cmd)
2201 dword_0 |= UTP_REQ_DESC_INT_CMD;
2202
2203 /* Transfer request descriptor header fields */
2204 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2205 /* dword_1 is reserved, hence it is set to 0 */
2206 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2207 /*
2208 * assigning invalid value for command status. Controller
2209 * updates OCS on command completion, with the command
2210 * status
2211 */
2212 req_desc->header.dword_2 =
2213 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2214 /* dword_3 is reserved, hence it is set to 0 */
2215 req_desc->header.dword_3 = 0;
51047266
YG		 2216
2217 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2218}
2219
2220/**
2221 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2222 * for scsi commands
8aa29f19
BVA		 2223 * @lrbp: local reference block pointer
2224 * @upiu_flags: flags
5a0b0cb9
SRT		 2225 */
2226static
2227void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2228{
2229 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2230 unsigned short cdb_len;
5a0b0cb9
SRT		 2231
2232 /* command descriptor fields */
2233 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2234 UPIU_TRANSACTION_COMMAND, upiu_flags,
2235 lrbp->lun, lrbp->task_tag);
2236 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2237 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2238
2239 /* Total EHS length and Data segment length will be zero */
2240 ucd_req_ptr->header.dword_2 = 0;
2241
2242 ucd_req_ptr->sc.exp_data_transfer_len =
2243 cpu_to_be32(lrbp->cmd->sdb.length);
2244
a851b2bd
AA		 2245 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, UFS_CDB_SIZE);
2246 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
52ac95fe
YG		 2247 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2248
2249 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2250}
2251
68078d5c
DR		 2252/**
2253 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2254 * for query requsts
2255 * @hba: UFS hba
2256 * @lrbp: local reference block pointer
2257 * @upiu_flags: flags
2258 */
2259static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2260 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2261{
2262 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2263 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2264 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2265
2266 /* Query request header */
2267 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2268 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2269 lrbp->lun, lrbp->task_tag);
2270 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2271 0, query->request.query_func, 0, 0);
2272
6861285c
ZL		 2273 /* Data segment length only need for WRITE_DESC */
2274 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2275 ucd_req_ptr->header.dword_2 =
2276 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2277 else
2278 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2279
2280 /* Copy the Query Request buffer as is */
2281 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2282 QUERY_OSF_SIZE);
68078d5c
DR		 2283
2284 /* Copy the Descriptor */
c6d4a831 2285 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2286 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2287
51047266 2288 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2289}
2290
5a0b0cb9
SRT		 2291static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2292{
2293 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2294
2295 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2296
2297 /* command descriptor fields */
2298 ucd_req_ptr->header.dword_0 =
2299 UPIU_HEADER_DWORD(
2300 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2301 /* clear rest of the fields of basic header */
2302 ucd_req_ptr->header.dword_1 = 0;
2303 ucd_req_ptr->header.dword_2 = 0;
2304
2305 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2306}
2307
7a3e97b0 2308/**
300bb13f
JP		 2309 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2310 * for Device Management Purposes
8aa29f19
BVA		 2311 * @hba: per adapter instance
2312 * @lrbp: pointer to local reference block
7a3e97b0 2313 */
300bb13f 2314static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2315{
7a3e97b0 2316 u32 upiu_flags;
5a0b0cb9 2317 int ret = 0;
7a3e97b0 2318
83dc7e3d 2319 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2320 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2321 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2322 else
2323 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2324
2325 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2326 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2327 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2328 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2329 ufshcd_prepare_utp_nop_upiu(lrbp);
2330 else
2331 ret = -EINVAL;
2332
2333 return ret;
2334}
2335
2336/**
2337 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2338 * for SCSI Purposes
8aa29f19
BVA		 2339 * @hba: per adapter instance
2340 * @lrbp: pointer to local reference block
300bb13f
JP		 2341 */
2342static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2343{
2344 u32 upiu_flags;
2345 int ret = 0;
2346
83dc7e3d 2347 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2348 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2349 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2350 else
2351 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2352
2353 if (likely(lrbp->cmd)) {
2354 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2355 lrbp->cmd->sc_data_direction);
2356 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2357 } else {
2358 ret = -EINVAL;
2359 }
5a0b0cb9
SRT		 2360
2361 return ret;
7a3e97b0
SY		 2362}
2363
2a8fa600
SJ		 2364/**
2365 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2366 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2367 *
2368 * Returns SCSI W-LUN id
2369 */
2370static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2371{
2372 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2373}
2374
7a3e97b0
SY		 2375/**
2376 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2377 * @host: SCSI host pointer
7a3e97b0 2378 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2379 *
2380 * Returns 0 for success, non-zero in case of failure
2381 */
2382static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2383{
2384 struct ufshcd_lrb *lrbp;
2385 struct ufs_hba *hba;
2386 unsigned long flags;
2387 int tag;
2388 int err = 0;
2389
2390 hba = shost_priv(host);
2391
2392 tag = cmd->request->tag;
14497328
YG		 2393 if (!ufshcd_valid_tag(hba, tag)) {
2394 dev_err(hba->dev,
2395 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2396 __func__, tag, cmd, cmd->request);
2397 BUG();
2398 }
7a3e97b0 2399
a3cd5ec5 2400 if (!down_read_trylock(&hba->clk_scaling_lock))
2401 return SCSI_MLQUEUE_HOST_BUSY;
2402
3441da7d
SRT		 2403 spin_lock_irqsave(hba->host->host_lock, flags);
2404 switch (hba->ufshcd_state) {
2405 case UFSHCD_STATE_OPERATIONAL:
2406 break;
141f8165 2407 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2408 case UFSHCD_STATE_RESET:
7a3e97b0 2409 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2410 goto out_unlock;
2411 case UFSHCD_STATE_ERROR:
2412 set_host_byte(cmd, DID_ERROR);
2413 cmd->scsi_done(cmd);
2414 goto out_unlock;
2415 default:
2416 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2417 __func__, hba->ufshcd_state);
2418 set_host_byte(cmd, DID_BAD_TARGET);
2419 cmd->scsi_done(cmd);
2420 goto out_unlock;
7a3e97b0 2421 }
53c12d0e
YG		 2422
2423 /* if error handling is in progress, don't issue commands */
2424 if (ufshcd_eh_in_progress(hba)) {
2425 set_host_byte(cmd, DID_ERROR);
2426 cmd->scsi_done(cmd);
2427 goto out_unlock;
2428 }
3441da7d 2429 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2430
7fabb77b
GB		 2431 hba->req_abort_count = 0;
2432
5a0b0cb9
SRT		 2433 /* acquire the tag to make sure device cmds don't use it */
2434 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2435 /*
2436 * Dev manage command in progress, requeue the command.
2437 * Requeuing the command helps in cases where the request *may*
2438 * find different tag instead of waiting for dev manage command
2439 * completion.
2440 */
2441 err = SCSI_MLQUEUE_HOST_BUSY;
2442 goto out;
2443 }
2444
1ab27c9c
ST		 2445 err = ufshcd_hold(hba, true);
2446 if (err) {
2447 err = SCSI_MLQUEUE_HOST_BUSY;
2448 clear_bit_unlock(tag, &hba->lrb_in_use);
2449 goto out;
2450 }
2451 WARN_ON(hba->clk_gating.state != CLKS_ON);
2452
7a3e97b0
SY		 2453 lrbp = &hba->lrb[tag];
2454
5a0b0cb9 2455 WARN_ON(lrbp->cmd);
7a3e97b0 2456 lrbp->cmd = cmd;
dcea0bfb 2457 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2458 lrbp->sense_buffer = cmd->sense_buffer;
2459 lrbp->task_tag = tag;
0ce147d4 2460 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2461 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2462 lrbp->req_abort_skip = false;
7a3e97b0 2463
300bb13f
JP		 2464 ufshcd_comp_scsi_upiu(hba, lrbp);
2465
75b1cc4a 2466 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2467 if (err) {
2468 lrbp->cmd = NULL;
2469 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2470 goto out;
5a0b0cb9 2471 }
ad1a1b9c
GB		 2472 /* Make sure descriptors are ready before ringing the doorbell */
2473 wmb();
7a3e97b0
SY		 2474
2475 /* issue command to the controller */
2476 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2477 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2478 ufshcd_send_command(hba, tag);
3441da7d 2479out_unlock:
7a3e97b0
SY		 2480 spin_unlock_irqrestore(hba->host->host_lock, flags);
2481out:
a3cd5ec5 2482 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2483 return err;
2484}
2485
5a0b0cb9
SRT		 2486static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2487 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2488{
2489 lrbp->cmd = NULL;
2490 lrbp->sense_bufflen = 0;
2491 lrbp->sense_buffer = NULL;
2492 lrbp->task_tag = tag;
2493 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2494 lrbp->intr_cmd = true; /* No interrupt aggregation */
2495 hba->dev_cmd.type = cmd_type;
2496
300bb13f 2497 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2498}
2499
2500static int
2501ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2502{
2503 int err = 0;
2504 unsigned long flags;
2505 u32 mask = 1 << tag;
2506
2507 /* clear outstanding transaction before retry */
2508 spin_lock_irqsave(hba->host->host_lock, flags);
2509 ufshcd_utrl_clear(hba, tag);
2510 spin_unlock_irqrestore(hba->host->host_lock, flags);
2511
2512 /*
2513 * wait for for h/w to clear corresponding bit in door-bell.
2514 * max. wait is 1 sec.
2515 */
2516 err = ufshcd_wait_for_register(hba,
2517 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2518 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2519
2520 return err;
2521}
2522
c6d4a831
DR		 2523static int
2524ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2525{
2526 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2527
2528 /* Get the UPIU response */
2529 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2530 UPIU_RSP_CODE_OFFSET;
2531 return query_res->response;
2532}
2533
5a0b0cb9
SRT		 2534/**
2535 * ufshcd_dev_cmd_completion() - handles device management command responses
2536 * @hba: per adapter instance
2537 * @lrbp: pointer to local reference block
2538 */
2539static int
2540ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2541{
2542 int resp;
2543 int err = 0;
2544
ff8e20c6 2545 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2546 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2547
2548 switch (resp) {
2549 case UPIU_TRANSACTION_NOP_IN:
2550 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2551 err = -EINVAL;
2552 dev_err(hba->dev, "%s: unexpected response %x\n",
2553 __func__, resp);
2554 }
2555 break;
68078d5c 2556 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2557 err = ufshcd_check_query_response(hba, lrbp);
2558 if (!err)
2559 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2560 break;
5a0b0cb9
SRT		 2561 case UPIU_TRANSACTION_REJECT_UPIU:
2562 /* TODO: handle Reject UPIU Response */
2563 err = -EPERM;
2564 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2565 __func__);
2566 break;
2567 default:
2568 err = -EINVAL;
2569 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2570 __func__, resp);
2571 break;
2572 }
2573
2574 return err;
2575}
2576
2577static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2578 struct ufshcd_lrb *lrbp, int max_timeout)
2579{
2580 int err = 0;
2581 unsigned long time_left;
2582 unsigned long flags;
2583
2584 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2585 msecs_to_jiffies(max_timeout));
2586
ad1a1b9c
GB		 2587 /* Make sure descriptors are ready before ringing the doorbell */
2588 wmb();
5a0b0cb9
SRT		 2589 spin_lock_irqsave(hba->host->host_lock, flags);
2590 hba->dev_cmd.complete = NULL;
2591 if (likely(time_left)) {
2592 err = ufshcd_get_tr_ocs(lrbp);
2593 if (!err)
2594 err = ufshcd_dev_cmd_completion(hba, lrbp);
2595 }
2596 spin_unlock_irqrestore(hba->host->host_lock, flags);
2597
2598 if (!time_left) {
2599 err = -ETIMEDOUT;
a48353f6
YG		 2600 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2601 __func__, lrbp->task_tag);
5a0b0cb9 2602 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2603 /* successfully cleared the command, retry if needed */
5a0b0cb9 2604 err = -EAGAIN;
a48353f6
YG		 2605 /*
2606 * in case of an error, after clearing the doorbell,
2607 * we also need to clear the outstanding_request
2608 * field in hba
2609 */
2610 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2611 }
2612
2613 return err;
2614}
2615
2616/**
2617 * ufshcd_get_dev_cmd_tag - Get device management command tag
2618 * @hba: per-adapter instance
8aa29f19 2619 * @tag_out: pointer to variable with available slot value
5a0b0cb9
SRT		 2620 *
2621 * Get a free slot and lock it until device management command
2622 * completes.
2623 *
2624 * Returns false if free slot is unavailable for locking, else
2625 * return true with tag value in @tag.
2626 */
2627static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2628{
2629 int tag;
2630 bool ret = false;
2631 unsigned long tmp;
2632
2633 if (!tag_out)
2634 goto out;
2635
2636 do {
2637 tmp = ~hba->lrb_in_use;
2638 tag = find_last_bit(&tmp, hba->nutrs);
2639 if (tag >= hba->nutrs)
2640 goto out;
2641 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2642
2643 *tag_out = tag;
2644 ret = true;
2645out:
2646 return ret;
2647}
2648
2649static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2650{
2651 clear_bit_unlock(tag, &hba->lrb_in_use);
2652}
2653
2654/**
2655 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2656 * @hba: UFS hba
2657 * @cmd_type: specifies the type (NOP, Query...)
2658 * @timeout: time in seconds
5a0b0cb9 2659 *
68078d5c
DR		 2660 * NOTE: Since there is only one available tag for device management commands,
2661 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2662 */
2663static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2664 enum dev_cmd_type cmd_type, int timeout)
2665{
2666 struct ufshcd_lrb *lrbp;
2667 int err;
2668 int tag;
2669 struct completion wait;
2670 unsigned long flags;
2671
a3cd5ec5 2672 down_read(&hba->clk_scaling_lock);
2673
5a0b0cb9
SRT		 2674 /*
2675 * Get free slot, sleep if slots are unavailable.
2676 * Even though we use wait_event() which sleeps indefinitely,
2677 * the maximum wait time is bounded by SCSI request timeout.
2678 */
2679 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2680
2681 init_completion(&wait);
2682 lrbp = &hba->lrb[tag];
2683 WARN_ON(lrbp->cmd);
2684 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2685 if (unlikely(err))
2686 goto out_put_tag;
2687
2688 hba->dev_cmd.complete = &wait;
2689
6667e6d9 2690 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2691 /* Make sure descriptors are ready before ringing the doorbell */
2692 wmb();
5a0b0cb9 2693 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2694 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2695 ufshcd_send_command(hba, tag);
2696 spin_unlock_irqrestore(hba->host->host_lock, flags);
2697
2698 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2699
6667e6d9
OS		 2700 ufshcd_add_query_upiu_trace(hba, tag,
2701 err ? "query_complete_err" : "query_complete");
2702
5a0b0cb9
SRT		 2703out_put_tag:
2704 ufshcd_put_dev_cmd_tag(hba, tag);
2705 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2706 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2707 return err;
2708}
2709
d44a5f98
DR		 2710/**
2711 * ufshcd_init_query() - init the query response and request parameters
2712 * @hba: per-adapter instance
2713 * @request: address of the request pointer to be initialized
2714 * @response: address of the response pointer to be initialized
2715 * @opcode: operation to perform
2716 * @idn: flag idn to access
2717 * @index: LU number to access
2718 * @selector: query/flag/descriptor further identification
2719 */
2720static inline void ufshcd_init_query(struct ufs_hba *hba,
2721 struct ufs_query_req **request, struct ufs_query_res **response,
2722 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2723{
2724 *request = &hba->dev_cmd.query.request;
2725 *response = &hba->dev_cmd.query.response;
2726 memset(*request, 0, sizeof(struct ufs_query_req));
2727 memset(*response, 0, sizeof(struct ufs_query_res));
2728 (*request)->upiu_req.opcode = opcode;
2729 (*request)->upiu_req.idn = idn;
2730 (*request)->upiu_req.index = index;
2731 (*request)->upiu_req.selector = selector;
2732}
2733
dc3c8d3a
YG		 2734static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2735 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2736{
2737 int ret;
2738 int retries;
2739
2740 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2741 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2742 if (ret)
2743 dev_dbg(hba->dev,
2744 "%s: failed with error %d, retries %d\n",
2745 __func__, ret, retries);
2746 else
2747 break;
2748 }
2749
2750 if (ret)
2751 dev_err(hba->dev,
2752 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2753 __func__, opcode, idn, ret, retries);
2754 return ret;
2755}
2756
68078d5c
DR		 2757/**
2758 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2759 * @hba: per-adapter instance
2760 * @opcode: flag query to perform
2761 * @idn: flag idn to access
2762 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2763 *
2764 * Returns 0 for success, non-zero in case of failure
2765 */
dc3c8d3a 2766int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2767 enum flag_idn idn, bool *flag_res)
2768{
d44a5f98
DR		 2769 struct ufs_query_req *request = NULL;
2770 struct ufs_query_res *response = NULL;
2771 int err, index = 0, selector = 0;
e5ad406c 2772 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2773
2774 BUG_ON(!hba);
2775
1ab27c9c 2776 ufshcd_hold(hba, false);
68078d5c 2777 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2778 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2779 selector);
68078d5c
DR		 2780
2781 switch (opcode) {
2782 case UPIU_QUERY_OPCODE_SET_FLAG:
2783 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2784 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2785 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2786 break;
2787 case UPIU_QUERY_OPCODE_READ_FLAG:
2788 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2789 if (!flag_res) {
2790 /* No dummy reads */
2791 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2792 __func__);
2793 err = -EINVAL;
2794 goto out_unlock;
2795 }
2796 break;
2797 default:
2798 dev_err(hba->dev,
2799 "%s: Expected query flag opcode but got = %d\n",
2800 __func__, opcode);
2801 err = -EINVAL;
2802 goto out_unlock;
2803 }
68078d5c 2804
e5ad406c 2805 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2806
2807 if (err) {
2808 dev_err(hba->dev,
2809 "%s: Sending flag query for idn %d failed, err = %d\n",
2810 __func__, idn, err);
2811 goto out_unlock;
2812 }
2813
2814 if (flag_res)
e8c8e82a 2815 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2816 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2817
2818out_unlock:
2819 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2820 ufshcd_release(hba);
68078d5c
DR		 2821 return err;
2822}
2823
66ec6d59
SRT		 2824/**
2825 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2826 * @hba: per-adapter instance
2827 * @opcode: attribute opcode
2828 * @idn: attribute idn to access
2829 * @index: index field
2830 * @selector: selector field
2831 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2832 *
2833 * Returns 0 for success, non-zero in case of failure
2834*/
ec92b59c
SN		 2835int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2836 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2837{
d44a5f98
DR		 2838 struct ufs_query_req *request = NULL;
2839 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2840 int err;
2841
2842 BUG_ON(!hba);
2843
1ab27c9c 2844 ufshcd_hold(hba, false);
66ec6d59
SRT		 2845 if (!attr_val) {
2846 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2847 __func__, opcode);
2848 err = -EINVAL;
2849 goto out;
2850 }
2851
2852 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2853 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2854 selector);
66ec6d59
SRT		 2855
2856 switch (opcode) {
2857 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2858 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2859 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2860 break;
2861 case UPIU_QUERY_OPCODE_READ_ATTR:
2862 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2863 break;
2864 default:
2865 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2866 __func__, opcode);
2867 err = -EINVAL;
2868 goto out_unlock;
2869 }
2870
d44a5f98 2871 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2872
2873 if (err) {
4b761b58
YG		 2874 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2875 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2876 goto out_unlock;
2877 }
2878
e8c8e82a 2879 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2880
2881out_unlock:
2882 mutex_unlock(&hba->dev_cmd.lock);
2883out:
1ab27c9c 2884 ufshcd_release(hba);
66ec6d59
SRT		 2885 return err;
2886}
2887
5e86ae44
YG		 2888/**
2889 * ufshcd_query_attr_retry() - API function for sending query
2890 * attribute with retries
2891 * @hba: per-adapter instance
2892 * @opcode: attribute opcode
2893 * @idn: attribute idn to access
2894 * @index: index field
2895 * @selector: selector field
2896 * @attr_val: the attribute value after the query request
2897 * completes
2898 *
2899 * Returns 0 for success, non-zero in case of failure
2900*/
2901static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2902 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2903 u32 *attr_val)
2904{
2905 int ret = 0;
2906 u32 retries;
2907
2908 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2909 ret = ufshcd_query_attr(hba, opcode, idn, index,
2910 selector, attr_val);
2911 if (ret)
2912 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2913 __func__, ret, retries);
2914 else
2915 break;
2916 }
2917
2918 if (ret)
2919 dev_err(hba->dev,
2920 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2921 __func__, idn, ret, QUERY_REQ_RETRIES);
2922 return ret;
2923}
2924
a70e91b8 2925static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2926 enum query_opcode opcode, enum desc_idn idn, u8 index,
2927 u8 selector, u8 *desc_buf, int *buf_len)
2928{
2929 struct ufs_query_req *request = NULL;
2930 struct ufs_query_res *response = NULL;
2931 int err;
2932
2933 BUG_ON(!hba);
2934
1ab27c9c 2935 ufshcd_hold(hba, false);
d44a5f98
DR		 2936 if (!desc_buf) {
2937 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2938 __func__, opcode);
2939 err = -EINVAL;
2940 goto out;
2941 }
2942
a4b0e8a4 2943 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2944 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2945 __func__, *buf_len);
2946 err = -EINVAL;
2947 goto out;
2948 }
2949
2950 mutex_lock(&hba->dev_cmd.lock);
2951 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2952 selector);
2953 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2954 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2955
2956 switch (opcode) {
2957 case UPIU_QUERY_OPCODE_WRITE_DESC:
2958 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2959 break;
2960 case UPIU_QUERY_OPCODE_READ_DESC:
2961 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2962 break;
2963 default:
2964 dev_err(hba->dev,
2965 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2966 __func__, opcode);
2967 err = -EINVAL;
2968 goto out_unlock;
2969 }
2970
2971 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2972
2973 if (err) {
4b761b58
YG		 2974 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2975 __func__, opcode, idn, index, err);
d44a5f98
DR		 2976 goto out_unlock;
2977 }
2978
2979 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2980 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2981
2982out_unlock:
2983 mutex_unlock(&hba->dev_cmd.lock);
2984out:
1ab27c9c 2985 ufshcd_release(hba);
d44a5f98
DR		 2986 return err;
2987}
2988
a70e91b8 2989/**
8aa29f19
BVA		 2990 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2991 * @hba: per-adapter instance
2992 * @opcode: attribute opcode
2993 * @idn: attribute idn to access
2994 * @index: index field
2995 * @selector: selector field
2996 * @desc_buf: the buffer that contains the descriptor
2997 * @buf_len: length parameter passed to the device
a70e91b8
YG		 2998 *
2999 * Returns 0 for success, non-zero in case of failure.
3000 * The buf_len parameter will contain, on return, the length parameter
3001 * received on the response.
3002 */
2238d31c
SN		 3003int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3004 enum query_opcode opcode,
3005 enum desc_idn idn, u8 index,
3006 u8 selector,
3007 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3008{
3009 int err;
3010 int retries;
3011
3012 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3013 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3014 selector, desc_buf, buf_len);
3015 if (!err || err == -EINVAL)
3016 break;
3017 }
3018
3019 return err;
3020}
a70e91b8 3021
a4b0e8a4
PM		 3022/**
3023 * ufshcd_read_desc_length - read the specified descriptor length from header
3024 * @hba: Pointer to adapter instance
3025 * @desc_id: descriptor idn value
3026 * @desc_index: descriptor index
3027 * @desc_length: pointer to variable to read the length of descriptor
3028 *
3029 * Return 0 in case of success, non-zero otherwise
3030 */
3031static int ufshcd_read_desc_length(struct ufs_hba *hba,
3032 enum desc_idn desc_id,
3033 int desc_index,
3034 int *desc_length)
3035{
3036 int ret;
3037 u8 header[QUERY_DESC_HDR_SIZE];
3038 int header_len = QUERY_DESC_HDR_SIZE;
3039
3040 if (desc_id >= QUERY_DESC_IDN_MAX)
3041 return -EINVAL;
3042
3043 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3044 desc_id, desc_index, 0, header,
3045 &header_len);
3046
3047 if (ret) {
3048 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3049 __func__, desc_id);
3050 return ret;
3051 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3052 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3053 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3054 desc_id);
3055 ret = -EINVAL;
3056 }
3057
3058 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3059 return ret;
3060
3061}
3062
3063/**
3064 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3065 * @hba: Pointer to adapter instance
3066 * @desc_id: descriptor idn value
3067 * @desc_len: mapped desc length (out)
3068 *
3069 * Return 0 in case of success, non-zero otherwise
3070 */
3071int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3072 enum desc_idn desc_id, int *desc_len)
3073{
3074 switch (desc_id) {
3075 case QUERY_DESC_IDN_DEVICE:
3076 *desc_len = hba->desc_size.dev_desc;
3077 break;
3078 case QUERY_DESC_IDN_POWER:
3079 *desc_len = hba->desc_size.pwr_desc;
3080 break;
3081 case QUERY_DESC_IDN_GEOMETRY:
3082 *desc_len = hba->desc_size.geom_desc;
3083 break;
3084 case QUERY_DESC_IDN_CONFIGURATION:
3085 *desc_len = hba->desc_size.conf_desc;
3086 break;
3087 case QUERY_DESC_IDN_UNIT:
3088 *desc_len = hba->desc_size.unit_desc;
3089 break;
3090 case QUERY_DESC_IDN_INTERCONNECT:
3091 *desc_len = hba->desc_size.interc_desc;
3092 break;
3093 case QUERY_DESC_IDN_STRING:
3094 *desc_len = QUERY_DESC_MAX_SIZE;
3095 break;
c648c2d2
SN		 3096 case QUERY_DESC_IDN_HEALTH:
3097 *desc_len = hba->desc_size.hlth_desc;
3098 break;
a4b0e8a4
PM		 3099 case QUERY_DESC_IDN_RFU_0:
3100 case QUERY_DESC_IDN_RFU_1:
3101 *desc_len = 0;
3102 break;
3103 default:
3104 *desc_len = 0;
3105 return -EINVAL;
3106 }
3107 return 0;
3108}
3109EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3110
da461cec
SJ		 3111/**
3112 * ufshcd_read_desc_param - read the specified descriptor parameter
3113 * @hba: Pointer to adapter instance
3114 * @desc_id: descriptor idn value
3115 * @desc_index: descriptor index
3116 * @param_offset: offset of the parameter to read
3117 * @param_read_buf: pointer to buffer where parameter would be read
3118 * @param_size: sizeof(param_read_buf)
3119 *
3120 * Return 0 in case of success, non-zero otherwise
3121 */
45bced87
SN		 3122int ufshcd_read_desc_param(struct ufs_hba *hba,
3123 enum desc_idn desc_id,
3124 int desc_index,
3125 u8 param_offset,
3126 u8 *param_read_buf,
3127 u8 param_size)
da461cec
SJ		 3128{
3129 int ret;
3130 u8 *desc_buf;
a4b0e8a4 3131 int buff_len;
da461cec
SJ		 3132 bool is_kmalloc = true;
3133
a4b0e8a4
PM		 3134 /* Safety check */
3135 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3136 return -EINVAL;
3137
a4b0e8a4
PM		 3138 /* Get the max length of descriptor from structure filled up at probe
3139 * time.
3140 */
3141 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3142
a4b0e8a4
PM		 3143 /* Sanity checks */
3144 if (ret || !buff_len) {
3145 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3146 __func__);
3147 return ret;
3148 }
3149
3150 /* Check whether we need temp memory */
3151 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3152 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3153 if (!desc_buf)
3154 return -ENOMEM;
a4b0e8a4
PM		 3155 } else {
3156 desc_buf = param_read_buf;
3157 is_kmalloc = false;
da461cec
SJ		 3158 }
3159
a4b0e8a4 3160 /* Request for full descriptor */
a70e91b8 3161 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3162 desc_id, desc_index, 0,
3163 desc_buf, &buff_len);
da461cec 3164
bde44bb6 3165 if (ret) {
3166 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3167 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3168 goto out;
3169 }
3170
bde44bb6 3171 /* Sanity check */
3172 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3173 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3174 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3175 ret = -EINVAL;
3176 goto out;
3177 }
3178
a4b0e8a4
PM		 3179 /* Check wherher we will not copy more data, than available */
3180 if (is_kmalloc && param_size > buff_len)
3181 param_size = buff_len;
bde44bb6 3182
da461cec
SJ		 3183 if (is_kmalloc)
3184 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3185out:
3186 if (is_kmalloc)
3187 kfree(desc_buf);
3188 return ret;
3189}
3190
3191static inline int ufshcd_read_desc(struct ufs_hba *hba,
3192 enum desc_idn desc_id,
3193 int desc_index,
3194 u8 *buf,
3195 u32 size)
3196{
3197 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3198}
3199
3200static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3201 u8 *buf,
3202 u32 size)
3203{
dbd34a61 3204 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3205}
3206
8209b6d5 3207static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3208{
3209 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3210}
b573d484
YG		 3211
3212/**
3213 * ufshcd_read_string_desc - read string descriptor
3214 * @hba: pointer to adapter instance
3215 * @desc_index: descriptor index
3216 * @buf: pointer to buffer where descriptor would be read
3217 * @size: size of buf
3218 * @ascii: if true convert from unicode to ascii characters
3219 *
3220 * Return 0 in case of success, non-zero otherwise
3221 */
2238d31c
SN		 3222int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3223 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3224{
3225 int err = 0;
3226
3227 err = ufshcd_read_desc(hba,
3228 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3229
3230 if (err) {
3231 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3232 __func__, QUERY_REQ_RETRIES, err);
3233 goto out;
3234 }
3235
3236 if (ascii) {
3237 int desc_len;
3238 int ascii_len;
3239 int i;
3240 char *buff_ascii;
3241
3242 desc_len = buf[0];
3243 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3244 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3245 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3246 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3247 __func__);
3248 err = -ENOMEM;
3249 goto out;
3250 }
3251
3252 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3253 if (!buff_ascii) {
3254 err = -ENOMEM;
fcbefc3b 3255 goto out;
b573d484
YG		 3256 }
3257
3258 /*
3259 * the descriptor contains string in UTF16 format
3260 * we need to convert to utf-8 so it can be displayed
3261 */
3262 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3263 desc_len - QUERY_DESC_HDR_SIZE,
3264 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3265
3266 /* replace non-printable or non-ASCII characters with spaces */
3267 for (i = 0; i < ascii_len; i++)
3268 ufshcd_remove_non_printable(&buff_ascii[i]);
3269
3270 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3271 size - QUERY_DESC_HDR_SIZE);
3272 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3273 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3274 kfree(buff_ascii);
3275 }
3276out:
3277 return err;
3278}
b573d484 3279
da461cec
SJ		 3280/**
3281 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3282 * @hba: Pointer to adapter instance
3283 * @lun: lun id
3284 * @param_offset: offset of the parameter to read
3285 * @param_read_buf: pointer to buffer where parameter would be read
3286 * @param_size: sizeof(param_read_buf)
3287 *
3288 * Return 0 in case of success, non-zero otherwise
3289 */
3290static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3291 int lun,
3292 enum unit_desc_param param_offset,
3293 u8 *param_read_buf,
3294 u32 param_size)
3295{
3296 /*
3297 * Unit descriptors are only available for general purpose LUs (LUN id
3298 * from 0 to 7) and RPMB Well known LU.
3299 */
d829fc8a 3300 if (!ufs_is_valid_unit_desc_lun(lun))
da461cec
SJ		 3301 return -EOPNOTSUPP;
3302
3303 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3304 param_offset, param_read_buf, param_size);
3305}
3306
7a3e97b0
SY		 3307/**
3308 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3309 * @hba: per adapter instance
3310 *
3311 * 1. Allocate DMA memory for Command Descriptor array
3312 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3313 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3314 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3315 * (UTMRDL)
3316 * 4. Allocate memory for local reference block(lrb).
3317 *
3318 * Returns 0 for success, non-zero in case of failure
3319 */
3320static int ufshcd_memory_alloc(struct ufs_hba *hba)
3321{
3322 size_t utmrdl_size, utrdl_size, ucdl_size;
3323
3324 /* Allocate memory for UTP command descriptors */
3325 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3326 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3327 ucdl_size,
3328 &hba->ucdl_dma_addr,
3329 GFP_KERNEL);
7a3e97b0
SY		 3330
3331 /*
3332 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3333 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3334 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3335 * be aligned to 128 bytes as well
3336 */
3337 if (!hba->ucdl_base_addr ||
3338 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3339 dev_err(hba->dev,
7a3e97b0
SY		 3340 "Command Descriptor Memory allocation failed\n");
3341 goto out;
3342 }
3343
3344 /*
3345 * Allocate memory for UTP Transfer descriptors
3346 * UFSHCI requires 1024 byte alignment of UTRD
3347 */
3348 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3349 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3350 utrdl_size,
3351 &hba->utrdl_dma_addr,
3352 GFP_KERNEL);
7a3e97b0
SY		 3353 if (!hba->utrdl_base_addr ||
3354 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3355 dev_err(hba->dev,
7a3e97b0
SY		 3356 "Transfer Descriptor Memory allocation failed\n");
3357 goto out;
3358 }
3359
3360 /*
3361 * Allocate memory for UTP Task Management descriptors
3362 * UFSHCI requires 1024 byte alignment of UTMRD
3363 */
3364 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3365 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3366 utmrdl_size,
3367 &hba->utmrdl_dma_addr,
3368 GFP_KERNEL);
7a3e97b0
SY		 3369 if (!hba->utmrdl_base_addr ||
3370 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3371 dev_err(hba->dev,
7a3e97b0
SY		 3372 "Task Management Descriptor Memory allocation failed\n");
3373 goto out;
3374 }
3375
3376 /* Allocate memory for local reference block */
a86854d0
KC		 3377 hba->lrb = devm_kcalloc(hba->dev,
3378 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3379 GFP_KERNEL);
7a3e97b0 3380 if (!hba->lrb) {
3b1d0580 3381 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3382 goto out;
3383 }
3384 return 0;
3385out:
7a3e97b0
SY		 3386 return -ENOMEM;
3387}
3388
3389/**
3390 * ufshcd_host_memory_configure - configure local reference block with
3391 * memory offsets
3392 * @hba: per adapter instance
3393 *
3394 * Configure Host memory space
3395 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3396 * address.
3397 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3398 * and PRDT offset.
3399 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3400 * into local reference block.
3401 */
3402static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3403{
3404 struct utp_transfer_cmd_desc *cmd_descp;
3405 struct utp_transfer_req_desc *utrdlp;
3406 dma_addr_t cmd_desc_dma_addr;
3407 dma_addr_t cmd_desc_element_addr;
3408 u16 response_offset;
3409 u16 prdt_offset;
3410 int cmd_desc_size;
3411 int i;
3412
3413 utrdlp = hba->utrdl_base_addr;
3414 cmd_descp = hba->ucdl_base_addr;
3415
3416 response_offset =
3417 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3418 prdt_offset =
3419 offsetof(struct utp_transfer_cmd_desc, prd_table);
3420
3421 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3422 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3423
3424 for (i = 0; i < hba->nutrs; i++) {
3425 /* Configure UTRD with command descriptor base address */
3426 cmd_desc_element_addr =
3427 (cmd_desc_dma_addr + (cmd_desc_size * i));
3428 utrdlp[i].command_desc_base_addr_lo =
3429 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3430 utrdlp[i].command_desc_base_addr_hi =
3431 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3432
3433 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3434 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3435 utrdlp[i].response_upiu_offset =
3436 cpu_to_le16(response_offset);
3437 utrdlp[i].prd_table_offset =
3438 cpu_to_le16(prdt_offset);
3439 utrdlp[i].response_upiu_length =
3440 cpu_to_le16(ALIGNED_UPIU_SIZE);
3441 } else {
3442 utrdlp[i].response_upiu_offset =
7a3e97b0 3443 cpu_to_le16((response_offset >> 2));
75b1cc4a 3444 utrdlp[i].prd_table_offset =
7a3e97b0 3445 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3446 utrdlp[i].response_upiu_length =
3ca316c5 3447 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3448 }
7a3e97b0
SY		 3449
3450 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3451 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3452 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3453 hba->lrb[i].ucd_req_ptr =
3454 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3455 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3456 hba->lrb[i].ucd_rsp_ptr =
3457 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3458 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3459 response_offset;
7a3e97b0
SY		 3460 hba->lrb[i].ucd_prdt_ptr =
3461 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3462 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3463 prdt_offset;
7a3e97b0
SY		 3464 }
3465}
3466
3467/**
3468 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3469 * @hba: per adapter instance
3470 *
3471 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3472 * in order to initialize the Unipro link startup procedure.
3473 * Once the Unipro links are up, the device connected to the controller
3474 * is detected.
3475 *
3476 * Returns 0 on success, non-zero value on failure
3477 */
3478static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3479{
6ccf44fe
SJ		 3480 struct uic_command uic_cmd = {0};
3481 int ret;
7a3e97b0 3482
6ccf44fe 3483 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3484
6ccf44fe
SJ		 3485 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3486 if (ret)
ff8e20c6 3487 dev_dbg(hba->dev,
6ccf44fe
SJ		 3488 "dme-link-startup: error code %d\n", ret);
3489 return ret;
7a3e97b0 3490}
4404c5de
AA		 3491/**
3492 * ufshcd_dme_reset - UIC command for DME_RESET
3493 * @hba: per adapter instance
3494 *
3495 * DME_RESET command is issued in order to reset UniPro stack.
3496 * This function now deal with cold reset.
3497 *
3498 * Returns 0 on success, non-zero value on failure
3499 */
3500static int ufshcd_dme_reset(struct ufs_hba *hba)
3501{
3502 struct uic_command uic_cmd = {0};
3503 int ret;
3504
3505 uic_cmd.command = UIC_CMD_DME_RESET;
3506
3507 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3508 if (ret)
3509 dev_err(hba->dev,
3510 "dme-reset: error code %d\n", ret);
3511
3512 return ret;
3513}
3514
3515/**
3516 * ufshcd_dme_enable - UIC command for DME_ENABLE
3517 * @hba: per adapter instance
3518 *
3519 * DME_ENABLE command is issued in order to enable UniPro stack.
3520 *
3521 * Returns 0 on success, non-zero value on failure
3522 */
3523static int ufshcd_dme_enable(struct ufs_hba *hba)
3524{
3525 struct uic_command uic_cmd = {0};
3526 int ret;
3527
3528 uic_cmd.command = UIC_CMD_DME_ENABLE;
3529
3530 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3531 if (ret)
3532 dev_err(hba->dev,
3533 "dme-reset: error code %d\n", ret);
3534
3535 return ret;
3536}
7a3e97b0 3537
cad2e03d
YG		 3538static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3539{
3540 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3541 unsigned long min_sleep_time_us;
3542
3543 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3544 return;
3545
3546 /*
3547 * last_dme_cmd_tstamp will be 0 only for 1st call to
3548 * this function
3549 */
3550 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3551 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3552 } else {
3553 unsigned long delta =
3554 (unsigned long) ktime_to_us(
3555 ktime_sub(ktime_get(),
3556 hba->last_dme_cmd_tstamp));
3557
3558 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3559 min_sleep_time_us =
3560 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3561 else
3562 return; /* no more delay required */
3563 }
3564
3565 /* allow sleep for extra 50us if needed */
3566 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3567}
3568
12b4fdb4
SJ		 3569/**
3570 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3571 * @hba: per adapter instance
3572 * @attr_sel: uic command argument1
3573 * @attr_set: attribute set type as uic command argument2
3574 * @mib_val: setting value as uic command argument3
3575 * @peer: indicate whether peer or local
3576 *
3577 * Returns 0 on success, non-zero value on failure
3578 */
3579int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3580 u8 attr_set, u32 mib_val, u8 peer)
3581{
3582 struct uic_command uic_cmd = {0};
3583 static const char *const action[] = {
3584 "dme-set",
3585 "dme-peer-set"
3586 };
3587 const char *set = action[!!peer];
3588 int ret;
64238fbd 3589 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3590
3591 uic_cmd.command = peer ?
3592 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3593 uic_cmd.argument1 = attr_sel;
3594 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3595 uic_cmd.argument3 = mib_val;
3596
64238fbd
YG		 3597 do {
3598 /* for peer attributes we retry upon failure */
3599 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3600 if (ret)
3601 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3602 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3603 } while (ret && peer && --retries);
3604
f37e9f8c 3605 if (ret)
64238fbd 3606 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3607 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3608 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3609
3610 return ret;
3611}
3612EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3613
3614/**
3615 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3616 * @hba: per adapter instance
3617 * @attr_sel: uic command argument1
3618 * @mib_val: the value of the attribute as returned by the UIC command
3619 * @peer: indicate whether peer or local
3620 *
3621 * Returns 0 on success, non-zero value on failure
3622 */
3623int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3624 u32 *mib_val, u8 peer)
3625{
3626 struct uic_command uic_cmd = {0};
3627 static const char *const action[] = {
3628 "dme-get",
3629 "dme-peer-get"
3630 };
3631 const char *get = action[!!peer];
3632 int ret;
64238fbd 3633 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3634 struct ufs_pa_layer_attr orig_pwr_info;
3635 struct ufs_pa_layer_attr temp_pwr_info;
3636 bool pwr_mode_change = false;
3637
3638 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3639 orig_pwr_info = hba->pwr_info;
3640 temp_pwr_info = orig_pwr_info;
3641
3642 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3643 orig_pwr_info.pwr_rx == FAST_MODE) {
3644 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3645 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3646 pwr_mode_change = true;
3647 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3648 orig_pwr_info.pwr_rx == SLOW_MODE) {
3649 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3650 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3651 pwr_mode_change = true;
3652 }
3653 if (pwr_mode_change) {
3654 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3655 if (ret)
3656 goto out;
3657 }
3658 }
12b4fdb4
SJ		 3659
3660 uic_cmd.command = peer ?
3661 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3662 uic_cmd.argument1 = attr_sel;
3663
64238fbd
YG		 3664 do {
3665 /* for peer attributes we retry upon failure */
3666 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3667 if (ret)
3668 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3669 get, UIC_GET_ATTR_ID(attr_sel), ret);
3670 } while (ret && peer && --retries);
3671
f37e9f8c 3672 if (ret)
64238fbd 3673 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3674 get, UIC_GET_ATTR_ID(attr_sel),
3675 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3676
64238fbd 3677 if (mib_val && !ret)
12b4fdb4 3678 *mib_val = uic_cmd.argument3;
874237f7
YG		 3679
3680 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3681 && pwr_mode_change)
3682 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3683out:
3684 return ret;
3685}
3686EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3687
53b3d9c3 3688/**
57d104c1
SJ		 3689 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3690 * state) and waits for it to take effect.
3691 *
53b3d9c3 3692 * @hba: per adapter instance
57d104c1
SJ		 3693 * @cmd: UIC command to execute
3694 *
3695 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3696 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3697 * and device UniPro link and hence it's final completion would be indicated by
3698 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3699 * addition to normal UIC command completion Status (UCCS). This function only
3700 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3701 *
3702 * Returns 0 on success, non-zero value on failure
3703 */
57d104c1 3704static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3705{
57d104c1 3706 struct completion uic_async_done;
53b3d9c3
SJ		 3707 unsigned long flags;
3708 u8 status;
3709 int ret;
d75f7fe4 3710 bool reenable_intr = false;
53b3d9c3 3711
53b3d9c3 3712 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3713 init_completion(&uic_async_done);
cad2e03d 3714 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3715
3716 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3717 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3718 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3719 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3720 /*
3721 * Make sure UIC command completion interrupt is disabled before
3722 * issuing UIC command.
3723 */
3724 wmb();
3725 reenable_intr = true;
57d104c1 3726 }
d75f7fe4
YG		 3727 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3728 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3729 if (ret) {
3730 dev_err(hba->dev,
3731 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3732 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3733 goto out;
3734 }
3735
57d104c1 3736 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3737 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3738 dev_err(hba->dev,
57d104c1
SJ		 3739 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3740 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3741 ret = -ETIMEDOUT;
3742 goto out;
3743 }
3744
3745 status = ufshcd_get_upmcrs(hba);
3746 if (status != PWR_LOCAL) {
3747 dev_err(hba->dev,
479da360 3748 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3749 cmd->command, status);
53b3d9c3
SJ		 3750 ret = (status != PWR_OK) ? status : -1;
3751 }
3752out:
7942f7b5
VG		 3753 if (ret) {
3754 ufshcd_print_host_state(hba);
3755 ufshcd_print_pwr_info(hba);
3756 ufshcd_print_host_regs(hba);
3757 }
3758
53b3d9c3 3759 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3760 hba->active_uic_cmd = NULL;
57d104c1 3761 hba->uic_async_done = NULL;
d75f7fe4
YG		 3762 if (reenable_intr)
3763 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3764 spin_unlock_irqrestore(hba->host->host_lock, flags);
3765 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3766
53b3d9c3
SJ		 3767 return ret;
3768}
3769
57d104c1
SJ		 3770/**
3771 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3772 * using DME_SET primitives.
3773 * @hba: per adapter instance
3774 * @mode: powr mode value
3775 *
3776 * Returns 0 on success, non-zero value on failure
3777 */
3778static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3779{
3780 struct uic_command uic_cmd = {0};
1ab27c9c 3781 int ret;
57d104c1 3782
c3a2f9ee
YG		 3783 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3784 ret = ufshcd_dme_set(hba,
3785 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3786 if (ret) {
3787 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3788 __func__, ret);
3789 goto out;
3790 }
3791 }
3792
57d104c1
SJ		 3793 uic_cmd.command = UIC_CMD_DME_SET;
3794 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3795 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3796 ufshcd_hold(hba, false);
3797 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3798 ufshcd_release(hba);
57d104c1 3799
c3a2f9ee 3800out:
1ab27c9c 3801 return ret;
57d104c1
SJ		 3802}
3803
53c12d0e
YG		 3804static int ufshcd_link_recovery(struct ufs_hba *hba)
3805{
3806 int ret;
3807 unsigned long flags;
3808
3809 spin_lock_irqsave(hba->host->host_lock, flags);
3810 hba->ufshcd_state = UFSHCD_STATE_RESET;
3811 ufshcd_set_eh_in_progress(hba);
3812 spin_unlock_irqrestore(hba->host->host_lock, flags);
3813
3814 ret = ufshcd_host_reset_and_restore(hba);
3815
3816 spin_lock_irqsave(hba->host->host_lock, flags);
3817 if (ret)
3818 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3819 ufshcd_clear_eh_in_progress(hba);
3820 spin_unlock_irqrestore(hba->host->host_lock, flags);
3821
3822 if (ret)
3823 dev_err(hba->dev, "%s: link recovery failed, err %d",
3824 __func__, ret);
3825
3826 return ret;
3827}
3828
87d0b4a6 3829static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3830{
87d0b4a6 3831 int ret;
57d104c1 3832 struct uic_command uic_cmd = {0};
911a0771 3833 ktime_t start = ktime_get();
57d104c1 3834
ee32c909
KK		 3835 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3836
57d104c1 3837 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3838 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3839 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3840 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3841
53c12d0e 3842 if (ret) {
87d0b4a6
YG		 3843 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3844 __func__, ret);
3845
53c12d0e
YG		 3846 /*
3847 * If link recovery fails then return error so that caller
3848 * don't retry the hibern8 enter again.
3849 */
3850 if (ufshcd_link_recovery(hba))
3851 ret = -ENOLINK;
ee32c909
KK		 3852 } else
3853 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3854 POST_CHANGE);
53c12d0e 3855
87d0b4a6
YG		 3856 return ret;
3857}
3858
3859static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3860{
3861 int ret = 0, retries;
57d104c1 3862
87d0b4a6
YG		 3863 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3864 ret = __ufshcd_uic_hibern8_enter(hba);
3865 if (!ret || ret == -ENOLINK)
3866 goto out;
3867 }
3868out:
3869 return ret;
57d104c1
SJ		 3870}
3871
3872static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3873{
3874 struct uic_command uic_cmd = {0};
3875 int ret;
911a0771 3876 ktime_t start = ktime_get();
57d104c1 3877
ee32c909
KK		 3878 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3879
57d104c1
SJ		 3880 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3881 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3882 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3883 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3884
57d104c1 3885 if (ret) {
53c12d0e
YG		 3886 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3887 __func__, ret);
3888 ret = ufshcd_link_recovery(hba);
ff8e20c6 3889 } else {
ee32c909
KK		 3890 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3891 POST_CHANGE);
ff8e20c6
DR		 3892 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3893 hba->ufs_stats.hibern8_exit_cnt++;
3894 }
57d104c1
SJ		 3895
3896 return ret;
3897}
3898
ad448378
AH		 3899static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3900{
3901 unsigned long flags;
3902
3903 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
3904 return;
3905
3906 spin_lock_irqsave(hba->host->host_lock, flags);
3907 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3908 spin_unlock_irqrestore(hba->host->host_lock, flags);
3909}
3910
5064636c
YG		 3911 /**
3912 * ufshcd_init_pwr_info - setting the POR (power on reset)
3913 * values in hba power info
3914 * @hba: per-adapter instance
3915 */
3916static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3917{
3918 hba->pwr_info.gear_rx = UFS_PWM_G1;
3919 hba->pwr_info.gear_tx = UFS_PWM_G1;
3920 hba->pwr_info.lane_rx = 1;
3921 hba->pwr_info.lane_tx = 1;
3922 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3923 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3924 hba->pwr_info.hs_rate = 0;
3925}
3926
d3e89bac 3927/**
7eb584db
DR		 3928 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3929 * @hba: per-adapter instance
d3e89bac 3930 */
7eb584db 3931static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3932{
7eb584db
DR		 3933 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3934
3935 if (hba->max_pwr_info.is_valid)
3936 return 0;
3937
2349b533 3938 pwr_info->pwr_tx = FAST_MODE;
3939 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3940 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3941
3942 /* Get the connected lane count */
7eb584db
DR		 3943 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3944 &pwr_info->lane_rx);
3945 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3946 &pwr_info->lane_tx);
3947
3948 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3949 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3950 __func__,
3951 pwr_info->lane_rx,
3952 pwr_info->lane_tx);
3953 return -EINVAL;
3954 }
d3e89bac
SJ		 3955
3956 /*
3957 * First, get the maximum gears of HS speed.
3958 * If a zero value, it means there is no HSGEAR capability.
3959 * Then, get the maximum gears of PWM speed.
3960 */
7eb584db
DR		 3961 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3962 if (!pwr_info->gear_rx) {
3963 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3964 &pwr_info->gear_rx);
3965 if (!pwr_info->gear_rx) {
3966 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3967 __func__, pwr_info->gear_rx);
3968 return -EINVAL;
3969 }
2349b533 3970 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3971 }
3972
7eb584db
DR		 3973 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3974 &pwr_info->gear_tx);
3975 if (!pwr_info->gear_tx) {
d3e89bac 3976 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3977 &pwr_info->gear_tx);
3978 if (!pwr_info->gear_tx) {
3979 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3980 __func__, pwr_info->gear_tx);
3981 return -EINVAL;
3982 }
2349b533 3983 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3984 }
3985
3986 hba->max_pwr_info.is_valid = true;
3987 return 0;
3988}
3989
3990static int ufshcd_change_power_mode(struct ufs_hba *hba,
3991 struct ufs_pa_layer_attr *pwr_mode)
3992{
3993 int ret;
3994
3995 /* if already configured to the requested pwr_mode */
3996 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3997 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3998 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3999 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4000 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4001 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4002 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4003 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4004 return 0;
d3e89bac
SJ		 4005 }
4006
4007 /*
4008 * Configure attributes for power mode change with below.
4009 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4010 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4011 * - PA_HSSERIES
4012 */
7eb584db
DR		 4013 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4014 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4015 pwr_mode->lane_rx);
4016 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4017 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4018 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4019 else
4020 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4021
7eb584db
DR		 4022 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4023 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4024 pwr_mode->lane_tx);
4025 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4026 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4027 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4028 else
4029 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4030
7eb584db
DR		 4031 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4032 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4033 pwr_mode->pwr_rx == FAST_MODE ||
4034 pwr_mode->pwr_tx == FAST_MODE)
4035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4036 pwr_mode->hs_rate);
d3e89bac 4037
7eb584db
DR		 4038 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4039 | pwr_mode->pwr_tx);
4040
4041 if (ret) {
d3e89bac 4042 dev_err(hba->dev,
7eb584db
DR		 4043 "%s: power mode change failed %d\n", __func__, ret);
4044 } else {
0263bcd0
YG		 4045 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4046 pwr_mode);
7eb584db
DR		 4047
4048 memcpy(&hba->pwr_info, pwr_mode,
4049 sizeof(struct ufs_pa_layer_attr));
4050 }
4051
4052 return ret;
4053}
4054
4055/**
4056 * ufshcd_config_pwr_mode - configure a new power mode
4057 * @hba: per-adapter instance
4058 * @desired_pwr_mode: desired power configuration
4059 */
0d846e70 4060int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4061 struct ufs_pa_layer_attr *desired_pwr_mode)
4062{
4063 struct ufs_pa_layer_attr final_params = { 0 };
4064 int ret;
4065
0263bcd0
YG		 4066 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4067 desired_pwr_mode, &final_params);
4068
4069 if (ret)
7eb584db
DR		 4070 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4071
4072 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5 4073 if (!ret)
4074 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 4075
4076 return ret;
4077}
0d846e70 4078EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4079
68078d5c
DR		 4080/**
4081 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4082 * @hba: per-adapter instance
68078d5c
DR		 4083 *
4084 * Set fDeviceInit flag and poll until device toggles it.
4085 */
4086static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4087{
dc3c8d3a
YG		 4088 int i;
4089 int err;
68078d5c
DR		 4090 bool flag_res = 1;
4091
dc3c8d3a
YG		 4092 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4093 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4094 if (err) {
4095 dev_err(hba->dev,
4096 "%s setting fDeviceInit flag failed with error %d\n",
4097 __func__, err);
4098 goto out;
4099 }
4100
dc3c8d3a
YG		 4101 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4102 for (i = 0; i < 1000 && !err && flag_res; i++)
4103 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4104 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4105
68078d5c
DR		 4106 if (err)
4107 dev_err(hba->dev,
4108 "%s reading fDeviceInit flag failed with error %d\n",
4109 __func__, err);
4110 else if (flag_res)
4111 dev_err(hba->dev,
4112 "%s fDeviceInit was not cleared by the device\n",
4113 __func__);
4114
4115out:
4116 return err;
4117}
4118
7a3e97b0
SY		 4119/**
4120 * ufshcd_make_hba_operational - Make UFS controller operational
4121 * @hba: per adapter instance
4122 *
4123 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4124 * 1. Enable required interrupts
4125 * 2. Configure interrupt aggregation
897efe62 4126 * 3. Program UTRL and UTMRL base address
5c0c28a8 4127 * 4. Configure run-stop-registers
7a3e97b0
SY		 4128 *
4129 * Returns 0 on success, non-zero value on failure
4130 */
4131static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4132{
4133 int err = 0;
4134 u32 reg;
4135
6ccf44fe
SJ		 4136 /* Enable required interrupts */
4137 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4138
4139 /* Configure interrupt aggregation */
b852190e
YG		 4140 if (ufshcd_is_intr_aggr_allowed(hba))
4141 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4142 else
4143 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4144
4145 /* Configure UTRL and UTMRL base address registers */
4146 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4147 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4148 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4149 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4150 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4151 REG_UTP_TASK_REQ_LIST_BASE_L);
4152 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4153 REG_UTP_TASK_REQ_LIST_BASE_H);
4154
897efe62
YG		 4155 /*
4156 * Make sure base address and interrupt setup are updated before
4157 * enabling the run/stop registers below.
4158 */
4159 wmb();
4160
7a3e97b0
SY		 4161 /*
4162 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4163 */
5c0c28a8 4164 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4165 if (!(ufshcd_get_lists_status(reg))) {
4166 ufshcd_enable_run_stop_reg(hba);
4167 } else {
3b1d0580 4168 dev_err(hba->dev,
7a3e97b0
SY		 4169 "Host controller not ready to process requests");
4170 err = -EIO;
4171 goto out;
4172 }
4173
7a3e97b0
SY		 4174out:
4175 return err;
4176}
4177
596585a2
YG		 4178/**
4179 * ufshcd_hba_stop - Send controller to reset state
4180 * @hba: per adapter instance
4181 * @can_sleep: perform sleep or just spin
4182 */
4183static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4184{
4185 int err;
4186
4187 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4188 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4189 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4190 10, 1, can_sleep);
4191 if (err)
4192 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4193}
4194
7a3e97b0 4195/**
4404c5de 4196 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4197 * @hba: per adapter instance
4198 *
4199 * The controller resets itself and controller firmware initialization
4200 * sequence kicks off. When controller is ready it will set
4201 * the Host Controller Enable bit to 1.
4202 *
4203 * Returns 0 on success, non-zero value on failure
4204 */
4404c5de 4205static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0
SY		 4206{
4207 int retry;
4208
4209 /*
4210 * msleep of 1 and 5 used in this function might result in msleep(20),
4211 * but it was necessary to send the UFS FPGA to reset mode during
4212 * development and testing of this driver. msleep can be changed to
4213 * mdelay and retry count can be reduced based on the controller.
4214 */
596585a2 4215 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4216 /* change controller state to "reset state" */
596585a2 4217 ufshcd_hba_stop(hba, true);
7a3e97b0 4218
57d104c1
SJ		 4219 /* UniPro link is disabled at this point */
4220 ufshcd_set_link_off(hba);
4221
0263bcd0 4222 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4223
7a3e97b0
SY		 4224 /* start controller initialization sequence */
4225 ufshcd_hba_start(hba);
4226
4227 /*
4228 * To initialize a UFS host controller HCE bit must be set to 1.
4229 * During initialization the HCE bit value changes from 1->0->1.
4230 * When the host controller completes initialization sequence
4231 * it sets the value of HCE bit to 1. The same HCE bit is read back
4232 * to check if the controller has completed initialization sequence.
4233 * So without this delay the value HCE = 1, set in the previous
4234 * instruction might be read back.
4235 * This delay can be changed based on the controller.
4236 */
4237 msleep(1);
4238
4239 /* wait for the host controller to complete initialization */
4240 retry = 10;
4241 while (ufshcd_is_hba_active(hba)) {
4242 if (retry) {
4243 retry--;
4244 } else {
3b1d0580 4245 dev_err(hba->dev,
7a3e97b0
SY		 4246 "Controller enable failed\n");
4247 return -EIO;
4248 }
4249 msleep(5);
4250 }
5c0c28a8 4251
1d337ec2 4252 /* enable UIC related interrupts */
57d104c1 4253 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4254
0263bcd0 4255 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4256
7a3e97b0
SY		 4257 return 0;
4258}
4259
4404c5de
AA		 4260static int ufshcd_hba_enable(struct ufs_hba *hba)
4261{
4262 int ret;
4263
4264 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4265 ufshcd_set_link_off(hba);
4266 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4267
4268 /* enable UIC related interrupts */
4269 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4270 ret = ufshcd_dme_reset(hba);
4271 if (!ret) {
4272 ret = ufshcd_dme_enable(hba);
4273 if (!ret)
4274 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4275 if (ret)
4276 dev_err(hba->dev,
4277 "Host controller enable failed with non-hce\n");
4278 }
4279 } else {
4280 ret = ufshcd_hba_execute_hce(hba);
4281 }
4282
4283 return ret;
4284}
7ca38cf3
YG		 4285static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4286{
4287 int tx_lanes, i, err = 0;
4288
4289 if (!peer)
4290 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4291 &tx_lanes);
4292 else
4293 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4294 &tx_lanes);
4295 for (i = 0; i < tx_lanes; i++) {
4296 if (!peer)
4297 err = ufshcd_dme_set(hba,
4298 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4299 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4300 0);
4301 else
4302 err = ufshcd_dme_peer_set(hba,
4303 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4304 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4305 0);
4306 if (err) {
4307 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4308 __func__, peer, i, err);
4309 break;
4310 }
4311 }
4312
4313 return err;
4314}
4315
4316static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4317{
4318 return ufshcd_disable_tx_lcc(hba, true);
4319}
4320
7a3e97b0 4321/**
6ccf44fe 4322 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4323 * @hba: per adapter instance
4324 *
6ccf44fe 4325 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4326 */
6ccf44fe 4327static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4328{
6ccf44fe 4329 int ret;
1d337ec2 4330 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4331 bool link_startup_again = false;
7a3e97b0 4332
7caf489b 4333 /*
4334 * If UFS device isn't active then we will have to issue link startup
4335 * 2 times to make sure the device state move to active.
4336 */
4337 if (!ufshcd_is_ufs_dev_active(hba))
4338 link_startup_again = true;
7a3e97b0 4339
7caf489b 4340link_startup:
1d337ec2 4341 do {
0263bcd0 4342 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4343
1d337ec2 4344 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4345
1d337ec2
SRT		 4346 /* check if device is detected by inter-connect layer */
4347 if (!ret && !ufshcd_is_device_present(hba)) {
4348 dev_err(hba->dev, "%s: Device not present\n", __func__);
4349 ret = -ENXIO;
4350 goto out;
4351 }
6ccf44fe 4352
1d337ec2
SRT		 4353 /*
4354 * DME link lost indication is only received when link is up,
4355 * but we can't be sure if the link is up until link startup
4356 * succeeds. So reset the local Uni-Pro and try again.
4357 */
4358 if (ret && ufshcd_hba_enable(hba))
4359 goto out;
4360 } while (ret && retries--);
4361
4362 if (ret)
4363 /* failed to get the link up... retire */
5c0c28a8 4364 goto out;
5c0c28a8 4365
7caf489b 4366 if (link_startup_again) {
4367 link_startup_again = false;
4368 retries = DME_LINKSTARTUP_RETRIES;
4369 goto link_startup;
4370 }
4371
d2aebb9b 4372 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4373 ufshcd_init_pwr_info(hba);
4374 ufshcd_print_pwr_info(hba);
4375
7ca38cf3
YG		 4376 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4377 ret = ufshcd_disable_device_tx_lcc(hba);
4378 if (ret)
4379 goto out;
4380 }
4381
5c0c28a8 4382 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4383 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4384 if (ret)
4385 goto out;
7a3e97b0 4386
5c0c28a8 4387 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4388out:
7942f7b5 4389 if (ret) {
6ccf44fe 4390 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4391 ufshcd_print_host_state(hba);
4392 ufshcd_print_pwr_info(hba);
4393 ufshcd_print_host_regs(hba);
4394 }
6ccf44fe 4395 return ret;
7a3e97b0
SY		 4396}
4397
5a0b0cb9
SRT		 4398/**
4399 * ufshcd_verify_dev_init() - Verify device initialization
4400 * @hba: per-adapter instance
4401 *
4402 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4403 * device Transport Protocol (UTP) layer is ready after a reset.
4404 * If the UTP layer at the device side is not initialized, it may
4405 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4406 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4407 */
4408static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4409{
4410 int err = 0;
4411 int retries;
4412
1ab27c9c 4413 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4414 mutex_lock(&hba->dev_cmd.lock);
4415 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4416 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4417 NOP_OUT_TIMEOUT);
4418
4419 if (!err || err == -ETIMEDOUT)
4420 break;
4421
4422 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4423 }
4424 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4425 ufshcd_release(hba);
5a0b0cb9
SRT		 4426
4427 if (err)
4428 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4429 return err;
4430}
4431
0ce147d4
SJ		 4432/**
4433 * ufshcd_set_queue_depth - set lun queue depth
4434 * @sdev: pointer to SCSI device
4435 *
4436 * Read bLUQueueDepth value and activate scsi tagged command
4437 * queueing. For WLUN, queue depth is set to 1. For best-effort
4438 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4439 * value that host can queue.
4440 */
4441static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4442{
4443 int ret = 0;
4444 u8 lun_qdepth;
4445 struct ufs_hba *hba;
4446
4447 hba = shost_priv(sdev->host);
4448
4449 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4450 ret = ufshcd_read_unit_desc_param(hba,
4451 ufshcd_scsi_to_upiu_lun(sdev->lun),
4452 UNIT_DESC_PARAM_LU_Q_DEPTH,
4453 &lun_qdepth,
4454 sizeof(lun_qdepth));
0ce147d4
SJ		 4455
4456 /* Some WLUN doesn't support unit descriptor */
4457 if (ret == -EOPNOTSUPP)
4458 lun_qdepth = 1;
4459 else if (!lun_qdepth)
4460 /* eventually, we can figure out the real queue depth */
4461 lun_qdepth = hba->nutrs;
4462 else
4463 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4464
4465 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4466 __func__, lun_qdepth);
db5ed4df 4467 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4468}
4469
57d104c1
SJ		 4470/*
4471 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4472 * @hba: per-adapter instance
4473 * @lun: UFS device lun id
4474 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4475 *
4476 * Returns 0 in case of success and b_lu_write_protect status would be returned
4477 * @b_lu_write_protect parameter.
4478 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4479 * Returns -EINVAL in case of invalid parameters passed to this function.
4480 */
4481static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4482 u8 lun,
4483 u8 *b_lu_write_protect)
4484{
4485 int ret;
4486
4487 if (!b_lu_write_protect)
4488 ret = -EINVAL;
4489 /*
4490 * According to UFS device spec, RPMB LU can't be write
4491 * protected so skip reading bLUWriteProtect parameter for
4492 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4493 */
4494 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4495 ret = -ENOTSUPP;
4496 else
4497 ret = ufshcd_read_unit_desc_param(hba,
4498 lun,
4499 UNIT_DESC_PARAM_LU_WR_PROTECT,
4500 b_lu_write_protect,
4501 sizeof(*b_lu_write_protect));
4502 return ret;
4503}
4504
4505/**
4506 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4507 * status
4508 * @hba: per-adapter instance
4509 * @sdev: pointer to SCSI device
4510 *
4511 */
4512static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4513 struct scsi_device *sdev)
4514{
4515 if (hba->dev_info.f_power_on_wp_en &&
4516 !hba->dev_info.is_lu_power_on_wp) {
4517 u8 b_lu_write_protect;
4518
4519 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4520 &b_lu_write_protect) &&
4521 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4522 hba->dev_info.is_lu_power_on_wp = true;
4523 }
4524}
4525
7a3e97b0
SY		 4526/**
4527 * ufshcd_slave_alloc - handle initial SCSI device configurations
4528 * @sdev: pointer to SCSI device
4529 *
4530 * Returns success
4531 */
4532static int ufshcd_slave_alloc(struct scsi_device *sdev)
4533{
4534 struct ufs_hba *hba;
4535
4536 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4537
4538 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4539 sdev->use_10_for_ms = 1;
7a3e97b0 4540
e8e7f271
SRT		 4541 /* allow SCSI layer to restart the device in case of errors */
4542 sdev->allow_restart = 1;
4264fd61 4543
b2a6c522
SRT		 4544 /* REPORT SUPPORTED OPERATION CODES is not supported */
4545 sdev->no_report_opcodes = 1;
4546
84af7e8b
SRT		 4547 /* WRITE_SAME command is not supported */
4548 sdev->no_write_same = 1;
e8e7f271 4549
0ce147d4 4550 ufshcd_set_queue_depth(sdev);
4264fd61 4551
57d104c1
SJ		 4552 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4553
7a3e97b0
SY		 4554 return 0;
4555}
4556
4264fd61
SRT		 4557/**
4558 * ufshcd_change_queue_depth - change queue depth
4559 * @sdev: pointer to SCSI device
4560 * @depth: required depth to set
4264fd61 4561 *
db5ed4df 4562 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4563 */
db5ed4df 4564static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4565{
4566 struct ufs_hba *hba = shost_priv(sdev->host);
4567
4568 if (depth > hba->nutrs)
4569 depth = hba->nutrs;
db5ed4df 4570 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4571}
4572
eeda4749
AM		 4573/**
4574 * ufshcd_slave_configure - adjust SCSI device configurations
4575 * @sdev: pointer to SCSI device
4576 */
4577static int ufshcd_slave_configure(struct scsi_device *sdev)
4578{
4579 struct request_queue *q = sdev->request_queue;
4580
4581 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4582 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4583
4584 return 0;
4585}
4586
7a3e97b0
SY		 4587/**
4588 * ufshcd_slave_destroy - remove SCSI device configurations
4589 * @sdev: pointer to SCSI device
4590 */
4591static void ufshcd_slave_destroy(struct scsi_device *sdev)
4592{
4593 struct ufs_hba *hba;
4594
4595 hba = shost_priv(sdev->host);
0ce147d4 4596 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4597 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4598 unsigned long flags;
4599
4600 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4601 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4602 spin_unlock_irqrestore(hba->host->host_lock, flags);
4603 }
7a3e97b0
SY		 4604}
4605
7a3e97b0
SY		 4606/**
4607 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4608 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4609 * @scsi_status: SCSI command status
4610 *
4611 * Returns value base on SCSI command status
4612 */
4613static inline int
4614ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4615{
4616 int result = 0;
4617
4618 switch (scsi_status) {
7a3e97b0 4619 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4620 ufshcd_copy_sense_data(lrbp);
4621 case SAM_STAT_GOOD:
7a3e97b0
SY		 4622 result |= DID_OK << 16 |
4623 COMMAND_COMPLETE << 8 |
1c2623c5 4624 scsi_status;
7a3e97b0
SY		 4625 break;
4626 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4627 case SAM_STAT_BUSY:
7a3e97b0 4628 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4629 ufshcd_copy_sense_data(lrbp);
4630 result |= scsi_status;
7a3e97b0
SY		 4631 break;
4632 default:
4633 result |= DID_ERROR << 16;
4634 break;
4635 } /* end of switch */
4636
4637 return result;
4638}
4639
4640/**
4641 * ufshcd_transfer_rsp_status - Get overall status of the response
4642 * @hba: per adapter instance
8aa29f19 4643 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4644 *
4645 * Returns result of the command to notify SCSI midlayer
4646 */
4647static inline int
4648ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4649{
4650 int result = 0;
4651 int scsi_status;
4652 int ocs;
4653
4654 /* overall command status of utrd */
4655 ocs = ufshcd_get_tr_ocs(lrbp);
4656
4657 switch (ocs) {
4658 case OCS_SUCCESS:
5a0b0cb9 4659 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4660 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4661 switch (result) {
4662 case UPIU_TRANSACTION_RESPONSE:
4663 /*
4664 * get the response UPIU result to extract
4665 * the SCSI command status
4666 */
4667 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4668
4669 /*
4670 * get the result based on SCSI status response
4671 * to notify the SCSI midlayer of the command status
4672 */
4673 scsi_status = result & MASK_SCSI_STATUS;
4674 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4675
f05ac2e5
YG		 4676 /*
4677 * Currently we are only supporting BKOPs exception
4678 * events hence we can ignore BKOPs exception event
4679 * during power management callbacks. BKOPs exception
4680 * event is not expected to be raised in runtime suspend
4681 * callback as it allows the urgent bkops.
4682 * During system suspend, we are anyway forcefully
4683 * disabling the bkops and if urgent bkops is needed
4684 * it will be enabled on system resume. Long term
4685 * solution could be to abort the system suspend if
4686 * UFS device needs urgent BKOPs.
4687 */
4688 if (!hba->pm_op_in_progress &&
4689 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4690 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4691 break;
4692 case UPIU_TRANSACTION_REJECT_UPIU:
4693 /* TODO: handle Reject UPIU Response */
4694 result = DID_ERROR << 16;
3b1d0580 4695 dev_err(hba->dev,
5a0b0cb9
SRT		 4696 "Reject UPIU not fully implemented\n");
4697 break;
4698 default:
4699 result = DID_ERROR << 16;
4700 dev_err(hba->dev,
4701 "Unexpected request response code = %x\n",
4702 result);
7a3e97b0
SY		 4703 break;
4704 }
7a3e97b0
SY		 4705 break;
4706 case OCS_ABORTED:
4707 result |= DID_ABORT << 16;
4708 break;
e8e7f271
SRT		 4709 case OCS_INVALID_COMMAND_STATUS:
4710 result |= DID_REQUEUE << 16;
4711 break;
7a3e97b0
SY		 4712 case OCS_INVALID_CMD_TABLE_ATTR:
4713 case OCS_INVALID_PRDT_ATTR:
4714 case OCS_MISMATCH_DATA_BUF_SIZE:
4715 case OCS_MISMATCH_RESP_UPIU_SIZE:
4716 case OCS_PEER_COMM_FAILURE:
4717 case OCS_FATAL_ERROR:
4718 default:
4719 result |= DID_ERROR << 16;
3b1d0580 4720 dev_err(hba->dev,
ff8e20c6
DR		 4721 "OCS error from controller = %x for tag %d\n",
4722 ocs, lrbp->task_tag);
4723 ufshcd_print_host_regs(hba);
6ba65588 4724 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4725 break;
4726 } /* end of switch */
4727
66cc820f
DR		 4728 if (host_byte(result) != DID_OK)
4729 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4730 return result;
4731}
4732
6ccf44fe
SJ		 4733/**
4734 * ufshcd_uic_cmd_compl - handle completion of uic command
4735 * @hba: per adapter instance
53b3d9c3 4736 * @intr_status: interrupt status generated by the controller
6ccf44fe 4737 */
53b3d9c3 4738static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4739{
53b3d9c3 4740 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4741 hba->active_uic_cmd->argument2 |=
4742 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4743 hba->active_uic_cmd->argument3 =
4744 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4745 complete(&hba->active_uic_cmd->done);
4746 }
53b3d9c3 4747
57d104c1
SJ		 4748 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4749 complete(hba->uic_async_done);
6ccf44fe
SJ		 4750}
4751
7a3e97b0 4752/**
9a47ec7c 4753 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4754 * @hba: per adapter instance
9a47ec7c 4755 * @completed_reqs: requests to complete
7a3e97b0 4756 */
9a47ec7c
YG		 4757static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4758 unsigned long completed_reqs)
7a3e97b0 4759{
5a0b0cb9
SRT		 4760 struct ufshcd_lrb *lrbp;
4761 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4762 int result;
4763 int index;
e9d501b1 4764
e9d501b1
DR		 4765 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4766 lrbp = &hba->lrb[index];
4767 cmd = lrbp->cmd;
4768 if (cmd) {
1a07f2d9 4769 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4770 result = ufshcd_transfer_rsp_status(hba, lrbp);
4771 scsi_dma_unmap(cmd);
4772 cmd->result = result;
4773 /* Mark completed command as NULL in LRB */
4774 lrbp->cmd = NULL;
4775 clear_bit_unlock(index, &hba->lrb_in_use);
4776 /* Do not touch lrbp after scsi done */
4777 cmd->scsi_done(cmd);
1ab27c9c 4778 __ufshcd_release(hba);
300bb13f
JP		 4779 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4780 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4781 if (hba->dev_cmd.complete) {
4782 ufshcd_add_command_trace(hba, index,
4783 "dev_complete");
e9d501b1 4784 complete(hba->dev_cmd.complete);
1a07f2d9 4785 }
e9d501b1 4786 }
401f1e44 4787 if (ufshcd_is_clkscaling_supported(hba))
4788 hba->clk_scaling.active_reqs--;
09017188
ZL		 4789
4790 lrbp->compl_time_stamp = ktime_get();
e9d501b1 4791 }
7a3e97b0
SY		 4792
4793 /* clear corresponding bits of completed commands */
4794 hba->outstanding_reqs ^= completed_reqs;
4795
856b3483
ST		 4796 ufshcd_clk_scaling_update_busy(hba);
4797
5a0b0cb9
SRT		 4798 /* we might have free'd some tags above */
4799 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4800}
4801
9a47ec7c
YG		 4802/**
4803 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4804 * @hba: per adapter instance
4805 */
4806static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4807{
4808 unsigned long completed_reqs;
4809 u32 tr_doorbell;
4810
4811 /* Resetting interrupt aggregation counters first and reading the
4812 * DOOR_BELL afterward allows us to handle all the completed requests.
4813 * In order to prevent other interrupts starvation the DB is read once
4814 * after reset. The down side of this solution is the possibility of
4815 * false interrupt if device completes another request after resetting
4816 * aggregation and before reading the DB.
4817 */
5ac6abc9
AA		 4818 if (ufshcd_is_intr_aggr_allowed(hba) &&
4819 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 4820 ufshcd_reset_intr_aggr(hba);
4821
4822 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4823 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4824
4825 __ufshcd_transfer_req_compl(hba, completed_reqs);
4826}
4827
66ec6d59
SRT		 4828/**
4829 * ufshcd_disable_ee - disable exception event
4830 * @hba: per-adapter instance
4831 * @mask: exception event to disable
4832 *
4833 * Disables exception event in the device so that the EVENT_ALERT
4834 * bit is not set.
4835 *
4836 * Returns zero on success, non-zero error value on failure.
4837 */
4838static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4839{
4840 int err = 0;
4841 u32 val;
4842
4843 if (!(hba->ee_ctrl_mask & mask))
4844 goto out;
4845
4846 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4847 val &= MASK_EE_STATUS;
5e86ae44 4848 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4849 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4850 if (!err)
4851 hba->ee_ctrl_mask &= ~mask;
4852out:
4853 return err;
4854}
4855
4856/**
4857 * ufshcd_enable_ee - enable exception event
4858 * @hba: per-adapter instance
4859 * @mask: exception event to enable
4860 *
4861 * Enable corresponding exception event in the device to allow
4862 * device to alert host in critical scenarios.
4863 *
4864 * Returns zero on success, non-zero error value on failure.
4865 */
4866static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4867{
4868 int err = 0;
4869 u32 val;
4870
4871 if (hba->ee_ctrl_mask & mask)
4872 goto out;
4873
4874 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4875 val &= MASK_EE_STATUS;
5e86ae44 4876 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4877 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4878 if (!err)
4879 hba->ee_ctrl_mask |= mask;
4880out:
4881 return err;
4882}
4883
4884/**
4885 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4886 * @hba: per-adapter instance
4887 *
4888 * Allow device to manage background operations on its own. Enabling
4889 * this might lead to inconsistent latencies during normal data transfers
4890 * as the device is allowed to manage its own way of handling background
4891 * operations.
4892 *
4893 * Returns zero on success, non-zero on failure.
4894 */
4895static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4896{
4897 int err = 0;
4898
4899 if (hba->auto_bkops_enabled)
4900 goto out;
4901
dc3c8d3a 4902 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4903 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4904 if (err) {
4905 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4906 __func__, err);
4907 goto out;
4908 }
4909
4910 hba->auto_bkops_enabled = true;
7ff5ab47 4911 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4912
4913 /* No need of URGENT_BKOPS exception from the device */
4914 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4915 if (err)
4916 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4917 __func__, err);
4918out:
4919 return err;
4920}
4921
4922/**
4923 * ufshcd_disable_auto_bkops - block device in doing background operations
4924 * @hba: per-adapter instance
4925 *
4926 * Disabling background operations improves command response latency but
4927 * has drawback of device moving into critical state where the device is
4928 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4929 * host is idle so that BKOPS are managed effectively without any negative
4930 * impacts.
4931 *
4932 * Returns zero on success, non-zero on failure.
4933 */
4934static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4935{
4936 int err = 0;
4937
4938 if (!hba->auto_bkops_enabled)
4939 goto out;
4940
4941 /*
4942 * If host assisted BKOPs is to be enabled, make sure
4943 * urgent bkops exception is allowed.
4944 */
4945 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4946 if (err) {
4947 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4948 __func__, err);
4949 goto out;
4950 }
4951
dc3c8d3a 4952 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4953 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4954 if (err) {
4955 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4956 __func__, err);
4957 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4958 goto out;
4959 }
4960
4961 hba->auto_bkops_enabled = false;
7ff5ab47 4962 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4963out:
4964 return err;
4965}
4966
4967/**
4e768e76 4968 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4969 * @hba: per adapter instance
4970 *
4971 * After a device reset the device may toggle the BKOPS_EN flag
4972 * to default value. The s/w tracking variables should be updated
4e768e76 4973 * as well. This function would change the auto-bkops state based on
4974 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4975 */
4e768e76 4976static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4977{
4e768e76 4978 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4979 hba->auto_bkops_enabled = false;
4980 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4981 ufshcd_enable_auto_bkops(hba);
4982 } else {
4983 hba->auto_bkops_enabled = true;
4984 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4985 ufshcd_disable_auto_bkops(hba);
4986 }
66ec6d59
SRT		 4987}
4988
4989static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4990{
5e86ae44 4991 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4992 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4993}
4994
4995/**
57d104c1 4996 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4997 * @hba: per-adapter instance
57d104c1 4998 * @status: bkops_status value
66ec6d59 4999 *
57d104c1
SJ		 5000 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5001 * flag in the device to permit background operations if the device
5002 * bkops_status is greater than or equal to "status" argument passed to
5003 * this function, disable otherwise.
5004 *
5005 * Returns 0 for success, non-zero in case of failure.
5006 *
5007 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5008 * to know whether auto bkops is enabled or disabled after this function
5009 * returns control to it.
66ec6d59 5010 */
57d104c1
SJ		 5011static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5012 enum bkops_status status)
66ec6d59
SRT		 5013{
5014 int err;
57d104c1 5015 u32 curr_status = 0;
66ec6d59 5016
57d104c1 5017 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5018 if (err) {
5019 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5020 __func__, err);
5021 goto out;
57d104c1
SJ		 5022 } else if (curr_status > BKOPS_STATUS_MAX) {
5023 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5024 __func__, curr_status);
5025 err = -EINVAL;
5026 goto out;
66ec6d59
SRT		 5027 }
5028
57d104c1 5029 if (curr_status >= status)
66ec6d59 5030 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5031 else
5032 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5033out:
5034 return err;
5035}
5036
57d104c1
SJ		 5037/**
5038 * ufshcd_urgent_bkops - handle urgent bkops exception event
5039 * @hba: per-adapter instance
5040 *
5041 * Enable fBackgroundOpsEn flag in the device to permit background
5042 * operations.
5043 *
5044 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5045 * and negative error value for any other failure.
5046 */
5047static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5048{
afdfff59 5049 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5050}
5051
66ec6d59
SRT		 5052static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5053{
5e86ae44 5054 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5055 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5056}
5057
afdfff59
YG		 5058static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5059{
5060 int err;
5061 u32 curr_status = 0;
5062
5063 if (hba->is_urgent_bkops_lvl_checked)
5064 goto enable_auto_bkops;
5065
5066 err = ufshcd_get_bkops_status(hba, &curr_status);
5067 if (err) {
5068 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5069 __func__, err);
5070 goto out;
5071 }
5072
5073 /*
5074 * We are seeing that some devices are raising the urgent bkops
5075 * exception events even when BKOPS status doesn't indicate performace
5076 * impacted or critical. Handle these device by determining their urgent
5077 * bkops status at runtime.
5078 */
5079 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5080 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5081 __func__, curr_status);
5082 /* update the current status as the urgent bkops level */
5083 hba->urgent_bkops_lvl = curr_status;
5084 hba->is_urgent_bkops_lvl_checked = true;
5085 }
5086
5087enable_auto_bkops:
5088 err = ufshcd_enable_auto_bkops(hba);
5089out:
5090 if (err < 0)
5091 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5092 __func__, err);
5093}
5094
66ec6d59
SRT		 5095/**
5096 * ufshcd_exception_event_handler - handle exceptions raised by device
5097 * @work: pointer to work data
5098 *
5099 * Read bExceptionEventStatus attribute from the device and handle the
5100 * exception event accordingly.
5101 */
5102static void ufshcd_exception_event_handler(struct work_struct *work)
5103{
5104 struct ufs_hba *hba;
5105 int err;
5106 u32 status = 0;
5107 hba = container_of(work, struct ufs_hba, eeh_work);
5108
62694735 5109 pm_runtime_get_sync(hba->dev);
2e3611e9 5110 scsi_block_requests(hba->host);
66ec6d59
SRT		 5111 err = ufshcd_get_ee_status(hba, &status);
5112 if (err) {
5113 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5114 __func__, err);
5115 goto out;
5116 }
5117
5118 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5119
5120 if (status & MASK_EE_URGENT_BKOPS)
5121 ufshcd_bkops_exception_event_handler(hba);
5122
66ec6d59 5123out:
2e3611e9 5124 scsi_unblock_requests(hba->host);
62694735 5125 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5126 return;
5127}
5128
9a47ec7c
YG		 5129/* Complete requests that have door-bell cleared */
5130static void ufshcd_complete_requests(struct ufs_hba *hba)
5131{
5132 ufshcd_transfer_req_compl(hba);
5133 ufshcd_tmc_handler(hba);
5134}
5135
583fa62d
YG		 5136/**
5137 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5138 * to recover from the DL NAC errors or not.
5139 * @hba: per-adapter instance
5140 *
5141 * Returns true if error handling is required, false otherwise
5142 */
5143static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5144{
5145 unsigned long flags;
5146 bool err_handling = true;
5147
5148 spin_lock_irqsave(hba->host->host_lock, flags);
5149 /*
5150 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5151 * device fatal error and/or DL NAC & REPLAY timeout errors.
5152 */
5153 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5154 goto out;
5155
5156 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5157 ((hba->saved_err & UIC_ERROR) &&
5158 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5159 goto out;
5160
5161 if ((hba->saved_err & UIC_ERROR) &&
5162 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5163 int err;
5164 /*
5165 * wait for 50ms to see if we can get any other errors or not.
5166 */
5167 spin_unlock_irqrestore(hba->host->host_lock, flags);
5168 msleep(50);
5169 spin_lock_irqsave(hba->host->host_lock, flags);
5170
5171 /*
5172 * now check if we have got any other severe errors other than
5173 * DL NAC error?
5174 */
5175 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5176 ((hba->saved_err & UIC_ERROR) &&
5177 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5178 goto out;
5179
5180 /*
5181 * As DL NAC is the only error received so far, send out NOP
5182 * command to confirm if link is still active or not.
5183 * - If we don't get any response then do error recovery.
5184 * - If we get response then clear the DL NAC error bit.
5185 */
5186
5187 spin_unlock_irqrestore(hba->host->host_lock, flags);
5188 err = ufshcd_verify_dev_init(hba);
5189 spin_lock_irqsave(hba->host->host_lock, flags);
5190
5191 if (err)
5192 goto out;
5193
5194 /* Link seems to be alive hence ignore the DL NAC errors */
5195 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5196 hba->saved_err &= ~UIC_ERROR;
5197 /* clear NAC error */
5198 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5199 if (!hba->saved_uic_err) {
5200 err_handling = false;
5201 goto out;
5202 }
5203 }
5204out:
5205 spin_unlock_irqrestore(hba->host->host_lock, flags);
5206 return err_handling;
5207}
5208
7a3e97b0 5209/**
e8e7f271
SRT		 5210 * ufshcd_err_handler - handle UFS errors that require s/w attention
5211 * @work: pointer to work structure
7a3e97b0 5212 */
e8e7f271 5213static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5214{
5215 struct ufs_hba *hba;
e8e7f271
SRT		 5216 unsigned long flags;
5217 u32 err_xfer = 0;
5218 u32 err_tm = 0;
5219 int err = 0;
5220 int tag;
9a47ec7c 5221 bool needs_reset = false;
e8e7f271
SRT		 5222
5223 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5224
62694735 5225 pm_runtime_get_sync(hba->dev);
1ab27c9c 5226 ufshcd_hold(hba, false);
e8e7f271
SRT		 5227
5228 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5229 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5230 goto out;
e8e7f271
SRT		 5231
5232 hba->ufshcd_state = UFSHCD_STATE_RESET;
5233 ufshcd_set_eh_in_progress(hba);
5234
5235 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5236 ufshcd_complete_requests(hba);
583fa62d
YG		 5237
5238 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5239 bool ret;
5240
5241 spin_unlock_irqrestore(hba->host->host_lock, flags);
5242 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5243 ret = ufshcd_quirk_dl_nac_errors(hba);
5244 spin_lock_irqsave(hba->host->host_lock, flags);
5245 if (!ret)
5246 goto skip_err_handling;
5247 }
9a47ec7c
YG		 5248 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5249 ((hba->saved_err & UIC_ERROR) &&
5250 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5251 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5252 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5253 needs_reset = true;
e8e7f271 5254
9a47ec7c
YG		 5255 /*
5256 * if host reset is required then skip clearing the pending
5257 * transfers forcefully because they will automatically get
5258 * cleared after link startup.
5259 */
5260 if (needs_reset)
5261 goto skip_pending_xfer_clear;
5262
5263 /* release lock as clear command might sleep */
5264 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5265 /* Clear pending transfer requests */
9a47ec7c
YG		 5266 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5267 if (ufshcd_clear_cmd(hba, tag)) {
5268 err_xfer = true;
5269 goto lock_skip_pending_xfer_clear;
5270 }
5271 }
e8e7f271
SRT		 5272
5273 /* Clear pending task management requests */
9a47ec7c
YG		 5274 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5275 if (ufshcd_clear_tm_cmd(hba, tag)) {
5276 err_tm = true;
5277 goto lock_skip_pending_xfer_clear;
5278 }
5279 }
e8e7f271 5280
9a47ec7c 5281lock_skip_pending_xfer_clear:
e8e7f271 5282 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5283
9a47ec7c
YG		 5284 /* Complete the requests that are cleared by s/w */
5285 ufshcd_complete_requests(hba);
5286
5287 if (err_xfer || err_tm)
5288 needs_reset = true;
5289
5290skip_pending_xfer_clear:
e8e7f271 5291 /* Fatal errors need reset */
9a47ec7c
YG		 5292 if (needs_reset) {
5293 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5294
5295 /*
5296 * ufshcd_reset_and_restore() does the link reinitialization
5297 * which will need atleast one empty doorbell slot to send the
5298 * device management commands (NOP and query commands).
5299 * If there is no slot empty at this moment then free up last
5300 * slot forcefully.
5301 */
5302 if (hba->outstanding_reqs == max_doorbells)
5303 __ufshcd_transfer_req_compl(hba,
5304 (1UL << (hba->nutrs - 1)));
5305
5306 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5307 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5308 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5309 if (err) {
5310 dev_err(hba->dev, "%s: reset and restore failed\n",
5311 __func__);
5312 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5313 }
5314 /*
5315 * Inform scsi mid-layer that we did reset and allow to handle
5316 * Unit Attention properly.
5317 */
5318 scsi_report_bus_reset(hba->host, 0);
5319 hba->saved_err = 0;
5320 hba->saved_uic_err = 0;
5321 }
9a47ec7c 5322
583fa62d 5323skip_err_handling:
9a47ec7c
YG		 5324 if (!needs_reset) {
5325 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5326 if (hba->saved_err || hba->saved_uic_err)
5327 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5328 __func__, hba->saved_err, hba->saved_uic_err);
5329 }
5330
e8e7f271
SRT		 5331 ufshcd_clear_eh_in_progress(hba);
5332
5333out:
9a47ec7c 5334 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5335 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5336 ufshcd_release(hba);
62694735 5337 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5338}
5339
ff8e20c6
DR		 5340static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5341 u32 reg)
5342{
5343 reg_hist->reg[reg_hist->pos] = reg;
5344 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5345 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5346}
5347
7a3e97b0 5348/**
e8e7f271
SRT		 5349 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5350 * @hba: per-adapter instance
7a3e97b0 5351 */
e8e7f271 5352static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5353{
5354 u32 reg;
5355
fb7b45f0
DR		 5356 /* PHY layer lane error */
5357 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5358 /* Ignore LINERESET indication, as this is not an error */
5359 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5360 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5361 /*
5362 * To know whether this error is fatal or not, DB timeout
5363 * must be checked but this error is handled separately.
5364 */
5365 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5366 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5367 }
fb7b45f0 5368
e8e7f271
SRT		 5369 /* PA_INIT_ERROR is fatal and needs UIC reset */
5370 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5371 if (reg)
5372 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5373
e8e7f271
SRT		 5374 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5375 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5376 else if (hba->dev_quirks &
5377 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5378 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5379 hba->uic_error |=
5380 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5381 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5382 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5383 }
e8e7f271
SRT		 5384
5385 /* UIC NL/TL/DME errors needs software retry */
5386 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5387 if (reg) {
5388 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5389 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5390 }
e8e7f271
SRT		 5391
5392 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5393 if (reg) {
5394 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5395 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5396 }
e8e7f271
SRT		 5397
5398 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5399 if (reg) {
5400 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5401 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5402 }
e8e7f271
SRT		 5403
5404 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5405 __func__, hba->uic_error);
5406}
5407
5408/**
5409 * ufshcd_check_errors - Check for errors that need s/w attention
5410 * @hba: per-adapter instance
5411 */
5412static void ufshcd_check_errors(struct ufs_hba *hba)
5413{
5414 bool queue_eh_work = false;
5415
7a3e97b0 5416 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5417 queue_eh_work = true;
7a3e97b0
SY		 5418
5419 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5420 hba->uic_error = 0;
5421 ufshcd_update_uic_error(hba);
5422 if (hba->uic_error)
5423 queue_eh_work = true;
7a3e97b0 5424 }
e8e7f271
SRT		 5425
5426 if (queue_eh_work) {
9a47ec7c
YG		 5427 /*
5428 * update the transfer error masks to sticky bits, let's do this
5429 * irrespective of current ufshcd_state.
5430 */
5431 hba->saved_err |= hba->errors;
5432 hba->saved_uic_err |= hba->uic_error;
5433
e8e7f271
SRT		 5434 /* handle fatal errors only when link is functional */
5435 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5436 /* block commands from scsi mid-layer */
38135535 5437 ufshcd_scsi_block_requests(hba);
e8e7f271 5438
141f8165 5439 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5440
5441 /* dump controller state before resetting */
5442 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5443 bool pr_prdt = !!(hba->saved_err &
5444 SYSTEM_BUS_FATAL_ERROR);
5445
5446 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5447 __func__, hba->saved_err,
5448 hba->saved_uic_err);
5449
5450 ufshcd_print_host_regs(hba);
5451 ufshcd_print_pwr_info(hba);
5452 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5453 ufshcd_print_trs(hba, hba->outstanding_reqs,
5454 pr_prdt);
5455 }
e8e7f271
SRT		 5456 schedule_work(&hba->eh_work);
5457 }
3441da7d 5458 }
e8e7f271
SRT		 5459 /*
5460 * if (!queue_eh_work) -
5461 * Other errors are either non-fatal where host recovers
5462 * itself without s/w intervention or errors that will be
5463 * handled by the SCSI core layer.
5464 */
7a3e97b0
SY		 5465}
5466
5467/**
5468 * ufshcd_tmc_handler - handle task management function completion
5469 * @hba: per adapter instance
5470 */
5471static void ufshcd_tmc_handler(struct ufs_hba *hba)
5472{
5473 u32 tm_doorbell;
5474
b873a275 5475 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5476 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5477 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5478}
5479
5480/**
5481 * ufshcd_sl_intr - Interrupt service routine
5482 * @hba: per adapter instance
5483 * @intr_status: contains interrupts generated by the controller
5484 */
5485static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5486{
5487 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5488 if (hba->errors)
e8e7f271 5489 ufshcd_check_errors(hba);
7a3e97b0 5490
53b3d9c3
SJ		 5491 if (intr_status & UFSHCD_UIC_MASK)
5492 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5493
5494 if (intr_status & UTP_TASK_REQ_COMPL)
5495 ufshcd_tmc_handler(hba);
5496
5497 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5498 ufshcd_transfer_req_compl(hba);
5499}
5500
5501/**
5502 * ufshcd_intr - Main interrupt service routine
5503 * @irq: irq number
5504 * @__hba: pointer to adapter instance
5505 *
5506 * Returns IRQ_HANDLED - If interrupt is valid
5507 * IRQ_NONE - If invalid interrupt
5508 */
5509static irqreturn_t ufshcd_intr(int irq, void *__hba)
5510{
d75f7fe4 5511 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5512 irqreturn_t retval = IRQ_NONE;
5513 struct ufs_hba *hba = __hba;
7f6ba4f1 5514 int retries = hba->nutrs;
7a3e97b0
SY		 5515
5516 spin_lock(hba->host->host_lock);
b873a275 5517 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5518
7f6ba4f1
VG		 5519 /*
5520 * There could be max of hba->nutrs reqs in flight and in worst case
5521 * if the reqs get finished 1 by 1 after the interrupt status is
5522 * read, make sure we handle them by checking the interrupt status
5523 * again in a loop until we process all of the reqs before returning.
5524 */
5525 do {
5526 enabled_intr_status =
5527 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5528 if (intr_status)
5529 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5530 if (enabled_intr_status) {
5531 ufshcd_sl_intr(hba, enabled_intr_status);
5532 retval = IRQ_HANDLED;
5533 }
5534
5535 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5536 } while (intr_status && --retries);
d75f7fe4 5537
7a3e97b0
SY		 5538 spin_unlock(hba->host->host_lock);
5539 return retval;
5540}
5541
e2933132
SRT		 5542static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5543{
5544 int err = 0;
5545 u32 mask = 1 << tag;
5546 unsigned long flags;
5547
5548 if (!test_bit(tag, &hba->outstanding_tasks))
5549 goto out;
5550
5551 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5552 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5553 spin_unlock_irqrestore(hba->host->host_lock, flags);
5554
5555 /* poll for max. 1 sec to clear door bell register by h/w */
5556 err = ufshcd_wait_for_register(hba,
5557 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5558 mask, 0, 1000, 1000, true);
e2933132
SRT		 5559out:
5560 return err;
5561}
5562
c6049cd9
CH		 5563static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5564 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5565{
c6049cd9 5566 struct Scsi_Host *host = hba->host;
7a3e97b0 5567 unsigned long flags;
c6049cd9 5568 int free_slot, task_tag, err;
7a3e97b0 5569
e2933132
SRT		 5570 /*
5571 * Get free slot, sleep if slots are unavailable.
5572 * Even though we use wait_event() which sleeps indefinitely,
5573 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5574 */
5575 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5576 ufshcd_hold(hba, false);
7a3e97b0 5577
e2933132 5578 spin_lock_irqsave(host->host_lock, flags);
e2933132 5579 task_tag = hba->nutrs + free_slot;
7a3e97b0 5580
c6049cd9
CH		 5581 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5582
5583 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5584 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5585
7a3e97b0
SY		 5586 /* send command to the controller */
5587 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5588
5589 /* Make sure descriptors are ready before ringing the task doorbell */
5590 wmb();
5591
b873a275 5592 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5593 /* Make sure that doorbell is committed immediately */
5594 wmb();
7a3e97b0
SY		 5595
5596 spin_unlock_irqrestore(host->host_lock, flags);
5597
6667e6d9
OS		 5598 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5599
7a3e97b0 5600 /* wait until the task management command is completed */
e2933132
SRT		 5601 err = wait_event_timeout(hba->tm_wq,
5602 test_bit(free_slot, &hba->tm_condition),
5603 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5604 if (!err) {
6667e6d9 5605 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5606 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5607 __func__, tm_function);
5608 if (ufshcd_clear_tm_cmd(hba, free_slot))
5609 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5610 __func__, free_slot);
5611 err = -ETIMEDOUT;
5612 } else {
c6049cd9
CH		 5613 err = 0;
5614 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5615
6667e6d9 5616 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
c6049cd9
CH		 5617
5618 spin_lock_irqsave(hba->host->host_lock, flags);
5619 __clear_bit(free_slot, &hba->outstanding_tasks);
5620 spin_unlock_irqrestore(hba->host->host_lock, flags);
5621
7a3e97b0 5622 }
e2933132 5623
7a3e97b0 5624 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5625 ufshcd_put_tm_slot(hba, free_slot);
5626 wake_up(&hba->tm_tag_wq);
5627
1ab27c9c 5628 ufshcd_release(hba);
7a3e97b0
SY		 5629 return err;
5630}
5631
c6049cd9
CH		 5632/**
5633 * ufshcd_issue_tm_cmd - issues task management commands to controller
5634 * @hba: per adapter instance
5635 * @lun_id: LUN ID to which TM command is sent
5636 * @task_id: task ID to which the TM command is applicable
5637 * @tm_function: task management function opcode
5638 * @tm_response: task management service response return value
5639 *
5640 * Returns non-zero value on error, zero on success.
5641 */
5642static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5643 u8 tm_function, u8 *tm_response)
5644{
5645 struct utp_task_req_desc treq = { { 0 }, };
5646 int ocs_value, err;
5647
5648 /* Configure task request descriptor */
5649 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5650 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5651
5652 /* Configure task request UPIU */
5653 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5654 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5655 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5656
5657 /*
5658 * The host shall provide the same value for LUN field in the basic
5659 * header and for Input Parameter.
5660 */
5661 treq.input_param1 = cpu_to_be32(lun_id);
5662 treq.input_param2 = cpu_to_be32(task_id);
5663
5664 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5665 if (err == -ETIMEDOUT)
5666 return err;
5667
5668 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5669 if (ocs_value != OCS_SUCCESS)
5670 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5671 __func__, ocs_value);
5672 else if (tm_response)
5673 *tm_response = be32_to_cpu(treq.output_param1) &
5674 MASK_TM_SERVICE_RESP;
5675 return err;
5676}
5677
5e0a86ee
AA		 5678/**
5679 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
5680 * @hba: per-adapter instance
5681 * @req_upiu: upiu request
5682 * @rsp_upiu: upiu reply
5683 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
5684 * @desc_buff: pointer to descriptor buffer, NULL if NA
5685 * @buff_len: descriptor size, 0 if NA
5686 * @desc_op: descriptor operation
5687 *
5688 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
5689 * Therefore, it "rides" the device management infrastructure: uses its tag and
5690 * tasks work queues.
5691 *
5692 * Since there is only one available tag for device management commands,
5693 * the caller is expected to hold the hba->dev_cmd.lock mutex.
5694 */
5695static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
5696 struct utp_upiu_req *req_upiu,
5697 struct utp_upiu_req *rsp_upiu,
5698 u8 *desc_buff, int *buff_len,
5699 int cmd_type,
5700 enum query_opcode desc_op)
5701{
5702 struct ufshcd_lrb *lrbp;
5703 int err = 0;
5704 int tag;
5705 struct completion wait;
5706 unsigned long flags;
5707 u32 upiu_flags;
5708
5709 down_read(&hba->clk_scaling_lock);
5710
5711 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
5712
5713 init_completion(&wait);
5714 lrbp = &hba->lrb[tag];
5715 WARN_ON(lrbp->cmd);
5716
5717 lrbp->cmd = NULL;
5718 lrbp->sense_bufflen = 0;
5719 lrbp->sense_buffer = NULL;
5720 lrbp->task_tag = tag;
5721 lrbp->lun = 0;
5722 lrbp->intr_cmd = true;
5723 hba->dev_cmd.type = cmd_type;
5724
5725 switch (hba->ufs_version) {
5726 case UFSHCI_VERSION_10:
5727 case UFSHCI_VERSION_11:
5728 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
5729 break;
5730 default:
5731 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5732 break;
5733 }
5734
5735 /* update the task tag in the request upiu */
5736 req_upiu->header.dword_0 |= cpu_to_be32(tag);
5737
5738 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
5739
5740 /* just copy the upiu request as it is */
5741 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
5742 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
5743 /* The Data Segment Area is optional depending upon the query
5744 * function value. for WRITE DESCRIPTOR, the data segment
5745 * follows right after the tsf.
5746 */
5747 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
5748 *buff_len = 0;
5749 }
5750
5751 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5752
5753 hba->dev_cmd.complete = &wait;
5754
5755 /* Make sure descriptors are ready before ringing the doorbell */
5756 wmb();
5757 spin_lock_irqsave(hba->host->host_lock, flags);
5758 ufshcd_send_command(hba, tag);
5759 spin_unlock_irqrestore(hba->host->host_lock, flags);
5760
5761 /*
5762 * ignore the returning value here - ufshcd_check_query_response is
5763 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
5764 * read the response directly ignoring all errors.
5765 */
5766 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
5767
5768 /* just copy the upiu response as it is */
5769 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
5770
5771 ufshcd_put_dev_cmd_tag(hba, tag);
5772 wake_up(&hba->dev_cmd.tag_wq);
5773 up_read(&hba->clk_scaling_lock);
5774 return err;
5775}
5776
5777/**
5778 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
5779 * @hba: per-adapter instance
5780 * @req_upiu: upiu request
5781 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
5782 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
5783 * @desc_buff: pointer to descriptor buffer, NULL if NA
5784 * @buff_len: descriptor size, 0 if NA
5785 * @desc_op: descriptor operation
5786 *
5787 * Supports UTP Transfer requests (nop and query), and UTP Task
5788 * Management requests.
5789 * It is up to the caller to fill the upiu conent properly, as it will
5790 * be copied without any further input validations.
5791 */
5792int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
5793 struct utp_upiu_req *req_upiu,
5794 struct utp_upiu_req *rsp_upiu,
5795 int msgcode,
5796 u8 *desc_buff, int *buff_len,
5797 enum query_opcode desc_op)
5798{
5799 int err;
5800 int cmd_type = DEV_CMD_TYPE_QUERY;
5801 struct utp_task_req_desc treq = { { 0 }, };
5802 int ocs_value;
5803 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
5804
5805 if (desc_buff && desc_op != UPIU_QUERY_OPCODE_WRITE_DESC) {
5806 err = -ENOTSUPP;
5807 goto out;
5808 }
5809
5810 switch (msgcode) {
5811 case UPIU_TRANSACTION_NOP_OUT:
5812 cmd_type = DEV_CMD_TYPE_NOP;
5813 /* fall through */
5814 case UPIU_TRANSACTION_QUERY_REQ:
5815 ufshcd_hold(hba, false);
5816 mutex_lock(&hba->dev_cmd.lock);
5817 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
5818 desc_buff, buff_len,
5819 cmd_type, desc_op);
5820 mutex_unlock(&hba->dev_cmd.lock);
5821 ufshcd_release(hba);
5822
5823 break;
5824 case UPIU_TRANSACTION_TASK_REQ:
5825 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5826 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5827
5828 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
5829
5830 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
5831 if (err == -ETIMEDOUT)
5832 break;
5833
5834 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5835 if (ocs_value != OCS_SUCCESS) {
5836 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
5837 ocs_value);
5838 break;
5839 }
5840
5841 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
5842
5843 break;
5844 default:
5845 err = -EINVAL;
5846
5847 break;
5848 }
5849
5850out:
5851 return err;
5852}
5853
7a3e97b0 5854/**
3441da7d
SRT		 5855 * ufshcd_eh_device_reset_handler - device reset handler registered to
5856 * scsi layer.
7a3e97b0
SY		 5857 * @cmd: SCSI command pointer
5858 *
5859 * Returns SUCCESS/FAILED
5860 */
3441da7d 5861static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5862{
5863 struct Scsi_Host *host;
5864 struct ufs_hba *hba;
5865 unsigned int tag;
5866 u32 pos;
5867 int err;
e2933132
SRT		 5868 u8 resp = 0xF;
5869 struct ufshcd_lrb *lrbp;
3441da7d 5870 unsigned long flags;
7a3e97b0
SY		 5871
5872 host = cmd->device->host;
5873 hba = shost_priv(host);
5874 tag = cmd->request->tag;
5875
e2933132
SRT		 5876 lrbp = &hba->lrb[tag];
5877 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5878 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5879 if (!err)
5880 err = resp;
7a3e97b0 5881 goto out;
e2933132 5882 }
7a3e97b0 5883
3441da7d
SRT		 5884 /* clear the commands that were pending for corresponding LUN */
5885 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5886 if (hba->lrb[pos].lun == lrbp->lun) {
5887 err = ufshcd_clear_cmd(hba, pos);
5888 if (err)
5889 break;
7a3e97b0 5890 }
3441da7d
SRT		 5891 }
5892 spin_lock_irqsave(host->host_lock, flags);
5893 ufshcd_transfer_req_compl(hba);
5894 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5895
7a3e97b0 5896out:
7fabb77b 5897 hba->req_abort_count = 0;
3441da7d
SRT		 5898 if (!err) {
5899 err = SUCCESS;
5900 } else {
5901 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5902 err = FAILED;
5903 }
7a3e97b0
SY		 5904 return err;
5905}
5906
e0b299e3
GB		 5907static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5908{
5909 struct ufshcd_lrb *lrbp;
5910 int tag;
5911
5912 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5913 lrbp = &hba->lrb[tag];
5914 lrbp->req_abort_skip = true;
5915 }
5916}
5917
7a3e97b0
SY		 5918/**
5919 * ufshcd_abort - abort a specific command
5920 * @cmd: SCSI command pointer
5921 *
f20810d8
SRT		 5922 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5923 * command, and in host controller by clearing the door-bell register. There can
5924 * be race between controller sending the command to the device while abort is
5925 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5926 * really issued and then try to abort it.
5927 *
7a3e97b0
SY		 5928 * Returns SUCCESS/FAILED
5929 */
5930static int ufshcd_abort(struct scsi_cmnd *cmd)
5931{
5932 struct Scsi_Host *host;
5933 struct ufs_hba *hba;
5934 unsigned long flags;
5935 unsigned int tag;
f20810d8
SRT		 5936 int err = 0;
5937 int poll_cnt;
e2933132
SRT		 5938 u8 resp = 0xF;
5939 struct ufshcd_lrb *lrbp;
e9d501b1 5940 u32 reg;
7a3e97b0
SY		 5941
5942 host = cmd->device->host;
5943 hba = shost_priv(host);
5944 tag = cmd->request->tag;
e7d38257 5945 lrbp = &hba->lrb[tag];
14497328
YG		 5946 if (!ufshcd_valid_tag(hba, tag)) {
5947 dev_err(hba->dev,
5948 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5949 __func__, tag, cmd, cmd->request);
5950 BUG();
5951 }
7a3e97b0 5952
e7d38257
DR		 5953 /*
5954 * Task abort to the device W-LUN is illegal. When this command
5955 * will fail, due to spec violation, scsi err handling next step
5956 * will be to send LU reset which, again, is a spec violation.
5957 * To avoid these unnecessary/illegal step we skip to the last error
5958 * handling stage: reset and restore.
5959 */
5960 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5961 return ufshcd_eh_host_reset_handler(cmd);
5962
1ab27c9c 5963 ufshcd_hold(hba, false);
14497328 5964 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5965 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5966 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5967 dev_err(hba->dev,
5968 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5969 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5970 goto out;
14497328 5971 }
7a3e97b0 5972
e9d501b1
DR		 5973 if (!(reg & (1 << tag))) {
5974 dev_err(hba->dev,
5975 "%s: cmd was completed, but without a notifying intr, tag = %d",
5976 __func__, tag);
5977 }
5978
66cc820f
DR		 5979 /* Print Transfer Request of aborted task */
5980 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5981
7fabb77b
GB		 5982 /*
5983 * Print detailed info about aborted request.
5984 * As more than one request might get aborted at the same time,
5985 * print full information only for the first aborted request in order
5986 * to reduce repeated printouts. For other aborted requests only print
5987 * basic details.
5988 */
5989 scsi_print_command(hba->lrb[tag].cmd);
5990 if (!hba->req_abort_count) {
5991 ufshcd_print_host_regs(hba);
6ba65588 5992 ufshcd_print_host_state(hba);
7fabb77b
GB		 5993 ufshcd_print_pwr_info(hba);
5994 ufshcd_print_trs(hba, 1 << tag, true);
5995 } else {
5996 ufshcd_print_trs(hba, 1 << tag, false);
5997 }
5998 hba->req_abort_count++;
e0b299e3
GB		 5999
6000 /* Skip task abort in case previous aborts failed and report failure */
6001 if (lrbp->req_abort_skip) {
6002 err = -EIO;
6003 goto out;
6004 }
6005
f20810d8
SRT		 6006 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6007 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6008 UFS_QUERY_TASK, &resp);
6009 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6010 /* cmd pending in the device */
ff8e20c6
DR		 6011 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6012 __func__, tag);
f20810d8
SRT		 6013 break;
6014 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6015 /*
6016 * cmd not pending in the device, check if it is
6017 * in transition.
6018 */
ff8e20c6
DR		 6019 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6020 __func__, tag);
f20810d8
SRT		 6021 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6022 if (reg & (1 << tag)) {
6023 /* sleep for max. 200us to stabilize */
6024 usleep_range(100, 200);
6025 continue;
6026 }
6027 /* command completed already */
ff8e20c6
DR		 6028 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6029 __func__, tag);
f20810d8
SRT		 6030 goto out;
6031 } else {
ff8e20c6
DR		 6032 dev_err(hba->dev,
6033 "%s: no response from device. tag = %d, err %d\n",
6034 __func__, tag, err);
f20810d8
SRT		 6035 if (!err)
6036 err = resp; /* service response error */
6037 goto out;
6038 }
6039 }
6040
6041 if (!poll_cnt) {
6042 err = -EBUSY;
7a3e97b0
SY		 6043 goto out;
6044 }
7a3e97b0 6045
e2933132
SRT		 6046 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6047 UFS_ABORT_TASK, &resp);
6048 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6049 if (!err) {
f20810d8 6050 err = resp; /* service response error */
ff8e20c6
DR		 6051 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6052 __func__, tag, err);
6053 }
7a3e97b0 6054 goto out;
e2933132 6055 }
7a3e97b0 6056
f20810d8 6057 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6058 if (err) {
6059 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6060 __func__, tag, err);
f20810d8 6061 goto out;
ff8e20c6 6062 }
f20810d8 6063
7a3e97b0
SY		 6064 scsi_dma_unmap(cmd);
6065
6066 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6067 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6068 hba->lrb[tag].cmd = NULL;
6069 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 6070
6071 clear_bit_unlock(tag, &hba->lrb_in_use);
6072 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 6073
7a3e97b0 6074out:
f20810d8
SRT		 6075 if (!err) {
6076 err = SUCCESS;
6077 } else {
6078 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6079 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6080 err = FAILED;
6081 }
6082
1ab27c9c
ST		 6083 /*
6084 * This ufshcd_release() corresponds to the original scsi cmd that got
6085 * aborted here (as we won't get any IRQ for it).
6086 */
6087 ufshcd_release(hba);
7a3e97b0
SY		 6088 return err;
6089}
6090
3441da7d
SRT		 6091/**
6092 * ufshcd_host_reset_and_restore - reset and restore host controller
6093 * @hba: per-adapter instance
6094 *
6095 * Note that host controller reset may issue DME_RESET to
6096 * local and remote (device) Uni-Pro stack and the attributes
6097 * are reset to default state.
6098 *
6099 * Returns zero on success, non-zero on failure
6100 */
6101static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6102{
6103 int err;
3441da7d
SRT		 6104 unsigned long flags;
6105
6106 /* Reset the host controller */
6107 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 6108 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 6109 spin_unlock_irqrestore(hba->host->host_lock, flags);
6110
a3cd5ec5 6111 /* scale up clocks to max frequency before full reinitialization */
6112 ufshcd_scale_clks(hba, true);
6113
3441da7d
SRT		 6114 err = ufshcd_hba_enable(hba);
6115 if (err)
6116 goto out;
6117
6118 /* Establish the link again and restore the device */
1d337ec2
SRT		 6119 err = ufshcd_probe_hba(hba);
6120
6121 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 6122 err = -EIO;
6123out:
6124 if (err)
6125 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
6126
6127 return err;
6128}
6129
6130/**
6131 * ufshcd_reset_and_restore - reset and re-initialize host/device
6132 * @hba: per-adapter instance
6133 *
6134 * Reset and recover device, host and re-establish link. This
6135 * is helpful to recover the communication in fatal error conditions.
6136 *
6137 * Returns zero on success, non-zero on failure
6138 */
6139static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6140{
6141 int err = 0;
6142 unsigned long flags;
1d337ec2 6143 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6144
1d337ec2
SRT		 6145 do {
6146 err = ufshcd_host_reset_and_restore(hba);
6147 } while (err && --retries);
3441da7d
SRT		 6148
6149 /*
6150 * After reset the door-bell might be cleared, complete
6151 * outstanding requests in s/w here.
6152 */
6153 spin_lock_irqsave(hba->host->host_lock, flags);
6154 ufshcd_transfer_req_compl(hba);
6155 ufshcd_tmc_handler(hba);
6156 spin_unlock_irqrestore(hba->host->host_lock, flags);
6157
6158 return err;
6159}
6160
6161/**
6162 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6163 * @cmd: SCSI command pointer
3441da7d
SRT		 6164 *
6165 * Returns SUCCESS/FAILED
6166 */
6167static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6168{
6169 int err;
6170 unsigned long flags;
6171 struct ufs_hba *hba;
6172
6173 hba = shost_priv(cmd->device->host);
6174
1ab27c9c 6175 ufshcd_hold(hba, false);
3441da7d
SRT		 6176 /*
6177 * Check if there is any race with fatal error handling.
6178 * If so, wait for it to complete. Even though fatal error
6179 * handling does reset and restore in some cases, don't assume
6180 * anything out of it. We are just avoiding race here.
6181 */
6182 do {
6183 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6184 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6185 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6186 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6187 break;
6188 spin_unlock_irqrestore(hba->host->host_lock, flags);
6189 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6190 flush_work(&hba->eh_work);
3441da7d
SRT		 6191 } while (1);
6192
6193 hba->ufshcd_state = UFSHCD_STATE_RESET;
6194 ufshcd_set_eh_in_progress(hba);
6195 spin_unlock_irqrestore(hba->host->host_lock, flags);
6196
6197 err = ufshcd_reset_and_restore(hba);
6198
6199 spin_lock_irqsave(hba->host->host_lock, flags);
6200 if (!err) {
6201 err = SUCCESS;
6202 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6203 } else {
6204 err = FAILED;
6205 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6206 }
6207 ufshcd_clear_eh_in_progress(hba);
6208 spin_unlock_irqrestore(hba->host->host_lock, flags);
6209
1ab27c9c 6210 ufshcd_release(hba);
3441da7d
SRT		 6211 return err;
6212}
6213
3a4bf06d
YG		 6214/**
6215 * ufshcd_get_max_icc_level - calculate the ICC level
6216 * @sup_curr_uA: max. current supported by the regulator
6217 * @start_scan: row at the desc table to start scan from
6218 * @buff: power descriptor buffer
6219 *
6220 * Returns calculated max ICC level for specific regulator
6221 */
6222static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6223{
6224 int i;
6225 int curr_uA;
6226 u16 data;
6227 u16 unit;
6228
6229 for (i = start_scan; i >= 0; i--) {
d79713f9 6230 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6231 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6232 ATTR_ICC_LVL_UNIT_OFFSET;
6233 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6234 switch (unit) {
6235 case UFSHCD_NANO_AMP:
6236 curr_uA = curr_uA / 1000;
6237 break;
6238 case UFSHCD_MILI_AMP:
6239 curr_uA = curr_uA * 1000;
6240 break;
6241 case UFSHCD_AMP:
6242 curr_uA = curr_uA * 1000 * 1000;
6243 break;
6244 case UFSHCD_MICRO_AMP:
6245 default:
6246 break;
6247 }
6248 if (sup_curr_uA >= curr_uA)
6249 break;
6250 }
6251 if (i < 0) {
6252 i = 0;
6253 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6254 }
6255
6256 return (u32)i;
6257}
6258
6259/**
6260 * ufshcd_calc_icc_level - calculate the max ICC level
6261 * In case regulators are not initialized we'll return 0
6262 * @hba: per-adapter instance
6263 * @desc_buf: power descriptor buffer to extract ICC levels from.
6264 * @len: length of desc_buff
6265 *
6266 * Returns calculated ICC level
6267 */
6268static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6269 u8 *desc_buf, int len)
6270{
6271 u32 icc_level = 0;
6272
6273 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6274 !hba->vreg_info.vccq2) {
6275 dev_err(hba->dev,
6276 "%s: Regulator capability was not set, actvIccLevel=%d",
6277 __func__, icc_level);
6278 goto out;
6279 }
6280
6281 if (hba->vreg_info.vcc)
6282 icc_level = ufshcd_get_max_icc_level(
6283 hba->vreg_info.vcc->max_uA,
6284 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6285 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6286
6287 if (hba->vreg_info.vccq)
6288 icc_level = ufshcd_get_max_icc_level(
6289 hba->vreg_info.vccq->max_uA,
6290 icc_level,
6291 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6292
6293 if (hba->vreg_info.vccq2)
6294 icc_level = ufshcd_get_max_icc_level(
6295 hba->vreg_info.vccq2->max_uA,
6296 icc_level,
6297 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6298out:
6299 return icc_level;
6300}
6301
6302static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6303{
6304 int ret;
a4b0e8a4 6305 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a
KC		 6306 u8 *desc_buf;
6307
6308 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6309 if (!desc_buf)
6310 return;
3a4bf06d
YG		 6311
6312 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6313 if (ret) {
6314 dev_err(hba->dev,
6315 "%s: Failed reading power descriptor.len = %d ret = %d",
6316 __func__, buff_len, ret);
bbe21d7a 6317 goto out;
3a4bf06d
YG		 6318 }
6319
6320 hba->init_prefetch_data.icc_level =
6321 ufshcd_find_max_sup_active_icc_level(hba,
6322 desc_buf, buff_len);
6323 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6324 __func__, hba->init_prefetch_data.icc_level);
6325
dbd34a61
SM		 6326 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6327 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6328 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6329
6330 if (ret)
6331 dev_err(hba->dev,
6332 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6333 __func__, hba->init_prefetch_data.icc_level , ret);
6334
bbe21d7a
KC		 6335out:
6336 kfree(desc_buf);
3a4bf06d
YG		 6337}
6338
2a8fa600
SJ		 6339/**
6340 * ufshcd_scsi_add_wlus - Adds required W-LUs
6341 * @hba: per-adapter instance
6342 *
6343 * UFS device specification requires the UFS devices to support 4 well known
6344 * logical units:
6345 * "REPORT_LUNS" (address: 01h)
6346 * "UFS Device" (address: 50h)
6347 * "RPMB" (address: 44h)
6348 * "BOOT" (address: 30h)
6349 * UFS device's power management needs to be controlled by "POWER CONDITION"
6350 * field of SSU (START STOP UNIT) command. But this "power condition" field
6351 * will take effect only when its sent to "UFS device" well known logical unit
6352 * hence we require the scsi_device instance to represent this logical unit in
6353 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6354 *
2a8fa600
SJ		 6355 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6356 * Block) LU so user space process can control this LU. User space may also
6357 * want to have access to BOOT LU.
8aa29f19 6358 *
2a8fa600
SJ		 6359 * This function adds scsi device instances for each of all well known LUs
6360 * (except "REPORT LUNS" LU).
6361 *
6362 * Returns zero on success (all required W-LUs are added successfully),
6363 * non-zero error value on failure (if failed to add any of the required W-LU).
6364 */
6365static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6366{
6367 int ret = 0;
7c48bfd0
AM		 6368 struct scsi_device *sdev_rpmb;
6369 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6370
6371 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6372 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6373 if (IS_ERR(hba->sdev_ufs_device)) {
6374 ret = PTR_ERR(hba->sdev_ufs_device);
6375 hba->sdev_ufs_device = NULL;
6376 goto out;
6377 }
7c48bfd0 6378 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6379
7c48bfd0 6380 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6381 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6382 if (IS_ERR(sdev_rpmb)) {
6383 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6384 goto remove_sdev_ufs_device;
2a8fa600 6385 }
7c48bfd0 6386 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6387
6388 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6389 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6390 if (IS_ERR(sdev_boot))
6391 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6392 else
6393 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6394 goto out;
6395
2a8fa600
SJ		 6396remove_sdev_ufs_device:
6397 scsi_remove_device(hba->sdev_ufs_device);
6398out:
6399 return ret;
6400}
6401
93fdd5ac
TW		 6402static int ufs_get_device_desc(struct ufs_hba *hba,
6403 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6404{
6405 int err;
bbe21d7a 6406 size_t buff_len;
c58ab7aa 6407 u8 model_index;
bbe21d7a
KC		 6408 u8 *desc_buf;
6409
6410 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6411 QUERY_DESC_MAX_SIZE + 1);
6412 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6413 if (!desc_buf) {
6414 err = -ENOMEM;
6415 goto out;
6416 }
c58ab7aa 6417
a4b0e8a4 6418 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6419 if (err) {
6420 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6421 __func__, err);
6422 goto out;
6423 }
6424
6425 /*
6426 * getting vendor (manufacturerID) and Bank Index in big endian
6427 * format
6428 */
93fdd5ac 6429 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6430 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6431
6432 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6433
bbe21d7a
KC		 6434 /* Zero-pad entire buffer for string termination. */
6435 memset(desc_buf, 0, buff_len);
6436
6437 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
8aa29f19 6438 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
c58ab7aa
YG		 6439 if (err) {
6440 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6441 __func__, err);
6442 goto out;
6443 }
6444
bbe21d7a
KC		 6445 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
6446 strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
6447 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
c58ab7aa
YG		 6448 MAX_MODEL_LEN));
6449
6450 /* Null terminate the model string */
93fdd5ac 6451 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6452
6453out:
bbe21d7a 6454 kfree(desc_buf);
c58ab7aa
YG		 6455 return err;
6456}
6457
93fdd5ac
TW		 6458static void ufs_fixup_device_setup(struct ufs_hba *hba,
6459 struct ufs_dev_desc *dev_desc)
c58ab7aa 6460{
c58ab7aa 6461 struct ufs_dev_fix *f;
c58ab7aa
YG		 6462
6463 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6464 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6465 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6466 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6467 !strcmp(f->card.model, UFS_ANY_MODEL)))
6468 hba->dev_quirks |= f->quirk;
6469 }
6470}
6471
37113106
YG		 6472/**
6473 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6474 * @hba: per-adapter instance
6475 *
6476 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6477 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6478 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6479 * the hibern8 exit latency.
6480 *
6481 * Returns zero on success, non-zero error value on failure.
6482 */
6483static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6484{
6485 int ret = 0;
6486 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6487
6488 ret = ufshcd_dme_peer_get(hba,
6489 UIC_ARG_MIB_SEL(
6490 RX_MIN_ACTIVATETIME_CAPABILITY,
6491 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6492 &peer_rx_min_activatetime);
6493 if (ret)
6494 goto out;
6495
6496 /* make sure proper unit conversion is applied */
6497 tuned_pa_tactivate =
6498 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6499 / PA_TACTIVATE_TIME_UNIT_US);
6500 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6501 tuned_pa_tactivate);
6502
6503out:
6504 return ret;
6505}
6506
6507/**
6508 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6509 * @hba: per-adapter instance
6510 *
6511 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6512 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6513 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6514 * This optimal value can help reduce the hibern8 exit latency.
6515 *
6516 * Returns zero on success, non-zero error value on failure.
6517 */
6518static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6519{
6520 int ret = 0;
6521 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6522 u32 max_hibern8_time, tuned_pa_hibern8time;
6523
6524 ret = ufshcd_dme_get(hba,
6525 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6526 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6527 &local_tx_hibern8_time_cap);
6528 if (ret)
6529 goto out;
6530
6531 ret = ufshcd_dme_peer_get(hba,
6532 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6533 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6534 &peer_rx_hibern8_time_cap);
6535 if (ret)
6536 goto out;
6537
6538 max_hibern8_time = max(local_tx_hibern8_time_cap,
6539 peer_rx_hibern8_time_cap);
6540 /* make sure proper unit conversion is applied */
6541 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6542 / PA_HIBERN8_TIME_UNIT_US);
6543 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6544 tuned_pa_hibern8time);
6545out:
6546 return ret;
6547}
6548
c6a6db43 6549/**
6550 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6551 * less than device PA_TACTIVATE time.
6552 * @hba: per-adapter instance
6553 *
6554 * Some UFS devices require host PA_TACTIVATE to be lower than device
6555 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6556 * for such devices.
6557 *
6558 * Returns zero on success, non-zero error value on failure.
6559 */
6560static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6561{
6562 int ret = 0;
6563 u32 granularity, peer_granularity;
6564 u32 pa_tactivate, peer_pa_tactivate;
6565 u32 pa_tactivate_us, peer_pa_tactivate_us;
6566 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6567
6568 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6569 &granularity);
6570 if (ret)
6571 goto out;
6572
6573 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6574 &peer_granularity);
6575 if (ret)
6576 goto out;
6577
6578 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6579 (granularity > PA_GRANULARITY_MAX_VAL)) {
6580 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6581 __func__, granularity);
6582 return -EINVAL;
6583 }
6584
6585 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6586 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6587 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6588 __func__, peer_granularity);
6589 return -EINVAL;
6590 }
6591
6592 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6593 if (ret)
6594 goto out;
6595
6596 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6597 &peer_pa_tactivate);
6598 if (ret)
6599 goto out;
6600
6601 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6602 peer_pa_tactivate_us = peer_pa_tactivate *
6603 gran_to_us_table[peer_granularity - 1];
6604
6605 if (pa_tactivate_us > peer_pa_tactivate_us) {
6606 u32 new_peer_pa_tactivate;
6607
6608 new_peer_pa_tactivate = pa_tactivate_us /
6609 gran_to_us_table[peer_granularity - 1];
6610 new_peer_pa_tactivate++;
6611 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6612 new_peer_pa_tactivate);
6613 }
6614
6615out:
6616 return ret;
6617}
6618
37113106
YG		 6619static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6620{
6621 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6622 ufshcd_tune_pa_tactivate(hba);
6623 ufshcd_tune_pa_hibern8time(hba);
6624 }
6625
6626 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6627 /* set 1ms timeout for PA_TACTIVATE */
6628 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 6629
6630 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6631 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6632
6633 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6634}
6635
ff8e20c6
DR		 6636static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6637{
6638 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6639
6640 hba->ufs_stats.hibern8_exit_cnt = 0;
6641 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6642
6643 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6644 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6645 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6646 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6647 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6648
6649 hba->req_abort_count = 0;
ff8e20c6
DR		 6650}
6651
a4b0e8a4
PM		 6652static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6653{
6654 int err;
6655
6656 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6657 &hba->desc_size.dev_desc);
6658 if (err)
6659 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6660
6661 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6662 &hba->desc_size.pwr_desc);
6663 if (err)
6664 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6665
6666 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6667 &hba->desc_size.interc_desc);
6668 if (err)
6669 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6670
6671 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6672 &hba->desc_size.conf_desc);
6673 if (err)
6674 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6675
6676 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6677 &hba->desc_size.unit_desc);
6678 if (err)
6679 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6680
6681 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6682 &hba->desc_size.geom_desc);
6683 if (err)
6684 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2
SN		 6685 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6686 &hba->desc_size.hlth_desc);
6687 if (err)
6688 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6689}
6690
6691static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6692{
6693 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6694 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6695 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6696 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6697 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6698 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2 6699 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6700}
6701
6ccf44fe 6702/**
1d337ec2
SRT		 6703 * ufshcd_probe_hba - probe hba to detect device and initialize
6704 * @hba: per-adapter instance
6705 *
6706 * Execute link-startup and verify device initialization
6ccf44fe 6707 */
1d337ec2 6708static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6709{
93fdd5ac 6710 struct ufs_dev_desc card = {0};
6ccf44fe 6711 int ret;
7ff5ab47 6712 ktime_t start = ktime_get();
6ccf44fe
SJ		 6713
6714 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6715 if (ret)
6716 goto out;
6717
afdfff59
YG		 6718 /* set the default level for urgent bkops */
6719 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6720 hba->is_urgent_bkops_lvl_checked = false;
6721
ff8e20c6
DR		 6722 /* Debug counters initialization */
6723 ufshcd_clear_dbg_ufs_stats(hba);
6724
57d104c1
SJ		 6725 /* UniPro link is active now */
6726 ufshcd_set_link_active(hba);
d3e89bac 6727
ad448378
AH		 6728 /* Enable Auto-Hibernate if configured */
6729 ufshcd_auto_hibern8_enable(hba);
6730
5a0b0cb9
SRT		 6731 ret = ufshcd_verify_dev_init(hba);
6732 if (ret)
6733 goto out;
68078d5c
DR		 6734
6735 ret = ufshcd_complete_dev_init(hba);
6736 if (ret)
6737 goto out;
5a0b0cb9 6738
a4b0e8a4
PM		 6739 /* Init check for device descriptor sizes */
6740 ufshcd_init_desc_sizes(hba);
6741
93fdd5ac
TW		 6742 ret = ufs_get_device_desc(hba, &card);
6743 if (ret) {
6744 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6745 __func__, ret);
6746 goto out;
6747 }
6748
6749 ufs_fixup_device_setup(hba, &card);
37113106 6750 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6751
6752 ret = ufshcd_set_vccq_rail_unused(hba,
6753 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6754 if (ret)
6755 goto out;
6756
57d104c1
SJ		 6757 /* UFS device is also active now */
6758 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6759 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6760 hba->wlun_dev_clr_ua = true;
6761
7eb584db
DR		 6762 if (ufshcd_get_max_pwr_mode(hba)) {
6763 dev_err(hba->dev,
6764 "%s: Failed getting max supported power mode\n",
6765 __func__);
6766 } else {
6767 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6768 if (ret) {
7eb584db
DR		 6769 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6770 __func__, ret);
8643ae66
DL		 6771 goto out;
6772 }
7eb584db 6773 }
57d104c1 6774
53c12d0e
YG		 6775 /* set the state as operational after switching to desired gear */
6776 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6777
57d104c1
SJ		 6778 /*
6779 * If we are in error handling context or in power management callbacks
6780 * context, no need to scan the host
6781 */
6782 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6783 bool flag;
6784
6785 /* clear any previous UFS device information */
6786 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6787 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6788 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6789 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6790
3a4bf06d
YG		 6791 if (!hba->is_init_prefetch)
6792 ufshcd_init_icc_levels(hba);
6793
2a8fa600
SJ		 6794 /* Add required well known logical units to scsi mid layer */
6795 if (ufshcd_scsi_add_wlus(hba))
6796 goto out;
6797
0701e49d 6798 /* Initialize devfreq after UFS device is detected */
6799 if (ufshcd_is_clkscaling_supported(hba)) {
6800 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6801 &hba->pwr_info,
6802 sizeof(struct ufs_pa_layer_attr));
6803 hba->clk_scaling.saved_pwr_info.is_valid = true;
6804 if (!hba->devfreq) {
deac444f
BA		 6805 ret = ufshcd_devfreq_init(hba);
6806 if (ret)
0701e49d 6807 goto out;
0701e49d 6808 }
6809 hba->clk_scaling.is_allowed = true;
6810 }
6811
df032bf2
AA		 6812 ufs_bsg_probe(hba);
6813
3441da7d
SRT		 6814 scsi_scan_host(hba->host);
6815 pm_runtime_put_sync(hba->dev);
6816 }
3a4bf06d
YG		 6817
6818 if (!hba->is_init_prefetch)
6819 hba->is_init_prefetch = true;
6820
5a0b0cb9 6821out:
1d337ec2
SRT		 6822 /*
6823 * If we failed to initialize the device or the device is not
6824 * present, turn off the power/clocks etc.
6825 */
57d104c1
SJ		 6826 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6827 pm_runtime_put_sync(hba->dev);
eebcc196 6828 ufshcd_exit_clk_scaling(hba);
1d337ec2 6829 ufshcd_hba_exit(hba);
57d104c1 6830 }
1d337ec2 6831
7ff5ab47 6832 trace_ufshcd_init(dev_name(hba->dev), ret,
6833 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6834 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6835 return ret;
6836}
6837
6838/**
6839 * ufshcd_async_scan - asynchronous execution for probing hba
6840 * @data: data pointer to pass to this function
6841 * @cookie: cookie data
6842 */
6843static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6844{
6845 struct ufs_hba *hba = (struct ufs_hba *)data;
6846
6847 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6848}
6849
f550c65b
YG		 6850static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6851{
6852 unsigned long flags;
6853 struct Scsi_Host *host;
6854 struct ufs_hba *hba;
6855 int index;
6856 bool found = false;
6857
6858 if (!scmd || !scmd->device || !scmd->device->host)
6600593c 6859 return BLK_EH_DONE;
f550c65b
YG		 6860
6861 host = scmd->device->host;
6862 hba = shost_priv(host);
6863 if (!hba)
6600593c 6864 return BLK_EH_DONE;
f550c65b
YG		 6865
6866 spin_lock_irqsave(host->host_lock, flags);
6867
6868 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6869 if (hba->lrb[index].cmd == scmd) {
6870 found = true;
6871 break;
6872 }
6873 }
6874
6875 spin_unlock_irqrestore(host->host_lock, flags);
6876
6877 /*
6878 * Bypass SCSI error handling and reset the block layer timer if this
6879 * SCSI command was not actually dispatched to UFS driver, otherwise
6880 * let SCSI layer handle the error as usual.
6881 */
6600593c 6882 return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
f550c65b
YG		 6883}
6884
d829fc8a
SN		 6885static const struct attribute_group *ufshcd_driver_groups[] = {
6886 &ufs_sysfs_unit_descriptor_group,
ec92b59c 6887 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 6888 NULL,
6889};
6890
7a3e97b0
SY		 6891static struct scsi_host_template ufshcd_driver_template = {
6892 .module = THIS_MODULE,
6893 .name = UFSHCD,
6894 .proc_name = UFSHCD,
6895 .queuecommand = ufshcd_queuecommand,
6896 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6897 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6898 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6899 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6900 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6901 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6902 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6903 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6904 .this_id = -1,
6905 .sg_tablesize = SG_ALL,
6906 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6907 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6908 .max_host_blocked = 1,
c40ecc12 6909 .track_queue_depth = 1,
d829fc8a 6910 .sdev_groups = ufshcd_driver_groups,
7a3e97b0
SY		 6911};
6912
57d104c1
SJ		 6913static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6914 int ua)
6915{
7b16a07c 6916 int ret;
57d104c1 6917
7b16a07c
BA		 6918 if (!vreg)
6919 return 0;
57d104c1 6920
7b16a07c
BA		 6921 ret = regulator_set_load(vreg->reg, ua);
6922 if (ret < 0) {
6923 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6924 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6925 }
6926
6927 return ret;
6928}
6929
6930static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6931 struct ufs_vreg *vreg)
6932{
60f01870
YG		 6933 if (!vreg)
6934 return 0;
6935 else if (vreg->unused)
6936 return 0;
6937 else
6938 return ufshcd_config_vreg_load(hba->dev, vreg,
6939 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6940}
6941
6942static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6943 struct ufs_vreg *vreg)
6944{
60f01870
YG		 6945 if (!vreg)
6946 return 0;
6947 else if (vreg->unused)
6948 return 0;
6949 else
6950 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6951}
6952
aa497613
SRT		 6953static int ufshcd_config_vreg(struct device *dev,
6954 struct ufs_vreg *vreg, bool on)
6955{
6956 int ret = 0;
72753590
GS		 6957 struct regulator *reg;
6958 const char *name;
aa497613
SRT		 6959 int min_uV, uA_load;
6960
6961 BUG_ON(!vreg);
6962
72753590
GS		 6963 reg = vreg->reg;
6964 name = vreg->name;
6965
aa497613
SRT		 6966 if (regulator_count_voltages(reg) > 0) {
6967 min_uV = on ? vreg->min_uV : 0;
6968 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6969 if (ret) {
6970 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6971 __func__, name, ret);
6972 goto out;
6973 }
6974
6975 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6976 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6977 if (ret)
aa497613 6978 goto out;
aa497613
SRT		 6979 }
6980out:
6981 return ret;
6982}
6983
6984static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6985{
6986 int ret = 0;
6987
60f01870
YG		 6988 if (!vreg)
6989 goto out;
6990 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6991 goto out;
6992
6993 ret = ufshcd_config_vreg(dev, vreg, true);
6994 if (!ret)
6995 ret = regulator_enable(vreg->reg);
6996
6997 if (!ret)
6998 vreg->enabled = true;
6999 else
7000 dev_err(dev, "%s: %s enable failed, err=%d\n",
7001 __func__, vreg->name, ret);
7002out:
7003 return ret;
7004}
7005
7006static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7007{
7008 int ret = 0;
7009
60f01870
YG		 7010 if (!vreg)
7011 goto out;
7012 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 7013 goto out;
7014
7015 ret = regulator_disable(vreg->reg);
7016
7017 if (!ret) {
7018 /* ignore errors on applying disable config */
7019 ufshcd_config_vreg(dev, vreg, false);
7020 vreg->enabled = false;
7021 } else {
7022 dev_err(dev, "%s: %s disable failed, err=%d\n",
7023 __func__, vreg->name, ret);
7024 }
7025out:
7026 return ret;
7027}
7028
7029static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7030{
7031 int ret = 0;
7032 struct device *dev = hba->dev;
7033 struct ufs_vreg_info *info = &hba->vreg_info;
7034
7035 if (!info)
7036 goto out;
7037
7038 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7039 if (ret)
7040 goto out;
7041
7042 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7043 if (ret)
7044 goto out;
7045
7046 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7047 if (ret)
7048 goto out;
7049
7050out:
7051 if (ret) {
7052 ufshcd_toggle_vreg(dev, info->vccq2, false);
7053 ufshcd_toggle_vreg(dev, info->vccq, false);
7054 ufshcd_toggle_vreg(dev, info->vcc, false);
7055 }
7056 return ret;
7057}
7058
6a771a65
RS		 7059static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7060{
7061 struct ufs_vreg_info *info = &hba->vreg_info;
7062
7063 if (info)
7064 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
7065
7066 return 0;
7067}
7068
aa497613
SRT		 7069static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7070{
7071 int ret = 0;
7072
7073 if (!vreg)
7074 goto out;
7075
7076 vreg->reg = devm_regulator_get(dev, vreg->name);
7077 if (IS_ERR(vreg->reg)) {
7078 ret = PTR_ERR(vreg->reg);
7079 dev_err(dev, "%s: %s get failed, err=%d\n",
7080 __func__, vreg->name, ret);
7081 }
7082out:
7083 return ret;
7084}
7085
7086static int ufshcd_init_vreg(struct ufs_hba *hba)
7087{
7088 int ret = 0;
7089 struct device *dev = hba->dev;
7090 struct ufs_vreg_info *info = &hba->vreg_info;
7091
7092 if (!info)
7093 goto out;
7094
7095 ret = ufshcd_get_vreg(dev, info->vcc);
7096 if (ret)
7097 goto out;
7098
7099 ret = ufshcd_get_vreg(dev, info->vccq);
7100 if (ret)
7101 goto out;
7102
7103 ret = ufshcd_get_vreg(dev, info->vccq2);
7104out:
7105 return ret;
7106}
7107
6a771a65
RS		 7108static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7109{
7110 struct ufs_vreg_info *info = &hba->vreg_info;
7111
7112 if (info)
7113 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7114
7115 return 0;
7116}
7117
60f01870
YG		 7118static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
7119{
7120 int ret = 0;
7121 struct ufs_vreg_info *info = &hba->vreg_info;
7122
7123 if (!info)
7124 goto out;
7125 else if (!info->vccq)
7126 goto out;
7127
7128 if (unused) {
7129 /* shut off the rail here */
7130 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
7131 /*
7132 * Mark this rail as no longer used, so it doesn't get enabled
7133 * later by mistake
7134 */
7135 if (!ret)
7136 info->vccq->unused = true;
7137 } else {
7138 /*
7139 * rail should have been already enabled hence just make sure
7140 * that unused flag is cleared.
7141 */
7142 info->vccq->unused = false;
7143 }
7144out:
7145 return ret;
7146}
7147
57d104c1
SJ		 7148static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7149 bool skip_ref_clk)
c6e79dac
SRT		 7150{
7151 int ret = 0;
7152 struct ufs_clk_info *clki;
7153 struct list_head *head = &hba->clk_list_head;
1ab27c9c 7154 unsigned long flags;
911a0771 7155 ktime_t start = ktime_get();
7156 bool clk_state_changed = false;
c6e79dac 7157
566ec9ad 7158 if (list_empty(head))
c6e79dac
SRT		 7159 goto out;
7160
b334456e
SJ		 7161 /*
7162 * vendor specific setup_clocks ops may depend on clocks managed by
7163 * this standard driver hence call the vendor specific setup_clocks
7164 * before disabling the clocks managed here.
7165 */
7166 if (!on) {
7167 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7168 if (ret)
7169 return ret;
7170 }
1e879e8f 7171
c6e79dac
SRT		 7172 list_for_each_entry(clki, head, list) {
7173 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7174 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7175 continue;
7176
911a0771 7177 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7178 if (on && !clki->enabled) {
7179 ret = clk_prepare_enable(clki->clk);
7180 if (ret) {
7181 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7182 __func__, clki->name, ret);
7183 goto out;
7184 }
7185 } else if (!on && clki->enabled) {
7186 clk_disable_unprepare(clki->clk);
7187 }
7188 clki->enabled = on;
7189 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7190 clki->name, on ? "en" : "dis");
7191 }
7192 }
1ab27c9c 7193
b334456e
SJ		 7194 /*
7195 * vendor specific setup_clocks ops may depend on clocks managed by
7196 * this standard driver hence call the vendor specific setup_clocks
7197 * after enabling the clocks managed here.
7198 */
7199 if (on) {
7200 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7201 if (ret)
7202 return ret;
7203 }
1e879e8f 7204
c6e79dac
SRT		 7205out:
7206 if (ret) {
7207 list_for_each_entry(clki, head, list) {
7208 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7209 clk_disable_unprepare(clki->clk);
7210 }
7ff5ab47 7211 } else if (!ret && on) {
1ab27c9c
ST		 7212 spin_lock_irqsave(hba->host->host_lock, flags);
7213 hba->clk_gating.state = CLKS_ON;
7ff5ab47 7214 trace_ufshcd_clk_gating(dev_name(hba->dev),
7215 hba->clk_gating.state);
1ab27c9c 7216 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7217 }
7ff5ab47 7218
911a0771 7219 if (clk_state_changed)
7220 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7221 (on ? "on" : "off"),
7222 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7223 return ret;
7224}
7225
57d104c1
SJ		 7226static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7227{
7228 return __ufshcd_setup_clocks(hba, on, false);
7229}
7230
c6e79dac
SRT		 7231static int ufshcd_init_clocks(struct ufs_hba *hba)
7232{
7233 int ret = 0;
7234 struct ufs_clk_info *clki;
7235 struct device *dev = hba->dev;
7236 struct list_head *head = &hba->clk_list_head;
7237
566ec9ad 7238 if (list_empty(head))
c6e79dac
SRT		 7239 goto out;
7240
7241 list_for_each_entry(clki, head, list) {
7242 if (!clki->name)
7243 continue;
7244
7245 clki->clk = devm_clk_get(dev, clki->name);
7246 if (IS_ERR(clki->clk)) {
7247 ret = PTR_ERR(clki->clk);
7248 dev_err(dev, "%s: %s clk get failed, %d\n",
7249 __func__, clki->name, ret);
7250 goto out;
7251 }
7252
7253 if (clki->max_freq) {
7254 ret = clk_set_rate(clki->clk, clki->max_freq);
7255 if (ret) {
7256 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7257 __func__, clki->name,
7258 clki->max_freq, ret);
7259 goto out;
7260 }
856b3483 7261 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7262 }
7263 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7264 clki->name, clk_get_rate(clki->clk));
7265 }
7266out:
7267 return ret;
7268}
7269
5c0c28a8
SRT		 7270static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7271{
7272 int err = 0;
7273
7274 if (!hba->vops)
7275 goto out;
7276
0263bcd0
YG		 7277 err = ufshcd_vops_init(hba);
7278 if (err)
7279 goto out;
5c0c28a8 7280
0263bcd0
YG		 7281 err = ufshcd_vops_setup_regulators(hba, true);
7282 if (err)
7283 goto out_exit;
5c0c28a8
SRT		 7284
7285 goto out;
7286
5c0c28a8 7287out_exit:
0263bcd0 7288 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7289out:
7290 if (err)
7291 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7292 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7293 return err;
7294}
7295
7296static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7297{
7298 if (!hba->vops)
7299 return;
7300
0263bcd0 7301 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7302
0263bcd0 7303 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7304}
7305
aa497613
SRT		 7306static int ufshcd_hba_init(struct ufs_hba *hba)
7307{
7308 int err;
7309
6a771a65
RS		 7310 /*
7311 * Handle host controller power separately from the UFS device power
7312 * rails as it will help controlling the UFS host controller power
7313 * collapse easily which is different than UFS device power collapse.
7314 * Also, enable the host controller power before we go ahead with rest
7315 * of the initialization here.
7316 */
7317 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7318 if (err)
7319 goto out;
7320
6a771a65 7321 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7322 if (err)
7323 goto out;
7324
6a771a65
RS		 7325 err = ufshcd_init_clocks(hba);
7326 if (err)
7327 goto out_disable_hba_vreg;
7328
7329 err = ufshcd_setup_clocks(hba, true);
7330 if (err)
7331 goto out_disable_hba_vreg;
7332
c6e79dac
SRT		 7333 err = ufshcd_init_vreg(hba);
7334 if (err)
7335 goto out_disable_clks;
7336
7337 err = ufshcd_setup_vreg(hba, true);
7338 if (err)
7339 goto out_disable_clks;
7340
aa497613
SRT		 7341 err = ufshcd_variant_hba_init(hba);
7342 if (err)
7343 goto out_disable_vreg;
7344
1d337ec2 7345 hba->is_powered = true;
aa497613
SRT		 7346 goto out;
7347
7348out_disable_vreg:
7349 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7350out_disable_clks:
7351 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7352out_disable_hba_vreg:
7353 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7354out:
7355 return err;
7356}
7357
7358static void ufshcd_hba_exit(struct ufs_hba *hba)
7359{
1d337ec2
SRT		 7360 if (hba->is_powered) {
7361 ufshcd_variant_hba_exit(hba);
7362 ufshcd_setup_vreg(hba, false);
a508253d 7363 ufshcd_suspend_clkscaling(hba);
eebcc196 7364 if (ufshcd_is_clkscaling_supported(hba))
0701e49d 7365 if (hba->devfreq)
7366 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7367 ufshcd_setup_clocks(hba, false);
7368 ufshcd_setup_hba_vreg(hba, false);
7369 hba->is_powered = false;
7370 }
aa497613
SRT		 7371}
7372
57d104c1
SJ		 7373static int
7374ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7375{
7376 unsigned char cmd[6] = {REQUEST_SENSE,
7377 0,
7378 0,
7379 0,
dcea0bfb 7380 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 7381 0};
7382 char *buffer;
7383 int ret;
7384
dcea0bfb 7385 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7386 if (!buffer) {
7387 ret = -ENOMEM;
7388 goto out;
7389 }
7390
fcbfffe2
CH		 7391 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7392 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
7393 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7394 if (ret)
7395 pr_err("%s: failed with err %d\n", __func__, ret);
7396
7397 kfree(buffer);
7398out:
7399 return ret;
7400}
7401
7402/**
7403 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7404 * power mode
7405 * @hba: per adapter instance
7406 * @pwr_mode: device power mode to set
7407 *
7408 * Returns 0 if requested power mode is set successfully
7409 * Returns non-zero if failed to set the requested power mode
7410 */
7411static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7412 enum ufs_dev_pwr_mode pwr_mode)
7413{
7414 unsigned char cmd[6] = { START_STOP };
7415 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7416 struct scsi_device *sdp;
7417 unsigned long flags;
57d104c1
SJ		 7418 int ret;
7419
7c48bfd0
AM		 7420 spin_lock_irqsave(hba->host->host_lock, flags);
7421 sdp = hba->sdev_ufs_device;
7422 if (sdp) {
7423 ret = scsi_device_get(sdp);
7424 if (!ret && !scsi_device_online(sdp)) {
7425 ret = -ENODEV;
7426 scsi_device_put(sdp);
7427 }
7428 } else {
7429 ret = -ENODEV;
7430 }
7431 spin_unlock_irqrestore(hba->host->host_lock, flags);
7432
7433 if (ret)
7434 return ret;
57d104c1
SJ		 7435
7436 /*
7437 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7438 * handling, which would wait for host to be resumed. Since we know
7439 * we are functional while we are here, skip host resume in error
7440 * handling context.
7441 */
7442 hba->host->eh_noresume = 1;
7443 if (hba->wlun_dev_clr_ua) {
7444 ret = ufshcd_send_request_sense(hba, sdp);
7445 if (ret)
7446 goto out;
7447 /* Unit attention condition is cleared now */
7448 hba->wlun_dev_clr_ua = false;
7449 }
7450
7451 cmd[4] = pwr_mode << 4;
7452
7453 /*
7454 * Current function would be generally called from the power management
e8064021 7455 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7456 * already suspended childs.
7457 */
fcbfffe2
CH		 7458 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7459 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7460 if (ret) {
7461 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7462 "START_STOP failed for power mode: %d, result %x\n",
7463 pwr_mode, ret);
c65be1a6 7464 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7465 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7466 }
7467
7468 if (!ret)
7469 hba->curr_dev_pwr_mode = pwr_mode;
7470out:
7c48bfd0 7471 scsi_device_put(sdp);
57d104c1
SJ		 7472 hba->host->eh_noresume = 0;
7473 return ret;
7474}
7475
7476static int ufshcd_link_state_transition(struct ufs_hba *hba,
7477 enum uic_link_state req_link_state,
7478 int check_for_bkops)
7479{
7480 int ret = 0;
7481
7482 if (req_link_state == hba->uic_link_state)
7483 return 0;
7484
7485 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7486 ret = ufshcd_uic_hibern8_enter(hba);
7487 if (!ret)
7488 ufshcd_set_link_hibern8(hba);
7489 else
7490 goto out;
7491 }
7492 /*
7493 * If autobkops is enabled, link can't be turned off because
7494 * turning off the link would also turn off the device.
7495 */
7496 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7497 (!check_for_bkops || (check_for_bkops &&
7498 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7499 /*
7500 * Let's make sure that link is in low power mode, we are doing
7501 * this currently by putting the link in Hibern8. Otherway to
7502 * put the link in low power mode is to send the DME end point
7503 * to device and then send the DME reset command to local
7504 * unipro. But putting the link in hibern8 is much faster.
7505 */
7506 ret = ufshcd_uic_hibern8_enter(hba);
7507 if (ret)
7508 goto out;
57d104c1
SJ		 7509 /*
7510 * Change controller state to "reset state" which
7511 * should also put the link in off/reset state
7512 */
596585a2 7513 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7514 /*
7515 * TODO: Check if we need any delay to make sure that
7516 * controller is reset
7517 */
7518 ufshcd_set_link_off(hba);
7519 }
7520
7521out:
7522 return ret;
7523}
7524
7525static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7526{
b799fdf7
YG		 7527 /*
7528 * It seems some UFS devices may keep drawing more than sleep current
7529 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7530 * To avoid this situation, add 2ms delay before putting these UFS
7531 * rails in LPM mode.
7532 */
7533 if (!ufshcd_is_link_active(hba) &&
7534 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7535 usleep_range(2000, 2100);
7536
57d104c1
SJ		 7537 /*
7538 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7539 * power.
7540 *
7541 * If UFS device and link is in OFF state, all power supplies (VCC,
7542 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7543 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7544 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7545 *
7546 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7547 * in low power state which would save some power.
7548 */
7549 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7550 !hba->dev_info.is_lu_power_on_wp) {
7551 ufshcd_setup_vreg(hba, false);
7552 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7553 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7554 if (!ufshcd_is_link_active(hba)) {
7555 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7556 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7557 }
7558 }
7559}
7560
7561static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7562{
7563 int ret = 0;
7564
7565 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7566 !hba->dev_info.is_lu_power_on_wp) {
7567 ret = ufshcd_setup_vreg(hba, true);
7568 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7569 if (!ret && !ufshcd_is_link_active(hba)) {
7570 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7571 if (ret)
7572 goto vcc_disable;
7573 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7574 if (ret)
7575 goto vccq_lpm;
7576 }
69d72ac8 7577 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7578 }
7579 goto out;
7580
7581vccq_lpm:
7582 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7583vcc_disable:
7584 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7585out:
7586 return ret;
7587}
7588
7589static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7590{
7591 if (ufshcd_is_link_off(hba))
7592 ufshcd_setup_hba_vreg(hba, false);
7593}
7594
7595static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7596{
7597 if (ufshcd_is_link_off(hba))
7598 ufshcd_setup_hba_vreg(hba, true);
7599}
7600
7a3e97b0 7601/**
57d104c1 7602 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7603 * @hba: per adapter instance
57d104c1
SJ		 7604 * @pm_op: desired low power operation type
7605 *
7606 * This function will try to put the UFS device and link into low power
7607 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7608 * (System PM level).
7609 *
7610 * If this function is called during shutdown, it will make sure that
7611 * both UFS device and UFS link is powered off.
7a3e97b0 7612 *
57d104c1
SJ		 7613 * NOTE: UFS device & link must be active before we enter in this function.
7614 *
7615 * Returns 0 for success and non-zero for failure
7a3e97b0 7616 */
57d104c1 7617static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7618{
57d104c1
SJ		 7619 int ret = 0;
7620 enum ufs_pm_level pm_lvl;
7621 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7622 enum uic_link_state req_link_state;
7623
7624 hba->pm_op_in_progress = 1;
7625 if (!ufshcd_is_shutdown_pm(pm_op)) {
7626 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7627 hba->rpm_lvl : hba->spm_lvl;
7628 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7629 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7630 } else {
7631 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7632 req_link_state = UIC_LINK_OFF_STATE;
7633 }
7634
7a3e97b0 7635 /*
57d104c1
SJ		 7636 * If we can't transition into any of the low power modes
7637 * just gate the clocks.
7a3e97b0 7638 */
1ab27c9c
ST		 7639 ufshcd_hold(hba, false);
7640 hba->clk_gating.is_suspended = true;
7641
401f1e44 7642 if (hba->clk_scaling.is_allowed) {
7643 cancel_work_sync(&hba->clk_scaling.suspend_work);
7644 cancel_work_sync(&hba->clk_scaling.resume_work);
7645 ufshcd_suspend_clkscaling(hba);
7646 }
d6fcf81a 7647
57d104c1
SJ		 7648 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7649 req_link_state == UIC_LINK_ACTIVE_STATE) {
7650 goto disable_clks;
7651 }
7a3e97b0 7652
57d104c1
SJ		 7653 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7654 (req_link_state == hba->uic_link_state))
d6fcf81a 7655 goto enable_gating;
57d104c1
SJ		 7656
7657 /* UFS device & link must be active before we enter in this function */
7658 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7659 ret = -EINVAL;
d6fcf81a 7660 goto enable_gating;
57d104c1
SJ		 7661 }
7662
7663 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7664 if (ufshcd_can_autobkops_during_suspend(hba)) {
7665 /*
7666 * The device is idle with no requests in the queue,
7667 * allow background operations if bkops status shows
7668 * that performance might be impacted.
7669 */
7670 ret = ufshcd_urgent_bkops(hba);
7671 if (ret)
7672 goto enable_gating;
7673 } else {
7674 /* make sure that auto bkops is disabled */
7675 ufshcd_disable_auto_bkops(hba);
7676 }
57d104c1
SJ		 7677 }
7678
7679 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7680 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7681 !ufshcd_is_runtime_pm(pm_op))) {
7682 /* ensure that bkops is disabled */
7683 ufshcd_disable_auto_bkops(hba);
7684 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7685 if (ret)
1ab27c9c 7686 goto enable_gating;
57d104c1
SJ		 7687 }
7688
7689 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7690 if (ret)
7691 goto set_dev_active;
7692
7693 ufshcd_vreg_set_lpm(hba);
7694
7695disable_clks:
7696 /*
7697 * Call vendor specific suspend callback. As these callbacks may access
7698 * vendor specific host controller register space call them before the
7699 * host clocks are ON.
7700 */
0263bcd0
YG		 7701 ret = ufshcd_vops_suspend(hba, pm_op);
7702 if (ret)
7703 goto set_link_active;
57d104c1 7704
57d104c1
SJ		 7705 if (!ufshcd_is_link_active(hba))
7706 ufshcd_setup_clocks(hba, false);
7707 else
7708 /* If link is active, device ref_clk can't be switched off */
7709 __ufshcd_setup_clocks(hba, false, true);
7710
1ab27c9c 7711 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7712 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7713 /*
7714 * Disable the host irq as host controller as there won't be any
0263bcd0 7715 * host controller transaction expected till resume.
57d104c1
SJ		 7716 */
7717 ufshcd_disable_irq(hba);
7718 /* Put the host controller in low power mode if possible */
7719 ufshcd_hba_vreg_set_lpm(hba);
7720 goto out;
7721
57d104c1 7722set_link_active:
401f1e44 7723 if (hba->clk_scaling.is_allowed)
7724 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7725 ufshcd_vreg_set_hpm(hba);
7726 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7727 ufshcd_set_link_active(hba);
7728 else if (ufshcd_is_link_off(hba))
7729 ufshcd_host_reset_and_restore(hba);
7730set_dev_active:
7731 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7732 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7733enable_gating:
401f1e44 7734 if (hba->clk_scaling.is_allowed)
7735 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7736 hba->clk_gating.is_suspended = false;
7737 ufshcd_release(hba);
57d104c1
SJ		 7738out:
7739 hba->pm_op_in_progress = 0;
7740 return ret;
7a3e97b0
SY		 7741}
7742
7743/**
57d104c1 7744 * ufshcd_resume - helper function for resume operations
3b1d0580 7745 * @hba: per adapter instance
57d104c1 7746 * @pm_op: runtime PM or system PM
7a3e97b0 7747 *
57d104c1
SJ		 7748 * This function basically brings the UFS device, UniPro link and controller
7749 * to active state.
7750 *
7751 * Returns 0 for success and non-zero for failure
7a3e97b0 7752 */
57d104c1 7753static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7754{
57d104c1
SJ		 7755 int ret;
7756 enum uic_link_state old_link_state;
7757
7758 hba->pm_op_in_progress = 1;
7759 old_link_state = hba->uic_link_state;
7760
7761 ufshcd_hba_vreg_set_hpm(hba);
7762 /* Make sure clocks are enabled before accessing controller */
7763 ret = ufshcd_setup_clocks(hba, true);
7764 if (ret)
7765 goto out;
7766
57d104c1
SJ		 7767 /* enable the host irq as host controller would be active soon */
7768 ret = ufshcd_enable_irq(hba);
7769 if (ret)
7770 goto disable_irq_and_vops_clks;
7771
7772 ret = ufshcd_vreg_set_hpm(hba);
7773 if (ret)
7774 goto disable_irq_and_vops_clks;
7775
7a3e97b0 7776 /*
57d104c1
SJ		 7777 * Call vendor specific resume callback. As these callbacks may access
7778 * vendor specific host controller register space call them when the
7779 * host clocks are ON.
7a3e97b0 7780 */
0263bcd0
YG		 7781 ret = ufshcd_vops_resume(hba, pm_op);
7782 if (ret)
7783 goto disable_vreg;
57d104c1
SJ		 7784
7785 if (ufshcd_is_link_hibern8(hba)) {
7786 ret = ufshcd_uic_hibern8_exit(hba);
7787 if (!ret)
7788 ufshcd_set_link_active(hba);
7789 else
7790 goto vendor_suspend;
7791 } else if (ufshcd_is_link_off(hba)) {
7792 ret = ufshcd_host_reset_and_restore(hba);
7793 /*
7794 * ufshcd_host_reset_and_restore() should have already
7795 * set the link state as active
7796 */
7797 if (ret || !ufshcd_is_link_active(hba))
7798 goto vendor_suspend;
7799 }
7800
7801 if (!ufshcd_is_ufs_dev_active(hba)) {
7802 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7803 if (ret)
7804 goto set_old_link_state;
7805 }
7806
4e768e76 7807 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7808 ufshcd_enable_auto_bkops(hba);
7809 else
7810 /*
7811 * If BKOPs operations are urgently needed at this moment then
7812 * keep auto-bkops enabled or else disable it.
7813 */
7814 ufshcd_urgent_bkops(hba);
7815
1ab27c9c
ST		 7816 hba->clk_gating.is_suspended = false;
7817
fcb0c4b0
ST		 7818 if (hba->clk_scaling.is_allowed)
7819 ufshcd_resume_clkscaling(hba);
856b3483 7820
1ab27c9c
ST		 7821 /* Schedule clock gating in case of no access to UFS device yet */
7822 ufshcd_release(hba);
ad448378
AH		 7823
7824 /* Enable Auto-Hibernate if configured */
7825 ufshcd_auto_hibern8_enable(hba);
7826
57d104c1
SJ		 7827 goto out;
7828
7829set_old_link_state:
7830 ufshcd_link_state_transition(hba, old_link_state, 0);
7831vendor_suspend:
0263bcd0 7832 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7833disable_vreg:
7834 ufshcd_vreg_set_lpm(hba);
7835disable_irq_and_vops_clks:
7836 ufshcd_disable_irq(hba);
401f1e44 7837 if (hba->clk_scaling.is_allowed)
7838 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7839 ufshcd_setup_clocks(hba, false);
7840out:
7841 hba->pm_op_in_progress = 0;
7842 return ret;
7843}
7844
7845/**
7846 * ufshcd_system_suspend - system suspend routine
7847 * @hba: per adapter instance
57d104c1
SJ		 7848 *
7849 * Check the description of ufshcd_suspend() function for more details.
7850 *
7851 * Returns 0 for success and non-zero for failure
7852 */
7853int ufshcd_system_suspend(struct ufs_hba *hba)
7854{
7855 int ret = 0;
7ff5ab47 7856 ktime_t start = ktime_get();
57d104c1
SJ		 7857
7858 if (!hba || !hba->is_powered)
233b594b 7859 return 0;
57d104c1 7860
0b257734 7861 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7862 hba->curr_dev_pwr_mode) &&
7863 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7864 hba->uic_link_state))
7865 goto out;
57d104c1 7866
0b257734 7867 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7868 /*
7869 * UFS device and/or UFS link low power states during runtime
7870 * suspend seems to be different than what is expected during
7871 * system suspend. Hence runtime resume the devic & link and
7872 * let the system suspend low power states to take effect.
7873 * TODO: If resume takes longer time, we might have optimize
7874 * it in future by not resuming everything if possible.
7875 */
7876 ret = ufshcd_runtime_resume(hba);
7877 if (ret)
7878 goto out;
7879 }
7880
7881 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7882out:
7ff5ab47 7883 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7884 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7885 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7886 if (!ret)
7887 hba->is_sys_suspended = true;
57d104c1
SJ		 7888 return ret;
7889}
7890EXPORT_SYMBOL(ufshcd_system_suspend);
7891
7892/**
7893 * ufshcd_system_resume - system resume routine
7894 * @hba: per adapter instance
7895 *
7896 * Returns 0 for success and non-zero for failure
7897 */
7a3e97b0 7898
57d104c1
SJ		 7899int ufshcd_system_resume(struct ufs_hba *hba)
7900{
7ff5ab47 7901 int ret = 0;
7902 ktime_t start = ktime_get();
7903
e3ce73d6
YG		 7904 if (!hba)
7905 return -EINVAL;
7906
7907 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7908 /*
7909 * Let the runtime resume take care of resuming
7910 * if runtime suspended.
7911 */
7ff5ab47 7912 goto out;
7913 else
7914 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7915out:
7916 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7917 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7918 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7919 return ret;
7a3e97b0 7920}
57d104c1 7921EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7922
57d104c1
SJ		 7923/**
7924 * ufshcd_runtime_suspend - runtime suspend routine
7925 * @hba: per adapter instance
7926 *
7927 * Check the description of ufshcd_suspend() function for more details.
7928 *
7929 * Returns 0 for success and non-zero for failure
7930 */
66ec6d59
SRT		 7931int ufshcd_runtime_suspend(struct ufs_hba *hba)
7932{
7ff5ab47 7933 int ret = 0;
7934 ktime_t start = ktime_get();
7935
e3ce73d6
YG		 7936 if (!hba)
7937 return -EINVAL;
7938
7939 if (!hba->is_powered)
7ff5ab47 7940 goto out;
7941 else
7942 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7943out:
7944 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7945 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7946 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7947 return ret;
66ec6d59
SRT		 7948}
7949EXPORT_SYMBOL(ufshcd_runtime_suspend);
7950
57d104c1
SJ		 7951/**
7952 * ufshcd_runtime_resume - runtime resume routine
7953 * @hba: per adapter instance
7954 *
7955 * This function basically brings the UFS device, UniPro link and controller
7956 * to active state. Following operations are done in this function:
7957 *
7958 * 1. Turn on all the controller related clocks
7959 * 2. Bring the UniPro link out of Hibernate state
7960 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7961 * to active state.
7962 * 4. If auto-bkops is enabled on the device, disable it.
7963 *
7964 * So following would be the possible power state after this function return
7965 * successfully:
7966 * S1: UFS device in Active state with VCC rail ON
7967 * UniPro link in Active state
7968 * All the UFS/UniPro controller clocks are ON
7969 *
7970 * Returns 0 for success and non-zero for failure
7971 */
66ec6d59
SRT		 7972int ufshcd_runtime_resume(struct ufs_hba *hba)
7973{
7ff5ab47 7974 int ret = 0;
7975 ktime_t start = ktime_get();
7976
e3ce73d6
YG		 7977 if (!hba)
7978 return -EINVAL;
7979
7980 if (!hba->is_powered)
7ff5ab47 7981 goto out;
7982 else
7983 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7984out:
7985 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7986 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7987 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7988 return ret;
66ec6d59
SRT		 7989}
7990EXPORT_SYMBOL(ufshcd_runtime_resume);
7991
7992int ufshcd_runtime_idle(struct ufs_hba *hba)
7993{
7994 return 0;
7995}
7996EXPORT_SYMBOL(ufshcd_runtime_idle);
7997
57d104c1
SJ		 7998/**
7999 * ufshcd_shutdown - shutdown routine
8000 * @hba: per adapter instance
8001 *
8002 * This function would power off both UFS device and UFS link.
8003 *
8004 * Returns 0 always to allow force shutdown even in case of errors.
8005 */
8006int ufshcd_shutdown(struct ufs_hba *hba)
8007{
8008 int ret = 0;
8009
8010 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8011 goto out;
8012
8013 if (pm_runtime_suspended(hba->dev)) {
8014 ret = ufshcd_runtime_resume(hba);
8015 if (ret)
8016 goto out;
8017 }
8018
8019 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8020out:
8021 if (ret)
8022 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8023 /* allow force shutdown even in case of errors */
8024 return 0;
8025}
8026EXPORT_SYMBOL(ufshcd_shutdown);
8027
7a3e97b0 8028/**
3b1d0580 8029 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8030 * data structure memory
8aa29f19 8031 * @hba: per adapter instance
7a3e97b0 8032 */
3b1d0580 8033void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8034{
df032bf2 8035 ufs_bsg_remove(hba);
cbb6813e 8036 ufs_sysfs_remove_nodes(hba->dev);
cfdf9c91 8037 scsi_remove_host(hba->host);
7a3e97b0 8038 /* disable interrupts */
2fbd009b 8039 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8040 ufshcd_hba_stop(hba, true);
7a3e97b0 8041
eebcc196 8042 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8043 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8044 if (ufshcd_is_clkscaling_supported(hba))
8045 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8046 ufshcd_hba_exit(hba);
3b1d0580
VH		 8047}
8048EXPORT_SYMBOL_GPL(ufshcd_remove);
8049
47555a5c
YG		 8050/**
8051 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8052 * @hba: pointer to Host Bus Adapter (HBA)
8053 */
8054void ufshcd_dealloc_host(struct ufs_hba *hba)
8055{
8056 scsi_host_put(hba->host);
8057}
8058EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8059
ca3d7bf9
AM		 8060/**
8061 * ufshcd_set_dma_mask - Set dma mask based on the controller
8062 * addressing capability
8063 * @hba: per adapter instance
8064 *
8065 * Returns 0 for success, non-zero for failure
8066 */
8067static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8068{
8069 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8070 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8071 return 0;
8072 }
8073 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8074}
8075
7a3e97b0 8076/**
5c0c28a8 8077 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8078 * @dev: pointer to device handle
8079 * @hba_handle: driver private handle
7a3e97b0
SY		 8080 * Returns 0 on success, non-zero value on failure
8081 */
5c0c28a8 8082int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8083{
8084 struct Scsi_Host *host;
8085 struct ufs_hba *hba;
5c0c28a8 8086 int err = 0;
7a3e97b0 8087
3b1d0580
VH		 8088 if (!dev) {
8089 dev_err(dev,
8090 "Invalid memory reference for dev is NULL\n");
8091 err = -ENODEV;
7a3e97b0
SY		 8092 goto out_error;
8093 }
8094
7a3e97b0
SY		 8095 host = scsi_host_alloc(&ufshcd_driver_template,
8096 sizeof(struct ufs_hba));
8097 if (!host) {
3b1d0580 8098 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8099 err = -ENOMEM;
3b1d0580 8100 goto out_error;
7a3e97b0
SY		 8101 }
8102 hba = shost_priv(host);
7a3e97b0 8103 hba->host = host;
3b1d0580 8104 hba->dev = dev;
5c0c28a8
SRT		 8105 *hba_handle = hba;
8106
566ec9ad
SM		 8107 INIT_LIST_HEAD(&hba->clk_list_head);
8108
5c0c28a8
SRT		 8109out_error:
8110 return err;
8111}
8112EXPORT_SYMBOL(ufshcd_alloc_host);
8113
8114/**
8115 * ufshcd_init - Driver initialization routine
8116 * @hba: per-adapter instance
8117 * @mmio_base: base register address
8118 * @irq: Interrupt line of device
8119 * Returns 0 on success, non-zero value on failure
8120 */
8121int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8122{
8123 int err;
8124 struct Scsi_Host *host = hba->host;
8125 struct device *dev = hba->dev;
8126
8127 if (!mmio_base) {
8128 dev_err(hba->dev,
8129 "Invalid memory reference for mmio_base is NULL\n");
8130 err = -ENODEV;
8131 goto out_error;
8132 }
8133
3b1d0580
VH		 8134 hba->mmio_base = mmio_base;
8135 hba->irq = irq;
7a3e97b0 8136
a4b0e8a4
PM		 8137 /* Set descriptor lengths to specification defaults */
8138 ufshcd_def_desc_sizes(hba);
8139
aa497613 8140 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8141 if (err)
8142 goto out_error;
8143
7a3e97b0
SY		 8144 /* Read capabilities registers */
8145 ufshcd_hba_capabilities(hba);
8146
8147 /* Get UFS version supported by the controller */
8148 hba->ufs_version = ufshcd_get_ufs_version(hba);
8149
c01848c6
YG		 8150 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8151 (hba->ufs_version != UFSHCI_VERSION_11) &&
8152 (hba->ufs_version != UFSHCI_VERSION_20) &&
8153 (hba->ufs_version != UFSHCI_VERSION_21))
8154 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8155 hba->ufs_version);
8156
2fbd009b
SJ		 8157 /* Get Interrupt bit mask per version */
8158 hba->intr_mask = ufshcd_get_intr_mask(hba);
8159
ca3d7bf9
AM		 8160 err = ufshcd_set_dma_mask(hba);
8161 if (err) {
8162 dev_err(hba->dev, "set dma mask failed\n");
8163 goto out_disable;
8164 }
8165
7a3e97b0
SY		 8166 /* Allocate memory for host memory space */
8167 err = ufshcd_memory_alloc(hba);
8168 if (err) {
3b1d0580
VH		 8169 dev_err(hba->dev, "Memory allocation failed\n");
8170 goto out_disable;
7a3e97b0
SY		 8171 }
8172
8173 /* Configure LRB */
8174 ufshcd_host_memory_configure(hba);
8175
8176 host->can_queue = hba->nutrs;
8177 host->cmd_per_lun = hba->nutrs;
8178 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8179 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8180 host->max_channel = UFSHCD_MAX_CHANNEL;
8181 host->unique_id = host->host_no;
a851b2bd 8182 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8183
7eb584db
DR		 8184 hba->max_pwr_info.is_valid = false;
8185
7a3e97b0 8186 /* Initailize wait queue for task management */
e2933132
SRT		 8187 init_waitqueue_head(&hba->tm_wq);
8188 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 8189
8190 /* Initialize work queues */
e8e7f271 8191 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8192 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8193
6ccf44fe
SJ		 8194 /* Initialize UIC command mutex */
8195 mutex_init(&hba->uic_cmd_mutex);
8196
5a0b0cb9
SRT		 8197 /* Initialize mutex for device management commands */
8198 mutex_init(&hba->dev_cmd.lock);
8199
a3cd5ec5 8200 init_rwsem(&hba->clk_scaling_lock);
8201
5a0b0cb9
SRT		 8202 /* Initialize device management tag acquire wait queue */
8203 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8204
1ab27c9c 8205 ufshcd_init_clk_gating(hba);
199ef13c 8206
eebcc196
VG		 8207 ufshcd_init_clk_scaling(hba);
8208
199ef13c
YG		 8209 /*
8210 * In order to avoid any spurious interrupt immediately after
8211 * registering UFS controller interrupt handler, clear any pending UFS
8212 * interrupt status and disable all the UFS interrupts.
8213 */
8214 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8215 REG_INTERRUPT_STATUS);
8216 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8217 /*
8218 * Make sure that UFS interrupts are disabled and any pending interrupt
8219 * status is cleared before registering UFS interrupt handler.
8220 */
8221 mb();
8222
7a3e97b0 8223 /* IRQ registration */
2953f850 8224 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8225 if (err) {
3b1d0580 8226 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8227 goto exit_gating;
57d104c1
SJ		 8228 } else {
8229 hba->is_irq_enabled = true;
7a3e97b0
SY		 8230 }
8231
3b1d0580 8232 err = scsi_add_host(host, hba->dev);
7a3e97b0 8233 if (err) {
3b1d0580 8234 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8235 goto exit_gating;
7a3e97b0
SY		 8236 }
8237
6ccf44fe
SJ		 8238 /* Host controller enable */
8239 err = ufshcd_hba_enable(hba);
7a3e97b0 8240 if (err) {
6ccf44fe 8241 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8242 ufshcd_print_host_regs(hba);
6ba65588 8243 ufshcd_print_host_state(hba);
3b1d0580 8244 goto out_remove_scsi_host;
7a3e97b0 8245 }
6ccf44fe 8246
0c8f7586 8247 /*
8248 * Set the default power management level for runtime and system PM.
8249 * Default power saving mode is to keep UFS link in Hibern8 state
8250 * and UFS device in sleep state.
8251 */
8252 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8253 UFS_SLEEP_PWR_MODE,
8254 UIC_LINK_HIBERN8_STATE);
8255 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8256 UFS_SLEEP_PWR_MODE,
8257 UIC_LINK_HIBERN8_STATE);
8258
ad448378
AH		 8259 /* Set the default auto-hiberate idle timer value to 150 ms */
8260 if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
8261 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8262 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8263 }
8264
62694735
SRT		 8265 /* Hold auto suspend until async scan completes */
8266 pm_runtime_get_sync(dev);
38135535 8267 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8268 /*
7caf489b 8269 * We are assuming that device wasn't put in sleep/power-down
8270 * state exclusively during the boot stage before kernel.
8271 * This assumption helps avoid doing link startup twice during
8272 * ufshcd_probe_hba().
57d104c1 8273 */
7caf489b 8274 ufshcd_set_ufs_dev_active(hba);
57d104c1 8275
6ccf44fe 8276 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8277 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8278
7a3e97b0
SY		 8279 return 0;
8280
3b1d0580
VH		 8281out_remove_scsi_host:
8282 scsi_remove_host(hba->host);
1ab27c9c 8283exit_gating:
eebcc196 8284 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8285 ufshcd_exit_clk_gating(hba);
3b1d0580 8286out_disable:
57d104c1 8287 hba->is_irq_enabled = false;
aa497613 8288 ufshcd_hba_exit(hba);
3b1d0580
VH		 8289out_error:
8290 return err;
8291}
8292EXPORT_SYMBOL_GPL(ufshcd_init);
8293
3b1d0580
VH		 8294MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8295MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8296MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8297MODULE_LICENSE("GPL");
8298MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)