scsi: ufshcd: Fix race between clk scaling and ungate work
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT
35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY
38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
dcea0bfb
GB
48#define UFSHCD_REQ_SENSE_SIZE 18
49
2fbd009b
SJ
50#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
51 UTP_TASK_REQ_COMPL |\
52 UFSHCD_ERROR_MASK)
6ccf44fe
SJ
53/* UIC command timeout, unit: ms */
54#define UIC_CMD_TIMEOUT 500
2fbd009b 55
5a0b0cb9
SRT
56/* NOP OUT retries waiting for NOP IN response */
57#define NOP_OUT_RETRIES 10
58/* Timeout after 30 msecs if NOP OUT hangs without response */
59#define NOP_OUT_TIMEOUT 30 /* msecs */
60
68078d5c
DR
61/* Query request retries */
62#define QUERY_REQ_RETRIES 10
63/* Query request timeout */
64#define QUERY_REQ_TIMEOUT 30 /* msec */
e5ad406c
YG
65/*
66 * Query request timeout for fDeviceInit flag
67 * fDeviceInit query response time for some devices is too large that default
68 * QUERY_REQ_TIMEOUT may not be enough for such devices.
69 */
70#define QUERY_FDEVICEINIT_REQ_TIMEOUT 600 /* msec */
68078d5c 71
e2933132
SRT
72/* Task management command timeout */
73#define TM_CMD_TIMEOUT 100 /* msecs */
74
64238fbd
YG
75/* maximum number of retries for a general UIC command */
76#define UFS_UIC_COMMAND_RETRIES 3
77
1d337ec2
SRT
78/* maximum number of link-startup retries */
79#define DME_LINKSTARTUP_RETRIES 3
80
87d0b4a6
YG
81/* Maximum retries for Hibern8 enter */
82#define UIC_HIBERN8_ENTER_RETRIES 3
83
1d337ec2
SRT
84/* maximum number of reset retries before giving up */
85#define MAX_HOST_RESET_RETRIES 5
86
68078d5c
DR
87/* Expose the flag value from utp_upiu_query.value */
88#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
89
7d568652
SJ
90/* Interrupt aggregation default timeout, unit: 40us */
91#define INT_AGGR_DEF_TO 0x02
92
aa497613
SRT
93#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
94 ({ \
95 int _ret; \
96 if (_on) \
97 _ret = ufshcd_enable_vreg(_dev, _vreg); \
98 else \
99 _ret = ufshcd_disable_vreg(_dev, _vreg); \
100 _ret; \
101 })
102
da461cec
SJ
103static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 111 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ
112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114};
115
7a3e97b0
SY
116enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
7a3e97b0
SY
119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121};
122
123/* UFSHCD states */
124enum {
7a3e97b0
SY
125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
3441da7d
SRT
127 UFSHCD_STATE_OPERATIONAL,
128};
129
130/* UFSHCD error handling flags */
131enum {
132 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY
133};
134
e8e7f271
SRT
135/* UFSHCD UIC layer error flags */
136enum {
137 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG
138 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
139 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
140 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
141 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
142 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT
143};
144
7a3e97b0
SY
145/* Interrupt configuration options */
146enum {
147 UFSHCD_INT_DISABLE,
148 UFSHCD_INT_ENABLE,
149 UFSHCD_INT_CLEAR,
150};
151
3441da7d
SRT
152#define ufshcd_set_eh_in_progress(h) \
153 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
154#define ufshcd_eh_in_progress(h) \
155 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
156#define ufshcd_clear_eh_in_progress(h) \
157 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
158
57d104c1
SJ
159#define ufshcd_set_ufs_dev_active(h) \
160 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
161#define ufshcd_set_ufs_dev_sleep(h) \
162 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
163#define ufshcd_set_ufs_dev_poweroff(h) \
164 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
165#define ufshcd_is_ufs_dev_active(h) \
166 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
167#define ufshcd_is_ufs_dev_sleep(h) \
168 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
169#define ufshcd_is_ufs_dev_poweroff(h) \
170 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
171
172static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
173 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
175 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
177 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
179};
180
181static inline enum ufs_dev_pwr_mode
182ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
183{
184 return ufs_pm_lvl_states[lvl].dev_state;
185}
186
187static inline enum uic_link_state
188ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
189{
190 return ufs_pm_lvl_states[lvl].link_state;
191}
192
3441da7d
SRT
193static void ufshcd_tmc_handler(struct ufs_hba *hba);
194static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT
195static int ufshcd_reset_and_restore(struct ufs_hba *hba);
196static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT
197static void ufshcd_hba_exit(struct ufs_hba *hba);
198static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST
199static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
200 bool skip_ref_clk);
201static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 202static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST
203static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
204static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 205static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ
206static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
207static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR
208static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
209 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG
210static int ufshcd_change_power_mode(struct ufs_hba *hba,
211 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG
212static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
213{
214 return tag >= 0 && tag < hba->nutrs;
215}
57d104c1
SJ
216
217static inline int ufshcd_enable_irq(struct ufs_hba *hba)
218{
219 int ret = 0;
220
221 if (!hba->is_irq_enabled) {
222 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
223 hba);
224 if (ret)
225 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
226 __func__, ret);
227 hba->is_irq_enabled = true;
228 }
229
230 return ret;
231}
232
233static inline void ufshcd_disable_irq(struct ufs_hba *hba)
234{
235 if (hba->is_irq_enabled) {
236 free_irq(hba->irq, hba);
237 hba->is_irq_enabled = false;
238 }
239}
3441da7d 240
b573d484
YG
241/* replace non-printable or non-ASCII characters with spaces */
242static inline void ufshcd_remove_non_printable(char *val)
243{
244 if (!val)
245 return;
246
247 if (*val < 0x20 || *val > 0x7e)
248 *val = ' ';
249}
250
5a0b0cb9
SRT
251/*
252 * ufshcd_wait_for_register - wait for register value to change
253 * @hba - per-adapter interface
254 * @reg - mmio register offset
255 * @mask - mask to apply to read register value
256 * @val - wait condition
257 * @interval_us - polling interval in microsecs
258 * @timeout_ms - timeout in millisecs
596585a2 259 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT
260 *
261 * Returns -ETIMEDOUT on error, zero on success
262 */
596585a2
YG
263int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
264 u32 val, unsigned long interval_us,
265 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT
266{
267 int err = 0;
268 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
269
270 /* ignore bits that we don't intend to wait on */
271 val = val & mask;
272
273 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG
274 if (can_sleep)
275 usleep_range(interval_us, interval_us + 50);
276 else
277 udelay(interval_us);
5a0b0cb9
SRT
278 if (time_after(jiffies, timeout)) {
279 if ((ufshcd_readl(hba, reg) & mask) != val)
280 err = -ETIMEDOUT;
281 break;
282 }
283 }
284
285 return err;
286}
287
2fbd009b
SJ
288/**
289 * ufshcd_get_intr_mask - Get the interrupt bit mask
290 * @hba - Pointer to adapter instance
291 *
292 * Returns interrupt bit mask per version
293 */
294static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
295{
296 if (hba->ufs_version == UFSHCI_VERSION_10)
297 return INTERRUPT_MASK_ALL_VER_10;
298 else
299 return INTERRUPT_MASK_ALL_VER_11;
300}
301
7a3e97b0
SY
302/**
303 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
304 * @hba - Pointer to adapter instance
305 *
306 * Returns UFSHCI version supported by the controller
307 */
308static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
309{
0263bcd0
YG
310 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
311 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 312
b873a275 313 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY
314}
315
316/**
317 * ufshcd_is_device_present - Check if any device connected to
318 * the host controller
5c0c28a8 319 * @hba: pointer to adapter instance
7a3e97b0 320 *
73ec513a 321 * Returns 1 if device present, 0 if no device detected
7a3e97b0 322 */
5c0c28a8 323static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 324{
5c0c28a8
SRT
325 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
326 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY
327}
328
329/**
330 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
331 * @lrb: pointer to local command reference block
332 *
333 * This function is used to get the OCS field from UTRD
334 * Returns the OCS field in the UTRD
335 */
336static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
337{
e8c8e82a 338 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY
339}
340
341/**
342 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
343 * @task_req_descp: pointer to utp_task_req_desc structure
344 *
345 * This function is used to get the OCS field from UTMRD
346 * Returns the OCS field in the UTMRD
347 */
348static inline int
349ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
350{
e8c8e82a 351 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY
352}
353
354/**
355 * ufshcd_get_tm_free_slot - get a free slot for task management request
356 * @hba: per adapter instance
e2933132 357 * @free_slot: pointer to variable with available slot value
7a3e97b0 358 *
e2933132
SRT
359 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
360 * Returns 0 if free slot is not available, else return 1 with tag value
361 * in @free_slot.
7a3e97b0 362 */
e2933132 363static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 364{
e2933132
SRT
365 int tag;
366 bool ret = false;
367
368 if (!free_slot)
369 goto out;
370
371 do {
372 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
373 if (tag >= hba->nutmrs)
374 goto out;
375 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
376
377 *free_slot = tag;
378 ret = true;
379out:
380 return ret;
381}
382
383static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
384{
385 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY
386}
387
388/**
389 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
390 * @hba: per adapter instance
391 * @pos: position of the bit to be cleared
392 */
393static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
394{
b873a275 395 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY
396}
397
a48353f6
YG
398/**
399 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
400 * @hba: per adapter instance
401 * @tag: position of the bit to be cleared
402 */
403static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
404{
405 __clear_bit(tag, &hba->outstanding_reqs);
406}
407
7a3e97b0
SY
408/**
409 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
410 * @reg: Register value of host controller status
411 *
412 * Returns integer, 0 on Success and positive value if failed
413 */
414static inline int ufshcd_get_lists_status(u32 reg)
415{
416 /*
417 * The mask 0xFF is for the following HCS register bits
418 * Bit Description
419 * 0 Device Present
420 * 1 UTRLRDY
421 * 2 UTMRLRDY
422 * 3 UCRDY
897efe62 423 * 4-7 reserved
7a3e97b0 424 */
897efe62 425 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY
426}
427
428/**
429 * ufshcd_get_uic_cmd_result - Get the UIC command result
430 * @hba: Pointer to adapter instance
431 *
432 * This function gets the result of UIC command completion
433 * Returns 0 on success, non zero value on error
434 */
435static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
436{
b873a275 437 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY
438 MASK_UIC_COMMAND_RESULT;
439}
440
12b4fdb4
SJ
441/**
442 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
443 * @hba: Pointer to adapter instance
444 *
445 * This function gets UIC command argument3
446 * Returns 0 on success, non zero value on error
447 */
448static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
449{
450 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
451}
452
7a3e97b0 453/**
5a0b0cb9 454 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 455 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY
456 */
457static inline int
5a0b0cb9 458ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 459{
5a0b0cb9 460 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY
461}
462
463/**
464 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
465 * @ucd_rsp_ptr: pointer to response UPIU
466 *
467 * This function gets the response status and scsi_status from response UPIU
468 * Returns the response result code.
469 */
470static inline int
471ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
472{
473 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
474}
475
1c2623c5
SJ
476/*
477 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
478 * from response UPIU
479 * @ucd_rsp_ptr: pointer to response UPIU
480 *
481 * Return the data segment length.
482 */
483static inline unsigned int
484ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
485{
486 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
487 MASK_RSP_UPIU_DATA_SEG_LEN;
488}
489
66ec6d59
SRT
490/**
491 * ufshcd_is_exception_event - Check if the device raised an exception event
492 * @ucd_rsp_ptr: pointer to response UPIU
493 *
494 * The function checks if the device raised an exception event indicated in
495 * the Device Information field of response UPIU.
496 *
497 * Returns true if exception is raised, false otherwise.
498 */
499static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
500{
501 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
502 MASK_RSP_EXCEPTION_EVENT ? true : false;
503}
504
7a3e97b0 505/**
7d568652 506 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 507 * @hba: per adapter instance
7a3e97b0
SY
508 */
509static inline void
7d568652 510ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 511{
7d568652
SJ
512 ufshcd_writel(hba, INT_AGGR_ENABLE |
513 INT_AGGR_COUNTER_AND_TIMER_RESET,
514 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
515}
516
517/**
518 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
519 * @hba: per adapter instance
520 * @cnt: Interrupt aggregation counter threshold
521 * @tmout: Interrupt aggregation timeout value
522 */
523static inline void
524ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
525{
526 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
527 INT_AGGR_COUNTER_THLD_VAL(cnt) |
528 INT_AGGR_TIMEOUT_VAL(tmout),
529 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY
530}
531
b852190e
YG
532/**
533 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
534 * @hba: per adapter instance
535 */
536static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
537{
538 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
539}
540
7a3e97b0
SY
541/**
542 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
543 * When run-stop registers are set to 1, it indicates the
544 * host controller that it can process the requests
545 * @hba: per adapter instance
546 */
547static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
548{
b873a275
SJ
549 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
550 REG_UTP_TASK_REQ_LIST_RUN_STOP);
551 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
552 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY
553}
554
7a3e97b0
SY
555/**
556 * ufshcd_hba_start - Start controller initialization sequence
557 * @hba: per adapter instance
558 */
559static inline void ufshcd_hba_start(struct ufs_hba *hba)
560{
b873a275 561 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY
562}
563
564/**
565 * ufshcd_is_hba_active - Get controller state
566 * @hba: per adapter instance
567 *
568 * Returns zero if controller is active, 1 otherwise
569 */
570static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
571{
b873a275 572 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY
573}
574
37113106
YG
575u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
576{
577 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
578 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
579 (hba->ufs_version == UFSHCI_VERSION_11))
580 return UFS_UNIPRO_VER_1_41;
581 else
582 return UFS_UNIPRO_VER_1_6;
583}
584EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
585
586static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
587{
588 /*
589 * If both host and device support UniPro ver1.6 or later, PA layer
590 * parameters tuning happens during link startup itself.
591 *
592 * We can manually tune PA layer parameters if either host or device
593 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
594 * logic simple, we will only do manual tuning if local unipro version
595 * doesn't support ver1.6 or later.
596 */
597 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
598 return true;
599 else
600 return false;
601}
602
a508253d
GB
603static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
604{
605 if (ufshcd_is_clkscaling_enabled(hba)) {
606 devfreq_suspend_device(hba->devfreq);
607 hba->clk_scaling.window_start_t = 0;
608 }
609}
610
611static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
612{
613 if (ufshcd_is_clkscaling_enabled(hba))
614 devfreq_resume_device(hba->devfreq);
615}
616
1ab27c9c
ST
617static void ufshcd_ungate_work(struct work_struct *work)
618{
619 int ret;
620 unsigned long flags;
621 struct ufs_hba *hba = container_of(work, struct ufs_hba,
622 clk_gating.ungate_work);
623
624 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
625
626 spin_lock_irqsave(hba->host->host_lock, flags);
627 if (hba->clk_gating.state == CLKS_ON) {
628 spin_unlock_irqrestore(hba->host->host_lock, flags);
629 goto unblock_reqs;
630 }
631
632 spin_unlock_irqrestore(hba->host->host_lock, flags);
633 ufshcd_setup_clocks(hba, true);
634
635 /* Exit from hibern8 */
636 if (ufshcd_can_hibern8_during_gating(hba)) {
637 /* Prevent gating in this path */
638 hba->clk_gating.is_suspended = true;
639 if (ufshcd_is_link_hibern8(hba)) {
640 ret = ufshcd_uic_hibern8_exit(hba);
641 if (ret)
642 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
643 __func__, ret);
644 else
645 ufshcd_set_link_active(hba);
646 }
647 hba->clk_gating.is_suspended = false;
648 }
649unblock_reqs:
a508253d 650 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST
651 scsi_unblock_requests(hba->host);
652}
653
654/**
655 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
656 * Also, exit from hibern8 mode and set the link as active.
657 * @hba: per adapter instance
658 * @async: This indicates whether caller should ungate clocks asynchronously.
659 */
660int ufshcd_hold(struct ufs_hba *hba, bool async)
661{
662 int rc = 0;
663 unsigned long flags;
664
665 if (!ufshcd_is_clkgating_allowed(hba))
666 goto out;
1ab27c9c
ST
667 spin_lock_irqsave(hba->host->host_lock, flags);
668 hba->clk_gating.active_reqs++;
669
53c12d0e
YG
670 if (ufshcd_eh_in_progress(hba)) {
671 spin_unlock_irqrestore(hba->host->host_lock, flags);
672 return 0;
673 }
674
856b3483 675start:
1ab27c9c
ST
676 switch (hba->clk_gating.state) {
677 case CLKS_ON:
f2a785ac
VG
678 /*
679 * Wait for the ungate work to complete if in progress.
680 * Though the clocks may be in ON state, the link could
681 * still be in hibner8 state if hibern8 is allowed
682 * during clock gating.
683 * Make sure we exit hibern8 state also in addition to
684 * clocks being ON.
685 */
686 if (ufshcd_can_hibern8_during_gating(hba) &&
687 ufshcd_is_link_hibern8(hba)) {
688 spin_unlock_irqrestore(hba->host->host_lock, flags);
689 flush_work(&hba->clk_gating.ungate_work);
690 spin_lock_irqsave(hba->host->host_lock, flags);
691 goto start;
692 }
1ab27c9c
ST
693 break;
694 case REQ_CLKS_OFF:
695 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
696 hba->clk_gating.state = CLKS_ON;
697 break;
698 }
699 /*
700 * If we here, it means gating work is either done or
701 * currently running. Hence, fall through to cancel gating
702 * work and to enable clocks.
703 */
704 case CLKS_OFF:
705 scsi_block_requests(hba->host);
706 hba->clk_gating.state = REQ_CLKS_ON;
707 schedule_work(&hba->clk_gating.ungate_work);
708 /*
709 * fall through to check if we should wait for this
710 * work to be done or not.
711 */
712 case REQ_CLKS_ON:
713 if (async) {
714 rc = -EAGAIN;
715 hba->clk_gating.active_reqs--;
716 break;
717 }
718
719 spin_unlock_irqrestore(hba->host->host_lock, flags);
720 flush_work(&hba->clk_gating.ungate_work);
721 /* Make sure state is CLKS_ON before returning */
856b3483 722 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST
723 goto start;
724 default:
725 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
726 __func__, hba->clk_gating.state);
727 break;
728 }
729 spin_unlock_irqrestore(hba->host->host_lock, flags);
730out:
731 return rc;
732}
6e3fd44d 733EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST
734
735static void ufshcd_gate_work(struct work_struct *work)
736{
737 struct ufs_hba *hba = container_of(work, struct ufs_hba,
738 clk_gating.gate_work.work);
739 unsigned long flags;
740
741 spin_lock_irqsave(hba->host->host_lock, flags);
742 if (hba->clk_gating.is_suspended) {
743 hba->clk_gating.state = CLKS_ON;
744 goto rel_lock;
745 }
746
747 if (hba->clk_gating.active_reqs
748 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
749 || hba->lrb_in_use || hba->outstanding_tasks
750 || hba->active_uic_cmd || hba->uic_async_done)
751 goto rel_lock;
752
753 spin_unlock_irqrestore(hba->host->host_lock, flags);
754
755 /* put the link into hibern8 mode before turning off clocks */
756 if (ufshcd_can_hibern8_during_gating(hba)) {
757 if (ufshcd_uic_hibern8_enter(hba)) {
758 hba->clk_gating.state = CLKS_ON;
759 goto out;
760 }
761 ufshcd_set_link_hibern8(hba);
762 }
763
a508253d 764 ufshcd_suspend_clkscaling(hba);
856b3483 765
1ab27c9c
ST
766 if (!ufshcd_is_link_active(hba))
767 ufshcd_setup_clocks(hba, false);
768 else
769 /* If link is active, device ref_clk can't be switched off */
770 __ufshcd_setup_clocks(hba, false, true);
771
772 /*
773 * In case you are here to cancel this work the gating state
774 * would be marked as REQ_CLKS_ON. In this case keep the state
775 * as REQ_CLKS_ON which would anyway imply that clocks are off
776 * and a request to turn them on is pending. By doing this way,
777 * we keep the state machine in tact and this would ultimately
778 * prevent from doing cancel work multiple times when there are
779 * new requests arriving before the current cancel work is done.
780 */
781 spin_lock_irqsave(hba->host->host_lock, flags);
782 if (hba->clk_gating.state == REQ_CLKS_OFF)
783 hba->clk_gating.state = CLKS_OFF;
784
785rel_lock:
786 spin_unlock_irqrestore(hba->host->host_lock, flags);
787out:
788 return;
789}
790
791/* host lock must be held before calling this variant */
792static void __ufshcd_release(struct ufs_hba *hba)
793{
794 if (!ufshcd_is_clkgating_allowed(hba))
795 return;
796
797 hba->clk_gating.active_reqs--;
798
799 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
800 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
801 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG
802 || hba->active_uic_cmd || hba->uic_async_done
803 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST
804 return;
805
806 hba->clk_gating.state = REQ_CLKS_OFF;
807 schedule_delayed_work(&hba->clk_gating.gate_work,
808 msecs_to_jiffies(hba->clk_gating.delay_ms));
809}
810
811void ufshcd_release(struct ufs_hba *hba)
812{
813 unsigned long flags;
814
815 spin_lock_irqsave(hba->host->host_lock, flags);
816 __ufshcd_release(hba);
817 spin_unlock_irqrestore(hba->host->host_lock, flags);
818}
6e3fd44d 819EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST
820
821static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
822 struct device_attribute *attr, char *buf)
823{
824 struct ufs_hba *hba = dev_get_drvdata(dev);
825
826 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
827}
828
829static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
830 struct device_attribute *attr, const char *buf, size_t count)
831{
832 struct ufs_hba *hba = dev_get_drvdata(dev);
833 unsigned long flags, value;
834
835 if (kstrtoul(buf, 0, &value))
836 return -EINVAL;
837
838 spin_lock_irqsave(hba->host->host_lock, flags);
839 hba->clk_gating.delay_ms = value;
840 spin_unlock_irqrestore(hba->host->host_lock, flags);
841 return count;
842}
843
844static void ufshcd_init_clk_gating(struct ufs_hba *hba)
845{
846 if (!ufshcd_is_clkgating_allowed(hba))
847 return;
848
849 hba->clk_gating.delay_ms = 150;
850 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
851 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
852
853 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
854 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
855 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
856 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
857 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
858 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
859 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
860}
861
862static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
863{
864 if (!ufshcd_is_clkgating_allowed(hba))
865 return;
866 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM
867 cancel_work_sync(&hba->clk_gating.ungate_work);
868 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST
869}
870
856b3483
ST
871/* Must be called with host lock acquired */
872static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
873{
874 if (!ufshcd_is_clkscaling_enabled(hba))
875 return;
876
877 if (!hba->clk_scaling.is_busy_started) {
878 hba->clk_scaling.busy_start_t = ktime_get();
879 hba->clk_scaling.is_busy_started = true;
880 }
881}
882
883static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
884{
885 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
886
887 if (!ufshcd_is_clkscaling_enabled(hba))
888 return;
889
890 if (!hba->outstanding_reqs && scaling->is_busy_started) {
891 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
892 scaling->busy_start_t));
893 scaling->busy_start_t = ktime_set(0, 0);
894 scaling->is_busy_started = false;
895 }
896}
7a3e97b0
SY
897/**
898 * ufshcd_send_command - Send SCSI or device management commands
899 * @hba: per adapter instance
900 * @task_tag: Task tag of the command
901 */
902static inline
903void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
904{
856b3483 905 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 906 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 907 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB
908 /* Make sure that doorbell is committed immediately */
909 wmb();
7a3e97b0
SY
910}
911
912/**
913 * ufshcd_copy_sense_data - Copy sense data in case of check condition
914 * @lrb - pointer to local reference block
915 */
916static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
917{
918 int len;
1c2623c5
SJ
919 if (lrbp->sense_buffer &&
920 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG
921 int len_to_copy;
922
5a0b0cb9 923 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG
924 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
925
7a3e97b0 926 memcpy(lrbp->sense_buffer,
5a0b0cb9 927 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 928 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY
929 }
930}
931
68078d5c
DR
932/**
933 * ufshcd_copy_query_response() - Copy the Query Response and the data
934 * descriptor
935 * @hba: per adapter instance
936 * @lrb - pointer to local reference block
937 */
938static
c6d4a831 939int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR
940{
941 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
942
68078d5c 943 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 944
68078d5c
DR
945 /* Get the descriptor */
946 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 947 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 948 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR
949 u16 resp_len;
950 u16 buf_len;
68078d5c
DR
951
952 /* data segment length */
c6d4a831 953 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 954 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT
955 buf_len = be16_to_cpu(
956 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR
957 if (likely(buf_len >= resp_len)) {
958 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
959 } else {
960 dev_warn(hba->dev,
961 "%s: Response size is bigger than buffer",
962 __func__);
963 return -EINVAL;
964 }
68078d5c 965 }
c6d4a831
DR
966
967 return 0;
68078d5c
DR
968}
969
7a3e97b0
SY
970/**
971 * ufshcd_hba_capabilities - Read controller capabilities
972 * @hba: per adapter instance
973 */
974static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
975{
b873a275 976 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY
977
978 /* nutrs and nutmrs are 0 based values */
979 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
980 hba->nutmrs =
981 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
982}
983
984/**
6ccf44fe
SJ
985 * ufshcd_ready_for_uic_cmd - Check if controller is ready
986 * to accept UIC commands
7a3e97b0 987 * @hba: per adapter instance
6ccf44fe
SJ
988 * Return true on success, else false
989 */
990static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
991{
992 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
993 return true;
994 else
995 return false;
996}
997
53b3d9c3
SJ
998/**
999 * ufshcd_get_upmcrs - Get the power mode change request status
1000 * @hba: Pointer to adapter instance
1001 *
1002 * This function gets the UPMCRS field of HCS register
1003 * Returns value of UPMCRS field
1004 */
1005static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1006{
1007 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1008}
1009
6ccf44fe
SJ
1010/**
1011 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1012 * @hba: per adapter instance
1013 * @uic_cmd: UIC command
1014 *
1015 * Mutex must be held.
7a3e97b0
SY
1016 */
1017static inline void
6ccf44fe 1018ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1019{
6ccf44fe
SJ
1020 WARN_ON(hba->active_uic_cmd);
1021
1022 hba->active_uic_cmd = uic_cmd;
1023
7a3e97b0 1024 /* Write Args */
6ccf44fe
SJ
1025 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1026 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1027 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY
1028
1029 /* Write UIC Cmd */
6ccf44fe 1030 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1031 REG_UIC_COMMAND);
7a3e97b0
SY
1032}
1033
6ccf44fe
SJ
1034/**
1035 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1036 * @hba: per adapter instance
1037 * @uic_command: UIC command
1038 *
1039 * Must be called with mutex held.
1040 * Returns 0 only if success.
1041 */
1042static int
1043ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1044{
1045 int ret;
1046 unsigned long flags;
1047
1048 if (wait_for_completion_timeout(&uic_cmd->done,
1049 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1050 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1051 else
1052 ret = -ETIMEDOUT;
1053
1054 spin_lock_irqsave(hba->host->host_lock, flags);
1055 hba->active_uic_cmd = NULL;
1056 spin_unlock_irqrestore(hba->host->host_lock, flags);
1057
1058 return ret;
1059}
1060
1061/**
1062 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1063 * @hba: per adapter instance
1064 * @uic_cmd: UIC command
d75f7fe4 1065 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ
1066 *
1067 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1068 * with mutex held and host_lock locked.
6ccf44fe
SJ
1069 * Returns 0 only if success.
1070 */
1071static int
d75f7fe4
YG
1072__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1073 bool completion)
6ccf44fe 1074{
6ccf44fe
SJ
1075 if (!ufshcd_ready_for_uic_cmd(hba)) {
1076 dev_err(hba->dev,
1077 "Controller not ready to accept UIC commands\n");
1078 return -EIO;
1079 }
1080
d75f7fe4
YG
1081 if (completion)
1082 init_completion(&uic_cmd->done);
6ccf44fe 1083
6ccf44fe 1084 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1085
57d104c1 1086 return 0;
6ccf44fe
SJ
1087}
1088
1089/**
1090 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1091 * @hba: per adapter instance
1092 * @uic_cmd: UIC command
1093 *
1094 * Returns 0 only if success.
1095 */
1096static int
1097ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1098{
1099 int ret;
57d104c1 1100 unsigned long flags;
6ccf44fe 1101
1ab27c9c 1102 ufshcd_hold(hba, false);
6ccf44fe 1103 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG
1104 ufshcd_add_delay_before_dme_cmd(hba);
1105
57d104c1 1106 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1107 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ
1108 spin_unlock_irqrestore(hba->host->host_lock, flags);
1109 if (!ret)
1110 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1111
6ccf44fe
SJ
1112 mutex_unlock(&hba->uic_cmd_mutex);
1113
1ab27c9c 1114 ufshcd_release(hba);
6ccf44fe
SJ
1115 return ret;
1116}
1117
7a3e97b0
SY
1118/**
1119 * ufshcd_map_sg - Map scatter-gather list to prdt
1120 * @lrbp - pointer to local reference block
1121 *
1122 * Returns 0 in case of success, non-zero value in case of failure
1123 */
1124static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
1125{
1126 struct ufshcd_sg_entry *prd_table;
1127 struct scatterlist *sg;
1128 struct scsi_cmnd *cmd;
1129 int sg_segments;
1130 int i;
1131
1132 cmd = lrbp->cmd;
1133 sg_segments = scsi_dma_map(cmd);
1134 if (sg_segments < 0)
1135 return sg_segments;
1136
1137 if (sg_segments) {
1138 lrbp->utr_descriptor_ptr->prd_table_length =
1139 cpu_to_le16((u16) (sg_segments));
1140
1141 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1142
1143 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1144 prd_table[i].size =
1145 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1146 prd_table[i].base_addr =
1147 cpu_to_le32(lower_32_bits(sg->dma_address));
1148 prd_table[i].upper_addr =
1149 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1150 prd_table[i].reserved = 0;
7a3e97b0
SY
1151 }
1152 } else {
1153 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1154 }
1155
1156 return 0;
1157}
1158
1159/**
2fbd009b 1160 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1161 * @hba: per adapter instance
2fbd009b 1162 * @intrs: interrupt bits
7a3e97b0 1163 */
2fbd009b 1164static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1165{
2fbd009b
SJ
1166 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1167
1168 if (hba->ufs_version == UFSHCI_VERSION_10) {
1169 u32 rw;
1170 rw = set & INTERRUPT_MASK_RW_VER_10;
1171 set = rw | ((set ^ intrs) & intrs);
1172 } else {
1173 set |= intrs;
1174 }
1175
1176 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1177}
1178
1179/**
1180 * ufshcd_disable_intr - disable interrupts
1181 * @hba: per adapter instance
1182 * @intrs: interrupt bits
1183 */
1184static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1185{
1186 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1187
1188 if (hba->ufs_version == UFSHCI_VERSION_10) {
1189 u32 rw;
1190 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1191 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1192 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1193
1194 } else {
1195 set &= ~intrs;
7a3e97b0 1196 }
2fbd009b
SJ
1197
1198 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY
1199}
1200
5a0b0cb9
SRT
1201/**
1202 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1203 * descriptor according to request
1204 * @lrbp: pointer to local reference block
1205 * @upiu_flags: flags required in the header
1206 * @cmd_dir: requests data direction
1207 */
1208static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1209 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT
1210{
1211 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1212 u32 data_direction;
1213 u32 dword_0;
1214
1215 if (cmd_dir == DMA_FROM_DEVICE) {
1216 data_direction = UTP_DEVICE_TO_HOST;
1217 *upiu_flags = UPIU_CMD_FLAGS_READ;
1218 } else if (cmd_dir == DMA_TO_DEVICE) {
1219 data_direction = UTP_HOST_TO_DEVICE;
1220 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1221 } else {
1222 data_direction = UTP_NO_DATA_TRANSFER;
1223 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1224 }
1225
1226 dword_0 = data_direction | (lrbp->command_type
1227 << UPIU_COMMAND_TYPE_OFFSET);
1228 if (lrbp->intr_cmd)
1229 dword_0 |= UTP_REQ_DESC_INT_CMD;
1230
1231 /* Transfer request descriptor header fields */
1232 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG
1233 /* dword_1 is reserved, hence it is set to 0 */
1234 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT
1235 /*
1236 * assigning invalid value for command status. Controller
1237 * updates OCS on command completion, with the command
1238 * status
1239 */
1240 req_desc->header.dword_2 =
1241 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG
1242 /* dword_3 is reserved, hence it is set to 0 */
1243 req_desc->header.dword_3 = 0;
51047266
YG
1244
1245 req_desc->prd_table_length = 0;
5a0b0cb9
SRT
1246}
1247
1248/**
1249 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1250 * for scsi commands
1251 * @lrbp - local reference block pointer
1252 * @upiu_flags - flags
1253 */
1254static
1255void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1256{
1257 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1258 unsigned short cdb_len;
5a0b0cb9
SRT
1259
1260 /* command descriptor fields */
1261 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1262 UPIU_TRANSACTION_COMMAND, upiu_flags,
1263 lrbp->lun, lrbp->task_tag);
1264 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1265 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1266
1267 /* Total EHS length and Data segment length will be zero */
1268 ucd_req_ptr->header.dword_2 = 0;
1269
1270 ucd_req_ptr->sc.exp_data_transfer_len =
1271 cpu_to_be32(lrbp->cmd->sdb.length);
1272
52ac95fe
YG
1273 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1274 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1275 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1276
1277 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT
1278}
1279
68078d5c
DR
1280/**
1281 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1282 * for query requsts
1283 * @hba: UFS hba
1284 * @lrbp: local reference block pointer
1285 * @upiu_flags: flags
1286 */
1287static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1288 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1289{
1290 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1291 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1292 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR
1293 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1294
1295 /* Query request header */
1296 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1297 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1298 lrbp->lun, lrbp->task_tag);
1299 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1300 0, query->request.query_func, 0, 0);
1301
6861285c
ZL
1302 /* Data segment length only need for WRITE_DESC */
1303 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1304 ucd_req_ptr->header.dword_2 =
1305 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
1306 else
1307 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR
1308
1309 /* Copy the Query Request buffer as is */
1310 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1311 QUERY_OSF_SIZE);
68078d5c
DR
1312
1313 /* Copy the Descriptor */
c6d4a831
DR
1314 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1315 memcpy(descp, query->descriptor, len);
1316
51047266 1317 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR
1318}
1319
5a0b0cb9
SRT
1320static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1321{
1322 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1323
1324 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1325
1326 /* command descriptor fields */
1327 ucd_req_ptr->header.dword_0 =
1328 UPIU_HEADER_DWORD(
1329 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG
1330 /* clear rest of the fields of basic header */
1331 ucd_req_ptr->header.dword_1 = 0;
1332 ucd_req_ptr->header.dword_2 = 0;
1333
1334 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT
1335}
1336
7a3e97b0 1337/**
300bb13f
JP
1338 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1339 * for Device Management Purposes
5a0b0cb9 1340 * @hba - per adapter instance
7a3e97b0
SY
1341 * @lrb - pointer to local reference block
1342 */
300bb13f 1343static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1344{
7a3e97b0 1345 u32 upiu_flags;
5a0b0cb9 1346 int ret = 0;
7a3e97b0 1347
300bb13f
JP
1348 if (hba->ufs_version == UFSHCI_VERSION_20)
1349 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1350 else
1351 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1352
1353 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1354 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1355 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1356 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1357 ufshcd_prepare_utp_nop_upiu(lrbp);
1358 else
1359 ret = -EINVAL;
1360
1361 return ret;
1362}
1363
1364/**
1365 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1366 * for SCSI Purposes
1367 * @hba - per adapter instance
1368 * @lrb - pointer to local reference block
1369 */
1370static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1371{
1372 u32 upiu_flags;
1373 int ret = 0;
1374
1375 if (hba->ufs_version == UFSHCI_VERSION_20)
1376 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1377 else
1378 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1379
1380 if (likely(lrbp->cmd)) {
1381 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1382 lrbp->cmd->sc_data_direction);
1383 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1384 } else {
1385 ret = -EINVAL;
1386 }
5a0b0cb9
SRT
1387
1388 return ret;
7a3e97b0
SY
1389}
1390
0ce147d4
SJ
1391/*
1392 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1393 * @scsi_lun: scsi LUN id
1394 *
1395 * Returns UPIU LUN id
1396 */
1397static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1398{
1399 if (scsi_is_wlun(scsi_lun))
1400 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1401 | UFS_UPIU_WLUN_ID;
1402 else
1403 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1404}
1405
2a8fa600
SJ
1406/**
1407 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1408 * @scsi_lun: UPIU W-LUN id
1409 *
1410 * Returns SCSI W-LUN id
1411 */
1412static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1413{
1414 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1415}
1416
7a3e97b0
SY
1417/**
1418 * ufshcd_queuecommand - main entry point for SCSI requests
1419 * @cmd: command from SCSI Midlayer
1420 * @done: call back function
1421 *
1422 * Returns 0 for success, non-zero in case of failure
1423 */
1424static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1425{
1426 struct ufshcd_lrb *lrbp;
1427 struct ufs_hba *hba;
1428 unsigned long flags;
1429 int tag;
1430 int err = 0;
1431
1432 hba = shost_priv(host);
1433
1434 tag = cmd->request->tag;
14497328
YG
1435 if (!ufshcd_valid_tag(hba, tag)) {
1436 dev_err(hba->dev,
1437 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1438 __func__, tag, cmd, cmd->request);
1439 BUG();
1440 }
7a3e97b0 1441
3441da7d
SRT
1442 spin_lock_irqsave(hba->host->host_lock, flags);
1443 switch (hba->ufshcd_state) {
1444 case UFSHCD_STATE_OPERATIONAL:
1445 break;
1446 case UFSHCD_STATE_RESET:
7a3e97b0 1447 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT
1448 goto out_unlock;
1449 case UFSHCD_STATE_ERROR:
1450 set_host_byte(cmd, DID_ERROR);
1451 cmd->scsi_done(cmd);
1452 goto out_unlock;
1453 default:
1454 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1455 __func__, hba->ufshcd_state);
1456 set_host_byte(cmd, DID_BAD_TARGET);
1457 cmd->scsi_done(cmd);
1458 goto out_unlock;
7a3e97b0 1459 }
53c12d0e
YG
1460
1461 /* if error handling is in progress, don't issue commands */
1462 if (ufshcd_eh_in_progress(hba)) {
1463 set_host_byte(cmd, DID_ERROR);
1464 cmd->scsi_done(cmd);
1465 goto out_unlock;
1466 }
3441da7d 1467 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1468
5a0b0cb9
SRT
1469 /* acquire the tag to make sure device cmds don't use it */
1470 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1471 /*
1472 * Dev manage command in progress, requeue the command.
1473 * Requeuing the command helps in cases where the request *may*
1474 * find different tag instead of waiting for dev manage command
1475 * completion.
1476 */
1477 err = SCSI_MLQUEUE_HOST_BUSY;
1478 goto out;
1479 }
1480
1ab27c9c
ST
1481 err = ufshcd_hold(hba, true);
1482 if (err) {
1483 err = SCSI_MLQUEUE_HOST_BUSY;
1484 clear_bit_unlock(tag, &hba->lrb_in_use);
1485 goto out;
1486 }
1487 WARN_ON(hba->clk_gating.state != CLKS_ON);
1488
7a3e97b0
SY
1489 lrbp = &hba->lrb[tag];
1490
5a0b0cb9 1491 WARN_ON(lrbp->cmd);
7a3e97b0 1492 lrbp->cmd = cmd;
dcea0bfb 1493 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY
1494 lrbp->sense_buffer = cmd->sense_buffer;
1495 lrbp->task_tag = tag;
0ce147d4 1496 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1497 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1498
300bb13f
JP
1499 ufshcd_comp_scsi_upiu(hba, lrbp);
1500
7a3e97b0 1501 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT
1502 if (err) {
1503 lrbp->cmd = NULL;
1504 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1505 goto out;
5a0b0cb9 1506 }
ad1a1b9c
GB
1507 /* Make sure descriptors are ready before ringing the doorbell */
1508 wmb();
7a3e97b0
SY
1509
1510 /* issue command to the controller */
1511 spin_lock_irqsave(hba->host->host_lock, flags);
1512 ufshcd_send_command(hba, tag);
3441da7d 1513out_unlock:
7a3e97b0
SY
1514 spin_unlock_irqrestore(hba->host->host_lock, flags);
1515out:
1516 return err;
1517}
1518
5a0b0cb9
SRT
1519static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1520 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1521{
1522 lrbp->cmd = NULL;
1523 lrbp->sense_bufflen = 0;
1524 lrbp->sense_buffer = NULL;
1525 lrbp->task_tag = tag;
1526 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT
1527 lrbp->intr_cmd = true; /* No interrupt aggregation */
1528 hba->dev_cmd.type = cmd_type;
1529
300bb13f 1530 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT
1531}
1532
1533static int
1534ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1535{
1536 int err = 0;
1537 unsigned long flags;
1538 u32 mask = 1 << tag;
1539
1540 /* clear outstanding transaction before retry */
1541 spin_lock_irqsave(hba->host->host_lock, flags);
1542 ufshcd_utrl_clear(hba, tag);
1543 spin_unlock_irqrestore(hba->host->host_lock, flags);
1544
1545 /*
1546 * wait for for h/w to clear corresponding bit in door-bell.
1547 * max. wait is 1 sec.
1548 */
1549 err = ufshcd_wait_for_register(hba,
1550 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1551 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT
1552
1553 return err;
1554}
1555
c6d4a831
DR
1556static int
1557ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1558{
1559 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1560
1561 /* Get the UPIU response */
1562 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1563 UPIU_RSP_CODE_OFFSET;
1564 return query_res->response;
1565}
1566
5a0b0cb9
SRT
1567/**
1568 * ufshcd_dev_cmd_completion() - handles device management command responses
1569 * @hba: per adapter instance
1570 * @lrbp: pointer to local reference block
1571 */
1572static int
1573ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1574{
1575 int resp;
1576 int err = 0;
1577
1578 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1579
1580 switch (resp) {
1581 case UPIU_TRANSACTION_NOP_IN:
1582 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1583 err = -EINVAL;
1584 dev_err(hba->dev, "%s: unexpected response %x\n",
1585 __func__, resp);
1586 }
1587 break;
68078d5c 1588 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR
1589 err = ufshcd_check_query_response(hba, lrbp);
1590 if (!err)
1591 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1592 break;
5a0b0cb9
SRT
1593 case UPIU_TRANSACTION_REJECT_UPIU:
1594 /* TODO: handle Reject UPIU Response */
1595 err = -EPERM;
1596 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1597 __func__);
1598 break;
1599 default:
1600 err = -EINVAL;
1601 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1602 __func__, resp);
1603 break;
1604 }
1605
1606 return err;
1607}
1608
1609static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1610 struct ufshcd_lrb *lrbp, int max_timeout)
1611{
1612 int err = 0;
1613 unsigned long time_left;
1614 unsigned long flags;
1615
1616 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1617 msecs_to_jiffies(max_timeout));
1618
ad1a1b9c
GB
1619 /* Make sure descriptors are ready before ringing the doorbell */
1620 wmb();
5a0b0cb9
SRT
1621 spin_lock_irqsave(hba->host->host_lock, flags);
1622 hba->dev_cmd.complete = NULL;
1623 if (likely(time_left)) {
1624 err = ufshcd_get_tr_ocs(lrbp);
1625 if (!err)
1626 err = ufshcd_dev_cmd_completion(hba, lrbp);
1627 }
1628 spin_unlock_irqrestore(hba->host->host_lock, flags);
1629
1630 if (!time_left) {
1631 err = -ETIMEDOUT;
a48353f6
YG
1632 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1633 __func__, lrbp->task_tag);
5a0b0cb9 1634 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1635 /* successfully cleared the command, retry if needed */
5a0b0cb9 1636 err = -EAGAIN;
a48353f6
YG
1637 /*
1638 * in case of an error, after clearing the doorbell,
1639 * we also need to clear the outstanding_request
1640 * field in hba
1641 */
1642 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT
1643 }
1644
1645 return err;
1646}
1647
1648/**
1649 * ufshcd_get_dev_cmd_tag - Get device management command tag
1650 * @hba: per-adapter instance
1651 * @tag: pointer to variable with available slot value
1652 *
1653 * Get a free slot and lock it until device management command
1654 * completes.
1655 *
1656 * Returns false if free slot is unavailable for locking, else
1657 * return true with tag value in @tag.
1658 */
1659static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1660{
1661 int tag;
1662 bool ret = false;
1663 unsigned long tmp;
1664
1665 if (!tag_out)
1666 goto out;
1667
1668 do {
1669 tmp = ~hba->lrb_in_use;
1670 tag = find_last_bit(&tmp, hba->nutrs);
1671 if (tag >= hba->nutrs)
1672 goto out;
1673 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1674
1675 *tag_out = tag;
1676 ret = true;
1677out:
1678 return ret;
1679}
1680
1681static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1682{
1683 clear_bit_unlock(tag, &hba->lrb_in_use);
1684}
1685
1686/**
1687 * ufshcd_exec_dev_cmd - API for sending device management requests
1688 * @hba - UFS hba
1689 * @cmd_type - specifies the type (NOP, Query...)
1690 * @timeout - time in seconds
1691 *
68078d5c
DR
1692 * NOTE: Since there is only one available tag for device management commands,
1693 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT
1694 */
1695static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1696 enum dev_cmd_type cmd_type, int timeout)
1697{
1698 struct ufshcd_lrb *lrbp;
1699 int err;
1700 int tag;
1701 struct completion wait;
1702 unsigned long flags;
1703
1704 /*
1705 * Get free slot, sleep if slots are unavailable.
1706 * Even though we use wait_event() which sleeps indefinitely,
1707 * the maximum wait time is bounded by SCSI request timeout.
1708 */
1709 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1710
1711 init_completion(&wait);
1712 lrbp = &hba->lrb[tag];
1713 WARN_ON(lrbp->cmd);
1714 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1715 if (unlikely(err))
1716 goto out_put_tag;
1717
1718 hba->dev_cmd.complete = &wait;
1719
e3dfdc53
YG
1720 /* Make sure descriptors are ready before ringing the doorbell */
1721 wmb();
5a0b0cb9
SRT
1722 spin_lock_irqsave(hba->host->host_lock, flags);
1723 ufshcd_send_command(hba, tag);
1724 spin_unlock_irqrestore(hba->host->host_lock, flags);
1725
1726 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1727
1728out_put_tag:
1729 ufshcd_put_dev_cmd_tag(hba, tag);
1730 wake_up(&hba->dev_cmd.tag_wq);
1731 return err;
1732}
1733
d44a5f98
DR
1734/**
1735 * ufshcd_init_query() - init the query response and request parameters
1736 * @hba: per-adapter instance
1737 * @request: address of the request pointer to be initialized
1738 * @response: address of the response pointer to be initialized
1739 * @opcode: operation to perform
1740 * @idn: flag idn to access
1741 * @index: LU number to access
1742 * @selector: query/flag/descriptor further identification
1743 */
1744static inline void ufshcd_init_query(struct ufs_hba *hba,
1745 struct ufs_query_req **request, struct ufs_query_res **response,
1746 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1747{
1748 *request = &hba->dev_cmd.query.request;
1749 *response = &hba->dev_cmd.query.response;
1750 memset(*request, 0, sizeof(struct ufs_query_req));
1751 memset(*response, 0, sizeof(struct ufs_query_res));
1752 (*request)->upiu_req.opcode = opcode;
1753 (*request)->upiu_req.idn = idn;
1754 (*request)->upiu_req.index = index;
1755 (*request)->upiu_req.selector = selector;
1756}
1757
dc3c8d3a
YG
1758static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1759 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
1760{
1761 int ret;
1762 int retries;
1763
1764 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1765 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1766 if (ret)
1767 dev_dbg(hba->dev,
1768 "%s: failed with error %d, retries %d\n",
1769 __func__, ret, retries);
1770 else
1771 break;
1772 }
1773
1774 if (ret)
1775 dev_err(hba->dev,
1776 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1777 __func__, opcode, idn, ret, retries);
1778 return ret;
1779}
1780
68078d5c
DR
1781/**
1782 * ufshcd_query_flag() - API function for sending flag query requests
1783 * hba: per-adapter instance
1784 * query_opcode: flag query to perform
1785 * idn: flag idn to access
1786 * flag_res: the flag value after the query request completes
1787 *
1788 * Returns 0 for success, non-zero in case of failure
1789 */
dc3c8d3a 1790int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR
1791 enum flag_idn idn, bool *flag_res)
1792{
d44a5f98
DR
1793 struct ufs_query_req *request = NULL;
1794 struct ufs_query_res *response = NULL;
1795 int err, index = 0, selector = 0;
e5ad406c 1796 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR
1797
1798 BUG_ON(!hba);
1799
1ab27c9c 1800 ufshcd_hold(hba, false);
68078d5c 1801 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR
1802 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1803 selector);
68078d5c
DR
1804
1805 switch (opcode) {
1806 case UPIU_QUERY_OPCODE_SET_FLAG:
1807 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1808 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1809 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1810 break;
1811 case UPIU_QUERY_OPCODE_READ_FLAG:
1812 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1813 if (!flag_res) {
1814 /* No dummy reads */
1815 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1816 __func__);
1817 err = -EINVAL;
1818 goto out_unlock;
1819 }
1820 break;
1821 default:
1822 dev_err(hba->dev,
1823 "%s: Expected query flag opcode but got = %d\n",
1824 __func__, opcode);
1825 err = -EINVAL;
1826 goto out_unlock;
1827 }
68078d5c 1828
e5ad406c
YG
1829 if (idn == QUERY_FLAG_IDN_FDEVICEINIT)
1830 timeout = QUERY_FDEVICEINIT_REQ_TIMEOUT;
1831
1832 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR
1833
1834 if (err) {
1835 dev_err(hba->dev,
1836 "%s: Sending flag query for idn %d failed, err = %d\n",
1837 __func__, idn, err);
1838 goto out_unlock;
1839 }
1840
1841 if (flag_res)
e8c8e82a 1842 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR
1843 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1844
1845out_unlock:
1846 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1847 ufshcd_release(hba);
68078d5c
DR
1848 return err;
1849}
1850
66ec6d59
SRT
1851/**
1852 * ufshcd_query_attr - API function for sending attribute requests
1853 * hba: per-adapter instance
1854 * opcode: attribute opcode
1855 * idn: attribute idn to access
1856 * index: index field
1857 * selector: selector field
1858 * attr_val: the attribute value after the query request completes
1859 *
1860 * Returns 0 for success, non-zero in case of failure
1861*/
bdbe5d2f 1862static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT
1863 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1864{
d44a5f98
DR
1865 struct ufs_query_req *request = NULL;
1866 struct ufs_query_res *response = NULL;
66ec6d59
SRT
1867 int err;
1868
1869 BUG_ON(!hba);
1870
1ab27c9c 1871 ufshcd_hold(hba, false);
66ec6d59
SRT
1872 if (!attr_val) {
1873 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1874 __func__, opcode);
1875 err = -EINVAL;
1876 goto out;
1877 }
1878
1879 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR
1880 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1881 selector);
66ec6d59
SRT
1882
1883 switch (opcode) {
1884 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1885 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1886 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT
1887 break;
1888 case UPIU_QUERY_OPCODE_READ_ATTR:
1889 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1890 break;
1891 default:
1892 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1893 __func__, opcode);
1894 err = -EINVAL;
1895 goto out_unlock;
1896 }
1897
d44a5f98 1898 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT
1899
1900 if (err) {
1901 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1902 __func__, opcode, idn, err);
1903 goto out_unlock;
1904 }
1905
e8c8e82a 1906 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT
1907
1908out_unlock:
1909 mutex_unlock(&hba->dev_cmd.lock);
1910out:
1ab27c9c 1911 ufshcd_release(hba);
66ec6d59
SRT
1912 return err;
1913}
1914
5e86ae44
YG
1915/**
1916 * ufshcd_query_attr_retry() - API function for sending query
1917 * attribute with retries
1918 * @hba: per-adapter instance
1919 * @opcode: attribute opcode
1920 * @idn: attribute idn to access
1921 * @index: index field
1922 * @selector: selector field
1923 * @attr_val: the attribute value after the query request
1924 * completes
1925 *
1926 * Returns 0 for success, non-zero in case of failure
1927*/
1928static int ufshcd_query_attr_retry(struct ufs_hba *hba,
1929 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1930 u32 *attr_val)
1931{
1932 int ret = 0;
1933 u32 retries;
1934
1935 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1936 ret = ufshcd_query_attr(hba, opcode, idn, index,
1937 selector, attr_val);
1938 if (ret)
1939 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
1940 __func__, ret, retries);
1941 else
1942 break;
1943 }
1944
1945 if (ret)
1946 dev_err(hba->dev,
1947 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
1948 __func__, idn, ret, QUERY_REQ_RETRIES);
1949 return ret;
1950}
1951
a70e91b8 1952static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR
1953 enum query_opcode opcode, enum desc_idn idn, u8 index,
1954 u8 selector, u8 *desc_buf, int *buf_len)
1955{
1956 struct ufs_query_req *request = NULL;
1957 struct ufs_query_res *response = NULL;
1958 int err;
1959
1960 BUG_ON(!hba);
1961
1ab27c9c 1962 ufshcd_hold(hba, false);
d44a5f98
DR
1963 if (!desc_buf) {
1964 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1965 __func__, opcode);
1966 err = -EINVAL;
1967 goto out;
1968 }
1969
1970 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1971 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1972 __func__, *buf_len);
1973 err = -EINVAL;
1974 goto out;
1975 }
1976
1977 mutex_lock(&hba->dev_cmd.lock);
1978 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1979 selector);
1980 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1981 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR
1982
1983 switch (opcode) {
1984 case UPIU_QUERY_OPCODE_WRITE_DESC:
1985 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1986 break;
1987 case UPIU_QUERY_OPCODE_READ_DESC:
1988 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1989 break;
1990 default:
1991 dev_err(hba->dev,
1992 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1993 __func__, opcode);
1994 err = -EINVAL;
1995 goto out_unlock;
1996 }
1997
1998 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1999
2000 if (err) {
2001 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
2002 __func__, opcode, idn, err);
2003 goto out_unlock;
2004 }
2005
2006 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2007 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR
2008
2009out_unlock:
2010 mutex_unlock(&hba->dev_cmd.lock);
2011out:
1ab27c9c 2012 ufshcd_release(hba);
d44a5f98
DR
2013 return err;
2014}
2015
a70e91b8
YG
2016/**
2017 * ufshcd_query_descriptor_retry - API function for sending descriptor
2018 * requests
2019 * hba: per-adapter instance
2020 * opcode: attribute opcode
2021 * idn: attribute idn to access
2022 * index: index field
2023 * selector: selector field
2024 * desc_buf: the buffer that contains the descriptor
2025 * buf_len: length parameter passed to the device
2026 *
2027 * Returns 0 for success, non-zero in case of failure.
2028 * The buf_len parameter will contain, on return, the length parameter
2029 * received on the response.
2030 */
2031int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2032 enum query_opcode opcode, enum desc_idn idn, u8 index,
2033 u8 selector, u8 *desc_buf, int *buf_len)
2034{
2035 int err;
2036 int retries;
2037
2038 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2039 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2040 selector, desc_buf, buf_len);
2041 if (!err || err == -EINVAL)
2042 break;
2043 }
2044
2045 return err;
2046}
2047EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2048
da461cec
SJ
2049/**
2050 * ufshcd_read_desc_param - read the specified descriptor parameter
2051 * @hba: Pointer to adapter instance
2052 * @desc_id: descriptor idn value
2053 * @desc_index: descriptor index
2054 * @param_offset: offset of the parameter to read
2055 * @param_read_buf: pointer to buffer where parameter would be read
2056 * @param_size: sizeof(param_read_buf)
2057 *
2058 * Return 0 in case of success, non-zero otherwise
2059 */
2060static int ufshcd_read_desc_param(struct ufs_hba *hba,
2061 enum desc_idn desc_id,
2062 int desc_index,
2063 u32 param_offset,
2064 u8 *param_read_buf,
2065 u32 param_size)
2066{
2067 int ret;
2068 u8 *desc_buf;
2069 u32 buff_len;
2070 bool is_kmalloc = true;
2071
2072 /* safety checks */
2073 if (desc_id >= QUERY_DESC_IDN_MAX)
2074 return -EINVAL;
2075
2076 buff_len = ufs_query_desc_max_size[desc_id];
2077 if ((param_offset + param_size) > buff_len)
2078 return -EINVAL;
2079
2080 if (!param_offset && (param_size == buff_len)) {
2081 /* memory space already available to hold full descriptor */
2082 desc_buf = param_read_buf;
2083 is_kmalloc = false;
2084 } else {
2085 /* allocate memory to hold full descriptor */
2086 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2087 if (!desc_buf)
2088 return -ENOMEM;
2089 }
2090
a70e91b8
YG
2091 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2092 desc_id, desc_index, 0, desc_buf,
2093 &buff_len);
da461cec
SJ
2094
2095 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
2096 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
2097 ufs_query_desc_max_size[desc_id])
2098 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
2099 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
2100 __func__, desc_id, param_offset, buff_len, ret);
2101 if (!ret)
2102 ret = -EINVAL;
2103
2104 goto out;
2105 }
2106
2107 if (is_kmalloc)
2108 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2109out:
2110 if (is_kmalloc)
2111 kfree(desc_buf);
2112 return ret;
2113}
2114
2115static inline int ufshcd_read_desc(struct ufs_hba *hba,
2116 enum desc_idn desc_id,
2117 int desc_index,
2118 u8 *buf,
2119 u32 size)
2120{
2121 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2122}
2123
2124static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2125 u8 *buf,
2126 u32 size)
2127{
2128 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2129}
2130
b573d484
YG
2131int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2132{
2133 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2134}
2135EXPORT_SYMBOL(ufshcd_read_device_desc);
2136
2137/**
2138 * ufshcd_read_string_desc - read string descriptor
2139 * @hba: pointer to adapter instance
2140 * @desc_index: descriptor index
2141 * @buf: pointer to buffer where descriptor would be read
2142 * @size: size of buf
2143 * @ascii: if true convert from unicode to ascii characters
2144 *
2145 * Return 0 in case of success, non-zero otherwise
2146 */
2147int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2148 u32 size, bool ascii)
2149{
2150 int err = 0;
2151
2152 err = ufshcd_read_desc(hba,
2153 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2154
2155 if (err) {
2156 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2157 __func__, QUERY_REQ_RETRIES, err);
2158 goto out;
2159 }
2160
2161 if (ascii) {
2162 int desc_len;
2163 int ascii_len;
2164 int i;
2165 char *buff_ascii;
2166
2167 desc_len = buf[0];
2168 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2169 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2170 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2171 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2172 __func__);
2173 err = -ENOMEM;
2174 goto out;
2175 }
2176
2177 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2178 if (!buff_ascii) {
2179 err = -ENOMEM;
fcbefc3b 2180 goto out;
b573d484
YG
2181 }
2182
2183 /*
2184 * the descriptor contains string in UTF16 format
2185 * we need to convert to utf-8 so it can be displayed
2186 */
2187 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2188 desc_len - QUERY_DESC_HDR_SIZE,
2189 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2190
2191 /* replace non-printable or non-ASCII characters with spaces */
2192 for (i = 0; i < ascii_len; i++)
2193 ufshcd_remove_non_printable(&buff_ascii[i]);
2194
2195 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2196 size - QUERY_DESC_HDR_SIZE);
2197 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2198 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG
2199 kfree(buff_ascii);
2200 }
2201out:
2202 return err;
2203}
2204EXPORT_SYMBOL(ufshcd_read_string_desc);
2205
da461cec
SJ
2206/**
2207 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2208 * @hba: Pointer to adapter instance
2209 * @lun: lun id
2210 * @param_offset: offset of the parameter to read
2211 * @param_read_buf: pointer to buffer where parameter would be read
2212 * @param_size: sizeof(param_read_buf)
2213 *
2214 * Return 0 in case of success, non-zero otherwise
2215 */
2216static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2217 int lun,
2218 enum unit_desc_param param_offset,
2219 u8 *param_read_buf,
2220 u32 param_size)
2221{
2222 /*
2223 * Unit descriptors are only available for general purpose LUs (LUN id
2224 * from 0 to 7) and RPMB Well known LU.
2225 */
0ce147d4 2226 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ
2227 return -EOPNOTSUPP;
2228
2229 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2230 param_offset, param_read_buf, param_size);
2231}
2232
7a3e97b0
SY
2233/**
2234 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2235 * @hba: per adapter instance
2236 *
2237 * 1. Allocate DMA memory for Command Descriptor array
2238 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2239 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2240 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2241 * (UTMRDL)
2242 * 4. Allocate memory for local reference block(lrb).
2243 *
2244 * Returns 0 for success, non-zero in case of failure
2245 */
2246static int ufshcd_memory_alloc(struct ufs_hba *hba)
2247{
2248 size_t utmrdl_size, utrdl_size, ucdl_size;
2249
2250 /* Allocate memory for UTP command descriptors */
2251 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ
2252 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2253 ucdl_size,
2254 &hba->ucdl_dma_addr,
2255 GFP_KERNEL);
7a3e97b0
SY
2256
2257 /*
2258 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2259 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2260 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2261 * be aligned to 128 bytes as well
2262 */
2263 if (!hba->ucdl_base_addr ||
2264 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2265 dev_err(hba->dev,
7a3e97b0
SY
2266 "Command Descriptor Memory allocation failed\n");
2267 goto out;
2268 }
2269
2270 /*
2271 * Allocate memory for UTP Transfer descriptors
2272 * UFSHCI requires 1024 byte alignment of UTRD
2273 */
2274 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ
2275 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2276 utrdl_size,
2277 &hba->utrdl_dma_addr,
2278 GFP_KERNEL);
7a3e97b0
SY
2279 if (!hba->utrdl_base_addr ||
2280 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2281 dev_err(hba->dev,
7a3e97b0
SY
2282 "Transfer Descriptor Memory allocation failed\n");
2283 goto out;
2284 }
2285
2286 /*
2287 * Allocate memory for UTP Task Management descriptors
2288 * UFSHCI requires 1024 byte alignment of UTMRD
2289 */
2290 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ
2291 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2292 utmrdl_size,
2293 &hba->utmrdl_dma_addr,
2294 GFP_KERNEL);
7a3e97b0
SY
2295 if (!hba->utmrdl_base_addr ||
2296 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2297 dev_err(hba->dev,
7a3e97b0
SY
2298 "Task Management Descriptor Memory allocation failed\n");
2299 goto out;
2300 }
2301
2302 /* Allocate memory for local reference block */
2953f850
SJ
2303 hba->lrb = devm_kzalloc(hba->dev,
2304 hba->nutrs * sizeof(struct ufshcd_lrb),
2305 GFP_KERNEL);
7a3e97b0 2306 if (!hba->lrb) {
3b1d0580 2307 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY
2308 goto out;
2309 }
2310 return 0;
2311out:
7a3e97b0
SY
2312 return -ENOMEM;
2313}
2314
2315/**
2316 * ufshcd_host_memory_configure - configure local reference block with
2317 * memory offsets
2318 * @hba: per adapter instance
2319 *
2320 * Configure Host memory space
2321 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2322 * address.
2323 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2324 * and PRDT offset.
2325 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2326 * into local reference block.
2327 */
2328static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2329{
2330 struct utp_transfer_cmd_desc *cmd_descp;
2331 struct utp_transfer_req_desc *utrdlp;
2332 dma_addr_t cmd_desc_dma_addr;
2333 dma_addr_t cmd_desc_element_addr;
2334 u16 response_offset;
2335 u16 prdt_offset;
2336 int cmd_desc_size;
2337 int i;
2338
2339 utrdlp = hba->utrdl_base_addr;
2340 cmd_descp = hba->ucdl_base_addr;
2341
2342 response_offset =
2343 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2344 prdt_offset =
2345 offsetof(struct utp_transfer_cmd_desc, prd_table);
2346
2347 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2348 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2349
2350 for (i = 0; i < hba->nutrs; i++) {
2351 /* Configure UTRD with command descriptor base address */
2352 cmd_desc_element_addr =
2353 (cmd_desc_dma_addr + (cmd_desc_size * i));
2354 utrdlp[i].command_desc_base_addr_lo =
2355 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2356 utrdlp[i].command_desc_base_addr_hi =
2357 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2358
2359 /* Response upiu and prdt offset should be in double words */
2360 utrdlp[i].response_upiu_offset =
2361 cpu_to_le16((response_offset >> 2));
2362 utrdlp[i].prd_table_offset =
2363 cpu_to_le16((prdt_offset >> 2));
2364 utrdlp[i].response_upiu_length =
3ca316c5 2365 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY
2366
2367 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT
2368 hba->lrb[i].ucd_req_ptr =
2369 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY
2370 hba->lrb[i].ucd_rsp_ptr =
2371 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2372 hba->lrb[i].ucd_prdt_ptr =
2373 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2374 }
2375}
2376
2377/**
2378 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2379 * @hba: per adapter instance
2380 *
2381 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2382 * in order to initialize the Unipro link startup procedure.
2383 * Once the Unipro links are up, the device connected to the controller
2384 * is detected.
2385 *
2386 * Returns 0 on success, non-zero value on failure
2387 */
2388static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2389{
6ccf44fe
SJ
2390 struct uic_command uic_cmd = {0};
2391 int ret;
7a3e97b0 2392
6ccf44fe 2393 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2394
6ccf44fe
SJ
2395 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2396 if (ret)
2397 dev_err(hba->dev,
2398 "dme-link-startup: error code %d\n", ret);
2399 return ret;
7a3e97b0
SY
2400}
2401
cad2e03d
YG
2402static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2403{
2404 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2405 unsigned long min_sleep_time_us;
2406
2407 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2408 return;
2409
2410 /*
2411 * last_dme_cmd_tstamp will be 0 only for 1st call to
2412 * this function
2413 */
2414 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2415 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2416 } else {
2417 unsigned long delta =
2418 (unsigned long) ktime_to_us(
2419 ktime_sub(ktime_get(),
2420 hba->last_dme_cmd_tstamp));
2421
2422 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2423 min_sleep_time_us =
2424 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2425 else
2426 return; /* no more delay required */
2427 }
2428
2429 /* allow sleep for extra 50us if needed */
2430 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2431}
2432
12b4fdb4
SJ
2433/**
2434 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2435 * @hba: per adapter instance
2436 * @attr_sel: uic command argument1
2437 * @attr_set: attribute set type as uic command argument2
2438 * @mib_val: setting value as uic command argument3
2439 * @peer: indicate whether peer or local
2440 *
2441 * Returns 0 on success, non-zero value on failure
2442 */
2443int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2444 u8 attr_set, u32 mib_val, u8 peer)
2445{
2446 struct uic_command uic_cmd = {0};
2447 static const char *const action[] = {
2448 "dme-set",
2449 "dme-peer-set"
2450 };
2451 const char *set = action[!!peer];
2452 int ret;
64238fbd 2453 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ
2454
2455 uic_cmd.command = peer ?
2456 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2457 uic_cmd.argument1 = attr_sel;
2458 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2459 uic_cmd.argument3 = mib_val;
2460
64238fbd
YG
2461 do {
2462 /* for peer attributes we retry upon failure */
2463 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2464 if (ret)
2465 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2466 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2467 } while (ret && peer && --retries);
2468
2469 if (!retries)
2470 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
2471 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2472 retries);
12b4fdb4
SJ
2473
2474 return ret;
2475}
2476EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2477
2478/**
2479 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2480 * @hba: per adapter instance
2481 * @attr_sel: uic command argument1
2482 * @mib_val: the value of the attribute as returned by the UIC command
2483 * @peer: indicate whether peer or local
2484 *
2485 * Returns 0 on success, non-zero value on failure
2486 */
2487int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2488 u32 *mib_val, u8 peer)
2489{
2490 struct uic_command uic_cmd = {0};
2491 static const char *const action[] = {
2492 "dme-get",
2493 "dme-peer-get"
2494 };
2495 const char *get = action[!!peer];
2496 int ret;
64238fbd 2497 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG
2498 struct ufs_pa_layer_attr orig_pwr_info;
2499 struct ufs_pa_layer_attr temp_pwr_info;
2500 bool pwr_mode_change = false;
2501
2502 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2503 orig_pwr_info = hba->pwr_info;
2504 temp_pwr_info = orig_pwr_info;
2505
2506 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2507 orig_pwr_info.pwr_rx == FAST_MODE) {
2508 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2509 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2510 pwr_mode_change = true;
2511 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2512 orig_pwr_info.pwr_rx == SLOW_MODE) {
2513 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2514 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2515 pwr_mode_change = true;
2516 }
2517 if (pwr_mode_change) {
2518 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2519 if (ret)
2520 goto out;
2521 }
2522 }
12b4fdb4
SJ
2523
2524 uic_cmd.command = peer ?
2525 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2526 uic_cmd.argument1 = attr_sel;
2527
64238fbd
YG
2528 do {
2529 /* for peer attributes we retry upon failure */
2530 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2531 if (ret)
2532 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2533 get, UIC_GET_ATTR_ID(attr_sel), ret);
2534 } while (ret && peer && --retries);
2535
2536 if (!retries)
2537 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
2538 get, UIC_GET_ATTR_ID(attr_sel), retries);
12b4fdb4 2539
64238fbd 2540 if (mib_val && !ret)
12b4fdb4 2541 *mib_val = uic_cmd.argument3;
874237f7
YG
2542
2543 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2544 && pwr_mode_change)
2545 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ
2546out:
2547 return ret;
2548}
2549EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2550
53b3d9c3 2551/**
57d104c1
SJ
2552 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2553 * state) and waits for it to take effect.
2554 *
53b3d9c3 2555 * @hba: per adapter instance
57d104c1
SJ
2556 * @cmd: UIC command to execute
2557 *
2558 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2559 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2560 * and device UniPro link and hence it's final completion would be indicated by
2561 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2562 * addition to normal UIC command completion Status (UCCS). This function only
2563 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ
2564 *
2565 * Returns 0 on success, non-zero value on failure
2566 */
57d104c1 2567static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2568{
57d104c1 2569 struct completion uic_async_done;
53b3d9c3
SJ
2570 unsigned long flags;
2571 u8 status;
2572 int ret;
d75f7fe4 2573 bool reenable_intr = false;
53b3d9c3 2574
53b3d9c3 2575 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2576 init_completion(&uic_async_done);
cad2e03d 2577 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ
2578
2579 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2580 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG
2581 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2582 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2583 /*
2584 * Make sure UIC command completion interrupt is disabled before
2585 * issuing UIC command.
2586 */
2587 wmb();
2588 reenable_intr = true;
57d104c1 2589 }
d75f7fe4
YG
2590 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2591 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ
2592 if (ret) {
2593 dev_err(hba->dev,
2594 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2595 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ
2596 goto out;
2597 }
2598
57d104c1 2599 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ
2600 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2601 dev_err(hba->dev,
57d104c1
SJ
2602 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2603 cmd->command, cmd->argument3);
53b3d9c3
SJ
2604 ret = -ETIMEDOUT;
2605 goto out;
2606 }
2607
2608 status = ufshcd_get_upmcrs(hba);
2609 if (status != PWR_LOCAL) {
2610 dev_err(hba->dev,
73615428 2611 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2612 cmd->command, status);
53b3d9c3
SJ
2613 ret = (status != PWR_OK) ? status : -1;
2614 }
2615out:
2616 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2617 hba->active_uic_cmd = NULL;
57d104c1 2618 hba->uic_async_done = NULL;
d75f7fe4
YG
2619 if (reenable_intr)
2620 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ
2621 spin_unlock_irqrestore(hba->host->host_lock, flags);
2622 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2623
53b3d9c3
SJ
2624 return ret;
2625}
2626
57d104c1
SJ
2627/**
2628 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2629 * using DME_SET primitives.
2630 * @hba: per adapter instance
2631 * @mode: powr mode value
2632 *
2633 * Returns 0 on success, non-zero value on failure
2634 */
2635static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2636{
2637 struct uic_command uic_cmd = {0};
1ab27c9c 2638 int ret;
57d104c1 2639
c3a2f9ee
YG
2640 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2641 ret = ufshcd_dme_set(hba,
2642 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2643 if (ret) {
2644 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2645 __func__, ret);
2646 goto out;
2647 }
2648 }
2649
57d104c1
SJ
2650 uic_cmd.command = UIC_CMD_DME_SET;
2651 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2652 uic_cmd.argument3 = mode;
1ab27c9c
ST
2653 ufshcd_hold(hba, false);
2654 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2655 ufshcd_release(hba);
57d104c1 2656
c3a2f9ee 2657out:
1ab27c9c 2658 return ret;
57d104c1
SJ
2659}
2660
53c12d0e
YG
2661static int ufshcd_link_recovery(struct ufs_hba *hba)
2662{
2663 int ret;
2664 unsigned long flags;
2665
2666 spin_lock_irqsave(hba->host->host_lock, flags);
2667 hba->ufshcd_state = UFSHCD_STATE_RESET;
2668 ufshcd_set_eh_in_progress(hba);
2669 spin_unlock_irqrestore(hba->host->host_lock, flags);
2670
2671 ret = ufshcd_host_reset_and_restore(hba);
2672
2673 spin_lock_irqsave(hba->host->host_lock, flags);
2674 if (ret)
2675 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2676 ufshcd_clear_eh_in_progress(hba);
2677 spin_unlock_irqrestore(hba->host->host_lock, flags);
2678
2679 if (ret)
2680 dev_err(hba->dev, "%s: link recovery failed, err %d",
2681 __func__, ret);
2682
2683 return ret;
2684}
2685
87d0b4a6 2686static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 2687{
87d0b4a6 2688 int ret;
57d104c1
SJ
2689 struct uic_command uic_cmd = {0};
2690
2691 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG
2692 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2693
53c12d0e 2694 if (ret) {
87d0b4a6
YG
2695 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
2696 __func__, ret);
2697
53c12d0e
YG
2698 /*
2699 * If link recovery fails then return error so that caller
2700 * don't retry the hibern8 enter again.
2701 */
2702 if (ufshcd_link_recovery(hba))
2703 ret = -ENOLINK;
2704 }
2705
87d0b4a6
YG
2706 return ret;
2707}
2708
2709static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2710{
2711 int ret = 0, retries;
57d104c1 2712
87d0b4a6
YG
2713 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
2714 ret = __ufshcd_uic_hibern8_enter(hba);
2715 if (!ret || ret == -ENOLINK)
2716 goto out;
2717 }
2718out:
2719 return ret;
57d104c1
SJ
2720}
2721
2722static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2723{
2724 struct uic_command uic_cmd = {0};
2725 int ret;
2726
2727 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2728 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2729 if (ret) {
53c12d0e
YG
2730 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
2731 __func__, ret);
2732 ret = ufshcd_link_recovery(hba);
57d104c1
SJ
2733 }
2734
2735 return ret;
2736}
2737
5064636c
YG
2738 /**
2739 * ufshcd_init_pwr_info - setting the POR (power on reset)
2740 * values in hba power info
2741 * @hba: per-adapter instance
2742 */
2743static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2744{
2745 hba->pwr_info.gear_rx = UFS_PWM_G1;
2746 hba->pwr_info.gear_tx = UFS_PWM_G1;
2747 hba->pwr_info.lane_rx = 1;
2748 hba->pwr_info.lane_tx = 1;
2749 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2750 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2751 hba->pwr_info.hs_rate = 0;
2752}
2753
d3e89bac 2754/**
7eb584db
DR
2755 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2756 * @hba: per-adapter instance
d3e89bac 2757 */
7eb584db 2758static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2759{
7eb584db
DR
2760 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2761
2762 if (hba->max_pwr_info.is_valid)
2763 return 0;
2764
2765 pwr_info->pwr_tx = FASTAUTO_MODE;
2766 pwr_info->pwr_rx = FASTAUTO_MODE;
2767 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ
2768
2769 /* Get the connected lane count */
7eb584db
DR
2770 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2771 &pwr_info->lane_rx);
2772 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2773 &pwr_info->lane_tx);
2774
2775 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2776 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2777 __func__,
2778 pwr_info->lane_rx,
2779 pwr_info->lane_tx);
2780 return -EINVAL;
2781 }
d3e89bac
SJ
2782
2783 /*
2784 * First, get the maximum gears of HS speed.
2785 * If a zero value, it means there is no HSGEAR capability.
2786 * Then, get the maximum gears of PWM speed.
2787 */
7eb584db
DR
2788 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2789 if (!pwr_info->gear_rx) {
2790 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2791 &pwr_info->gear_rx);
2792 if (!pwr_info->gear_rx) {
2793 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2794 __func__, pwr_info->gear_rx);
2795 return -EINVAL;
2796 }
2797 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ
2798 }
2799
7eb584db
DR
2800 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2801 &pwr_info->gear_tx);
2802 if (!pwr_info->gear_tx) {
d3e89bac 2803 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR
2804 &pwr_info->gear_tx);
2805 if (!pwr_info->gear_tx) {
2806 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2807 __func__, pwr_info->gear_tx);
2808 return -EINVAL;
2809 }
2810 pwr_info->pwr_tx = SLOWAUTO_MODE;
2811 }
2812
2813 hba->max_pwr_info.is_valid = true;
2814 return 0;
2815}
2816
2817static int ufshcd_change_power_mode(struct ufs_hba *hba,
2818 struct ufs_pa_layer_attr *pwr_mode)
2819{
2820 int ret;
2821
2822 /* if already configured to the requested pwr_mode */
2823 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2824 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2825 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2826 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2827 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2828 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2829 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2830 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2831 return 0;
d3e89bac
SJ
2832 }
2833
2834 /*
2835 * Configure attributes for power mode change with below.
2836 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2837 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2838 * - PA_HSSERIES
2839 */
7eb584db
DR
2840 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2841 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2842 pwr_mode->lane_rx);
2843 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2844 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2845 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR
2846 else
2847 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2848
7eb584db
DR
2849 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2850 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2851 pwr_mode->lane_tx);
2852 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2853 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2854 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR
2855 else
2856 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2857
7eb584db
DR
2858 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2859 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2860 pwr_mode->pwr_rx == FAST_MODE ||
2861 pwr_mode->pwr_tx == FAST_MODE)
2862 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2863 pwr_mode->hs_rate);
d3e89bac 2864
7eb584db
DR
2865 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2866 | pwr_mode->pwr_tx);
2867
2868 if (ret) {
d3e89bac 2869 dev_err(hba->dev,
7eb584db
DR
2870 "%s: power mode change failed %d\n", __func__, ret);
2871 } else {
0263bcd0
YG
2872 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2873 pwr_mode);
7eb584db
DR
2874
2875 memcpy(&hba->pwr_info, pwr_mode,
2876 sizeof(struct ufs_pa_layer_attr));
2877 }
2878
2879 return ret;
2880}
2881
2882/**
2883 * ufshcd_config_pwr_mode - configure a new power mode
2884 * @hba: per-adapter instance
2885 * @desired_pwr_mode: desired power configuration
2886 */
2887static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2888 struct ufs_pa_layer_attr *desired_pwr_mode)
2889{
2890 struct ufs_pa_layer_attr final_params = { 0 };
2891 int ret;
2892
0263bcd0
YG
2893 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2894 desired_pwr_mode, &final_params);
2895
2896 if (ret)
7eb584db
DR
2897 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2898
2899 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ
2900
2901 return ret;
2902}
2903
68078d5c
DR
2904/**
2905 * ufshcd_complete_dev_init() - checks device readiness
2906 * hba: per-adapter instance
2907 *
2908 * Set fDeviceInit flag and poll until device toggles it.
2909 */
2910static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2911{
dc3c8d3a
YG
2912 int i;
2913 int err;
68078d5c
DR
2914 bool flag_res = 1;
2915
dc3c8d3a
YG
2916 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2917 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR
2918 if (err) {
2919 dev_err(hba->dev,
2920 "%s setting fDeviceInit flag failed with error %d\n",
2921 __func__, err);
2922 goto out;
2923 }
2924
dc3c8d3a
YG
2925 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
2926 for (i = 0; i < 1000 && !err && flag_res; i++)
2927 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
2928 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2929
68078d5c
DR
2930 if (err)
2931 dev_err(hba->dev,
2932 "%s reading fDeviceInit flag failed with error %d\n",
2933 __func__, err);
2934 else if (flag_res)
2935 dev_err(hba->dev,
2936 "%s fDeviceInit was not cleared by the device\n",
2937 __func__);
2938
2939out:
2940 return err;
2941}
2942
7a3e97b0
SY
2943/**
2944 * ufshcd_make_hba_operational - Make UFS controller operational
2945 * @hba: per adapter instance
2946 *
2947 * To bring UFS host controller to operational state,
5c0c28a8
SRT
2948 * 1. Enable required interrupts
2949 * 2. Configure interrupt aggregation
897efe62 2950 * 3. Program UTRL and UTMRL base address
5c0c28a8 2951 * 4. Configure run-stop-registers
7a3e97b0
SY
2952 *
2953 * Returns 0 on success, non-zero value on failure
2954 */
2955static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2956{
2957 int err = 0;
2958 u32 reg;
2959
6ccf44fe
SJ
2960 /* Enable required interrupts */
2961 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2962
2963 /* Configure interrupt aggregation */
b852190e
YG
2964 if (ufshcd_is_intr_aggr_allowed(hba))
2965 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
2966 else
2967 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ
2968
2969 /* Configure UTRL and UTMRL base address registers */
2970 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2971 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2972 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2973 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2974 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2975 REG_UTP_TASK_REQ_LIST_BASE_L);
2976 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2977 REG_UTP_TASK_REQ_LIST_BASE_H);
2978
897efe62
YG
2979 /*
2980 * Make sure base address and interrupt setup are updated before
2981 * enabling the run/stop registers below.
2982 */
2983 wmb();
2984
7a3e97b0
SY
2985 /*
2986 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 2987 */
5c0c28a8 2988 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY
2989 if (!(ufshcd_get_lists_status(reg))) {
2990 ufshcd_enable_run_stop_reg(hba);
2991 } else {
3b1d0580 2992 dev_err(hba->dev,
7a3e97b0
SY
2993 "Host controller not ready to process requests");
2994 err = -EIO;
2995 goto out;
2996 }
2997
7a3e97b0
SY
2998out:
2999 return err;
3000}
3001
596585a2
YG
3002/**
3003 * ufshcd_hba_stop - Send controller to reset state
3004 * @hba: per adapter instance
3005 * @can_sleep: perform sleep or just spin
3006 */
3007static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3008{
3009 int err;
3010
3011 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3012 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3013 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3014 10, 1, can_sleep);
3015 if (err)
3016 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3017}
3018
7a3e97b0
SY
3019/**
3020 * ufshcd_hba_enable - initialize the controller
3021 * @hba: per adapter instance
3022 *
3023 * The controller resets itself and controller firmware initialization
3024 * sequence kicks off. When controller is ready it will set
3025 * the Host Controller Enable bit to 1.
3026 *
3027 * Returns 0 on success, non-zero value on failure
3028 */
3029static int ufshcd_hba_enable(struct ufs_hba *hba)
3030{
3031 int retry;
3032
3033 /*
3034 * msleep of 1 and 5 used in this function might result in msleep(20),
3035 * but it was necessary to send the UFS FPGA to reset mode during
3036 * development and testing of this driver. msleep can be changed to
3037 * mdelay and retry count can be reduced based on the controller.
3038 */
596585a2 3039 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3040 /* change controller state to "reset state" */
596585a2 3041 ufshcd_hba_stop(hba, true);
7a3e97b0 3042
57d104c1
SJ
3043 /* UniPro link is disabled at this point */
3044 ufshcd_set_link_off(hba);
3045
0263bcd0 3046 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3047
7a3e97b0
SY
3048 /* start controller initialization sequence */
3049 ufshcd_hba_start(hba);
3050
3051 /*
3052 * To initialize a UFS host controller HCE bit must be set to 1.
3053 * During initialization the HCE bit value changes from 1->0->1.
3054 * When the host controller completes initialization sequence
3055 * it sets the value of HCE bit to 1. The same HCE bit is read back
3056 * to check if the controller has completed initialization sequence.
3057 * So without this delay the value HCE = 1, set in the previous
3058 * instruction might be read back.
3059 * This delay can be changed based on the controller.
3060 */
3061 msleep(1);
3062
3063 /* wait for the host controller to complete initialization */
3064 retry = 10;
3065 while (ufshcd_is_hba_active(hba)) {
3066 if (retry) {
3067 retry--;
3068 } else {
3b1d0580 3069 dev_err(hba->dev,
7a3e97b0
SY
3070 "Controller enable failed\n");
3071 return -EIO;
3072 }
3073 msleep(5);
3074 }
5c0c28a8 3075
1d337ec2 3076 /* enable UIC related interrupts */
57d104c1 3077 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3078
0263bcd0 3079 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3080
7a3e97b0
SY
3081 return 0;
3082}
3083
7ca38cf3
YG
3084static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3085{
3086 int tx_lanes, i, err = 0;
3087
3088 if (!peer)
3089 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3090 &tx_lanes);
3091 else
3092 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3093 &tx_lanes);
3094 for (i = 0; i < tx_lanes; i++) {
3095 if (!peer)
3096 err = ufshcd_dme_set(hba,
3097 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3098 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3099 0);
3100 else
3101 err = ufshcd_dme_peer_set(hba,
3102 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3103 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3104 0);
3105 if (err) {
3106 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3107 __func__, peer, i, err);
3108 break;
3109 }
3110 }
3111
3112 return err;
3113}
3114
3115static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3116{
3117 return ufshcd_disable_tx_lcc(hba, true);
3118}
3119
7a3e97b0 3120/**
6ccf44fe 3121 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY
3122 * @hba: per adapter instance
3123 *
6ccf44fe 3124 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3125 */
6ccf44fe 3126static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3127{
6ccf44fe 3128 int ret;
1d337ec2 3129 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 3130
1d337ec2 3131 do {
0263bcd0 3132 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3133
1d337ec2 3134 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3135
1d337ec2
SRT
3136 /* check if device is detected by inter-connect layer */
3137 if (!ret && !ufshcd_is_device_present(hba)) {
3138 dev_err(hba->dev, "%s: Device not present\n", __func__);
3139 ret = -ENXIO;
3140 goto out;
3141 }
6ccf44fe 3142
1d337ec2
SRT
3143 /*
3144 * DME link lost indication is only received when link is up,
3145 * but we can't be sure if the link is up until link startup
3146 * succeeds. So reset the local Uni-Pro and try again.
3147 */
3148 if (ret && ufshcd_hba_enable(hba))
3149 goto out;
3150 } while (ret && retries--);
3151
3152 if (ret)
3153 /* failed to get the link up... retire */
5c0c28a8 3154 goto out;
5c0c28a8 3155
7ca38cf3
YG
3156 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3157 ret = ufshcd_disable_device_tx_lcc(hba);
3158 if (ret)
3159 goto out;
3160 }
3161
5c0c28a8 3162 /* Include any host controller configuration via UIC commands */
0263bcd0
YG
3163 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3164 if (ret)
3165 goto out;
7a3e97b0 3166
5c0c28a8 3167 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ
3168out:
3169 if (ret)
3170 dev_err(hba->dev, "link startup failed %d\n", ret);
3171 return ret;
7a3e97b0
SY
3172}
3173
5a0b0cb9
SRT
3174/**
3175 * ufshcd_verify_dev_init() - Verify device initialization
3176 * @hba: per-adapter instance
3177 *
3178 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3179 * device Transport Protocol (UTP) layer is ready after a reset.
3180 * If the UTP layer at the device side is not initialized, it may
3181 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3182 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3183 */
3184static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3185{
3186 int err = 0;
3187 int retries;
3188
1ab27c9c 3189 ufshcd_hold(hba, false);
5a0b0cb9
SRT
3190 mutex_lock(&hba->dev_cmd.lock);
3191 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3192 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3193 NOP_OUT_TIMEOUT);
3194
3195 if (!err || err == -ETIMEDOUT)
3196 break;
3197
3198 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3199 }
3200 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3201 ufshcd_release(hba);
5a0b0cb9
SRT
3202
3203 if (err)
3204 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3205 return err;
3206}
3207
0ce147d4
SJ
3208/**
3209 * ufshcd_set_queue_depth - set lun queue depth
3210 * @sdev: pointer to SCSI device
3211 *
3212 * Read bLUQueueDepth value and activate scsi tagged command
3213 * queueing. For WLUN, queue depth is set to 1. For best-effort
3214 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3215 * value that host can queue.
3216 */
3217static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3218{
3219 int ret = 0;
3220 u8 lun_qdepth;
3221 struct ufs_hba *hba;
3222
3223 hba = shost_priv(sdev->host);
3224
3225 lun_qdepth = hba->nutrs;
3226 ret = ufshcd_read_unit_desc_param(hba,
3227 ufshcd_scsi_to_upiu_lun(sdev->lun),
3228 UNIT_DESC_PARAM_LU_Q_DEPTH,
3229 &lun_qdepth,
3230 sizeof(lun_qdepth));
3231
3232 /* Some WLUN doesn't support unit descriptor */
3233 if (ret == -EOPNOTSUPP)
3234 lun_qdepth = 1;
3235 else if (!lun_qdepth)
3236 /* eventually, we can figure out the real queue depth */
3237 lun_qdepth = hba->nutrs;
3238 else
3239 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3240
3241 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3242 __func__, lun_qdepth);
db5ed4df 3243 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ
3244}
3245
57d104c1
SJ
3246/*
3247 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3248 * @hba: per-adapter instance
3249 * @lun: UFS device lun id
3250 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3251 *
3252 * Returns 0 in case of success and b_lu_write_protect status would be returned
3253 * @b_lu_write_protect parameter.
3254 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3255 * Returns -EINVAL in case of invalid parameters passed to this function.
3256 */
3257static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3258 u8 lun,
3259 u8 *b_lu_write_protect)
3260{
3261 int ret;
3262
3263 if (!b_lu_write_protect)
3264 ret = -EINVAL;
3265 /*
3266 * According to UFS device spec, RPMB LU can't be write
3267 * protected so skip reading bLUWriteProtect parameter for
3268 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3269 */
3270 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3271 ret = -ENOTSUPP;
3272 else
3273 ret = ufshcd_read_unit_desc_param(hba,
3274 lun,
3275 UNIT_DESC_PARAM_LU_WR_PROTECT,
3276 b_lu_write_protect,
3277 sizeof(*b_lu_write_protect));
3278 return ret;
3279}
3280
3281/**
3282 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3283 * status
3284 * @hba: per-adapter instance
3285 * @sdev: pointer to SCSI device
3286 *
3287 */
3288static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3289 struct scsi_device *sdev)
3290{
3291 if (hba->dev_info.f_power_on_wp_en &&
3292 !hba->dev_info.is_lu_power_on_wp) {
3293 u8 b_lu_write_protect;
3294
3295 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3296 &b_lu_write_protect) &&
3297 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3298 hba->dev_info.is_lu_power_on_wp = true;
3299 }
3300}
3301
7a3e97b0
SY
3302/**
3303 * ufshcd_slave_alloc - handle initial SCSI device configurations
3304 * @sdev: pointer to SCSI device
3305 *
3306 * Returns success
3307 */
3308static int ufshcd_slave_alloc(struct scsi_device *sdev)
3309{
3310 struct ufs_hba *hba;
3311
3312 hba = shost_priv(sdev->host);
7a3e97b0
SY
3313
3314 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3315 sdev->use_10_for_ms = 1;
7a3e97b0 3316
e8e7f271
SRT
3317 /* allow SCSI layer to restart the device in case of errors */
3318 sdev->allow_restart = 1;
4264fd61 3319
b2a6c522
SRT
3320 /* REPORT SUPPORTED OPERATION CODES is not supported */
3321 sdev->no_report_opcodes = 1;
3322
e8e7f271 3323
0ce147d4 3324 ufshcd_set_queue_depth(sdev);
4264fd61 3325
57d104c1
SJ
3326 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3327
7a3e97b0
SY
3328 return 0;
3329}
3330
4264fd61
SRT
3331/**
3332 * ufshcd_change_queue_depth - change queue depth
3333 * @sdev: pointer to SCSI device
3334 * @depth: required depth to set
4264fd61 3335 *
db5ed4df 3336 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3337 */
db5ed4df 3338static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT
3339{
3340 struct ufs_hba *hba = shost_priv(sdev->host);
3341
3342 if (depth > hba->nutrs)
3343 depth = hba->nutrs;
db5ed4df 3344 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT
3345}
3346
eeda4749
AM
3347/**
3348 * ufshcd_slave_configure - adjust SCSI device configurations
3349 * @sdev: pointer to SCSI device
3350 */
3351static int ufshcd_slave_configure(struct scsi_device *sdev)
3352{
3353 struct request_queue *q = sdev->request_queue;
3354
3355 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3356 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3357
3358 return 0;
3359}
3360
7a3e97b0
SY
3361/**
3362 * ufshcd_slave_destroy - remove SCSI device configurations
3363 * @sdev: pointer to SCSI device
3364 */
3365static void ufshcd_slave_destroy(struct scsi_device *sdev)
3366{
3367 struct ufs_hba *hba;
3368
3369 hba = shost_priv(sdev->host);
0ce147d4 3370 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM
3371 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3372 unsigned long flags;
3373
3374 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3375 hba->sdev_ufs_device = NULL;
7c48bfd0
AM
3376 spin_unlock_irqrestore(hba->host->host_lock, flags);
3377 }
7a3e97b0
SY
3378}
3379
3380/**
3381 * ufshcd_task_req_compl - handle task management request completion
3382 * @hba: per adapter instance
3383 * @index: index of the completed request
e2933132 3384 * @resp: task management service response
7a3e97b0 3385 *
e2933132 3386 * Returns non-zero value on error, zero on success
7a3e97b0 3387 */
e2933132 3388static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY
3389{
3390 struct utp_task_req_desc *task_req_descp;
3391 struct utp_upiu_task_rsp *task_rsp_upiup;
3392 unsigned long flags;
3393 int ocs_value;
3394 int task_result;
3395
3396 spin_lock_irqsave(hba->host->host_lock, flags);
3397
3398 /* Clear completed tasks from outstanding_tasks */
3399 __clear_bit(index, &hba->outstanding_tasks);
3400
3401 task_req_descp = hba->utmrdl_base_addr;
3402 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3403
3404 if (ocs_value == OCS_SUCCESS) {
3405 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3406 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK
3407 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3408 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT
3409 if (resp)
3410 *resp = (u8)task_result;
7a3e97b0 3411 } else {
e2933132
SRT
3412 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3413 __func__, ocs_value);
7a3e97b0
SY
3414 }
3415 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT
3416
3417 return ocs_value;
7a3e97b0
SY
3418}
3419
7a3e97b0
SY
3420/**
3421 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3422 * @lrb: pointer to local reference block of completed command
3423 * @scsi_status: SCSI command status
3424 *
3425 * Returns value base on SCSI command status
3426 */
3427static inline int
3428ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3429{
3430 int result = 0;
3431
3432 switch (scsi_status) {
7a3e97b0 3433 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ
3434 ufshcd_copy_sense_data(lrbp);
3435 case SAM_STAT_GOOD:
7a3e97b0
SY
3436 result |= DID_OK << 16 |
3437 COMMAND_COMPLETE << 8 |
1c2623c5 3438 scsi_status;
7a3e97b0
SY
3439 break;
3440 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3441 case SAM_STAT_BUSY:
7a3e97b0 3442 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ
3443 ufshcd_copy_sense_data(lrbp);
3444 result |= scsi_status;
7a3e97b0
SY
3445 break;
3446 default:
3447 result |= DID_ERROR << 16;
3448 break;
3449 } /* end of switch */
3450
3451 return result;
3452}
3453
3454/**
3455 * ufshcd_transfer_rsp_status - Get overall status of the response
3456 * @hba: per adapter instance
3457 * @lrb: pointer to local reference block of completed command
3458 *
3459 * Returns result of the command to notify SCSI midlayer
3460 */
3461static inline int
3462ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3463{
3464 int result = 0;
3465 int scsi_status;
3466 int ocs;
3467
3468 /* overall command status of utrd */
3469 ocs = ufshcd_get_tr_ocs(lrbp);
3470
3471 switch (ocs) {
3472 case OCS_SUCCESS:
5a0b0cb9 3473 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3474
5a0b0cb9
SRT
3475 switch (result) {
3476 case UPIU_TRANSACTION_RESPONSE:
3477 /*
3478 * get the response UPIU result to extract
3479 * the SCSI command status
3480 */
3481 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3482
3483 /*
3484 * get the result based on SCSI status response
3485 * to notify the SCSI midlayer of the command status
3486 */
3487 scsi_status = result & MASK_SCSI_STATUS;
3488 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3489
f05ac2e5
YG
3490 /*
3491 * Currently we are only supporting BKOPs exception
3492 * events hence we can ignore BKOPs exception event
3493 * during power management callbacks. BKOPs exception
3494 * event is not expected to be raised in runtime suspend
3495 * callback as it allows the urgent bkops.
3496 * During system suspend, we are anyway forcefully
3497 * disabling the bkops and if urgent bkops is needed
3498 * it will be enabled on system resume. Long term
3499 * solution could be to abort the system suspend if
3500 * UFS device needs urgent BKOPs.
3501 */
3502 if (!hba->pm_op_in_progress &&
3503 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3504 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT
3505 break;
3506 case UPIU_TRANSACTION_REJECT_UPIU:
3507 /* TODO: handle Reject UPIU Response */
3508 result = DID_ERROR << 16;
3b1d0580 3509 dev_err(hba->dev,
5a0b0cb9
SRT
3510 "Reject UPIU not fully implemented\n");
3511 break;
3512 default:
3513 result = DID_ERROR << 16;
3514 dev_err(hba->dev,
3515 "Unexpected request response code = %x\n",
3516 result);
7a3e97b0
SY
3517 break;
3518 }
7a3e97b0
SY
3519 break;
3520 case OCS_ABORTED:
3521 result |= DID_ABORT << 16;
3522 break;
e8e7f271
SRT
3523 case OCS_INVALID_COMMAND_STATUS:
3524 result |= DID_REQUEUE << 16;
3525 break;
7a3e97b0
SY
3526 case OCS_INVALID_CMD_TABLE_ATTR:
3527 case OCS_INVALID_PRDT_ATTR:
3528 case OCS_MISMATCH_DATA_BUF_SIZE:
3529 case OCS_MISMATCH_RESP_UPIU_SIZE:
3530 case OCS_PEER_COMM_FAILURE:
3531 case OCS_FATAL_ERROR:
3532 default:
3533 result |= DID_ERROR << 16;
3b1d0580 3534 dev_err(hba->dev,
7a3e97b0
SY
3535 "OCS error from controller = %x\n", ocs);
3536 break;
3537 } /* end of switch */
3538
3539 return result;
3540}
3541
6ccf44fe
SJ
3542/**
3543 * ufshcd_uic_cmd_compl - handle completion of uic command
3544 * @hba: per adapter instance
53b3d9c3 3545 * @intr_status: interrupt status generated by the controller
6ccf44fe 3546 */
53b3d9c3 3547static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3548{
53b3d9c3 3549 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ
3550 hba->active_uic_cmd->argument2 |=
3551 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ
3552 hba->active_uic_cmd->argument3 =
3553 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ
3554 complete(&hba->active_uic_cmd->done);
3555 }
53b3d9c3 3556
57d104c1
SJ
3557 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3558 complete(hba->uic_async_done);
6ccf44fe
SJ
3559}
3560
7a3e97b0 3561/**
9a47ec7c 3562 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3563 * @hba: per adapter instance
9a47ec7c 3564 * @completed_reqs: requests to complete
7a3e97b0 3565 */
9a47ec7c
YG
3566static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3567 unsigned long completed_reqs)
7a3e97b0 3568{
5a0b0cb9
SRT
3569 struct ufshcd_lrb *lrbp;
3570 struct scsi_cmnd *cmd;
7a3e97b0
SY
3571 int result;
3572 int index;
e9d501b1 3573
e9d501b1
DR
3574 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3575 lrbp = &hba->lrb[index];
3576 cmd = lrbp->cmd;
3577 if (cmd) {
3578 result = ufshcd_transfer_rsp_status(hba, lrbp);
3579 scsi_dma_unmap(cmd);
3580 cmd->result = result;
3581 /* Mark completed command as NULL in LRB */
3582 lrbp->cmd = NULL;
3583 clear_bit_unlock(index, &hba->lrb_in_use);
3584 /* Do not touch lrbp after scsi done */
3585 cmd->scsi_done(cmd);
1ab27c9c 3586 __ufshcd_release(hba);
300bb13f
JP
3587 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3588 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR
3589 if (hba->dev_cmd.complete)
3590 complete(hba->dev_cmd.complete);
3591 }
3592 }
7a3e97b0
SY
3593
3594 /* clear corresponding bits of completed commands */
3595 hba->outstanding_reqs ^= completed_reqs;
3596
856b3483
ST
3597 ufshcd_clk_scaling_update_busy(hba);
3598
5a0b0cb9
SRT
3599 /* we might have free'd some tags above */
3600 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY
3601}
3602
9a47ec7c
YG
3603/**
3604 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3605 * @hba: per adapter instance
3606 */
3607static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3608{
3609 unsigned long completed_reqs;
3610 u32 tr_doorbell;
3611
3612 /* Resetting interrupt aggregation counters first and reading the
3613 * DOOR_BELL afterward allows us to handle all the completed requests.
3614 * In order to prevent other interrupts starvation the DB is read once
3615 * after reset. The down side of this solution is the possibility of
3616 * false interrupt if device completes another request after resetting
3617 * aggregation and before reading the DB.
3618 */
3619 if (ufshcd_is_intr_aggr_allowed(hba))
3620 ufshcd_reset_intr_aggr(hba);
3621
3622 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3623 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3624
3625 __ufshcd_transfer_req_compl(hba, completed_reqs);
3626}
3627
66ec6d59
SRT
3628/**
3629 * ufshcd_disable_ee - disable exception event
3630 * @hba: per-adapter instance
3631 * @mask: exception event to disable
3632 *
3633 * Disables exception event in the device so that the EVENT_ALERT
3634 * bit is not set.
3635 *
3636 * Returns zero on success, non-zero error value on failure.
3637 */
3638static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3639{
3640 int err = 0;
3641 u32 val;
3642
3643 if (!(hba->ee_ctrl_mask & mask))
3644 goto out;
3645
3646 val = hba->ee_ctrl_mask & ~mask;
3647 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3648 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT
3649 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3650 if (!err)
3651 hba->ee_ctrl_mask &= ~mask;
3652out:
3653 return err;
3654}
3655
3656/**
3657 * ufshcd_enable_ee - enable exception event
3658 * @hba: per-adapter instance
3659 * @mask: exception event to enable
3660 *
3661 * Enable corresponding exception event in the device to allow
3662 * device to alert host in critical scenarios.
3663 *
3664 * Returns zero on success, non-zero error value on failure.
3665 */
3666static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3667{
3668 int err = 0;
3669 u32 val;
3670
3671 if (hba->ee_ctrl_mask & mask)
3672 goto out;
3673
3674 val = hba->ee_ctrl_mask | mask;
3675 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3676 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT
3677 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3678 if (!err)
3679 hba->ee_ctrl_mask |= mask;
3680out:
3681 return err;
3682}
3683
3684/**
3685 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3686 * @hba: per-adapter instance
3687 *
3688 * Allow device to manage background operations on its own. Enabling
3689 * this might lead to inconsistent latencies during normal data transfers
3690 * as the device is allowed to manage its own way of handling background
3691 * operations.
3692 *
3693 * Returns zero on success, non-zero on failure.
3694 */
3695static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3696{
3697 int err = 0;
3698
3699 if (hba->auto_bkops_enabled)
3700 goto out;
3701
dc3c8d3a 3702 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT
3703 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3704 if (err) {
3705 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3706 __func__, err);
3707 goto out;
3708 }
3709
3710 hba->auto_bkops_enabled = true;
3711
3712 /* No need of URGENT_BKOPS exception from the device */
3713 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3714 if (err)
3715 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3716 __func__, err);
3717out:
3718 return err;
3719}
3720
3721/**
3722 * ufshcd_disable_auto_bkops - block device in doing background operations
3723 * @hba: per-adapter instance
3724 *
3725 * Disabling background operations improves command response latency but
3726 * has drawback of device moving into critical state where the device is
3727 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3728 * host is idle so that BKOPS are managed effectively without any negative
3729 * impacts.
3730 *
3731 * Returns zero on success, non-zero on failure.
3732 */
3733static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3734{
3735 int err = 0;
3736
3737 if (!hba->auto_bkops_enabled)
3738 goto out;
3739
3740 /*
3741 * If host assisted BKOPs is to be enabled, make sure
3742 * urgent bkops exception is allowed.
3743 */
3744 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3745 if (err) {
3746 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3747 __func__, err);
3748 goto out;
3749 }
3750
dc3c8d3a 3751 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT
3752 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3753 if (err) {
3754 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3755 __func__, err);
3756 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3757 goto out;
3758 }
3759
3760 hba->auto_bkops_enabled = false;
3761out:
3762 return err;
3763}
3764
3765/**
3766 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3767 * @hba: per adapter instance
3768 *
3769 * After a device reset the device may toggle the BKOPS_EN flag
3770 * to default value. The s/w tracking variables should be updated
3771 * as well. Do this by forcing enable of auto bkops.
3772 */
3773static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3774{
3775 hba->auto_bkops_enabled = false;
3776 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3777 ufshcd_enable_auto_bkops(hba);
3778}
3779
3780static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3781{
5e86ae44 3782 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT
3783 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3784}
3785
3786/**
57d104c1 3787 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3788 * @hba: per-adapter instance
57d104c1 3789 * @status: bkops_status value
66ec6d59 3790 *
57d104c1
SJ
3791 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3792 * flag in the device to permit background operations if the device
3793 * bkops_status is greater than or equal to "status" argument passed to
3794 * this function, disable otherwise.
3795 *
3796 * Returns 0 for success, non-zero in case of failure.
3797 *
3798 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3799 * to know whether auto bkops is enabled or disabled after this function
3800 * returns control to it.
66ec6d59 3801 */
57d104c1
SJ
3802static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3803 enum bkops_status status)
66ec6d59
SRT
3804{
3805 int err;
57d104c1 3806 u32 curr_status = 0;
66ec6d59 3807
57d104c1 3808 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT
3809 if (err) {
3810 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3811 __func__, err);
3812 goto out;
57d104c1
SJ
3813 } else if (curr_status > BKOPS_STATUS_MAX) {
3814 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3815 __func__, curr_status);
3816 err = -EINVAL;
3817 goto out;
66ec6d59
SRT
3818 }
3819
57d104c1 3820 if (curr_status >= status)
66ec6d59 3821 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ
3822 else
3823 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT
3824out:
3825 return err;
3826}
3827
57d104c1
SJ
3828/**
3829 * ufshcd_urgent_bkops - handle urgent bkops exception event
3830 * @hba: per-adapter instance
3831 *
3832 * Enable fBackgroundOpsEn flag in the device to permit background
3833 * operations.
3834 *
3835 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3836 * and negative error value for any other failure.
3837 */
3838static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3839{
afdfff59 3840 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ
3841}
3842
66ec6d59
SRT
3843static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3844{
5e86ae44 3845 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT
3846 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3847}
3848
afdfff59
YG
3849static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
3850{
3851 int err;
3852 u32 curr_status = 0;
3853
3854 if (hba->is_urgent_bkops_lvl_checked)
3855 goto enable_auto_bkops;
3856
3857 err = ufshcd_get_bkops_status(hba, &curr_status);
3858 if (err) {
3859 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3860 __func__, err);
3861 goto out;
3862 }
3863
3864 /*
3865 * We are seeing that some devices are raising the urgent bkops
3866 * exception events even when BKOPS status doesn't indicate performace
3867 * impacted or critical. Handle these device by determining their urgent
3868 * bkops status at runtime.
3869 */
3870 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
3871 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
3872 __func__, curr_status);
3873 /* update the current status as the urgent bkops level */
3874 hba->urgent_bkops_lvl = curr_status;
3875 hba->is_urgent_bkops_lvl_checked = true;
3876 }
3877
3878enable_auto_bkops:
3879 err = ufshcd_enable_auto_bkops(hba);
3880out:
3881 if (err < 0)
3882 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3883 __func__, err);
3884}
3885
66ec6d59
SRT
3886/**
3887 * ufshcd_exception_event_handler - handle exceptions raised by device
3888 * @work: pointer to work data
3889 *
3890 * Read bExceptionEventStatus attribute from the device and handle the
3891 * exception event accordingly.
3892 */
3893static void ufshcd_exception_event_handler(struct work_struct *work)
3894{
3895 struct ufs_hba *hba;
3896 int err;
3897 u32 status = 0;
3898 hba = container_of(work, struct ufs_hba, eeh_work);
3899
62694735 3900 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT
3901 err = ufshcd_get_ee_status(hba, &status);
3902 if (err) {
3903 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3904 __func__, err);
3905 goto out;
3906 }
3907
3908 status &= hba->ee_ctrl_mask;
afdfff59
YG
3909
3910 if (status & MASK_EE_URGENT_BKOPS)
3911 ufshcd_bkops_exception_event_handler(hba);
3912
66ec6d59 3913out:
62694735 3914 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT
3915 return;
3916}
3917
9a47ec7c
YG
3918/* Complete requests that have door-bell cleared */
3919static void ufshcd_complete_requests(struct ufs_hba *hba)
3920{
3921 ufshcd_transfer_req_compl(hba);
3922 ufshcd_tmc_handler(hba);
3923}
3924
583fa62d
YG
3925/**
3926 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
3927 * to recover from the DL NAC errors or not.
3928 * @hba: per-adapter instance
3929 *
3930 * Returns true if error handling is required, false otherwise
3931 */
3932static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
3933{
3934 unsigned long flags;
3935 bool err_handling = true;
3936
3937 spin_lock_irqsave(hba->host->host_lock, flags);
3938 /*
3939 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
3940 * device fatal error and/or DL NAC & REPLAY timeout errors.
3941 */
3942 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
3943 goto out;
3944
3945 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
3946 ((hba->saved_err & UIC_ERROR) &&
3947 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
3948 goto out;
3949
3950 if ((hba->saved_err & UIC_ERROR) &&
3951 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
3952 int err;
3953 /*
3954 * wait for 50ms to see if we can get any other errors or not.
3955 */
3956 spin_unlock_irqrestore(hba->host->host_lock, flags);
3957 msleep(50);
3958 spin_lock_irqsave(hba->host->host_lock, flags);
3959
3960 /*
3961 * now check if we have got any other severe errors other than
3962 * DL NAC error?
3963 */
3964 if ((hba->saved_err & INT_FATAL_ERRORS) ||
3965 ((hba->saved_err & UIC_ERROR) &&
3966 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
3967 goto out;
3968
3969 /*
3970 * As DL NAC is the only error received so far, send out NOP
3971 * command to confirm if link is still active or not.
3972 * - If we don't get any response then do error recovery.
3973 * - If we get response then clear the DL NAC error bit.
3974 */
3975
3976 spin_unlock_irqrestore(hba->host->host_lock, flags);
3977 err = ufshcd_verify_dev_init(hba);
3978 spin_lock_irqsave(hba->host->host_lock, flags);
3979
3980 if (err)
3981 goto out;
3982
3983 /* Link seems to be alive hence ignore the DL NAC errors */
3984 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
3985 hba->saved_err &= ~UIC_ERROR;
3986 /* clear NAC error */
3987 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
3988 if (!hba->saved_uic_err) {
3989 err_handling = false;
3990 goto out;
3991 }
3992 }
3993out:
3994 spin_unlock_irqrestore(hba->host->host_lock, flags);
3995 return err_handling;
3996}
3997
7a3e97b0 3998/**
e8e7f271
SRT
3999 * ufshcd_err_handler - handle UFS errors that require s/w attention
4000 * @work: pointer to work structure
7a3e97b0 4001 */
e8e7f271 4002static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY
4003{
4004 struct ufs_hba *hba;
e8e7f271
SRT
4005 unsigned long flags;
4006 u32 err_xfer = 0;
4007 u32 err_tm = 0;
4008 int err = 0;
4009 int tag;
9a47ec7c 4010 bool needs_reset = false;
e8e7f271
SRT
4011
4012 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 4013
62694735 4014 pm_runtime_get_sync(hba->dev);
1ab27c9c 4015 ufshcd_hold(hba, false);
e8e7f271
SRT
4016
4017 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 4018 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 4019 goto out;
e8e7f271
SRT
4020
4021 hba->ufshcd_state = UFSHCD_STATE_RESET;
4022 ufshcd_set_eh_in_progress(hba);
4023
4024 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 4025 ufshcd_complete_requests(hba);
583fa62d
YG
4026
4027 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4028 bool ret;
4029
4030 spin_unlock_irqrestore(hba->host->host_lock, flags);
4031 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
4032 ret = ufshcd_quirk_dl_nac_errors(hba);
4033 spin_lock_irqsave(hba->host->host_lock, flags);
4034 if (!ret)
4035 goto skip_err_handling;
4036 }
9a47ec7c
YG
4037 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4038 ((hba->saved_err & UIC_ERROR) &&
4039 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4040 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4041 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4042 needs_reset = true;
e8e7f271 4043
9a47ec7c
YG
4044 /*
4045 * if host reset is required then skip clearing the pending
4046 * transfers forcefully because they will automatically get
4047 * cleared after link startup.
4048 */
4049 if (needs_reset)
4050 goto skip_pending_xfer_clear;
4051
4052 /* release lock as clear command might sleep */
4053 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4054 /* Clear pending transfer requests */
9a47ec7c
YG
4055 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4056 if (ufshcd_clear_cmd(hba, tag)) {
4057 err_xfer = true;
4058 goto lock_skip_pending_xfer_clear;
4059 }
4060 }
e8e7f271
SRT
4061
4062 /* Clear pending task management requests */
9a47ec7c
YG
4063 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4064 if (ufshcd_clear_tm_cmd(hba, tag)) {
4065 err_tm = true;
4066 goto lock_skip_pending_xfer_clear;
4067 }
4068 }
e8e7f271 4069
9a47ec7c 4070lock_skip_pending_xfer_clear:
e8e7f271 4071 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4072
9a47ec7c
YG
4073 /* Complete the requests that are cleared by s/w */
4074 ufshcd_complete_requests(hba);
4075
4076 if (err_xfer || err_tm)
4077 needs_reset = true;
4078
4079skip_pending_xfer_clear:
e8e7f271 4080 /* Fatal errors need reset */
9a47ec7c
YG
4081 if (needs_reset) {
4082 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4083
4084 /*
4085 * ufshcd_reset_and_restore() does the link reinitialization
4086 * which will need atleast one empty doorbell slot to send the
4087 * device management commands (NOP and query commands).
4088 * If there is no slot empty at this moment then free up last
4089 * slot forcefully.
4090 */
4091 if (hba->outstanding_reqs == max_doorbells)
4092 __ufshcd_transfer_req_compl(hba,
4093 (1UL << (hba->nutrs - 1)));
4094
4095 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4096 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4097 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT
4098 if (err) {
4099 dev_err(hba->dev, "%s: reset and restore failed\n",
4100 __func__);
4101 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4102 }
4103 /*
4104 * Inform scsi mid-layer that we did reset and allow to handle
4105 * Unit Attention properly.
4106 */
4107 scsi_report_bus_reset(hba->host, 0);
4108 hba->saved_err = 0;
4109 hba->saved_uic_err = 0;
4110 }
9a47ec7c 4111
583fa62d 4112skip_err_handling:
9a47ec7c
YG
4113 if (!needs_reset) {
4114 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4115 if (hba->saved_err || hba->saved_uic_err)
4116 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4117 __func__, hba->saved_err, hba->saved_uic_err);
4118 }
4119
e8e7f271
SRT
4120 ufshcd_clear_eh_in_progress(hba);
4121
4122out:
9a47ec7c 4123 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4124 scsi_unblock_requests(hba->host);
1ab27c9c 4125 ufshcd_release(hba);
62694735 4126 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY
4127}
4128
4129/**
e8e7f271
SRT
4130 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4131 * @hba: per-adapter instance
7a3e97b0 4132 */
e8e7f271 4133static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY
4134{
4135 u32 reg;
4136
e8e7f271
SRT
4137 /* PA_INIT_ERROR is fatal and needs UIC reset */
4138 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4139 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4140 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG
4141 else if (hba->dev_quirks &
4142 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4143 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4144 hba->uic_error |=
4145 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4146 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4147 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4148 }
e8e7f271
SRT
4149
4150 /* UIC NL/TL/DME errors needs software retry */
4151 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4152 if (reg)
4153 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4154
4155 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4156 if (reg)
4157 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4158
4159 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4160 if (reg)
4161 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4162
4163 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4164 __func__, hba->uic_error);
4165}
4166
4167/**
4168 * ufshcd_check_errors - Check for errors that need s/w attention
4169 * @hba: per-adapter instance
4170 */
4171static void ufshcd_check_errors(struct ufs_hba *hba)
4172{
4173 bool queue_eh_work = false;
4174
7a3e97b0 4175 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4176 queue_eh_work = true;
7a3e97b0
SY
4177
4178 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT
4179 hba->uic_error = 0;
4180 ufshcd_update_uic_error(hba);
4181 if (hba->uic_error)
4182 queue_eh_work = true;
7a3e97b0 4183 }
e8e7f271
SRT
4184
4185 if (queue_eh_work) {
9a47ec7c
YG
4186 /*
4187 * update the transfer error masks to sticky bits, let's do this
4188 * irrespective of current ufshcd_state.
4189 */
4190 hba->saved_err |= hba->errors;
4191 hba->saved_uic_err |= hba->uic_error;
4192
e8e7f271
SRT
4193 /* handle fatal errors only when link is functional */
4194 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4195 /* block commands from scsi mid-layer */
4196 scsi_block_requests(hba->host);
4197
e8e7f271
SRT
4198 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4199 schedule_work(&hba->eh_work);
4200 }
3441da7d 4201 }
e8e7f271
SRT
4202 /*
4203 * if (!queue_eh_work) -
4204 * Other errors are either non-fatal where host recovers
4205 * itself without s/w intervention or errors that will be
4206 * handled by the SCSI core layer.
4207 */
7a3e97b0
SY
4208}
4209
4210/**
4211 * ufshcd_tmc_handler - handle task management function completion
4212 * @hba: per adapter instance
4213 */
4214static void ufshcd_tmc_handler(struct ufs_hba *hba)
4215{
4216 u32 tm_doorbell;
4217
b873a275 4218 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4219 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4220 wake_up(&hba->tm_wq);
7a3e97b0
SY
4221}
4222
4223/**
4224 * ufshcd_sl_intr - Interrupt service routine
4225 * @hba: per adapter instance
4226 * @intr_status: contains interrupts generated by the controller
4227 */
4228static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4229{
4230 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4231 if (hba->errors)
e8e7f271 4232 ufshcd_check_errors(hba);
7a3e97b0 4233
53b3d9c3
SJ
4234 if (intr_status & UFSHCD_UIC_MASK)
4235 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY
4236
4237 if (intr_status & UTP_TASK_REQ_COMPL)
4238 ufshcd_tmc_handler(hba);
4239
4240 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4241 ufshcd_transfer_req_compl(hba);
4242}
4243
4244/**
4245 * ufshcd_intr - Main interrupt service routine
4246 * @irq: irq number
4247 * @__hba: pointer to adapter instance
4248 *
4249 * Returns IRQ_HANDLED - If interrupt is valid
4250 * IRQ_NONE - If invalid interrupt
4251 */
4252static irqreturn_t ufshcd_intr(int irq, void *__hba)
4253{
d75f7fe4 4254 u32 intr_status, enabled_intr_status;
7a3e97b0
SY
4255 irqreturn_t retval = IRQ_NONE;
4256 struct ufs_hba *hba = __hba;
4257
4258 spin_lock(hba->host->host_lock);
b873a275 4259 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG
4260 enabled_intr_status =
4261 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4262
d75f7fe4 4263 if (intr_status)
261ea452 4264 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG
4265
4266 if (enabled_intr_status) {
4267 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY
4268 retval = IRQ_HANDLED;
4269 }
4270 spin_unlock(hba->host->host_lock);
4271 return retval;
4272}
4273
e2933132
SRT
4274static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4275{
4276 int err = 0;
4277 u32 mask = 1 << tag;
4278 unsigned long flags;
4279
4280 if (!test_bit(tag, &hba->outstanding_tasks))
4281 goto out;
4282
4283 spin_lock_irqsave(hba->host->host_lock, flags);
4284 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4285 spin_unlock_irqrestore(hba->host->host_lock, flags);
4286
4287 /* poll for max. 1 sec to clear door bell register by h/w */
4288 err = ufshcd_wait_for_register(hba,
4289 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4290 mask, 0, 1000, 1000, true);
e2933132
SRT
4291out:
4292 return err;
4293}
4294
7a3e97b0
SY
4295/**
4296 * ufshcd_issue_tm_cmd - issues task management commands to controller
4297 * @hba: per adapter instance
e2933132
SRT
4298 * @lun_id: LUN ID to which TM command is sent
4299 * @task_id: task ID to which the TM command is applicable
4300 * @tm_function: task management function opcode
4301 * @tm_response: task management service response return value
7a3e97b0 4302 *
e2933132 4303 * Returns non-zero value on error, zero on success.
7a3e97b0 4304 */
e2933132
SRT
4305static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4306 u8 tm_function, u8 *tm_response)
7a3e97b0
SY
4307{
4308 struct utp_task_req_desc *task_req_descp;
4309 struct utp_upiu_task_req *task_req_upiup;
4310 struct Scsi_Host *host;
4311 unsigned long flags;
e2933132 4312 int free_slot;
7a3e97b0 4313 int err;
e2933132 4314 int task_tag;
7a3e97b0
SY
4315
4316 host = hba->host;
4317
e2933132
SRT
4318 /*
4319 * Get free slot, sleep if slots are unavailable.
4320 * Even though we use wait_event() which sleeps indefinitely,
4321 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4322 */
4323 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4324 ufshcd_hold(hba, false);
7a3e97b0 4325
e2933132 4326 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY
4327 task_req_descp = hba->utmrdl_base_addr;
4328 task_req_descp += free_slot;
4329
4330 /* Configure task request descriptor */
4331 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4332 task_req_descp->header.dword_2 =
4333 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4334
4335 /* Configure task request UPIU */
4336 task_req_upiup =
4337 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4338 task_tag = hba->nutrs + free_slot;
7a3e97b0 4339 task_req_upiup->header.dword_0 =
5a0b0cb9 4340 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4341 lun_id, task_tag);
7a3e97b0 4342 task_req_upiup->header.dword_1 =
5a0b0cb9 4343 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ
4344 /*
4345 * The host shall provide the same value for LUN field in the basic
4346 * header and for Input Parameter.
4347 */
e2933132
SRT
4348 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4349 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY
4350
4351 /* send command to the controller */
4352 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG
4353
4354 /* Make sure descriptors are ready before ringing the task doorbell */
4355 wmb();
4356
b873a275 4357 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB
4358 /* Make sure that doorbell is committed immediately */
4359 wmb();
7a3e97b0
SY
4360
4361 spin_unlock_irqrestore(host->host_lock, flags);
4362
4363 /* wait until the task management command is completed */
e2933132
SRT
4364 err = wait_event_timeout(hba->tm_wq,
4365 test_bit(free_slot, &hba->tm_condition),
4366 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4367 if (!err) {
e2933132
SRT
4368 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4369 __func__, tm_function);
4370 if (ufshcd_clear_tm_cmd(hba, free_slot))
4371 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4372 __func__, free_slot);
4373 err = -ETIMEDOUT;
4374 } else {
4375 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4376 }
e2933132 4377
7a3e97b0 4378 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT
4379 ufshcd_put_tm_slot(hba, free_slot);
4380 wake_up(&hba->tm_tag_wq);
4381
1ab27c9c 4382 ufshcd_release(hba);
7a3e97b0
SY
4383 return err;
4384}
4385
4386/**
3441da7d
SRT
4387 * ufshcd_eh_device_reset_handler - device reset handler registered to
4388 * scsi layer.
7a3e97b0
SY
4389 * @cmd: SCSI command pointer
4390 *
4391 * Returns SUCCESS/FAILED
4392 */
3441da7d 4393static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY
4394{
4395 struct Scsi_Host *host;
4396 struct ufs_hba *hba;
4397 unsigned int tag;
4398 u32 pos;
4399 int err;
e2933132
SRT
4400 u8 resp = 0xF;
4401 struct ufshcd_lrb *lrbp;
3441da7d 4402 unsigned long flags;
7a3e97b0
SY
4403
4404 host = cmd->device->host;
4405 hba = shost_priv(host);
4406 tag = cmd->request->tag;
4407
e2933132
SRT
4408 lrbp = &hba->lrb[tag];
4409 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4410 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT
4411 if (!err)
4412 err = resp;
7a3e97b0 4413 goto out;
e2933132 4414 }
7a3e97b0 4415
3441da7d
SRT
4416 /* clear the commands that were pending for corresponding LUN */
4417 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4418 if (hba->lrb[pos].lun == lrbp->lun) {
4419 err = ufshcd_clear_cmd(hba, pos);
4420 if (err)
4421 break;
7a3e97b0 4422 }
3441da7d
SRT
4423 }
4424 spin_lock_irqsave(host->host_lock, flags);
4425 ufshcd_transfer_req_compl(hba);
4426 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4427out:
3441da7d
SRT
4428 if (!err) {
4429 err = SUCCESS;
4430 } else {
4431 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4432 err = FAILED;
4433 }
7a3e97b0
SY
4434 return err;
4435}
4436
7a3e97b0
SY
4437/**
4438 * ufshcd_abort - abort a specific command
4439 * @cmd: SCSI command pointer
4440 *
f20810d8
SRT
4441 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4442 * command, and in host controller by clearing the door-bell register. There can
4443 * be race between controller sending the command to the device while abort is
4444 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4445 * really issued and then try to abort it.
4446 *
7a3e97b0
SY
4447 * Returns SUCCESS/FAILED
4448 */
4449static int ufshcd_abort(struct scsi_cmnd *cmd)
4450{
4451 struct Scsi_Host *host;
4452 struct ufs_hba *hba;
4453 unsigned long flags;
4454 unsigned int tag;
f20810d8
SRT
4455 int err = 0;
4456 int poll_cnt;
e2933132
SRT
4457 u8 resp = 0xF;
4458 struct ufshcd_lrb *lrbp;
e9d501b1 4459 u32 reg;
7a3e97b0
SY
4460
4461 host = cmd->device->host;
4462 hba = shost_priv(host);
4463 tag = cmd->request->tag;
14497328
YG
4464 if (!ufshcd_valid_tag(hba, tag)) {
4465 dev_err(hba->dev,
4466 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4467 __func__, tag, cmd, cmd->request);
4468 BUG();
4469 }
7a3e97b0 4470
1ab27c9c 4471 ufshcd_hold(hba, false);
14497328 4472 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4473 /* If command is already aborted/completed, return SUCCESS */
14497328
YG
4474 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4475 dev_err(hba->dev,
4476 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4477 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4478 goto out;
14497328 4479 }
7a3e97b0 4480
e9d501b1
DR
4481 if (!(reg & (1 << tag))) {
4482 dev_err(hba->dev,
4483 "%s: cmd was completed, but without a notifying intr, tag = %d",
4484 __func__, tag);
4485 }
4486
f20810d8
SRT
4487 lrbp = &hba->lrb[tag];
4488 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4489 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4490 UFS_QUERY_TASK, &resp);
4491 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4492 /* cmd pending in the device */
4493 break;
4494 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT
4495 /*
4496 * cmd not pending in the device, check if it is
4497 * in transition.
4498 */
4499 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4500 if (reg & (1 << tag)) {
4501 /* sleep for max. 200us to stabilize */
4502 usleep_range(100, 200);
4503 continue;
4504 }
4505 /* command completed already */
4506 goto out;
4507 } else {
4508 if (!err)
4509 err = resp; /* service response error */
4510 goto out;
4511 }
4512 }
4513
4514 if (!poll_cnt) {
4515 err = -EBUSY;
7a3e97b0
SY
4516 goto out;
4517 }
7a3e97b0 4518
e2933132
SRT
4519 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4520 UFS_ABORT_TASK, &resp);
4521 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT
4522 if (!err)
4523 err = resp; /* service response error */
7a3e97b0 4524 goto out;
e2933132 4525 }
7a3e97b0 4526
f20810d8
SRT
4527 err = ufshcd_clear_cmd(hba, tag);
4528 if (err)
4529 goto out;
4530
7a3e97b0
SY
4531 scsi_dma_unmap(cmd);
4532
4533 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4534 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY
4535 hba->lrb[tag].cmd = NULL;
4536 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT
4537
4538 clear_bit_unlock(tag, &hba->lrb_in_use);
4539 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4540
7a3e97b0 4541out:
f20810d8
SRT
4542 if (!err) {
4543 err = SUCCESS;
4544 } else {
4545 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4546 err = FAILED;
4547 }
4548
1ab27c9c
ST
4549 /*
4550 * This ufshcd_release() corresponds to the original scsi cmd that got
4551 * aborted here (as we won't get any IRQ for it).
4552 */
4553 ufshcd_release(hba);
7a3e97b0
SY
4554 return err;
4555}
4556
3441da7d
SRT
4557/**
4558 * ufshcd_host_reset_and_restore - reset and restore host controller
4559 * @hba: per-adapter instance
4560 *
4561 * Note that host controller reset may issue DME_RESET to
4562 * local and remote (device) Uni-Pro stack and the attributes
4563 * are reset to default state.
4564 *
4565 * Returns zero on success, non-zero on failure
4566 */
4567static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4568{
4569 int err;
3441da7d
SRT
4570 unsigned long flags;
4571
4572 /* Reset the host controller */
4573 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4574 ufshcd_hba_stop(hba, false);
3441da7d
SRT
4575 spin_unlock_irqrestore(hba->host->host_lock, flags);
4576
4577 err = ufshcd_hba_enable(hba);
4578 if (err)
4579 goto out;
4580
4581 /* Establish the link again and restore the device */
1d337ec2
SRT
4582 err = ufshcd_probe_hba(hba);
4583
4584 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT
4585 err = -EIO;
4586out:
4587 if (err)
4588 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4589
4590 return err;
4591}
4592
4593/**
4594 * ufshcd_reset_and_restore - reset and re-initialize host/device
4595 * @hba: per-adapter instance
4596 *
4597 * Reset and recover device, host and re-establish link. This
4598 * is helpful to recover the communication in fatal error conditions.
4599 *
4600 * Returns zero on success, non-zero on failure
4601 */
4602static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4603{
4604 int err = 0;
4605 unsigned long flags;
1d337ec2 4606 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4607
1d337ec2
SRT
4608 do {
4609 err = ufshcd_host_reset_and_restore(hba);
4610 } while (err && --retries);
3441da7d
SRT
4611
4612 /*
4613 * After reset the door-bell might be cleared, complete
4614 * outstanding requests in s/w here.
4615 */
4616 spin_lock_irqsave(hba->host->host_lock, flags);
4617 ufshcd_transfer_req_compl(hba);
4618 ufshcd_tmc_handler(hba);
4619 spin_unlock_irqrestore(hba->host->host_lock, flags);
4620
4621 return err;
4622}
4623
4624/**
4625 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4626 * @cmd - SCSI command pointer
4627 *
4628 * Returns SUCCESS/FAILED
4629 */
4630static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4631{
4632 int err;
4633 unsigned long flags;
4634 struct ufs_hba *hba;
4635
4636 hba = shost_priv(cmd->device->host);
4637
1ab27c9c 4638 ufshcd_hold(hba, false);
3441da7d
SRT
4639 /*
4640 * Check if there is any race with fatal error handling.
4641 * If so, wait for it to complete. Even though fatal error
4642 * handling does reset and restore in some cases, don't assume
4643 * anything out of it. We are just avoiding race here.
4644 */
4645 do {
4646 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4647 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT
4648 hba->ufshcd_state == UFSHCD_STATE_RESET))
4649 break;
4650 spin_unlock_irqrestore(hba->host->host_lock, flags);
4651 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4652 flush_work(&hba->eh_work);
3441da7d
SRT
4653 } while (1);
4654
4655 hba->ufshcd_state = UFSHCD_STATE_RESET;
4656 ufshcd_set_eh_in_progress(hba);
4657 spin_unlock_irqrestore(hba->host->host_lock, flags);
4658
4659 err = ufshcd_reset_and_restore(hba);
4660
4661 spin_lock_irqsave(hba->host->host_lock, flags);
4662 if (!err) {
4663 err = SUCCESS;
4664 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4665 } else {
4666 err = FAILED;
4667 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4668 }
4669 ufshcd_clear_eh_in_progress(hba);
4670 spin_unlock_irqrestore(hba->host->host_lock, flags);
4671
1ab27c9c 4672 ufshcd_release(hba);
3441da7d
SRT
4673 return err;
4674}
4675
3a4bf06d
YG
4676/**
4677 * ufshcd_get_max_icc_level - calculate the ICC level
4678 * @sup_curr_uA: max. current supported by the regulator
4679 * @start_scan: row at the desc table to start scan from
4680 * @buff: power descriptor buffer
4681 *
4682 * Returns calculated max ICC level for specific regulator
4683 */
4684static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4685{
4686 int i;
4687 int curr_uA;
4688 u16 data;
4689 u16 unit;
4690
4691 for (i = start_scan; i >= 0; i--) {
4692 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4693 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4694 ATTR_ICC_LVL_UNIT_OFFSET;
4695 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4696 switch (unit) {
4697 case UFSHCD_NANO_AMP:
4698 curr_uA = curr_uA / 1000;
4699 break;
4700 case UFSHCD_MILI_AMP:
4701 curr_uA = curr_uA * 1000;
4702 break;
4703 case UFSHCD_AMP:
4704 curr_uA = curr_uA * 1000 * 1000;
4705 break;
4706 case UFSHCD_MICRO_AMP:
4707 default:
4708 break;
4709 }
4710 if (sup_curr_uA >= curr_uA)
4711 break;
4712 }
4713 if (i < 0) {
4714 i = 0;
4715 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4716 }
4717
4718 return (u32)i;
4719}
4720
4721/**
4722 * ufshcd_calc_icc_level - calculate the max ICC level
4723 * In case regulators are not initialized we'll return 0
4724 * @hba: per-adapter instance
4725 * @desc_buf: power descriptor buffer to extract ICC levels from.
4726 * @len: length of desc_buff
4727 *
4728 * Returns calculated ICC level
4729 */
4730static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4731 u8 *desc_buf, int len)
4732{
4733 u32 icc_level = 0;
4734
4735 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4736 !hba->vreg_info.vccq2) {
4737 dev_err(hba->dev,
4738 "%s: Regulator capability was not set, actvIccLevel=%d",
4739 __func__, icc_level);
4740 goto out;
4741 }
4742
4743 if (hba->vreg_info.vcc)
4744 icc_level = ufshcd_get_max_icc_level(
4745 hba->vreg_info.vcc->max_uA,
4746 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4747 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4748
4749 if (hba->vreg_info.vccq)
4750 icc_level = ufshcd_get_max_icc_level(
4751 hba->vreg_info.vccq->max_uA,
4752 icc_level,
4753 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4754
4755 if (hba->vreg_info.vccq2)
4756 icc_level = ufshcd_get_max_icc_level(
4757 hba->vreg_info.vccq2->max_uA,
4758 icc_level,
4759 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4760out:
4761 return icc_level;
4762}
4763
4764static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4765{
4766 int ret;
4767 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4768 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4769
4770 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4771 if (ret) {
4772 dev_err(hba->dev,
4773 "%s: Failed reading power descriptor.len = %d ret = %d",
4774 __func__, buff_len, ret);
4775 return;
4776 }
4777
4778 hba->init_prefetch_data.icc_level =
4779 ufshcd_find_max_sup_active_icc_level(hba,
4780 desc_buf, buff_len);
4781 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4782 __func__, hba->init_prefetch_data.icc_level);
4783
5e86ae44
YG
4784 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4785 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4786 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG
4787
4788 if (ret)
4789 dev_err(hba->dev,
4790 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4791 __func__, hba->init_prefetch_data.icc_level , ret);
4792
4793}
4794
2a8fa600
SJ
4795/**
4796 * ufshcd_scsi_add_wlus - Adds required W-LUs
4797 * @hba: per-adapter instance
4798 *
4799 * UFS device specification requires the UFS devices to support 4 well known
4800 * logical units:
4801 * "REPORT_LUNS" (address: 01h)
4802 * "UFS Device" (address: 50h)
4803 * "RPMB" (address: 44h)
4804 * "BOOT" (address: 30h)
4805 * UFS device's power management needs to be controlled by "POWER CONDITION"
4806 * field of SSU (START STOP UNIT) command. But this "power condition" field
4807 * will take effect only when its sent to "UFS device" well known logical unit
4808 * hence we require the scsi_device instance to represent this logical unit in
4809 * order for the UFS host driver to send the SSU command for power management.
4810
4811 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4812 * Block) LU so user space process can control this LU. User space may also
4813 * want to have access to BOOT LU.
4814
4815 * This function adds scsi device instances for each of all well known LUs
4816 * (except "REPORT LUNS" LU).
4817 *
4818 * Returns zero on success (all required W-LUs are added successfully),
4819 * non-zero error value on failure (if failed to add any of the required W-LU).
4820 */
4821static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4822{
4823 int ret = 0;
7c48bfd0
AM
4824 struct scsi_device *sdev_rpmb;
4825 struct scsi_device *sdev_boot;
2a8fa600
SJ
4826
4827 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4828 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4829 if (IS_ERR(hba->sdev_ufs_device)) {
4830 ret = PTR_ERR(hba->sdev_ufs_device);
4831 hba->sdev_ufs_device = NULL;
4832 goto out;
4833 }
7c48bfd0 4834 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4835
7c48bfd0 4836 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4837 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM
4838 if (IS_ERR(sdev_boot)) {
4839 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ
4840 goto remove_sdev_ufs_device;
4841 }
7c48bfd0 4842 scsi_device_put(sdev_boot);
2a8fa600 4843
7c48bfd0 4844 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4845 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM
4846 if (IS_ERR(sdev_rpmb)) {
4847 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ
4848 goto remove_sdev_boot;
4849 }
7c48bfd0 4850 scsi_device_put(sdev_rpmb);
2a8fa600
SJ
4851 goto out;
4852
4853remove_sdev_boot:
7c48bfd0 4854 scsi_remove_device(sdev_boot);
2a8fa600
SJ
4855remove_sdev_ufs_device:
4856 scsi_remove_device(hba->sdev_ufs_device);
4857out:
4858 return ret;
4859}
4860
c58ab7aa
YG
4861static int ufs_get_device_info(struct ufs_hba *hba,
4862 struct ufs_device_info *card_data)
4863{
4864 int err;
4865 u8 model_index;
4866 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
4867 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
4868
4869 err = ufshcd_read_device_desc(hba, desc_buf,
4870 QUERY_DESC_DEVICE_MAX_SIZE);
4871 if (err) {
4872 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
4873 __func__, err);
4874 goto out;
4875 }
4876
4877 /*
4878 * getting vendor (manufacturerID) and Bank Index in big endian
4879 * format
4880 */
4881 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
4882 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
4883
4884 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4885
4886 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
4887 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
4888 if (err) {
4889 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
4890 __func__, err);
4891 goto out;
4892 }
4893
4894 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
4895 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
4896 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
4897 MAX_MODEL_LEN));
4898
4899 /* Null terminate the model string */
4900 card_data->model[MAX_MODEL_LEN] = '\0';
4901
4902out:
4903 return err;
4904}
4905
4906void ufs_advertise_fixup_device(struct ufs_hba *hba)
4907{
4908 int err;
4909 struct ufs_dev_fix *f;
4910 struct ufs_device_info card_data;
4911
4912 card_data.wmanufacturerid = 0;
4913
4914 err = ufs_get_device_info(hba, &card_data);
4915 if (err) {
4916 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
4917 __func__, err);
4918 return;
4919 }
4920
4921 for (f = ufs_fixups; f->quirk; f++) {
4922 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
4923 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
4924 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
4925 !strcmp(f->card.model, UFS_ANY_MODEL)))
4926 hba->dev_quirks |= f->quirk;
4927 }
4928}
4929
37113106
YG
4930/**
4931 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
4932 * @hba: per-adapter instance
4933 *
4934 * PA_TActivate parameter can be tuned manually if UniPro version is less than
4935 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
4936 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
4937 * the hibern8 exit latency.
4938 *
4939 * Returns zero on success, non-zero error value on failure.
4940 */
4941static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
4942{
4943 int ret = 0;
4944 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
4945
4946 ret = ufshcd_dme_peer_get(hba,
4947 UIC_ARG_MIB_SEL(
4948 RX_MIN_ACTIVATETIME_CAPABILITY,
4949 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
4950 &peer_rx_min_activatetime);
4951 if (ret)
4952 goto out;
4953
4954 /* make sure proper unit conversion is applied */
4955 tuned_pa_tactivate =
4956 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
4957 / PA_TACTIVATE_TIME_UNIT_US);
4958 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
4959 tuned_pa_tactivate);
4960
4961out:
4962 return ret;
4963}
4964
4965/**
4966 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
4967 * @hba: per-adapter instance
4968 *
4969 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
4970 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
4971 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
4972 * This optimal value can help reduce the hibern8 exit latency.
4973 *
4974 * Returns zero on success, non-zero error value on failure.
4975 */
4976static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
4977{
4978 int ret = 0;
4979 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
4980 u32 max_hibern8_time, tuned_pa_hibern8time;
4981
4982 ret = ufshcd_dme_get(hba,
4983 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
4984 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
4985 &local_tx_hibern8_time_cap);
4986 if (ret)
4987 goto out;
4988
4989 ret = ufshcd_dme_peer_get(hba,
4990 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
4991 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
4992 &peer_rx_hibern8_time_cap);
4993 if (ret)
4994 goto out;
4995
4996 max_hibern8_time = max(local_tx_hibern8_time_cap,
4997 peer_rx_hibern8_time_cap);
4998 /* make sure proper unit conversion is applied */
4999 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
5000 / PA_HIBERN8_TIME_UNIT_US);
5001 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
5002 tuned_pa_hibern8time);
5003out:
5004 return ret;
5005}
5006
5007static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
5008{
5009 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
5010 ufshcd_tune_pa_tactivate(hba);
5011 ufshcd_tune_pa_hibern8time(hba);
5012 }
5013
5014 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
5015 /* set 1ms timeout for PA_TACTIVATE */
5016 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
5017}
5018
6ccf44fe 5019/**
1d337ec2
SRT
5020 * ufshcd_probe_hba - probe hba to detect device and initialize
5021 * @hba: per-adapter instance
5022 *
5023 * Execute link-startup and verify device initialization
6ccf44fe 5024 */
1d337ec2 5025static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 5026{
6ccf44fe
SJ
5027 int ret;
5028
5029 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT
5030 if (ret)
5031 goto out;
5032
5064636c
YG
5033 ufshcd_init_pwr_info(hba);
5034
afdfff59
YG
5035 /* set the default level for urgent bkops */
5036 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5037 hba->is_urgent_bkops_lvl_checked = false;
5038
57d104c1
SJ
5039 /* UniPro link is active now */
5040 ufshcd_set_link_active(hba);
d3e89bac 5041
5a0b0cb9
SRT
5042 ret = ufshcd_verify_dev_init(hba);
5043 if (ret)
5044 goto out;
68078d5c
DR
5045
5046 ret = ufshcd_complete_dev_init(hba);
5047 if (ret)
5048 goto out;
5a0b0cb9 5049
c58ab7aa 5050 ufs_advertise_fixup_device(hba);
37113106 5051 ufshcd_tune_unipro_params(hba);
60f01870
YG
5052
5053 ret = ufshcd_set_vccq_rail_unused(hba,
5054 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5055 if (ret)
5056 goto out;
5057
57d104c1
SJ
5058 /* UFS device is also active now */
5059 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5060 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ
5061 hba->wlun_dev_clr_ua = true;
5062
7eb584db
DR
5063 if (ufshcd_get_max_pwr_mode(hba)) {
5064 dev_err(hba->dev,
5065 "%s: Failed getting max supported power mode\n",
5066 __func__);
5067 } else {
5068 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 5069 if (ret) {
7eb584db
DR
5070 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5071 __func__, ret);
8643ae66
DL
5072 goto out;
5073 }
7eb584db 5074 }
57d104c1 5075
53c12d0e
YG
5076 /* set the state as operational after switching to desired gear */
5077 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ
5078 /*
5079 * If we are in error handling context or in power management callbacks
5080 * context, no need to scan the host
5081 */
5082 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5083 bool flag;
5084
5085 /* clear any previous UFS device information */
5086 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG
5087 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5088 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5089 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5090
3a4bf06d
YG
5091 if (!hba->is_init_prefetch)
5092 ufshcd_init_icc_levels(hba);
5093
2a8fa600
SJ
5094 /* Add required well known logical units to scsi mid layer */
5095 if (ufshcd_scsi_add_wlus(hba))
5096 goto out;
5097
3441da7d
SRT
5098 scsi_scan_host(hba->host);
5099 pm_runtime_put_sync(hba->dev);
5100 }
3a4bf06d
YG
5101
5102 if (!hba->is_init_prefetch)
5103 hba->is_init_prefetch = true;
5104
856b3483 5105 /* Resume devfreq after UFS device is detected */
a508253d 5106 ufshcd_resume_clkscaling(hba);
856b3483 5107
5a0b0cb9 5108out:
1d337ec2
SRT
5109 /*
5110 * If we failed to initialize the device or the device is not
5111 * present, turn off the power/clocks etc.
5112 */
57d104c1
SJ
5113 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5114 pm_runtime_put_sync(hba->dev);
1d337ec2 5115 ufshcd_hba_exit(hba);
57d104c1 5116 }
1d337ec2
SRT
5117
5118 return ret;
5119}
5120
5121/**
5122 * ufshcd_async_scan - asynchronous execution for probing hba
5123 * @data: data pointer to pass to this function
5124 * @cookie: cookie data
5125 */
5126static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5127{
5128 struct ufs_hba *hba = (struct ufs_hba *)data;
5129
5130 ufshcd_probe_hba(hba);
6ccf44fe
SJ
5131}
5132
f550c65b
YG
5133static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5134{
5135 unsigned long flags;
5136 struct Scsi_Host *host;
5137 struct ufs_hba *hba;
5138 int index;
5139 bool found = false;
5140
5141 if (!scmd || !scmd->device || !scmd->device->host)
5142 return BLK_EH_NOT_HANDLED;
5143
5144 host = scmd->device->host;
5145 hba = shost_priv(host);
5146 if (!hba)
5147 return BLK_EH_NOT_HANDLED;
5148
5149 spin_lock_irqsave(host->host_lock, flags);
5150
5151 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5152 if (hba->lrb[index].cmd == scmd) {
5153 found = true;
5154 break;
5155 }
5156 }
5157
5158 spin_unlock_irqrestore(host->host_lock, flags);
5159
5160 /*
5161 * Bypass SCSI error handling and reset the block layer timer if this
5162 * SCSI command was not actually dispatched to UFS driver, otherwise
5163 * let SCSI layer handle the error as usual.
5164 */
5165 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5166}
5167
7a3e97b0
SY
5168static struct scsi_host_template ufshcd_driver_template = {
5169 .module = THIS_MODULE,
5170 .name = UFSHCD,
5171 .proc_name = UFSHCD,
5172 .queuecommand = ufshcd_queuecommand,
5173 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5174 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5175 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5176 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5177 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT
5178 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5179 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5180 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY
5181 .this_id = -1,
5182 .sg_tablesize = SG_ALL,
5183 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5184 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5185 .max_host_blocked = 1,
c40ecc12 5186 .track_queue_depth = 1,
7a3e97b0
SY
5187};
5188
57d104c1
SJ
5189static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5190 int ua)
5191{
7b16a07c 5192 int ret;
57d104c1 5193
7b16a07c
BA
5194 if (!vreg)
5195 return 0;
57d104c1 5196
7b16a07c
BA
5197 ret = regulator_set_load(vreg->reg, ua);
5198 if (ret < 0) {
5199 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5200 __func__, vreg->name, ua, ret);
57d104c1
SJ
5201 }
5202
5203 return ret;
5204}
5205
5206static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5207 struct ufs_vreg *vreg)
5208{
60f01870
YG
5209 if (!vreg)
5210 return 0;
5211 else if (vreg->unused)
5212 return 0;
5213 else
5214 return ufshcd_config_vreg_load(hba->dev, vreg,
5215 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ
5216}
5217
5218static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5219 struct ufs_vreg *vreg)
5220{
60f01870
YG
5221 if (!vreg)
5222 return 0;
5223 else if (vreg->unused)
5224 return 0;
5225 else
5226 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ
5227}
5228
aa497613
SRT
5229static int ufshcd_config_vreg(struct device *dev,
5230 struct ufs_vreg *vreg, bool on)
5231{
5232 int ret = 0;
5233 struct regulator *reg = vreg->reg;
5234 const char *name = vreg->name;
5235 int min_uV, uA_load;
5236
5237 BUG_ON(!vreg);
5238
5239 if (regulator_count_voltages(reg) > 0) {
5240 min_uV = on ? vreg->min_uV : 0;
5241 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5242 if (ret) {
5243 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5244 __func__, name, ret);
5245 goto out;
5246 }
5247
5248 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ
5249 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5250 if (ret)
aa497613 5251 goto out;
aa497613
SRT
5252 }
5253out:
5254 return ret;
5255}
5256
5257static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5258{
5259 int ret = 0;
5260
60f01870
YG
5261 if (!vreg)
5262 goto out;
5263 else if (vreg->enabled || vreg->unused)
aa497613
SRT
5264 goto out;
5265
5266 ret = ufshcd_config_vreg(dev, vreg, true);
5267 if (!ret)
5268 ret = regulator_enable(vreg->reg);
5269
5270 if (!ret)
5271 vreg->enabled = true;
5272 else
5273 dev_err(dev, "%s: %s enable failed, err=%d\n",
5274 __func__, vreg->name, ret);
5275out:
5276 return ret;
5277}
5278
5279static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5280{
5281 int ret = 0;
5282
60f01870
YG
5283 if (!vreg)
5284 goto out;
5285 else if (!vreg->enabled || vreg->unused)
aa497613
SRT
5286 goto out;
5287
5288 ret = regulator_disable(vreg->reg);
5289
5290 if (!ret) {
5291 /* ignore errors on applying disable config */
5292 ufshcd_config_vreg(dev, vreg, false);
5293 vreg->enabled = false;
5294 } else {
5295 dev_err(dev, "%s: %s disable failed, err=%d\n",
5296 __func__, vreg->name, ret);
5297 }
5298out:
5299 return ret;
5300}
5301
5302static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5303{
5304 int ret = 0;
5305 struct device *dev = hba->dev;
5306 struct ufs_vreg_info *info = &hba->vreg_info;
5307
5308 if (!info)
5309 goto out;
5310
5311 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5312 if (ret)
5313 goto out;
5314
5315 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5316 if (ret)
5317 goto out;
5318
5319 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5320 if (ret)
5321 goto out;
5322
5323out:
5324 if (ret) {
5325 ufshcd_toggle_vreg(dev, info->vccq2, false);
5326 ufshcd_toggle_vreg(dev, info->vccq, false);
5327 ufshcd_toggle_vreg(dev, info->vcc, false);
5328 }
5329 return ret;
5330}
5331
6a771a65
RS
5332static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5333{
5334 struct ufs_vreg_info *info = &hba->vreg_info;
5335
5336 if (info)
5337 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5338
5339 return 0;
5340}
5341
aa497613
SRT
5342static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5343{
5344 int ret = 0;
5345
5346 if (!vreg)
5347 goto out;
5348
5349 vreg->reg = devm_regulator_get(dev, vreg->name);
5350 if (IS_ERR(vreg->reg)) {
5351 ret = PTR_ERR(vreg->reg);
5352 dev_err(dev, "%s: %s get failed, err=%d\n",
5353 __func__, vreg->name, ret);
5354 }
5355out:
5356 return ret;
5357}
5358
5359static int ufshcd_init_vreg(struct ufs_hba *hba)
5360{
5361 int ret = 0;
5362 struct device *dev = hba->dev;
5363 struct ufs_vreg_info *info = &hba->vreg_info;
5364
5365 if (!info)
5366 goto out;
5367
5368 ret = ufshcd_get_vreg(dev, info->vcc);
5369 if (ret)
5370 goto out;
5371
5372 ret = ufshcd_get_vreg(dev, info->vccq);
5373 if (ret)
5374 goto out;
5375
5376 ret = ufshcd_get_vreg(dev, info->vccq2);
5377out:
5378 return ret;
5379}
5380
6a771a65
RS
5381static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5382{
5383 struct ufs_vreg_info *info = &hba->vreg_info;
5384
5385 if (info)
5386 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5387
5388 return 0;
5389}
5390
60f01870
YG
5391static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5392{
5393 int ret = 0;
5394 struct ufs_vreg_info *info = &hba->vreg_info;
5395
5396 if (!info)
5397 goto out;
5398 else if (!info->vccq)
5399 goto out;
5400
5401 if (unused) {
5402 /* shut off the rail here */
5403 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5404 /*
5405 * Mark this rail as no longer used, so it doesn't get enabled
5406 * later by mistake
5407 */
5408 if (!ret)
5409 info->vccq->unused = true;
5410 } else {
5411 /*
5412 * rail should have been already enabled hence just make sure
5413 * that unused flag is cleared.
5414 */
5415 info->vccq->unused = false;
5416 }
5417out:
5418 return ret;
5419}
5420
57d104c1
SJ
5421static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5422 bool skip_ref_clk)
c6e79dac
SRT
5423{
5424 int ret = 0;
5425 struct ufs_clk_info *clki;
5426 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5427 unsigned long flags;
c6e79dac
SRT
5428
5429 if (!head || list_empty(head))
5430 goto out;
5431
1e879e8f
SJ
5432 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
5433 if (ret)
5434 return ret;
5435
c6e79dac
SRT
5436 list_for_each_entry(clki, head, list) {
5437 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ
5438 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5439 continue;
5440
c6e79dac
SRT
5441 if (on && !clki->enabled) {
5442 ret = clk_prepare_enable(clki->clk);
5443 if (ret) {
5444 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5445 __func__, clki->name, ret);
5446 goto out;
5447 }
5448 } else if (!on && clki->enabled) {
5449 clk_disable_unprepare(clki->clk);
5450 }
5451 clki->enabled = on;
5452 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5453 clki->name, on ? "en" : "dis");
5454 }
5455 }
1ab27c9c 5456
1e879e8f
SJ
5457 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
5458 if (ret)
5459 return ret;
5460
c6e79dac
SRT
5461out:
5462 if (ret) {
5463 list_for_each_entry(clki, head, list) {
5464 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5465 clk_disable_unprepare(clki->clk);
5466 }
eda910e4 5467 } else if (on) {
1ab27c9c
ST
5468 spin_lock_irqsave(hba->host->host_lock, flags);
5469 hba->clk_gating.state = CLKS_ON;
5470 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT
5471 }
5472 return ret;
5473}
5474
57d104c1
SJ
5475static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
5476{
5477 return __ufshcd_setup_clocks(hba, on, false);
5478}
5479
c6e79dac
SRT
5480static int ufshcd_init_clocks(struct ufs_hba *hba)
5481{
5482 int ret = 0;
5483 struct ufs_clk_info *clki;
5484 struct device *dev = hba->dev;
5485 struct list_head *head = &hba->clk_list_head;
5486
5487 if (!head || list_empty(head))
5488 goto out;
5489
5490 list_for_each_entry(clki, head, list) {
5491 if (!clki->name)
5492 continue;
5493
5494 clki->clk = devm_clk_get(dev, clki->name);
5495 if (IS_ERR(clki->clk)) {
5496 ret = PTR_ERR(clki->clk);
5497 dev_err(dev, "%s: %s clk get failed, %d\n",
5498 __func__, clki->name, ret);
5499 goto out;
5500 }
5501
5502 if (clki->max_freq) {
5503 ret = clk_set_rate(clki->clk, clki->max_freq);
5504 if (ret) {
5505 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5506 __func__, clki->name,
5507 clki->max_freq, ret);
5508 goto out;
5509 }
856b3483 5510 clki->curr_freq = clki->max_freq;
c6e79dac
SRT
5511 }
5512 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
5513 clki->name, clk_get_rate(clki->clk));
5514 }
5515out:
5516 return ret;
5517}
5518
5c0c28a8
SRT
5519static int ufshcd_variant_hba_init(struct ufs_hba *hba)
5520{
5521 int err = 0;
5522
5523 if (!hba->vops)
5524 goto out;
5525
0263bcd0
YG
5526 err = ufshcd_vops_init(hba);
5527 if (err)
5528 goto out;
5c0c28a8 5529
0263bcd0
YG
5530 err = ufshcd_vops_setup_regulators(hba, true);
5531 if (err)
5532 goto out_exit;
5c0c28a8
SRT
5533
5534 goto out;
5535
5c0c28a8 5536out_exit:
0263bcd0 5537 ufshcd_vops_exit(hba);
5c0c28a8
SRT
5538out:
5539 if (err)
5540 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 5541 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT
5542 return err;
5543}
5544
5545static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
5546{
5547 if (!hba->vops)
5548 return;
5549
0263bcd0 5550 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 5551
0263bcd0 5552 ufshcd_vops_exit(hba);
5c0c28a8
SRT
5553}
5554
aa497613
SRT
5555static int ufshcd_hba_init(struct ufs_hba *hba)
5556{
5557 int err;
5558
6a771a65
RS
5559 /*
5560 * Handle host controller power separately from the UFS device power
5561 * rails as it will help controlling the UFS host controller power
5562 * collapse easily which is different than UFS device power collapse.
5563 * Also, enable the host controller power before we go ahead with rest
5564 * of the initialization here.
5565 */
5566 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT
5567 if (err)
5568 goto out;
5569
6a771a65 5570 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT
5571 if (err)
5572 goto out;
5573
6a771a65
RS
5574 err = ufshcd_init_clocks(hba);
5575 if (err)
5576 goto out_disable_hba_vreg;
5577
5578 err = ufshcd_setup_clocks(hba, true);
5579 if (err)
5580 goto out_disable_hba_vreg;
5581
c6e79dac
SRT
5582 err = ufshcd_init_vreg(hba);
5583 if (err)
5584 goto out_disable_clks;
5585
5586 err = ufshcd_setup_vreg(hba, true);
5587 if (err)
5588 goto out_disable_clks;
5589
aa497613
SRT
5590 err = ufshcd_variant_hba_init(hba);
5591 if (err)
5592 goto out_disable_vreg;
5593
1d337ec2 5594 hba->is_powered = true;
aa497613
SRT
5595 goto out;
5596
5597out_disable_vreg:
5598 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT
5599out_disable_clks:
5600 ufshcd_setup_clocks(hba, false);
6a771a65
RS
5601out_disable_hba_vreg:
5602 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT
5603out:
5604 return err;
5605}
5606
5607static void ufshcd_hba_exit(struct ufs_hba *hba)
5608{
1d337ec2
SRT
5609 if (hba->is_powered) {
5610 ufshcd_variant_hba_exit(hba);
5611 ufshcd_setup_vreg(hba, false);
a508253d 5612 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT
5613 ufshcd_setup_clocks(hba, false);
5614 ufshcd_setup_hba_vreg(hba, false);
5615 hba->is_powered = false;
5616 }
aa497613
SRT
5617}
5618
57d104c1
SJ
5619static int
5620ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
5621{
5622 unsigned char cmd[6] = {REQUEST_SENSE,
5623 0,
5624 0,
5625 0,
dcea0bfb 5626 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ
5627 0};
5628 char *buffer;
5629 int ret;
5630
dcea0bfb 5631 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ
5632 if (!buffer) {
5633 ret = -ENOMEM;
5634 goto out;
5635 }
5636
5637 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 5638 UFSHCD_REQ_SENSE_SIZE, NULL,
57d104c1
SJ
5639 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
5640 if (ret)
5641 pr_err("%s: failed with err %d\n", __func__, ret);
5642
5643 kfree(buffer);
5644out:
5645 return ret;
5646}
5647
5648/**
5649 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
5650 * power mode
5651 * @hba: per adapter instance
5652 * @pwr_mode: device power mode to set
5653 *
5654 * Returns 0 if requested power mode is set successfully
5655 * Returns non-zero if failed to set the requested power mode
5656 */
5657static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
5658 enum ufs_dev_pwr_mode pwr_mode)
5659{
5660 unsigned char cmd[6] = { START_STOP };
5661 struct scsi_sense_hdr sshdr;
7c48bfd0
AM
5662 struct scsi_device *sdp;
5663 unsigned long flags;
57d104c1
SJ
5664 int ret;
5665
7c48bfd0
AM
5666 spin_lock_irqsave(hba->host->host_lock, flags);
5667 sdp = hba->sdev_ufs_device;
5668 if (sdp) {
5669 ret = scsi_device_get(sdp);
5670 if (!ret && !scsi_device_online(sdp)) {
5671 ret = -ENODEV;
5672 scsi_device_put(sdp);
5673 }
5674 } else {
5675 ret = -ENODEV;
5676 }
5677 spin_unlock_irqrestore(hba->host->host_lock, flags);
5678
5679 if (ret)
5680 return ret;
57d104c1
SJ
5681
5682 /*
5683 * If scsi commands fail, the scsi mid-layer schedules scsi error-
5684 * handling, which would wait for host to be resumed. Since we know
5685 * we are functional while we are here, skip host resume in error
5686 * handling context.
5687 */
5688 hba->host->eh_noresume = 1;
5689 if (hba->wlun_dev_clr_ua) {
5690 ret = ufshcd_send_request_sense(hba, sdp);
5691 if (ret)
5692 goto out;
5693 /* Unit attention condition is cleared now */
5694 hba->wlun_dev_clr_ua = false;
5695 }
5696
5697 cmd[4] = pwr_mode << 4;
5698
5699 /*
5700 * Current function would be generally called from the power management
5701 * callbacks hence set the REQ_PM flag so that it doesn't resume the
5702 * already suspended childs.
5703 */
5704 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
5705 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
5706 if (ret) {
5707 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR
5708 "START_STOP failed for power mode: %d, result %x\n",
5709 pwr_mode, ret);
21045519
HR
5710 if (driver_byte(ret) & DRIVER_SENSE)
5711 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ
5712 }
5713
5714 if (!ret)
5715 hba->curr_dev_pwr_mode = pwr_mode;
5716out:
7c48bfd0 5717 scsi_device_put(sdp);
57d104c1
SJ
5718 hba->host->eh_noresume = 0;
5719 return ret;
5720}
5721
5722static int ufshcd_link_state_transition(struct ufs_hba *hba,
5723 enum uic_link_state req_link_state,
5724 int check_for_bkops)
5725{
5726 int ret = 0;
5727
5728 if (req_link_state == hba->uic_link_state)
5729 return 0;
5730
5731 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5732 ret = ufshcd_uic_hibern8_enter(hba);
5733 if (!ret)
5734 ufshcd_set_link_hibern8(hba);
5735 else
5736 goto out;
5737 }
5738 /*
5739 * If autobkops is enabled, link can't be turned off because
5740 * turning off the link would also turn off the device.
5741 */
5742 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
5743 (!check_for_bkops || (check_for_bkops &&
5744 !hba->auto_bkops_enabled))) {
f3099fbd
YG
5745 /*
5746 * Let's make sure that link is in low power mode, we are doing
5747 * this currently by putting the link in Hibern8. Otherway to
5748 * put the link in low power mode is to send the DME end point
5749 * to device and then send the DME reset command to local
5750 * unipro. But putting the link in hibern8 is much faster.
5751 */
5752 ret = ufshcd_uic_hibern8_enter(hba);
5753 if (ret)
5754 goto out;
57d104c1
SJ
5755 /*
5756 * Change controller state to "reset state" which
5757 * should also put the link in off/reset state
5758 */
596585a2 5759 ufshcd_hba_stop(hba, true);
57d104c1
SJ
5760 /*
5761 * TODO: Check if we need any delay to make sure that
5762 * controller is reset
5763 */
5764 ufshcd_set_link_off(hba);
5765 }
5766
5767out:
5768 return ret;
5769}
5770
5771static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
5772{
b799fdf7
YG
5773 /*
5774 * It seems some UFS devices may keep drawing more than sleep current
5775 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
5776 * To avoid this situation, add 2ms delay before putting these UFS
5777 * rails in LPM mode.
5778 */
5779 if (!ufshcd_is_link_active(hba) &&
5780 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
5781 usleep_range(2000, 2100);
5782
57d104c1
SJ
5783 /*
5784 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
5785 * power.
5786 *
5787 * If UFS device and link is in OFF state, all power supplies (VCC,
5788 * VCCQ, VCCQ2) can be turned off if power on write protect is not
5789 * required. If UFS link is inactive (Hibern8 or OFF state) and device
5790 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
5791 *
5792 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
5793 * in low power state which would save some power.
5794 */
5795 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5796 !hba->dev_info.is_lu_power_on_wp) {
5797 ufshcd_setup_vreg(hba, false);
5798 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5799 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5800 if (!ufshcd_is_link_active(hba)) {
5801 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5802 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
5803 }
5804 }
5805}
5806
5807static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
5808{
5809 int ret = 0;
5810
5811 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5812 !hba->dev_info.is_lu_power_on_wp) {
5813 ret = ufshcd_setup_vreg(hba, true);
5814 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5815 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
5816 if (!ret && !ufshcd_is_link_active(hba)) {
5817 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5818 if (ret)
5819 goto vcc_disable;
5820 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5821 if (ret)
5822 goto vccq_lpm;
5823 }
5824 }
5825 goto out;
5826
5827vccq_lpm:
5828 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5829vcc_disable:
5830 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5831out:
5832 return ret;
5833}
5834
5835static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
5836{
5837 if (ufshcd_is_link_off(hba))
5838 ufshcd_setup_hba_vreg(hba, false);
5839}
5840
5841static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
5842{
5843 if (ufshcd_is_link_off(hba))
5844 ufshcd_setup_hba_vreg(hba, true);
5845}
5846
7a3e97b0 5847/**
57d104c1 5848 * ufshcd_suspend - helper function for suspend operations
3b1d0580 5849 * @hba: per adapter instance
57d104c1
SJ
5850 * @pm_op: desired low power operation type
5851 *
5852 * This function will try to put the UFS device and link into low power
5853 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
5854 * (System PM level).
5855 *
5856 * If this function is called during shutdown, it will make sure that
5857 * both UFS device and UFS link is powered off.
7a3e97b0 5858 *
57d104c1
SJ
5859 * NOTE: UFS device & link must be active before we enter in this function.
5860 *
5861 * Returns 0 for success and non-zero for failure
7a3e97b0 5862 */
57d104c1 5863static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5864{
57d104c1
SJ
5865 int ret = 0;
5866 enum ufs_pm_level pm_lvl;
5867 enum ufs_dev_pwr_mode req_dev_pwr_mode;
5868 enum uic_link_state req_link_state;
5869
5870 hba->pm_op_in_progress = 1;
5871 if (!ufshcd_is_shutdown_pm(pm_op)) {
5872 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
5873 hba->rpm_lvl : hba->spm_lvl;
5874 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
5875 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
5876 } else {
5877 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
5878 req_link_state = UIC_LINK_OFF_STATE;
5879 }
5880
7a3e97b0 5881 /*
57d104c1
SJ
5882 * If we can't transition into any of the low power modes
5883 * just gate the clocks.
7a3e97b0 5884 */
1ab27c9c
ST
5885 ufshcd_hold(hba, false);
5886 hba->clk_gating.is_suspended = true;
5887
57d104c1
SJ
5888 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
5889 req_link_state == UIC_LINK_ACTIVE_STATE) {
5890 goto disable_clks;
5891 }
7a3e97b0 5892
57d104c1
SJ
5893 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
5894 (req_link_state == hba->uic_link_state))
5895 goto out;
5896
5897 /* UFS device & link must be active before we enter in this function */
5898 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
5899 ret = -EINVAL;
5900 goto out;
5901 }
5902
5903 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ
5904 if (ufshcd_can_autobkops_during_suspend(hba)) {
5905 /*
5906 * The device is idle with no requests in the queue,
5907 * allow background operations if bkops status shows
5908 * that performance might be impacted.
5909 */
5910 ret = ufshcd_urgent_bkops(hba);
5911 if (ret)
5912 goto enable_gating;
5913 } else {
5914 /* make sure that auto bkops is disabled */
5915 ufshcd_disable_auto_bkops(hba);
5916 }
57d104c1
SJ
5917 }
5918
5919 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
5920 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
5921 !ufshcd_is_runtime_pm(pm_op))) {
5922 /* ensure that bkops is disabled */
5923 ufshcd_disable_auto_bkops(hba);
5924 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
5925 if (ret)
1ab27c9c 5926 goto enable_gating;
57d104c1
SJ
5927 }
5928
5929 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
5930 if (ret)
5931 goto set_dev_active;
5932
5933 ufshcd_vreg_set_lpm(hba);
5934
5935disable_clks:
856b3483
ST
5936 /*
5937 * The clock scaling needs access to controller registers. Hence, Wait
5938 * for pending clock scaling work to be done before clocks are
5939 * turned off.
5940 */
a508253d
GB
5941 ufshcd_suspend_clkscaling(hba);
5942
57d104c1
SJ
5943 /*
5944 * Call vendor specific suspend callback. As these callbacks may access
5945 * vendor specific host controller register space call them before the
5946 * host clocks are ON.
5947 */
0263bcd0
YG
5948 ret = ufshcd_vops_suspend(hba, pm_op);
5949 if (ret)
5950 goto set_link_active;
57d104c1 5951
57d104c1
SJ
5952 if (!ufshcd_is_link_active(hba))
5953 ufshcd_setup_clocks(hba, false);
5954 else
5955 /* If link is active, device ref_clk can't be switched off */
5956 __ufshcd_setup_clocks(hba, false, true);
5957
1ab27c9c 5958 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ
5959 /*
5960 * Disable the host irq as host controller as there won't be any
0263bcd0 5961 * host controller transaction expected till resume.
57d104c1
SJ
5962 */
5963 ufshcd_disable_irq(hba);
5964 /* Put the host controller in low power mode if possible */
5965 ufshcd_hba_vreg_set_lpm(hba);
5966 goto out;
5967
57d104c1 5968set_link_active:
a508253d 5969 ufshcd_resume_clkscaling(hba);
57d104c1
SJ
5970 ufshcd_vreg_set_hpm(hba);
5971 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
5972 ufshcd_set_link_active(hba);
5973 else if (ufshcd_is_link_off(hba))
5974 ufshcd_host_reset_and_restore(hba);
5975set_dev_active:
5976 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
5977 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST
5978enable_gating:
5979 hba->clk_gating.is_suspended = false;
5980 ufshcd_release(hba);
57d104c1
SJ
5981out:
5982 hba->pm_op_in_progress = 0;
5983 return ret;
7a3e97b0
SY
5984}
5985
5986/**
57d104c1 5987 * ufshcd_resume - helper function for resume operations
3b1d0580 5988 * @hba: per adapter instance
57d104c1 5989 * @pm_op: runtime PM or system PM
7a3e97b0 5990 *
57d104c1
SJ
5991 * This function basically brings the UFS device, UniPro link and controller
5992 * to active state.
5993 *
5994 * Returns 0 for success and non-zero for failure
7a3e97b0 5995 */
57d104c1 5996static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5997{
57d104c1
SJ
5998 int ret;
5999 enum uic_link_state old_link_state;
6000
6001 hba->pm_op_in_progress = 1;
6002 old_link_state = hba->uic_link_state;
6003
6004 ufshcd_hba_vreg_set_hpm(hba);
6005 /* Make sure clocks are enabled before accessing controller */
6006 ret = ufshcd_setup_clocks(hba, true);
6007 if (ret)
6008 goto out;
6009
57d104c1
SJ
6010 /* enable the host irq as host controller would be active soon */
6011 ret = ufshcd_enable_irq(hba);
6012 if (ret)
6013 goto disable_irq_and_vops_clks;
6014
6015 ret = ufshcd_vreg_set_hpm(hba);
6016 if (ret)
6017 goto disable_irq_and_vops_clks;
6018
7a3e97b0 6019 /*
57d104c1
SJ
6020 * Call vendor specific resume callback. As these callbacks may access
6021 * vendor specific host controller register space call them when the
6022 * host clocks are ON.
7a3e97b0 6023 */
0263bcd0
YG
6024 ret = ufshcd_vops_resume(hba, pm_op);
6025 if (ret)
6026 goto disable_vreg;
57d104c1
SJ
6027
6028 if (ufshcd_is_link_hibern8(hba)) {
6029 ret = ufshcd_uic_hibern8_exit(hba);
6030 if (!ret)
6031 ufshcd_set_link_active(hba);
6032 else
6033 goto vendor_suspend;
6034 } else if (ufshcd_is_link_off(hba)) {
6035 ret = ufshcd_host_reset_and_restore(hba);
6036 /*
6037 * ufshcd_host_reset_and_restore() should have already
6038 * set the link state as active
6039 */
6040 if (ret || !ufshcd_is_link_active(hba))
6041 goto vendor_suspend;
6042 }
6043
6044 if (!ufshcd_is_ufs_dev_active(hba)) {
6045 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6046 if (ret)
6047 goto set_old_link_state;
6048 }
6049
374a246e
SJ
6050 /*
6051 * If BKOPs operations are urgently needed at this moment then
6052 * keep auto-bkops enabled or else disable it.
6053 */
6054 ufshcd_urgent_bkops(hba);
1ab27c9c
ST
6055 hba->clk_gating.is_suspended = false;
6056
a508253d 6057 ufshcd_resume_clkscaling(hba);
856b3483 6058
1ab27c9c
ST
6059 /* Schedule clock gating in case of no access to UFS device yet */
6060 ufshcd_release(hba);
57d104c1
SJ
6061 goto out;
6062
6063set_old_link_state:
6064 ufshcd_link_state_transition(hba, old_link_state, 0);
6065vendor_suspend:
0263bcd0 6066 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ
6067disable_vreg:
6068 ufshcd_vreg_set_lpm(hba);
6069disable_irq_and_vops_clks:
6070 ufshcd_disable_irq(hba);
a508253d 6071 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ
6072 ufshcd_setup_clocks(hba, false);
6073out:
6074 hba->pm_op_in_progress = 0;
6075 return ret;
6076}
6077
6078/**
6079 * ufshcd_system_suspend - system suspend routine
6080 * @hba: per adapter instance
6081 * @pm_op: runtime PM or system PM
6082 *
6083 * Check the description of ufshcd_suspend() function for more details.
6084 *
6085 * Returns 0 for success and non-zero for failure
6086 */
6087int ufshcd_system_suspend(struct ufs_hba *hba)
6088{
6089 int ret = 0;
6090
6091 if (!hba || !hba->is_powered)
233b594b 6092 return 0;
57d104c1
SJ
6093
6094 if (pm_runtime_suspended(hba->dev)) {
6095 if (hba->rpm_lvl == hba->spm_lvl)
6096 /*
6097 * There is possibility that device may still be in
6098 * active state during the runtime suspend.
6099 */
6100 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6101 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
6102 goto out;
6103
6104 /*
6105 * UFS device and/or UFS link low power states during runtime
6106 * suspend seems to be different than what is expected during
6107 * system suspend. Hence runtime resume the devic & link and
6108 * let the system suspend low power states to take effect.
6109 * TODO: If resume takes longer time, we might have optimize
6110 * it in future by not resuming everything if possible.
6111 */
6112 ret = ufshcd_runtime_resume(hba);
6113 if (ret)
6114 goto out;
6115 }
6116
6117 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6118out:
e785060e
DR
6119 if (!ret)
6120 hba->is_sys_suspended = true;
57d104c1
SJ
6121 return ret;
6122}
6123EXPORT_SYMBOL(ufshcd_system_suspend);
6124
6125/**
6126 * ufshcd_system_resume - system resume routine
6127 * @hba: per adapter instance
6128 *
6129 * Returns 0 for success and non-zero for failure
6130 */
7a3e97b0 6131
57d104c1
SJ
6132int ufshcd_system_resume(struct ufs_hba *hba)
6133{
e3ce73d6
YG
6134 if (!hba)
6135 return -EINVAL;
6136
6137 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ
6138 /*
6139 * Let the runtime resume take care of resuming
6140 * if runtime suspended.
6141 */
6142 return 0;
6143
6144 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 6145}
57d104c1 6146EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6147
57d104c1
SJ
6148/**
6149 * ufshcd_runtime_suspend - runtime suspend routine
6150 * @hba: per adapter instance
6151 *
6152 * Check the description of ufshcd_suspend() function for more details.
6153 *
6154 * Returns 0 for success and non-zero for failure
6155 */
66ec6d59
SRT
6156int ufshcd_runtime_suspend(struct ufs_hba *hba)
6157{
e3ce73d6
YG
6158 if (!hba)
6159 return -EINVAL;
6160
6161 if (!hba->is_powered)
66ec6d59
SRT
6162 return 0;
6163
57d104c1 6164 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT
6165}
6166EXPORT_SYMBOL(ufshcd_runtime_suspend);
6167
57d104c1
SJ
6168/**
6169 * ufshcd_runtime_resume - runtime resume routine
6170 * @hba: per adapter instance
6171 *
6172 * This function basically brings the UFS device, UniPro link and controller
6173 * to active state. Following operations are done in this function:
6174 *
6175 * 1. Turn on all the controller related clocks
6176 * 2. Bring the UniPro link out of Hibernate state
6177 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6178 * to active state.
6179 * 4. If auto-bkops is enabled on the device, disable it.
6180 *
6181 * So following would be the possible power state after this function return
6182 * successfully:
6183 * S1: UFS device in Active state with VCC rail ON
6184 * UniPro link in Active state
6185 * All the UFS/UniPro controller clocks are ON
6186 *
6187 * Returns 0 for success and non-zero for failure
6188 */
66ec6d59
SRT
6189int ufshcd_runtime_resume(struct ufs_hba *hba)
6190{
e3ce73d6
YG
6191 if (!hba)
6192 return -EINVAL;
6193
6194 if (!hba->is_powered)
66ec6d59 6195 return 0;
e3ce73d6
YG
6196
6197 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT
6198}
6199EXPORT_SYMBOL(ufshcd_runtime_resume);
6200
6201int ufshcd_runtime_idle(struct ufs_hba *hba)
6202{
6203 return 0;
6204}
6205EXPORT_SYMBOL(ufshcd_runtime_idle);
6206
57d104c1
SJ
6207/**
6208 * ufshcd_shutdown - shutdown routine
6209 * @hba: per adapter instance
6210 *
6211 * This function would power off both UFS device and UFS link.
6212 *
6213 * Returns 0 always to allow force shutdown even in case of errors.
6214 */
6215int ufshcd_shutdown(struct ufs_hba *hba)
6216{
6217 int ret = 0;
6218
6219 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6220 goto out;
6221
6222 if (pm_runtime_suspended(hba->dev)) {
6223 ret = ufshcd_runtime_resume(hba);
6224 if (ret)
6225 goto out;
6226 }
6227
6228 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6229out:
6230 if (ret)
6231 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6232 /* allow force shutdown even in case of errors */
6233 return 0;
6234}
6235EXPORT_SYMBOL(ufshcd_shutdown);
6236
7a3e97b0 6237/**
3b1d0580 6238 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6239 * data structure memory
3b1d0580 6240 * @hba - per adapter instance
7a3e97b0 6241 */
3b1d0580 6242void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6243{
cfdf9c91 6244 scsi_remove_host(hba->host);
7a3e97b0 6245 /* disable interrupts */
2fbd009b 6246 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6247 ufshcd_hba_stop(hba, true);
7a3e97b0 6248
7a3e97b0 6249 scsi_host_put(hba->host);
5c0c28a8 6250
1ab27c9c 6251 ufshcd_exit_clk_gating(hba);
856b3483
ST
6252 if (ufshcd_is_clkscaling_enabled(hba))
6253 devfreq_remove_device(hba->devfreq);
aa497613 6254 ufshcd_hba_exit(hba);
3b1d0580
VH
6255}
6256EXPORT_SYMBOL_GPL(ufshcd_remove);
6257
47555a5c
YG
6258/**
6259 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6260 * @hba: pointer to Host Bus Adapter (HBA)
6261 */
6262void ufshcd_dealloc_host(struct ufs_hba *hba)
6263{
6264 scsi_host_put(hba->host);
6265}
6266EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6267
ca3d7bf9
AM
6268/**
6269 * ufshcd_set_dma_mask - Set dma mask based on the controller
6270 * addressing capability
6271 * @hba: per adapter instance
6272 *
6273 * Returns 0 for success, non-zero for failure
6274 */
6275static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6276{
6277 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6278 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6279 return 0;
6280 }
6281 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6282}
6283
7a3e97b0 6284/**
5c0c28a8 6285 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH
6286 * @dev: pointer to device handle
6287 * @hba_handle: driver private handle
7a3e97b0
SY
6288 * Returns 0 on success, non-zero value on failure
6289 */
5c0c28a8 6290int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY
6291{
6292 struct Scsi_Host *host;
6293 struct ufs_hba *hba;
5c0c28a8 6294 int err = 0;
7a3e97b0 6295
3b1d0580
VH
6296 if (!dev) {
6297 dev_err(dev,
6298 "Invalid memory reference for dev is NULL\n");
6299 err = -ENODEV;
7a3e97b0
SY
6300 goto out_error;
6301 }
6302
7a3e97b0
SY
6303 host = scsi_host_alloc(&ufshcd_driver_template,
6304 sizeof(struct ufs_hba));
6305 if (!host) {
3b1d0580 6306 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6307 err = -ENOMEM;
3b1d0580 6308 goto out_error;
7a3e97b0
SY
6309 }
6310 hba = shost_priv(host);
7a3e97b0 6311 hba->host = host;
3b1d0580 6312 hba->dev = dev;
5c0c28a8
SRT
6313 *hba_handle = hba;
6314
6315out_error:
6316 return err;
6317}
6318EXPORT_SYMBOL(ufshcd_alloc_host);
6319
856b3483
ST
6320static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6321{
6322 int ret = 0;
6323 struct ufs_clk_info *clki;
6324 struct list_head *head = &hba->clk_list_head;
6325
6326 if (!head || list_empty(head))
6327 goto out;
6328
f06fcc71
YG
6329 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
6330 if (ret)
6331 return ret;
6332
856b3483
ST
6333 list_for_each_entry(clki, head, list) {
6334 if (!IS_ERR_OR_NULL(clki->clk)) {
6335 if (scale_up && clki->max_freq) {
6336 if (clki->curr_freq == clki->max_freq)
6337 continue;
6338 ret = clk_set_rate(clki->clk, clki->max_freq);
6339 if (ret) {
6340 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6341 __func__, clki->name,
6342 clki->max_freq, ret);
6343 break;
6344 }
6345 clki->curr_freq = clki->max_freq;
6346
6347 } else if (!scale_up && clki->min_freq) {
6348 if (clki->curr_freq == clki->min_freq)
6349 continue;
6350 ret = clk_set_rate(clki->clk, clki->min_freq);
6351 if (ret) {
6352 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6353 __func__, clki->name,
6354 clki->min_freq, ret);
6355 break;
6356 }
6357 clki->curr_freq = clki->min_freq;
6358 }
6359 }
6360 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
6361 clki->name, clk_get_rate(clki->clk));
6362 }
f06fcc71
YG
6363
6364 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
6365
856b3483
ST
6366out:
6367 return ret;
6368}
6369
6370static int ufshcd_devfreq_target(struct device *dev,
6371 unsigned long *freq, u32 flags)
6372{
6373 int err = 0;
6374 struct ufs_hba *hba = dev_get_drvdata(dev);
6375
6376 if (!ufshcd_is_clkscaling_enabled(hba))
6377 return -EINVAL;
6378
6379 if (*freq == UINT_MAX)
6380 err = ufshcd_scale_clks(hba, true);
6381 else if (*freq == 0)
6382 err = ufshcd_scale_clks(hba, false);
6383
6384 return err;
6385}
6386
6387static int ufshcd_devfreq_get_dev_status(struct device *dev,
6388 struct devfreq_dev_status *stat)
6389{
6390 struct ufs_hba *hba = dev_get_drvdata(dev);
6391 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
6392 unsigned long flags;
6393
6394 if (!ufshcd_is_clkscaling_enabled(hba))
6395 return -EINVAL;
6396
6397 memset(stat, 0, sizeof(*stat));
6398
6399 spin_lock_irqsave(hba->host->host_lock, flags);
6400 if (!scaling->window_start_t)
6401 goto start_window;
6402
6403 if (scaling->is_busy_started)
6404 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
6405 scaling->busy_start_t));
6406
6407 stat->total_time = jiffies_to_usecs((long)jiffies -
6408 (long)scaling->window_start_t);
6409 stat->busy_time = scaling->tot_busy_t;
6410start_window:
6411 scaling->window_start_t = jiffies;
6412 scaling->tot_busy_t = 0;
6413
6414 if (hba->outstanding_reqs) {
6415 scaling->busy_start_t = ktime_get();
6416 scaling->is_busy_started = true;
6417 } else {
6418 scaling->busy_start_t = ktime_set(0, 0);
6419 scaling->is_busy_started = false;
6420 }
6421 spin_unlock_irqrestore(hba->host->host_lock, flags);
6422 return 0;
6423}
6424
6425static struct devfreq_dev_profile ufs_devfreq_profile = {
6426 .polling_ms = 100,
6427 .target = ufshcd_devfreq_target,
6428 .get_dev_status = ufshcd_devfreq_get_dev_status,
6429};
6430
5c0c28a8
SRT
6431/**
6432 * ufshcd_init - Driver initialization routine
6433 * @hba: per-adapter instance
6434 * @mmio_base: base register address
6435 * @irq: Interrupt line of device
6436 * Returns 0 on success, non-zero value on failure
6437 */
6438int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
6439{
6440 int err;
6441 struct Scsi_Host *host = hba->host;
6442 struct device *dev = hba->dev;
6443
6444 if (!mmio_base) {
6445 dev_err(hba->dev,
6446 "Invalid memory reference for mmio_base is NULL\n");
6447 err = -ENODEV;
6448 goto out_error;
6449 }
6450
3b1d0580
VH
6451 hba->mmio_base = mmio_base;
6452 hba->irq = irq;
7a3e97b0 6453
aa497613 6454 err = ufshcd_hba_init(hba);
5c0c28a8
SRT
6455 if (err)
6456 goto out_error;
6457
7a3e97b0
SY
6458 /* Read capabilities registers */
6459 ufshcd_hba_capabilities(hba);
6460
6461 /* Get UFS version supported by the controller */
6462 hba->ufs_version = ufshcd_get_ufs_version(hba);
6463
2fbd009b
SJ
6464 /* Get Interrupt bit mask per version */
6465 hba->intr_mask = ufshcd_get_intr_mask(hba);
6466
ca3d7bf9
AM
6467 err = ufshcd_set_dma_mask(hba);
6468 if (err) {
6469 dev_err(hba->dev, "set dma mask failed\n");
6470 goto out_disable;
6471 }
6472
7a3e97b0
SY
6473 /* Allocate memory for host memory space */
6474 err = ufshcd_memory_alloc(hba);
6475 if (err) {
3b1d0580
VH
6476 dev_err(hba->dev, "Memory allocation failed\n");
6477 goto out_disable;
7a3e97b0
SY
6478 }
6479
6480 /* Configure LRB */
6481 ufshcd_host_memory_configure(hba);
6482
6483 host->can_queue = hba->nutrs;
6484 host->cmd_per_lun = hba->nutrs;
6485 host->max_id = UFSHCD_MAX_ID;
0ce147d4 6486 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY
6487 host->max_channel = UFSHCD_MAX_CHANNEL;
6488 host->unique_id = host->host_no;
6489 host->max_cmd_len = MAX_CDB_SIZE;
6490
7eb584db
DR
6491 hba->max_pwr_info.is_valid = false;
6492
7a3e97b0 6493 /* Initailize wait queue for task management */
e2933132
SRT
6494 init_waitqueue_head(&hba->tm_wq);
6495 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY
6496
6497 /* Initialize work queues */
e8e7f271 6498 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 6499 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 6500
6ccf44fe
SJ
6501 /* Initialize UIC command mutex */
6502 mutex_init(&hba->uic_cmd_mutex);
6503
5a0b0cb9
SRT
6504 /* Initialize mutex for device management commands */
6505 mutex_init(&hba->dev_cmd.lock);
6506
6507 /* Initialize device management tag acquire wait queue */
6508 init_waitqueue_head(&hba->dev_cmd.tag_wq);
6509
1ab27c9c 6510 ufshcd_init_clk_gating(hba);
199ef13c
YG
6511
6512 /*
6513 * In order to avoid any spurious interrupt immediately after
6514 * registering UFS controller interrupt handler, clear any pending UFS
6515 * interrupt status and disable all the UFS interrupts.
6516 */
6517 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
6518 REG_INTERRUPT_STATUS);
6519 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
6520 /*
6521 * Make sure that UFS interrupts are disabled and any pending interrupt
6522 * status is cleared before registering UFS interrupt handler.
6523 */
6524 mb();
6525
7a3e97b0 6526 /* IRQ registration */
2953f850 6527 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 6528 if (err) {
3b1d0580 6529 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 6530 goto exit_gating;
57d104c1
SJ
6531 } else {
6532 hba->is_irq_enabled = true;
7a3e97b0
SY
6533 }
6534
3b1d0580 6535 err = scsi_add_host(host, hba->dev);
7a3e97b0 6536 if (err) {
3b1d0580 6537 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 6538 goto exit_gating;
7a3e97b0
SY
6539 }
6540
6ccf44fe
SJ
6541 /* Host controller enable */
6542 err = ufshcd_hba_enable(hba);
7a3e97b0 6543 if (err) {
6ccf44fe 6544 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 6545 goto out_remove_scsi_host;
7a3e97b0 6546 }
6ccf44fe 6547
856b3483
ST
6548 if (ufshcd_is_clkscaling_enabled(hba)) {
6549 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
6550 "simple_ondemand", NULL);
6551 if (IS_ERR(hba->devfreq)) {
6552 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
6553 PTR_ERR(hba->devfreq));
73811c94 6554 err = PTR_ERR(hba->devfreq);
856b3483
ST
6555 goto out_remove_scsi_host;
6556 }
6557 /* Suspend devfreq until the UFS device is detected */
a508253d 6558 ufshcd_suspend_clkscaling(hba);
856b3483
ST
6559 }
6560
62694735
SRT
6561 /* Hold auto suspend until async scan completes */
6562 pm_runtime_get_sync(dev);
6563
57d104c1
SJ
6564 /*
6565 * The device-initialize-sequence hasn't been invoked yet.
6566 * Set the device to power-off state
6567 */
6568 ufshcd_set_ufs_dev_poweroff(hba);
6569
6ccf44fe
SJ
6570 async_schedule(ufshcd_async_scan, hba);
6571
7a3e97b0
SY
6572 return 0;
6573
3b1d0580
VH
6574out_remove_scsi_host:
6575 scsi_remove_host(hba->host);
1ab27c9c
ST
6576exit_gating:
6577 ufshcd_exit_clk_gating(hba);
3b1d0580 6578out_disable:
57d104c1 6579 hba->is_irq_enabled = false;
3b1d0580 6580 scsi_host_put(host);
aa497613 6581 ufshcd_hba_exit(hba);
3b1d0580
VH
6582out_error:
6583 return err;
6584}
6585EXPORT_SYMBOL_GPL(ufshcd_init);
6586
3b1d0580
VH
6587MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
6588MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 6589MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY
6590MODULE_LICENSE("GPL");
6591MODULE_VERSION(UFSHCD_DRIVER_VERSION);