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scsi: ufs: avoid exception event handler racing with PM callbacks
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
6ccf44fe 42
e0eca63e 43#include "ufshcd.h"
53b3d9c3 44#include "unipro.h"
7a3e97b0 45
2fbd009b
SJ		 46#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
47 UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 49/* UIC command timeout, unit: ms */
50#define UIC_CMD_TIMEOUT 500
2fbd009b 51
5a0b0cb9
SRT		 52/* NOP OUT retries waiting for NOP IN response */
53#define NOP_OUT_RETRIES 10
54/* Timeout after 30 msecs if NOP OUT hangs without response */
55#define NOP_OUT_TIMEOUT 30 /* msecs */
56
68078d5c
DR		 57/* Query request retries */
58#define QUERY_REQ_RETRIES 10
59/* Query request timeout */
60#define QUERY_REQ_TIMEOUT 30 /* msec */
e5ad406c
YG		 61/*
62 * Query request timeout for fDeviceInit flag
63 * fDeviceInit query response time for some devices is too large that default
64 * QUERY_REQ_TIMEOUT may not be enough for such devices.
65 */
66#define QUERY_FDEVICEINIT_REQ_TIMEOUT 600 /* msec */
68078d5c 67
e2933132
SRT		 68/* Task management command timeout */
69#define TM_CMD_TIMEOUT 100 /* msecs */
70
1d337ec2
SRT		 71/* maximum number of link-startup retries */
72#define DME_LINKSTARTUP_RETRIES 3
73
74/* maximum number of reset retries before giving up */
75#define MAX_HOST_RESET_RETRIES 5
76
68078d5c
DR		 77/* Expose the flag value from utp_upiu_query.value */
78#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
79
7d568652
SJ		 80/* Interrupt aggregation default timeout, unit: 40us */
81#define INT_AGGR_DEF_TO 0x02
82
aa497613
SRT		 83#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
84 ({ \
85 int _ret; \
86 if (_on) \
87 _ret = ufshcd_enable_vreg(_dev, _vreg); \
88 else \
89 _ret = ufshcd_disable_vreg(_dev, _vreg); \
90 _ret; \
91 })
92
da461cec
SJ		 93static u32 ufs_query_desc_max_size[] = {
94 QUERY_DESC_DEVICE_MAX_SIZE,
95 QUERY_DESC_CONFIGURAION_MAX_SIZE,
96 QUERY_DESC_UNIT_MAX_SIZE,
97 QUERY_DESC_RFU_MAX_SIZE,
98 QUERY_DESC_INTERCONNECT_MAX_SIZE,
99 QUERY_DESC_STRING_MAX_SIZE,
100 QUERY_DESC_RFU_MAX_SIZE,
101 QUERY_DESC_GEOMETRY_MAZ_SIZE,
102 QUERY_DESC_POWER_MAX_SIZE,
103 QUERY_DESC_RFU_MAX_SIZE,
104};
105
7a3e97b0
SY		 106enum {
107 UFSHCD_MAX_CHANNEL = 0,
108 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 109 UFSHCD_CMD_PER_LUN = 32,
110 UFSHCD_CAN_QUEUE = 32,
111};
112
113/* UFSHCD states */
114enum {
7a3e97b0
SY		 115 UFSHCD_STATE_RESET,
116 UFSHCD_STATE_ERROR,
3441da7d
SRT		 117 UFSHCD_STATE_OPERATIONAL,
118};
119
120/* UFSHCD error handling flags */
121enum {
122 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 123};
124
e8e7f271
SRT		 125/* UFSHCD UIC layer error flags */
126enum {
127 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
128 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
129 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
130 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
131};
132
7a3e97b0
SY		 133/* Interrupt configuration options */
134enum {
135 UFSHCD_INT_DISABLE,
136 UFSHCD_INT_ENABLE,
137 UFSHCD_INT_CLEAR,
138};
139
3441da7d
SRT		 140#define ufshcd_set_eh_in_progress(h) \
141 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
142#define ufshcd_eh_in_progress(h) \
143 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
144#define ufshcd_clear_eh_in_progress(h) \
145 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
146
57d104c1
SJ		 147#define ufshcd_set_ufs_dev_active(h) \
148 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
149#define ufshcd_set_ufs_dev_sleep(h) \
150 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
151#define ufshcd_set_ufs_dev_poweroff(h) \
152 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
153#define ufshcd_is_ufs_dev_active(h) \
154 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
155#define ufshcd_is_ufs_dev_sleep(h) \
156 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
157#define ufshcd_is_ufs_dev_poweroff(h) \
158 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
159
160static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
161 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
162 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
163 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
164 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
165 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
166 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
167};
168
169static inline enum ufs_dev_pwr_mode
170ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].dev_state;
173}
174
175static inline enum uic_link_state
176ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
177{
178 return ufs_pm_lvl_states[lvl].link_state;
179}
180
3441da7d
SRT		 181static void ufshcd_tmc_handler(struct ufs_hba *hba);
182static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 183static int ufshcd_reset_and_restore(struct ufs_hba *hba);
184static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 185static void ufshcd_hba_exit(struct ufs_hba *hba);
186static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 187static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
188 bool skip_ref_clk);
189static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
190static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
191static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 192static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ		 193static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
194static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 195static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
196 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 197static int ufshcd_change_power_mode(struct ufs_hba *hba,
198 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 199static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
200{
201 return tag >= 0 && tag < hba->nutrs;
202}
57d104c1
SJ		 203
204static inline int ufshcd_enable_irq(struct ufs_hba *hba)
205{
206 int ret = 0;
207
208 if (!hba->is_irq_enabled) {
209 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
210 hba);
211 if (ret)
212 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
213 __func__, ret);
214 hba->is_irq_enabled = true;
215 }
216
217 return ret;
218}
219
220static inline void ufshcd_disable_irq(struct ufs_hba *hba)
221{
222 if (hba->is_irq_enabled) {
223 free_irq(hba->irq, hba);
224 hba->is_irq_enabled = false;
225 }
226}
3441da7d 227
5a0b0cb9
SRT		 228/*
229 * ufshcd_wait_for_register - wait for register value to change
230 * @hba - per-adapter interface
231 * @reg - mmio register offset
232 * @mask - mask to apply to read register value
233 * @val - wait condition
234 * @interval_us - polling interval in microsecs
235 * @timeout_ms - timeout in millisecs
236 *
237 * Returns -ETIMEDOUT on error, zero on success
238 */
239static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
240 u32 val, unsigned long interval_us, unsigned long timeout_ms)
241{
242 int err = 0;
243 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
244
245 /* ignore bits that we don't intend to wait on */
246 val = val & mask;
247
248 while ((ufshcd_readl(hba, reg) & mask) != val) {
249 /* wakeup within 50us of expiry */
250 usleep_range(interval_us, interval_us + 50);
251
252 if (time_after(jiffies, timeout)) {
253 if ((ufshcd_readl(hba, reg) & mask) != val)
254 err = -ETIMEDOUT;
255 break;
256 }
257 }
258
259 return err;
260}
261
2fbd009b
SJ		 262/**
263 * ufshcd_get_intr_mask - Get the interrupt bit mask
264 * @hba - Pointer to adapter instance
265 *
266 * Returns interrupt bit mask per version
267 */
268static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
269{
270 if (hba->ufs_version == UFSHCI_VERSION_10)
271 return INTERRUPT_MASK_ALL_VER_10;
272 else
273 return INTERRUPT_MASK_ALL_VER_11;
274}
275
7a3e97b0
SY		 276/**
277 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
278 * @hba - Pointer to adapter instance
279 *
280 * Returns UFSHCI version supported by the controller
281 */
282static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
283{
0263bcd0
YG		 284 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
285 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 286
b873a275 287 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 288}
289
290/**
291 * ufshcd_is_device_present - Check if any device connected to
292 * the host controller
5c0c28a8 293 * @hba: pointer to adapter instance
7a3e97b0 294 *
73ec513a 295 * Returns 1 if device present, 0 if no device detected
7a3e97b0 296 */
5c0c28a8 297static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 298{
5c0c28a8
SRT		 299 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
300 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 301}
302
303/**
304 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
305 * @lrb: pointer to local command reference block
306 *
307 * This function is used to get the OCS field from UTRD
308 * Returns the OCS field in the UTRD
309 */
310static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
311{
e8c8e82a 312 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 313}
314
315/**
316 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
317 * @task_req_descp: pointer to utp_task_req_desc structure
318 *
319 * This function is used to get the OCS field from UTMRD
320 * Returns the OCS field in the UTMRD
321 */
322static inline int
323ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
324{
e8c8e82a 325 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 326}
327
328/**
329 * ufshcd_get_tm_free_slot - get a free slot for task management request
330 * @hba: per adapter instance
e2933132 331 * @free_slot: pointer to variable with available slot value
7a3e97b0 332 *
e2933132
SRT		 333 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
334 * Returns 0 if free slot is not available, else return 1 with tag value
335 * in @free_slot.
7a3e97b0 336 */
e2933132 337static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 338{
e2933132
SRT		 339 int tag;
340 bool ret = false;
341
342 if (!free_slot)
343 goto out;
344
345 do {
346 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
347 if (tag >= hba->nutmrs)
348 goto out;
349 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
350
351 *free_slot = tag;
352 ret = true;
353out:
354 return ret;
355}
356
357static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
358{
359 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 360}
361
362/**
363 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
364 * @hba: per adapter instance
365 * @pos: position of the bit to be cleared
366 */
367static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
368{
b873a275 369 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 370}
371
a48353f6
YG		 372/**
373 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
374 * @hba: per adapter instance
375 * @tag: position of the bit to be cleared
376 */
377static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
378{
379 __clear_bit(tag, &hba->outstanding_reqs);
380}
381
7a3e97b0
SY		 382/**
383 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
384 * @reg: Register value of host controller status
385 *
386 * Returns integer, 0 on Success and positive value if failed
387 */
388static inline int ufshcd_get_lists_status(u32 reg)
389{
390 /*
391 * The mask 0xFF is for the following HCS register bits
392 * Bit Description
393 * 0 Device Present
394 * 1 UTRLRDY
395 * 2 UTMRLRDY
396 * 3 UCRDY
397 * 4 HEI
398 * 5 DEI
399 * 6-7 reserved
400 */
401 return (((reg) & (0xFF)) >> 1) ^ (0x07);
402}
403
404/**
405 * ufshcd_get_uic_cmd_result - Get the UIC command result
406 * @hba: Pointer to adapter instance
407 *
408 * This function gets the result of UIC command completion
409 * Returns 0 on success, non zero value on error
410 */
411static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
412{
b873a275 413 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 414 MASK_UIC_COMMAND_RESULT;
415}
416
12b4fdb4
SJ		 417/**
418 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
419 * @hba: Pointer to adapter instance
420 *
421 * This function gets UIC command argument3
422 * Returns 0 on success, non zero value on error
423 */
424static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
425{
426 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
427}
428
7a3e97b0 429/**
5a0b0cb9 430 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 431 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 432 */
433static inline int
5a0b0cb9 434ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 435{
5a0b0cb9 436 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 437}
438
439/**
440 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
441 * @ucd_rsp_ptr: pointer to response UPIU
442 *
443 * This function gets the response status and scsi_status from response UPIU
444 * Returns the response result code.
445 */
446static inline int
447ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
448{
449 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
450}
451
1c2623c5
SJ		 452/*
453 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
454 * from response UPIU
455 * @ucd_rsp_ptr: pointer to response UPIU
456 *
457 * Return the data segment length.
458 */
459static inline unsigned int
460ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
461{
462 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
463 MASK_RSP_UPIU_DATA_SEG_LEN;
464}
465
66ec6d59
SRT		 466/**
467 * ufshcd_is_exception_event - Check if the device raised an exception event
468 * @ucd_rsp_ptr: pointer to response UPIU
469 *
470 * The function checks if the device raised an exception event indicated in
471 * the Device Information field of response UPIU.
472 *
473 * Returns true if exception is raised, false otherwise.
474 */
475static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
476{
477 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
478 MASK_RSP_EXCEPTION_EVENT ? true : false;
479}
480
7a3e97b0 481/**
7d568652 482 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 483 * @hba: per adapter instance
7a3e97b0
SY		 484 */
485static inline void
7d568652 486ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 487{
7d568652
SJ		 488 ufshcd_writel(hba, INT_AGGR_ENABLE |
489 INT_AGGR_COUNTER_AND_TIMER_RESET,
490 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
491}
492
493/**
494 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
495 * @hba: per adapter instance
496 * @cnt: Interrupt aggregation counter threshold
497 * @tmout: Interrupt aggregation timeout value
498 */
499static inline void
500ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
501{
502 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
503 INT_AGGR_COUNTER_THLD_VAL(cnt) |
504 INT_AGGR_TIMEOUT_VAL(tmout),
505 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 506}
507
b852190e
YG		 508/**
509 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
510 * @hba: per adapter instance
511 */
512static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
513{
514 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
515}
516
7a3e97b0
SY		 517/**
518 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
519 * When run-stop registers are set to 1, it indicates the
520 * host controller that it can process the requests
521 * @hba: per adapter instance
522 */
523static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
524{
b873a275
SJ		 525 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
526 REG_UTP_TASK_REQ_LIST_RUN_STOP);
527 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
528 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 529}
530
7a3e97b0
SY		 531/**
532 * ufshcd_hba_start - Start controller initialization sequence
533 * @hba: per adapter instance
534 */
535static inline void ufshcd_hba_start(struct ufs_hba *hba)
536{
b873a275 537 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 538}
539
540/**
541 * ufshcd_is_hba_active - Get controller state
542 * @hba: per adapter instance
543 *
544 * Returns zero if controller is active, 1 otherwise
545 */
546static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
547{
b873a275 548 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 549}
550
1ab27c9c
ST		 551static void ufshcd_ungate_work(struct work_struct *work)
552{
553 int ret;
554 unsigned long flags;
555 struct ufs_hba *hba = container_of(work, struct ufs_hba,
556 clk_gating.ungate_work);
557
558 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
559
560 spin_lock_irqsave(hba->host->host_lock, flags);
561 if (hba->clk_gating.state == CLKS_ON) {
562 spin_unlock_irqrestore(hba->host->host_lock, flags);
563 goto unblock_reqs;
564 }
565
566 spin_unlock_irqrestore(hba->host->host_lock, flags);
567 ufshcd_setup_clocks(hba, true);
568
569 /* Exit from hibern8 */
570 if (ufshcd_can_hibern8_during_gating(hba)) {
571 /* Prevent gating in this path */
572 hba->clk_gating.is_suspended = true;
573 if (ufshcd_is_link_hibern8(hba)) {
574 ret = ufshcd_uic_hibern8_exit(hba);
575 if (ret)
576 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
577 __func__, ret);
578 else
579 ufshcd_set_link_active(hba);
580 }
581 hba->clk_gating.is_suspended = false;
582 }
583unblock_reqs:
856b3483
ST		 584 if (ufshcd_is_clkscaling_enabled(hba))
585 devfreq_resume_device(hba->devfreq);
1ab27c9c
ST		 586 scsi_unblock_requests(hba->host);
587}
588
589/**
590 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
591 * Also, exit from hibern8 mode and set the link as active.
592 * @hba: per adapter instance
593 * @async: This indicates whether caller should ungate clocks asynchronously.
594 */
595int ufshcd_hold(struct ufs_hba *hba, bool async)
596{
597 int rc = 0;
598 unsigned long flags;
599
600 if (!ufshcd_is_clkgating_allowed(hba))
601 goto out;
1ab27c9c
ST		 602 spin_lock_irqsave(hba->host->host_lock, flags);
603 hba->clk_gating.active_reqs++;
604
856b3483 605start:
1ab27c9c
ST		 606 switch (hba->clk_gating.state) {
607 case CLKS_ON:
608 break;
609 case REQ_CLKS_OFF:
610 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
611 hba->clk_gating.state = CLKS_ON;
612 break;
613 }
614 /*
615 * If we here, it means gating work is either done or
616 * currently running. Hence, fall through to cancel gating
617 * work and to enable clocks.
618 */
619 case CLKS_OFF:
620 scsi_block_requests(hba->host);
621 hba->clk_gating.state = REQ_CLKS_ON;
622 schedule_work(&hba->clk_gating.ungate_work);
623 /*
624 * fall through to check if we should wait for this
625 * work to be done or not.
626 */
627 case REQ_CLKS_ON:
628 if (async) {
629 rc = -EAGAIN;
630 hba->clk_gating.active_reqs--;
631 break;
632 }
633
634 spin_unlock_irqrestore(hba->host->host_lock, flags);
635 flush_work(&hba->clk_gating.ungate_work);
636 /* Make sure state is CLKS_ON before returning */
856b3483 637 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 638 goto start;
639 default:
640 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
641 __func__, hba->clk_gating.state);
642 break;
643 }
644 spin_unlock_irqrestore(hba->host->host_lock, flags);
645out:
646 return rc;
647}
6e3fd44d 648EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 649
650static void ufshcd_gate_work(struct work_struct *work)
651{
652 struct ufs_hba *hba = container_of(work, struct ufs_hba,
653 clk_gating.gate_work.work);
654 unsigned long flags;
655
656 spin_lock_irqsave(hba->host->host_lock, flags);
657 if (hba->clk_gating.is_suspended) {
658 hba->clk_gating.state = CLKS_ON;
659 goto rel_lock;
660 }
661
662 if (hba->clk_gating.active_reqs
663 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
664 || hba->lrb_in_use || hba->outstanding_tasks
665 || hba->active_uic_cmd || hba->uic_async_done)
666 goto rel_lock;
667
668 spin_unlock_irqrestore(hba->host->host_lock, flags);
669
670 /* put the link into hibern8 mode before turning off clocks */
671 if (ufshcd_can_hibern8_during_gating(hba)) {
672 if (ufshcd_uic_hibern8_enter(hba)) {
673 hba->clk_gating.state = CLKS_ON;
674 goto out;
675 }
676 ufshcd_set_link_hibern8(hba);
677 }
678
856b3483
ST		 679 if (ufshcd_is_clkscaling_enabled(hba)) {
680 devfreq_suspend_device(hba->devfreq);
681 hba->clk_scaling.window_start_t = 0;
682 }
683
1ab27c9c
ST		 684 if (!ufshcd_is_link_active(hba))
685 ufshcd_setup_clocks(hba, false);
686 else
687 /* If link is active, device ref_clk can't be switched off */
688 __ufshcd_setup_clocks(hba, false, true);
689
690 /*
691 * In case you are here to cancel this work the gating state
692 * would be marked as REQ_CLKS_ON. In this case keep the state
693 * as REQ_CLKS_ON which would anyway imply that clocks are off
694 * and a request to turn them on is pending. By doing this way,
695 * we keep the state machine in tact and this would ultimately
696 * prevent from doing cancel work multiple times when there are
697 * new requests arriving before the current cancel work is done.
698 */
699 spin_lock_irqsave(hba->host->host_lock, flags);
700 if (hba->clk_gating.state == REQ_CLKS_OFF)
701 hba->clk_gating.state = CLKS_OFF;
702
703rel_lock:
704 spin_unlock_irqrestore(hba->host->host_lock, flags);
705out:
706 return;
707}
708
709/* host lock must be held before calling this variant */
710static void __ufshcd_release(struct ufs_hba *hba)
711{
712 if (!ufshcd_is_clkgating_allowed(hba))
713 return;
714
715 hba->clk_gating.active_reqs--;
716
717 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
718 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
719 || hba->lrb_in_use || hba->outstanding_tasks
720 || hba->active_uic_cmd || hba->uic_async_done)
721 return;
722
723 hba->clk_gating.state = REQ_CLKS_OFF;
724 schedule_delayed_work(&hba->clk_gating.gate_work,
725 msecs_to_jiffies(hba->clk_gating.delay_ms));
726}
727
728void ufshcd_release(struct ufs_hba *hba)
729{
730 unsigned long flags;
731
732 spin_lock_irqsave(hba->host->host_lock, flags);
733 __ufshcd_release(hba);
734 spin_unlock_irqrestore(hba->host->host_lock, flags);
735}
6e3fd44d 736EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 737
738static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
739 struct device_attribute *attr, char *buf)
740{
741 struct ufs_hba *hba = dev_get_drvdata(dev);
742
743 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
744}
745
746static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
747 struct device_attribute *attr, const char *buf, size_t count)
748{
749 struct ufs_hba *hba = dev_get_drvdata(dev);
750 unsigned long flags, value;
751
752 if (kstrtoul(buf, 0, &value))
753 return -EINVAL;
754
755 spin_lock_irqsave(hba->host->host_lock, flags);
756 hba->clk_gating.delay_ms = value;
757 spin_unlock_irqrestore(hba->host->host_lock, flags);
758 return count;
759}
760
761static void ufshcd_init_clk_gating(struct ufs_hba *hba)
762{
763 if (!ufshcd_is_clkgating_allowed(hba))
764 return;
765
766 hba->clk_gating.delay_ms = 150;
767 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
768 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
769
770 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
771 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
772 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
773 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
774 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
775 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
776 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
777}
778
779static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
780{
781 if (!ufshcd_is_clkgating_allowed(hba))
782 return;
783 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM		 784 cancel_work_sync(&hba->clk_gating.ungate_work);
785 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 786}
787
856b3483
ST		 788/* Must be called with host lock acquired */
789static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
790{
791 if (!ufshcd_is_clkscaling_enabled(hba))
792 return;
793
794 if (!hba->clk_scaling.is_busy_started) {
795 hba->clk_scaling.busy_start_t = ktime_get();
796 hba->clk_scaling.is_busy_started = true;
797 }
798}
799
800static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
801{
802 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
803
804 if (!ufshcd_is_clkscaling_enabled(hba))
805 return;
806
807 if (!hba->outstanding_reqs && scaling->is_busy_started) {
808 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
809 scaling->busy_start_t));
810 scaling->busy_start_t = ktime_set(0, 0);
811 scaling->is_busy_started = false;
812 }
813}
7a3e97b0
SY		 814/**
815 * ufshcd_send_command - Send SCSI or device management commands
816 * @hba: per adapter instance
817 * @task_tag: Task tag of the command
818 */
819static inline
820void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
821{
856b3483 822 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 823 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 824 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 825}
826
827/**
828 * ufshcd_copy_sense_data - Copy sense data in case of check condition
829 * @lrb - pointer to local reference block
830 */
831static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
832{
833 int len;
1c2623c5
SJ		 834 if (lrbp->sense_buffer &&
835 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 836 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 837 memcpy(lrbp->sense_buffer,
5a0b0cb9 838 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 839 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
840 }
841}
842
68078d5c
DR		 843/**
844 * ufshcd_copy_query_response() - Copy the Query Response and the data
845 * descriptor
846 * @hba: per adapter instance
847 * @lrb - pointer to local reference block
848 */
849static
c6d4a831 850int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 851{
852 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
853
68078d5c 854 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 855
68078d5c
DR		 856 /* Get the descriptor */
857 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 858 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 859 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 860 u16 resp_len;
861 u16 buf_len;
68078d5c
DR		 862
863 /* data segment length */
c6d4a831 864 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 865 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 866 buf_len = be16_to_cpu(
867 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 868 if (likely(buf_len >= resp_len)) {
869 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
870 } else {
871 dev_warn(hba->dev,
872 "%s: Response size is bigger than buffer",
873 __func__);
874 return -EINVAL;
875 }
68078d5c 876 }
c6d4a831
DR		 877
878 return 0;
68078d5c
DR		 879}
880
7a3e97b0
SY		 881/**
882 * ufshcd_hba_capabilities - Read controller capabilities
883 * @hba: per adapter instance
884 */
885static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
886{
b873a275 887 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 888
889 /* nutrs and nutmrs are 0 based values */
890 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
891 hba->nutmrs =
892 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
893}
894
895/**
6ccf44fe
SJ		 896 * ufshcd_ready_for_uic_cmd - Check if controller is ready
897 * to accept UIC commands
7a3e97b0 898 * @hba: per adapter instance
6ccf44fe
SJ		 899 * Return true on success, else false
900 */
901static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
902{
903 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
904 return true;
905 else
906 return false;
907}
908
53b3d9c3
SJ		 909/**
910 * ufshcd_get_upmcrs - Get the power mode change request status
911 * @hba: Pointer to adapter instance
912 *
913 * This function gets the UPMCRS field of HCS register
914 * Returns value of UPMCRS field
915 */
916static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
917{
918 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
919}
920
6ccf44fe
SJ		 921/**
922 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
923 * @hba: per adapter instance
924 * @uic_cmd: UIC command
925 *
926 * Mutex must be held.
7a3e97b0
SY		 927 */
928static inline void
6ccf44fe 929ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 930{
6ccf44fe
SJ		 931 WARN_ON(hba->active_uic_cmd);
932
933 hba->active_uic_cmd = uic_cmd;
934
7a3e97b0 935 /* Write Args */
6ccf44fe
SJ		 936 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
937 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
938 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 939
940 /* Write UIC Cmd */
6ccf44fe 941 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 942 REG_UIC_COMMAND);
7a3e97b0
SY		 943}
944
6ccf44fe
SJ		 945/**
946 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
947 * @hba: per adapter instance
948 * @uic_command: UIC command
949 *
950 * Must be called with mutex held.
951 * Returns 0 only if success.
952 */
953static int
954ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
955{
956 int ret;
957 unsigned long flags;
958
959 if (wait_for_completion_timeout(&uic_cmd->done,
960 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
961 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
962 else
963 ret = -ETIMEDOUT;
964
965 spin_lock_irqsave(hba->host->host_lock, flags);
966 hba->active_uic_cmd = NULL;
967 spin_unlock_irqrestore(hba->host->host_lock, flags);
968
969 return ret;
970}
971
972/**
973 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
974 * @hba: per adapter instance
975 * @uic_cmd: UIC command
976 *
977 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 978 * with mutex held and host_lock locked.
6ccf44fe
SJ		 979 * Returns 0 only if success.
980 */
981static int
982__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
983{
6ccf44fe
SJ		 984 if (!ufshcd_ready_for_uic_cmd(hba)) {
985 dev_err(hba->dev,
986 "Controller not ready to accept UIC commands\n");
987 return -EIO;
988 }
989
990 init_completion(&uic_cmd->done);
991
6ccf44fe 992 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 993
57d104c1 994 return 0;
6ccf44fe
SJ		 995}
996
997/**
998 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
999 * @hba: per adapter instance
1000 * @uic_cmd: UIC command
1001 *
1002 * Returns 0 only if success.
1003 */
1004static int
1005ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1006{
1007 int ret;
57d104c1 1008 unsigned long flags;
6ccf44fe 1009
1ab27c9c 1010 ufshcd_hold(hba, false);
6ccf44fe 1011 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1012 ufshcd_add_delay_before_dme_cmd(hba);
1013
57d104c1 1014 spin_lock_irqsave(hba->host->host_lock, flags);
6ccf44fe 1015 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
57d104c1
SJ		 1016 spin_unlock_irqrestore(hba->host->host_lock, flags);
1017 if (!ret)
1018 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1019
6ccf44fe
SJ		 1020 mutex_unlock(&hba->uic_cmd_mutex);
1021
1ab27c9c 1022 ufshcd_release(hba);
6ccf44fe
SJ		 1023 return ret;
1024}
1025
7a3e97b0
SY		 1026/**
1027 * ufshcd_map_sg - Map scatter-gather list to prdt
1028 * @lrbp - pointer to local reference block
1029 *
1030 * Returns 0 in case of success, non-zero value in case of failure
1031 */
1032static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
1033{
1034 struct ufshcd_sg_entry *prd_table;
1035 struct scatterlist *sg;
1036 struct scsi_cmnd *cmd;
1037 int sg_segments;
1038 int i;
1039
1040 cmd = lrbp->cmd;
1041 sg_segments = scsi_dma_map(cmd);
1042 if (sg_segments < 0)
1043 return sg_segments;
1044
1045 if (sg_segments) {
1046 lrbp->utr_descriptor_ptr->prd_table_length =
1047 cpu_to_le16((u16) (sg_segments));
1048
1049 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1050
1051 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1052 prd_table[i].size =
1053 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1054 prd_table[i].base_addr =
1055 cpu_to_le32(lower_32_bits(sg->dma_address));
1056 prd_table[i].upper_addr =
1057 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1058 prd_table[i].reserved = 0;
7a3e97b0
SY		 1059 }
1060 } else {
1061 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1062 }
1063
1064 return 0;
1065}
1066
1067/**
2fbd009b 1068 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1069 * @hba: per adapter instance
2fbd009b 1070 * @intrs: interrupt bits
7a3e97b0 1071 */
2fbd009b 1072static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1073{
2fbd009b
SJ		 1074 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1075
1076 if (hba->ufs_version == UFSHCI_VERSION_10) {
1077 u32 rw;
1078 rw = set & INTERRUPT_MASK_RW_VER_10;
1079 set = rw | ((set ^ intrs) & intrs);
1080 } else {
1081 set |= intrs;
1082 }
1083
1084 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1085}
1086
1087/**
1088 * ufshcd_disable_intr - disable interrupts
1089 * @hba: per adapter instance
1090 * @intrs: interrupt bits
1091 */
1092static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1093{
1094 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1095
1096 if (hba->ufs_version == UFSHCI_VERSION_10) {
1097 u32 rw;
1098 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1099 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1100 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1101
1102 } else {
1103 set &= ~intrs;
7a3e97b0 1104 }
2fbd009b
SJ		 1105
1106 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1107}
1108
5a0b0cb9
SRT		 1109/**
1110 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1111 * descriptor according to request
1112 * @lrbp: pointer to local reference block
1113 * @upiu_flags: flags required in the header
1114 * @cmd_dir: requests data direction
1115 */
1116static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
1117 u32 *upiu_flags, enum dma_data_direction cmd_dir)
1118{
1119 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1120 u32 data_direction;
1121 u32 dword_0;
1122
1123 if (cmd_dir == DMA_FROM_DEVICE) {
1124 data_direction = UTP_DEVICE_TO_HOST;
1125 *upiu_flags = UPIU_CMD_FLAGS_READ;
1126 } else if (cmd_dir == DMA_TO_DEVICE) {
1127 data_direction = UTP_HOST_TO_DEVICE;
1128 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1129 } else {
1130 data_direction = UTP_NO_DATA_TRANSFER;
1131 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1132 }
1133
1134 dword_0 = data_direction | (lrbp->command_type
1135 << UPIU_COMMAND_TYPE_OFFSET);
1136 if (lrbp->intr_cmd)
1137 dword_0 |= UTP_REQ_DESC_INT_CMD;
1138
1139 /* Transfer request descriptor header fields */
1140 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1141 /* dword_1 is reserved, hence it is set to 0 */
1142 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1143 /*
1144 * assigning invalid value for command status. Controller
1145 * updates OCS on command completion, with the command
1146 * status
1147 */
1148 req_desc->header.dword_2 =
1149 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1150 /* dword_3 is reserved, hence it is set to 0 */
1151 req_desc->header.dword_3 = 0;
51047266
YG		 1152
1153 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1154}
1155
1156/**
1157 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1158 * for scsi commands
1159 * @lrbp - local reference block pointer
1160 * @upiu_flags - flags
1161 */
1162static
1163void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1164{
1165 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1166 unsigned short cdb_len;
5a0b0cb9
SRT		 1167
1168 /* command descriptor fields */
1169 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1170 UPIU_TRANSACTION_COMMAND, upiu_flags,
1171 lrbp->lun, lrbp->task_tag);
1172 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1173 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1174
1175 /* Total EHS length and Data segment length will be zero */
1176 ucd_req_ptr->header.dword_2 = 0;
1177
1178 ucd_req_ptr->sc.exp_data_transfer_len =
1179 cpu_to_be32(lrbp->cmd->sdb.length);
1180
52ac95fe
YG		 1181 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1182 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1183 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1184
1185 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1186}
1187
68078d5c
DR		 1188/**
1189 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1190 * for query requsts
1191 * @hba: UFS hba
1192 * @lrbp: local reference block pointer
1193 * @upiu_flags: flags
1194 */
1195static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1196 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1197{
1198 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1199 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1200 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1201 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1202
1203 /* Query request header */
1204 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1205 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1206 lrbp->lun, lrbp->task_tag);
1207 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1208 0, query->request.query_func, 0, 0);
1209
1210 /* Data segment length */
1211 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1212 0, 0, len >> 8, (u8)len);
1213
1214 /* Copy the Query Request buffer as is */
1215 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1216 QUERY_OSF_SIZE);
68078d5c
DR		 1217
1218 /* Copy the Descriptor */
c6d4a831
DR		 1219 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1220 memcpy(descp, query->descriptor, len);
1221
51047266 1222 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1223}
1224
5a0b0cb9
SRT		 1225static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1226{
1227 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1228
1229 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1230
1231 /* command descriptor fields */
1232 ucd_req_ptr->header.dword_0 =
1233 UPIU_HEADER_DWORD(
1234 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1235 /* clear rest of the fields of basic header */
1236 ucd_req_ptr->header.dword_1 = 0;
1237 ucd_req_ptr->header.dword_2 = 0;
1238
1239 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1240}
1241
7a3e97b0
SY		 1242/**
1243 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 1244 * @hba - per adapter instance
7a3e97b0
SY		 1245 * @lrb - pointer to local reference block
1246 */
5a0b0cb9 1247static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1248{
7a3e97b0 1249 u32 upiu_flags;
5a0b0cb9 1250 int ret = 0;
7a3e97b0
SY		 1251
1252 switch (lrbp->command_type) {
1253 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 1254 if (likely(lrbp->cmd)) {
1255 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1256 lrbp->cmd->sc_data_direction);
1257 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 1258 } else {
5a0b0cb9 1259 ret = -EINVAL;
7a3e97b0 1260 }
7a3e97b0
SY		 1261 break;
1262 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 1263 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 1264 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1265 ufshcd_prepare_utp_query_req_upiu(
1266 hba, lrbp, upiu_flags);
1267 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 1268 ufshcd_prepare_utp_nop_upiu(lrbp);
1269 else
1270 ret = -EINVAL;
7a3e97b0
SY		 1271 break;
1272 case UTP_CMD_TYPE_UFS:
1273 /* For UFS native command implementation */
5a0b0cb9
SRT		 1274 ret = -ENOTSUPP;
1275 dev_err(hba->dev, "%s: UFS native command are not supported\n",
1276 __func__);
1277 break;
1278 default:
1279 ret = -ENOTSUPP;
1280 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
1281 __func__, lrbp->command_type);
7a3e97b0
SY		 1282 break;
1283 } /* end of switch */
5a0b0cb9
SRT		 1284
1285 return ret;
7a3e97b0
SY		 1286}
1287
0ce147d4
SJ		 1288/*
1289 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1290 * @scsi_lun: scsi LUN id
1291 *
1292 * Returns UPIU LUN id
1293 */
1294static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1295{
1296 if (scsi_is_wlun(scsi_lun))
1297 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1298 | UFS_UPIU_WLUN_ID;
1299 else
1300 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1301}
1302
2a8fa600
SJ		 1303/**
1304 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1305 * @scsi_lun: UPIU W-LUN id
1306 *
1307 * Returns SCSI W-LUN id
1308 */
1309static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1310{
1311 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1312}
1313
7a3e97b0
SY		 1314/**
1315 * ufshcd_queuecommand - main entry point for SCSI requests
1316 * @cmd: command from SCSI Midlayer
1317 * @done: call back function
1318 *
1319 * Returns 0 for success, non-zero in case of failure
1320 */
1321static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1322{
1323 struct ufshcd_lrb *lrbp;
1324 struct ufs_hba *hba;
1325 unsigned long flags;
1326 int tag;
1327 int err = 0;
1328
1329 hba = shost_priv(host);
1330
1331 tag = cmd->request->tag;
14497328
YG		 1332 if (!ufshcd_valid_tag(hba, tag)) {
1333 dev_err(hba->dev,
1334 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1335 __func__, tag, cmd, cmd->request);
1336 BUG();
1337 }
7a3e97b0 1338
3441da7d
SRT		 1339 spin_lock_irqsave(hba->host->host_lock, flags);
1340 switch (hba->ufshcd_state) {
1341 case UFSHCD_STATE_OPERATIONAL:
1342 break;
1343 case UFSHCD_STATE_RESET:
7a3e97b0 1344 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1345 goto out_unlock;
1346 case UFSHCD_STATE_ERROR:
1347 set_host_byte(cmd, DID_ERROR);
1348 cmd->scsi_done(cmd);
1349 goto out_unlock;
1350 default:
1351 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1352 __func__, hba->ufshcd_state);
1353 set_host_byte(cmd, DID_BAD_TARGET);
1354 cmd->scsi_done(cmd);
1355 goto out_unlock;
7a3e97b0 1356 }
3441da7d 1357 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1358
5a0b0cb9
SRT		 1359 /* acquire the tag to make sure device cmds don't use it */
1360 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1361 /*
1362 * Dev manage command in progress, requeue the command.
1363 * Requeuing the command helps in cases where the request *may*
1364 * find different tag instead of waiting for dev manage command
1365 * completion.
1366 */
1367 err = SCSI_MLQUEUE_HOST_BUSY;
1368 goto out;
1369 }
1370
1ab27c9c
ST		 1371 err = ufshcd_hold(hba, true);
1372 if (err) {
1373 err = SCSI_MLQUEUE_HOST_BUSY;
1374 clear_bit_unlock(tag, &hba->lrb_in_use);
1375 goto out;
1376 }
1377 WARN_ON(hba->clk_gating.state != CLKS_ON);
1378
7a3e97b0
SY		 1379 lrbp = &hba->lrb[tag];
1380
5a0b0cb9 1381 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 1382 lrbp->cmd = cmd;
1383 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1384 lrbp->sense_buffer = cmd->sense_buffer;
1385 lrbp->task_tag = tag;
0ce147d4 1386 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1387 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0
SY		 1388 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1389
1390 /* form UPIU before issuing the command */
5a0b0cb9 1391 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 1392 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 1393 if (err) {
1394 lrbp->cmd = NULL;
1395 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1396 goto out;
5a0b0cb9 1397 }
7a3e97b0
SY		 1398
1399 /* issue command to the controller */
1400 spin_lock_irqsave(hba->host->host_lock, flags);
1401 ufshcd_send_command(hba, tag);
3441da7d 1402out_unlock:
7a3e97b0
SY		 1403 spin_unlock_irqrestore(hba->host->host_lock, flags);
1404out:
1405 return err;
1406}
1407
5a0b0cb9
SRT		 1408static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1409 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1410{
1411 lrbp->cmd = NULL;
1412 lrbp->sense_bufflen = 0;
1413 lrbp->sense_buffer = NULL;
1414 lrbp->task_tag = tag;
1415 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
1416 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1417 lrbp->intr_cmd = true; /* No interrupt aggregation */
1418 hba->dev_cmd.type = cmd_type;
1419
1420 return ufshcd_compose_upiu(hba, lrbp);
1421}
1422
1423static int
1424ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1425{
1426 int err = 0;
1427 unsigned long flags;
1428 u32 mask = 1 << tag;
1429
1430 /* clear outstanding transaction before retry */
1431 spin_lock_irqsave(hba->host->host_lock, flags);
1432 ufshcd_utrl_clear(hba, tag);
1433 spin_unlock_irqrestore(hba->host->host_lock, flags);
1434
1435 /*
1436 * wait for for h/w to clear corresponding bit in door-bell.
1437 * max. wait is 1 sec.
1438 */
1439 err = ufshcd_wait_for_register(hba,
1440 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1441 mask, ~mask, 1000, 1000);
1442
1443 return err;
1444}
1445
c6d4a831
DR		 1446static int
1447ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1448{
1449 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1450
1451 /* Get the UPIU response */
1452 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1453 UPIU_RSP_CODE_OFFSET;
1454 return query_res->response;
1455}
1456
5a0b0cb9
SRT		 1457/**
1458 * ufshcd_dev_cmd_completion() - handles device management command responses
1459 * @hba: per adapter instance
1460 * @lrbp: pointer to local reference block
1461 */
1462static int
1463ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1464{
1465 int resp;
1466 int err = 0;
1467
1468 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1469
1470 switch (resp) {
1471 case UPIU_TRANSACTION_NOP_IN:
1472 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1473 err = -EINVAL;
1474 dev_err(hba->dev, "%s: unexpected response %x\n",
1475 __func__, resp);
1476 }
1477 break;
68078d5c 1478 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1479 err = ufshcd_check_query_response(hba, lrbp);
1480 if (!err)
1481 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1482 break;
5a0b0cb9
SRT		 1483 case UPIU_TRANSACTION_REJECT_UPIU:
1484 /* TODO: handle Reject UPIU Response */
1485 err = -EPERM;
1486 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1487 __func__);
1488 break;
1489 default:
1490 err = -EINVAL;
1491 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1492 __func__, resp);
1493 break;
1494 }
1495
1496 return err;
1497}
1498
1499static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1500 struct ufshcd_lrb *lrbp, int max_timeout)
1501{
1502 int err = 0;
1503 unsigned long time_left;
1504 unsigned long flags;
1505
1506 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1507 msecs_to_jiffies(max_timeout));
1508
1509 spin_lock_irqsave(hba->host->host_lock, flags);
1510 hba->dev_cmd.complete = NULL;
1511 if (likely(time_left)) {
1512 err = ufshcd_get_tr_ocs(lrbp);
1513 if (!err)
1514 err = ufshcd_dev_cmd_completion(hba, lrbp);
1515 }
1516 spin_unlock_irqrestore(hba->host->host_lock, flags);
1517
1518 if (!time_left) {
1519 err = -ETIMEDOUT;
a48353f6
YG		 1520 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1521 __func__, lrbp->task_tag);
5a0b0cb9 1522 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1523 /* successfully cleared the command, retry if needed */
5a0b0cb9 1524 err = -EAGAIN;
a48353f6
YG		 1525 /*
1526 * in case of an error, after clearing the doorbell,
1527 * we also need to clear the outstanding_request
1528 * field in hba
1529 */
1530 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1531 }
1532
1533 return err;
1534}
1535
1536/**
1537 * ufshcd_get_dev_cmd_tag - Get device management command tag
1538 * @hba: per-adapter instance
1539 * @tag: pointer to variable with available slot value
1540 *
1541 * Get a free slot and lock it until device management command
1542 * completes.
1543 *
1544 * Returns false if free slot is unavailable for locking, else
1545 * return true with tag value in @tag.
1546 */
1547static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1548{
1549 int tag;
1550 bool ret = false;
1551 unsigned long tmp;
1552
1553 if (!tag_out)
1554 goto out;
1555
1556 do {
1557 tmp = ~hba->lrb_in_use;
1558 tag = find_last_bit(&tmp, hba->nutrs);
1559 if (tag >= hba->nutrs)
1560 goto out;
1561 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1562
1563 *tag_out = tag;
1564 ret = true;
1565out:
1566 return ret;
1567}
1568
1569static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1570{
1571 clear_bit_unlock(tag, &hba->lrb_in_use);
1572}
1573
1574/**
1575 * ufshcd_exec_dev_cmd - API for sending device management requests
1576 * @hba - UFS hba
1577 * @cmd_type - specifies the type (NOP, Query...)
1578 * @timeout - time in seconds
1579 *
68078d5c
DR		 1580 * NOTE: Since there is only one available tag for device management commands,
1581 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1582 */
1583static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1584 enum dev_cmd_type cmd_type, int timeout)
1585{
1586 struct ufshcd_lrb *lrbp;
1587 int err;
1588 int tag;
1589 struct completion wait;
1590 unsigned long flags;
1591
1592 /*
1593 * Get free slot, sleep if slots are unavailable.
1594 * Even though we use wait_event() which sleeps indefinitely,
1595 * the maximum wait time is bounded by SCSI request timeout.
1596 */
1597 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1598
1599 init_completion(&wait);
1600 lrbp = &hba->lrb[tag];
1601 WARN_ON(lrbp->cmd);
1602 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1603 if (unlikely(err))
1604 goto out_put_tag;
1605
1606 hba->dev_cmd.complete = &wait;
1607
1608 spin_lock_irqsave(hba->host->host_lock, flags);
1609 ufshcd_send_command(hba, tag);
1610 spin_unlock_irqrestore(hba->host->host_lock, flags);
1611
1612 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1613
1614out_put_tag:
1615 ufshcd_put_dev_cmd_tag(hba, tag);
1616 wake_up(&hba->dev_cmd.tag_wq);
1617 return err;
1618}
1619
d44a5f98
DR		 1620/**
1621 * ufshcd_init_query() - init the query response and request parameters
1622 * @hba: per-adapter instance
1623 * @request: address of the request pointer to be initialized
1624 * @response: address of the response pointer to be initialized
1625 * @opcode: operation to perform
1626 * @idn: flag idn to access
1627 * @index: LU number to access
1628 * @selector: query/flag/descriptor further identification
1629 */
1630static inline void ufshcd_init_query(struct ufs_hba *hba,
1631 struct ufs_query_req **request, struct ufs_query_res **response,
1632 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1633{
1634 *request = &hba->dev_cmd.query.request;
1635 *response = &hba->dev_cmd.query.response;
1636 memset(*request, 0, sizeof(struct ufs_query_req));
1637 memset(*response, 0, sizeof(struct ufs_query_res));
1638 (*request)->upiu_req.opcode = opcode;
1639 (*request)->upiu_req.idn = idn;
1640 (*request)->upiu_req.index = index;
1641 (*request)->upiu_req.selector = selector;
1642}
1643
68078d5c
DR		 1644/**
1645 * ufshcd_query_flag() - API function for sending flag query requests
1646 * hba: per-adapter instance
1647 * query_opcode: flag query to perform
1648 * idn: flag idn to access
1649 * flag_res: the flag value after the query request completes
1650 *
1651 * Returns 0 for success, non-zero in case of failure
1652 */
1653static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1654 enum flag_idn idn, bool *flag_res)
1655{
d44a5f98
DR		 1656 struct ufs_query_req *request = NULL;
1657 struct ufs_query_res *response = NULL;
1658 int err, index = 0, selector = 0;
e5ad406c 1659 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 1660
1661 BUG_ON(!hba);
1662
1ab27c9c 1663 ufshcd_hold(hba, false);
68078d5c 1664 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1665 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1666 selector);
68078d5c
DR		 1667
1668 switch (opcode) {
1669 case UPIU_QUERY_OPCODE_SET_FLAG:
1670 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1671 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1672 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1673 break;
1674 case UPIU_QUERY_OPCODE_READ_FLAG:
1675 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1676 if (!flag_res) {
1677 /* No dummy reads */
1678 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1679 __func__);
1680 err = -EINVAL;
1681 goto out_unlock;
1682 }
1683 break;
1684 default:
1685 dev_err(hba->dev,
1686 "%s: Expected query flag opcode but got = %d\n",
1687 __func__, opcode);
1688 err = -EINVAL;
1689 goto out_unlock;
1690 }
68078d5c 1691
e5ad406c
YG		 1692 if (idn == QUERY_FLAG_IDN_FDEVICEINIT)
1693 timeout = QUERY_FDEVICEINIT_REQ_TIMEOUT;
1694
1695 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 1696
1697 if (err) {
1698 dev_err(hba->dev,
1699 "%s: Sending flag query for idn %d failed, err = %d\n",
1700 __func__, idn, err);
1701 goto out_unlock;
1702 }
1703
1704 if (flag_res)
e8c8e82a 1705 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1706 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1707
1708out_unlock:
1709 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1710 ufshcd_release(hba);
68078d5c
DR		 1711 return err;
1712}
1713
66ec6d59
SRT		 1714/**
1715 * ufshcd_query_attr - API function for sending attribute requests
1716 * hba: per-adapter instance
1717 * opcode: attribute opcode
1718 * idn: attribute idn to access
1719 * index: index field
1720 * selector: selector field
1721 * attr_val: the attribute value after the query request completes
1722 *
1723 * Returns 0 for success, non-zero in case of failure
1724*/
bdbe5d2f 1725static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1726 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1727{
d44a5f98
DR		 1728 struct ufs_query_req *request = NULL;
1729 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1730 int err;
1731
1732 BUG_ON(!hba);
1733
1ab27c9c 1734 ufshcd_hold(hba, false);
66ec6d59
SRT		 1735 if (!attr_val) {
1736 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1737 __func__, opcode);
1738 err = -EINVAL;
1739 goto out;
1740 }
1741
1742 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1743 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1744 selector);
66ec6d59
SRT		 1745
1746 switch (opcode) {
1747 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1748 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1749 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1750 break;
1751 case UPIU_QUERY_OPCODE_READ_ATTR:
1752 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1753 break;
1754 default:
1755 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1756 __func__, opcode);
1757 err = -EINVAL;
1758 goto out_unlock;
1759 }
1760
d44a5f98 1761 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1762
1763 if (err) {
1764 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1765 __func__, opcode, idn, err);
1766 goto out_unlock;
1767 }
1768
e8c8e82a 1769 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1770
1771out_unlock:
1772 mutex_unlock(&hba->dev_cmd.lock);
1773out:
1ab27c9c 1774 ufshcd_release(hba);
66ec6d59
SRT		 1775 return err;
1776}
1777
d44a5f98
DR		 1778/**
1779 * ufshcd_query_descriptor - API function for sending descriptor requests
1780 * hba: per-adapter instance
1781 * opcode: attribute opcode
1782 * idn: attribute idn to access
1783 * index: index field
1784 * selector: selector field
1785 * desc_buf: the buffer that contains the descriptor
1786 * buf_len: length parameter passed to the device
1787 *
1788 * Returns 0 for success, non-zero in case of failure.
1789 * The buf_len parameter will contain, on return, the length parameter
1790 * received on the response.
1791 */
7289f983 1792static int ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1793 enum query_opcode opcode, enum desc_idn idn, u8 index,
1794 u8 selector, u8 *desc_buf, int *buf_len)
1795{
1796 struct ufs_query_req *request = NULL;
1797 struct ufs_query_res *response = NULL;
1798 int err;
1799
1800 BUG_ON(!hba);
1801
1ab27c9c 1802 ufshcd_hold(hba, false);
d44a5f98
DR		 1803 if (!desc_buf) {
1804 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1805 __func__, opcode);
1806 err = -EINVAL;
1807 goto out;
1808 }
1809
1810 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1811 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1812 __func__, *buf_len);
1813 err = -EINVAL;
1814 goto out;
1815 }
1816
1817 mutex_lock(&hba->dev_cmd.lock);
1818 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1819 selector);
1820 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1821 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1822
1823 switch (opcode) {
1824 case UPIU_QUERY_OPCODE_WRITE_DESC:
1825 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1826 break;
1827 case UPIU_QUERY_OPCODE_READ_DESC:
1828 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1829 break;
1830 default:
1831 dev_err(hba->dev,
1832 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1833 __func__, opcode);
1834 err = -EINVAL;
1835 goto out_unlock;
1836 }
1837
1838 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1839
1840 if (err) {
1841 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1842 __func__, opcode, idn, err);
1843 goto out_unlock;
1844 }
1845
1846 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1847 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1848
1849out_unlock:
1850 mutex_unlock(&hba->dev_cmd.lock);
1851out:
1ab27c9c 1852 ufshcd_release(hba);
d44a5f98
DR		 1853 return err;
1854}
1855
da461cec
SJ		 1856/**
1857 * ufshcd_read_desc_param - read the specified descriptor parameter
1858 * @hba: Pointer to adapter instance
1859 * @desc_id: descriptor idn value
1860 * @desc_index: descriptor index
1861 * @param_offset: offset of the parameter to read
1862 * @param_read_buf: pointer to buffer where parameter would be read
1863 * @param_size: sizeof(param_read_buf)
1864 *
1865 * Return 0 in case of success, non-zero otherwise
1866 */
1867static int ufshcd_read_desc_param(struct ufs_hba *hba,
1868 enum desc_idn desc_id,
1869 int desc_index,
1870 u32 param_offset,
1871 u8 *param_read_buf,
1872 u32 param_size)
1873{
1874 int ret;
1875 u8 *desc_buf;
1876 u32 buff_len;
1877 bool is_kmalloc = true;
1878
1879 /* safety checks */
1880 if (desc_id >= QUERY_DESC_IDN_MAX)
1881 return -EINVAL;
1882
1883 buff_len = ufs_query_desc_max_size[desc_id];
1884 if ((param_offset + param_size) > buff_len)
1885 return -EINVAL;
1886
1887 if (!param_offset && (param_size == buff_len)) {
1888 /* memory space already available to hold full descriptor */
1889 desc_buf = param_read_buf;
1890 is_kmalloc = false;
1891 } else {
1892 /* allocate memory to hold full descriptor */
1893 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1894 if (!desc_buf)
1895 return -ENOMEM;
1896 }
1897
1898 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1899 desc_id, desc_index, 0, desc_buf,
1900 &buff_len);
1901
1902 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1903 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1904 ufs_query_desc_max_size[desc_id])
1905 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1906 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1907 __func__, desc_id, param_offset, buff_len, ret);
1908 if (!ret)
1909 ret = -EINVAL;
1910
1911 goto out;
1912 }
1913
1914 if (is_kmalloc)
1915 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1916out:
1917 if (is_kmalloc)
1918 kfree(desc_buf);
1919 return ret;
1920}
1921
1922static inline int ufshcd_read_desc(struct ufs_hba *hba,
1923 enum desc_idn desc_id,
1924 int desc_index,
1925 u8 *buf,
1926 u32 size)
1927{
1928 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1929}
1930
1931static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1932 u8 *buf,
1933 u32 size)
1934{
1935 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1936}
1937
1938/**
1939 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1940 * @hba: Pointer to adapter instance
1941 * @lun: lun id
1942 * @param_offset: offset of the parameter to read
1943 * @param_read_buf: pointer to buffer where parameter would be read
1944 * @param_size: sizeof(param_read_buf)
1945 *
1946 * Return 0 in case of success, non-zero otherwise
1947 */
1948static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1949 int lun,
1950 enum unit_desc_param param_offset,
1951 u8 *param_read_buf,
1952 u32 param_size)
1953{
1954 /*
1955 * Unit descriptors are only available for general purpose LUs (LUN id
1956 * from 0 to 7) and RPMB Well known LU.
1957 */
0ce147d4 1958 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 1959 return -EOPNOTSUPP;
1960
1961 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1962 param_offset, param_read_buf, param_size);
1963}
1964
7a3e97b0
SY		 1965/**
1966 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1967 * @hba: per adapter instance
1968 *
1969 * 1. Allocate DMA memory for Command Descriptor array
1970 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1971 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1972 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1973 * (UTMRDL)
1974 * 4. Allocate memory for local reference block(lrb).
1975 *
1976 * Returns 0 for success, non-zero in case of failure
1977 */
1978static int ufshcd_memory_alloc(struct ufs_hba *hba)
1979{
1980 size_t utmrdl_size, utrdl_size, ucdl_size;
1981
1982 /* Allocate memory for UTP command descriptors */
1983 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1984 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1985 ucdl_size,
1986 &hba->ucdl_dma_addr,
1987 GFP_KERNEL);
7a3e97b0
SY		 1988
1989 /*
1990 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1991 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1992 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1993 * be aligned to 128 bytes as well
1994 */
1995 if (!hba->ucdl_base_addr ||
1996 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1997 dev_err(hba->dev,
7a3e97b0
SY		 1998 "Command Descriptor Memory allocation failed\n");
1999 goto out;
2000 }
2001
2002 /*
2003 * Allocate memory for UTP Transfer descriptors
2004 * UFSHCI requires 1024 byte alignment of UTRD
2005 */
2006 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2007 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2008 utrdl_size,
2009 &hba->utrdl_dma_addr,
2010 GFP_KERNEL);
7a3e97b0
SY		 2011 if (!hba->utrdl_base_addr ||
2012 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2013 dev_err(hba->dev,
7a3e97b0
SY		 2014 "Transfer Descriptor Memory allocation failed\n");
2015 goto out;
2016 }
2017
2018 /*
2019 * Allocate memory for UTP Task Management descriptors
2020 * UFSHCI requires 1024 byte alignment of UTMRD
2021 */
2022 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2023 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2024 utmrdl_size,
2025 &hba->utmrdl_dma_addr,
2026 GFP_KERNEL);
7a3e97b0
SY		 2027 if (!hba->utmrdl_base_addr ||
2028 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2029 dev_err(hba->dev,
7a3e97b0
SY		 2030 "Task Management Descriptor Memory allocation failed\n");
2031 goto out;
2032 }
2033
2034 /* Allocate memory for local reference block */
2953f850
SJ		 2035 hba->lrb = devm_kzalloc(hba->dev,
2036 hba->nutrs * sizeof(struct ufshcd_lrb),
2037 GFP_KERNEL);
7a3e97b0 2038 if (!hba->lrb) {
3b1d0580 2039 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2040 goto out;
2041 }
2042 return 0;
2043out:
7a3e97b0
SY		 2044 return -ENOMEM;
2045}
2046
2047/**
2048 * ufshcd_host_memory_configure - configure local reference block with
2049 * memory offsets
2050 * @hba: per adapter instance
2051 *
2052 * Configure Host memory space
2053 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2054 * address.
2055 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2056 * and PRDT offset.
2057 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2058 * into local reference block.
2059 */
2060static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2061{
2062 struct utp_transfer_cmd_desc *cmd_descp;
2063 struct utp_transfer_req_desc *utrdlp;
2064 dma_addr_t cmd_desc_dma_addr;
2065 dma_addr_t cmd_desc_element_addr;
2066 u16 response_offset;
2067 u16 prdt_offset;
2068 int cmd_desc_size;
2069 int i;
2070
2071 utrdlp = hba->utrdl_base_addr;
2072 cmd_descp = hba->ucdl_base_addr;
2073
2074 response_offset =
2075 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2076 prdt_offset =
2077 offsetof(struct utp_transfer_cmd_desc, prd_table);
2078
2079 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2080 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2081
2082 for (i = 0; i < hba->nutrs; i++) {
2083 /* Configure UTRD with command descriptor base address */
2084 cmd_desc_element_addr =
2085 (cmd_desc_dma_addr + (cmd_desc_size * i));
2086 utrdlp[i].command_desc_base_addr_lo =
2087 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2088 utrdlp[i].command_desc_base_addr_hi =
2089 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2090
2091 /* Response upiu and prdt offset should be in double words */
2092 utrdlp[i].response_upiu_offset =
2093 cpu_to_le16((response_offset >> 2));
2094 utrdlp[i].prd_table_offset =
2095 cpu_to_le16((prdt_offset >> 2));
2096 utrdlp[i].response_upiu_length =
3ca316c5 2097 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 2098
2099 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2100 hba->lrb[i].ucd_req_ptr =
2101 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2102 hba->lrb[i].ucd_rsp_ptr =
2103 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2104 hba->lrb[i].ucd_prdt_ptr =
2105 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2106 }
2107}
2108
2109/**
2110 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2111 * @hba: per adapter instance
2112 *
2113 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2114 * in order to initialize the Unipro link startup procedure.
2115 * Once the Unipro links are up, the device connected to the controller
2116 * is detected.
2117 *
2118 * Returns 0 on success, non-zero value on failure
2119 */
2120static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2121{
6ccf44fe
SJ		 2122 struct uic_command uic_cmd = {0};
2123 int ret;
7a3e97b0 2124
6ccf44fe 2125 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2126
6ccf44fe
SJ		 2127 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2128 if (ret)
2129 dev_err(hba->dev,
2130 "dme-link-startup: error code %d\n", ret);
2131 return ret;
7a3e97b0
SY		 2132}
2133
cad2e03d
YG		 2134static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2135{
2136 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2137 unsigned long min_sleep_time_us;
2138
2139 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2140 return;
2141
2142 /*
2143 * last_dme_cmd_tstamp will be 0 only for 1st call to
2144 * this function
2145 */
2146 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2147 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2148 } else {
2149 unsigned long delta =
2150 (unsigned long) ktime_to_us(
2151 ktime_sub(ktime_get(),
2152 hba->last_dme_cmd_tstamp));
2153
2154 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2155 min_sleep_time_us =
2156 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2157 else
2158 return; /* no more delay required */
2159 }
2160
2161 /* allow sleep for extra 50us if needed */
2162 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2163}
2164
12b4fdb4
SJ		 2165/**
2166 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2167 * @hba: per adapter instance
2168 * @attr_sel: uic command argument1
2169 * @attr_set: attribute set type as uic command argument2
2170 * @mib_val: setting value as uic command argument3
2171 * @peer: indicate whether peer or local
2172 *
2173 * Returns 0 on success, non-zero value on failure
2174 */
2175int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2176 u8 attr_set, u32 mib_val, u8 peer)
2177{
2178 struct uic_command uic_cmd = {0};
2179 static const char *const action[] = {
2180 "dme-set",
2181 "dme-peer-set"
2182 };
2183 const char *set = action[!!peer];
2184 int ret;
2185
2186 uic_cmd.command = peer ?
2187 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2188 uic_cmd.argument1 = attr_sel;
2189 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2190 uic_cmd.argument3 = mib_val;
2191
2192 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2193 if (ret)
2194 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2195 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2196
2197 return ret;
2198}
2199EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2200
2201/**
2202 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2203 * @hba: per adapter instance
2204 * @attr_sel: uic command argument1
2205 * @mib_val: the value of the attribute as returned by the UIC command
2206 * @peer: indicate whether peer or local
2207 *
2208 * Returns 0 on success, non-zero value on failure
2209 */
2210int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2211 u32 *mib_val, u8 peer)
2212{
2213 struct uic_command uic_cmd = {0};
2214 static const char *const action[] = {
2215 "dme-get",
2216 "dme-peer-get"
2217 };
2218 const char *get = action[!!peer];
2219 int ret;
874237f7
YG		 2220 struct ufs_pa_layer_attr orig_pwr_info;
2221 struct ufs_pa_layer_attr temp_pwr_info;
2222 bool pwr_mode_change = false;
2223
2224 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2225 orig_pwr_info = hba->pwr_info;
2226 temp_pwr_info = orig_pwr_info;
2227
2228 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2229 orig_pwr_info.pwr_rx == FAST_MODE) {
2230 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2231 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2232 pwr_mode_change = true;
2233 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2234 orig_pwr_info.pwr_rx == SLOW_MODE) {
2235 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2236 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2237 pwr_mode_change = true;
2238 }
2239 if (pwr_mode_change) {
2240 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2241 if (ret)
2242 goto out;
2243 }
2244 }
12b4fdb4
SJ		 2245
2246 uic_cmd.command = peer ?
2247 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2248 uic_cmd.argument1 = attr_sel;
2249
2250 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2251 if (ret) {
2252 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
2253 get, UIC_GET_ATTR_ID(attr_sel), ret);
2254 goto out;
2255 }
2256
2257 if (mib_val)
2258 *mib_val = uic_cmd.argument3;
874237f7
YG		 2259
2260 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2261 && pwr_mode_change)
2262 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2263out:
2264 return ret;
2265}
2266EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2267
53b3d9c3 2268/**
57d104c1
SJ		 2269 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2270 * state) and waits for it to take effect.
2271 *
53b3d9c3 2272 * @hba: per adapter instance
57d104c1
SJ		 2273 * @cmd: UIC command to execute
2274 *
2275 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2276 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2277 * and device UniPro link and hence it's final completion would be indicated by
2278 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2279 * addition to normal UIC command completion Status (UCCS). This function only
2280 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2281 *
2282 * Returns 0 on success, non-zero value on failure
2283 */
57d104c1 2284static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2285{
57d104c1 2286 struct completion uic_async_done;
53b3d9c3
SJ		 2287 unsigned long flags;
2288 u8 status;
2289 int ret;
2290
53b3d9c3 2291 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2292 init_completion(&uic_async_done);
cad2e03d 2293 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2294
2295 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1
SJ		 2296 hba->uic_async_done = &uic_async_done;
2297 ret = __ufshcd_send_uic_cmd(hba, cmd);
53b3d9c3 2298 spin_unlock_irqrestore(hba->host->host_lock, flags);
53b3d9c3
SJ		 2299 if (ret) {
2300 dev_err(hba->dev,
57d104c1
SJ		 2301 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2302 cmd->command, cmd->argument3, ret);
2303 goto out;
2304 }
2305 ret = ufshcd_wait_for_uic_cmd(hba, cmd);
2306 if (ret) {
2307 dev_err(hba->dev,
2308 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2309 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2310 goto out;
2311 }
2312
57d104c1 2313 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2314 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2315 dev_err(hba->dev,
57d104c1
SJ		 2316 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2317 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2318 ret = -ETIMEDOUT;
2319 goto out;
2320 }
2321
2322 status = ufshcd_get_upmcrs(hba);
2323 if (status != PWR_LOCAL) {
2324 dev_err(hba->dev,
57d104c1
SJ		 2325 "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
2326 cmd->command, status);
53b3d9c3
SJ		 2327 ret = (status != PWR_OK) ? status : -1;
2328 }
2329out:
2330 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2331 hba->uic_async_done = NULL;
53b3d9c3
SJ		 2332 spin_unlock_irqrestore(hba->host->host_lock, flags);
2333 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2334
53b3d9c3
SJ		 2335 return ret;
2336}
2337
57d104c1
SJ		 2338/**
2339 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2340 * using DME_SET primitives.
2341 * @hba: per adapter instance
2342 * @mode: powr mode value
2343 *
2344 * Returns 0 on success, non-zero value on failure
2345 */
2346static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2347{
2348 struct uic_command uic_cmd = {0};
1ab27c9c 2349 int ret;
57d104c1 2350
c3a2f9ee
YG		 2351 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2352 ret = ufshcd_dme_set(hba,
2353 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2354 if (ret) {
2355 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2356 __func__, ret);
2357 goto out;
2358 }
2359 }
2360
57d104c1
SJ		 2361 uic_cmd.command = UIC_CMD_DME_SET;
2362 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2363 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2364 ufshcd_hold(hba, false);
2365 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2366 ufshcd_release(hba);
57d104c1 2367
c3a2f9ee 2368out:
1ab27c9c 2369 return ret;
57d104c1
SJ		 2370}
2371
2372static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2373{
2374 struct uic_command uic_cmd = {0};
2375
2376 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
2377
2378 return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2379}
2380
2381static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2382{
2383 struct uic_command uic_cmd = {0};
2384 int ret;
2385
2386 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2387 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2388 if (ret) {
2389 ufshcd_set_link_off(hba);
2390 ret = ufshcd_host_reset_and_restore(hba);
2391 }
2392
2393 return ret;
2394}
2395
5064636c
YG		 2396 /**
2397 * ufshcd_init_pwr_info - setting the POR (power on reset)
2398 * values in hba power info
2399 * @hba: per-adapter instance
2400 */
2401static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2402{
2403 hba->pwr_info.gear_rx = UFS_PWM_G1;
2404 hba->pwr_info.gear_tx = UFS_PWM_G1;
2405 hba->pwr_info.lane_rx = 1;
2406 hba->pwr_info.lane_tx = 1;
2407 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2408 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2409 hba->pwr_info.hs_rate = 0;
2410}
2411
d3e89bac 2412/**
7eb584db
DR		 2413 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2414 * @hba: per-adapter instance
d3e89bac 2415 */
7eb584db 2416static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2417{
7eb584db
DR		 2418 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2419
2420 if (hba->max_pwr_info.is_valid)
2421 return 0;
2422
2423 pwr_info->pwr_tx = FASTAUTO_MODE;
2424 pwr_info->pwr_rx = FASTAUTO_MODE;
2425 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2426
2427 /* Get the connected lane count */
7eb584db
DR		 2428 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2429 &pwr_info->lane_rx);
2430 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2431 &pwr_info->lane_tx);
2432
2433 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2434 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2435 __func__,
2436 pwr_info->lane_rx,
2437 pwr_info->lane_tx);
2438 return -EINVAL;
2439 }
d3e89bac
SJ		 2440
2441 /*
2442 * First, get the maximum gears of HS speed.
2443 * If a zero value, it means there is no HSGEAR capability.
2444 * Then, get the maximum gears of PWM speed.
2445 */
7eb584db
DR		 2446 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2447 if (!pwr_info->gear_rx) {
2448 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2449 &pwr_info->gear_rx);
2450 if (!pwr_info->gear_rx) {
2451 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2452 __func__, pwr_info->gear_rx);
2453 return -EINVAL;
2454 }
2455 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2456 }
2457
7eb584db
DR		 2458 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2459 &pwr_info->gear_tx);
2460 if (!pwr_info->gear_tx) {
d3e89bac 2461 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2462 &pwr_info->gear_tx);
2463 if (!pwr_info->gear_tx) {
2464 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2465 __func__, pwr_info->gear_tx);
2466 return -EINVAL;
2467 }
2468 pwr_info->pwr_tx = SLOWAUTO_MODE;
2469 }
2470
2471 hba->max_pwr_info.is_valid = true;
2472 return 0;
2473}
2474
2475static int ufshcd_change_power_mode(struct ufs_hba *hba,
2476 struct ufs_pa_layer_attr *pwr_mode)
2477{
2478 int ret;
2479
2480 /* if already configured to the requested pwr_mode */
2481 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2482 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2483 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2484 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2485 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2486 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2487 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2488 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2489 return 0;
d3e89bac
SJ		 2490 }
2491
2492 /*
2493 * Configure attributes for power mode change with below.
2494 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2495 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2496 * - PA_HSSERIES
2497 */
7eb584db
DR		 2498 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2499 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2500 pwr_mode->lane_rx);
2501 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2502 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2503 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2504 else
2505 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2506
7eb584db
DR		 2507 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2508 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2509 pwr_mode->lane_tx);
2510 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2511 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2512 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2513 else
2514 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2515
7eb584db
DR		 2516 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2517 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2518 pwr_mode->pwr_rx == FAST_MODE ||
2519 pwr_mode->pwr_tx == FAST_MODE)
2520 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2521 pwr_mode->hs_rate);
d3e89bac 2522
7eb584db
DR		 2523 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2524 | pwr_mode->pwr_tx);
2525
2526 if (ret) {
d3e89bac 2527 dev_err(hba->dev,
7eb584db
DR		 2528 "%s: power mode change failed %d\n", __func__, ret);
2529 } else {
0263bcd0
YG		 2530 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2531 pwr_mode);
7eb584db
DR		 2532
2533 memcpy(&hba->pwr_info, pwr_mode,
2534 sizeof(struct ufs_pa_layer_attr));
2535 }
2536
2537 return ret;
2538}
2539
2540/**
2541 * ufshcd_config_pwr_mode - configure a new power mode
2542 * @hba: per-adapter instance
2543 * @desired_pwr_mode: desired power configuration
2544 */
2545static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2546 struct ufs_pa_layer_attr *desired_pwr_mode)
2547{
2548 struct ufs_pa_layer_attr final_params = { 0 };
2549 int ret;
2550
0263bcd0
YG		 2551 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2552 desired_pwr_mode, &final_params);
2553
2554 if (ret)
7eb584db
DR		 2555 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2556
2557 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2558
2559 return ret;
2560}
2561
68078d5c
DR		 2562/**
2563 * ufshcd_complete_dev_init() - checks device readiness
2564 * hba: per-adapter instance
2565 *
2566 * Set fDeviceInit flag and poll until device toggles it.
2567 */
2568static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2569{
2570 int i, retries, err = 0;
2571 bool flag_res = 1;
2572
2573 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2574 /* Set the fDeviceInit flag */
2575 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2576 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
2577 if (!err || err == -ETIMEDOUT)
2578 break;
2579 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2580 }
2581 if (err) {
2582 dev_err(hba->dev,
2583 "%s setting fDeviceInit flag failed with error %d\n",
2584 __func__, err);
2585 goto out;
2586 }
2587
2588 /* poll for max. 100 iterations for fDeviceInit flag to clear */
2589 for (i = 0; i < 100 && !err && flag_res; i++) {
2590 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2591 err = ufshcd_query_flag(hba,
2592 UPIU_QUERY_OPCODE_READ_FLAG,
2593 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2594 if (!err || err == -ETIMEDOUT)
2595 break;
2596 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
2597 err);
2598 }
2599 }
2600 if (err)
2601 dev_err(hba->dev,
2602 "%s reading fDeviceInit flag failed with error %d\n",
2603 __func__, err);
2604 else if (flag_res)
2605 dev_err(hba->dev,
2606 "%s fDeviceInit was not cleared by the device\n",
2607 __func__);
2608
2609out:
2610 return err;
2611}
2612
7a3e97b0
SY		 2613/**
2614 * ufshcd_make_hba_operational - Make UFS controller operational
2615 * @hba: per adapter instance
2616 *
2617 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2618 * 1. Enable required interrupts
2619 * 2. Configure interrupt aggregation
2620 * 3. Program UTRL and UTMRL base addres
2621 * 4. Configure run-stop-registers
7a3e97b0
SY		 2622 *
2623 * Returns 0 on success, non-zero value on failure
2624 */
2625static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2626{
2627 int err = 0;
2628 u32 reg;
2629
6ccf44fe
SJ		 2630 /* Enable required interrupts */
2631 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2632
2633 /* Configure interrupt aggregation */
b852190e
YG		 2634 if (ufshcd_is_intr_aggr_allowed(hba))
2635 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
2636 else
2637 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 2638
2639 /* Configure UTRL and UTMRL base address registers */
2640 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2641 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2642 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2643 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2644 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2645 REG_UTP_TASK_REQ_LIST_BASE_L);
2646 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2647 REG_UTP_TASK_REQ_LIST_BASE_H);
2648
7a3e97b0
SY		 2649 /*
2650 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
2651 * DEI, HEI bits must be 0
2652 */
5c0c28a8 2653 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 2654 if (!(ufshcd_get_lists_status(reg))) {
2655 ufshcd_enable_run_stop_reg(hba);
2656 } else {
3b1d0580 2657 dev_err(hba->dev,
7a3e97b0
SY		 2658 "Host controller not ready to process requests");
2659 err = -EIO;
2660 goto out;
2661 }
2662
7a3e97b0
SY		 2663out:
2664 return err;
2665}
2666
2667/**
2668 * ufshcd_hba_enable - initialize the controller
2669 * @hba: per adapter instance
2670 *
2671 * The controller resets itself and controller firmware initialization
2672 * sequence kicks off. When controller is ready it will set
2673 * the Host Controller Enable bit to 1.
2674 *
2675 * Returns 0 on success, non-zero value on failure
2676 */
2677static int ufshcd_hba_enable(struct ufs_hba *hba)
2678{
2679 int retry;
2680
2681 /*
2682 * msleep of 1 and 5 used in this function might result in msleep(20),
2683 * but it was necessary to send the UFS FPGA to reset mode during
2684 * development and testing of this driver. msleep can be changed to
2685 * mdelay and retry count can be reduced based on the controller.
2686 */
2687 if (!ufshcd_is_hba_active(hba)) {
2688
2689 /* change controller state to "reset state" */
2690 ufshcd_hba_stop(hba);
2691
2692 /*
2693 * This delay is based on the testing done with UFS host
2694 * controller FPGA. The delay can be changed based on the
2695 * host controller used.
2696 */
2697 msleep(5);
2698 }
2699
57d104c1
SJ		 2700 /* UniPro link is disabled at this point */
2701 ufshcd_set_link_off(hba);
2702
0263bcd0 2703 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 2704
7a3e97b0
SY		 2705 /* start controller initialization sequence */
2706 ufshcd_hba_start(hba);
2707
2708 /*
2709 * To initialize a UFS host controller HCE bit must be set to 1.
2710 * During initialization the HCE bit value changes from 1->0->1.
2711 * When the host controller completes initialization sequence
2712 * it sets the value of HCE bit to 1. The same HCE bit is read back
2713 * to check if the controller has completed initialization sequence.
2714 * So without this delay the value HCE = 1, set in the previous
2715 * instruction might be read back.
2716 * This delay can be changed based on the controller.
2717 */
2718 msleep(1);
2719
2720 /* wait for the host controller to complete initialization */
2721 retry = 10;
2722 while (ufshcd_is_hba_active(hba)) {
2723 if (retry) {
2724 retry--;
2725 } else {
3b1d0580 2726 dev_err(hba->dev,
7a3e97b0
SY		 2727 "Controller enable failed\n");
2728 return -EIO;
2729 }
2730 msleep(5);
2731 }
5c0c28a8 2732
1d337ec2 2733 /* enable UIC related interrupts */
57d104c1 2734 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 2735
0263bcd0 2736 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 2737
7a3e97b0
SY		 2738 return 0;
2739}
2740
7ca38cf3
YG		 2741static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
2742{
2743 int tx_lanes, i, err = 0;
2744
2745 if (!peer)
2746 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2747 &tx_lanes);
2748 else
2749 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2750 &tx_lanes);
2751 for (i = 0; i < tx_lanes; i++) {
2752 if (!peer)
2753 err = ufshcd_dme_set(hba,
2754 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
2755 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
2756 0);
2757 else
2758 err = ufshcd_dme_peer_set(hba,
2759 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
2760 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
2761 0);
2762 if (err) {
2763 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
2764 __func__, peer, i, err);
2765 break;
2766 }
2767 }
2768
2769 return err;
2770}
2771
2772static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
2773{
2774 return ufshcd_disable_tx_lcc(hba, true);
2775}
2776
7a3e97b0 2777/**
6ccf44fe 2778 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 2779 * @hba: per adapter instance
2780 *
6ccf44fe 2781 * Returns 0 for success, non-zero in case of failure
7a3e97b0 2782 */
6ccf44fe 2783static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 2784{
6ccf44fe 2785 int ret;
1d337ec2 2786 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 2787
1d337ec2 2788 do {
0263bcd0 2789 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 2790
1d337ec2 2791 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 2792
1d337ec2
SRT		 2793 /* check if device is detected by inter-connect layer */
2794 if (!ret && !ufshcd_is_device_present(hba)) {
2795 dev_err(hba->dev, "%s: Device not present\n", __func__);
2796 ret = -ENXIO;
2797 goto out;
2798 }
6ccf44fe 2799
1d337ec2
SRT		 2800 /*
2801 * DME link lost indication is only received when link is up,
2802 * but we can't be sure if the link is up until link startup
2803 * succeeds. So reset the local Uni-Pro and try again.
2804 */
2805 if (ret && ufshcd_hba_enable(hba))
2806 goto out;
2807 } while (ret && retries--);
2808
2809 if (ret)
2810 /* failed to get the link up... retire */
5c0c28a8 2811 goto out;
5c0c28a8 2812
7ca38cf3
YG		 2813 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
2814 ret = ufshcd_disable_device_tx_lcc(hba);
2815 if (ret)
2816 goto out;
2817 }
2818
5c0c28a8 2819 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 2820 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
2821 if (ret)
2822 goto out;
7a3e97b0 2823
5c0c28a8 2824 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 2825out:
2826 if (ret)
2827 dev_err(hba->dev, "link startup failed %d\n", ret);
2828 return ret;
7a3e97b0
SY		 2829}
2830
5a0b0cb9
SRT		 2831/**
2832 * ufshcd_verify_dev_init() - Verify device initialization
2833 * @hba: per-adapter instance
2834 *
2835 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2836 * device Transport Protocol (UTP) layer is ready after a reset.
2837 * If the UTP layer at the device side is not initialized, it may
2838 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2839 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2840 */
2841static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2842{
2843 int err = 0;
2844 int retries;
2845
1ab27c9c 2846 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 2847 mutex_lock(&hba->dev_cmd.lock);
2848 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2849 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2850 NOP_OUT_TIMEOUT);
2851
2852 if (!err || err == -ETIMEDOUT)
2853 break;
2854
2855 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2856 }
2857 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2858 ufshcd_release(hba);
5a0b0cb9
SRT		 2859
2860 if (err)
2861 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2862 return err;
2863}
2864
0ce147d4
SJ		 2865/**
2866 * ufshcd_set_queue_depth - set lun queue depth
2867 * @sdev: pointer to SCSI device
2868 *
2869 * Read bLUQueueDepth value and activate scsi tagged command
2870 * queueing. For WLUN, queue depth is set to 1. For best-effort
2871 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
2872 * value that host can queue.
2873 */
2874static void ufshcd_set_queue_depth(struct scsi_device *sdev)
2875{
2876 int ret = 0;
2877 u8 lun_qdepth;
2878 struct ufs_hba *hba;
2879
2880 hba = shost_priv(sdev->host);
2881
2882 lun_qdepth = hba->nutrs;
2883 ret = ufshcd_read_unit_desc_param(hba,
2884 ufshcd_scsi_to_upiu_lun(sdev->lun),
2885 UNIT_DESC_PARAM_LU_Q_DEPTH,
2886 &lun_qdepth,
2887 sizeof(lun_qdepth));
2888
2889 /* Some WLUN doesn't support unit descriptor */
2890 if (ret == -EOPNOTSUPP)
2891 lun_qdepth = 1;
2892 else if (!lun_qdepth)
2893 /* eventually, we can figure out the real queue depth */
2894 lun_qdepth = hba->nutrs;
2895 else
2896 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
2897
2898 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2899 __func__, lun_qdepth);
db5ed4df 2900 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 2901}
2902
57d104c1
SJ		 2903/*
2904 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
2905 * @hba: per-adapter instance
2906 * @lun: UFS device lun id
2907 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
2908 *
2909 * Returns 0 in case of success and b_lu_write_protect status would be returned
2910 * @b_lu_write_protect parameter.
2911 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
2912 * Returns -EINVAL in case of invalid parameters passed to this function.
2913 */
2914static int ufshcd_get_lu_wp(struct ufs_hba *hba,
2915 u8 lun,
2916 u8 *b_lu_write_protect)
2917{
2918 int ret;
2919
2920 if (!b_lu_write_protect)
2921 ret = -EINVAL;
2922 /*
2923 * According to UFS device spec, RPMB LU can't be write
2924 * protected so skip reading bLUWriteProtect parameter for
2925 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
2926 */
2927 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
2928 ret = -ENOTSUPP;
2929 else
2930 ret = ufshcd_read_unit_desc_param(hba,
2931 lun,
2932 UNIT_DESC_PARAM_LU_WR_PROTECT,
2933 b_lu_write_protect,
2934 sizeof(*b_lu_write_protect));
2935 return ret;
2936}
2937
2938/**
2939 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
2940 * status
2941 * @hba: per-adapter instance
2942 * @sdev: pointer to SCSI device
2943 *
2944 */
2945static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
2946 struct scsi_device *sdev)
2947{
2948 if (hba->dev_info.f_power_on_wp_en &&
2949 !hba->dev_info.is_lu_power_on_wp) {
2950 u8 b_lu_write_protect;
2951
2952 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
2953 &b_lu_write_protect) &&
2954 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
2955 hba->dev_info.is_lu_power_on_wp = true;
2956 }
2957}
2958
7a3e97b0
SY		 2959/**
2960 * ufshcd_slave_alloc - handle initial SCSI device configurations
2961 * @sdev: pointer to SCSI device
2962 *
2963 * Returns success
2964 */
2965static int ufshcd_slave_alloc(struct scsi_device *sdev)
2966{
2967 struct ufs_hba *hba;
2968
2969 hba = shost_priv(sdev->host);
7a3e97b0
SY		 2970
2971 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2972 sdev->use_10_for_ms = 1;
7a3e97b0 2973
e8e7f271
SRT		 2974 /* allow SCSI layer to restart the device in case of errors */
2975 sdev->allow_restart = 1;
4264fd61 2976
b2a6c522
SRT		 2977 /* REPORT SUPPORTED OPERATION CODES is not supported */
2978 sdev->no_report_opcodes = 1;
2979
e8e7f271 2980
0ce147d4 2981 ufshcd_set_queue_depth(sdev);
4264fd61 2982
57d104c1
SJ		 2983 ufshcd_get_lu_power_on_wp_status(hba, sdev);
2984
7a3e97b0
SY		 2985 return 0;
2986}
2987
4264fd61
SRT		 2988/**
2989 * ufshcd_change_queue_depth - change queue depth
2990 * @sdev: pointer to SCSI device
2991 * @depth: required depth to set
4264fd61 2992 *
db5ed4df 2993 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 2994 */
db5ed4df 2995static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 2996{
2997 struct ufs_hba *hba = shost_priv(sdev->host);
2998
2999 if (depth > hba->nutrs)
3000 depth = hba->nutrs;
db5ed4df 3001 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3002}
3003
eeda4749
AM		 3004/**
3005 * ufshcd_slave_configure - adjust SCSI device configurations
3006 * @sdev: pointer to SCSI device
3007 */
3008static int ufshcd_slave_configure(struct scsi_device *sdev)
3009{
3010 struct request_queue *q = sdev->request_queue;
3011
3012 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3013 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3014
3015 return 0;
3016}
3017
7a3e97b0
SY		 3018/**
3019 * ufshcd_slave_destroy - remove SCSI device configurations
3020 * @sdev: pointer to SCSI device
3021 */
3022static void ufshcd_slave_destroy(struct scsi_device *sdev)
3023{
3024 struct ufs_hba *hba;
3025
3026 hba = shost_priv(sdev->host);
0ce147d4 3027 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3028 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3029 unsigned long flags;
3030
3031 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3032 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3033 spin_unlock_irqrestore(hba->host->host_lock, flags);
3034 }
7a3e97b0
SY		 3035}
3036
3037/**
3038 * ufshcd_task_req_compl - handle task management request completion
3039 * @hba: per adapter instance
3040 * @index: index of the completed request
e2933132 3041 * @resp: task management service response
7a3e97b0 3042 *
e2933132 3043 * Returns non-zero value on error, zero on success
7a3e97b0 3044 */
e2933132 3045static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3046{
3047 struct utp_task_req_desc *task_req_descp;
3048 struct utp_upiu_task_rsp *task_rsp_upiup;
3049 unsigned long flags;
3050 int ocs_value;
3051 int task_result;
3052
3053 spin_lock_irqsave(hba->host->host_lock, flags);
3054
3055 /* Clear completed tasks from outstanding_tasks */
3056 __clear_bit(index, &hba->outstanding_tasks);
3057
3058 task_req_descp = hba->utmrdl_base_addr;
3059 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3060
3061 if (ocs_value == OCS_SUCCESS) {
3062 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3063 task_req_descp[index].task_rsp_upiu;
3064 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
3065 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 3066 if (resp)
3067 *resp = (u8)task_result;
7a3e97b0 3068 } else {
e2933132
SRT		 3069 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3070 __func__, ocs_value);
7a3e97b0
SY		 3071 }
3072 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3073
3074 return ocs_value;
7a3e97b0
SY		 3075}
3076
7a3e97b0
SY		 3077/**
3078 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3079 * @lrb: pointer to local reference block of completed command
3080 * @scsi_status: SCSI command status
3081 *
3082 * Returns value base on SCSI command status
3083 */
3084static inline int
3085ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3086{
3087 int result = 0;
3088
3089 switch (scsi_status) {
7a3e97b0 3090 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3091 ufshcd_copy_sense_data(lrbp);
3092 case SAM_STAT_GOOD:
7a3e97b0
SY		 3093 result |= DID_OK << 16 |
3094 COMMAND_COMPLETE << 8 |
1c2623c5 3095 scsi_status;
7a3e97b0
SY		 3096 break;
3097 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3098 case SAM_STAT_BUSY:
7a3e97b0 3099 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3100 ufshcd_copy_sense_data(lrbp);
3101 result |= scsi_status;
7a3e97b0
SY		 3102 break;
3103 default:
3104 result |= DID_ERROR << 16;
3105 break;
3106 } /* end of switch */
3107
3108 return result;
3109}
3110
3111/**
3112 * ufshcd_transfer_rsp_status - Get overall status of the response
3113 * @hba: per adapter instance
3114 * @lrb: pointer to local reference block of completed command
3115 *
3116 * Returns result of the command to notify SCSI midlayer
3117 */
3118static inline int
3119ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3120{
3121 int result = 0;
3122 int scsi_status;
3123 int ocs;
3124
3125 /* overall command status of utrd */
3126 ocs = ufshcd_get_tr_ocs(lrbp);
3127
3128 switch (ocs) {
3129 case OCS_SUCCESS:
5a0b0cb9 3130 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3131
5a0b0cb9
SRT		 3132 switch (result) {
3133 case UPIU_TRANSACTION_RESPONSE:
3134 /*
3135 * get the response UPIU result to extract
3136 * the SCSI command status
3137 */
3138 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3139
3140 /*
3141 * get the result based on SCSI status response
3142 * to notify the SCSI midlayer of the command status
3143 */
3144 scsi_status = result & MASK_SCSI_STATUS;
3145 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3146
f05ac2e5
YG		 3147 /*
3148 * Currently we are only supporting BKOPs exception
3149 * events hence we can ignore BKOPs exception event
3150 * during power management callbacks. BKOPs exception
3151 * event is not expected to be raised in runtime suspend
3152 * callback as it allows the urgent bkops.
3153 * During system suspend, we are anyway forcefully
3154 * disabling the bkops and if urgent bkops is needed
3155 * it will be enabled on system resume. Long term
3156 * solution could be to abort the system suspend if
3157 * UFS device needs urgent BKOPs.
3158 */
3159 if (!hba->pm_op_in_progress &&
3160 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3161 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3162 break;
3163 case UPIU_TRANSACTION_REJECT_UPIU:
3164 /* TODO: handle Reject UPIU Response */
3165 result = DID_ERROR << 16;
3b1d0580 3166 dev_err(hba->dev,
5a0b0cb9
SRT		 3167 "Reject UPIU not fully implemented\n");
3168 break;
3169 default:
3170 result = DID_ERROR << 16;
3171 dev_err(hba->dev,
3172 "Unexpected request response code = %x\n",
3173 result);
7a3e97b0
SY		 3174 break;
3175 }
7a3e97b0
SY		 3176 break;
3177 case OCS_ABORTED:
3178 result |= DID_ABORT << 16;
3179 break;
e8e7f271
SRT		 3180 case OCS_INVALID_COMMAND_STATUS:
3181 result |= DID_REQUEUE << 16;
3182 break;
7a3e97b0
SY		 3183 case OCS_INVALID_CMD_TABLE_ATTR:
3184 case OCS_INVALID_PRDT_ATTR:
3185 case OCS_MISMATCH_DATA_BUF_SIZE:
3186 case OCS_MISMATCH_RESP_UPIU_SIZE:
3187 case OCS_PEER_COMM_FAILURE:
3188 case OCS_FATAL_ERROR:
3189 default:
3190 result |= DID_ERROR << 16;
3b1d0580 3191 dev_err(hba->dev,
7a3e97b0
SY		 3192 "OCS error from controller = %x\n", ocs);
3193 break;
3194 } /* end of switch */
3195
3196 return result;
3197}
3198
6ccf44fe
SJ		 3199/**
3200 * ufshcd_uic_cmd_compl - handle completion of uic command
3201 * @hba: per adapter instance
53b3d9c3 3202 * @intr_status: interrupt status generated by the controller
6ccf44fe 3203 */
53b3d9c3 3204static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3205{
53b3d9c3 3206 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3207 hba->active_uic_cmd->argument2 |=
3208 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3209 hba->active_uic_cmd->argument3 =
3210 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3211 complete(&hba->active_uic_cmd->done);
3212 }
53b3d9c3 3213
57d104c1
SJ		 3214 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3215 complete(hba->uic_async_done);
6ccf44fe
SJ		 3216}
3217
7a3e97b0
SY		 3218/**
3219 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3220 * @hba: per adapter instance
3221 */
3222static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3223{
5a0b0cb9
SRT		 3224 struct ufshcd_lrb *lrbp;
3225 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3226 unsigned long completed_reqs;
3227 u32 tr_doorbell;
3228 int result;
3229 int index;
e9d501b1
DR		 3230
3231 /* Resetting interrupt aggregation counters first and reading the
3232 * DOOR_BELL afterward allows us to handle all the completed requests.
3233 * In order to prevent other interrupts starvation the DB is read once
3234 * after reset. The down side of this solution is the possibility of
3235 * false interrupt if device completes another request after resetting
3236 * aggregation and before reading the DB.
3237 */
b852190e
YG		 3238 if (ufshcd_is_intr_aggr_allowed(hba))
3239 ufshcd_reset_intr_aggr(hba);
7a3e97b0 3240
b873a275 3241 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 3242 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3243
e9d501b1
DR		 3244 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3245 lrbp = &hba->lrb[index];
3246 cmd = lrbp->cmd;
3247 if (cmd) {
3248 result = ufshcd_transfer_rsp_status(hba, lrbp);
3249 scsi_dma_unmap(cmd);
3250 cmd->result = result;
3251 /* Mark completed command as NULL in LRB */
3252 lrbp->cmd = NULL;
3253 clear_bit_unlock(index, &hba->lrb_in_use);
3254 /* Do not touch lrbp after scsi done */
3255 cmd->scsi_done(cmd);
1ab27c9c 3256 __ufshcd_release(hba);
e9d501b1
DR		 3257 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
3258 if (hba->dev_cmd.complete)
3259 complete(hba->dev_cmd.complete);
3260 }
3261 }
7a3e97b0
SY		 3262
3263 /* clear corresponding bits of completed commands */
3264 hba->outstanding_reqs ^= completed_reqs;
3265
856b3483
ST		 3266 ufshcd_clk_scaling_update_busy(hba);
3267
5a0b0cb9
SRT		 3268 /* we might have free'd some tags above */
3269 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3270}
3271
66ec6d59
SRT		 3272/**
3273 * ufshcd_disable_ee - disable exception event
3274 * @hba: per-adapter instance
3275 * @mask: exception event to disable
3276 *
3277 * Disables exception event in the device so that the EVENT_ALERT
3278 * bit is not set.
3279 *
3280 * Returns zero on success, non-zero error value on failure.
3281 */
3282static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3283{
3284 int err = 0;
3285 u32 val;
3286
3287 if (!(hba->ee_ctrl_mask & mask))
3288 goto out;
3289
3290 val = hba->ee_ctrl_mask & ~mask;
3291 val &= 0xFFFF; /* 2 bytes */
3292 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3293 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3294 if (!err)
3295 hba->ee_ctrl_mask &= ~mask;
3296out:
3297 return err;
3298}
3299
3300/**
3301 * ufshcd_enable_ee - enable exception event
3302 * @hba: per-adapter instance
3303 * @mask: exception event to enable
3304 *
3305 * Enable corresponding exception event in the device to allow
3306 * device to alert host in critical scenarios.
3307 *
3308 * Returns zero on success, non-zero error value on failure.
3309 */
3310static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3311{
3312 int err = 0;
3313 u32 val;
3314
3315 if (hba->ee_ctrl_mask & mask)
3316 goto out;
3317
3318 val = hba->ee_ctrl_mask | mask;
3319 val &= 0xFFFF; /* 2 bytes */
3320 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3321 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3322 if (!err)
3323 hba->ee_ctrl_mask |= mask;
3324out:
3325 return err;
3326}
3327
3328/**
3329 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3330 * @hba: per-adapter instance
3331 *
3332 * Allow device to manage background operations on its own. Enabling
3333 * this might lead to inconsistent latencies during normal data transfers
3334 * as the device is allowed to manage its own way of handling background
3335 * operations.
3336 *
3337 * Returns zero on success, non-zero on failure.
3338 */
3339static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3340{
3341 int err = 0;
3342
3343 if (hba->auto_bkops_enabled)
3344 goto out;
3345
3346 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3347 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3348 if (err) {
3349 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3350 __func__, err);
3351 goto out;
3352 }
3353
3354 hba->auto_bkops_enabled = true;
3355
3356 /* No need of URGENT_BKOPS exception from the device */
3357 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3358 if (err)
3359 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3360 __func__, err);
3361out:
3362 return err;
3363}
3364
3365/**
3366 * ufshcd_disable_auto_bkops - block device in doing background operations
3367 * @hba: per-adapter instance
3368 *
3369 * Disabling background operations improves command response latency but
3370 * has drawback of device moving into critical state where the device is
3371 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3372 * host is idle so that BKOPS are managed effectively without any negative
3373 * impacts.
3374 *
3375 * Returns zero on success, non-zero on failure.
3376 */
3377static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3378{
3379 int err = 0;
3380
3381 if (!hba->auto_bkops_enabled)
3382 goto out;
3383
3384 /*
3385 * If host assisted BKOPs is to be enabled, make sure
3386 * urgent bkops exception is allowed.
3387 */
3388 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3389 if (err) {
3390 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3391 __func__, err);
3392 goto out;
3393 }
3394
3395 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
3396 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3397 if (err) {
3398 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3399 __func__, err);
3400 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3401 goto out;
3402 }
3403
3404 hba->auto_bkops_enabled = false;
3405out:
3406 return err;
3407}
3408
3409/**
3410 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3411 * @hba: per adapter instance
3412 *
3413 * After a device reset the device may toggle the BKOPS_EN flag
3414 * to default value. The s/w tracking variables should be updated
3415 * as well. Do this by forcing enable of auto bkops.
3416 */
3417static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3418{
3419 hba->auto_bkops_enabled = false;
3420 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3421 ufshcd_enable_auto_bkops(hba);
3422}
3423
3424static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3425{
3426 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3427 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3428}
3429
3430/**
57d104c1 3431 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3432 * @hba: per-adapter instance
57d104c1 3433 * @status: bkops_status value
66ec6d59 3434 *
57d104c1
SJ		 3435 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3436 * flag in the device to permit background operations if the device
3437 * bkops_status is greater than or equal to "status" argument passed to
3438 * this function, disable otherwise.
3439 *
3440 * Returns 0 for success, non-zero in case of failure.
3441 *
3442 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3443 * to know whether auto bkops is enabled or disabled after this function
3444 * returns control to it.
66ec6d59 3445 */
57d104c1
SJ		 3446static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3447 enum bkops_status status)
66ec6d59
SRT		 3448{
3449 int err;
57d104c1 3450 u32 curr_status = 0;
66ec6d59 3451
57d104c1 3452 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3453 if (err) {
3454 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3455 __func__, err);
3456 goto out;
57d104c1
SJ		 3457 } else if (curr_status > BKOPS_STATUS_MAX) {
3458 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3459 __func__, curr_status);
3460 err = -EINVAL;
3461 goto out;
66ec6d59
SRT		 3462 }
3463
57d104c1 3464 if (curr_status >= status)
66ec6d59 3465 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3466 else
3467 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3468out:
3469 return err;
3470}
3471
57d104c1
SJ		 3472/**
3473 * ufshcd_urgent_bkops - handle urgent bkops exception event
3474 * @hba: per-adapter instance
3475 *
3476 * Enable fBackgroundOpsEn flag in the device to permit background
3477 * operations.
3478 *
3479 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3480 * and negative error value for any other failure.
3481 */
3482static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3483{
3484 return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
3485}
3486
66ec6d59
SRT		 3487static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3488{
3489 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3490 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3491}
3492
3493/**
3494 * ufshcd_exception_event_handler - handle exceptions raised by device
3495 * @work: pointer to work data
3496 *
3497 * Read bExceptionEventStatus attribute from the device and handle the
3498 * exception event accordingly.
3499 */
3500static void ufshcd_exception_event_handler(struct work_struct *work)
3501{
3502 struct ufs_hba *hba;
3503 int err;
3504 u32 status = 0;
3505 hba = container_of(work, struct ufs_hba, eeh_work);
3506
62694735 3507 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3508 err = ufshcd_get_ee_status(hba, &status);
3509 if (err) {
3510 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3511 __func__, err);
3512 goto out;
3513 }
3514
3515 status &= hba->ee_ctrl_mask;
3516 if (status & MASK_EE_URGENT_BKOPS) {
3517 err = ufshcd_urgent_bkops(hba);
57d104c1 3518 if (err < 0)
66ec6d59
SRT		 3519 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3520 __func__, err);
3521 }
3522out:
62694735 3523 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3524 return;
3525}
3526
7a3e97b0 3527/**
e8e7f271
SRT		 3528 * ufshcd_err_handler - handle UFS errors that require s/w attention
3529 * @work: pointer to work structure
7a3e97b0 3530 */
e8e7f271 3531static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 3532{
3533 struct ufs_hba *hba;
e8e7f271
SRT		 3534 unsigned long flags;
3535 u32 err_xfer = 0;
3536 u32 err_tm = 0;
3537 int err = 0;
3538 int tag;
3539
3540 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 3541
62694735 3542 pm_runtime_get_sync(hba->dev);
1ab27c9c 3543 ufshcd_hold(hba, false);
e8e7f271
SRT		 3544
3545 spin_lock_irqsave(hba->host->host_lock, flags);
3546 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
3547 spin_unlock_irqrestore(hba->host->host_lock, flags);
3548 goto out;
3549 }
3550
3551 hba->ufshcd_state = UFSHCD_STATE_RESET;
3552 ufshcd_set_eh_in_progress(hba);
3553
3554 /* Complete requests that have door-bell cleared by h/w */
3555 ufshcd_transfer_req_compl(hba);
3556 ufshcd_tmc_handler(hba);
3557 spin_unlock_irqrestore(hba->host->host_lock, flags);
3558
3559 /* Clear pending transfer requests */
3560 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
3561 if (ufshcd_clear_cmd(hba, tag))
3562 err_xfer |= 1 << tag;
3563
3564 /* Clear pending task management requests */
3565 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
3566 if (ufshcd_clear_tm_cmd(hba, tag))
3567 err_tm |= 1 << tag;
3568
3569 /* Complete the requests that are cleared by s/w */
3570 spin_lock_irqsave(hba->host->host_lock, flags);
3571 ufshcd_transfer_req_compl(hba);
3572 ufshcd_tmc_handler(hba);
3573 spin_unlock_irqrestore(hba->host->host_lock, flags);
3574
3575 /* Fatal errors need reset */
3576 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
3577 ((hba->saved_err & UIC_ERROR) &&
3578 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
3579 err = ufshcd_reset_and_restore(hba);
3580 if (err) {
3581 dev_err(hba->dev, "%s: reset and restore failed\n",
3582 __func__);
3583 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3584 }
3585 /*
3586 * Inform scsi mid-layer that we did reset and allow to handle
3587 * Unit Attention properly.
3588 */
3589 scsi_report_bus_reset(hba->host, 0);
3590 hba->saved_err = 0;
3591 hba->saved_uic_err = 0;
3592 }
3593 ufshcd_clear_eh_in_progress(hba);
3594
3595out:
3596 scsi_unblock_requests(hba->host);
1ab27c9c 3597 ufshcd_release(hba);
62694735 3598 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 3599}
3600
3601/**
e8e7f271
SRT		 3602 * ufshcd_update_uic_error - check and set fatal UIC error flags.
3603 * @hba: per-adapter instance
7a3e97b0 3604 */
e8e7f271 3605static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 3606{
3607 u32 reg;
3608
e8e7f271
SRT		 3609 /* PA_INIT_ERROR is fatal and needs UIC reset */
3610 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
3611 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
3612 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
3613
3614 /* UIC NL/TL/DME errors needs software retry */
3615 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
3616 if (reg)
3617 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
3618
3619 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
3620 if (reg)
3621 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
3622
3623 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
3624 if (reg)
3625 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
3626
3627 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
3628 __func__, hba->uic_error);
3629}
3630
3631/**
3632 * ufshcd_check_errors - Check for errors that need s/w attention
3633 * @hba: per-adapter instance
3634 */
3635static void ufshcd_check_errors(struct ufs_hba *hba)
3636{
3637 bool queue_eh_work = false;
3638
7a3e97b0 3639 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 3640 queue_eh_work = true;
7a3e97b0
SY		 3641
3642 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 3643 hba->uic_error = 0;
3644 ufshcd_update_uic_error(hba);
3645 if (hba->uic_error)
3646 queue_eh_work = true;
7a3e97b0 3647 }
e8e7f271
SRT		 3648
3649 if (queue_eh_work) {
3650 /* handle fatal errors only when link is functional */
3651 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
3652 /* block commands from scsi mid-layer */
3653 scsi_block_requests(hba->host);
3654
3655 /* transfer error masks to sticky bits */
3656 hba->saved_err |= hba->errors;
3657 hba->saved_uic_err |= hba->uic_error;
3658
3659 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3660 schedule_work(&hba->eh_work);
3661 }
3441da7d 3662 }
e8e7f271
SRT		 3663 /*
3664 * if (!queue_eh_work) -
3665 * Other errors are either non-fatal where host recovers
3666 * itself without s/w intervention or errors that will be
3667 * handled by the SCSI core layer.
3668 */
7a3e97b0
SY		 3669}
3670
3671/**
3672 * ufshcd_tmc_handler - handle task management function completion
3673 * @hba: per adapter instance
3674 */
3675static void ufshcd_tmc_handler(struct ufs_hba *hba)
3676{
3677 u32 tm_doorbell;
3678
b873a275 3679 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 3680 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 3681 wake_up(&hba->tm_wq);
7a3e97b0
SY		 3682}
3683
3684/**
3685 * ufshcd_sl_intr - Interrupt service routine
3686 * @hba: per adapter instance
3687 * @intr_status: contains interrupts generated by the controller
3688 */
3689static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
3690{
3691 hba->errors = UFSHCD_ERROR_MASK & intr_status;
3692 if (hba->errors)
e8e7f271 3693 ufshcd_check_errors(hba);
7a3e97b0 3694
53b3d9c3
SJ		 3695 if (intr_status & UFSHCD_UIC_MASK)
3696 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 3697
3698 if (intr_status & UTP_TASK_REQ_COMPL)
3699 ufshcd_tmc_handler(hba);
3700
3701 if (intr_status & UTP_TRANSFER_REQ_COMPL)
3702 ufshcd_transfer_req_compl(hba);
3703}
3704
3705/**
3706 * ufshcd_intr - Main interrupt service routine
3707 * @irq: irq number
3708 * @__hba: pointer to adapter instance
3709 *
3710 * Returns IRQ_HANDLED - If interrupt is valid
3711 * IRQ_NONE - If invalid interrupt
3712 */
3713static irqreturn_t ufshcd_intr(int irq, void *__hba)
3714{
3715 u32 intr_status;
3716 irqreturn_t retval = IRQ_NONE;
3717 struct ufs_hba *hba = __hba;
3718
3719 spin_lock(hba->host->host_lock);
b873a275 3720 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 3721
3722 if (intr_status) {
261ea452 3723 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 3724 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 3725 retval = IRQ_HANDLED;
3726 }
3727 spin_unlock(hba->host->host_lock);
3728 return retval;
3729}
3730
e2933132
SRT		 3731static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
3732{
3733 int err = 0;
3734 u32 mask = 1 << tag;
3735 unsigned long flags;
3736
3737 if (!test_bit(tag, &hba->outstanding_tasks))
3738 goto out;
3739
3740 spin_lock_irqsave(hba->host->host_lock, flags);
3741 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
3742 spin_unlock_irqrestore(hba->host->host_lock, flags);
3743
3744 /* poll for max. 1 sec to clear door bell register by h/w */
3745 err = ufshcd_wait_for_register(hba,
3746 REG_UTP_TASK_REQ_DOOR_BELL,
3747 mask, 0, 1000, 1000);
3748out:
3749 return err;
3750}
3751
7a3e97b0
SY		 3752/**
3753 * ufshcd_issue_tm_cmd - issues task management commands to controller
3754 * @hba: per adapter instance
e2933132
SRT		 3755 * @lun_id: LUN ID to which TM command is sent
3756 * @task_id: task ID to which the TM command is applicable
3757 * @tm_function: task management function opcode
3758 * @tm_response: task management service response return value
7a3e97b0 3759 *
e2933132 3760 * Returns non-zero value on error, zero on success.
7a3e97b0 3761 */
e2933132
SRT		 3762static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
3763 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 3764{
3765 struct utp_task_req_desc *task_req_descp;
3766 struct utp_upiu_task_req *task_req_upiup;
3767 struct Scsi_Host *host;
3768 unsigned long flags;
e2933132 3769 int free_slot;
7a3e97b0 3770 int err;
e2933132 3771 int task_tag;
7a3e97b0
SY		 3772
3773 host = hba->host;
3774
e2933132
SRT		 3775 /*
3776 * Get free slot, sleep if slots are unavailable.
3777 * Even though we use wait_event() which sleeps indefinitely,
3778 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
3779 */
3780 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 3781 ufshcd_hold(hba, false);
7a3e97b0 3782
e2933132 3783 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3784 task_req_descp = hba->utmrdl_base_addr;
3785 task_req_descp += free_slot;
3786
3787 /* Configure task request descriptor */
3788 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
3789 task_req_descp->header.dword_2 =
3790 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
3791
3792 /* Configure task request UPIU */
3793 task_req_upiup =
3794 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 3795 task_tag = hba->nutrs + free_slot;
7a3e97b0 3796 task_req_upiup->header.dword_0 =
5a0b0cb9 3797 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 3798 lun_id, task_tag);
7a3e97b0 3799 task_req_upiup->header.dword_1 =
5a0b0cb9 3800 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 3801 /*
3802 * The host shall provide the same value for LUN field in the basic
3803 * header and for Input Parameter.
3804 */
e2933132
SRT		 3805 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
3806 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 3807
3808 /* send command to the controller */
3809 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 3810 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 3811
3812 spin_unlock_irqrestore(host->host_lock, flags);
3813
3814 /* wait until the task management command is completed */
e2933132
SRT		 3815 err = wait_event_timeout(hba->tm_wq,
3816 test_bit(free_slot, &hba->tm_condition),
3817 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 3818 if (!err) {
e2933132
SRT		 3819 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
3820 __func__, tm_function);
3821 if (ufshcd_clear_tm_cmd(hba, free_slot))
3822 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
3823 __func__, free_slot);
3824 err = -ETIMEDOUT;
3825 } else {
3826 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 3827 }
e2933132 3828
7a3e97b0 3829 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 3830 ufshcd_put_tm_slot(hba, free_slot);
3831 wake_up(&hba->tm_tag_wq);
3832
1ab27c9c 3833 ufshcd_release(hba);
7a3e97b0
SY		 3834 return err;
3835}
3836
3837/**
3441da7d
SRT		 3838 * ufshcd_eh_device_reset_handler - device reset handler registered to
3839 * scsi layer.
7a3e97b0
SY		 3840 * @cmd: SCSI command pointer
3841 *
3842 * Returns SUCCESS/FAILED
3843 */
3441da7d 3844static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 3845{
3846 struct Scsi_Host *host;
3847 struct ufs_hba *hba;
3848 unsigned int tag;
3849 u32 pos;
3850 int err;
e2933132
SRT		 3851 u8 resp = 0xF;
3852 struct ufshcd_lrb *lrbp;
3441da7d 3853 unsigned long flags;
7a3e97b0
SY		 3854
3855 host = cmd->device->host;
3856 hba = shost_priv(host);
3857 tag = cmd->request->tag;
3858
e2933132
SRT		 3859 lrbp = &hba->lrb[tag];
3860 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
3861 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 3862 if (!err)
3863 err = resp;
7a3e97b0 3864 goto out;
e2933132 3865 }
7a3e97b0 3866
3441da7d
SRT		 3867 /* clear the commands that were pending for corresponding LUN */
3868 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3869 if (hba->lrb[pos].lun == lrbp->lun) {
3870 err = ufshcd_clear_cmd(hba, pos);
3871 if (err)
3872 break;
7a3e97b0 3873 }
3441da7d
SRT		 3874 }
3875 spin_lock_irqsave(host->host_lock, flags);
3876 ufshcd_transfer_req_compl(hba);
3877 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 3878out:
3441da7d
SRT		 3879 if (!err) {
3880 err = SUCCESS;
3881 } else {
3882 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3883 err = FAILED;
3884 }
7a3e97b0
SY		 3885 return err;
3886}
3887
7a3e97b0
SY		 3888/**
3889 * ufshcd_abort - abort a specific command
3890 * @cmd: SCSI command pointer
3891 *
f20810d8
SRT		 3892 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3893 * command, and in host controller by clearing the door-bell register. There can
3894 * be race between controller sending the command to the device while abort is
3895 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3896 * really issued and then try to abort it.
3897 *
7a3e97b0
SY		 3898 * Returns SUCCESS/FAILED
3899 */
3900static int ufshcd_abort(struct scsi_cmnd *cmd)
3901{
3902 struct Scsi_Host *host;
3903 struct ufs_hba *hba;
3904 unsigned long flags;
3905 unsigned int tag;
f20810d8
SRT		 3906 int err = 0;
3907 int poll_cnt;
e2933132
SRT		 3908 u8 resp = 0xF;
3909 struct ufshcd_lrb *lrbp;
e9d501b1 3910 u32 reg;
7a3e97b0
SY		 3911
3912 host = cmd->device->host;
3913 hba = shost_priv(host);
3914 tag = cmd->request->tag;
14497328
YG		 3915 if (!ufshcd_valid_tag(hba, tag)) {
3916 dev_err(hba->dev,
3917 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
3918 __func__, tag, cmd, cmd->request);
3919 BUG();
3920 }
7a3e97b0 3921
1ab27c9c 3922 ufshcd_hold(hba, false);
14497328 3923 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 3924 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 3925 if (!(test_bit(tag, &hba->outstanding_reqs))) {
3926 dev_err(hba->dev,
3927 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
3928 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 3929 goto out;
14497328 3930 }
7a3e97b0 3931
e9d501b1
DR		 3932 if (!(reg & (1 << tag))) {
3933 dev_err(hba->dev,
3934 "%s: cmd was completed, but without a notifying intr, tag = %d",
3935 __func__, tag);
3936 }
3937
f20810d8
SRT		 3938 lrbp = &hba->lrb[tag];
3939 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3940 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3941 UFS_QUERY_TASK, &resp);
3942 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3943 /* cmd pending in the device */
3944 break;
3945 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3946 /*
3947 * cmd not pending in the device, check if it is
3948 * in transition.
3949 */
3950 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3951 if (reg & (1 << tag)) {
3952 /* sleep for max. 200us to stabilize */
3953 usleep_range(100, 200);
3954 continue;
3955 }
3956 /* command completed already */
3957 goto out;
3958 } else {
3959 if (!err)
3960 err = resp; /* service response error */
3961 goto out;
3962 }
3963 }
3964
3965 if (!poll_cnt) {
3966 err = -EBUSY;
7a3e97b0
SY		 3967 goto out;
3968 }
7a3e97b0 3969
e2933132
SRT		 3970 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3971 UFS_ABORT_TASK, &resp);
3972 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3973 if (!err)
3974 err = resp; /* service response error */
7a3e97b0 3975 goto out;
e2933132 3976 }
7a3e97b0 3977
f20810d8
SRT		 3978 err = ufshcd_clear_cmd(hba, tag);
3979 if (err)
3980 goto out;
3981
7a3e97b0
SY		 3982 scsi_dma_unmap(cmd);
3983
3984 spin_lock_irqsave(host->host_lock, flags);
a48353f6 3985 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 3986 hba->lrb[tag].cmd = NULL;
3987 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 3988
3989 clear_bit_unlock(tag, &hba->lrb_in_use);
3990 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 3991
7a3e97b0 3992out:
f20810d8
SRT		 3993 if (!err) {
3994 err = SUCCESS;
3995 } else {
3996 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3997 err = FAILED;
3998 }
3999
1ab27c9c
ST		 4000 /*
4001 * This ufshcd_release() corresponds to the original scsi cmd that got
4002 * aborted here (as we won't get any IRQ for it).
4003 */
4004 ufshcd_release(hba);
7a3e97b0
SY		 4005 return err;
4006}
4007
3441da7d
SRT		 4008/**
4009 * ufshcd_host_reset_and_restore - reset and restore host controller
4010 * @hba: per-adapter instance
4011 *
4012 * Note that host controller reset may issue DME_RESET to
4013 * local and remote (device) Uni-Pro stack and the attributes
4014 * are reset to default state.
4015 *
4016 * Returns zero on success, non-zero on failure
4017 */
4018static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4019{
4020 int err;
3441da7d
SRT		 4021 unsigned long flags;
4022
4023 /* Reset the host controller */
4024 spin_lock_irqsave(hba->host->host_lock, flags);
4025 ufshcd_hba_stop(hba);
4026 spin_unlock_irqrestore(hba->host->host_lock, flags);
4027
4028 err = ufshcd_hba_enable(hba);
4029 if (err)
4030 goto out;
4031
4032 /* Establish the link again and restore the device */
1d337ec2
SRT		 4033 err = ufshcd_probe_hba(hba);
4034
4035 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 4036 err = -EIO;
4037out:
4038 if (err)
4039 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4040
4041 return err;
4042}
4043
4044/**
4045 * ufshcd_reset_and_restore - reset and re-initialize host/device
4046 * @hba: per-adapter instance
4047 *
4048 * Reset and recover device, host and re-establish link. This
4049 * is helpful to recover the communication in fatal error conditions.
4050 *
4051 * Returns zero on success, non-zero on failure
4052 */
4053static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4054{
4055 int err = 0;
4056 unsigned long flags;
1d337ec2 4057 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4058
1d337ec2
SRT		 4059 do {
4060 err = ufshcd_host_reset_and_restore(hba);
4061 } while (err && --retries);
3441da7d
SRT		 4062
4063 /*
4064 * After reset the door-bell might be cleared, complete
4065 * outstanding requests in s/w here.
4066 */
4067 spin_lock_irqsave(hba->host->host_lock, flags);
4068 ufshcd_transfer_req_compl(hba);
4069 ufshcd_tmc_handler(hba);
4070 spin_unlock_irqrestore(hba->host->host_lock, flags);
4071
4072 return err;
4073}
4074
4075/**
4076 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4077 * @cmd - SCSI command pointer
4078 *
4079 * Returns SUCCESS/FAILED
4080 */
4081static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4082{
4083 int err;
4084 unsigned long flags;
4085 struct ufs_hba *hba;
4086
4087 hba = shost_priv(cmd->device->host);
4088
1ab27c9c 4089 ufshcd_hold(hba, false);
3441da7d
SRT		 4090 /*
4091 * Check if there is any race with fatal error handling.
4092 * If so, wait for it to complete. Even though fatal error
4093 * handling does reset and restore in some cases, don't assume
4094 * anything out of it. We are just avoiding race here.
4095 */
4096 do {
4097 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4098 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 4099 hba->ufshcd_state == UFSHCD_STATE_RESET))
4100 break;
4101 spin_unlock_irqrestore(hba->host->host_lock, flags);
4102 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4103 flush_work(&hba->eh_work);
3441da7d
SRT		 4104 } while (1);
4105
4106 hba->ufshcd_state = UFSHCD_STATE_RESET;
4107 ufshcd_set_eh_in_progress(hba);
4108 spin_unlock_irqrestore(hba->host->host_lock, flags);
4109
4110 err = ufshcd_reset_and_restore(hba);
4111
4112 spin_lock_irqsave(hba->host->host_lock, flags);
4113 if (!err) {
4114 err = SUCCESS;
4115 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4116 } else {
4117 err = FAILED;
4118 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4119 }
4120 ufshcd_clear_eh_in_progress(hba);
4121 spin_unlock_irqrestore(hba->host->host_lock, flags);
4122
1ab27c9c 4123 ufshcd_release(hba);
3441da7d
SRT		 4124 return err;
4125}
4126
3a4bf06d
YG		 4127/**
4128 * ufshcd_get_max_icc_level - calculate the ICC level
4129 * @sup_curr_uA: max. current supported by the regulator
4130 * @start_scan: row at the desc table to start scan from
4131 * @buff: power descriptor buffer
4132 *
4133 * Returns calculated max ICC level for specific regulator
4134 */
4135static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4136{
4137 int i;
4138 int curr_uA;
4139 u16 data;
4140 u16 unit;
4141
4142 for (i = start_scan; i >= 0; i--) {
4143 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4144 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4145 ATTR_ICC_LVL_UNIT_OFFSET;
4146 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4147 switch (unit) {
4148 case UFSHCD_NANO_AMP:
4149 curr_uA = curr_uA / 1000;
4150 break;
4151 case UFSHCD_MILI_AMP:
4152 curr_uA = curr_uA * 1000;
4153 break;
4154 case UFSHCD_AMP:
4155 curr_uA = curr_uA * 1000 * 1000;
4156 break;
4157 case UFSHCD_MICRO_AMP:
4158 default:
4159 break;
4160 }
4161 if (sup_curr_uA >= curr_uA)
4162 break;
4163 }
4164 if (i < 0) {
4165 i = 0;
4166 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4167 }
4168
4169 return (u32)i;
4170}
4171
4172/**
4173 * ufshcd_calc_icc_level - calculate the max ICC level
4174 * In case regulators are not initialized we'll return 0
4175 * @hba: per-adapter instance
4176 * @desc_buf: power descriptor buffer to extract ICC levels from.
4177 * @len: length of desc_buff
4178 *
4179 * Returns calculated ICC level
4180 */
4181static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4182 u8 *desc_buf, int len)
4183{
4184 u32 icc_level = 0;
4185
4186 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4187 !hba->vreg_info.vccq2) {
4188 dev_err(hba->dev,
4189 "%s: Regulator capability was not set, actvIccLevel=%d",
4190 __func__, icc_level);
4191 goto out;
4192 }
4193
4194 if (hba->vreg_info.vcc)
4195 icc_level = ufshcd_get_max_icc_level(
4196 hba->vreg_info.vcc->max_uA,
4197 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4198 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4199
4200 if (hba->vreg_info.vccq)
4201 icc_level = ufshcd_get_max_icc_level(
4202 hba->vreg_info.vccq->max_uA,
4203 icc_level,
4204 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4205
4206 if (hba->vreg_info.vccq2)
4207 icc_level = ufshcd_get_max_icc_level(
4208 hba->vreg_info.vccq2->max_uA,
4209 icc_level,
4210 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4211out:
4212 return icc_level;
4213}
4214
4215static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4216{
4217 int ret;
4218 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4219 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4220
4221 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4222 if (ret) {
4223 dev_err(hba->dev,
4224 "%s: Failed reading power descriptor.len = %d ret = %d",
4225 __func__, buff_len, ret);
4226 return;
4227 }
4228
4229 hba->init_prefetch_data.icc_level =
4230 ufshcd_find_max_sup_active_icc_level(hba,
4231 desc_buf, buff_len);
4232 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4233 __func__, hba->init_prefetch_data.icc_level);
4234
4235 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4236 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4237 &hba->init_prefetch_data.icc_level);
4238
4239 if (ret)
4240 dev_err(hba->dev,
4241 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4242 __func__, hba->init_prefetch_data.icc_level , ret);
4243
4244}
4245
2a8fa600
SJ		 4246/**
4247 * ufshcd_scsi_add_wlus - Adds required W-LUs
4248 * @hba: per-adapter instance
4249 *
4250 * UFS device specification requires the UFS devices to support 4 well known
4251 * logical units:
4252 * "REPORT_LUNS" (address: 01h)
4253 * "UFS Device" (address: 50h)
4254 * "RPMB" (address: 44h)
4255 * "BOOT" (address: 30h)
4256 * UFS device's power management needs to be controlled by "POWER CONDITION"
4257 * field of SSU (START STOP UNIT) command. But this "power condition" field
4258 * will take effect only when its sent to "UFS device" well known logical unit
4259 * hence we require the scsi_device instance to represent this logical unit in
4260 * order for the UFS host driver to send the SSU command for power management.
4261
4262 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4263 * Block) LU so user space process can control this LU. User space may also
4264 * want to have access to BOOT LU.
4265
4266 * This function adds scsi device instances for each of all well known LUs
4267 * (except "REPORT LUNS" LU).
4268 *
4269 * Returns zero on success (all required W-LUs are added successfully),
4270 * non-zero error value on failure (if failed to add any of the required W-LU).
4271 */
4272static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4273{
4274 int ret = 0;
7c48bfd0
AM		 4275 struct scsi_device *sdev_rpmb;
4276 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4277
4278 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4279 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4280 if (IS_ERR(hba->sdev_ufs_device)) {
4281 ret = PTR_ERR(hba->sdev_ufs_device);
4282 hba->sdev_ufs_device = NULL;
4283 goto out;
4284 }
7c48bfd0 4285 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4286
7c48bfd0 4287 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4288 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4289 if (IS_ERR(sdev_boot)) {
4290 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4291 goto remove_sdev_ufs_device;
4292 }
7c48bfd0 4293 scsi_device_put(sdev_boot);
2a8fa600 4294
7c48bfd0 4295 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4296 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4297 if (IS_ERR(sdev_rpmb)) {
4298 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4299 goto remove_sdev_boot;
4300 }
7c48bfd0 4301 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4302 goto out;
4303
4304remove_sdev_boot:
7c48bfd0 4305 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4306remove_sdev_ufs_device:
4307 scsi_remove_device(hba->sdev_ufs_device);
4308out:
4309 return ret;
4310}
4311
6ccf44fe 4312/**
1d337ec2
SRT		 4313 * ufshcd_probe_hba - probe hba to detect device and initialize
4314 * @hba: per-adapter instance
4315 *
4316 * Execute link-startup and verify device initialization
6ccf44fe 4317 */
1d337ec2 4318static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 4319{
6ccf44fe
SJ		 4320 int ret;
4321
4322 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 4323 if (ret)
4324 goto out;
4325
5064636c
YG		 4326 ufshcd_init_pwr_info(hba);
4327
57d104c1
SJ		 4328 /* UniPro link is active now */
4329 ufshcd_set_link_active(hba);
d3e89bac 4330
5a0b0cb9
SRT		 4331 ret = ufshcd_verify_dev_init(hba);
4332 if (ret)
4333 goto out;
68078d5c
DR		 4334
4335 ret = ufshcd_complete_dev_init(hba);
4336 if (ret)
4337 goto out;
5a0b0cb9 4338
57d104c1
SJ		 4339 /* UFS device is also active now */
4340 ufshcd_set_ufs_dev_active(hba);
66ec6d59 4341 ufshcd_force_reset_auto_bkops(hba);
3441da7d 4342 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 4343 hba->wlun_dev_clr_ua = true;
4344
7eb584db
DR		 4345 if (ufshcd_get_max_pwr_mode(hba)) {
4346 dev_err(hba->dev,
4347 "%s: Failed getting max supported power mode\n",
4348 __func__);
4349 } else {
4350 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
4351 if (ret)
4352 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
4353 __func__, ret);
4354 }
57d104c1
SJ		 4355
4356 /*
4357 * If we are in error handling context or in power management callbacks
4358 * context, no need to scan the host
4359 */
4360 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4361 bool flag;
4362
4363 /* clear any previous UFS device information */
4364 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
4365 if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4366 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
4367 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 4368
3a4bf06d
YG		 4369 if (!hba->is_init_prefetch)
4370 ufshcd_init_icc_levels(hba);
4371
2a8fa600
SJ		 4372 /* Add required well known logical units to scsi mid layer */
4373 if (ufshcd_scsi_add_wlus(hba))
4374 goto out;
4375
3441da7d
SRT		 4376 scsi_scan_host(hba->host);
4377 pm_runtime_put_sync(hba->dev);
4378 }
3a4bf06d
YG		 4379
4380 if (!hba->is_init_prefetch)
4381 hba->is_init_prefetch = true;
4382
856b3483
ST		 4383 /* Resume devfreq after UFS device is detected */
4384 if (ufshcd_is_clkscaling_enabled(hba))
4385 devfreq_resume_device(hba->devfreq);
4386
5a0b0cb9 4387out:
1d337ec2
SRT		 4388 /*
4389 * If we failed to initialize the device or the device is not
4390 * present, turn off the power/clocks etc.
4391 */
57d104c1
SJ		 4392 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4393 pm_runtime_put_sync(hba->dev);
1d337ec2 4394 ufshcd_hba_exit(hba);
57d104c1 4395 }
1d337ec2
SRT		 4396
4397 return ret;
4398}
4399
4400/**
4401 * ufshcd_async_scan - asynchronous execution for probing hba
4402 * @data: data pointer to pass to this function
4403 * @cookie: cookie data
4404 */
4405static void ufshcd_async_scan(void *data, async_cookie_t cookie)
4406{
4407 struct ufs_hba *hba = (struct ufs_hba *)data;
4408
4409 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 4410}
4411
7a3e97b0
SY		 4412static struct scsi_host_template ufshcd_driver_template = {
4413 .module = THIS_MODULE,
4414 .name = UFSHCD,
4415 .proc_name = UFSHCD,
4416 .queuecommand = ufshcd_queuecommand,
4417 .slave_alloc = ufshcd_slave_alloc,
eeda4749 4418 .slave_configure = ufshcd_slave_configure,
7a3e97b0 4419 .slave_destroy = ufshcd_slave_destroy,
4264fd61 4420 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 4421 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 4422 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
4423 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 4424 .this_id = -1,
4425 .sg_tablesize = SG_ALL,
4426 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
4427 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 4428 .max_host_blocked = 1,
c40ecc12 4429 .track_queue_depth = 1,
7a3e97b0
SY		 4430};
4431
57d104c1
SJ		 4432static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
4433 int ua)
4434{
7b16a07c 4435 int ret;
57d104c1 4436
7b16a07c
BA		 4437 if (!vreg)
4438 return 0;
57d104c1 4439
7b16a07c
BA		 4440 ret = regulator_set_load(vreg->reg, ua);
4441 if (ret < 0) {
4442 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
4443 __func__, vreg->name, ua, ret);
57d104c1
SJ		 4444 }
4445
4446 return ret;
4447}
4448
4449static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
4450 struct ufs_vreg *vreg)
4451{
4452 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
4453}
4454
4455static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
4456 struct ufs_vreg *vreg)
4457{
4458 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
4459}
4460
aa497613
SRT		 4461static int ufshcd_config_vreg(struct device *dev,
4462 struct ufs_vreg *vreg, bool on)
4463{
4464 int ret = 0;
4465 struct regulator *reg = vreg->reg;
4466 const char *name = vreg->name;
4467 int min_uV, uA_load;
4468
4469 BUG_ON(!vreg);
4470
4471 if (regulator_count_voltages(reg) > 0) {
4472 min_uV = on ? vreg->min_uV : 0;
4473 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
4474 if (ret) {
4475 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
4476 __func__, name, ret);
4477 goto out;
4478 }
4479
4480 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 4481 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
4482 if (ret)
aa497613 4483 goto out;
aa497613
SRT		 4484 }
4485out:
4486 return ret;
4487}
4488
4489static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
4490{
4491 int ret = 0;
4492
4493 if (!vreg || vreg->enabled)
4494 goto out;
4495
4496 ret = ufshcd_config_vreg(dev, vreg, true);
4497 if (!ret)
4498 ret = regulator_enable(vreg->reg);
4499
4500 if (!ret)
4501 vreg->enabled = true;
4502 else
4503 dev_err(dev, "%s: %s enable failed, err=%d\n",
4504 __func__, vreg->name, ret);
4505out:
4506 return ret;
4507}
4508
4509static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
4510{
4511 int ret = 0;
4512
4513 if (!vreg || !vreg->enabled)
4514 goto out;
4515
4516 ret = regulator_disable(vreg->reg);
4517
4518 if (!ret) {
4519 /* ignore errors on applying disable config */
4520 ufshcd_config_vreg(dev, vreg, false);
4521 vreg->enabled = false;
4522 } else {
4523 dev_err(dev, "%s: %s disable failed, err=%d\n",
4524 __func__, vreg->name, ret);
4525 }
4526out:
4527 return ret;
4528}
4529
4530static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
4531{
4532 int ret = 0;
4533 struct device *dev = hba->dev;
4534 struct ufs_vreg_info *info = &hba->vreg_info;
4535
4536 if (!info)
4537 goto out;
4538
4539 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
4540 if (ret)
4541 goto out;
4542
4543 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
4544 if (ret)
4545 goto out;
4546
4547 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
4548 if (ret)
4549 goto out;
4550
4551out:
4552 if (ret) {
4553 ufshcd_toggle_vreg(dev, info->vccq2, false);
4554 ufshcd_toggle_vreg(dev, info->vccq, false);
4555 ufshcd_toggle_vreg(dev, info->vcc, false);
4556 }
4557 return ret;
4558}
4559
6a771a65
RS		 4560static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
4561{
4562 struct ufs_vreg_info *info = &hba->vreg_info;
4563
4564 if (info)
4565 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
4566
4567 return 0;
4568}
4569
aa497613
SRT		 4570static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
4571{
4572 int ret = 0;
4573
4574 if (!vreg)
4575 goto out;
4576
4577 vreg->reg = devm_regulator_get(dev, vreg->name);
4578 if (IS_ERR(vreg->reg)) {
4579 ret = PTR_ERR(vreg->reg);
4580 dev_err(dev, "%s: %s get failed, err=%d\n",
4581 __func__, vreg->name, ret);
4582 }
4583out:
4584 return ret;
4585}
4586
4587static int ufshcd_init_vreg(struct ufs_hba *hba)
4588{
4589 int ret = 0;
4590 struct device *dev = hba->dev;
4591 struct ufs_vreg_info *info = &hba->vreg_info;
4592
4593 if (!info)
4594 goto out;
4595
4596 ret = ufshcd_get_vreg(dev, info->vcc);
4597 if (ret)
4598 goto out;
4599
4600 ret = ufshcd_get_vreg(dev, info->vccq);
4601 if (ret)
4602 goto out;
4603
4604 ret = ufshcd_get_vreg(dev, info->vccq2);
4605out:
4606 return ret;
4607}
4608
6a771a65
RS		 4609static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
4610{
4611 struct ufs_vreg_info *info = &hba->vreg_info;
4612
4613 if (info)
4614 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
4615
4616 return 0;
4617}
4618
57d104c1
SJ		 4619static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
4620 bool skip_ref_clk)
c6e79dac
SRT		 4621{
4622 int ret = 0;
4623 struct ufs_clk_info *clki;
4624 struct list_head *head = &hba->clk_list_head;
1ab27c9c 4625 unsigned long flags;
c6e79dac
SRT		 4626
4627 if (!head || list_empty(head))
4628 goto out;
4629
4630 list_for_each_entry(clki, head, list) {
4631 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 4632 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
4633 continue;
4634
c6e79dac
SRT		 4635 if (on && !clki->enabled) {
4636 ret = clk_prepare_enable(clki->clk);
4637 if (ret) {
4638 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
4639 __func__, clki->name, ret);
4640 goto out;
4641 }
4642 } else if (!on && clki->enabled) {
4643 clk_disable_unprepare(clki->clk);
4644 }
4645 clki->enabled = on;
4646 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
4647 clki->name, on ? "en" : "dis");
4648 }
4649 }
1ab27c9c 4650
0263bcd0 4651 ret = ufshcd_vops_setup_clocks(hba, on);
c6e79dac
SRT		 4652out:
4653 if (ret) {
4654 list_for_each_entry(clki, head, list) {
4655 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
4656 clk_disable_unprepare(clki->clk);
4657 }
eda910e4 4658 } else if (on) {
1ab27c9c
ST		 4659 spin_lock_irqsave(hba->host->host_lock, flags);
4660 hba->clk_gating.state = CLKS_ON;
4661 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 4662 }
4663 return ret;
4664}
4665
57d104c1
SJ		 4666static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
4667{
4668 return __ufshcd_setup_clocks(hba, on, false);
4669}
4670
c6e79dac
SRT		 4671static int ufshcd_init_clocks(struct ufs_hba *hba)
4672{
4673 int ret = 0;
4674 struct ufs_clk_info *clki;
4675 struct device *dev = hba->dev;
4676 struct list_head *head = &hba->clk_list_head;
4677
4678 if (!head || list_empty(head))
4679 goto out;
4680
4681 list_for_each_entry(clki, head, list) {
4682 if (!clki->name)
4683 continue;
4684
4685 clki->clk = devm_clk_get(dev, clki->name);
4686 if (IS_ERR(clki->clk)) {
4687 ret = PTR_ERR(clki->clk);
4688 dev_err(dev, "%s: %s clk get failed, %d\n",
4689 __func__, clki->name, ret);
4690 goto out;
4691 }
4692
4693 if (clki->max_freq) {
4694 ret = clk_set_rate(clki->clk, clki->max_freq);
4695 if (ret) {
4696 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
4697 __func__, clki->name,
4698 clki->max_freq, ret);
4699 goto out;
4700 }
856b3483 4701 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 4702 }
4703 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
4704 clki->name, clk_get_rate(clki->clk));
4705 }
4706out:
4707 return ret;
4708}
4709
5c0c28a8
SRT		 4710static int ufshcd_variant_hba_init(struct ufs_hba *hba)
4711{
4712 int err = 0;
4713
4714 if (!hba->vops)
4715 goto out;
4716
0263bcd0
YG		 4717 err = ufshcd_vops_init(hba);
4718 if (err)
4719 goto out;
5c0c28a8 4720
0263bcd0
YG		 4721 err = ufshcd_vops_setup_regulators(hba, true);
4722 if (err)
4723 goto out_exit;
5c0c28a8
SRT		 4724
4725 goto out;
4726
5c0c28a8 4727out_exit:
0263bcd0 4728 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 4729out:
4730 if (err)
4731 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 4732 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 4733 return err;
4734}
4735
4736static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
4737{
4738 if (!hba->vops)
4739 return;
4740
0263bcd0 4741 ufshcd_vops_setup_clocks(hba, false);
5c0c28a8 4742
0263bcd0 4743 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 4744
0263bcd0 4745 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 4746}
4747
aa497613
SRT		 4748static int ufshcd_hba_init(struct ufs_hba *hba)
4749{
4750 int err;
4751
6a771a65
RS		 4752 /*
4753 * Handle host controller power separately from the UFS device power
4754 * rails as it will help controlling the UFS host controller power
4755 * collapse easily which is different than UFS device power collapse.
4756 * Also, enable the host controller power before we go ahead with rest
4757 * of the initialization here.
4758 */
4759 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 4760 if (err)
4761 goto out;
4762
6a771a65 4763 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 4764 if (err)
4765 goto out;
4766
6a771a65
RS		 4767 err = ufshcd_init_clocks(hba);
4768 if (err)
4769 goto out_disable_hba_vreg;
4770
4771 err = ufshcd_setup_clocks(hba, true);
4772 if (err)
4773 goto out_disable_hba_vreg;
4774
c6e79dac
SRT		 4775 err = ufshcd_init_vreg(hba);
4776 if (err)
4777 goto out_disable_clks;
4778
4779 err = ufshcd_setup_vreg(hba, true);
4780 if (err)
4781 goto out_disable_clks;
4782
aa497613
SRT		 4783 err = ufshcd_variant_hba_init(hba);
4784 if (err)
4785 goto out_disable_vreg;
4786
1d337ec2 4787 hba->is_powered = true;
aa497613
SRT		 4788 goto out;
4789
4790out_disable_vreg:
4791 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 4792out_disable_clks:
4793 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 4794out_disable_hba_vreg:
4795 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 4796out:
4797 return err;
4798}
4799
4800static void ufshcd_hba_exit(struct ufs_hba *hba)
4801{
1d337ec2
SRT		 4802 if (hba->is_powered) {
4803 ufshcd_variant_hba_exit(hba);
4804 ufshcd_setup_vreg(hba, false);
4805 ufshcd_setup_clocks(hba, false);
4806 ufshcd_setup_hba_vreg(hba, false);
4807 hba->is_powered = false;
4808 }
aa497613
SRT		 4809}
4810
57d104c1
SJ		 4811static int
4812ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
4813{
4814 unsigned char cmd[6] = {REQUEST_SENSE,
4815 0,
4816 0,
4817 0,
4818 SCSI_SENSE_BUFFERSIZE,
4819 0};
4820 char *buffer;
4821 int ret;
4822
4823 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4824 if (!buffer) {
4825 ret = -ENOMEM;
4826 goto out;
4827 }
4828
4829 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
4830 SCSI_SENSE_BUFFERSIZE, NULL,
4831 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
4832 if (ret)
4833 pr_err("%s: failed with err %d\n", __func__, ret);
4834
4835 kfree(buffer);
4836out:
4837 return ret;
4838}
4839
4840/**
4841 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
4842 * power mode
4843 * @hba: per adapter instance
4844 * @pwr_mode: device power mode to set
4845 *
4846 * Returns 0 if requested power mode is set successfully
4847 * Returns non-zero if failed to set the requested power mode
4848 */
4849static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
4850 enum ufs_dev_pwr_mode pwr_mode)
4851{
4852 unsigned char cmd[6] = { START_STOP };
4853 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 4854 struct scsi_device *sdp;
4855 unsigned long flags;
57d104c1
SJ		 4856 int ret;
4857
7c48bfd0
AM		 4858 spin_lock_irqsave(hba->host->host_lock, flags);
4859 sdp = hba->sdev_ufs_device;
4860 if (sdp) {
4861 ret = scsi_device_get(sdp);
4862 if (!ret && !scsi_device_online(sdp)) {
4863 ret = -ENODEV;
4864 scsi_device_put(sdp);
4865 }
4866 } else {
4867 ret = -ENODEV;
4868 }
4869 spin_unlock_irqrestore(hba->host->host_lock, flags);
4870
4871 if (ret)
4872 return ret;
57d104c1
SJ		 4873
4874 /*
4875 * If scsi commands fail, the scsi mid-layer schedules scsi error-
4876 * handling, which would wait for host to be resumed. Since we know
4877 * we are functional while we are here, skip host resume in error
4878 * handling context.
4879 */
4880 hba->host->eh_noresume = 1;
4881 if (hba->wlun_dev_clr_ua) {
4882 ret = ufshcd_send_request_sense(hba, sdp);
4883 if (ret)
4884 goto out;
4885 /* Unit attention condition is cleared now */
4886 hba->wlun_dev_clr_ua = false;
4887 }
4888
4889 cmd[4] = pwr_mode << 4;
4890
4891 /*
4892 * Current function would be generally called from the power management
4893 * callbacks hence set the REQ_PM flag so that it doesn't resume the
4894 * already suspended childs.
4895 */
4896 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
4897 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
4898 if (ret) {
4899 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 4900 "START_STOP failed for power mode: %d, result %x\n",
4901 pwr_mode, ret);
21045519
HR		 4902 if (driver_byte(ret) & DRIVER_SENSE)
4903 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 4904 }
4905
4906 if (!ret)
4907 hba->curr_dev_pwr_mode = pwr_mode;
4908out:
7c48bfd0 4909 scsi_device_put(sdp);
57d104c1
SJ		 4910 hba->host->eh_noresume = 0;
4911 return ret;
4912}
4913
4914static int ufshcd_link_state_transition(struct ufs_hba *hba,
4915 enum uic_link_state req_link_state,
4916 int check_for_bkops)
4917{
4918 int ret = 0;
4919
4920 if (req_link_state == hba->uic_link_state)
4921 return 0;
4922
4923 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
4924 ret = ufshcd_uic_hibern8_enter(hba);
4925 if (!ret)
4926 ufshcd_set_link_hibern8(hba);
4927 else
4928 goto out;
4929 }
4930 /*
4931 * If autobkops is enabled, link can't be turned off because
4932 * turning off the link would also turn off the device.
4933 */
4934 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
4935 (!check_for_bkops || (check_for_bkops &&
4936 !hba->auto_bkops_enabled))) {
4937 /*
4938 * Change controller state to "reset state" which
4939 * should also put the link in off/reset state
4940 */
4941 ufshcd_hba_stop(hba);
4942 /*
4943 * TODO: Check if we need any delay to make sure that
4944 * controller is reset
4945 */
4946 ufshcd_set_link_off(hba);
4947 }
4948
4949out:
4950 return ret;
4951}
4952
4953static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
4954{
4955 /*
4956 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
4957 * power.
4958 *
4959 * If UFS device and link is in OFF state, all power supplies (VCC,
4960 * VCCQ, VCCQ2) can be turned off if power on write protect is not
4961 * required. If UFS link is inactive (Hibern8 or OFF state) and device
4962 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
4963 *
4964 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
4965 * in low power state which would save some power.
4966 */
4967 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4968 !hba->dev_info.is_lu_power_on_wp) {
4969 ufshcd_setup_vreg(hba, false);
4970 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4971 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4972 if (!ufshcd_is_link_active(hba)) {
4973 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4974 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
4975 }
4976 }
4977}
4978
4979static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
4980{
4981 int ret = 0;
4982
4983 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4984 !hba->dev_info.is_lu_power_on_wp) {
4985 ret = ufshcd_setup_vreg(hba, true);
4986 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4987 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
4988 if (!ret && !ufshcd_is_link_active(hba)) {
4989 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
4990 if (ret)
4991 goto vcc_disable;
4992 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
4993 if (ret)
4994 goto vccq_lpm;
4995 }
4996 }
4997 goto out;
4998
4999vccq_lpm:
5000 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5001vcc_disable:
5002 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5003out:
5004 return ret;
5005}
5006
5007static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
5008{
5009 if (ufshcd_is_link_off(hba))
5010 ufshcd_setup_hba_vreg(hba, false);
5011}
5012
5013static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
5014{
5015 if (ufshcd_is_link_off(hba))
5016 ufshcd_setup_hba_vreg(hba, true);
5017}
5018
7a3e97b0 5019/**
57d104c1 5020 * ufshcd_suspend - helper function for suspend operations
3b1d0580 5021 * @hba: per adapter instance
57d104c1
SJ		 5022 * @pm_op: desired low power operation type
5023 *
5024 * This function will try to put the UFS device and link into low power
5025 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
5026 * (System PM level).
5027 *
5028 * If this function is called during shutdown, it will make sure that
5029 * both UFS device and UFS link is powered off.
7a3e97b0 5030 *
57d104c1
SJ		 5031 * NOTE: UFS device & link must be active before we enter in this function.
5032 *
5033 * Returns 0 for success and non-zero for failure
7a3e97b0 5034 */
57d104c1 5035static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5036{
57d104c1
SJ		 5037 int ret = 0;
5038 enum ufs_pm_level pm_lvl;
5039 enum ufs_dev_pwr_mode req_dev_pwr_mode;
5040 enum uic_link_state req_link_state;
5041
5042 hba->pm_op_in_progress = 1;
5043 if (!ufshcd_is_shutdown_pm(pm_op)) {
5044 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
5045 hba->rpm_lvl : hba->spm_lvl;
5046 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
5047 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
5048 } else {
5049 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
5050 req_link_state = UIC_LINK_OFF_STATE;
5051 }
5052
7a3e97b0 5053 /*
57d104c1
SJ		 5054 * If we can't transition into any of the low power modes
5055 * just gate the clocks.
7a3e97b0 5056 */
1ab27c9c
ST		 5057 ufshcd_hold(hba, false);
5058 hba->clk_gating.is_suspended = true;
5059
57d104c1
SJ		 5060 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
5061 req_link_state == UIC_LINK_ACTIVE_STATE) {
5062 goto disable_clks;
5063 }
7a3e97b0 5064
57d104c1
SJ		 5065 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
5066 (req_link_state == hba->uic_link_state))
5067 goto out;
5068
5069 /* UFS device & link must be active before we enter in this function */
5070 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
5071 ret = -EINVAL;
5072 goto out;
5073 }
5074
5075 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 5076 if (ufshcd_can_autobkops_during_suspend(hba)) {
5077 /*
5078 * The device is idle with no requests in the queue,
5079 * allow background operations if bkops status shows
5080 * that performance might be impacted.
5081 */
5082 ret = ufshcd_urgent_bkops(hba);
5083 if (ret)
5084 goto enable_gating;
5085 } else {
5086 /* make sure that auto bkops is disabled */
5087 ufshcd_disable_auto_bkops(hba);
5088 }
57d104c1
SJ		 5089 }
5090
5091 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
5092 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
5093 !ufshcd_is_runtime_pm(pm_op))) {
5094 /* ensure that bkops is disabled */
5095 ufshcd_disable_auto_bkops(hba);
5096 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
5097 if (ret)
1ab27c9c 5098 goto enable_gating;
57d104c1
SJ		 5099 }
5100
5101 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
5102 if (ret)
5103 goto set_dev_active;
5104
5105 ufshcd_vreg_set_lpm(hba);
5106
5107disable_clks:
856b3483
ST		 5108 /*
5109 * The clock scaling needs access to controller registers. Hence, Wait
5110 * for pending clock scaling work to be done before clocks are
5111 * turned off.
5112 */
5113 if (ufshcd_is_clkscaling_enabled(hba)) {
5114 devfreq_suspend_device(hba->devfreq);
5115 hba->clk_scaling.window_start_t = 0;
5116 }
57d104c1
SJ		 5117 /*
5118 * Call vendor specific suspend callback. As these callbacks may access
5119 * vendor specific host controller register space call them before the
5120 * host clocks are ON.
5121 */
0263bcd0
YG		 5122 ret = ufshcd_vops_suspend(hba, pm_op);
5123 if (ret)
5124 goto set_link_active;
57d104c1 5125
0263bcd0
YG		 5126 ret = ufshcd_vops_setup_clocks(hba, false);
5127 if (ret)
5128 goto vops_resume;
57d104c1
SJ		 5129
5130 if (!ufshcd_is_link_active(hba))
5131 ufshcd_setup_clocks(hba, false);
5132 else
5133 /* If link is active, device ref_clk can't be switched off */
5134 __ufshcd_setup_clocks(hba, false, true);
5135
1ab27c9c 5136 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 5137 /*
5138 * Disable the host irq as host controller as there won't be any
0263bcd0 5139 * host controller transaction expected till resume.
57d104c1
SJ		 5140 */
5141 ufshcd_disable_irq(hba);
5142 /* Put the host controller in low power mode if possible */
5143 ufshcd_hba_vreg_set_lpm(hba);
5144 goto out;
5145
5146vops_resume:
0263bcd0 5147 ufshcd_vops_resume(hba, pm_op);
57d104c1
SJ		 5148set_link_active:
5149 ufshcd_vreg_set_hpm(hba);
5150 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
5151 ufshcd_set_link_active(hba);
5152 else if (ufshcd_is_link_off(hba))
5153 ufshcd_host_reset_and_restore(hba);
5154set_dev_active:
5155 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
5156 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST		 5157enable_gating:
5158 hba->clk_gating.is_suspended = false;
5159 ufshcd_release(hba);
57d104c1
SJ		 5160out:
5161 hba->pm_op_in_progress = 0;
5162 return ret;
7a3e97b0
SY		 5163}
5164
5165/**
57d104c1 5166 * ufshcd_resume - helper function for resume operations
3b1d0580 5167 * @hba: per adapter instance
57d104c1 5168 * @pm_op: runtime PM or system PM
7a3e97b0 5169 *
57d104c1
SJ		 5170 * This function basically brings the UFS device, UniPro link and controller
5171 * to active state.
5172 *
5173 * Returns 0 for success and non-zero for failure
7a3e97b0 5174 */
57d104c1 5175static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5176{
57d104c1
SJ		 5177 int ret;
5178 enum uic_link_state old_link_state;
5179
5180 hba->pm_op_in_progress = 1;
5181 old_link_state = hba->uic_link_state;
5182
5183 ufshcd_hba_vreg_set_hpm(hba);
5184 /* Make sure clocks are enabled before accessing controller */
5185 ret = ufshcd_setup_clocks(hba, true);
5186 if (ret)
5187 goto out;
5188
57d104c1
SJ		 5189 /* enable the host irq as host controller would be active soon */
5190 ret = ufshcd_enable_irq(hba);
5191 if (ret)
5192 goto disable_irq_and_vops_clks;
5193
5194 ret = ufshcd_vreg_set_hpm(hba);
5195 if (ret)
5196 goto disable_irq_and_vops_clks;
5197
7a3e97b0 5198 /*
57d104c1
SJ		 5199 * Call vendor specific resume callback. As these callbacks may access
5200 * vendor specific host controller register space call them when the
5201 * host clocks are ON.
7a3e97b0 5202 */
0263bcd0
YG		 5203 ret = ufshcd_vops_resume(hba, pm_op);
5204 if (ret)
5205 goto disable_vreg;
57d104c1
SJ		 5206
5207 if (ufshcd_is_link_hibern8(hba)) {
5208 ret = ufshcd_uic_hibern8_exit(hba);
5209 if (!ret)
5210 ufshcd_set_link_active(hba);
5211 else
5212 goto vendor_suspend;
5213 } else if (ufshcd_is_link_off(hba)) {
5214 ret = ufshcd_host_reset_and_restore(hba);
5215 /*
5216 * ufshcd_host_reset_and_restore() should have already
5217 * set the link state as active
5218 */
5219 if (ret || !ufshcd_is_link_active(hba))
5220 goto vendor_suspend;
5221 }
5222
5223 if (!ufshcd_is_ufs_dev_active(hba)) {
5224 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
5225 if (ret)
5226 goto set_old_link_state;
5227 }
5228
374a246e
SJ		 5229 /*
5230 * If BKOPs operations are urgently needed at this moment then
5231 * keep auto-bkops enabled or else disable it.
5232 */
5233 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 5234 hba->clk_gating.is_suspended = false;
5235
856b3483
ST		 5236 if (ufshcd_is_clkscaling_enabled(hba))
5237 devfreq_resume_device(hba->devfreq);
5238
1ab27c9c
ST		 5239 /* Schedule clock gating in case of no access to UFS device yet */
5240 ufshcd_release(hba);
57d104c1
SJ		 5241 goto out;
5242
5243set_old_link_state:
5244 ufshcd_link_state_transition(hba, old_link_state, 0);
5245vendor_suspend:
0263bcd0 5246 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 5247disable_vreg:
5248 ufshcd_vreg_set_lpm(hba);
5249disable_irq_and_vops_clks:
5250 ufshcd_disable_irq(hba);
57d104c1
SJ		 5251 ufshcd_setup_clocks(hba, false);
5252out:
5253 hba->pm_op_in_progress = 0;
5254 return ret;
5255}
5256
5257/**
5258 * ufshcd_system_suspend - system suspend routine
5259 * @hba: per adapter instance
5260 * @pm_op: runtime PM or system PM
5261 *
5262 * Check the description of ufshcd_suspend() function for more details.
5263 *
5264 * Returns 0 for success and non-zero for failure
5265 */
5266int ufshcd_system_suspend(struct ufs_hba *hba)
5267{
5268 int ret = 0;
5269
5270 if (!hba || !hba->is_powered)
233b594b 5271 return 0;
57d104c1
SJ		 5272
5273 if (pm_runtime_suspended(hba->dev)) {
5274 if (hba->rpm_lvl == hba->spm_lvl)
5275 /*
5276 * There is possibility that device may still be in
5277 * active state during the runtime suspend.
5278 */
5279 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
5280 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
5281 goto out;
5282
5283 /*
5284 * UFS device and/or UFS link low power states during runtime
5285 * suspend seems to be different than what is expected during
5286 * system suspend. Hence runtime resume the devic & link and
5287 * let the system suspend low power states to take effect.
5288 * TODO: If resume takes longer time, we might have optimize
5289 * it in future by not resuming everything if possible.
5290 */
5291 ret = ufshcd_runtime_resume(hba);
5292 if (ret)
5293 goto out;
5294 }
5295
5296 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
5297out:
e785060e
DR		 5298 if (!ret)
5299 hba->is_sys_suspended = true;
57d104c1
SJ		 5300 return ret;
5301}
5302EXPORT_SYMBOL(ufshcd_system_suspend);
5303
5304/**
5305 * ufshcd_system_resume - system resume routine
5306 * @hba: per adapter instance
5307 *
5308 * Returns 0 for success and non-zero for failure
5309 */
7a3e97b0 5310
57d104c1
SJ		 5311int ufshcd_system_resume(struct ufs_hba *hba)
5312{
5313 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
5314 /*
5315 * Let the runtime resume take care of resuming
5316 * if runtime suspended.
5317 */
5318 return 0;
5319
5320 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 5321}
57d104c1 5322EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 5323
57d104c1
SJ		 5324/**
5325 * ufshcd_runtime_suspend - runtime suspend routine
5326 * @hba: per adapter instance
5327 *
5328 * Check the description of ufshcd_suspend() function for more details.
5329 *
5330 * Returns 0 for success and non-zero for failure
5331 */
66ec6d59
SRT		 5332int ufshcd_runtime_suspend(struct ufs_hba *hba)
5333{
57d104c1 5334 if (!hba || !hba->is_powered)
66ec6d59
SRT		 5335 return 0;
5336
57d104c1 5337 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5338}
5339EXPORT_SYMBOL(ufshcd_runtime_suspend);
5340
57d104c1
SJ		 5341/**
5342 * ufshcd_runtime_resume - runtime resume routine
5343 * @hba: per adapter instance
5344 *
5345 * This function basically brings the UFS device, UniPro link and controller
5346 * to active state. Following operations are done in this function:
5347 *
5348 * 1. Turn on all the controller related clocks
5349 * 2. Bring the UniPro link out of Hibernate state
5350 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
5351 * to active state.
5352 * 4. If auto-bkops is enabled on the device, disable it.
5353 *
5354 * So following would be the possible power state after this function return
5355 * successfully:
5356 * S1: UFS device in Active state with VCC rail ON
5357 * UniPro link in Active state
5358 * All the UFS/UniPro controller clocks are ON
5359 *
5360 * Returns 0 for success and non-zero for failure
5361 */
66ec6d59
SRT		 5362int ufshcd_runtime_resume(struct ufs_hba *hba)
5363{
57d104c1 5364 if (!hba || !hba->is_powered)
66ec6d59 5365 return 0;
57d104c1
SJ		 5366 else
5367 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5368}
5369EXPORT_SYMBOL(ufshcd_runtime_resume);
5370
5371int ufshcd_runtime_idle(struct ufs_hba *hba)
5372{
5373 return 0;
5374}
5375EXPORT_SYMBOL(ufshcd_runtime_idle);
5376
57d104c1
SJ		 5377/**
5378 * ufshcd_shutdown - shutdown routine
5379 * @hba: per adapter instance
5380 *
5381 * This function would power off both UFS device and UFS link.
5382 *
5383 * Returns 0 always to allow force shutdown even in case of errors.
5384 */
5385int ufshcd_shutdown(struct ufs_hba *hba)
5386{
5387 int ret = 0;
5388
5389 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
5390 goto out;
5391
5392 if (pm_runtime_suspended(hba->dev)) {
5393 ret = ufshcd_runtime_resume(hba);
5394 if (ret)
5395 goto out;
5396 }
5397
5398 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
5399out:
5400 if (ret)
5401 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
5402 /* allow force shutdown even in case of errors */
5403 return 0;
5404}
5405EXPORT_SYMBOL(ufshcd_shutdown);
5406
7a3e97b0 5407/**
3b1d0580 5408 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 5409 * data structure memory
3b1d0580 5410 * @hba - per adapter instance
7a3e97b0 5411 */
3b1d0580 5412void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 5413{
cfdf9c91 5414 scsi_remove_host(hba->host);
7a3e97b0 5415 /* disable interrupts */
2fbd009b 5416 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 5417 ufshcd_hba_stop(hba);
7a3e97b0 5418
7a3e97b0 5419 scsi_host_put(hba->host);
5c0c28a8 5420
1ab27c9c 5421 ufshcd_exit_clk_gating(hba);
856b3483
ST		 5422 if (ufshcd_is_clkscaling_enabled(hba))
5423 devfreq_remove_device(hba->devfreq);
aa497613 5424 ufshcd_hba_exit(hba);
3b1d0580
VH		 5425}
5426EXPORT_SYMBOL_GPL(ufshcd_remove);
5427
47555a5c
YG		 5428/**
5429 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
5430 * @hba: pointer to Host Bus Adapter (HBA)
5431 */
5432void ufshcd_dealloc_host(struct ufs_hba *hba)
5433{
5434 scsi_host_put(hba->host);
5435}
5436EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
5437
ca3d7bf9
AM		 5438/**
5439 * ufshcd_set_dma_mask - Set dma mask based on the controller
5440 * addressing capability
5441 * @hba: per adapter instance
5442 *
5443 * Returns 0 for success, non-zero for failure
5444 */
5445static int ufshcd_set_dma_mask(struct ufs_hba *hba)
5446{
5447 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
5448 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
5449 return 0;
5450 }
5451 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
5452}
5453
7a3e97b0 5454/**
5c0c28a8 5455 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 5456 * @dev: pointer to device handle
5457 * @hba_handle: driver private handle
7a3e97b0
SY		 5458 * Returns 0 on success, non-zero value on failure
5459 */
5c0c28a8 5460int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 5461{
5462 struct Scsi_Host *host;
5463 struct ufs_hba *hba;
5c0c28a8 5464 int err = 0;
7a3e97b0 5465
3b1d0580
VH		 5466 if (!dev) {
5467 dev_err(dev,
5468 "Invalid memory reference for dev is NULL\n");
5469 err = -ENODEV;
7a3e97b0
SY		 5470 goto out_error;
5471 }
5472
7a3e97b0
SY		 5473 host = scsi_host_alloc(&ufshcd_driver_template,
5474 sizeof(struct ufs_hba));
5475 if (!host) {
3b1d0580 5476 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 5477 err = -ENOMEM;
3b1d0580 5478 goto out_error;
7a3e97b0
SY		 5479 }
5480 hba = shost_priv(host);
7a3e97b0 5481 hba->host = host;
3b1d0580 5482 hba->dev = dev;
5c0c28a8
SRT		 5483 *hba_handle = hba;
5484
5485out_error:
5486 return err;
5487}
5488EXPORT_SYMBOL(ufshcd_alloc_host);
5489
856b3483
ST		 5490static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
5491{
5492 int ret = 0;
5493 struct ufs_clk_info *clki;
5494 struct list_head *head = &hba->clk_list_head;
5495
5496 if (!head || list_empty(head))
5497 goto out;
5498
f06fcc71
YG		 5499 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
5500 if (ret)
5501 return ret;
5502
856b3483
ST		 5503 list_for_each_entry(clki, head, list) {
5504 if (!IS_ERR_OR_NULL(clki->clk)) {
5505 if (scale_up && clki->max_freq) {
5506 if (clki->curr_freq == clki->max_freq)
5507 continue;
5508 ret = clk_set_rate(clki->clk, clki->max_freq);
5509 if (ret) {
5510 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5511 __func__, clki->name,
5512 clki->max_freq, ret);
5513 break;
5514 }
5515 clki->curr_freq = clki->max_freq;
5516
5517 } else if (!scale_up && clki->min_freq) {
5518 if (clki->curr_freq == clki->min_freq)
5519 continue;
5520 ret = clk_set_rate(clki->clk, clki->min_freq);
5521 if (ret) {
5522 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5523 __func__, clki->name,
5524 clki->min_freq, ret);
5525 break;
5526 }
5527 clki->curr_freq = clki->min_freq;
5528 }
5529 }
5530 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
5531 clki->name, clk_get_rate(clki->clk));
5532 }
f06fcc71
YG		 5533
5534 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
5535
856b3483
ST		 5536out:
5537 return ret;
5538}
5539
5540static int ufshcd_devfreq_target(struct device *dev,
5541 unsigned long *freq, u32 flags)
5542{
5543 int err = 0;
5544 struct ufs_hba *hba = dev_get_drvdata(dev);
5545
5546 if (!ufshcd_is_clkscaling_enabled(hba))
5547 return -EINVAL;
5548
5549 if (*freq == UINT_MAX)
5550 err = ufshcd_scale_clks(hba, true);
5551 else if (*freq == 0)
5552 err = ufshcd_scale_clks(hba, false);
5553
5554 return err;
5555}
5556
5557static int ufshcd_devfreq_get_dev_status(struct device *dev,
5558 struct devfreq_dev_status *stat)
5559{
5560 struct ufs_hba *hba = dev_get_drvdata(dev);
5561 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
5562 unsigned long flags;
5563
5564 if (!ufshcd_is_clkscaling_enabled(hba))
5565 return -EINVAL;
5566
5567 memset(stat, 0, sizeof(*stat));
5568
5569 spin_lock_irqsave(hba->host->host_lock, flags);
5570 if (!scaling->window_start_t)
5571 goto start_window;
5572
5573 if (scaling->is_busy_started)
5574 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
5575 scaling->busy_start_t));
5576
5577 stat->total_time = jiffies_to_usecs((long)jiffies -
5578 (long)scaling->window_start_t);
5579 stat->busy_time = scaling->tot_busy_t;
5580start_window:
5581 scaling->window_start_t = jiffies;
5582 scaling->tot_busy_t = 0;
5583
5584 if (hba->outstanding_reqs) {
5585 scaling->busy_start_t = ktime_get();
5586 scaling->is_busy_started = true;
5587 } else {
5588 scaling->busy_start_t = ktime_set(0, 0);
5589 scaling->is_busy_started = false;
5590 }
5591 spin_unlock_irqrestore(hba->host->host_lock, flags);
5592 return 0;
5593}
5594
5595static struct devfreq_dev_profile ufs_devfreq_profile = {
5596 .polling_ms = 100,
5597 .target = ufshcd_devfreq_target,
5598 .get_dev_status = ufshcd_devfreq_get_dev_status,
5599};
5600
5c0c28a8
SRT		 5601/**
5602 * ufshcd_init - Driver initialization routine
5603 * @hba: per-adapter instance
5604 * @mmio_base: base register address
5605 * @irq: Interrupt line of device
5606 * Returns 0 on success, non-zero value on failure
5607 */
5608int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
5609{
5610 int err;
5611 struct Scsi_Host *host = hba->host;
5612 struct device *dev = hba->dev;
5613
5614 if (!mmio_base) {
5615 dev_err(hba->dev,
5616 "Invalid memory reference for mmio_base is NULL\n");
5617 err = -ENODEV;
5618 goto out_error;
5619 }
5620
3b1d0580
VH		 5621 hba->mmio_base = mmio_base;
5622 hba->irq = irq;
7a3e97b0 5623
aa497613 5624 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 5625 if (err)
5626 goto out_error;
5627
7a3e97b0
SY		 5628 /* Read capabilities registers */
5629 ufshcd_hba_capabilities(hba);
5630
5631 /* Get UFS version supported by the controller */
5632 hba->ufs_version = ufshcd_get_ufs_version(hba);
5633
2fbd009b
SJ		 5634 /* Get Interrupt bit mask per version */
5635 hba->intr_mask = ufshcd_get_intr_mask(hba);
5636
ca3d7bf9
AM		 5637 err = ufshcd_set_dma_mask(hba);
5638 if (err) {
5639 dev_err(hba->dev, "set dma mask failed\n");
5640 goto out_disable;
5641 }
5642
7a3e97b0
SY		 5643 /* Allocate memory for host memory space */
5644 err = ufshcd_memory_alloc(hba);
5645 if (err) {
3b1d0580
VH		 5646 dev_err(hba->dev, "Memory allocation failed\n");
5647 goto out_disable;
7a3e97b0
SY		 5648 }
5649
5650 /* Configure LRB */
5651 ufshcd_host_memory_configure(hba);
5652
5653 host->can_queue = hba->nutrs;
5654 host->cmd_per_lun = hba->nutrs;
5655 host->max_id = UFSHCD_MAX_ID;
0ce147d4 5656 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 5657 host->max_channel = UFSHCD_MAX_CHANNEL;
5658 host->unique_id = host->host_no;
5659 host->max_cmd_len = MAX_CDB_SIZE;
5660
7eb584db
DR		 5661 hba->max_pwr_info.is_valid = false;
5662
7a3e97b0 5663 /* Initailize wait queue for task management */
e2933132
SRT		 5664 init_waitqueue_head(&hba->tm_wq);
5665 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 5666
5667 /* Initialize work queues */
e8e7f271 5668 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 5669 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 5670
6ccf44fe
SJ		 5671 /* Initialize UIC command mutex */
5672 mutex_init(&hba->uic_cmd_mutex);
5673
5a0b0cb9
SRT		 5674 /* Initialize mutex for device management commands */
5675 mutex_init(&hba->dev_cmd.lock);
5676
5677 /* Initialize device management tag acquire wait queue */
5678 init_waitqueue_head(&hba->dev_cmd.tag_wq);
5679
1ab27c9c 5680 ufshcd_init_clk_gating(hba);
7a3e97b0 5681 /* IRQ registration */
2953f850 5682 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 5683 if (err) {
3b1d0580 5684 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 5685 goto exit_gating;
57d104c1
SJ		 5686 } else {
5687 hba->is_irq_enabled = true;
7a3e97b0
SY		 5688 }
5689
3b1d0580 5690 err = scsi_add_host(host, hba->dev);
7a3e97b0 5691 if (err) {
3b1d0580 5692 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 5693 goto exit_gating;
7a3e97b0
SY		 5694 }
5695
6ccf44fe
SJ		 5696 /* Host controller enable */
5697 err = ufshcd_hba_enable(hba);
7a3e97b0 5698 if (err) {
6ccf44fe 5699 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 5700 goto out_remove_scsi_host;
7a3e97b0 5701 }
6ccf44fe 5702
856b3483
ST		 5703 if (ufshcd_is_clkscaling_enabled(hba)) {
5704 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
5705 "simple_ondemand", NULL);
5706 if (IS_ERR(hba->devfreq)) {
5707 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
5708 PTR_ERR(hba->devfreq));
5709 goto out_remove_scsi_host;
5710 }
5711 /* Suspend devfreq until the UFS device is detected */
5712 devfreq_suspend_device(hba->devfreq);
5713 hba->clk_scaling.window_start_t = 0;
5714 }
5715
62694735
SRT		 5716 /* Hold auto suspend until async scan completes */
5717 pm_runtime_get_sync(dev);
5718
57d104c1
SJ		 5719 /*
5720 * The device-initialize-sequence hasn't been invoked yet.
5721 * Set the device to power-off state
5722 */
5723 ufshcd_set_ufs_dev_poweroff(hba);
5724
6ccf44fe
SJ		 5725 async_schedule(ufshcd_async_scan, hba);
5726
7a3e97b0
SY		 5727 return 0;
5728
3b1d0580
VH		 5729out_remove_scsi_host:
5730 scsi_remove_host(hba->host);
1ab27c9c
ST		 5731exit_gating:
5732 ufshcd_exit_clk_gating(hba);
3b1d0580 5733out_disable:
57d104c1 5734 hba->is_irq_enabled = false;
3b1d0580 5735 scsi_host_put(host);
aa497613 5736 ufshcd_hba_exit(hba);
3b1d0580
VH		 5737out_error:
5738 return err;
5739}
5740EXPORT_SYMBOL_GPL(ufshcd_init);
5741
3b1d0580
VH		 5742MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
5743MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 5744MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 5745MODULE_LICENSE("GPL");
5746MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)