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scsi: ufs: core: Probe for temperature notification support
[linux-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
67351119 1// SPDX-License-Identifier: GPL-2.0-or-later
7a3e97b0 2/*
e0eca63e 3 * Universal Flash Storage Host controller driver Core
3b1d0580 4 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 */
11
6ccf44fe 12#include <linux/async.h>
856b3483 13#include <linux/devfreq.h>
b573d484 14#include <linux/nls.h>
54b879b7 15#include <linux/of.h>
ad448378 16#include <linux/bitfield.h>
fb276f77 17#include <linux/blk-pm.h>
c72e79c0 18#include <linux/blkdev.h>
b294ff3e 19#include <scsi/scsi_driver.h>
a113eaaf
BVA		 20#include <scsi/scsi_transport.h>
21#include "../scsi_transport_api.h"
e0eca63e 22#include "ufshcd.h"
c58ab7aa 23#include "ufs_quirks.h"
53b3d9c3 24#include "unipro.h"
cbb6813e 25#include "ufs-sysfs.h"
b6cacaf2 26#include "ufs-debugfs.h"
c11a1ae9 27#include "ufs-fault-injection.h"
df032bf2 28#include "ufs_bsg.h"
df043c74 29#include "ufshcd-crypto.h"
f02bc975 30#include "ufshpb.h"
3d17b9b5 31#include <asm/unaligned.h>
7a3e97b0 32
7ff5ab47 33#define CREATE_TRACE_POINTS
34#include <trace/events/ufs.h>
35
2fbd009b
SJ		 36#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
37 UTP_TASK_REQ_COMPL |\
38 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 39/* UIC command timeout, unit: ms */
40#define UIC_CMD_TIMEOUT 500
2fbd009b 41
5a0b0cb9
SRT		 42/* NOP OUT retries waiting for NOP IN response */
43#define NOP_OUT_RETRIES 10
782e2efb
DP		 44/* Timeout after 50 msecs if NOP OUT hangs without response */
45#define NOP_OUT_TIMEOUT 50 /* msecs */
5a0b0cb9 46
68078d5c 47/* Query request retries */
10fe5888 48#define QUERY_REQ_RETRIES 3
68078d5c 49/* Query request timeout */
10fe5888 50#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 51
e2933132
SRT		 52/* Task management command timeout */
53#define TM_CMD_TIMEOUT 100 /* msecs */
54
64238fbd
YG		 55/* maximum number of retries for a general UIC command */
56#define UFS_UIC_COMMAND_RETRIES 3
57
1d337ec2
SRT		 58/* maximum number of link-startup retries */
59#define DME_LINKSTARTUP_RETRIES 3
60
87d0b4a6
YG		 61/* Maximum retries for Hibern8 enter */
62#define UIC_HIBERN8_ENTER_RETRIES 3
63
1d337ec2
SRT		 64/* maximum number of reset retries before giving up */
65#define MAX_HOST_RESET_RETRIES 5
66
68078d5c
DR		 67/* Expose the flag value from utp_upiu_query.value */
68#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
69
7d568652
SJ		 70/* Interrupt aggregation default timeout, unit: 40us */
71#define INT_AGGR_DEF_TO 0x02
72
49615ba1
SC		 73/* default delay of autosuspend: 2000 ms */
74#define RPM_AUTOSUSPEND_DELAY_MS 2000
75
51dd905b
SC		 76/* Default delay of RPM device flush delayed work */
77#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
78
09f17791
CG		 79/* Default value of wait time before gating device ref clock */
80#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
81
29707fab
KK		 82/* Polling time to wait for fDeviceInit */
83#define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
84
b294ff3e
AD		 85#define wlun_dev_to_hba(dv) shost_priv(to_scsi_device(dv)->host)
86
aa497613
SRT		 87#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
88 ({ \
89 int _ret; \
90 if (_on) \
91 _ret = ufshcd_enable_vreg(_dev, _vreg); \
92 else \
93 _ret = ufshcd_disable_vreg(_dev, _vreg); \
94 _ret; \
95 })
96
ba80917d
TW		 97#define ufshcd_hex_dump(prefix_str, buf, len) do { \
98 size_t __len = (len); \
99 print_hex_dump(KERN_ERR, prefix_str, \
100 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
101 16, 4, buf, __len, false); \
102} while (0)
103
104int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
105 const char *prefix)
106{
d6724756
MG		 107 u32 *regs;
108 size_t pos;
109
110 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
111 return -EINVAL;
ba80917d 112
cddaebaf 113 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 114 if (!regs)
115 return -ENOMEM;
116
d6724756
MG		 117 for (pos = 0; pos < len; pos += 4)
118 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
119
ba80917d
TW		 120 ufshcd_hex_dump(prefix, regs, len);
121 kfree(regs);
122
123 return 0;
124}
125EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 126
7a3e97b0
SY		 127enum {
128 UFSHCD_MAX_CHANNEL = 0,
129 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 130 UFSHCD_CMD_PER_LUN = 32,
131 UFSHCD_CAN_QUEUE = 32,
132};
133
3441da7d
SRT		 134/* UFSHCD error handling flags */
135enum {
136 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 137};
138
e8e7f271
SRT		 139/* UFSHCD UIC layer error flags */
140enum {
141 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 142 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
143 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
144 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
145 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
146 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
2355b66e 147 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
e8e7f271
SRT		 148};
149
3441da7d 150#define ufshcd_set_eh_in_progress(h) \
9c490d2d 151 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 152#define ufshcd_eh_in_progress(h) \
9c490d2d 153 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 154#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 155 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 156
cbb6813e 157struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
e2ac7ab2
BVA		 158 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
159 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
161 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
162 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
163 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
fe1d4c2e
AH		 164 /*
165 * For DeepSleep, the link is first put in hibern8 and then off.
166 * Leaving the link in hibern8 is not supported.
167 */
e2ac7ab2 168 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
57d104c1
SJ		 169};
170
171static inline enum ufs_dev_pwr_mode
172ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
173{
174 return ufs_pm_lvl_states[lvl].dev_state;
175}
176
177static inline enum uic_link_state
178ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
179{
180 return ufs_pm_lvl_states[lvl].link_state;
181}
182
0c8f7586 183static inline enum ufs_pm_level
184ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
185 enum uic_link_state link_state)
186{
187 enum ufs_pm_level lvl;
188
189 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
190 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
191 (ufs_pm_lvl_states[lvl].link_state == link_state))
192 return lvl;
193 }
194
195 /* if no match found, return the level 0 */
196 return UFS_PM_LVL_0;
197}
198
56d4a186
SJ		 199static struct ufs_dev_fix ufs_fixups[] = {
200 /* UFS cards deviations table */
c0a18ee0 201 UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
63522bf3
BH		 202 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
203 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ),
56d4a186 204 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
ed0b40ff
SC		 205 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
206 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
56d4a186 207 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
ed0b40ff
SC		 208 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
209 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
210 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
211 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 212 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
214 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
215 UFS_DEVICE_QUIRK_PA_TACTIVATE),
216 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
217 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 218 END_FIX
219};
220
9333d775 221static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 222static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 223static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 224static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 225static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 226static void ufshcd_hba_exit(struct ufs_hba *hba);
1918651f 227static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
1b9e2141 228static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
1ab27c9c 229static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
1ab27c9c 230static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 231static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 232static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 233static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
234static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 235static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 236static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 237static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 238static int ufshcd_change_power_mode(struct ufs_hba *hba,
239 struct ufs_pa_layer_attr *pwr_mode);
c72e79c0
CG		 240static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
241static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
242static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
243 struct ufs_vreg *vreg);
307348f6 244static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
3b5f3c0d
YH		 245static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
246static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
dd7143e2
CG		 247static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
248static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
3d17b9b5 249
5231d38c 250static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 251{
57d104c1 252 if (!hba->is_irq_enabled) {
5231d38c 253 enable_irq(hba->irq);
57d104c1
SJ		 254 hba->is_irq_enabled = true;
255 }
57d104c1
SJ		 256}
257
258static inline void ufshcd_disable_irq(struct ufs_hba *hba)
259{
260 if (hba->is_irq_enabled) {
5231d38c 261 disable_irq(hba->irq);
57d104c1
SJ		 262 hba->is_irq_enabled = false;
263 }
264}
3441da7d 265
3d17b9b5
AD		 266static inline void ufshcd_wb_config(struct ufs_hba *hba)
267{
79e3520f 268 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 269 return;
270
3b5f3c0d
YH		 271 ufshcd_wb_toggle(hba, true);
272
273 ufshcd_wb_toggle_flush_during_h8(hba, true);
21acf460
SC		 274 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
275 ufshcd_wb_toggle_flush(hba, true);
3d17b9b5
AD		 276}
277
38135535
SJ		 278static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
279{
280 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
281 scsi_unblock_requests(hba->host);
282}
283
284static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
285{
286 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
287 scsi_block_requests(hba->host);
288}
289
6667e6d9 290static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 291 enum ufs_trace_str_t str_t)
6667e6d9
OS		 292{
293 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
89ac2c3b 294 struct utp_upiu_header *header;
6667e6d9 295
9d5095e7
BH		 296 if (!trace_ufshcd_upiu_enabled())
297 return;
298
89ac2c3b
BH		 299 if (str_t == UFS_CMD_SEND)
300 header = &rq->header;
301 else
302 header = &hba->lrb[tag].ucd_rsp_ptr->header;
303
304 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
867fdc2d 305 UFS_TSF_CDB);
6667e6d9
OS		 306}
307
fb475b74
AA		 308static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
309 enum ufs_trace_str_t str_t,
310 struct utp_upiu_req *rq_rsp)
6667e6d9 311{
9d5095e7
BH		 312 if (!trace_ufshcd_upiu_enabled())
313 return;
6667e6d9 314
be20b51c 315 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
867fdc2d 316 &rq_rsp->qr, UFS_TSF_OSF);
6667e6d9
OS		 317}
318
319static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 320 enum ufs_trace_str_t str_t)
6667e6d9 321{
6667e6d9 322 int off = (int)tag - hba->nutrs;
391e388f 323 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 324
9d5095e7
BH		 325 if (!trace_ufshcd_upiu_enabled())
326 return;
327
0ed083e9 328 if (str_t == UFS_TM_SEND)
1352eec8
GS		 329 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
330 &descp->upiu_req.req_header,
331 &descp->upiu_req.input_param1,
332 UFS_TSF_TM_INPUT);
0ed083e9 333 else
1352eec8
GS		 334 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
335 &descp->upiu_rsp.rsp_header,
336 &descp->upiu_rsp.output_param1,
337 UFS_TSF_TM_OUTPUT);
6667e6d9
OS		 338}
339
aa5c6979
SC		 340static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
341 struct uic_command *ucmd,
28fa68fc 342 enum ufs_trace_str_t str_t)
aa5c6979
SC		 343{
344 u32 cmd;
345
346 if (!trace_ufshcd_uic_command_enabled())
347 return;
348
28fa68fc 349 if (str_t == UFS_CMD_SEND)
aa5c6979
SC		 350 cmd = ucmd->command;
351 else
352 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
353
28fa68fc 354 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
aa5c6979
SC		 355 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
356 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
357 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
358}
359
28fa68fc
BH		 360static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
361 enum ufs_trace_str_t str_t)
1a07f2d9 362{
102851fc 363 u64 lba;
69a314d6 364 u8 opcode = 0, group_id = 0;
1a07f2d9 365 u32 intr, doorbell;
e7c3b379 366 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 367 struct scsi_cmnd *cmd = lrbp->cmd;
3f2c1002 368 struct request *rq = scsi_cmd_to_rq(cmd);
1a07f2d9
LS		 369 int transfer_len = -1;
370
44b5de36
BH		 371 if (!cmd)
372 return;
373
44b5de36
BH		 374 /* trace UPIU also */
375 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
f0101af4
BH		 376 if (!trace_ufshcd_command_enabled())
377 return;
378
44b5de36 379 opcode = cmd->cmnd[0];
54815088 380 lba = scsi_get_lba(cmd);
44b5de36
BH		 381
382 if (opcode == READ_10 || opcode == WRITE_10) {
383 /*
384 * Currently we only fully trace read(10) and write(10) commands
385 */
386 transfer_len =
387 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
388 if (opcode == WRITE_10)
389 group_id = lrbp->cmd->cmnd[6];
390 } else if (opcode == UNMAP) {
391 /*
392 * The number of Bytes to be unmapped beginning with the lba.
393 */
3f2c1002 394 transfer_len = blk_rq_bytes(rq);
1a07f2d9
LS		 395 }
396
397 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
398 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
28fa68fc 399 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
69a314d6 400 doorbell, transfer_len, intr, lba, opcode, group_id);
1a07f2d9
LS		 401}
402
ff8e20c6
DR		 403static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
404{
405 struct ufs_clk_info *clki;
406 struct list_head *head = &hba->clk_list_head;
407
566ec9ad 408 if (list_empty(head))
ff8e20c6
DR		 409 return;
410
411 list_for_each_entry(clki, head, list) {
412 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
413 clki->max_freq)
414 dev_err(hba->dev, "clk: %s, rate: %u\n",
415 clki->name, clki->curr_freq);
416 }
417}
418
e965e5e0
SC		 419static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
420 char *err_name)
ff8e20c6
DR		 421{
422 int i;
27752647 423 bool found = false;
e965e5e0 424 struct ufs_event_hist *e;
ff8e20c6 425
e965e5e0
SC		 426 if (id >= UFS_EVT_CNT)
427 return;
ff8e20c6 428
e965e5e0 429 e = &hba->ufs_stats.event[id];
ff8e20c6 430
e965e5e0
SC		 431 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
432 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
433
434 if (e->tstamp[p] == 0)
ff8e20c6 435 continue;
c5397f13 436 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
e965e5e0 437 e->val[p], ktime_to_us(e->tstamp[p]));
27752647 438 found = true;
ff8e20c6 439 }
27752647
SC		 440
441 if (!found)
fd1fb4d5 442 dev_err(hba->dev, "No record of %s\n", err_name);
bafd09f8
DH		 443 else
444 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
ff8e20c6
DR		 445}
446
e965e5e0 447static void ufshcd_print_evt_hist(struct ufs_hba *hba)
66cc820f 448{
ba80917d 449 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
ff8e20c6 450
e965e5e0
SC		 451 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
452 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
453 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
454 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
455 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
456 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
457 "auto_hibern8_err");
458 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
459 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
460 "link_startup_fail");
461 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
462 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
463 "suspend_fail");
464 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
465 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
466 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
ff8e20c6 467
7c486d91 468 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 469}
470
471static
472void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
473{
474 struct ufshcd_lrb *lrbp;
7fabb77b 475 int prdt_length;
66cc820f
DR		 476 int tag;
477
478 for_each_set_bit(tag, &bitmap, hba->nutrs) {
479 lrbp = &hba->lrb[tag];
480
ff8e20c6
DR		 481 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
482 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 483 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
484 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 485 dev_err(hba->dev,
486 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
487 tag, (u64)lrbp->utrd_dma_addr);
488
66cc820f
DR		 489 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
490 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 491 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
492 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 493 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
494 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 495 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
496 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 497 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
498 sizeof(struct utp_upiu_rsp));
66cc820f 499
7fabb77b
GB		 500 prdt_length = le16_to_cpu(
501 lrbp->utr_descriptor_ptr->prd_table_length);
cc770ce3
EB		 502 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
503 prdt_length /= sizeof(struct ufshcd_sg_entry);
504
7fabb77b
GB		 505 dev_err(hba->dev,
506 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
507 tag, prdt_length,
508 (u64)lrbp->ucd_prdt_dma_addr);
509
510 if (pr_prdt)
66cc820f 511 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 512 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 513 }
514}
515
516static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
517{
66cc820f
DR		 518 int tag;
519
520 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 521 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
522
66cc820f 523 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 524 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 525 }
526}
527
6ba65588
GB		 528static void ufshcd_print_host_state(struct ufs_hba *hba)
529{
3f8af604
CG		 530 struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
531
6ba65588 532 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 533 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
534 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 535 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
536 hba->saved_err, hba->saved_uic_err);
537 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
538 hba->curr_dev_pwr_mode, hba->uic_link_state);
539 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
540 hba->pm_op_in_progress, hba->is_sys_suspended);
541 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
542 hba->auto_bkops_enabled, hba->host->host_self_blocked);
543 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
3f8af604
CG		 544 dev_err(hba->dev,
545 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
546 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
547 hba->ufs_stats.hibern8_exit_cnt);
548 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
549 ktime_to_us(hba->ufs_stats.last_intr_ts),
550 hba->ufs_stats.last_intr_status);
6ba65588
GB		 551 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
552 hba->eh_flags, hba->req_abort_count);
3f8af604
CG		 553 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
554 hba->ufs_version, hba->capabilities, hba->caps);
6ba65588
GB		 555 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
556 hba->dev_quirks);
3f8af604
CG		 557 if (sdev_ufs)
558 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
559 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
560
561 ufshcd_print_clk_freqs(hba);
6ba65588
GB		 562}
563
ff8e20c6
DR		 564/**
565 * ufshcd_print_pwr_info - print power params as saved in hba
566 * power info
567 * @hba: per-adapter instance
568 */
569static void ufshcd_print_pwr_info(struct ufs_hba *hba)
570{
571 static const char * const names[] = {
572 "INVALID MODE",
573 "FAST MODE",
574 "SLOW_MODE",
575 "INVALID MODE",
576 "FASTAUTO_MODE",
577 "SLOWAUTO_MODE",
578 "INVALID MODE",
579 };
580
581 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
582 __func__,
583 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
584 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
585 names[hba->pwr_info.pwr_rx],
586 names[hba->pwr_info.pwr_tx],
587 hba->pwr_info.hs_rate);
588}
589
31a5d9ca
SC		 590static void ufshcd_device_reset(struct ufs_hba *hba)
591{
592 int err;
593
594 err = ufshcd_vops_device_reset(hba);
595
596 if (!err) {
597 ufshcd_set_ufs_dev_active(hba);
598 if (ufshcd_is_wb_allowed(hba)) {
4cd48995
BH		 599 hba->dev_info.wb_enabled = false;
600 hba->dev_info.wb_buf_flush_enabled = false;
31a5d9ca
SC		 601 }
602 }
603 if (err != -EOPNOTSUPP)
604 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
605}
606
5c955c10
SC		 607void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
608{
609 if (!us)
610 return;
611
612 if (us < 10)
613 udelay(us);
614 else
615 usleep_range(us, us + tolerance);
616}
617EXPORT_SYMBOL_GPL(ufshcd_delay_us);
618
5cac1095 619/**
5a0b0cb9 620 * ufshcd_wait_for_register - wait for register value to change
5cac1095
BVA		 621 * @hba: per-adapter interface
622 * @reg: mmio register offset
623 * @mask: mask to apply to the read register value
624 * @val: value to wait for
625 * @interval_us: polling interval in microseconds
626 * @timeout_ms: timeout in milliseconds
5a0b0cb9 627 *
5cac1095
BVA		 628 * Return:
629 * -ETIMEDOUT on error, zero on success.
5a0b0cb9 630 */
596585a2
YG		 631int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
632 u32 val, unsigned long interval_us,
5cac1095 633 unsigned long timeout_ms)
5a0b0cb9
SRT		 634{
635 int err = 0;
636 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
637
638 /* ignore bits that we don't intend to wait on */
639 val = val & mask;
640
641 while ((ufshcd_readl(hba, reg) & mask) != val) {
5cac1095 642 usleep_range(interval_us, interval_us + 50);
5a0b0cb9
SRT		 643 if (time_after(jiffies, timeout)) {
644 if ((ufshcd_readl(hba, reg) & mask) != val)
645 err = -ETIMEDOUT;
646 break;
647 }
648 }
649
650 return err;
651}
652
2fbd009b
SJ		 653/**
654 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 655 * @hba: Pointer to adapter instance
2fbd009b
SJ		 656 *
657 * Returns interrupt bit mask per version
658 */
659static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
660{
51428818
CC		 661 if (hba->ufs_version == ufshci_version(1, 0))
662 return INTERRUPT_MASK_ALL_VER_10;
663 if (hba->ufs_version <= ufshci_version(2, 0))
664 return INTERRUPT_MASK_ALL_VER_11;
c01848c6 665
51428818 666 return INTERRUPT_MASK_ALL_VER_21;
2fbd009b
SJ		 667}
668
7a3e97b0
SY		 669/**
670 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 671 * @hba: Pointer to adapter instance
7a3e97b0
SY		 672 *
673 * Returns UFSHCI version supported by the controller
674 */
675static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
676{
51428818
CC		 677 u32 ufshci_ver;
678
0263bcd0 679 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
51428818
CC		 680 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
681 else
682 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
9949e702 683
51428818
CC		 684 /*
685 * UFSHCI v1.x uses a different version scheme, in order
686 * to allow the use of comparisons with the ufshci_version
687 * function, we convert it to the same scheme as ufs 2.0+.
688 */
689 if (ufshci_ver & 0x00010000)
690 return ufshci_version(1, ufshci_ver & 0x00000100);
691
692 return ufshci_ver;
7a3e97b0
SY		 693}
694
695/**
696 * ufshcd_is_device_present - Check if any device connected to
697 * the host controller
5c0c28a8 698 * @hba: pointer to adapter instance
7a3e97b0 699 *
c9e6010b 700 * Returns true if device present, false if no device detected
7a3e97b0 701 */
c9e6010b 702static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 703{
5c0c28a8 704 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 705 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 706}
707
708/**
709 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 710 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 711 *
712 * This function is used to get the OCS field from UTRD
713 * Returns the OCS field in the UTRD
714 */
715static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
716{
e8c8e82a 717 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 718}
719
7a3e97b0
SY		 720/**
721 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
722 * @hba: per adapter instance
723 * @pos: position of the bit to be cleared
724 */
725static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
726{
87183841
AA		 727 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
728 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
729 else
730 ufshcd_writel(hba, ~(1 << pos),
731 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 732}
733
734/**
735 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
736 * @hba: per adapter instance
737 * @pos: position of the bit to be cleared
738 */
739static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
740{
87183841
AA		 741 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
742 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
743 else
744 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 745}
746
747/**
748 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
749 * @reg: Register value of host controller status
750 *
751 * Returns integer, 0 on Success and positive value if failed
752 */
753static inline int ufshcd_get_lists_status(u32 reg)
754{
6cf16115 755 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 756}
757
758/**
759 * ufshcd_get_uic_cmd_result - Get the UIC command result
760 * @hba: Pointer to adapter instance
761 *
762 * This function gets the result of UIC command completion
763 * Returns 0 on success, non zero value on error
764 */
765static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
766{
b873a275 767 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 768 MASK_UIC_COMMAND_RESULT;
769}
770
12b4fdb4
SJ		 771/**
772 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
773 * @hba: Pointer to adapter instance
774 *
775 * This function gets UIC command argument3
776 * Returns 0 on success, non zero value on error
777 */
778static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
779{
780 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
781}
782
7a3e97b0 783/**
5a0b0cb9 784 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 785 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 786 */
787static inline int
5a0b0cb9 788ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 789{
5a0b0cb9 790 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 791}
792
793/**
794 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
795 * @ucd_rsp_ptr: pointer to response UPIU
796 *
797 * This function gets the response status and scsi_status from response UPIU
798 * Returns the response result code.
799 */
800static inline int
801ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
802{
803 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
804}
805
1c2623c5
SJ		 806/*
807 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
808 * from response UPIU
809 * @ucd_rsp_ptr: pointer to response UPIU
810 *
811 * Return the data segment length.
812 */
813static inline unsigned int
814ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
815{
816 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
817 MASK_RSP_UPIU_DATA_SEG_LEN;
818}
819
66ec6d59
SRT		 820/**
821 * ufshcd_is_exception_event - Check if the device raised an exception event
822 * @ucd_rsp_ptr: pointer to response UPIU
823 *
824 * The function checks if the device raised an exception event indicated in
825 * the Device Information field of response UPIU.
826 *
827 * Returns true if exception is raised, false otherwise.
828 */
829static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
830{
831 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
832 MASK_RSP_EXCEPTION_EVENT ? true : false;
833}
834
7a3e97b0 835/**
7d568652 836 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 837 * @hba: per adapter instance
7a3e97b0
SY		 838 */
839static inline void
7d568652 840ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 841{
7d568652
SJ		 842 ufshcd_writel(hba, INT_AGGR_ENABLE |
843 INT_AGGR_COUNTER_AND_TIMER_RESET,
844 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
845}
846
847/**
848 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
849 * @hba: per adapter instance
850 * @cnt: Interrupt aggregation counter threshold
851 * @tmout: Interrupt aggregation timeout value
852 */
853static inline void
854ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
855{
856 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
857 INT_AGGR_COUNTER_THLD_VAL(cnt) |
858 INT_AGGR_TIMEOUT_VAL(tmout),
859 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 860}
861
b852190e
YG		 862/**
863 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
864 * @hba: per adapter instance
865 */
866static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
867{
868 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
869}
870
7a3e97b0
SY		 871/**
872 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
873 * When run-stop registers are set to 1, it indicates the
874 * host controller that it can process the requests
875 * @hba: per adapter instance
876 */
877static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
878{
b873a275
SJ		 879 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
880 REG_UTP_TASK_REQ_LIST_RUN_STOP);
881 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
882 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 883}
884
7a3e97b0
SY		 885/**
886 * ufshcd_hba_start - Start controller initialization sequence
887 * @hba: per adapter instance
888 */
889static inline void ufshcd_hba_start(struct ufs_hba *hba)
890{
df043c74
ST		 891 u32 val = CONTROLLER_ENABLE;
892
893 if (ufshcd_crypto_enable(hba))
894 val |= CRYPTO_GENERAL_ENABLE;
895
896 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 897}
898
899/**
900 * ufshcd_is_hba_active - Get controller state
901 * @hba: per adapter instance
902 *
c9e6010b 903 * Returns false if controller is active, true otherwise
7a3e97b0 904 */
c9e6010b 905static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 906{
4a8eec2b
TK		 907 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
908 ? false : true;
7a3e97b0
SY		 909}
910
37113106
YG		 911u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
912{
913 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
51428818 914 if (hba->ufs_version <= ufshci_version(1, 1))
37113106
YG		 915 return UFS_UNIPRO_VER_1_41;
916 else
917 return UFS_UNIPRO_VER_1_6;
918}
919EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
920
921static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
922{
923 /*
924 * If both host and device support UniPro ver1.6 or later, PA layer
925 * parameters tuning happens during link startup itself.
926 *
927 * We can manually tune PA layer parameters if either host or device
928 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
929 * logic simple, we will only do manual tuning if local unipro version
930 * doesn't support ver1.6 or later.
931 */
932 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
933 return true;
934 else
935 return false;
936}
937
394b949f
SJ		 938/**
939 * ufshcd_set_clk_freq - set UFS controller clock frequencies
940 * @hba: per adapter instance
941 * @scale_up: If True, set max possible frequency othewise set low frequency
942 *
943 * Returns 0 if successful
944 * Returns < 0 for any other errors
945 */
946static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 947{
948 int ret = 0;
949 struct ufs_clk_info *clki;
950 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 951
566ec9ad 952 if (list_empty(head))
a3cd5ec5 953 goto out;
954
a3cd5ec5 955 list_for_each_entry(clki, head, list) {
956 if (!IS_ERR_OR_NULL(clki->clk)) {
957 if (scale_up && clki->max_freq) {
958 if (clki->curr_freq == clki->max_freq)
959 continue;
960
a3cd5ec5 961 ret = clk_set_rate(clki->clk, clki->max_freq);
962 if (ret) {
963 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
964 __func__, clki->name,
965 clki->max_freq, ret);
966 break;
967 }
968 trace_ufshcd_clk_scaling(dev_name(hba->dev),
969 "scaled up", clki->name,
970 clki->curr_freq,
971 clki->max_freq);
972
973 clki->curr_freq = clki->max_freq;
974
975 } else if (!scale_up && clki->min_freq) {
976 if (clki->curr_freq == clki->min_freq)
977 continue;
978
a3cd5ec5 979 ret = clk_set_rate(clki->clk, clki->min_freq);
980 if (ret) {
981 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
982 __func__, clki->name,
983 clki->min_freq, ret);
984 break;
985 }
986 trace_ufshcd_clk_scaling(dev_name(hba->dev),
987 "scaled down", clki->name,
988 clki->curr_freq,
989 clki->min_freq);
990 clki->curr_freq = clki->min_freq;
991 }
992 }
993 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
994 clki->name, clk_get_rate(clki->clk));
995 }
996
394b949f
SJ		 997out:
998 return ret;
999}
1000
1001/**
1002 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1003 * @hba: per adapter instance
1004 * @scale_up: True if scaling up and false if scaling down
1005 *
1006 * Returns 0 if successful
1007 * Returns < 0 for any other errors
1008 */
1009static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1010{
1011 int ret = 0;
1012 ktime_t start = ktime_get();
1013
1014 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1015 if (ret)
1016 goto out;
1017
1018 ret = ufshcd_set_clk_freq(hba, scale_up);
1019 if (ret)
1020 goto out;
1021
a3cd5ec5 1022 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 1023 if (ret)
1024 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 1025
1026out:
394b949f 1027 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 1028 (scale_up ? "up" : "down"),
1029 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1030 return ret;
1031}
1032
1033/**
1034 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1035 * @hba: per adapter instance
1036 * @scale_up: True if scaling up and false if scaling down
1037 *
1038 * Returns true if scaling is required, false otherwise.
1039 */
1040static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1041 bool scale_up)
1042{
1043 struct ufs_clk_info *clki;
1044 struct list_head *head = &hba->clk_list_head;
1045
566ec9ad 1046 if (list_empty(head))
a3cd5ec5 1047 return false;
1048
1049 list_for_each_entry(clki, head, list) {
1050 if (!IS_ERR_OR_NULL(clki->clk)) {
1051 if (scale_up && clki->max_freq) {
1052 if (clki->curr_freq == clki->max_freq)
1053 continue;
1054 return true;
1055 } else if (!scale_up && clki->min_freq) {
1056 if (clki->curr_freq == clki->min_freq)
1057 continue;
1058 return true;
1059 }
1060 }
1061 }
1062
1063 return false;
1064}
1065
1066static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1067 u64 wait_timeout_us)
1068{
1069 unsigned long flags;
1070 int ret = 0;
1071 u32 tm_doorbell;
1072 u32 tr_doorbell;
1073 bool timeout = false, do_last_check = false;
1074 ktime_t start;
1075
1076 ufshcd_hold(hba, false);
1077 spin_lock_irqsave(hba->host->host_lock, flags);
1078 /*
1079 * Wait for all the outstanding tasks/transfer requests.
1080 * Verify by checking the doorbell registers are clear.
1081 */
1082 start = ktime_get();
1083 do {
1084 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1085 ret = -EBUSY;
1086 goto out;
1087 }
1088
1089 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1090 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1091 if (!tm_doorbell && !tr_doorbell) {
1092 timeout = false;
1093 break;
1094 } else if (do_last_check) {
1095 break;
1096 }
1097
1098 spin_unlock_irqrestore(hba->host->host_lock, flags);
1099 schedule();
1100 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1101 wait_timeout_us) {
1102 timeout = true;
1103 /*
1104 * We might have scheduled out for long time so make
1105 * sure to check if doorbells are cleared by this time
1106 * or not.
1107 */
1108 do_last_check = true;
1109 }
1110 spin_lock_irqsave(hba->host->host_lock, flags);
1111 } while (tm_doorbell || tr_doorbell);
1112
1113 if (timeout) {
1114 dev_err(hba->dev,
1115 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1116 __func__, tm_doorbell, tr_doorbell);
1117 ret = -EBUSY;
1118 }
1119out:
1120 spin_unlock_irqrestore(hba->host->host_lock, flags);
1121 ufshcd_release(hba);
1122 return ret;
1123}
1124
1125/**
1126 * ufshcd_scale_gear - scale up/down UFS gear
1127 * @hba: per adapter instance
1128 * @scale_up: True for scaling up gear and false for scaling down
1129 *
1130 * Returns 0 for success,
1131 * Returns -EBUSY if scaling can't happen at this time
1132 * Returns non-zero for any other errors
1133 */
1134static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1135{
a3cd5ec5 1136 int ret = 0;
1137 struct ufs_pa_layer_attr new_pwr_info;
1138
1139 if (scale_up) {
1140 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1141 sizeof(struct ufs_pa_layer_attr));
1142 } else {
1143 memcpy(&new_pwr_info, &hba->pwr_info,
1144 sizeof(struct ufs_pa_layer_attr));
1145
29b87e92
CG		 1146 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1147 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
a3cd5ec5 1148 /* save the current power mode */
1149 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1150 &hba->pwr_info,
1151 sizeof(struct ufs_pa_layer_attr));
1152
1153 /* scale down gear */
29b87e92
CG		 1154 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1155 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
a3cd5ec5 1156 }
1157 }
1158
1159 /* check if the power mode needs to be changed or not? */
6a9df818 1160 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1161 if (ret)
1162 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1163 __func__, ret,
1164 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1165 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1166
1167 return ret;
1168}
1169
1170static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1171{
1172 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1173 int ret = 0;
1174 /*
1175 * make sure that there are no outstanding requests when
1176 * clock scaling is in progress
1177 */
38135535 1178 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1179 down_write(&hba->clk_scaling_lock);
0e9d4ca4
CG		 1180
1181 if (!hba->clk_scaling.is_allowed ||
1182 ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
a3cd5ec5 1183 ret = -EBUSY;
1184 up_write(&hba->clk_scaling_lock);
38135535 1185 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1186 goto out;
a3cd5ec5 1187 }
1188
0e9d4ca4
CG		 1189 /* let's not get into low power until clock scaling is completed */
1190 ufshcd_hold(hba, false);
1191
1192out:
a3cd5ec5 1193 return ret;
1194}
1195
0e9d4ca4 1196static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
a3cd5ec5 1197{
0e9d4ca4
CG		 1198 if (writelock)
1199 up_write(&hba->clk_scaling_lock);
1200 else
1201 up_read(&hba->clk_scaling_lock);
38135535 1202 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1203 ufshcd_release(hba);
a3cd5ec5 1204}
1205
1206/**
1207 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1208 * @hba: per adapter instance
1209 * @scale_up: True for scaling up and false for scalin down
1210 *
1211 * Returns 0 for success,
1212 * Returns -EBUSY if scaling can't happen at this time
1213 * Returns non-zero for any other errors
1214 */
1215static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1216{
1217 int ret = 0;
0e9d4ca4 1218 bool is_writelock = true;
401f1e44 1219
a3cd5ec5 1220 ret = ufshcd_clock_scaling_prepare(hba);
1221 if (ret)
0e9d4ca4 1222 return ret;
a3cd5ec5 1223
1224 /* scale down the gear before scaling down clocks */
1225 if (!scale_up) {
1226 ret = ufshcd_scale_gear(hba, false);
1227 if (ret)
394b949f 1228 goto out_unprepare;
a3cd5ec5 1229 }
1230
1231 ret = ufshcd_scale_clks(hba, scale_up);
1232 if (ret) {
1233 if (!scale_up)
1234 ufshcd_scale_gear(hba, true);
394b949f 1235 goto out_unprepare;
a3cd5ec5 1236 }
1237
1238 /* scale up the gear after scaling up clocks */
1239 if (scale_up) {
1240 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1241 if (ret) {
a3cd5ec5 1242 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1243 goto out_unprepare;
1244 }
a3cd5ec5 1245 }
1246
3d17b9b5 1247 /* Enable Write Booster if we have scaled up else disable it */
0e9d4ca4
CG		 1248 downgrade_write(&hba->clk_scaling_lock);
1249 is_writelock = false;
3b5f3c0d 1250 ufshcd_wb_toggle(hba, scale_up);
3d17b9b5 1251
394b949f 1252out_unprepare:
0e9d4ca4 1253 ufshcd_clock_scaling_unprepare(hba, is_writelock);
a3cd5ec5 1254 return ret;
1255}
1256
401f1e44 1257static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1258{
1259 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1260 clk_scaling.suspend_work);
1261 unsigned long irq_flags;
1262
1263 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1264 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1265 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1266 return;
1267 }
1268 hba->clk_scaling.is_suspended = true;
1269 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1270
1271 __ufshcd_suspend_clkscaling(hba);
1272}
1273
1274static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1275{
1276 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1277 clk_scaling.resume_work);
1278 unsigned long irq_flags;
1279
1280 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1281 if (!hba->clk_scaling.is_suspended) {
1282 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1283 return;
1284 }
1285 hba->clk_scaling.is_suspended = false;
1286 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1287
1288 devfreq_resume_device(hba->devfreq);
1289}
1290
a3cd5ec5 1291static int ufshcd_devfreq_target(struct device *dev,
1292 unsigned long *freq, u32 flags)
1293{
1294 int ret = 0;
1295 struct ufs_hba *hba = dev_get_drvdata(dev);
1296 ktime_t start;
401f1e44 1297 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1298 struct list_head *clk_list = &hba->clk_list_head;
1299 struct ufs_clk_info *clki;
a3cd5ec5 1300 unsigned long irq_flags;
1301
1302 if (!ufshcd_is_clkscaling_supported(hba))
1303 return -EINVAL;
1304
91831d33
AD		 1305 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1306 /* Override with the closest supported frequency */
1307 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1308 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1309 if (ufshcd_eh_in_progress(hba)) {
1310 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1311 return 0;
1312 }
1313
401f1e44 1314 if (!hba->clk_scaling.active_reqs)
1315 sched_clk_scaling_suspend_work = true;
1316
092b4558
BA		 1317 if (list_empty(clk_list)) {
1318 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1319 goto out;
1320 }
1321
91831d33 1322 /* Decide based on the rounded-off frequency and update */
092b4558 1323 scale_up = (*freq == clki->max_freq) ? true : false;
91831d33
AD		 1324 if (!scale_up)
1325 *freq = clki->min_freq;
1326 /* Update the frequency */
401f1e44 1327 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1328 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1329 ret = 0;
1330 goto out; /* no state change required */
a3cd5ec5 1331 }
1332 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1333
1334 start = ktime_get();
a3cd5ec5 1335 ret = ufshcd_devfreq_scale(hba, scale_up);
1336
a3cd5ec5 1337 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1338 (scale_up ? "up" : "down"),
1339 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1340
401f1e44 1341out:
1342 if (sched_clk_scaling_suspend_work)
1343 queue_work(hba->clk_scaling.workq,
1344 &hba->clk_scaling.suspend_work);
1345
a3cd5ec5 1346 return ret;
1347}
1348
7252a360
BVA		 1349static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1350{
1351 int *busy = priv;
1352
1353 WARN_ON_ONCE(reserved);
1354 (*busy)++;
1355 return false;
1356}
1357
1358/* Whether or not any tag is in use by a request that is in progress. */
1359static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1360{
1361 struct request_queue *q = hba->cmd_queue;
1362 int busy = 0;
1363
1364 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1365 return busy;
1366}
a3cd5ec5 1367
1368static int ufshcd_devfreq_get_dev_status(struct device *dev,
1369 struct devfreq_dev_status *stat)
1370{
1371 struct ufs_hba *hba = dev_get_drvdata(dev);
1372 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1373 unsigned long flags;
91831d33
AD		 1374 struct list_head *clk_list = &hba->clk_list_head;
1375 struct ufs_clk_info *clki;
b1bf66d1 1376 ktime_t curr_t;
a3cd5ec5 1377
1378 if (!ufshcd_is_clkscaling_supported(hba))
1379 return -EINVAL;
1380
1381 memset(stat, 0, sizeof(*stat));
1382
1383 spin_lock_irqsave(hba->host->host_lock, flags);
b1bf66d1 1384 curr_t = ktime_get();
a3cd5ec5 1385 if (!scaling->window_start_t)
1386 goto start_window;
1387
91831d33
AD		 1388 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1389 /*
1390 * If current frequency is 0, then the ondemand governor considers
1391 * there's no initial frequency set. And it always requests to set
1392 * to max. frequency.
1393 */
1394 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1395 if (scaling->is_busy_started)
b1bf66d1
SC		 1396 scaling->tot_busy_t += ktime_us_delta(curr_t,
1397 scaling->busy_start_t);
a3cd5ec5 1398
b1bf66d1 1399 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
a3cd5ec5 1400 stat->busy_time = scaling->tot_busy_t;
1401start_window:
b1bf66d1 1402 scaling->window_start_t = curr_t;
a3cd5ec5 1403 scaling->tot_busy_t = 0;
1404
1405 if (hba->outstanding_reqs) {
b1bf66d1 1406 scaling->busy_start_t = curr_t;
a3cd5ec5 1407 scaling->is_busy_started = true;
1408 } else {
1409 scaling->busy_start_t = 0;
1410 scaling->is_busy_started = false;
1411 }
1412 spin_unlock_irqrestore(hba->host->host_lock, flags);
1413 return 0;
1414}
1415
deac444f
BA		 1416static int ufshcd_devfreq_init(struct ufs_hba *hba)
1417{
092b4558
BA		 1418 struct list_head *clk_list = &hba->clk_list_head;
1419 struct ufs_clk_info *clki;
deac444f
BA		 1420 struct devfreq *devfreq;
1421 int ret;
1422
092b4558
BA		 1423 /* Skip devfreq if we don't have any clocks in the list */
1424 if (list_empty(clk_list))
1425 return 0;
1426
1427 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1428 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1429 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1430
90b8491c
SC		 1431 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1432 &hba->vps->ondemand_data);
092b4558 1433 devfreq = devfreq_add_device(hba->dev,
90b8491c 1434 &hba->vps->devfreq_profile,
deac444f 1435 DEVFREQ_GOV_SIMPLE_ONDEMAND,
90b8491c 1436 &hba->vps->ondemand_data);
deac444f
BA		 1437 if (IS_ERR(devfreq)) {
1438 ret = PTR_ERR(devfreq);
1439 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1440
1441 dev_pm_opp_remove(hba->dev, clki->min_freq);
1442 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1443 return ret;
1444 }
1445
1446 hba->devfreq = devfreq;
1447
1448 return 0;
1449}
1450
092b4558
BA		 1451static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1452{
1453 struct list_head *clk_list = &hba->clk_list_head;
1454 struct ufs_clk_info *clki;
1455
1456 if (!hba->devfreq)
1457 return;
1458
1459 devfreq_remove_device(hba->devfreq);
1460 hba->devfreq = NULL;
1461
1462 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1463 dev_pm_opp_remove(hba->dev, clki->min_freq);
1464 dev_pm_opp_remove(hba->dev, clki->max_freq);
1465}
1466
401f1e44 1467static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1468{
1469 unsigned long flags;
1470
1471 devfreq_suspend_device(hba->devfreq);
1472 spin_lock_irqsave(hba->host->host_lock, flags);
1473 hba->clk_scaling.window_start_t = 0;
1474 spin_unlock_irqrestore(hba->host->host_lock, flags);
1475}
a3cd5ec5 1476
a508253d
GB		 1477static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1478{
401f1e44 1479 unsigned long flags;
1480 bool suspend = false;
1481
f9a7fa34
SC		 1482 cancel_work_sync(&hba->clk_scaling.suspend_work);
1483 cancel_work_sync(&hba->clk_scaling.resume_work);
fcb0c4b0 1484
401f1e44 1485 spin_lock_irqsave(hba->host->host_lock, flags);
1486 if (!hba->clk_scaling.is_suspended) {
1487 suspend = true;
1488 hba->clk_scaling.is_suspended = true;
1489 }
1490 spin_unlock_irqrestore(hba->host->host_lock, flags);
1491
1492 if (suspend)
1493 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1494}
1495
1496static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1497{
401f1e44 1498 unsigned long flags;
1499 bool resume = false;
1500
401f1e44 1501 spin_lock_irqsave(hba->host->host_lock, flags);
1502 if (hba->clk_scaling.is_suspended) {
1503 resume = true;
1504 hba->clk_scaling.is_suspended = false;
1505 }
1506 spin_unlock_irqrestore(hba->host->host_lock, flags);
1507
1508 if (resume)
1509 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1510}
1511
1512static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1513 struct device_attribute *attr, char *buf)
1514{
1515 struct ufs_hba *hba = dev_get_drvdata(dev);
1516
1481b7fe 1517 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
fcb0c4b0
ST		 1518}
1519
1520static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1521 struct device_attribute *attr, const char *buf, size_t count)
1522{
1523 struct ufs_hba *hba = dev_get_drvdata(dev);
1524 u32 value;
9cd20d3f 1525 int err = 0;
fcb0c4b0
ST		 1526
1527 if (kstrtou32(buf, 0, &value))
1528 return -EINVAL;
1529
9cd20d3f
CG		 1530 down(&hba->host_sem);
1531 if (!ufshcd_is_user_access_allowed(hba)) {
1532 err = -EBUSY;
1533 goto out;
1534 }
1535
fcb0c4b0 1536 value = !!value;
0e9d4ca4 1537 if (value == hba->clk_scaling.is_enabled)
fcb0c4b0
ST		 1538 goto out;
1539
b294ff3e 1540 ufshcd_rpm_get_sync(hba);
fcb0c4b0
ST		 1541 ufshcd_hold(hba, false);
1542
0e9d4ca4 1543 hba->clk_scaling.is_enabled = value;
401f1e44 1544
fcb0c4b0
ST		 1545 if (value) {
1546 ufshcd_resume_clkscaling(hba);
1547 } else {
1548 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1549 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1550 if (err)
1551 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1552 __func__, err);
1553 }
fcb0c4b0
ST		 1554
1555 ufshcd_release(hba);
b294ff3e 1556 ufshcd_rpm_put_sync(hba);
fcb0c4b0 1557out:
9cd20d3f
CG		 1558 up(&hba->host_sem);
1559 return err ? err : count;
a508253d
GB		 1560}
1561
4543d9d7 1562static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
a3cd5ec5 1563{
1564 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1565 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1566 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1567 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1568 hba->clk_scaling.enable_attr.attr.mode = 0644;
1569 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1570 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1571}
1572
4543d9d7
CG		 1573static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1574{
1575 if (hba->clk_scaling.enable_attr.attr.name)
1576 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1577}
1578
1579static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1580{
1581 char wq_name[sizeof("ufs_clkscaling_00")];
1582
1583 if (!ufshcd_is_clkscaling_supported(hba))
1584 return;
1585
80d892f4
CG		 1586 if (!hba->clk_scaling.min_gear)
1587 hba->clk_scaling.min_gear = UFS_HS_G1;
1588
4543d9d7
CG		 1589 INIT_WORK(&hba->clk_scaling.suspend_work,
1590 ufshcd_clk_scaling_suspend_work);
1591 INIT_WORK(&hba->clk_scaling.resume_work,
1592 ufshcd_clk_scaling_resume_work);
1593
1594 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1595 hba->host->host_no);
1596 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1597
1598 hba->clk_scaling.is_initialized = true;
1599}
1600
1601static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1602{
1603 if (!hba->clk_scaling.is_initialized)
1604 return;
1605
1606 ufshcd_remove_clk_scaling_sysfs(hba);
1607 destroy_workqueue(hba->clk_scaling.workq);
1608 ufshcd_devfreq_remove(hba);
1609 hba->clk_scaling.is_initialized = false;
1610}
1611
1ab27c9c
ST		 1612static void ufshcd_ungate_work(struct work_struct *work)
1613{
1614 int ret;
1615 unsigned long flags;
1616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1617 clk_gating.ungate_work);
1618
1619 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1620
1621 spin_lock_irqsave(hba->host->host_lock, flags);
1622 if (hba->clk_gating.state == CLKS_ON) {
1623 spin_unlock_irqrestore(hba->host->host_lock, flags);
1624 goto unblock_reqs;
1625 }
1626
1627 spin_unlock_irqrestore(hba->host->host_lock, flags);
dd7143e2 1628 ufshcd_hba_vreg_set_hpm(hba);
1ab27c9c
ST		 1629 ufshcd_setup_clocks(hba, true);
1630
8b0bbf00
SC		 1631 ufshcd_enable_irq(hba);
1632
1ab27c9c
ST		 1633 /* Exit from hibern8 */
1634 if (ufshcd_can_hibern8_during_gating(hba)) {
1635 /* Prevent gating in this path */
1636 hba->clk_gating.is_suspended = true;
1637 if (ufshcd_is_link_hibern8(hba)) {
1638 ret = ufshcd_uic_hibern8_exit(hba);
1639 if (ret)
1640 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1641 __func__, ret);
1642 else
1643 ufshcd_set_link_active(hba);
1644 }
1645 hba->clk_gating.is_suspended = false;
1646 }
1647unblock_reqs:
38135535 1648 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1649}
1650
1651/**
1652 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1653 * Also, exit from hibern8 mode and set the link as active.
1654 * @hba: per adapter instance
1655 * @async: This indicates whether caller should ungate clocks asynchronously.
1656 */
1657int ufshcd_hold(struct ufs_hba *hba, bool async)
1658{
1659 int rc = 0;
93b6c5db 1660 bool flush_result;
1ab27c9c
ST		 1661 unsigned long flags;
1662
1663 if (!ufshcd_is_clkgating_allowed(hba))
1664 goto out;
1ab27c9c
ST		 1665 spin_lock_irqsave(hba->host->host_lock, flags);
1666 hba->clk_gating.active_reqs++;
1667
856b3483 1668start:
1ab27c9c
ST		 1669 switch (hba->clk_gating.state) {
1670 case CLKS_ON:
f2a785ac
VG		 1671 /*
1672 * Wait for the ungate work to complete if in progress.
1673 * Though the clocks may be in ON state, the link could
1674 * still be in hibner8 state if hibern8 is allowed
1675 * during clock gating.
1676 * Make sure we exit hibern8 state also in addition to
1677 * clocks being ON.
1678 */
1679 if (ufshcd_can_hibern8_during_gating(hba) &&
1680 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1681 if (async) {
1682 rc = -EAGAIN;
1683 hba->clk_gating.active_reqs--;
1684 break;
1685 }
f2a785ac 1686 spin_unlock_irqrestore(hba->host->host_lock, flags);
93b6c5db
SC		 1687 flush_result = flush_work(&hba->clk_gating.ungate_work);
1688 if (hba->clk_gating.is_suspended && !flush_result)
1689 goto out;
f2a785ac
VG		 1690 spin_lock_irqsave(hba->host->host_lock, flags);
1691 goto start;
1692 }
1ab27c9c
ST		 1693 break;
1694 case REQ_CLKS_OFF:
1695 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1696 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1697 trace_ufshcd_clk_gating(dev_name(hba->dev),
1698 hba->clk_gating.state);
1ab27c9c
ST		 1699 break;
1700 }
1701 /*
9c490d2d 1702 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1703 * currently running. Hence, fall through to cancel gating
1704 * work and to enable clocks.
1705 */
df561f66 1706 fallthrough;
1ab27c9c 1707 case CLKS_OFF:
1ab27c9c 1708 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1709 trace_ufshcd_clk_gating(dev_name(hba->dev),
1710 hba->clk_gating.state);
da3fecb0
CG		 1711 if (queue_work(hba->clk_gating.clk_gating_workq,
1712 &hba->clk_gating.ungate_work))
1713 ufshcd_scsi_block_requests(hba);
1ab27c9c
ST		 1714 /*
1715 * fall through to check if we should wait for this
1716 * work to be done or not.
1717 */
df561f66 1718 fallthrough;
1ab27c9c
ST		 1719 case REQ_CLKS_ON:
1720 if (async) {
1721 rc = -EAGAIN;
1722 hba->clk_gating.active_reqs--;
1723 break;
1724 }
1725
1726 spin_unlock_irqrestore(hba->host->host_lock, flags);
1727 flush_work(&hba->clk_gating.ungate_work);
1728 /* Make sure state is CLKS_ON before returning */
856b3483 1729 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1730 goto start;
1731 default:
1732 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1733 __func__, hba->clk_gating.state);
1734 break;
1735 }
1736 spin_unlock_irqrestore(hba->host->host_lock, flags);
1737out:
1738 return rc;
1739}
6e3fd44d 1740EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1741
1742static void ufshcd_gate_work(struct work_struct *work)
1743{
1744 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1745 clk_gating.gate_work.work);
1746 unsigned long flags;
4db7a236 1747 int ret;
1ab27c9c
ST		 1748
1749 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1750 /*
1751 * In case you are here to cancel this work the gating state
1752 * would be marked as REQ_CLKS_ON. In this case save time by
1753 * skipping the gating work and exit after changing the clock
1754 * state to CLKS_ON.
1755 */
1756 if (hba->clk_gating.is_suspended ||
18f01374 1757 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1758 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1759 trace_ufshcd_clk_gating(dev_name(hba->dev),
1760 hba->clk_gating.state);
1ab27c9c
ST		 1761 goto rel_lock;
1762 }
1763
1764 if (hba->clk_gating.active_reqs
1765 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1766 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1ab27c9c
ST		 1767 || hba->active_uic_cmd || hba->uic_async_done)
1768 goto rel_lock;
1769
1770 spin_unlock_irqrestore(hba->host->host_lock, flags);
1771
1772 /* put the link into hibern8 mode before turning off clocks */
1773 if (ufshcd_can_hibern8_during_gating(hba)) {
4db7a236
CG		 1774 ret = ufshcd_uic_hibern8_enter(hba);
1775 if (ret) {
1ab27c9c 1776 hba->clk_gating.state = CLKS_ON;
4db7a236
CG		 1777 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1778 __func__, ret);
7ff5ab47 1779 trace_ufshcd_clk_gating(dev_name(hba->dev),
1780 hba->clk_gating.state);
1ab27c9c
ST		 1781 goto out;
1782 }
1783 ufshcd_set_link_hibern8(hba);
1784 }
1785
8b0bbf00
SC		 1786 ufshcd_disable_irq(hba);
1787
81309c24 1788 ufshcd_setup_clocks(hba, false);
1ab27c9c 1789
dd7143e2
CG		 1790 /* Put the host controller in low power mode if possible */
1791 ufshcd_hba_vreg_set_lpm(hba);
1ab27c9c
ST		 1792 /*
1793 * In case you are here to cancel this work the gating state
1794 * would be marked as REQ_CLKS_ON. In this case keep the state
1795 * as REQ_CLKS_ON which would anyway imply that clocks are off
1796 * and a request to turn them on is pending. By doing this way,
1797 * we keep the state machine in tact and this would ultimately
1798 * prevent from doing cancel work multiple times when there are
1799 * new requests arriving before the current cancel work is done.
1800 */
1801 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1802 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1803 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1804 trace_ufshcd_clk_gating(dev_name(hba->dev),
1805 hba->clk_gating.state);
1806 }
1ab27c9c
ST		 1807rel_lock:
1808 spin_unlock_irqrestore(hba->host->host_lock, flags);
1809out:
1810 return;
1811}
1812
1813/* host lock must be held before calling this variant */
1814static void __ufshcd_release(struct ufs_hba *hba)
1815{
1816 if (!ufshcd_is_clkgating_allowed(hba))
1817 return;
1818
1819 hba->clk_gating.active_reqs--;
1820
4db7a236
CG		 1821 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1822 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
8eb456be 1823 hba->outstanding_tasks ||
fd62de11
JK		 1824 hba->active_uic_cmd || hba->uic_async_done ||
1825 hba->clk_gating.state == CLKS_OFF)
1ab27c9c
ST		 1826 return;
1827
1828 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1829 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1830 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1831 &hba->clk_gating.gate_work,
1832 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1833}
1834
1835void ufshcd_release(struct ufs_hba *hba)
1836{
1837 unsigned long flags;
1838
1839 spin_lock_irqsave(hba->host->host_lock, flags);
1840 __ufshcd_release(hba);
1841 spin_unlock_irqrestore(hba->host->host_lock, flags);
1842}
6e3fd44d 1843EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1844
1845static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1846 struct device_attribute *attr, char *buf)
1847{
1848 struct ufs_hba *hba = dev_get_drvdata(dev);
1849
bafd09f8 1850 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1ab27c9c
ST		 1851}
1852
1853static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1854 struct device_attribute *attr, const char *buf, size_t count)
1855{
1856 struct ufs_hba *hba = dev_get_drvdata(dev);
1857 unsigned long flags, value;
1858
1859 if (kstrtoul(buf, 0, &value))
1860 return -EINVAL;
1861
1862 spin_lock_irqsave(hba->host->host_lock, flags);
1863 hba->clk_gating.delay_ms = value;
1864 spin_unlock_irqrestore(hba->host->host_lock, flags);
1865 return count;
1866}
1867
b427411a
ST		 1868static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1869 struct device_attribute *attr, char *buf)
1870{
1871 struct ufs_hba *hba = dev_get_drvdata(dev);
1872
bafd09f8 1873 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
b427411a
ST		 1874}
1875
1876static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1877 struct device_attribute *attr, const char *buf, size_t count)
1878{
1879 struct ufs_hba *hba = dev_get_drvdata(dev);
1880 unsigned long flags;
1881 u32 value;
1882
1883 if (kstrtou32(buf, 0, &value))
1884 return -EINVAL;
1885
1886 value = !!value;
b6645112
JK		 1887
1888 spin_lock_irqsave(hba->host->host_lock, flags);
b427411a
ST		 1889 if (value == hba->clk_gating.is_enabled)
1890 goto out;
1891
b6645112
JK		 1892 if (value)
1893 __ufshcd_release(hba);
1894 else
b427411a 1895 hba->clk_gating.active_reqs++;
b427411a
ST		 1896
1897 hba->clk_gating.is_enabled = value;
1898out:
b6645112 1899 spin_unlock_irqrestore(hba->host->host_lock, flags);
b427411a
ST		 1900 return count;
1901}
1902
4543d9d7 1903static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1904{
4543d9d7
CG		 1905 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1906 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1907 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1908 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1909 hba->clk_gating.delay_attr.attr.mode = 0644;
1910 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1911 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
eebcc196 1912
4543d9d7
CG		 1913 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1914 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1915 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1916 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1917 hba->clk_gating.enable_attr.attr.mode = 0644;
1918 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1919 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
eebcc196
VG		 1920}
1921
4543d9d7 1922static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1923{
4543d9d7
CG		 1924 if (hba->clk_gating.delay_attr.attr.name)
1925 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1926 if (hba->clk_gating.enable_attr.attr.name)
1927 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
eebcc196
VG		 1928}
1929
1ab27c9c
ST		 1930static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1931{
10e5e375
VV		 1932 char wq_name[sizeof("ufs_clk_gating_00")];
1933
1ab27c9c
ST		 1934 if (!ufshcd_is_clkgating_allowed(hba))
1935 return;
1936
2dec9475
CG		 1937 hba->clk_gating.state = CLKS_ON;
1938
1ab27c9c
ST		 1939 hba->clk_gating.delay_ms = 150;
1940 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1941 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1942
10e5e375
VV		 1943 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1944 hba->host->host_no);
1945 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
e93e6e49 1946 WQ_MEM_RECLAIM | WQ_HIGHPRI);
10e5e375 1947
4543d9d7 1948 ufshcd_init_clk_gating_sysfs(hba);
b427411a 1949
4543d9d7
CG		 1950 hba->clk_gating.is_enabled = true;
1951 hba->clk_gating.is_initialized = true;
1ab27c9c
ST		 1952}
1953
1954static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1955{
4543d9d7 1956 if (!hba->clk_gating.is_initialized)
1ab27c9c 1957 return;
4543d9d7 1958 ufshcd_remove_clk_gating_sysfs(hba);
97cd6805
AM		 1959 cancel_work_sync(&hba->clk_gating.ungate_work);
1960 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1961 destroy_workqueue(hba->clk_gating.clk_gating_workq);
4543d9d7 1962 hba->clk_gating.is_initialized = false;
1ab27c9c
ST		 1963}
1964
856b3483
ST		 1965/* Must be called with host lock acquired */
1966static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1967{
401f1e44 1968 bool queue_resume_work = false;
b1bf66d1 1969 ktime_t curr_t = ktime_get();
a45f9371 1970 unsigned long flags;
401f1e44 1971
fcb0c4b0 1972 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1973 return;
1974
a45f9371 1975 spin_lock_irqsave(hba->host->host_lock, flags);
401f1e44 1976 if (!hba->clk_scaling.active_reqs++)
1977 queue_resume_work = true;
1978
a45f9371
CG		 1979 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
1980 spin_unlock_irqrestore(hba->host->host_lock, flags);
401f1e44 1981 return;
a45f9371 1982 }
401f1e44 1983
1984 if (queue_resume_work)
1985 queue_work(hba->clk_scaling.workq,
1986 &hba->clk_scaling.resume_work);
1987
1988 if (!hba->clk_scaling.window_start_t) {
b1bf66d1 1989 hba->clk_scaling.window_start_t = curr_t;
401f1e44 1990 hba->clk_scaling.tot_busy_t = 0;
1991 hba->clk_scaling.is_busy_started = false;
1992 }
1993
856b3483 1994 if (!hba->clk_scaling.is_busy_started) {
b1bf66d1 1995 hba->clk_scaling.busy_start_t = curr_t;
856b3483
ST		 1996 hba->clk_scaling.is_busy_started = true;
1997 }
a45f9371 1998 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483
ST		 1999}
2000
2001static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2002{
2003 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
a45f9371 2004 unsigned long flags;
856b3483 2005
fcb0c4b0 2006 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2007 return;
2008
a45f9371
CG		 2009 spin_lock_irqsave(hba->host->host_lock, flags);
2010 hba->clk_scaling.active_reqs--;
856b3483
ST		 2011 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2012 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2013 scaling->busy_start_t));
8b0e1953 2014 scaling->busy_start_t = 0;
856b3483
ST		 2015 scaling->is_busy_started = false;
2016 }
a45f9371 2017 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2018}
1d8613a2
CG		 2019
2020static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2021{
2022 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2023 return READ;
2024 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2025 return WRITE;
2026 else
2027 return -EINVAL;
2028}
2029
2030static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2031 struct ufshcd_lrb *lrbp)
2032{
2033 struct ufs_hba_monitor *m = &hba->monitor;
2034
2035 return (m->enabled && lrbp && lrbp->cmd &&
2036 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2037 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2038}
2039
2040static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2041{
2042 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2043 unsigned long flags;
1d8613a2 2044
a45f9371 2045 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2
CG		 2046 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2047 hba->monitor.busy_start_ts[dir] = ktime_get();
a45f9371 2048 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d8613a2
CG		 2049}
2050
2051static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2052{
2053 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2054 unsigned long flags;
1d8613a2 2055
a45f9371 2056 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2 2057 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
3f2c1002 2058 struct request *req = scsi_cmd_to_rq(lrbp->cmd);
1d8613a2
CG		 2059 struct ufs_hba_monitor *m = &hba->monitor;
2060 ktime_t now, inc, lat;
2061
2062 now = lrbp->compl_time_stamp;
2063 inc = ktime_sub(now, m->busy_start_ts[dir]);
2064 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2065 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2066
2067 /* Update latencies */
2068 m->nr_req[dir]++;
2069 lat = ktime_sub(now, lrbp->issue_time_stamp);
2070 m->lat_sum[dir] += lat;
2071 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2072 m->lat_max[dir] = lat;
2073 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2074 m->lat_min[dir] = lat;
2075
2076 m->nr_queued[dir]--;
2077 /* Push forward the busy start of monitor */
2078 m->busy_start_ts[dir] = now;
2079 }
a45f9371 2080 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2081}
1d8613a2 2082
7a3e97b0
SY		 2083/**
2084 * ufshcd_send_command - Send SCSI or device management commands
2085 * @hba: per adapter instance
2086 * @task_tag: Task tag of the command
2087 */
2088static inline
2089void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2090{
6edfdcfe 2091 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
1f522c50 2092 unsigned long flags;
6edfdcfe
SC		 2093
2094 lrbp->issue_time_stamp = ktime_get();
2095 lrbp->compl_time_stamp = ktime_set(0, 0);
28fa68fc 2096 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
856b3483 2097 ufshcd_clk_scaling_start_busy(hba);
1d8613a2
CG		 2098 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2099 ufshcd_start_monitor(hba, lrbp);
169f5eb2
BVA		 2100
2101 spin_lock_irqsave(&hba->outstanding_lock, flags);
a024ad0d
BVA		 2102 if (hba->vops && hba->vops->setup_xfer_req)
2103 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
169f5eb2 2104 __set_bit(task_tag, &hba->outstanding_reqs);
1f522c50 2105 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
169f5eb2
BVA		 2106 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2107
ad1a1b9c
GB		 2108 /* Make sure that doorbell is committed immediately */
2109 wmb();
7a3e97b0
SY		 2110}
2111
2112/**
2113 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 2114 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2115 */
2116static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2117{
2118 int len;
1c2623c5
SJ		 2119 if (lrbp->sense_buffer &&
2120 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 2121 int len_to_copy;
2122
5a0b0cb9 2123 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 2124 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 2125
09a5a24f
AA		 2126 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2127 len_to_copy);
7a3e97b0
SY		 2128 }
2129}
2130
68078d5c
DR		 2131/**
2132 * ufshcd_copy_query_response() - Copy the Query Response and the data
2133 * descriptor
2134 * @hba: per adapter instance
8aa29f19 2135 * @lrbp: pointer to local reference block
68078d5c
DR		 2136 */
2137static
c6d4a831 2138int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 2139{
2140 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2141
68078d5c 2142 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 2143
68078d5c 2144 /* Get the descriptor */
1c90836f
AA		 2145 if (hba->dev_cmd.query.descriptor &&
2146 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 2147 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 2148 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 2149 u16 resp_len;
2150 u16 buf_len;
68078d5c
DR		 2151
2152 /* data segment length */
c6d4a831 2153 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 2154 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 2155 buf_len = be16_to_cpu(
2156 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 2157 if (likely(buf_len >= resp_len)) {
2158 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2159 } else {
2160 dev_warn(hba->dev,
3d4881d1
BH		 2161 "%s: rsp size %d is bigger than buffer size %d",
2162 __func__, resp_len, buf_len);
c6d4a831
DR		 2163 return -EINVAL;
2164 }
68078d5c 2165 }
c6d4a831
DR		 2166
2167 return 0;
68078d5c
DR		 2168}
2169
7a3e97b0
SY		 2170/**
2171 * ufshcd_hba_capabilities - Read controller capabilities
2172 * @hba: per adapter instance
df043c74
ST		 2173 *
2174 * Return: 0 on success, negative on error.
7a3e97b0 2175 */
df043c74 2176static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
7a3e97b0 2177{
df043c74
ST		 2178 int err;
2179
b873a275 2180 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 2181
2182 /* nutrs and nutmrs are 0 based values */
2183 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2184 hba->nutmrs =
2185 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
df043c74
ST		 2186
2187 /* Read crypto capabilities */
2188 err = ufshcd_hba_init_crypto_capabilities(hba);
2189 if (err)
2190 dev_err(hba->dev, "crypto setup failed\n");
2191
2192 return err;
7a3e97b0
SY		 2193}
2194
2195/**
6ccf44fe
SJ		 2196 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2197 * to accept UIC commands
7a3e97b0 2198 * @hba: per adapter instance
6ccf44fe
SJ		 2199 * Return true on success, else false
2200 */
2201static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2202{
2203 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2204 return true;
2205 else
2206 return false;
2207}
2208
53b3d9c3
SJ		 2209/**
2210 * ufshcd_get_upmcrs - Get the power mode change request status
2211 * @hba: Pointer to adapter instance
2212 *
2213 * This function gets the UPMCRS field of HCS register
2214 * Returns value of UPMCRS field
2215 */
2216static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2217{
2218 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2219}
2220
6ccf44fe 2221/**
35c7d874 2222 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
6ccf44fe
SJ		 2223 * @hba: per adapter instance
2224 * @uic_cmd: UIC command
7a3e97b0
SY		 2225 */
2226static inline void
6ccf44fe 2227ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2228{
35c7d874
BVA		 2229 lockdep_assert_held(&hba->uic_cmd_mutex);
2230
6ccf44fe
SJ		 2231 WARN_ON(hba->active_uic_cmd);
2232
2233 hba->active_uic_cmd = uic_cmd;
2234
7a3e97b0 2235 /* Write Args */
6ccf44fe
SJ		 2236 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2237 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2238 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0 2239
28fa68fc 2240 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
aa5c6979 2241
7a3e97b0 2242 /* Write UIC Cmd */
6ccf44fe 2243 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2244 REG_UIC_COMMAND);
7a3e97b0
SY		 2245}
2246
6ccf44fe 2247/**
35c7d874 2248 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
6ccf44fe 2249 * @hba: per adapter instance
8aa29f19 2250 * @uic_cmd: UIC command
6ccf44fe 2251 *
6ccf44fe
SJ		 2252 * Returns 0 only if success.
2253 */
2254static int
2255ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2256{
2257 int ret;
2258 unsigned long flags;
2259
35c7d874
BVA		 2260 lockdep_assert_held(&hba->uic_cmd_mutex);
2261
6ccf44fe 2262 if (wait_for_completion_timeout(&uic_cmd->done,
0f52fcb9 2263 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
6ccf44fe 2264 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
0f52fcb9 2265 } else {
6ccf44fe 2266 ret = -ETIMEDOUT;
0f52fcb9
CG		 2267 dev_err(hba->dev,
2268 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2269 uic_cmd->command, uic_cmd->argument3);
2270
2271 if (!uic_cmd->cmd_active) {
2272 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2273 __func__);
2274 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2275 }
2276 }
6ccf44fe
SJ		 2277
2278 spin_lock_irqsave(hba->host->host_lock, flags);
2279 hba->active_uic_cmd = NULL;
2280 spin_unlock_irqrestore(hba->host->host_lock, flags);
2281
2282 return ret;
2283}
2284
2285/**
2286 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2287 * @hba: per adapter instance
2288 * @uic_cmd: UIC command
d75f7fe4 2289 * @completion: initialize the completion only if this is set to true
6ccf44fe 2290 *
6ccf44fe
SJ		 2291 * Returns 0 only if success.
2292 */
2293static int
d75f7fe4
YG		 2294__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2295 bool completion)
6ccf44fe 2296{
35c7d874
BVA		 2297 lockdep_assert_held(&hba->uic_cmd_mutex);
2298 lockdep_assert_held(hba->host->host_lock);
2299
6ccf44fe
SJ		 2300 if (!ufshcd_ready_for_uic_cmd(hba)) {
2301 dev_err(hba->dev,
2302 "Controller not ready to accept UIC commands\n");
2303 return -EIO;
2304 }
2305
d75f7fe4
YG		 2306 if (completion)
2307 init_completion(&uic_cmd->done);
6ccf44fe 2308
0f52fcb9 2309 uic_cmd->cmd_active = 1;
6ccf44fe 2310 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2311
57d104c1 2312 return 0;
6ccf44fe
SJ		 2313}
2314
2315/**
2316 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2317 * @hba: per adapter instance
2318 * @uic_cmd: UIC command
2319 *
2320 * Returns 0 only if success.
2321 */
e77044c5 2322int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2323{
2324 int ret;
57d104c1 2325 unsigned long flags;
6ccf44fe 2326
1ab27c9c 2327 ufshcd_hold(hba, false);
6ccf44fe 2328 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2329 ufshcd_add_delay_before_dme_cmd(hba);
2330
57d104c1 2331 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2332 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2333 spin_unlock_irqrestore(hba->host->host_lock, flags);
2334 if (!ret)
2335 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2336
6ccf44fe
SJ		 2337 mutex_unlock(&hba->uic_cmd_mutex);
2338
1ab27c9c 2339 ufshcd_release(hba);
6ccf44fe
SJ		 2340 return ret;
2341}
2342
7a3e97b0
SY		 2343/**
2344 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2345 * @hba: per adapter instance
2346 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2347 *
2348 * Returns 0 in case of success, non-zero value in case of failure
2349 */
75b1cc4a 2350static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2351{
2352 struct ufshcd_sg_entry *prd_table;
2353 struct scatterlist *sg;
2354 struct scsi_cmnd *cmd;
2355 int sg_segments;
2356 int i;
2357
2358 cmd = lrbp->cmd;
2359 sg_segments = scsi_dma_map(cmd);
2360 if (sg_segments < 0)
2361 return sg_segments;
2362
2363 if (sg_segments) {
26f968d7
AA		 2364
2365 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2366 lrbp->utr_descriptor_ptr->prd_table_length =
2367 cpu_to_le16((sg_segments *
2368 sizeof(struct ufshcd_sg_entry)));
2369 else
2370 lrbp->utr_descriptor_ptr->prd_table_length =
2371 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2372
2373 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2374
2375 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2376 prd_table[i].size =
2377 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2378 prd_table[i].base_addr =
2379 cpu_to_le32(lower_32_bits(sg->dma_address));
2380 prd_table[i].upper_addr =
2381 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2382 prd_table[i].reserved = 0;
7a3e97b0
SY		 2383 }
2384 } else {
2385 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2386 }
2387
2388 return 0;
2389}
2390
2391/**
2fbd009b 2392 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2393 * @hba: per adapter instance
2fbd009b 2394 * @intrs: interrupt bits
7a3e97b0 2395 */
2fbd009b 2396static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2397{
2fbd009b
SJ		 2398 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2399
51428818 2400 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2401 u32 rw;
2402 rw = set & INTERRUPT_MASK_RW_VER_10;
2403 set = rw | ((set ^ intrs) & intrs);
2404 } else {
2405 set |= intrs;
2406 }
2407
2408 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2409}
2410
2411/**
2412 * ufshcd_disable_intr - disable interrupts
2413 * @hba: per adapter instance
2414 * @intrs: interrupt bits
2415 */
2416static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2417{
2418 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2419
51428818 2420 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2421 u32 rw;
2422 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2423 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2424 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2425
2426 } else {
2427 set &= ~intrs;
7a3e97b0 2428 }
2fbd009b
SJ		 2429
2430 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2431}
2432
5a0b0cb9
SRT		 2433/**
2434 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2435 * descriptor according to request
2436 * @lrbp: pointer to local reference block
2437 * @upiu_flags: flags required in the header
2438 * @cmd_dir: requests data direction
2439 */
2440static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
a23064c4 2441 u8 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2442{
2443 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2444 u32 data_direction;
2445 u32 dword_0;
df043c74
ST		 2446 u32 dword_1 = 0;
2447 u32 dword_3 = 0;
5a0b0cb9
SRT		 2448
2449 if (cmd_dir == DMA_FROM_DEVICE) {
2450 data_direction = UTP_DEVICE_TO_HOST;
2451 *upiu_flags = UPIU_CMD_FLAGS_READ;
2452 } else if (cmd_dir == DMA_TO_DEVICE) {
2453 data_direction = UTP_HOST_TO_DEVICE;
2454 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2455 } else {
2456 data_direction = UTP_NO_DATA_TRANSFER;
2457 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2458 }
2459
2460 dword_0 = data_direction | (lrbp->command_type
2461 << UPIU_COMMAND_TYPE_OFFSET);
2462 if (lrbp->intr_cmd)
2463 dword_0 |= UTP_REQ_DESC_INT_CMD;
2464
df043c74
ST		 2465 /* Prepare crypto related dwords */
2466 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2467
5a0b0cb9
SRT		 2468 /* Transfer request descriptor header fields */
2469 req_desc->header.dword_0 = cpu_to_le32(dword_0);
df043c74 2470 req_desc->header.dword_1 = cpu_to_le32(dword_1);
5a0b0cb9
SRT		 2471 /*
2472 * assigning invalid value for command status. Controller
2473 * updates OCS on command completion, with the command
2474 * status
2475 */
2476 req_desc->header.dword_2 =
2477 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
df043c74 2478 req_desc->header.dword_3 = cpu_to_le32(dword_3);
51047266
YG		 2479
2480 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2481}
2482
2483/**
2484 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2485 * for scsi commands
8aa29f19
BVA		 2486 * @lrbp: local reference block pointer
2487 * @upiu_flags: flags
5a0b0cb9
SRT		 2488 */
2489static
a23064c4 2490void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
5a0b0cb9 2491{
1b21b8f0 2492 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2493 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2494 unsigned short cdb_len;
5a0b0cb9
SRT		 2495
2496 /* command descriptor fields */
2497 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2498 UPIU_TRANSACTION_COMMAND, upiu_flags,
2499 lrbp->lun, lrbp->task_tag);
2500 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2501 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2502
2503 /* Total EHS length and Data segment length will be zero */
2504 ucd_req_ptr->header.dword_2 = 0;
2505
1b21b8f0 2506 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2507
1b21b8f0 2508 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2509 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2510 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2511
2512 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2513}
2514
68078d5c
DR		 2515/**
2516 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2517 * for query requsts
2518 * @hba: UFS hba
2519 * @lrbp: local reference block pointer
2520 * @upiu_flags: flags
2521 */
2522static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
a23064c4 2523 struct ufshcd_lrb *lrbp, u8 upiu_flags)
68078d5c
DR		 2524{
2525 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2526 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2527 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2528
2529 /* Query request header */
2530 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2531 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2532 lrbp->lun, lrbp->task_tag);
2533 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2534 0, query->request.query_func, 0, 0);
2535
6861285c
ZL		 2536 /* Data segment length only need for WRITE_DESC */
2537 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2538 ucd_req_ptr->header.dword_2 =
2539 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2540 else
2541 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2542
2543 /* Copy the Query Request buffer as is */
2544 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2545 QUERY_OSF_SIZE);
68078d5c
DR		 2546
2547 /* Copy the Descriptor */
c6d4a831 2548 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2549 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2550
51047266 2551 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2552}
2553
5a0b0cb9
SRT		 2554static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2555{
2556 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2557
2558 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2559
2560 /* command descriptor fields */
2561 ucd_req_ptr->header.dword_0 =
2562 UPIU_HEADER_DWORD(
2563 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2564 /* clear rest of the fields of basic header */
2565 ucd_req_ptr->header.dword_1 = 0;
2566 ucd_req_ptr->header.dword_2 = 0;
2567
2568 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2569}
2570
7a3e97b0 2571/**
f273c54b 2572 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
300bb13f 2573 * for Device Management Purposes
8aa29f19
BVA		 2574 * @hba: per adapter instance
2575 * @lrbp: pointer to local reference block
7a3e97b0 2576 */
f273c54b
BH		 2577static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2578 struct ufshcd_lrb *lrbp)
7a3e97b0 2579{
a23064c4 2580 u8 upiu_flags;
5a0b0cb9 2581 int ret = 0;
7a3e97b0 2582
51428818 2583 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2584 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2585 else
2586 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2587
2588 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2589 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2590 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2591 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2592 ufshcd_prepare_utp_nop_upiu(lrbp);
2593 else
2594 ret = -EINVAL;
2595
2596 return ret;
2597}
2598
2599/**
2600 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2601 * for SCSI Purposes
8aa29f19
BVA		 2602 * @hba: per adapter instance
2603 * @lrbp: pointer to local reference block
300bb13f
JP		 2604 */
2605static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2606{
a23064c4 2607 u8 upiu_flags;
300bb13f
JP		 2608 int ret = 0;
2609
51428818 2610 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2611 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2612 else
2613 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2614
2615 if (likely(lrbp->cmd)) {
2616 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2617 lrbp->cmd->sc_data_direction);
2618 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2619 } else {
2620 ret = -EINVAL;
2621 }
5a0b0cb9
SRT		 2622
2623 return ret;
7a3e97b0
SY		 2624}
2625
2a8fa600
SJ		 2626/**
2627 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2628 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2629 *
2630 * Returns SCSI W-LUN id
2631 */
2632static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2633{
2634 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2635}
2636
b294ff3e
AD		 2637static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2638{
2639 return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2640}
2641
2642static inline bool is_device_wlun(struct scsi_device *sdev)
2643{
2644 return sdev->lun ==
2645 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2646}
2647
4d2b8d40
BVA		 2648static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2649{
2650 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2651 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2652 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2653 i * sizeof(struct utp_transfer_cmd_desc);
2654 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2655 response_upiu);
2656 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2657
2658 lrb->utr_descriptor_ptr = utrdlp + i;
2659 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2660 i * sizeof(struct utp_transfer_req_desc);
2661 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2662 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2663 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2664 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2665 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2666 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2667}
2668
7a3e97b0
SY		 2669/**
2670 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2671 * @host: SCSI host pointer
7a3e97b0 2672 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2673 *
2674 * Returns 0 for success, non-zero in case of failure
2675 */
2676static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2677{
4728ab4a 2678 struct ufs_hba *hba = shost_priv(host);
3f2c1002 2679 int tag = scsi_cmd_to_rq(cmd)->tag;
7a3e97b0 2680 struct ufshcd_lrb *lrbp;
7a3e97b0
SY		 2681 int err = 0;
2682
4728ab4a 2683 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7a3e97b0 2684
a3cd5ec5 2685 if (!down_read_trylock(&hba->clk_scaling_lock))
2686 return SCSI_MLQUEUE_HOST_BUSY;
2687
a45f9371
CG		 2688 switch (hba->ufshcd_state) {
2689 case UFSHCD_STATE_OPERATIONAL:
2690 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2691 break;
2692 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2693 /*
2694 * pm_runtime_get_sync() is used at error handling preparation
2695 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2696 * PM ops, it can never be finished if we let SCSI layer keep
2697 * retrying it, which gets err handler stuck forever. Neither
2698 * can we let the scsi cmd pass through, because UFS is in bad
2699 * state, the scsi cmd may eventually time out, which will get
2700 * err handler blocked for too long. So, just fail the scsi cmd
2701 * sent from PM ops, err handler can recover PM error anyways.
2702 */
2703 if (hba->pm_op_in_progress) {
2704 hba->force_reset = true;
2705 set_host_byte(cmd, DID_BAD_TARGET);
2706 cmd->scsi_done(cmd);
2707 goto out;
2708 }
2709 fallthrough;
2710 case UFSHCD_STATE_RESET:
2711 err = SCSI_MLQUEUE_HOST_BUSY;
2712 goto out;
2713 case UFSHCD_STATE_ERROR:
2714 set_host_byte(cmd, DID_ERROR);
2715 cmd->scsi_done(cmd);
2716 goto out;
a45f9371
CG		 2717 }
2718
7fabb77b
GB		 2719 hba->req_abort_count = 0;
2720
1ab27c9c
ST		 2721 err = ufshcd_hold(hba, true);
2722 if (err) {
2723 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2724 goto out;
2725 }
2dec9475
CG		 2726 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2727 (hba->clk_gating.state != CLKS_ON));
1ab27c9c 2728
a45f9371 2729 lrbp = &hba->lrb[tag];
5a0b0cb9 2730 WARN_ON(lrbp->cmd);
7a3e97b0 2731 lrbp->cmd = cmd;
09a5a24f 2732 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2733 lrbp->sense_buffer = cmd->sense_buffer;
2734 lrbp->task_tag = tag;
0ce147d4 2735 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2736 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
df043c74 2737
3f2c1002 2738 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
df043c74 2739
e0b299e3 2740 lrbp->req_abort_skip = false;
7a3e97b0 2741
41d8a933
DP		 2742 err = ufshpb_prep(hba, lrbp);
2743 if (err == -EAGAIN) {
2744 lrbp->cmd = NULL;
2745 ufshcd_release(hba);
2746 goto out;
2747 }
2fff76f8 2748
300bb13f
JP		 2749 ufshcd_comp_scsi_upiu(hba, lrbp);
2750
75b1cc4a 2751 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2752 if (err) {
2753 lrbp->cmd = NULL;
17c7d35f 2754 ufshcd_release(hba);
7a3e97b0 2755 goto out;
5a0b0cb9 2756 }
7a3e97b0 2757
7a3e97b0 2758 ufshcd_send_command(hba, tag);
7a3e97b0 2759out:
a3cd5ec5 2760 up_read(&hba->clk_scaling_lock);
c11a1ae9
BVA		 2761
2762 if (ufs_trigger_eh())
2763 scsi_schedule_eh(hba->host);
2764
7a3e97b0
SY		 2765 return err;
2766}
2767
5a0b0cb9
SRT		 2768static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2769 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2770{
2771 lrbp->cmd = NULL;
2772 lrbp->sense_bufflen = 0;
2773 lrbp->sense_buffer = NULL;
2774 lrbp->task_tag = tag;
2775 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9 2776 lrbp->intr_cmd = true; /* No interrupt aggregation */
df043c74 2777 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5a0b0cb9
SRT		 2778 hba->dev_cmd.type = cmd_type;
2779
f273c54b 2780 return ufshcd_compose_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2781}
2782
2783static int
2784ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2785{
2786 int err = 0;
2787 unsigned long flags;
2788 u32 mask = 1 << tag;
2789
2790 /* clear outstanding transaction before retry */
2791 spin_lock_irqsave(hba->host->host_lock, flags);
2792 ufshcd_utrl_clear(hba, tag);
2793 spin_unlock_irqrestore(hba->host->host_lock, flags);
2794
2795 /*
32424902 2796 * wait for h/w to clear corresponding bit in door-bell.
5a0b0cb9
SRT		 2797 * max. wait is 1 sec.
2798 */
2799 err = ufshcd_wait_for_register(hba,
2800 REG_UTP_TRANSFER_REQ_DOOR_BELL,
5cac1095 2801 mask, ~mask, 1000, 1000);
5a0b0cb9
SRT		 2802
2803 return err;
2804}
2805
c6d4a831
DR		 2806static int
2807ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2808{
2809 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2810
2811 /* Get the UPIU response */
2812 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2813 UPIU_RSP_CODE_OFFSET;
2814 return query_res->response;
2815}
2816
5a0b0cb9
SRT		 2817/**
2818 * ufshcd_dev_cmd_completion() - handles device management command responses
2819 * @hba: per adapter instance
2820 * @lrbp: pointer to local reference block
2821 */
2822static int
2823ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2824{
2825 int resp;
2826 int err = 0;
2827
ff8e20c6 2828 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2829 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2830
2831 switch (resp) {
2832 case UPIU_TRANSACTION_NOP_IN:
2833 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2834 err = -EINVAL;
2835 dev_err(hba->dev, "%s: unexpected response %x\n",
2836 __func__, resp);
2837 }
2838 break;
68078d5c 2839 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2840 err = ufshcd_check_query_response(hba, lrbp);
2841 if (!err)
2842 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2843 break;
5a0b0cb9
SRT		 2844 case UPIU_TRANSACTION_REJECT_UPIU:
2845 /* TODO: handle Reject UPIU Response */
2846 err = -EPERM;
2847 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2848 __func__);
2849 break;
2850 default:
2851 err = -EINVAL;
2852 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2853 __func__, resp);
2854 break;
2855 }
2856
2857 return err;
2858}
2859
2860static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2861 struct ufshcd_lrb *lrbp, int max_timeout)
2862{
2863 int err = 0;
2864 unsigned long time_left;
2865 unsigned long flags;
2866
2867 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2868 msecs_to_jiffies(max_timeout));
2869
2870 spin_lock_irqsave(hba->host->host_lock, flags);
2871 hba->dev_cmd.complete = NULL;
2872 if (likely(time_left)) {
2873 err = ufshcd_get_tr_ocs(lrbp);
2874 if (!err)
2875 err = ufshcd_dev_cmd_completion(hba, lrbp);
2876 }
2877 spin_unlock_irqrestore(hba->host->host_lock, flags);
2878
2879 if (!time_left) {
2880 err = -ETIMEDOUT;
a48353f6
YG		 2881 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2882 __func__, lrbp->task_tag);
5a0b0cb9 2883 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2884 /* successfully cleared the command, retry if needed */
5a0b0cb9 2885 err = -EAGAIN;
a48353f6
YG		 2886 /*
2887 * in case of an error, after clearing the doorbell,
2888 * we also need to clear the outstanding_request
2889 * field in hba
2890 */
169f5eb2
BVA		 2891 spin_lock_irqsave(&hba->outstanding_lock, flags);
2892 __clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2893 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5a0b0cb9
SRT		 2894 }
2895
2896 return err;
2897}
2898
5a0b0cb9
SRT		 2899/**
2900 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2901 * @hba: UFS hba
2902 * @cmd_type: specifies the type (NOP, Query...)
d0b2b70e 2903 * @timeout: timeout in milliseconds
5a0b0cb9 2904 *
68078d5c
DR		 2905 * NOTE: Since there is only one available tag for device management commands,
2906 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2907 */
2908static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2909 enum dev_cmd_type cmd_type, int timeout)
2910{
7252a360 2911 struct request_queue *q = hba->cmd_queue;
8a686f26 2912 DECLARE_COMPLETION_ONSTACK(wait);
7252a360 2913 struct request *req;
5a0b0cb9
SRT		 2914 struct ufshcd_lrb *lrbp;
2915 int err;
2916 int tag;
5a0b0cb9 2917
a3cd5ec5 2918 down_read(&hba->clk_scaling_lock);
2919
5a0b0cb9
SRT		 2920 /*
2921 * Get free slot, sleep if slots are unavailable.
2922 * Even though we use wait_event() which sleeps indefinitely,
2923 * the maximum wait time is bounded by SCSI request timeout.
2924 */
7252a360 2925 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 2926 if (IS_ERR(req)) {
2927 err = PTR_ERR(req);
2928 goto out_unlock;
2929 }
7252a360 2930 tag = req->tag;
4728ab4a 2931 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
d0b2b70e
BVA		 2932 /* Set the timeout such that the SCSI error handler is not activated. */
2933 req->timeout = msecs_to_jiffies(2 * timeout);
2934 blk_mq_start_request(req);
5a0b0cb9 2935
a45f9371 2936 lrbp = &hba->lrb[tag];
5a0b0cb9
SRT		 2937 WARN_ON(lrbp->cmd);
2938 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2939 if (unlikely(err))
eb783bb8 2940 goto out;
5a0b0cb9
SRT		 2941
2942 hba->dev_cmd.complete = &wait;
2943
fb475b74 2944 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5a0b0cb9 2945
a45f9371 2946 ufshcd_send_command(hba, tag);
5a0b0cb9 2947 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
fb475b74
AA		 2948 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
2949 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6667e6d9 2950
eb783bb8 2951out:
7252a360 2952 blk_put_request(req);
bb14dd15 2953out_unlock:
a3cd5ec5 2954 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2955 return err;
2956}
2957
d44a5f98
DR		 2958/**
2959 * ufshcd_init_query() - init the query response and request parameters
2960 * @hba: per-adapter instance
2961 * @request: address of the request pointer to be initialized
2962 * @response: address of the response pointer to be initialized
2963 * @opcode: operation to perform
2964 * @idn: flag idn to access
2965 * @index: LU number to access
2966 * @selector: query/flag/descriptor further identification
2967 */
2968static inline void ufshcd_init_query(struct ufs_hba *hba,
2969 struct ufs_query_req **request, struct ufs_query_res **response,
2970 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2971{
2972 *request = &hba->dev_cmd.query.request;
2973 *response = &hba->dev_cmd.query.response;
2974 memset(*request, 0, sizeof(struct ufs_query_req));
2975 memset(*response, 0, sizeof(struct ufs_query_res));
2976 (*request)->upiu_req.opcode = opcode;
2977 (*request)->upiu_req.idn = idn;
2978 (*request)->upiu_req.index = index;
2979 (*request)->upiu_req.selector = selector;
2980}
2981
dc3c8d3a 2982static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1f34eedf 2983 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
dc3c8d3a
YG		 2984{
2985 int ret;
2986 int retries;
2987
2988 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1f34eedf 2989 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
dc3c8d3a
YG		 2990 if (ret)
2991 dev_dbg(hba->dev,
2992 "%s: failed with error %d, retries %d\n",
2993 __func__, ret, retries);
2994 else
2995 break;
2996 }
2997
2998 if (ret)
2999 dev_err(hba->dev,
3000 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3001 __func__, opcode, idn, ret, retries);
3002 return ret;
3003}
3004
68078d5c
DR		 3005/**
3006 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 3007 * @hba: per-adapter instance
3008 * @opcode: flag query to perform
3009 * @idn: flag idn to access
1f34eedf 3010 * @index: flag index to access
8aa29f19 3011 * @flag_res: the flag value after the query request completes
68078d5c
DR		 3012 *
3013 * Returns 0 for success, non-zero in case of failure
3014 */
dc3c8d3a 3015int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 3016 enum flag_idn idn, u8 index, bool *flag_res)
68078d5c 3017{
d44a5f98
DR		 3018 struct ufs_query_req *request = NULL;
3019 struct ufs_query_res *response = NULL;
1f34eedf 3020 int err, selector = 0;
e5ad406c 3021 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 3022
3023 BUG_ON(!hba);
3024
1ab27c9c 3025 ufshcd_hold(hba, false);
68078d5c 3026 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3027 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3028 selector);
68078d5c
DR		 3029
3030 switch (opcode) {
3031 case UPIU_QUERY_OPCODE_SET_FLAG:
3032 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3033 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3034 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3035 break;
3036 case UPIU_QUERY_OPCODE_READ_FLAG:
3037 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3038 if (!flag_res) {
3039 /* No dummy reads */
3040 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3041 __func__);
3042 err = -EINVAL;
3043 goto out_unlock;
3044 }
3045 break;
3046 default:
3047 dev_err(hba->dev,
3048 "%s: Expected query flag opcode but got = %d\n",
3049 __func__, opcode);
3050 err = -EINVAL;
3051 goto out_unlock;
3052 }
68078d5c 3053
e5ad406c 3054 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 3055
3056 if (err) {
3057 dev_err(hba->dev,
3058 "%s: Sending flag query for idn %d failed, err = %d\n",
3059 __func__, idn, err);
3060 goto out_unlock;
3061 }
3062
3063 if (flag_res)
e8c8e82a 3064 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 3065 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3066
3067out_unlock:
3068 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3069 ufshcd_release(hba);
68078d5c
DR		 3070 return err;
3071}
3072
66ec6d59
SRT		 3073/**
3074 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 3075 * @hba: per-adapter instance
3076 * @opcode: attribute opcode
3077 * @idn: attribute idn to access
3078 * @index: index field
3079 * @selector: selector field
3080 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 3081 *
3082 * Returns 0 for success, non-zero in case of failure
3083*/
ec92b59c
SN		 3084int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3085 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 3086{
d44a5f98
DR		 3087 struct ufs_query_req *request = NULL;
3088 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 3089 int err;
3090
3091 BUG_ON(!hba);
3092
3093 if (!attr_val) {
3094 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3095 __func__, opcode);
8ca1a40b 3096 return -EINVAL;
66ec6d59
SRT		 3097 }
3098
8ca1a40b 3099 ufshcd_hold(hba, false);
3100
66ec6d59 3101 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3102 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3103 selector);
66ec6d59
SRT		 3104
3105 switch (opcode) {
3106 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3107 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 3108 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 3109 break;
3110 case UPIU_QUERY_OPCODE_READ_ATTR:
3111 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3112 break;
3113 default:
3114 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3115 __func__, opcode);
3116 err = -EINVAL;
3117 goto out_unlock;
3118 }
3119
d44a5f98 3120 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 3121
3122 if (err) {
4b761b58
YG		 3123 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3124 __func__, opcode, idn, index, err);
66ec6d59
SRT		 3125 goto out_unlock;
3126 }
3127
e8c8e82a 3128 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 3129
3130out_unlock:
3131 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3132 ufshcd_release(hba);
66ec6d59
SRT		 3133 return err;
3134}
3135
5e86ae44
YG		 3136/**
3137 * ufshcd_query_attr_retry() - API function for sending query
3138 * attribute with retries
3139 * @hba: per-adapter instance
3140 * @opcode: attribute opcode
3141 * @idn: attribute idn to access
3142 * @index: index field
3143 * @selector: selector field
3144 * @attr_val: the attribute value after the query request
3145 * completes
3146 *
3147 * Returns 0 for success, non-zero in case of failure
3148*/
41d8a933 3149int ufshcd_query_attr_retry(struct ufs_hba *hba,
5e86ae44
YG		 3150 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3151 u32 *attr_val)
3152{
3153 int ret = 0;
3154 u32 retries;
3155
68c9fcfd 3156 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 3157 ret = ufshcd_query_attr(hba, opcode, idn, index,
3158 selector, attr_val);
3159 if (ret)
3160 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3161 __func__, ret, retries);
3162 else
3163 break;
3164 }
3165
3166 if (ret)
3167 dev_err(hba->dev,
3168 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3169 __func__, idn, ret, QUERY_REQ_RETRIES);
3170 return ret;
3171}
3172
a70e91b8 3173static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 3174 enum query_opcode opcode, enum desc_idn idn, u8 index,
3175 u8 selector, u8 *desc_buf, int *buf_len)
3176{
3177 struct ufs_query_req *request = NULL;
3178 struct ufs_query_res *response = NULL;
3179 int err;
3180
3181 BUG_ON(!hba);
3182
3183 if (!desc_buf) {
3184 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3185 __func__, opcode);
8ca1a40b 3186 return -EINVAL;
d44a5f98
DR		 3187 }
3188
a4b0e8a4 3189 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 3190 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3191 __func__, *buf_len);
8ca1a40b 3192 return -EINVAL;
d44a5f98
DR		 3193 }
3194
8ca1a40b 3195 ufshcd_hold(hba, false);
3196
d44a5f98
DR		 3197 mutex_lock(&hba->dev_cmd.lock);
3198 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3199 selector);
3200 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3201 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3202
3203 switch (opcode) {
3204 case UPIU_QUERY_OPCODE_WRITE_DESC:
3205 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3206 break;
3207 case UPIU_QUERY_OPCODE_READ_DESC:
3208 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3209 break;
3210 default:
3211 dev_err(hba->dev,
3212 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3213 __func__, opcode);
3214 err = -EINVAL;
3215 goto out_unlock;
3216 }
3217
3218 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3219
3220 if (err) {
4b761b58
YG		 3221 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3222 __func__, opcode, idn, index, err);
d44a5f98
DR		 3223 goto out_unlock;
3224 }
3225
ea2aab24 3226 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3227
3228out_unlock:
cfcbae38 3229 hba->dev_cmd.query.descriptor = NULL;
d44a5f98 3230 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3231 ufshcd_release(hba);
d44a5f98
DR		 3232 return err;
3233}
3234
a70e91b8 3235/**
8aa29f19
BVA		 3236 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3237 * @hba: per-adapter instance
3238 * @opcode: attribute opcode
3239 * @idn: attribute idn to access
3240 * @index: index field
3241 * @selector: selector field
3242 * @desc_buf: the buffer that contains the descriptor
3243 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3244 *
3245 * Returns 0 for success, non-zero in case of failure.
3246 * The buf_len parameter will contain, on return, the length parameter
3247 * received on the response.
3248 */
2238d31c
SN		 3249int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3250 enum query_opcode opcode,
3251 enum desc_idn idn, u8 index,
3252 u8 selector,
3253 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3254{
3255 int err;
3256 int retries;
3257
3258 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3259 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3260 selector, desc_buf, buf_len);
3261 if (!err || err == -EINVAL)
3262 break;
3263 }
3264
3265 return err;
3266}
a70e91b8 3267
a4b0e8a4
PM		 3268/**
3269 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3270 * @hba: Pointer to adapter instance
3271 * @desc_id: descriptor idn value
3272 * @desc_len: mapped desc length (out)
a4b0e8a4 3273 */
7a0bf85b
BH		 3274void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3275 int *desc_len)
a4b0e8a4 3276{
7a0bf85b
BH		 3277 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3278 desc_id == QUERY_DESC_IDN_RFU_1)
a4b0e8a4 3279 *desc_len = 0;
7a0bf85b
BH		 3280 else
3281 *desc_len = hba->desc_size[desc_id];
a4b0e8a4
PM		 3282}
3283EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3284
7a0bf85b 3285static void ufshcd_update_desc_length(struct ufs_hba *hba,
72fb690e 3286 enum desc_idn desc_id, int desc_index,
7a0bf85b
BH		 3287 unsigned char desc_len)
3288{
3289 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
72fb690e
BH		 3290 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3291 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3292 * than the RPMB unit, however, both descriptors share the same
3293 * desc_idn, to cover both unit descriptors with one length, we
3294 * choose the normal unit descriptor length by desc_index.
3295 */
7a0bf85b
BH		 3296 hba->desc_size[desc_id] = desc_len;
3297}
3298
da461cec
SJ		 3299/**
3300 * ufshcd_read_desc_param - read the specified descriptor parameter
3301 * @hba: Pointer to adapter instance
3302 * @desc_id: descriptor idn value
3303 * @desc_index: descriptor index
3304 * @param_offset: offset of the parameter to read
3305 * @param_read_buf: pointer to buffer where parameter would be read
3306 * @param_size: sizeof(param_read_buf)
3307 *
3308 * Return 0 in case of success, non-zero otherwise
3309 */
45bced87
SN		 3310int ufshcd_read_desc_param(struct ufs_hba *hba,
3311 enum desc_idn desc_id,
3312 int desc_index,
3313 u8 param_offset,
3314 u8 *param_read_buf,
3315 u8 param_size)
da461cec
SJ		 3316{
3317 int ret;
3318 u8 *desc_buf;
a4b0e8a4 3319 int buff_len;
da461cec
SJ		 3320 bool is_kmalloc = true;
3321
a4b0e8a4
PM		 3322 /* Safety check */
3323 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3324 return -EINVAL;
3325
7a0bf85b
BH		 3326 /* Get the length of descriptor */
3327 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3328 if (!buff_len) {
1699f980
CG		 3329 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3330 return -EINVAL;
3331 }
3332
3333 if (param_offset >= buff_len) {
3334 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3335 __func__, param_offset, desc_id, buff_len);
7a0bf85b 3336 return -EINVAL;
a4b0e8a4
PM		 3337 }
3338
3339 /* Check whether we need temp memory */
3340 if (param_offset != 0 || param_size < buff_len) {
1699f980 3341 desc_buf = kzalloc(buff_len, GFP_KERNEL);
da461cec
SJ		 3342 if (!desc_buf)
3343 return -ENOMEM;
a4b0e8a4
PM		 3344 } else {
3345 desc_buf = param_read_buf;
3346 is_kmalloc = false;
da461cec
SJ		 3347 }
3348
a4b0e8a4 3349 /* Request for full descriptor */
a70e91b8 3350 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3351 desc_id, desc_index, 0,
3352 desc_buf, &buff_len);
da461cec 3353
bde44bb6 3354 if (ret) {
1699f980 3355 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
bde44bb6 3356 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3357 goto out;
3358 }
3359
bde44bb6 3360 /* Sanity check */
3361 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1699f980 3362 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
bde44bb6 3363 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3364 ret = -EINVAL;
3365 goto out;
3366 }
3367
7a0bf85b
BH		 3368 /* Update descriptor length */
3369 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
72fb690e 3370 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
7a0bf85b 3371
1699f980
CG		 3372 if (is_kmalloc) {
3373 /* Make sure we don't copy more data than available */
d3d9c457
BVA		 3374 if (param_offset >= buff_len)
3375 ret = -EINVAL;
3376 else
3377 memcpy(param_read_buf, &desc_buf[param_offset],
3378 min_t(u32, param_size, buff_len - param_offset));
1699f980 3379 }
da461cec
SJ		 3380out:
3381 if (is_kmalloc)
3382 kfree(desc_buf);
3383 return ret;
3384}
3385
4b828fe1
TW		 3386/**
3387 * struct uc_string_id - unicode string
3388 *
3389 * @len: size of this descriptor inclusive
3390 * @type: descriptor type
3391 * @uc: unicode string character
3392 */
3393struct uc_string_id {
3394 u8 len;
3395 u8 type;
ec38c0ad 3396 wchar_t uc[];
4b828fe1
TW		 3397} __packed;
3398
3399/* replace non-printable or non-ASCII characters with spaces */
3400static inline char ufshcd_remove_non_printable(u8 ch)
3401{
3402 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3403}
3404
b573d484
YG		 3405/**
3406 * ufshcd_read_string_desc - read string descriptor
3407 * @hba: pointer to adapter instance
3408 * @desc_index: descriptor index
4b828fe1
TW		 3409 * @buf: pointer to buffer where descriptor would be read,
3410 * the caller should free the memory.
b573d484 3411 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3412 * null terminated string.
b573d484 3413 *
4b828fe1
TW		 3414 * Return:
3415 * * string size on success.
3416 * * -ENOMEM: on allocation failure
3417 * * -EINVAL: on a wrong parameter
b573d484 3418 */
4b828fe1
TW		 3419int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3420 u8 **buf, bool ascii)
b573d484 3421{
4b828fe1
TW		 3422 struct uc_string_id *uc_str;
3423 u8 *str;
3424 int ret;
b573d484 3425
4b828fe1
TW		 3426 if (!buf)
3427 return -EINVAL;
b573d484 3428
4b828fe1
TW		 3429 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3430 if (!uc_str)
3431 return -ENOMEM;
b573d484 3432
c4607a09
BH		 3433 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3434 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
4b828fe1
TW		 3435 if (ret < 0) {
3436 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3437 QUERY_REQ_RETRIES, ret);
3438 str = NULL;
3439 goto out;
3440 }
3441
3442 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3443 dev_dbg(hba->dev, "String Desc is of zero length\n");
3444 str = NULL;
3445 ret = 0;
b573d484
YG		 3446 goto out;
3447 }
3448
3449 if (ascii) {
4b828fe1 3450 ssize_t ascii_len;
b573d484 3451 int i;
b573d484 3452 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3453 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3454 str = kzalloc(ascii_len, GFP_KERNEL);
3455 if (!str) {
3456 ret = -ENOMEM;
fcbefc3b 3457 goto out;
b573d484
YG		 3458 }
3459
3460 /*
3461 * the descriptor contains string in UTF16 format
3462 * we need to convert to utf-8 so it can be displayed
3463 */
4b828fe1
TW		 3464 ret = utf16s_to_utf8s(uc_str->uc,
3465 uc_str->len - QUERY_DESC_HDR_SIZE,
3466 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3467
3468 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3469 for (i = 0; i < ret; i++)
3470 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3471
4b828fe1
TW		 3472 str[ret++] = '\0';
3473
3474 } else {
5f57704d 3475 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3476 if (!str) {
3477 ret = -ENOMEM;
3478 goto out;
3479 }
4b828fe1 3480 ret = uc_str->len;
b573d484
YG		 3481 }
3482out:
4b828fe1
TW		 3483 *buf = str;
3484 kfree(uc_str);
3485 return ret;
b573d484 3486}
b573d484 3487
da461cec
SJ		 3488/**
3489 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3490 * @hba: Pointer to adapter instance
3491 * @lun: lun id
3492 * @param_offset: offset of the parameter to read
3493 * @param_read_buf: pointer to buffer where parameter would be read
3494 * @param_size: sizeof(param_read_buf)
3495 *
3496 * Return 0 in case of success, non-zero otherwise
3497 */
3498static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3499 int lun,
3500 enum unit_desc_param param_offset,
3501 u8 *param_read_buf,
3502 u32 param_size)
3503{
3504 /*
3505 * Unit descriptors are only available for general purpose LUs (LUN id
3506 * from 0 to 7) and RPMB Well known LU.
3507 */
a2fca52e 3508 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
da461cec
SJ		 3509 return -EOPNOTSUPP;
3510
3511 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3512 param_offset, param_read_buf, param_size);
3513}
3514
09f17791
CG		 3515static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3516{
3517 int err = 0;
3518 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3519
3520 if (hba->dev_info.wspecversion >= 0x300) {
3521 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3522 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3523 &gating_wait);
3524 if (err)
3525 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3526 err, gating_wait);
3527
3528 if (gating_wait == 0) {
3529 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3530 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3531 gating_wait);
3532 }
3533
3534 hba->dev_info.clk_gating_wait_us = gating_wait;
3535 }
3536
3537 return err;
3538}
3539
7a3e97b0
SY		 3540/**
3541 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3542 * @hba: per adapter instance
3543 *
3544 * 1. Allocate DMA memory for Command Descriptor array
3545 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3546 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3547 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3548 * (UTMRDL)
3549 * 4. Allocate memory for local reference block(lrb).
3550 *
3551 * Returns 0 for success, non-zero in case of failure
3552 */
3553static int ufshcd_memory_alloc(struct ufs_hba *hba)
3554{
3555 size_t utmrdl_size, utrdl_size, ucdl_size;
3556
3557 /* Allocate memory for UTP command descriptors */
3558 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3559 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3560 ucdl_size,
3561 &hba->ucdl_dma_addr,
3562 GFP_KERNEL);
7a3e97b0
SY		 3563
3564 /*
3565 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3566 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3567 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3568 * be aligned to 128 bytes as well
3569 */
3570 if (!hba->ucdl_base_addr ||
3571 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3572 dev_err(hba->dev,
7a3e97b0
SY		 3573 "Command Descriptor Memory allocation failed\n");
3574 goto out;
3575 }
3576
3577 /*
3578 * Allocate memory for UTP Transfer descriptors
3579 * UFSHCI requires 1024 byte alignment of UTRD
3580 */
3581 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3582 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3583 utrdl_size,
3584 &hba->utrdl_dma_addr,
3585 GFP_KERNEL);
7a3e97b0
SY		 3586 if (!hba->utrdl_base_addr ||
3587 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3588 dev_err(hba->dev,
7a3e97b0
SY		 3589 "Transfer Descriptor Memory allocation failed\n");
3590 goto out;
3591 }
3592
3593 /*
3594 * Allocate memory for UTP Task Management descriptors
3595 * UFSHCI requires 1024 byte alignment of UTMRD
3596 */
3597 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3598 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3599 utmrdl_size,
3600 &hba->utmrdl_dma_addr,
3601 GFP_KERNEL);
7a3e97b0
SY		 3602 if (!hba->utmrdl_base_addr ||
3603 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3604 dev_err(hba->dev,
7a3e97b0
SY		 3605 "Task Management Descriptor Memory allocation failed\n");
3606 goto out;
3607 }
3608
3609 /* Allocate memory for local reference block */
a86854d0
KC		 3610 hba->lrb = devm_kcalloc(hba->dev,
3611 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3612 GFP_KERNEL);
7a3e97b0 3613 if (!hba->lrb) {
3b1d0580 3614 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3615 goto out;
3616 }
3617 return 0;
3618out:
7a3e97b0
SY		 3619 return -ENOMEM;
3620}
3621
3622/**
3623 * ufshcd_host_memory_configure - configure local reference block with
3624 * memory offsets
3625 * @hba: per adapter instance
3626 *
3627 * Configure Host memory space
3628 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3629 * address.
3630 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3631 * and PRDT offset.
3632 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3633 * into local reference block.
3634 */
3635static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3636{
7a3e97b0
SY		 3637 struct utp_transfer_req_desc *utrdlp;
3638 dma_addr_t cmd_desc_dma_addr;
3639 dma_addr_t cmd_desc_element_addr;
3640 u16 response_offset;
3641 u16 prdt_offset;
3642 int cmd_desc_size;
3643 int i;
3644
3645 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3646
3647 response_offset =
3648 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3649 prdt_offset =
3650 offsetof(struct utp_transfer_cmd_desc, prd_table);
3651
3652 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3653 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3654
3655 for (i = 0; i < hba->nutrs; i++) {
3656 /* Configure UTRD with command descriptor base address */
3657 cmd_desc_element_addr =
3658 (cmd_desc_dma_addr + (cmd_desc_size * i));
3659 utrdlp[i].command_desc_base_addr_lo =
3660 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3661 utrdlp[i].command_desc_base_addr_hi =
3662 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3663
3664 /* Response upiu and prdt offset should be in double words */
26f968d7
AA		 3665 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3666 utrdlp[i].response_upiu_offset =
3667 cpu_to_le16(response_offset);
3668 utrdlp[i].prd_table_offset =
3669 cpu_to_le16(prdt_offset);
3670 utrdlp[i].response_upiu_length =
3671 cpu_to_le16(ALIGNED_UPIU_SIZE);
3672 } else {
3673 utrdlp[i].response_upiu_offset =
3674 cpu_to_le16(response_offset >> 2);
3675 utrdlp[i].prd_table_offset =
3676 cpu_to_le16(prdt_offset >> 2);
3677 utrdlp[i].response_upiu_length =
3678 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3679 }
7a3e97b0 3680
4d2b8d40 3681 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3682 }
3683}
3684
3685/**
3686 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3687 * @hba: per adapter instance
3688 *
3689 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3690 * in order to initialize the Unipro link startup procedure.
3691 * Once the Unipro links are up, the device connected to the controller
3692 * is detected.
3693 *
3694 * Returns 0 on success, non-zero value on failure
3695 */
3696static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3697{
6ccf44fe
SJ		 3698 struct uic_command uic_cmd = {0};
3699 int ret;
7a3e97b0 3700
6ccf44fe 3701 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3702
6ccf44fe
SJ		 3703 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3704 if (ret)
ff8e20c6 3705 dev_dbg(hba->dev,
6ccf44fe
SJ		 3706 "dme-link-startup: error code %d\n", ret);
3707 return ret;
7a3e97b0 3708}
39bf2d83
AA		 3709/**
3710 * ufshcd_dme_reset - UIC command for DME_RESET
3711 * @hba: per adapter instance
3712 *
3713 * DME_RESET command is issued in order to reset UniPro stack.
3714 * This function now deals with cold reset.
3715 *
3716 * Returns 0 on success, non-zero value on failure
3717 */
3718static int ufshcd_dme_reset(struct ufs_hba *hba)
3719{
3720 struct uic_command uic_cmd = {0};
3721 int ret;
3722
3723 uic_cmd.command = UIC_CMD_DME_RESET;
3724
3725 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3726 if (ret)
3727 dev_err(hba->dev,
3728 "dme-reset: error code %d\n", ret);
3729
3730 return ret;
3731}
3732
fc85a74e
SC		 3733int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3734 int agreed_gear,
3735 int adapt_val)
3736{
3737 int ret;
3738
3739 if (agreed_gear != UFS_HS_G4)
66df79cc 3740 adapt_val = PA_NO_ADAPT;
fc85a74e
SC		 3741
3742 ret = ufshcd_dme_set(hba,
3743 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3744 adapt_val);
3745 return ret;
3746}
3747EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3748
39bf2d83
AA		 3749/**
3750 * ufshcd_dme_enable - UIC command for DME_ENABLE
3751 * @hba: per adapter instance
3752 *
3753 * DME_ENABLE command is issued in order to enable UniPro stack.
3754 *
3755 * Returns 0 on success, non-zero value on failure
3756 */
3757static int ufshcd_dme_enable(struct ufs_hba *hba)
3758{
3759 struct uic_command uic_cmd = {0};
3760 int ret;
3761
3762 uic_cmd.command = UIC_CMD_DME_ENABLE;
3763
3764 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3765 if (ret)
3766 dev_err(hba->dev,
1fa05700 3767 "dme-enable: error code %d\n", ret);
39bf2d83
AA		 3768
3769 return ret;
3770}
7a3e97b0 3771
cad2e03d
YG		 3772static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3773{
3774 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3775 unsigned long min_sleep_time_us;
3776
3777 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3778 return;
3779
3780 /*
3781 * last_dme_cmd_tstamp will be 0 only for 1st call to
3782 * this function
3783 */
3784 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3785 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3786 } else {
3787 unsigned long delta =
3788 (unsigned long) ktime_to_us(
3789 ktime_sub(ktime_get(),
3790 hba->last_dme_cmd_tstamp));
3791
3792 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3793 min_sleep_time_us =
3794 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3795 else
3796 return; /* no more delay required */
3797 }
3798
3799 /* allow sleep for extra 50us if needed */
3800 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3801}
3802
12b4fdb4
SJ		 3803/**
3804 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3805 * @hba: per adapter instance
3806 * @attr_sel: uic command argument1
3807 * @attr_set: attribute set type as uic command argument2
3808 * @mib_val: setting value as uic command argument3
3809 * @peer: indicate whether peer or local
3810 *
3811 * Returns 0 on success, non-zero value on failure
3812 */
3813int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3814 u8 attr_set, u32 mib_val, u8 peer)
3815{
3816 struct uic_command uic_cmd = {0};
3817 static const char *const action[] = {
3818 "dme-set",
3819 "dme-peer-set"
3820 };
3821 const char *set = action[!!peer];
3822 int ret;
64238fbd 3823 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3824
3825 uic_cmd.command = peer ?
3826 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3827 uic_cmd.argument1 = attr_sel;
3828 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3829 uic_cmd.argument3 = mib_val;
3830
64238fbd
YG		 3831 do {
3832 /* for peer attributes we retry upon failure */
3833 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3834 if (ret)
3835 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3836 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3837 } while (ret && peer && --retries);
3838
f37e9f8c 3839 if (ret)
64238fbd 3840 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3841 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3842 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3843
3844 return ret;
3845}
3846EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3847
3848/**
3849 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3850 * @hba: per adapter instance
3851 * @attr_sel: uic command argument1
3852 * @mib_val: the value of the attribute as returned by the UIC command
3853 * @peer: indicate whether peer or local
3854 *
3855 * Returns 0 on success, non-zero value on failure
3856 */
3857int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3858 u32 *mib_val, u8 peer)
3859{
3860 struct uic_command uic_cmd = {0};
3861 static const char *const action[] = {
3862 "dme-get",
3863 "dme-peer-get"
3864 };
3865 const char *get = action[!!peer];
3866 int ret;
64238fbd 3867 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3868 struct ufs_pa_layer_attr orig_pwr_info;
3869 struct ufs_pa_layer_attr temp_pwr_info;
3870 bool pwr_mode_change = false;
3871
3872 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3873 orig_pwr_info = hba->pwr_info;
3874 temp_pwr_info = orig_pwr_info;
3875
3876 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3877 orig_pwr_info.pwr_rx == FAST_MODE) {
3878 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3879 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3880 pwr_mode_change = true;
3881 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3882 orig_pwr_info.pwr_rx == SLOW_MODE) {
3883 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3884 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3885 pwr_mode_change = true;
3886 }
3887 if (pwr_mode_change) {
3888 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3889 if (ret)
3890 goto out;
3891 }
3892 }
12b4fdb4
SJ		 3893
3894 uic_cmd.command = peer ?
3895 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3896 uic_cmd.argument1 = attr_sel;
3897
64238fbd
YG		 3898 do {
3899 /* for peer attributes we retry upon failure */
3900 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3901 if (ret)
3902 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3903 get, UIC_GET_ATTR_ID(attr_sel), ret);
3904 } while (ret && peer && --retries);
3905
f37e9f8c 3906 if (ret)
64238fbd 3907 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3908 get, UIC_GET_ATTR_ID(attr_sel),
3909 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3910
64238fbd 3911 if (mib_val && !ret)
12b4fdb4 3912 *mib_val = uic_cmd.argument3;
874237f7
YG		 3913
3914 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3915 && pwr_mode_change)
3916 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3917out:
3918 return ret;
3919}
3920EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3921
a113eaaf
BVA		 3922static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
3923{
3924 lockdep_assert_held(hba->host->host_lock);
3925
3926 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
3927 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
3928}
3929
3930static void ufshcd_schedule_eh(struct ufs_hba *hba)
3931{
3932 bool schedule_eh = false;
3933 unsigned long flags;
3934
3935 spin_lock_irqsave(hba->host->host_lock, flags);
3936 /* handle fatal errors only when link is not in error state */
3937 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
3938 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
3939 ufshcd_is_saved_err_fatal(hba))
3940 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
3941 else
3942 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
3943 schedule_eh = true;
3944 }
3945 spin_unlock_irqrestore(hba->host->host_lock, flags);
3946
3947 if (schedule_eh)
3948 scsi_schedule_eh(hba->host);
3949}
3950
53b3d9c3 3951/**
57d104c1
SJ		 3952 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3953 * state) and waits for it to take effect.
3954 *
53b3d9c3 3955 * @hba: per adapter instance
57d104c1
SJ		 3956 * @cmd: UIC command to execute
3957 *
3958 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3959 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3960 * and device UniPro link and hence it's final completion would be indicated by
3961 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3962 * addition to normal UIC command completion Status (UCCS). This function only
3963 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3964 *
3965 * Returns 0 on success, non-zero value on failure
3966 */
57d104c1 3967static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3968{
8a686f26 3969 DECLARE_COMPLETION_ONSTACK(uic_async_done);
53b3d9c3 3970 unsigned long flags;
a113eaaf 3971 bool schedule_eh = false;
53b3d9c3
SJ		 3972 u8 status;
3973 int ret;
d75f7fe4 3974 bool reenable_intr = false;
53b3d9c3 3975
53b3d9c3 3976 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d 3977 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3978
3979 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236
CG		 3980 if (ufshcd_is_link_broken(hba)) {
3981 ret = -ENOLINK;
3982 goto out_unlock;
3983 }
57d104c1 3984 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3985 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3986 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3987 /*
3988 * Make sure UIC command completion interrupt is disabled before
3989 * issuing UIC command.
3990 */
3991 wmb();
3992 reenable_intr = true;
57d104c1 3993 }
d75f7fe4
YG		 3994 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3995 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3996 if (ret) {
3997 dev_err(hba->dev,
3998 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3999 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 4000 goto out;
4001 }
4002
57d104c1 4003 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 4004 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4005 dev_err(hba->dev,
57d104c1
SJ		 4006 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4007 cmd->command, cmd->argument3);
0f52fcb9
CG		 4008
4009 if (!cmd->cmd_active) {
4010 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4011 __func__);
4012 goto check_upmcrs;
4013 }
4014
53b3d9c3
SJ		 4015 ret = -ETIMEDOUT;
4016 goto out;
4017 }
4018
0f52fcb9 4019check_upmcrs:
53b3d9c3
SJ		 4020 status = ufshcd_get_upmcrs(hba);
4021 if (status != PWR_LOCAL) {
4022 dev_err(hba->dev,
479da360 4023 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 4024 cmd->command, status);
53b3d9c3
SJ		 4025 ret = (status != PWR_OK) ? status : -1;
4026 }
4027out:
7942f7b5
VG		 4028 if (ret) {
4029 ufshcd_print_host_state(hba);
4030 ufshcd_print_pwr_info(hba);
e965e5e0 4031 ufshcd_print_evt_hist(hba);
7942f7b5
VG		 4032 }
4033
53b3d9c3 4034 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 4035 hba->active_uic_cmd = NULL;
57d104c1 4036 hba->uic_async_done = NULL;
d75f7fe4
YG		 4037 if (reenable_intr)
4038 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4db7a236
CG		 4039 if (ret) {
4040 ufshcd_set_link_broken(hba);
a113eaaf 4041 schedule_eh = true;
4db7a236 4042 }
a113eaaf 4043
4db7a236 4044out_unlock:
53b3d9c3 4045 spin_unlock_irqrestore(hba->host->host_lock, flags);
a113eaaf
BVA		 4046
4047 if (schedule_eh)
4048 ufshcd_schedule_eh(hba);
53b3d9c3 4049 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 4050
53b3d9c3
SJ		 4051 return ret;
4052}
4053
57d104c1
SJ		 4054/**
4055 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4056 * using DME_SET primitives.
4057 * @hba: per adapter instance
4058 * @mode: powr mode value
4059 *
4060 * Returns 0 on success, non-zero value on failure
4061 */
4062static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4063{
4064 struct uic_command uic_cmd = {0};
1ab27c9c 4065 int ret;
57d104c1 4066
c3a2f9ee
YG		 4067 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4068 ret = ufshcd_dme_set(hba,
4069 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4070 if (ret) {
4071 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4072 __func__, ret);
4073 goto out;
4074 }
4075 }
4076
57d104c1
SJ		 4077 uic_cmd.command = UIC_CMD_DME_SET;
4078 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4079 uic_cmd.argument3 = mode;
1ab27c9c
ST		 4080 ufshcd_hold(hba, false);
4081 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4082 ufshcd_release(hba);
57d104c1 4083
c3a2f9ee 4084out:
1ab27c9c 4085 return ret;
57d104c1
SJ		 4086}
4087
087c5efa 4088int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 4089{
4090 int ret;
4091 unsigned long flags;
4092
4093 spin_lock_irqsave(hba->host->host_lock, flags);
4094 hba->ufshcd_state = UFSHCD_STATE_RESET;
4095 ufshcd_set_eh_in_progress(hba);
4096 spin_unlock_irqrestore(hba->host->host_lock, flags);
4097
ebdd1dfd 4098 /* Reset the attached device */
31a5d9ca 4099 ufshcd_device_reset(hba);
ebdd1dfd 4100
53c12d0e
YG		 4101 ret = ufshcd_host_reset_and_restore(hba);
4102
4103 spin_lock_irqsave(hba->host->host_lock, flags);
4104 if (ret)
4105 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4106 ufshcd_clear_eh_in_progress(hba);
4107 spin_unlock_irqrestore(hba->host->host_lock, flags);
4108
4109 if (ret)
4110 dev_err(hba->dev, "%s: link recovery failed, err %d",
4111 __func__, ret);
4ee7ee53
JK		 4112 else
4113 ufshcd_clear_ua_wluns(hba);
53c12d0e
YG		 4114
4115 return ret;
4116}
087c5efa 4117EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 4118
4db7a236 4119static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 4120{
87d0b4a6 4121 int ret;
57d104c1 4122 struct uic_command uic_cmd = {0};
911a0771 4123 ktime_t start = ktime_get();
57d104c1 4124
ee32c909
KK		 4125 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4126
57d104c1 4127 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 4128 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4129 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4130 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 4131
4db7a236 4132 if (ret)
87d0b4a6
YG		 4133 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4134 __func__, ret);
4db7a236 4135 else
ee32c909
KK		 4136 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4137 POST_CHANGE);
53c12d0e 4138
87d0b4a6
YG		 4139 return ret;
4140}
4141
9d19bf7a 4142int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 4143{
4144 struct uic_command uic_cmd = {0};
4145 int ret;
911a0771 4146 ktime_t start = ktime_get();
57d104c1 4147
ee32c909
KK		 4148 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4149
57d104c1
SJ		 4150 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4151 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4152 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4153 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4154
57d104c1 4155 if (ret) {
53c12d0e
YG		 4156 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4157 __func__, ret);
ff8e20c6 4158 } else {
ee32c909
KK		 4159 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4160 POST_CHANGE);
ff8e20c6
DR		 4161 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4162 hba->ufs_stats.hibern8_exit_cnt++;
4163 }
57d104c1
SJ		 4164
4165 return ret;
4166}
9d19bf7a 4167EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 4168
ba7af5ec
SC		 4169void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4170{
4171 unsigned long flags;
be7594a4 4172 bool update = false;
ba7af5ec 4173
be7594a4 4174 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 4175 return;
4176
4177 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 4178 if (hba->ahit != ahit) {
4179 hba->ahit = ahit;
4180 update = true;
4181 }
ba7af5ec 4182 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4 4183
b294ff3e
AD		 4184 if (update &&
4185 !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4186 ufshcd_rpm_get_sync(hba);
be7594a4
CG		 4187 ufshcd_hold(hba, false);
4188 ufshcd_auto_hibern8_enable(hba);
4189 ufshcd_release(hba);
b294ff3e 4190 ufshcd_rpm_put_sync(hba);
be7594a4 4191 }
ba7af5ec
SC		 4192}
4193EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4194
71d848b8 4195void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 4196{
4197 unsigned long flags;
4198
499f7a96 4199 if (!ufshcd_is_auto_hibern8_supported(hba))
ad448378
AH		 4200 return;
4201
4202 spin_lock_irqsave(hba->host->host_lock, flags);
4203 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4204 spin_unlock_irqrestore(hba->host->host_lock, flags);
4205}
4206
5064636c
YG		 4207 /**
4208 * ufshcd_init_pwr_info - setting the POR (power on reset)
4209 * values in hba power info
4210 * @hba: per-adapter instance
4211 */
4212static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4213{
4214 hba->pwr_info.gear_rx = UFS_PWM_G1;
4215 hba->pwr_info.gear_tx = UFS_PWM_G1;
4216 hba->pwr_info.lane_rx = 1;
4217 hba->pwr_info.lane_tx = 1;
4218 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4219 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4220 hba->pwr_info.hs_rate = 0;
4221}
4222
d3e89bac 4223/**
7eb584db
DR		 4224 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4225 * @hba: per-adapter instance
d3e89bac 4226 */
7eb584db 4227static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 4228{
7eb584db
DR		 4229 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4230
4231 if (hba->max_pwr_info.is_valid)
4232 return 0;
4233
2349b533 4234 pwr_info->pwr_tx = FAST_MODE;
4235 pwr_info->pwr_rx = FAST_MODE;
7eb584db 4236 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4237
4238 /* Get the connected lane count */
7eb584db
DR		 4239 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4240 &pwr_info->lane_rx);
4241 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4242 &pwr_info->lane_tx);
4243
4244 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4245 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4246 __func__,
4247 pwr_info->lane_rx,
4248 pwr_info->lane_tx);
4249 return -EINVAL;
4250 }
d3e89bac
SJ		 4251
4252 /*
4253 * First, get the maximum gears of HS speed.
4254 * If a zero value, it means there is no HSGEAR capability.
4255 * Then, get the maximum gears of PWM speed.
4256 */
7eb584db
DR		 4257 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4258 if (!pwr_info->gear_rx) {
4259 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4260 &pwr_info->gear_rx);
4261 if (!pwr_info->gear_rx) {
4262 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4263 __func__, pwr_info->gear_rx);
4264 return -EINVAL;
4265 }
2349b533 4266 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4267 }
4268
7eb584db
DR		 4269 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4270 &pwr_info->gear_tx);
4271 if (!pwr_info->gear_tx) {
d3e89bac 4272 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4273 &pwr_info->gear_tx);
4274 if (!pwr_info->gear_tx) {
4275 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4276 __func__, pwr_info->gear_tx);
4277 return -EINVAL;
4278 }
2349b533 4279 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4280 }
4281
4282 hba->max_pwr_info.is_valid = true;
4283 return 0;
4284}
4285
4286static int ufshcd_change_power_mode(struct ufs_hba *hba,
4287 struct ufs_pa_layer_attr *pwr_mode)
4288{
4289 int ret;
4290
4291 /* if already configured to the requested pwr_mode */
2355b66e
CG		 4292 if (!hba->force_pmc &&
4293 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
7eb584db
DR		 4294 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4295 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4296 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4297 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4298 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4299 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4300 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4301 return 0;
d3e89bac
SJ		 4302 }
4303
4304 /*
4305 * Configure attributes for power mode change with below.
4306 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4307 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4308 * - PA_HSSERIES
4309 */
7eb584db
DR		 4310 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4311 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4312 pwr_mode->lane_rx);
4313 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4314 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4315 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4316 else
4317 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4318
7eb584db
DR		 4319 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4320 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4321 pwr_mode->lane_tx);
4322 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4323 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4324 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4325 else
4326 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4327
7eb584db
DR		 4328 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4329 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4330 pwr_mode->pwr_rx == FAST_MODE ||
4331 pwr_mode->pwr_tx == FAST_MODE)
4332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4333 pwr_mode->hs_rate);
d3e89bac 4334
b1d0d2eb
KK		 4335 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4337 DL_FC0ProtectionTimeOutVal_Default);
4338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4339 DL_TC0ReplayTimeOutVal_Default);
4340 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4341 DL_AFC0ReqTimeOutVal_Default);
4342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4343 DL_FC1ProtectionTimeOutVal_Default);
4344 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4345 DL_TC1ReplayTimeOutVal_Default);
4346 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4347 DL_AFC1ReqTimeOutVal_Default);
4348
4349 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4350 DL_FC0ProtectionTimeOutVal_Default);
4351 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4352 DL_TC0ReplayTimeOutVal_Default);
4353 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4354 DL_AFC0ReqTimeOutVal_Default);
4355 }
08342537 4356
7eb584db
DR		 4357 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4358 | pwr_mode->pwr_tx);
4359
4360 if (ret) {
d3e89bac 4361 dev_err(hba->dev,
7eb584db
DR		 4362 "%s: power mode change failed %d\n", __func__, ret);
4363 } else {
0263bcd0
YG		 4364 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4365 pwr_mode);
7eb584db
DR		 4366
4367 memcpy(&hba->pwr_info, pwr_mode,
4368 sizeof(struct ufs_pa_layer_attr));
4369 }
4370
4371 return ret;
4372}
4373
4374/**
4375 * ufshcd_config_pwr_mode - configure a new power mode
4376 * @hba: per-adapter instance
4377 * @desired_pwr_mode: desired power configuration
4378 */
0d846e70 4379int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4380 struct ufs_pa_layer_attr *desired_pwr_mode)
4381{
4382 struct ufs_pa_layer_attr final_params = { 0 };
4383 int ret;
4384
0263bcd0
YG		 4385 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4386 desired_pwr_mode, &final_params);
4387
4388 if (ret)
7eb584db
DR		 4389 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4390
4391 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4392
4393 return ret;
4394}
0d846e70 4395EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4396
68078d5c
DR		 4397/**
4398 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4399 * @hba: per-adapter instance
68078d5c
DR		 4400 *
4401 * Set fDeviceInit flag and poll until device toggles it.
4402 */
4403static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4404{
dc3c8d3a 4405 int err;
7dfdcc39 4406 bool flag_res = true;
29707fab 4407 ktime_t timeout;
68078d5c 4408
dc3c8d3a 4409 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4410 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
68078d5c
DR		 4411 if (err) {
4412 dev_err(hba->dev,
4413 "%s setting fDeviceInit flag failed with error %d\n",
4414 __func__, err);
4415 goto out;
4416 }
4417
29707fab
KK		 4418 /* Poll fDeviceInit flag to be cleared */
4419 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4420 do {
4421 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4422 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4423 if (!flag_res)
4424 break;
4425 usleep_range(5000, 10000);
4426 } while (ktime_before(ktime_get(), timeout));
dc3c8d3a 4427
29707fab 4428 if (err) {
68078d5c 4429 dev_err(hba->dev,
29707fab
KK		 4430 "%s reading fDeviceInit flag failed with error %d\n",
4431 __func__, err);
4432 } else if (flag_res) {
68078d5c 4433 dev_err(hba->dev,
29707fab
KK		 4434 "%s fDeviceInit was not cleared by the device\n",
4435 __func__);
4436 err = -EBUSY;
4437 }
68078d5c
DR		 4438out:
4439 return err;
4440}
4441
7a3e97b0
SY		 4442/**
4443 * ufshcd_make_hba_operational - Make UFS controller operational
4444 * @hba: per adapter instance
4445 *
4446 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4447 * 1. Enable required interrupts
4448 * 2. Configure interrupt aggregation
897efe62 4449 * 3. Program UTRL and UTMRL base address
5c0c28a8 4450 * 4. Configure run-stop-registers
7a3e97b0
SY		 4451 *
4452 * Returns 0 on success, non-zero value on failure
4453 */
9d19bf7a 4454int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4455{
4456 int err = 0;
4457 u32 reg;
4458
6ccf44fe
SJ		 4459 /* Enable required interrupts */
4460 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4461
4462 /* Configure interrupt aggregation */
b852190e
YG		 4463 if (ufshcd_is_intr_aggr_allowed(hba))
4464 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4465 else
4466 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4467
4468 /* Configure UTRL and UTMRL base address registers */
4469 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4470 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4471 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4472 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4473 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4474 REG_UTP_TASK_REQ_LIST_BASE_L);
4475 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4476 REG_UTP_TASK_REQ_LIST_BASE_H);
4477
897efe62
YG		 4478 /*
4479 * Make sure base address and interrupt setup are updated before
4480 * enabling the run/stop registers below.
4481 */
4482 wmb();
4483
7a3e97b0
SY		 4484 /*
4485 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4486 */
5c0c28a8 4487 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4488 if (!(ufshcd_get_lists_status(reg))) {
4489 ufshcd_enable_run_stop_reg(hba);
4490 } else {
3b1d0580 4491 dev_err(hba->dev,
7a3e97b0
SY		 4492 "Host controller not ready to process requests");
4493 err = -EIO;
7a3e97b0
SY		 4494 }
4495
7a3e97b0
SY		 4496 return err;
4497}
9d19bf7a 4498EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4499
596585a2
YG		 4500/**
4501 * ufshcd_hba_stop - Send controller to reset state
4502 * @hba: per adapter instance
596585a2 4503 */
3a95f5b3 4504void ufshcd_hba_stop(struct ufs_hba *hba)
596585a2 4505{
5cac1095 4506 unsigned long flags;
596585a2
YG		 4507 int err;
4508
5cac1095
BVA		 4509 /*
4510 * Obtain the host lock to prevent that the controller is disabled
4511 * while the UFS interrupt handler is active on another CPU.
4512 */
4513 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4514 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
5cac1095
BVA		 4515 spin_unlock_irqrestore(hba->host->host_lock, flags);
4516
596585a2
YG		 4517 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4518 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
5cac1095 4519 10, 1);
596585a2
YG		 4520 if (err)
4521 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4522}
3a95f5b3 4523EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
596585a2 4524
7a3e97b0 4525/**
39bf2d83 4526 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4527 * @hba: per adapter instance
4528 *
4529 * The controller resets itself and controller firmware initialization
4530 * sequence kicks off. When controller is ready it will set
4531 * the Host Controller Enable bit to 1.
4532 *
4533 * Returns 0 on success, non-zero value on failure
4534 */
39bf2d83 4535static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0 4536{
6081b12c
SC		 4537 int retry_outer = 3;
4538 int retry_inner;
7a3e97b0 4539
6081b12c 4540start:
596585a2 4541 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4542 /* change controller state to "reset state" */
5cac1095 4543 ufshcd_hba_stop(hba);
7a3e97b0 4544
57d104c1
SJ		 4545 /* UniPro link is disabled at this point */
4546 ufshcd_set_link_off(hba);
4547
0263bcd0 4548 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4549
7a3e97b0
SY		 4550 /* start controller initialization sequence */
4551 ufshcd_hba_start(hba);
4552
4553 /*
4554 * To initialize a UFS host controller HCE bit must be set to 1.
4555 * During initialization the HCE bit value changes from 1->0->1.
4556 * When the host controller completes initialization sequence
4557 * it sets the value of HCE bit to 1. The same HCE bit is read back
4558 * to check if the controller has completed initialization sequence.
4559 * So without this delay the value HCE = 1, set in the previous
4560 * instruction might be read back.
4561 * This delay can be changed based on the controller.
4562 */
90b8491c 4563 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
7a3e97b0
SY		 4564
4565 /* wait for the host controller to complete initialization */
6081b12c 4566 retry_inner = 50;
7a3e97b0 4567 while (ufshcd_is_hba_active(hba)) {
6081b12c
SC		 4568 if (retry_inner) {
4569 retry_inner--;
7a3e97b0 4570 } else {
3b1d0580 4571 dev_err(hba->dev,
7a3e97b0 4572 "Controller enable failed\n");
6081b12c
SC		 4573 if (retry_outer) {
4574 retry_outer--;
4575 goto start;
4576 }
7a3e97b0
SY		 4577 return -EIO;
4578 }
9fc305ef 4579 usleep_range(1000, 1100);
7a3e97b0 4580 }
5c0c28a8 4581
1d337ec2 4582 /* enable UIC related interrupts */
57d104c1 4583 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4584
0263bcd0 4585 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4586
7a3e97b0
SY		 4587 return 0;
4588}
39bf2d83
AA		 4589
4590int ufshcd_hba_enable(struct ufs_hba *hba)
4591{
4592 int ret;
4593
4594 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4595 ufshcd_set_link_off(hba);
4596 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4597
4598 /* enable UIC related interrupts */
4599 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4600 ret = ufshcd_dme_reset(hba);
4601 if (!ret) {
4602 ret = ufshcd_dme_enable(hba);
4603 if (!ret)
4604 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4605 if (ret)
4606 dev_err(hba->dev,
4607 "Host controller enable failed with non-hce\n");
4608 }
4609 } else {
4610 ret = ufshcd_hba_execute_hce(hba);
4611 }
4612
4613 return ret;
4614}
9d19bf7a
SC		 4615EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4616
7ca38cf3
YG		 4617static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4618{
ba0320fb 4619 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4620
4621 if (!peer)
4622 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4623 &tx_lanes);
4624 else
4625 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4626 &tx_lanes);
4627 for (i = 0; i < tx_lanes; i++) {
4628 if (!peer)
4629 err = ufshcd_dme_set(hba,
4630 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4631 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4632 0);
4633 else
4634 err = ufshcd_dme_peer_set(hba,
4635 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4636 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4637 0);
4638 if (err) {
4639 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4640 __func__, peer, i, err);
4641 break;
4642 }
4643 }
4644
4645 return err;
4646}
4647
4648static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4649{
4650 return ufshcd_disable_tx_lcc(hba, true);
4651}
4652
e965e5e0 4653void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
8808b4e9 4654{
e965e5e0
SC		 4655 struct ufs_event_hist *e;
4656
4657 if (id >= UFS_EVT_CNT)
4658 return;
4659
4660 e = &hba->ufs_stats.event[id];
4661 e->val[e->pos] = val;
4662 e->tstamp[e->pos] = ktime_get();
b6cacaf2 4663 e->cnt += 1;
e965e5e0 4664 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
172614a9
SC		 4665
4666 ufshcd_vops_event_notify(hba, id, &val);
8808b4e9 4667}
e965e5e0 4668EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
8808b4e9 4669
7a3e97b0 4670/**
6ccf44fe 4671 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4672 * @hba: per adapter instance
4673 *
6ccf44fe 4674 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4675 */
6ccf44fe 4676static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4677{
6ccf44fe 4678 int ret;
1d337ec2 4679 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4680 bool link_startup_again = false;
7a3e97b0 4681
7caf489b 4682 /*
4683 * If UFS device isn't active then we will have to issue link startup
4684 * 2 times to make sure the device state move to active.
4685 */
4686 if (!ufshcd_is_ufs_dev_active(hba))
4687 link_startup_again = true;
7a3e97b0 4688
7caf489b 4689link_startup:
1d337ec2 4690 do {
0263bcd0 4691 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4692
1d337ec2 4693 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4694
1d337ec2
SRT		 4695 /* check if device is detected by inter-connect layer */
4696 if (!ret && !ufshcd_is_device_present(hba)) {
e965e5e0
SC		 4697 ufshcd_update_evt_hist(hba,
4698 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4699 0);
1d337ec2
SRT		 4700 dev_err(hba->dev, "%s: Device not present\n", __func__);
4701 ret = -ENXIO;
4702 goto out;
4703 }
6ccf44fe 4704
1d337ec2
SRT		 4705 /*
4706 * DME link lost indication is only received when link is up,
4707 * but we can't be sure if the link is up until link startup
4708 * succeeds. So reset the local Uni-Pro and try again.
4709 */
8808b4e9 4710 if (ret && ufshcd_hba_enable(hba)) {
e965e5e0
SC		 4711 ufshcd_update_evt_hist(hba,
4712 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4713 (u32)ret);
1d337ec2 4714 goto out;
8808b4e9 4715 }
1d337ec2
SRT		 4716 } while (ret && retries--);
4717
8808b4e9 4718 if (ret) {
1d337ec2 4719 /* failed to get the link up... retire */
e965e5e0
SC		 4720 ufshcd_update_evt_hist(hba,
4721 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4722 (u32)ret);
5c0c28a8 4723 goto out;
8808b4e9 4724 }
5c0c28a8 4725
7caf489b 4726 if (link_startup_again) {
4727 link_startup_again = false;
4728 retries = DME_LINKSTARTUP_RETRIES;
4729 goto link_startup;
4730 }
4731
d2aebb9b 4732 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4733 ufshcd_init_pwr_info(hba);
4734 ufshcd_print_pwr_info(hba);
4735
7ca38cf3
YG		 4736 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4737 ret = ufshcd_disable_device_tx_lcc(hba);
4738 if (ret)
4739 goto out;
4740 }
4741
5c0c28a8 4742 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4743 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4744 if (ret)
4745 goto out;
7a3e97b0 4746
2355b66e
CG		 4747 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4748 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5c0c28a8 4749 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4750out:
7942f7b5 4751 if (ret) {
6ccf44fe 4752 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4753 ufshcd_print_host_state(hba);
4754 ufshcd_print_pwr_info(hba);
e965e5e0 4755 ufshcd_print_evt_hist(hba);
7942f7b5 4756 }
6ccf44fe 4757 return ret;
7a3e97b0
SY		 4758}
4759
5a0b0cb9
SRT		 4760/**
4761 * ufshcd_verify_dev_init() - Verify device initialization
4762 * @hba: per-adapter instance
4763 *
4764 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4765 * device Transport Protocol (UTP) layer is ready after a reset.
4766 * If the UTP layer at the device side is not initialized, it may
4767 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4768 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4769 */
4770static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4771{
4772 int err = 0;
4773 int retries;
4774
1ab27c9c 4775 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4776 mutex_lock(&hba->dev_cmd.lock);
4777 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4778 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4779 NOP_OUT_TIMEOUT);
4780
4781 if (!err || err == -ETIMEDOUT)
4782 break;
4783
4784 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4785 }
4786 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4787 ufshcd_release(hba);
5a0b0cb9
SRT		 4788
4789 if (err)
4790 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4791 return err;
4792}
4793
0ce147d4
SJ		 4794/**
4795 * ufshcd_set_queue_depth - set lun queue depth
4796 * @sdev: pointer to SCSI device
4797 *
4798 * Read bLUQueueDepth value and activate scsi tagged command
4799 * queueing. For WLUN, queue depth is set to 1. For best-effort
4800 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4801 * value that host can queue.
4802 */
4803static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4804{
4805 int ret = 0;
4806 u8 lun_qdepth;
4807 struct ufs_hba *hba;
4808
4809 hba = shost_priv(sdev->host);
4810
4811 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4812 ret = ufshcd_read_unit_desc_param(hba,
4813 ufshcd_scsi_to_upiu_lun(sdev->lun),
4814 UNIT_DESC_PARAM_LU_Q_DEPTH,
4815 &lun_qdepth,
4816 sizeof(lun_qdepth));
0ce147d4
SJ		 4817
4818 /* Some WLUN doesn't support unit descriptor */
4819 if (ret == -EOPNOTSUPP)
4820 lun_qdepth = 1;
4821 else if (!lun_qdepth)
4822 /* eventually, we can figure out the real queue depth */
4823 lun_qdepth = hba->nutrs;
4824 else
4825 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4826
4827 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4828 __func__, lun_qdepth);
db5ed4df 4829 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4830}
4831
57d104c1
SJ		 4832/*
4833 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4834 * @hba: per-adapter instance
4835 * @lun: UFS device lun id
4836 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4837 *
4838 * Returns 0 in case of success and b_lu_write_protect status would be returned
4839 * @b_lu_write_protect parameter.
4840 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4841 * Returns -EINVAL in case of invalid parameters passed to this function.
4842 */
4843static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4844 u8 lun,
4845 u8 *b_lu_write_protect)
4846{
4847 int ret;
4848
4849 if (!b_lu_write_protect)
4850 ret = -EINVAL;
4851 /*
4852 * According to UFS device spec, RPMB LU can't be write
4853 * protected so skip reading bLUWriteProtect parameter for
4854 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4855 */
1baa8011 4856 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4857 ret = -ENOTSUPP;
4858 else
4859 ret = ufshcd_read_unit_desc_param(hba,
4860 lun,
4861 UNIT_DESC_PARAM_LU_WR_PROTECT,
4862 b_lu_write_protect,
4863 sizeof(*b_lu_write_protect));
4864 return ret;
4865}
4866
4867/**
4868 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4869 * status
4870 * @hba: per-adapter instance
4871 * @sdev: pointer to SCSI device
4872 *
4873 */
4874static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4875 struct scsi_device *sdev)
4876{
4877 if (hba->dev_info.f_power_on_wp_en &&
4878 !hba->dev_info.is_lu_power_on_wp) {
4879 u8 b_lu_write_protect;
4880
4881 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4882 &b_lu_write_protect) &&
4883 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4884 hba->dev_info.is_lu_power_on_wp = true;
4885 }
4886}
4887
b294ff3e
AD		 4888/**
4889 * ufshcd_setup_links - associate link b/w device wlun and other luns
4890 * @sdev: pointer to SCSI device
4891 * @hba: pointer to ufs hba
4892 */
4893static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4894{
4895 struct device_link *link;
4896
4897 /*
4898 * Device wlun is the supplier & rest of the luns are consumers.
4899 * This ensures that device wlun suspends after all other luns.
4900 */
4901 if (hba->sdev_ufs_device) {
4902 link = device_link_add(&sdev->sdev_gendev,
4903 &hba->sdev_ufs_device->sdev_gendev,
4904 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4905 if (!link) {
4906 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4907 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4908 return;
4909 }
4910 hba->luns_avail--;
4911 /* Ignore REPORT_LUN wlun probing */
4912 if (hba->luns_avail == 1) {
4913 ufshcd_rpm_put(hba);
4914 return;
4915 }
4916 } else {
4917 /*
4918 * Device wlun is probed. The assumption is that WLUNs are
4919 * scanned before other LUNs.
4920 */
4921 hba->luns_avail--;
4922 }
4923}
4924
7a3e97b0
SY		 4925/**
4926 * ufshcd_slave_alloc - handle initial SCSI device configurations
4927 * @sdev: pointer to SCSI device
4928 *
4929 * Returns success
4930 */
4931static int ufshcd_slave_alloc(struct scsi_device *sdev)
4932{
4933 struct ufs_hba *hba;
4934
4935 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4936
4937 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4938 sdev->use_10_for_ms = 1;
a3a76391
CG		 4939
4940 /* DBD field should be set to 1 in mode sense(10) */
4941 sdev->set_dbd_for_ms = 1;
7a3e97b0 4942
e8e7f271
SRT		 4943 /* allow SCSI layer to restart the device in case of errors */
4944 sdev->allow_restart = 1;
4264fd61 4945
b2a6c522
SRT		 4946 /* REPORT SUPPORTED OPERATION CODES is not supported */
4947 sdev->no_report_opcodes = 1;
4948
84af7e8b
SRT		 4949 /* WRITE_SAME command is not supported */
4950 sdev->no_write_same = 1;
e8e7f271 4951
0ce147d4 4952 ufshcd_set_queue_depth(sdev);
4264fd61 4953
57d104c1
SJ		 4954 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4955
b294ff3e
AD		 4956 ufshcd_setup_links(hba, sdev);
4957
7a3e97b0
SY		 4958 return 0;
4959}
4960
4264fd61
SRT		 4961/**
4962 * ufshcd_change_queue_depth - change queue depth
4963 * @sdev: pointer to SCSI device
4964 * @depth: required depth to set
4264fd61 4965 *
db5ed4df 4966 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4967 */
db5ed4df 4968static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4969{
4970 struct ufs_hba *hba = shost_priv(sdev->host);
4971
4972 if (depth > hba->nutrs)
4973 depth = hba->nutrs;
db5ed4df 4974 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4975}
4976
f02bc975
DP		 4977static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
4978{
4979 /* skip well-known LU */
41d8a933
DP		 4980 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4981 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
f02bc975
DP		 4982 return;
4983
4984 ufshpb_destroy_lu(hba, sdev);
4985}
4986
4987static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
4988{
4989 /* skip well-known LU */
4990 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4991 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4992 return;
4993
4994 ufshpb_init_hpb_lu(hba, sdev);
4995}
4996
eeda4749
AM		 4997/**
4998 * ufshcd_slave_configure - adjust SCSI device configurations
4999 * @sdev: pointer to SCSI device
5000 */
5001static int ufshcd_slave_configure(struct scsi_device *sdev)
5002{
49615ba1 5003 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 5004 struct request_queue *q = sdev->request_queue;
5005
f02bc975
DP		 5006 ufshcd_hpb_configure(hba, sdev);
5007
eeda4749 5008 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2b2bfc8a
KK		 5009 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5010 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
b294ff3e
AD		 5011 /*
5012 * Block runtime-pm until all consumers are added.
5013 * Refer ufshcd_setup_links().
5014 */
5015 if (is_device_wlun(sdev))
5016 pm_runtime_get_noresume(&sdev->sdev_gendev);
5017 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
49615ba1
SC		 5018 sdev->rpm_autosuspend = 1;
5019
df043c74
ST		 5020 ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
5021
eeda4749
AM		 5022 return 0;
5023}
5024
7a3e97b0
SY		 5025/**
5026 * ufshcd_slave_destroy - remove SCSI device configurations
5027 * @sdev: pointer to SCSI device
5028 */
5029static void ufshcd_slave_destroy(struct scsi_device *sdev)
5030{
5031 struct ufs_hba *hba;
bf25967a 5032 unsigned long flags;
7a3e97b0
SY		 5033
5034 hba = shost_priv(sdev->host);
f02bc975
DP		 5035
5036 ufshcd_hpb_destroy(hba, sdev);
5037
0ce147d4 5038 /* Drop the reference as it won't be needed anymore */
7c48bfd0 5039 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
7c48bfd0 5040 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 5041 hba->sdev_ufs_device = NULL;
7c48bfd0 5042 spin_unlock_irqrestore(hba->host->host_lock, flags);
bf25967a
AH		 5043 } else if (hba->sdev_ufs_device) {
5044 struct device *supplier = NULL;
5045
5046 /* Ensure UFS Device WLUN exists and does not disappear */
5047 spin_lock_irqsave(hba->host->host_lock, flags);
5048 if (hba->sdev_ufs_device) {
5049 supplier = &hba->sdev_ufs_device->sdev_gendev;
5050 get_device(supplier);
5051 }
5052 spin_unlock_irqrestore(hba->host->host_lock, flags);
5053
5054 if (supplier) {
5055 /*
5056 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5057 * device will not have been registered but can still
5058 * have a device link holding a reference to the device.
5059 */
5060 device_link_remove(&sdev->sdev_gendev, supplier);
5061 put_device(supplier);
5062 }
7c48bfd0 5063 }
7a3e97b0
SY		 5064}
5065
7a3e97b0
SY		 5066/**
5067 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 5068 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5069 * @scsi_status: SCSI command status
5070 *
5071 * Returns value base on SCSI command status
5072 */
5073static inline int
5074ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5075{
5076 int result = 0;
5077
5078 switch (scsi_status) {
7a3e97b0 5079 case SAM_STAT_CHECK_CONDITION:
1c2623c5 5080 ufshcd_copy_sense_data(lrbp);
df561f66 5081 fallthrough;
1c2623c5 5082 case SAM_STAT_GOOD:
db83d8a5 5083 result |= DID_OK << 16 | scsi_status;
7a3e97b0
SY		 5084 break;
5085 case SAM_STAT_TASK_SET_FULL:
1c2623c5 5086 case SAM_STAT_BUSY:
7a3e97b0 5087 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 5088 ufshcd_copy_sense_data(lrbp);
5089 result |= scsi_status;
7a3e97b0
SY		 5090 break;
5091 default:
5092 result |= DID_ERROR << 16;
5093 break;
5094 } /* end of switch */
5095
5096 return result;
5097}
5098
5099/**
5100 * ufshcd_transfer_rsp_status - Get overall status of the response
5101 * @hba: per adapter instance
8aa29f19 5102 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5103 *
5104 * Returns result of the command to notify SCSI midlayer
5105 */
5106static inline int
5107ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5108{
5109 int result = 0;
5110 int scsi_status;
5111 int ocs;
5112
5113 /* overall command status of utrd */
5114 ocs = ufshcd_get_tr_ocs(lrbp);
5115
d779a6e9
KK		 5116 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5117 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5118 MASK_RSP_UPIU_RESULT)
5119 ocs = OCS_SUCCESS;
5120 }
5121
7a3e97b0
SY		 5122 switch (ocs) {
5123 case OCS_SUCCESS:
5a0b0cb9 5124 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 5125 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 5126 switch (result) {
5127 case UPIU_TRANSACTION_RESPONSE:
5128 /*
5129 * get the response UPIU result to extract
5130 * the SCSI command status
5131 */
5132 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5133
5134 /*
5135 * get the result based on SCSI status response
5136 * to notify the SCSI midlayer of the command status
5137 */
5138 scsi_status = result & MASK_SCSI_STATUS;
5139 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 5140
f05ac2e5
YG		 5141 /*
5142 * Currently we are only supporting BKOPs exception
5143 * events hence we can ignore BKOPs exception event
5144 * during power management callbacks. BKOPs exception
5145 * event is not expected to be raised in runtime suspend
5146 * callback as it allows the urgent bkops.
5147 * During system suspend, we are anyway forcefully
5148 * disabling the bkops and if urgent bkops is needed
5149 * it will be enabled on system resume. Long term
5150 * solution could be to abort the system suspend if
5151 * UFS device needs urgent BKOPs.
5152 */
5153 if (!hba->pm_op_in_progress &&
aa53f580 5154 !ufshcd_eh_in_progress(hba) &&
b294ff3e
AD		 5155 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5156 /* Flushed in suspend */
5157 schedule_work(&hba->eeh_work);
4b5f4907
DP		 5158
5159 if (scsi_status == SAM_STAT_GOOD)
5160 ufshpb_rsp_upiu(hba, lrbp);
5a0b0cb9
SRT		 5161 break;
5162 case UPIU_TRANSACTION_REJECT_UPIU:
5163 /* TODO: handle Reject UPIU Response */
5164 result = DID_ERROR << 16;
3b1d0580 5165 dev_err(hba->dev,
5a0b0cb9
SRT		 5166 "Reject UPIU not fully implemented\n");
5167 break;
5168 default:
5a0b0cb9
SRT		 5169 dev_err(hba->dev,
5170 "Unexpected request response code = %x\n",
5171 result);
e0347d89 5172 result = DID_ERROR << 16;
7a3e97b0
SY		 5173 break;
5174 }
7a3e97b0
SY		 5175 break;
5176 case OCS_ABORTED:
5177 result |= DID_ABORT << 16;
5178 break;
e8e7f271
SRT		 5179 case OCS_INVALID_COMMAND_STATUS:
5180 result |= DID_REQUEUE << 16;
5181 break;
7a3e97b0
SY		 5182 case OCS_INVALID_CMD_TABLE_ATTR:
5183 case OCS_INVALID_PRDT_ATTR:
5184 case OCS_MISMATCH_DATA_BUF_SIZE:
5185 case OCS_MISMATCH_RESP_UPIU_SIZE:
5186 case OCS_PEER_COMM_FAILURE:
5187 case OCS_FATAL_ERROR:
5e7341e1
ST		 5188 case OCS_DEVICE_FATAL_ERROR:
5189 case OCS_INVALID_CRYPTO_CONFIG:
5190 case OCS_GENERAL_CRYPTO_ERROR:
7a3e97b0
SY		 5191 default:
5192 result |= DID_ERROR << 16;
3b1d0580 5193 dev_err(hba->dev,
ff8e20c6
DR		 5194 "OCS error from controller = %x for tag %d\n",
5195 ocs, lrbp->task_tag);
e965e5e0 5196 ufshcd_print_evt_hist(hba);
6ba65588 5197 ufshcd_print_host_state(hba);
7a3e97b0
SY		 5198 break;
5199 } /* end of switch */
5200
eeb1b55b
JK		 5201 if ((host_byte(result) != DID_OK) &&
5202 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
66cc820f 5203 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 5204 return result;
5205}
5206
a45f9371
CG		 5207static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5208 u32 intr_mask)
5209{
5210 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5211 !ufshcd_is_auto_hibern8_enabled(hba))
5212 return false;
5213
5214 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5215 return false;
5216
5217 if (hba->active_uic_cmd &&
5218 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5219 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5220 return false;
5221
5222 return true;
5223}
5224
6ccf44fe
SJ		 5225/**
5226 * ufshcd_uic_cmd_compl - handle completion of uic command
5227 * @hba: per adapter instance
53b3d9c3 5228 * @intr_status: interrupt status generated by the controller
9333d775
VG		 5229 *
5230 * Returns
5231 * IRQ_HANDLED - If interrupt is valid
5232 * IRQ_NONE - If invalid interrupt
6ccf44fe 5233 */
9333d775 5234static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 5235{
9333d775
VG		 5236 irqreturn_t retval = IRQ_NONE;
5237
a45f9371
CG		 5238 spin_lock(hba->host->host_lock);
5239 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5240 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5241
53b3d9c3 5242 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 5243 hba->active_uic_cmd->argument2 |=
5244 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 5245 hba->active_uic_cmd->argument3 =
5246 ufshcd_get_dme_attr_val(hba);
0f52fcb9
CG		 5247 if (!hba->uic_async_done)
5248 hba->active_uic_cmd->cmd_active = 0;
6ccf44fe 5249 complete(&hba->active_uic_cmd->done);
9333d775 5250 retval = IRQ_HANDLED;
6ccf44fe 5251 }
53b3d9c3 5252
9333d775 5253 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
0f52fcb9 5254 hba->active_uic_cmd->cmd_active = 0;
57d104c1 5255 complete(hba->uic_async_done);
9333d775
VG		 5256 retval = IRQ_HANDLED;
5257 }
aa5c6979
SC		 5258
5259 if (retval == IRQ_HANDLED)
5260 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
28fa68fc 5261 UFS_CMD_COMP);
a45f9371 5262 spin_unlock(hba->host->host_lock);
9333d775 5263 return retval;
6ccf44fe
SJ		 5264}
5265
7a3e97b0 5266/**
9a47ec7c 5267 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 5268 * @hba: per adapter instance
73dc3c4a
BVA		 5269 * @completed_reqs: bitmask that indicates which requests to complete
5270 * @retry_requests: whether to ask the SCSI core to retry completed requests
7a3e97b0 5271 */
9a47ec7c 5272static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
73dc3c4a
BVA		 5273 unsigned long completed_reqs,
5274 bool retry_requests)
7a3e97b0 5275{
5a0b0cb9
SRT		 5276 struct ufshcd_lrb *lrbp;
5277 struct scsi_cmnd *cmd;
7a3e97b0
SY		 5278 int result;
5279 int index;
7a7e66c6 5280 bool update_scaling = false;
e9d501b1 5281
e9d501b1
DR		 5282 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5283 lrbp = &hba->lrb[index];
a3170376 5284 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 5285 cmd = lrbp->cmd;
5286 if (cmd) {
1d8613a2
CG		 5287 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5288 ufshcd_update_monitor(hba, lrbp);
28fa68fc 5289 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
73dc3c4a
BVA		 5290 result = retry_requests ? DID_BUS_BUSY << 16 :
5291 ufshcd_transfer_rsp_status(hba, lrbp);
e9d501b1
DR		 5292 scsi_dma_unmap(cmd);
5293 cmd->result = result;
5294 /* Mark completed command as NULL in LRB */
5295 lrbp->cmd = NULL;
e9d501b1
DR		 5296 /* Do not touch lrbp after scsi done */
5297 cmd->scsi_done(cmd);
a45f9371 5298 ufshcd_release(hba);
7a7e66c6 5299 update_scaling = true;
300bb13f
JP		 5300 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5301 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 5302 if (hba->dev_cmd.complete) {
5303 ufshcd_add_command_trace(hba, index,
28fa68fc 5304 UFS_DEV_COMP);
e9d501b1 5305 complete(hba->dev_cmd.complete);
7a7e66c6 5306 update_scaling = true;
1a07f2d9 5307 }
e9d501b1 5308 }
a45f9371
CG		 5309 if (update_scaling)
5310 ufshcd_clk_scaling_update_busy(hba);
e9d501b1 5311 }
7a3e97b0
SY		 5312}
5313
9a47ec7c 5314/**
1f522c50 5315 * ufshcd_transfer_req_compl - handle SCSI and query command completion
9a47ec7c 5316 * @hba: per adapter instance
73dc3c4a 5317 * @retry_requests: whether or not to ask to retry requests
9333d775
VG		 5318 *
5319 * Returns
5320 * IRQ_HANDLED - If interrupt is valid
5321 * IRQ_NONE - If invalid interrupt
9a47ec7c 5322 */
73dc3c4a
BVA		 5323static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba,
5324 bool retry_requests)
9a47ec7c 5325{
1f522c50
BVA		 5326 unsigned long completed_reqs, flags;
5327 u32 tr_doorbell;
9a47ec7c
YG		 5328
5329 /* Resetting interrupt aggregation counters first and reading the
5330 * DOOR_BELL afterward allows us to handle all the completed requests.
5331 * In order to prevent other interrupts starvation the DB is read once
5332 * after reset. The down side of this solution is the possibility of
5333 * false interrupt if device completes another request after resetting
5334 * aggregation and before reading the DB.
5335 */
b638b5eb
AA		 5336 if (ufshcd_is_intr_aggr_allowed(hba) &&
5337 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 5338 ufshcd_reset_intr_aggr(hba);
5339
c11a1ae9
BVA		 5340 if (ufs_fail_completion())
5341 return IRQ_HANDLED;
5342
169f5eb2 5343 spin_lock_irqsave(&hba->outstanding_lock, flags);
1f522c50 5344 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
169f5eb2
BVA		 5345 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5346 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5347 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5348 hba->outstanding_reqs);
5349 hba->outstanding_reqs &= ~completed_reqs;
5350 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
9a47ec7c 5351
9333d775 5352 if (completed_reqs) {
73dc3c4a
BVA		 5353 __ufshcd_transfer_req_compl(hba, completed_reqs,
5354 retry_requests);
9333d775
VG		 5355 return IRQ_HANDLED;
5356 } else {
5357 return IRQ_NONE;
5358 }
9a47ec7c
YG		 5359}
5360
7deedfda 5361int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
cd469475
AH		 5362{
5363 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5364 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5365 &ee_ctrl_mask);
5366}
5367
7deedfda 5368int ufshcd_write_ee_control(struct ufs_hba *hba)
cd469475
AH		 5369{
5370 int err;
5371
5372 mutex_lock(&hba->ee_ctrl_mutex);
5373 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5374 mutex_unlock(&hba->ee_ctrl_mutex);
5375 if (err)
5376 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5377 __func__, err);
5378 return err;
5379}
5380
5381int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5382 u16 set, u16 clr)
5383{
5384 u16 new_mask, ee_ctrl_mask;
5385 int err = 0;
5386
5387 mutex_lock(&hba->ee_ctrl_mutex);
5388 new_mask = (*mask & ~clr) | set;
5389 ee_ctrl_mask = new_mask | *other_mask;
5390 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5391 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5392 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5393 if (!err) {
5394 hba->ee_ctrl_mask = ee_ctrl_mask;
5395 *mask = new_mask;
5396 }
5397 mutex_unlock(&hba->ee_ctrl_mutex);
5398 return err;
5399}
5400
66ec6d59
SRT		 5401/**
5402 * ufshcd_disable_ee - disable exception event
5403 * @hba: per-adapter instance
5404 * @mask: exception event to disable
5405 *
5406 * Disables exception event in the device so that the EVENT_ALERT
5407 * bit is not set.
5408 *
5409 * Returns zero on success, non-zero error value on failure.
5410 */
cd469475 5411static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5412{
cd469475 5413 return ufshcd_update_ee_drv_mask(hba, 0, mask);
66ec6d59
SRT		 5414}
5415
5416/**
5417 * ufshcd_enable_ee - enable exception event
5418 * @hba: per-adapter instance
5419 * @mask: exception event to enable
5420 *
5421 * Enable corresponding exception event in the device to allow
5422 * device to alert host in critical scenarios.
5423 *
5424 * Returns zero on success, non-zero error value on failure.
5425 */
cd469475 5426static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5427{
cd469475 5428 return ufshcd_update_ee_drv_mask(hba, mask, 0);
66ec6d59
SRT		 5429}
5430
5431/**
5432 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5433 * @hba: per-adapter instance
5434 *
5435 * Allow device to manage background operations on its own. Enabling
5436 * this might lead to inconsistent latencies during normal data transfers
5437 * as the device is allowed to manage its own way of handling background
5438 * operations.
5439 *
5440 * Returns zero on success, non-zero on failure.
5441 */
5442static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5443{
5444 int err = 0;
5445
5446 if (hba->auto_bkops_enabled)
5447 goto out;
5448
dc3c8d3a 5449 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 5450 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5451 if (err) {
5452 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5453 __func__, err);
5454 goto out;
5455 }
5456
5457 hba->auto_bkops_enabled = true;
7ff5ab47 5458 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5459
5460 /* No need of URGENT_BKOPS exception from the device */
5461 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5462 if (err)
5463 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5464 __func__, err);
5465out:
5466 return err;
5467}
5468
5469/**
5470 * ufshcd_disable_auto_bkops - block device in doing background operations
5471 * @hba: per-adapter instance
5472 *
5473 * Disabling background operations improves command response latency but
5474 * has drawback of device moving into critical state where the device is
5475 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5476 * host is idle so that BKOPS are managed effectively without any negative
5477 * impacts.
5478 *
5479 * Returns zero on success, non-zero on failure.
5480 */
5481static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5482{
5483 int err = 0;
5484
5485 if (!hba->auto_bkops_enabled)
5486 goto out;
5487
5488 /*
5489 * If host assisted BKOPs is to be enabled, make sure
5490 * urgent bkops exception is allowed.
5491 */
5492 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5493 if (err) {
5494 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5495 __func__, err);
5496 goto out;
5497 }
5498
dc3c8d3a 5499 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
1f34eedf 5500 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5501 if (err) {
5502 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5503 __func__, err);
5504 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5505 goto out;
5506 }
5507
5508 hba->auto_bkops_enabled = false;
7ff5ab47 5509 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5510 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5511out:
5512 return err;
5513}
5514
5515/**
4e768e76 5516 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5517 * @hba: per adapter instance
5518 *
5519 * After a device reset the device may toggle the BKOPS_EN flag
5520 * to default value. The s/w tracking variables should be updated
4e768e76 5521 * as well. This function would change the auto-bkops state based on
5522 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5523 */
4e768e76 5524static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5525{
4e768e76 5526 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5527 hba->auto_bkops_enabled = false;
5528 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5529 ufshcd_enable_auto_bkops(hba);
5530 } else {
5531 hba->auto_bkops_enabled = true;
5532 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5533 ufshcd_disable_auto_bkops(hba);
5534 }
7b6668d8 5535 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
24366c2a 5536 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5537}
5538
5539static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5540{
5e86ae44 5541 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5542 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5543}
5544
5545/**
57d104c1 5546 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5547 * @hba: per-adapter instance
57d104c1 5548 * @status: bkops_status value
66ec6d59 5549 *
57d104c1
SJ		 5550 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5551 * flag in the device to permit background operations if the device
5552 * bkops_status is greater than or equal to "status" argument passed to
5553 * this function, disable otherwise.
5554 *
5555 * Returns 0 for success, non-zero in case of failure.
5556 *
5557 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5558 * to know whether auto bkops is enabled or disabled after this function
5559 * returns control to it.
66ec6d59 5560 */
57d104c1
SJ		 5561static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5562 enum bkops_status status)
66ec6d59
SRT		 5563{
5564 int err;
57d104c1 5565 u32 curr_status = 0;
66ec6d59 5566
57d104c1 5567 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5568 if (err) {
5569 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5570 __func__, err);
5571 goto out;
57d104c1
SJ		 5572 } else if (curr_status > BKOPS_STATUS_MAX) {
5573 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5574 __func__, curr_status);
5575 err = -EINVAL;
5576 goto out;
66ec6d59
SRT		 5577 }
5578
57d104c1 5579 if (curr_status >= status)
66ec6d59 5580 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5581 else
5582 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5583out:
5584 return err;
5585}
5586
57d104c1
SJ		 5587/**
5588 * ufshcd_urgent_bkops - handle urgent bkops exception event
5589 * @hba: per-adapter instance
5590 *
5591 * Enable fBackgroundOpsEn flag in the device to permit background
5592 * operations.
5593 *
5594 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5595 * and negative error value for any other failure.
5596 */
5597static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5598{
afdfff59 5599 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5600}
5601
66ec6d59
SRT		 5602static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5603{
5e86ae44 5604 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5605 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5606}
5607
afdfff59
YG		 5608static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5609{
5610 int err;
5611 u32 curr_status = 0;
5612
5613 if (hba->is_urgent_bkops_lvl_checked)
5614 goto enable_auto_bkops;
5615
5616 err = ufshcd_get_bkops_status(hba, &curr_status);
5617 if (err) {
5618 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5619 __func__, err);
5620 goto out;
5621 }
5622
5623 /*
5624 * We are seeing that some devices are raising the urgent bkops
5625 * exception events even when BKOPS status doesn't indicate performace
5626 * impacted or critical. Handle these device by determining their urgent
5627 * bkops status at runtime.
5628 */
5629 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5630 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5631 __func__, curr_status);
5632 /* update the current status as the urgent bkops level */
5633 hba->urgent_bkops_lvl = curr_status;
5634 hba->is_urgent_bkops_lvl_checked = true;
5635 }
5636
5637enable_auto_bkops:
5638 err = ufshcd_enable_auto_bkops(hba);
5639out:
5640 if (err < 0)
5641 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5642 __func__, err);
5643}
5644
3b5f3c0d 5645static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
3d17b9b5 5646{
6f8d5a6a 5647 u8 index;
3b5f3c0d
YH		 5648 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5649 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5650
5651 index = ufshcd_wb_get_query_index(hba);
5652 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5653}
5654
5655int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5656{
5657 int ret;
3d17b9b5 5658
79e3520f 5659 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5660 return 0;
5661
4cd48995 5662 if (!(enable ^ hba->dev_info.wb_enabled))
3d17b9b5 5663 return 0;
3d17b9b5 5664
3b5f3c0d 5665 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
3d17b9b5 5666 if (ret) {
3b5f3c0d 5667 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
3d17b9b5
AD		 5668 __func__, enable ? "enable" : "disable", ret);
5669 return ret;
5670 }
5671
4cd48995 5672 hba->dev_info.wb_enabled = enable;
3b5f3c0d
YH		 5673 dev_info(hba->dev, "%s Write Booster %s\n",
5674 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5675
5676 return ret;
5677}
5678
3b5f3c0d 5679static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
3d17b9b5 5680{
3b5f3c0d 5681 int ret;
3d17b9b5 5682
3b5f3c0d
YH		 5683 ret = __ufshcd_wb_toggle(hba, set,
5684 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5685 if (ret) {
5686 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5687 __func__, set ? "enable" : "disable", ret);
5688 return;
5689 }
5690 dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5691 __func__, set ? "enabled" : "disabled");
3d17b9b5
AD		 5692}
5693
3b5f3c0d 5694static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
3d17b9b5
AD		 5695{
5696 int ret;
5697
d3ba622d
BH		 5698 if (!ufshcd_is_wb_allowed(hba) ||
5699 hba->dev_info.wb_buf_flush_enabled == enable)
3b5f3c0d 5700 return;
3d17b9b5 5701
3b5f3c0d 5702 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
3d17b9b5 5703 if (ret) {
d3ba622d
BH		 5704 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5705 enable ? "enable" : "disable", ret);
3b5f3c0d 5706 return;
3d17b9b5
AD		 5707 }
5708
d3ba622d
BH		 5709 hba->dev_info.wb_buf_flush_enabled = enable;
5710
3b5f3c0d
YH		 5711 dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5712 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5713}
5714
5715static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5716 u32 avail_buf)
5717{
5718 u32 cur_buf;
5719 int ret;
e31011ab 5720 u8 index;
3d17b9b5 5721
e31011ab 5722 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5723 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5724 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
e31011ab 5725 index, 0, &cur_buf);
3d17b9b5
AD		 5726 if (ret) {
5727 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5728 __func__, ret);
5729 return false;
5730 }
5731
5732 if (!cur_buf) {
5733 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5734 cur_buf);
5735 return false;
5736 }
d14734ae
SC		 5737 /* Let it continue to flush when available buffer exceeds threshold */
5738 if (avail_buf < hba->vps->wb_flush_threshold)
3d17b9b5
AD		 5739 return true;
5740
5741 return false;
5742}
5743
51dd905b 5744static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
3d17b9b5
AD		 5745{
5746 int ret;
5747 u32 avail_buf;
e31011ab 5748 u8 index;
3d17b9b5 5749
79e3520f 5750 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5751 return false;
5752 /*
5753 * The ufs device needs the vcc to be ON to flush.
5754 * With user-space reduction enabled, it's enough to enable flush
5755 * by checking only the available buffer. The threshold
5756 * defined here is > 90% full.
5757 * With user-space preserved enabled, the current-buffer
5758 * should be checked too because the wb buffer size can reduce
5759 * when disk tends to be full. This info is provided by current
5760 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5761 * keeping vcc on when current buffer is empty.
5762 */
e31011ab 5763 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5764 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5765 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
e31011ab 5766 index, 0, &avail_buf);
3d17b9b5
AD		 5767 if (ret) {
5768 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5769 __func__, ret);
5770 return false;
5771 }
5772
5773 if (!hba->dev_info.b_presrv_uspc_en) {
d14734ae 5774 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
3d17b9b5
AD		 5775 return true;
5776 return false;
5777 }
5778
5779 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5780}
5781
51dd905b
SC		 5782static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5783{
5784 struct ufs_hba *hba = container_of(to_delayed_work(work),
5785 struct ufs_hba,
5786 rpm_dev_flush_recheck_work);
5787 /*
5788 * To prevent unnecessary VCC power drain after device finishes
5789 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5790 * after a certain delay to recheck the threshold by next runtime
5791 * suspend.
5792 */
b294ff3e
AD		 5793 ufshcd_rpm_get_sync(hba);
5794 ufshcd_rpm_put_sync(hba);
51dd905b
SC		 5795}
5796
66ec6d59
SRT		 5797/**
5798 * ufshcd_exception_event_handler - handle exceptions raised by device
5799 * @work: pointer to work data
5800 *
5801 * Read bExceptionEventStatus attribute from the device and handle the
5802 * exception event accordingly.
5803 */
5804static void ufshcd_exception_event_handler(struct work_struct *work)
5805{
5806 struct ufs_hba *hba;
5807 int err;
5808 u32 status = 0;
5809 hba = container_of(work, struct ufs_hba, eeh_work);
5810
03e1d28e 5811 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5812 err = ufshcd_get_ee_status(hba, &status);
5813 if (err) {
5814 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5815 __func__, err);
5816 goto out;
5817 }
5818
f7733625
AH		 5819 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5820
cd469475 5821 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
afdfff59
YG		 5822 ufshcd_bkops_exception_event_handler(hba);
5823
7deedfda 5824 ufs_debugfs_exception_event(hba, status);
66ec6d59 5825out:
03e1d28e 5826 ufshcd_scsi_unblock_requests(hba);
66ec6d59
SRT		 5827 return;
5828}
5829
9a47ec7c
YG		 5830/* Complete requests that have door-bell cleared */
5831static void ufshcd_complete_requests(struct ufs_hba *hba)
5832{
73dc3c4a
BVA		 5833 ufshcd_transfer_req_compl(hba, /*retry_requests=*/false);
5834 ufshcd_tmc_handler(hba);
5835}
5836
5837static void ufshcd_retry_aborted_requests(struct ufs_hba *hba)
5838{
5839 ufshcd_transfer_req_compl(hba, /*retry_requests=*/true);
9a47ec7c
YG		 5840 ufshcd_tmc_handler(hba);
5841}
5842
583fa62d
YG		 5843/**
5844 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5845 * to recover from the DL NAC errors or not.
5846 * @hba: per-adapter instance
5847 *
5848 * Returns true if error handling is required, false otherwise
5849 */
5850static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5851{
5852 unsigned long flags;
5853 bool err_handling = true;
5854
5855 spin_lock_irqsave(hba->host->host_lock, flags);
5856 /*
5857 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5858 * device fatal error and/or DL NAC & REPLAY timeout errors.
5859 */
5860 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5861 goto out;
5862
5863 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5864 ((hba->saved_err & UIC_ERROR) &&
5865 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5866 goto out;
5867
5868 if ((hba->saved_err & UIC_ERROR) &&
5869 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5870 int err;
5871 /*
5872 * wait for 50ms to see if we can get any other errors or not.
5873 */
5874 spin_unlock_irqrestore(hba->host->host_lock, flags);
5875 msleep(50);
5876 spin_lock_irqsave(hba->host->host_lock, flags);
5877
5878 /*
5879 * now check if we have got any other severe errors other than
5880 * DL NAC error?
5881 */
5882 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5883 ((hba->saved_err & UIC_ERROR) &&
5884 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5885 goto out;
5886
5887 /*
5888 * As DL NAC is the only error received so far, send out NOP
5889 * command to confirm if link is still active or not.
5890 * - If we don't get any response then do error recovery.
5891 * - If we get response then clear the DL NAC error bit.
5892 */
5893
5894 spin_unlock_irqrestore(hba->host->host_lock, flags);
5895 err = ufshcd_verify_dev_init(hba);
5896 spin_lock_irqsave(hba->host->host_lock, flags);
5897
5898 if (err)
5899 goto out;
5900
5901 /* Link seems to be alive hence ignore the DL NAC errors */
5902 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5903 hba->saved_err &= ~UIC_ERROR;
5904 /* clear NAC error */
5905 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
b0008625 5906 if (!hba->saved_uic_err)
583fa62d 5907 err_handling = false;
583fa62d
YG		 5908 }
5909out:
5910 spin_unlock_irqrestore(hba->host->host_lock, flags);
5911 return err_handling;
5912}
5913
348e1bc5
SC		 5914static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
5915{
5916 down_write(&hba->clk_scaling_lock);
5917 hba->clk_scaling.is_allowed = allow;
5918 up_write(&hba->clk_scaling_lock);
5919}
5920
5921static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
5922{
5923 if (suspend) {
5924 if (hba->clk_scaling.is_enabled)
5925 ufshcd_suspend_clkscaling(hba);
5926 ufshcd_clk_scaling_allow(hba, false);
5927 } else {
5928 ufshcd_clk_scaling_allow(hba, true);
5929 if (hba->clk_scaling.is_enabled)
5930 ufshcd_resume_clkscaling(hba);
5931 }
5932}
5933
c72e79c0
CG		 5934static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5935{
b294ff3e
AD		 5936 ufshcd_rpm_get_sync(hba);
5937 if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
5938 hba->is_sys_suspended) {
88a92d6a
CG		 5939 enum ufs_pm_op pm_op;
5940
c72e79c0 5941 /*
b294ff3e 5942 * Don't assume anything of resume, if
c72e79c0
CG		 5943 * resume fails, irq and clocks can be OFF, and powers
5944 * can be OFF or in LPM.
5945 */
5946 ufshcd_setup_hba_vreg(hba, true);
5947 ufshcd_enable_irq(hba);
5948 ufshcd_setup_vreg(hba, true);
5949 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5950 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5951 ufshcd_hold(hba, false);
5952 if (!ufshcd_is_clkgating_allowed(hba))
5953 ufshcd_setup_clocks(hba, true);
5954 ufshcd_release(hba);
88a92d6a
CG		 5955 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
5956 ufshcd_vops_resume(hba, pm_op);
c72e79c0
CG		 5957 } else {
5958 ufshcd_hold(hba, false);
348e1bc5
SC		 5959 if (ufshcd_is_clkscaling_supported(hba) &&
5960 hba->clk_scaling.is_enabled)
c72e79c0 5961 ufshcd_suspend_clkscaling(hba);
348e1bc5 5962 ufshcd_clk_scaling_allow(hba, false);
c72e79c0 5963 }
aa53f580
CG		 5964 ufshcd_scsi_block_requests(hba);
5965 /* Drain ufshcd_queuecommand() */
5966 down_write(&hba->clk_scaling_lock);
5967 up_write(&hba->clk_scaling_lock);
5968 cancel_work_sync(&hba->eeh_work);
c72e79c0
CG		 5969}
5970
5971static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5972{
aa53f580 5973 ufshcd_scsi_unblock_requests(hba);
c72e79c0 5974 ufshcd_release(hba);
348e1bc5
SC		 5975 if (ufshcd_is_clkscaling_supported(hba))
5976 ufshcd_clk_scaling_suspend(hba, false);
aa53f580 5977 ufshcd_clear_ua_wluns(hba);
b294ff3e 5978 ufshcd_rpm_put(hba);
c72e79c0
CG		 5979}
5980
5981static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5982{
9cd20d3f 5983 return (!hba->is_powered || hba->shutting_down ||
b294ff3e 5984 !hba->sdev_ufs_device ||
9cd20d3f 5985 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
c72e79c0 5986 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
9cd20d3f 5987 ufshcd_is_link_broken(hba))));
c72e79c0
CG		 5988}
5989
5990#ifdef CONFIG_PM
5991static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5992{
5993 struct Scsi_Host *shost = hba->host;
5994 struct scsi_device *sdev;
5995 struct request_queue *q;
5996 int ret;
5997
88a92d6a 5998 hba->is_sys_suspended = false;
c72e79c0 5999 /*
b294ff3e 6000 * Set RPM status of wlun device to RPM_ACTIVE,
c72e79c0
CG		 6001 * this also clears its runtime error.
6002 */
b294ff3e
AD		 6003 ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
6004
6005 /* hba device might have a runtime error otherwise */
6006 if (ret)
6007 ret = pm_runtime_set_active(hba->dev);
c72e79c0 6008 /*
b294ff3e
AD		 6009 * If wlun device had runtime error, we also need to resume those
6010 * consumer scsi devices in case any of them has failed to be
6011 * resumed due to supplier runtime resume failure. This is to unblock
c72e79c0
CG		 6012 * blk_queue_enter in case there are bios waiting inside it.
6013 */
6014 if (!ret) {
6015 shost_for_each_device(sdev, shost) {
6016 q = sdev->request_queue;
6017 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6018 q->rpm_status == RPM_SUSPENDING))
6019 pm_request_resume(q->dev);
6020 }
6021 }
6022}
6023#else
6024static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6025{
6026}
6027#endif
6028
2355b66e
CG		 6029static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6030{
6031 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6032 u32 mode;
6033
6034 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6035
6036 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6037 return true;
6038
6039 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6040 return true;
6041
6042 return false;
6043}
6044
7a3e97b0 6045/**
e8e7f271 6046 * ufshcd_err_handler - handle UFS errors that require s/w attention
a113eaaf 6047 * @host: SCSI host pointer
7a3e97b0 6048 */
a113eaaf 6049static void ufshcd_err_handler(struct Scsi_Host *host)
7a3e97b0 6050{
a113eaaf 6051 struct ufs_hba *hba = shost_priv(host);
e8e7f271 6052 unsigned long flags;
307348f6
CG		 6053 bool err_xfer = false;
6054 bool err_tm = false;
2355b66e 6055 int err = 0, pmc_err;
e8e7f271 6056 int tag;
2355b66e 6057 bool needs_reset = false, needs_restore = false;
e8e7f271 6058
9cd20d3f 6059 down(&hba->host_sem);
e8e7f271 6060 spin_lock_irqsave(hba->host->host_lock, flags);
a113eaaf 6061 hba->host->host_eh_scheduled = 0;
c72e79c0 6062 if (ufshcd_err_handling_should_stop(hba)) {
4db7a236
CG		 6063 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6064 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6065 spin_unlock_irqrestore(hba->host->host_lock, flags);
9cd20d3f 6066 up(&hba->host_sem);
4db7a236
CG		 6067 return;
6068 }
6069 ufshcd_set_eh_in_progress(hba);
6070 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6071 ufshcd_err_handling_prepare(hba);
a45f9371
CG		 6072 /* Complete requests that have door-bell cleared by h/w */
6073 ufshcd_complete_requests(hba);
e8e7f271 6074 spin_lock_irqsave(hba->host->host_lock, flags);
aa53f580
CG		 6075 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6076 hba->ufshcd_state = UFSHCD_STATE_RESET;
88a92d6a
CG		 6077 /*
6078 * A full reset and restore might have happened after preparation
6079 * is finished, double check whether we should stop.
6080 */
6081 if (ufshcd_err_handling_should_stop(hba))
6082 goto skip_err_handling;
6083
583fa62d
YG		 6084 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6085 bool ret;
6086
6087 spin_unlock_irqrestore(hba->host->host_lock, flags);
6088 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6089 ret = ufshcd_quirk_dl_nac_errors(hba);
6090 spin_lock_irqsave(hba->host->host_lock, flags);
88a92d6a 6091 if (!ret && ufshcd_err_handling_should_stop(hba))
583fa62d
YG		 6092 goto skip_err_handling;
6093 }
4db7a236 6094
2355b66e
CG		 6095 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6096 (hba->saved_uic_err &&
6097 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
c3be8d1e
CG		 6098 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6099
6100 spin_unlock_irqrestore(hba->host->host_lock, flags);
6101 ufshcd_print_host_state(hba);
6102 ufshcd_print_pwr_info(hba);
e965e5e0 6103 ufshcd_print_evt_hist(hba);
c3be8d1e
CG		 6104 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6105 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6106 spin_lock_irqsave(hba->host->host_lock, flags);
6107 }
6108
9a47ec7c
YG		 6109 /*
6110 * if host reset is required then skip clearing the pending
2df74b69
CG		 6111 * transfers forcefully because they will get cleared during
6112 * host reset and restore
9a47ec7c 6113 */
88a92d6a
CG		 6114 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6115 ufshcd_is_saved_err_fatal(hba) ||
6116 ((hba->saved_err & UIC_ERROR) &&
6117 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6118 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6119 needs_reset = true;
2355b66e 6120 goto do_reset;
88a92d6a 6121 }
9a47ec7c 6122
2355b66e
CG		 6123 /*
6124 * If LINERESET was caught, UFS might have been put to PWM mode,
6125 * check if power mode restore is needed.
6126 */
6127 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6128 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6129 if (!hba->saved_uic_err)
6130 hba->saved_err &= ~UIC_ERROR;
6131 spin_unlock_irqrestore(hba->host->host_lock, flags);
6132 if (ufshcd_is_pwr_mode_restore_needed(hba))
6133 needs_restore = true;
6134 spin_lock_irqsave(hba->host->host_lock, flags);
6135 if (!hba->saved_err && !needs_restore)
6136 goto skip_err_handling;
6137 }
9a47ec7c 6138
2355b66e 6139 hba->silence_err_logs = true;
9a47ec7c
YG		 6140 /* release lock as clear command might sleep */
6141 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6142 /* Clear pending transfer requests */
9a47ec7c 6143 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
307348f6 6144 if (ufshcd_try_to_abort_task(hba, tag)) {
9a47ec7c
YG		 6145 err_xfer = true;
6146 goto lock_skip_pending_xfer_clear;
6147 }
6148 }
e8e7f271
SRT		 6149
6150 /* Clear pending task management requests */
9a47ec7c
YG		 6151 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6152 if (ufshcd_clear_tm_cmd(hba, tag)) {
6153 err_tm = true;
6154 goto lock_skip_pending_xfer_clear;
6155 }
6156 }
e8e7f271 6157
9a47ec7c 6158lock_skip_pending_xfer_clear:
73dc3c4a 6159 ufshcd_retry_aborted_requests(hba);
9a47ec7c 6160
a45f9371
CG		 6161 spin_lock_irqsave(hba->host->host_lock, flags);
6162 hba->silence_err_logs = false;
2355b66e 6163 if (err_xfer || err_tm) {
9a47ec7c 6164 needs_reset = true;
2355b66e
CG		 6165 goto do_reset;
6166 }
9a47ec7c 6167
2355b66e
CG		 6168 /*
6169 * After all reqs and tasks are cleared from doorbell,
6170 * now it is safe to retore power mode.
6171 */
6172 if (needs_restore) {
6173 spin_unlock_irqrestore(hba->host->host_lock, flags);
6174 /*
6175 * Hold the scaling lock just in case dev cmds
6176 * are sent via bsg and/or sysfs.
6177 */
6178 down_write(&hba->clk_scaling_lock);
6179 hba->force_pmc = true;
6180 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6181 if (pmc_err) {
6182 needs_reset = true;
6183 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6184 __func__, pmc_err);
6185 }
6186 hba->force_pmc = false;
6187 ufshcd_print_pwr_info(hba);
6188 up_write(&hba->clk_scaling_lock);
6189 spin_lock_irqsave(hba->host->host_lock, flags);
6190 }
9a47ec7c 6191
2355b66e 6192do_reset:
e8e7f271 6193 /* Fatal errors need reset */
9a47ec7c 6194 if (needs_reset) {
4db7a236 6195 hba->force_reset = false;
9a47ec7c 6196 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6197 err = ufshcd_reset_and_restore(hba);
4db7a236
CG		 6198 if (err)
6199 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6200 __func__, err);
c72e79c0
CG		 6201 else
6202 ufshcd_recover_pm_error(hba);
9a47ec7c 6203 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6204 }
9a47ec7c 6205
583fa62d 6206skip_err_handling:
9a47ec7c 6207 if (!needs_reset) {
4db7a236
CG		 6208 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6209 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
9a47ec7c
YG		 6210 if (hba->saved_err || hba->saved_uic_err)
6211 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6212 __func__, hba->saved_err, hba->saved_uic_err);
6213 }
e8e7f271 6214 ufshcd_clear_eh_in_progress(hba);
9a47ec7c 6215 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6216 ufshcd_err_handling_unprepare(hba);
9cd20d3f 6217 up(&hba->host_sem);
7a3e97b0
SY		 6218}
6219
6220/**
e8e7f271
SRT		 6221 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6222 * @hba: per-adapter instance
9333d775
VG		 6223 *
6224 * Returns
6225 * IRQ_HANDLED - If interrupt is valid
6226 * IRQ_NONE - If invalid interrupt
7a3e97b0 6227 */
9333d775 6228static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 6229{
6230 u32 reg;
9333d775 6231 irqreturn_t retval = IRQ_NONE;
7a3e97b0 6232
2355b66e 6233 /* PHY layer error */
fb7b45f0 6234 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
fb7b45f0 6235 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
2355b66e 6236 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6237 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
fb7b45f0
DR		 6238 /*
6239 * To know whether this error is fatal or not, DB timeout
6240 * must be checked but this error is handled separately.
6241 */
2355b66e
CG		 6242 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6243 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6244 __func__);
6245
6246 /* Got a LINERESET indication. */
6247 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6248 struct uic_command *cmd = NULL;
6249
6250 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6251 if (hba->uic_async_done && hba->active_uic_cmd)
6252 cmd = hba->active_uic_cmd;
6253 /*
6254 * Ignore the LINERESET during power mode change
6255 * operation via DME_SET command.
6256 */
6257 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6258 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6259 }
9333d775 6260 retval |= IRQ_HANDLED;
ff8e20c6 6261 }
fb7b45f0 6262
e8e7f271
SRT		 6263 /* PA_INIT_ERROR is fatal and needs UIC reset */
6264 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 6265 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6266 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6267 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
ff8e20c6 6268
9333d775
VG		 6269 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6270 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6271 else if (hba->dev_quirks &
6272 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6273 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6274 hba->uic_error |=
6275 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6276 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6277 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6278 }
6279 retval |= IRQ_HANDLED;
583fa62d 6280 }
e8e7f271
SRT		 6281
6282 /* UIC NL/TL/DME errors needs software retry */
6283 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 6284 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6285 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6286 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
e8e7f271 6287 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 6288 retval |= IRQ_HANDLED;
ff8e20c6 6289 }
e8e7f271
SRT		 6290
6291 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 6292 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6293 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6294 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
e8e7f271 6295 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 6296 retval |= IRQ_HANDLED;
ff8e20c6 6297 }
e8e7f271
SRT		 6298
6299 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 6300 if ((reg & UIC_DME_ERROR) &&
6301 (reg & UIC_DME_ERROR_CODE_MASK)) {
e965e5e0 6302 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
e8e7f271 6303 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 6304 retval |= IRQ_HANDLED;
ff8e20c6 6305 }
e8e7f271
SRT		 6306
6307 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6308 __func__, hba->uic_error);
9333d775 6309 return retval;
e8e7f271
SRT		 6310}
6311
6312/**
6313 * ufshcd_check_errors - Check for errors that need s/w attention
6314 * @hba: per-adapter instance
a45f9371 6315 * @intr_status: interrupt status generated by the controller
9333d775
VG		 6316 *
6317 * Returns
6318 * IRQ_HANDLED - If interrupt is valid
6319 * IRQ_NONE - If invalid interrupt
e8e7f271 6320 */
a45f9371 6321static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
e8e7f271
SRT		 6322{
6323 bool queue_eh_work = false;
9333d775 6324 irqreturn_t retval = IRQ_NONE;
e8e7f271 6325
a45f9371
CG		 6326 spin_lock(hba->host->host_lock);
6327 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6328
d3c615bf 6329 if (hba->errors & INT_FATAL_ERRORS) {
e965e5e0
SC		 6330 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6331 hba->errors);
e8e7f271 6332 queue_eh_work = true;
d3c615bf 6333 }
7a3e97b0
SY		 6334
6335 if (hba->errors & UIC_ERROR) {
e8e7f271 6336 hba->uic_error = 0;
9333d775 6337 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 6338 if (hba->uic_error)
6339 queue_eh_work = true;
7a3e97b0 6340 }
e8e7f271 6341
82174440
SC		 6342 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6343 dev_err(hba->dev,
6344 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6345 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6346 "Enter" : "Exit",
6347 hba->errors, ufshcd_get_upmcrs(hba));
e965e5e0 6348 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
d3c615bf 6349 hba->errors);
4db7a236 6350 ufshcd_set_link_broken(hba);
82174440
SC		 6351 queue_eh_work = true;
6352 }
6353
e8e7f271 6354 if (queue_eh_work) {
9a47ec7c
YG		 6355 /*
6356 * update the transfer error masks to sticky bits, let's do this
6357 * irrespective of current ufshcd_state.
6358 */
6359 hba->saved_err |= hba->errors;
6360 hba->saved_uic_err |= hba->uic_error;
6361
4db7a236 6362 /* dump controller state before resetting */
ace3804b
CG		 6363 if ((hba->saved_err &
6364 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
2355b66e
CG		 6365 (hba->saved_uic_err &&
6366 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
4db7a236 6367 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
66cc820f
DR		 6368 __func__, hba->saved_err,
6369 hba->saved_uic_err);
c3be8d1e
CG		 6370 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6371 "host_regs: ");
4db7a236 6372 ufshcd_print_pwr_info(hba);
e8e7f271 6373 }
9333d775 6374 retval |= IRQ_HANDLED;
3441da7d 6375 }
e8e7f271
SRT		 6376 /*
6377 * if (!queue_eh_work) -
6378 * Other errors are either non-fatal where host recovers
6379 * itself without s/w intervention or errors that will be
6380 * handled by the SCSI core layer.
6381 */
a45f9371
CG		 6382 hba->errors = 0;
6383 hba->uic_error = 0;
6384 spin_unlock(hba->host->host_lock);
a113eaaf
BVA		 6385
6386 if (queue_eh_work)
6387 ufshcd_schedule_eh(hba);
6388
9333d775 6389 return retval;
7a3e97b0
SY		 6390}
6391
69a6c269
BVA		 6392struct ctm_info {
6393 struct ufs_hba *hba;
6394 unsigned long pending;
6395 unsigned int ncpl;
6396};
6397
6398static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
6399{
6400 struct ctm_info *const ci = priv;
6401 struct completion *c;
6402
6403 WARN_ON_ONCE(reserved);
6404 if (test_bit(req->tag, &ci->pending))
6405 return true;
6406 ci->ncpl++;
6407 c = req->end_io_data;
6408 if (c)
6409 complete(c);
6410 return true;
6411}
6412
7a3e97b0
SY		 6413/**
6414 * ufshcd_tmc_handler - handle task management function completion
6415 * @hba: per adapter instance
9333d775
VG		 6416 *
6417 * Returns
6418 * IRQ_HANDLED - If interrupt is valid
6419 * IRQ_NONE - If invalid interrupt
7a3e97b0 6420 */
9333d775 6421static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 6422{
a45f9371 6423 unsigned long flags;
69a6c269
BVA		 6424 struct request_queue *q = hba->tmf_queue;
6425 struct ctm_info ci = {
6426 .hba = hba,
69a6c269 6427 };
7a3e97b0 6428
a45f9371
CG		 6429 spin_lock_irqsave(hba->host->host_lock, flags);
6430 ci.pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
69a6c269 6431 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
a45f9371
CG		 6432 spin_unlock_irqrestore(hba->host->host_lock, flags);
6433
69a6c269 6434 return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
7a3e97b0
SY		 6435}
6436
6437/**
6438 * ufshcd_sl_intr - Interrupt service routine
6439 * @hba: per adapter instance
6440 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 6441 *
6442 * Returns
6443 * IRQ_HANDLED - If interrupt is valid
6444 * IRQ_NONE - If invalid interrupt
7a3e97b0 6445 */
9333d775 6446static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 6447{
9333d775
VG		 6448 irqreturn_t retval = IRQ_NONE;
6449
53b3d9c3 6450 if (intr_status & UFSHCD_UIC_MASK)
9333d775 6451 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0 6452
a45f9371
CG		 6453 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6454 retval |= ufshcd_check_errors(hba, intr_status);
6455
7a3e97b0 6456 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 6457 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 6458
6459 if (intr_status & UTP_TRANSFER_REQ_COMPL)
73dc3c4a 6460 retval |= ufshcd_transfer_req_compl(hba, /*retry_requests=*/false);
9333d775
VG		 6461
6462 return retval;
7a3e97b0
SY		 6463}
6464
6465/**
6466 * ufshcd_intr - Main interrupt service routine
6467 * @irq: irq number
6468 * @__hba: pointer to adapter instance
6469 *
9333d775
VG		 6470 * Returns
6471 * IRQ_HANDLED - If interrupt is valid
6472 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 6473 */
6474static irqreturn_t ufshcd_intr(int irq, void *__hba)
6475{
127d5f7c 6476 u32 intr_status, enabled_intr_status = 0;
7a3e97b0
SY		 6477 irqreturn_t retval = IRQ_NONE;
6478 struct ufs_hba *hba = __hba;
7f6ba4f1 6479 int retries = hba->nutrs;
7a3e97b0 6480
b873a275 6481 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
3f8af604
CG		 6482 hba->ufs_stats.last_intr_status = intr_status;
6483 hba->ufs_stats.last_intr_ts = ktime_get();
7a3e97b0 6484
7f6ba4f1
VG		 6485 /*
6486 * There could be max of hba->nutrs reqs in flight and in worst case
6487 * if the reqs get finished 1 by 1 after the interrupt status is
6488 * read, make sure we handle them by checking the interrupt status
6489 * again in a loop until we process all of the reqs before returning.
6490 */
127d5f7c 6491 while (intr_status && retries--) {
7f6ba4f1
VG		 6492 enabled_intr_status =
6493 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
60ec3755 6494 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 6495 if (enabled_intr_status)
6496 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 6497
6498 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
127d5f7c 6499 }
d75f7fe4 6500
eeb1b55b 6501 if (enabled_intr_status && retval == IRQ_NONE &&
40d2fd05
BVA		 6502 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6503 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
eeb1b55b
JK		 6504 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6505 __func__,
6506 intr_status,
6507 hba->ufs_stats.last_intr_status,
6508 enabled_intr_status);
9333d775
VG		 6509 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6510 }
6511
7a3e97b0
SY		 6512 return retval;
6513}
6514
e2933132
SRT		 6515static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6516{
6517 int err = 0;
6518 u32 mask = 1 << tag;
6519 unsigned long flags;
6520
6521 if (!test_bit(tag, &hba->outstanding_tasks))
6522 goto out;
6523
6524 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 6525 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 6526 spin_unlock_irqrestore(hba->host->host_lock, flags);
6527
6528 /* poll for max. 1 sec to clear door bell register by h/w */
6529 err = ufshcd_wait_for_register(hba,
6530 REG_UTP_TASK_REQ_DOOR_BELL,
5cac1095 6531 mask, 0, 1000, 1000);
e2933132
SRT		 6532out:
6533 return err;
6534}
6535
c6049cd9
CH		 6536static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6537 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 6538{
69a6c269 6539 struct request_queue *q = hba->tmf_queue;
c6049cd9 6540 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 6541 DECLARE_COMPLETION_ONSTACK(wait);
6542 struct request *req;
7a3e97b0 6543 unsigned long flags;
4b42d557 6544 int task_tag, err;
7a3e97b0 6545
e2933132 6546 /*
4b42d557 6547 * blk_get_request() is used here only to get a free tag.
e2933132 6548 */
eeb1b55b
JK		 6549 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6550 if (IS_ERR(req))
6551 return PTR_ERR(req);
6552
69a6c269 6553 req->end_io_data = &wait;
1ab27c9c 6554 ufshcd_hold(hba, false);
7a3e97b0 6555
e2933132 6556 spin_lock_irqsave(host->host_lock, flags);
1235fc56 6557 blk_mq_start_request(req);
7a3e97b0 6558
4b42d557 6559 task_tag = req->tag;
1352eec8 6560 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
c6049cd9 6561
4b42d557
CG		 6562 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6563 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
d2877be4 6564
7a3e97b0 6565 /* send command to the controller */
4b42d557 6566 __set_bit(task_tag, &hba->outstanding_tasks);
897efe62 6567
4b42d557 6568 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 6569 /* Make sure that doorbell is committed immediately */
6570 wmb();
7a3e97b0
SY		 6571
6572 spin_unlock_irqrestore(host->host_lock, flags);
6573
28fa68fc 6574 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6667e6d9 6575
7a3e97b0 6576 /* wait until the task management command is completed */
69a6c269 6577 err = wait_for_completion_io_timeout(&wait,
e2933132 6578 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 6579 if (!err) {
69a6c269
BVA		 6580 /*
6581 * Make sure that ufshcd_compl_tm() does not trigger a
6582 * use-after-free.
6583 */
6584 req->end_io_data = NULL;
28fa68fc 6585 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
e2933132
SRT		 6586 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6587 __func__, tm_function);
4b42d557
CG		 6588 if (ufshcd_clear_tm_cmd(hba, task_tag))
6589 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6590 __func__, task_tag);
e2933132
SRT		 6591 err = -ETIMEDOUT;
6592 } else {
c6049cd9 6593 err = 0;
4b42d557 6594 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
c6049cd9 6595
28fa68fc 6596 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7a3e97b0 6597 }
e2933132 6598
b557217c 6599 spin_lock_irqsave(hba->host->host_lock, flags);
4b42d557 6600 __clear_bit(task_tag, &hba->outstanding_tasks);
b557217c
SC		 6601 spin_unlock_irqrestore(hba->host->host_lock, flags);
6602
4b42d557 6603 ufshcd_release(hba);
69a6c269 6604 blk_put_request(req);
e2933132 6605
7a3e97b0
SY		 6606 return err;
6607}
6608
c6049cd9
CH		 6609/**
6610 * ufshcd_issue_tm_cmd - issues task management commands to controller
6611 * @hba: per adapter instance
6612 * @lun_id: LUN ID to which TM command is sent
6613 * @task_id: task ID to which the TM command is applicable
6614 * @tm_function: task management function opcode
6615 * @tm_response: task management service response return value
6616 *
6617 * Returns non-zero value on error, zero on success.
6618 */
6619static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6620 u8 tm_function, u8 *tm_response)
6621{
6622 struct utp_task_req_desc treq = { { 0 }, };
6623 int ocs_value, err;
6624
6625 /* Configure task request descriptor */
6626 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6627 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6628
6629 /* Configure task request UPIU */
1352eec8 6630 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
c6049cd9 6631 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
1352eec8 6632 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
c6049cd9
CH		 6633
6634 /*
6635 * The host shall provide the same value for LUN field in the basic
6636 * header and for Input Parameter.
6637 */
1352eec8
GS		 6638 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6639 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
c6049cd9
CH		 6640
6641 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6642 if (err == -ETIMEDOUT)
6643 return err;
6644
6645 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6646 if (ocs_value != OCS_SUCCESS)
6647 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6648 __func__, ocs_value);
6649 else if (tm_response)
1352eec8 6650 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
c6049cd9
CH		 6651 MASK_TM_SERVICE_RESP;
6652 return err;
6653}
6654
5e0a86ee
AA		 6655/**
6656 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6657 * @hba: per-adapter instance
6658 * @req_upiu: upiu request
6659 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6660 * @desc_buff: pointer to descriptor buffer, NULL if NA
6661 * @buff_len: descriptor size, 0 if NA
d0e9760d 6662 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6663 * @desc_op: descriptor operation
6664 *
6665 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6666 * Therefore, it "rides" the device management infrastructure: uses its tag and
6667 * tasks work queues.
6668 *
6669 * Since there is only one available tag for device management commands,
6670 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6671 */
6672static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6673 struct utp_upiu_req *req_upiu,
6674 struct utp_upiu_req *rsp_upiu,
6675 u8 *desc_buff, int *buff_len,
7f674c38 6676 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6677 enum query_opcode desc_op)
6678{
7252a360 6679 struct request_queue *q = hba->cmd_queue;
8a686f26 6680 DECLARE_COMPLETION_ONSTACK(wait);
7252a360 6681 struct request *req;
5e0a86ee
AA		 6682 struct ufshcd_lrb *lrbp;
6683 int err = 0;
6684 int tag;
a23064c4 6685 u8 upiu_flags;
5e0a86ee
AA		 6686
6687 down_read(&hba->clk_scaling_lock);
6688
7252a360 6689 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 6690 if (IS_ERR(req)) {
6691 err = PTR_ERR(req);
6692 goto out_unlock;
6693 }
7252a360 6694 tag = req->tag;
4728ab4a 6695 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
5e0a86ee 6696
a45f9371 6697 if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
7a7e66c6
CG		 6698 err = -EBUSY;
6699 goto out;
6700 }
5e0a86ee 6701
a45f9371 6702 lrbp = &hba->lrb[tag];
7a7e66c6 6703 WARN_ON(lrbp->cmd);
5e0a86ee
AA		 6704 lrbp->cmd = NULL;
6705 lrbp->sense_bufflen = 0;
6706 lrbp->sense_buffer = NULL;
6707 lrbp->task_tag = tag;
6708 lrbp->lun = 0;
6709 lrbp->intr_cmd = true;
df043c74 6710 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5e0a86ee
AA		 6711 hba->dev_cmd.type = cmd_type;
6712
51428818 6713 if (hba->ufs_version <= ufshci_version(1, 1))
5e0a86ee 6714 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
51428818 6715 else
5e0a86ee 6716 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5e0a86ee
AA		 6717
6718 /* update the task tag in the request upiu */
6719 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6720
6721 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6722
6723 /* just copy the upiu request as it is */
6724 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6725 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6726 /* The Data Segment Area is optional depending upon the query
6727 * function value. for WRITE DESCRIPTOR, the data segment
6728 * follows right after the tsf.
6729 */
6730 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6731 *buff_len = 0;
6732 }
6733
6734 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6735
6736 hba->dev_cmd.complete = &wait;
6737
10542489 6738 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5e0a86ee 6739
a45f9371 6740 ufshcd_send_command(hba, tag);
5e0a86ee
AA		 6741 /*
6742 * ignore the returning value here - ufshcd_check_query_response is
6743 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6744 * read the response directly ignoring all errors.
6745 */
6746 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6747
6748 /* just copy the upiu response as it is */
6749 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6750 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6751 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6752 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6753 MASK_QUERY_DATA_SEG_LEN;
6754
6755 if (*buff_len >= resp_len) {
6756 memcpy(desc_buff, descp, resp_len);
6757 *buff_len = resp_len;
6758 } else {
3d4881d1
BH		 6759 dev_warn(hba->dev,
6760 "%s: rsp size %d is bigger than buffer size %d",
6761 __func__, resp_len, *buff_len);
4bbbe242
AA		 6762 *buff_len = 0;
6763 err = -EINVAL;
6764 }
6765 }
10542489
BH		 6766 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6767 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
5e0a86ee 6768
7a7e66c6 6769out:
7252a360 6770 blk_put_request(req);
bb14dd15 6771out_unlock:
5e0a86ee
AA		 6772 up_read(&hba->clk_scaling_lock);
6773 return err;
6774}
6775
6776/**
6777 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6778 * @hba: per-adapter instance
6779 * @req_upiu: upiu request
6780 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6781 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6782 * @desc_buff: pointer to descriptor buffer, NULL if NA
6783 * @buff_len: descriptor size, 0 if NA
6784 * @desc_op: descriptor operation
6785 *
6786 * Supports UTP Transfer requests (nop and query), and UTP Task
6787 * Management requests.
6788 * It is up to the caller to fill the upiu conent properly, as it will
6789 * be copied without any further input validations.
6790 */
6791int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6792 struct utp_upiu_req *req_upiu,
6793 struct utp_upiu_req *rsp_upiu,
6794 int msgcode,
6795 u8 *desc_buff, int *buff_len,
6796 enum query_opcode desc_op)
6797{
6798 int err;
7f674c38 6799 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee
AA		 6800 struct utp_task_req_desc treq = { { 0 }, };
6801 int ocs_value;
6802 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6803
5e0a86ee
AA		 6804 switch (msgcode) {
6805 case UPIU_TRANSACTION_NOP_OUT:
6806 cmd_type = DEV_CMD_TYPE_NOP;
df561f66 6807 fallthrough;
5e0a86ee
AA		 6808 case UPIU_TRANSACTION_QUERY_REQ:
6809 ufshcd_hold(hba, false);
6810 mutex_lock(&hba->dev_cmd.lock);
6811 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6812 desc_buff, buff_len,
6813 cmd_type, desc_op);
6814 mutex_unlock(&hba->dev_cmd.lock);
6815 ufshcd_release(hba);
6816
6817 break;
6818 case UPIU_TRANSACTION_TASK_REQ:
6819 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6820 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6821
1352eec8 6822 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
5e0a86ee
AA		 6823
6824 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6825 if (err == -ETIMEDOUT)
6826 break;
6827
6828 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6829 if (ocs_value != OCS_SUCCESS) {
6830 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6831 ocs_value);
6832 break;
6833 }
6834
1352eec8 6835 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
5e0a86ee
AA		 6836
6837 break;
6838 default:
6839 err = -EINVAL;
6840
6841 break;
6842 }
6843
5e0a86ee
AA		 6844 return err;
6845}
6846
7a3e97b0 6847/**
3441da7d
SRT		 6848 * ufshcd_eh_device_reset_handler - device reset handler registered to
6849 * scsi layer.
7a3e97b0
SY		 6850 * @cmd: SCSI command pointer
6851 *
6852 * Returns SUCCESS/FAILED
6853 */
3441da7d 6854static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6855{
6856 struct Scsi_Host *host;
6857 struct ufs_hba *hba;
7a3e97b0
SY		 6858 u32 pos;
6859 int err;
35fc4cd3 6860 u8 resp = 0xF, lun;
7a3e97b0
SY		 6861
6862 host = cmd->device->host;
6863 hba = shost_priv(host);
7a3e97b0 6864
35fc4cd3
CG		 6865 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6866 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
e2933132 6867 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6868 if (!err)
6869 err = resp;
7a3e97b0 6870 goto out;
e2933132 6871 }
7a3e97b0 6872
3441da7d
SRT		 6873 /* clear the commands that were pending for corresponding LUN */
6874 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
35fc4cd3 6875 if (hba->lrb[pos].lun == lun) {
3441da7d
SRT		 6876 err = ufshcd_clear_cmd(hba, pos);
6877 if (err)
6878 break;
73dc3c4a 6879 __ufshcd_transfer_req_compl(hba, pos, /*retry_requests=*/true);
7a3e97b0 6880 }
3441da7d 6881 }
7fabb77b 6882
7a3e97b0 6883out:
7fabb77b 6884 hba->req_abort_count = 0;
e965e5e0 6885 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
3441da7d
SRT		 6886 if (!err) {
6887 err = SUCCESS;
6888 } else {
6889 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6890 err = FAILED;
6891 }
7a3e97b0
SY		 6892 return err;
6893}
6894
e0b299e3
GB		 6895static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6896{
6897 struct ufshcd_lrb *lrbp;
6898 int tag;
6899
6900 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6901 lrbp = &hba->lrb[tag];
6902 lrbp->req_abort_skip = true;
6903 }
6904}
6905
7a3e97b0 6906/**
307348f6 6907 * ufshcd_try_to_abort_task - abort a specific task
d23ec0b6
LJ		 6908 * @hba: Pointer to adapter instance
6909 * @tag: Task tag/index to be aborted
7a3e97b0 6910 *
f20810d8
SRT		 6911 * Abort the pending command in device by sending UFS_ABORT_TASK task management
6912 * command, and in host controller by clearing the door-bell register. There can
6913 * be race between controller sending the command to the device while abort is
6914 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6915 * really issued and then try to abort it.
6916 *
307348f6
CG		 6917 * Returns zero on success, non-zero on failure
6918 */
6919static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6920{
6921 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6922 int err = 0;
6923 int poll_cnt;
6924 u8 resp = 0xF;
6925 u32 reg;
6926
6927 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6928 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6929 UFS_QUERY_TASK, &resp);
6930 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6931 /* cmd pending in the device */
6932 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6933 __func__, tag);
6934 break;
6935 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6936 /*
6937 * cmd not pending in the device, check if it is
6938 * in transition.
6939 */
6940 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6941 __func__, tag);
6942 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6943 if (reg & (1 << tag)) {
6944 /* sleep for max. 200us to stabilize */
6945 usleep_range(100, 200);
6946 continue;
6947 }
6948 /* command completed already */
6949 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6950 __func__, tag);
6951 goto out;
6952 } else {
6953 dev_err(hba->dev,
6954 "%s: no response from device. tag = %d, err %d\n",
6955 __func__, tag, err);
6956 if (!err)
6957 err = resp; /* service response error */
6958 goto out;
6959 }
6960 }
6961
6962 if (!poll_cnt) {
6963 err = -EBUSY;
6964 goto out;
6965 }
6966
6967 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6968 UFS_ABORT_TASK, &resp);
6969 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6970 if (!err) {
6971 err = resp; /* service response error */
6972 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6973 __func__, tag, err);
6974 }
6975 goto out;
6976 }
6977
6978 err = ufshcd_clear_cmd(hba, tag);
6979 if (err)
6980 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6981 __func__, tag, err);
6982
6983out:
6984 return err;
6985}
6986
6987/**
6988 * ufshcd_abort - scsi host template eh_abort_handler callback
6989 * @cmd: SCSI command pointer
6990 *
7a3e97b0
SY		 6991 * Returns SUCCESS/FAILED
6992 */
6993static int ufshcd_abort(struct scsi_cmnd *cmd)
6994{
4728ab4a
BVA		 6995 struct Scsi_Host *host = cmd->device->host;
6996 struct ufs_hba *hba = shost_priv(host);
3f2c1002 6997 int tag = scsi_cmd_to_rq(cmd)->tag;
4728ab4a 6998 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7a3e97b0 6999 unsigned long flags;
64180742 7000 int err = FAILED;
e9d501b1 7001 u32 reg;
7a3e97b0 7002
4728ab4a 7003 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7a3e97b0 7004
1ab27c9c 7005 ufshcd_hold(hba, false);
14497328 7006 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
64180742 7007 /* If command is already aborted/completed, return FAILED. */
14497328
YG		 7008 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7009 dev_err(hba->dev,
7010 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7011 __func__, tag, hba->outstanding_reqs, reg);
64180742 7012 goto release;
14497328 7013 }
7a3e97b0 7014
66cc820f 7015 /* Print Transfer Request of aborted task */
d87a1f6d 7016 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 7017
7fabb77b
GB		 7018 /*
7019 * Print detailed info about aborted request.
7020 * As more than one request might get aborted at the same time,
7021 * print full information only for the first aborted request in order
7022 * to reduce repeated printouts. For other aborted requests only print
7023 * basic details.
7024 */
7a7e66c6 7025 scsi_print_command(cmd);
7fabb77b 7026 if (!hba->req_abort_count) {
e965e5e0
SC		 7027 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7028 ufshcd_print_evt_hist(hba);
6ba65588 7029 ufshcd_print_host_state(hba);
7fabb77b
GB		 7030 ufshcd_print_pwr_info(hba);
7031 ufshcd_print_trs(hba, 1 << tag, true);
7032 } else {
7033 ufshcd_print_trs(hba, 1 << tag, false);
7034 }
7035 hba->req_abort_count++;
e0b299e3 7036
d87a1f6d
BH		 7037 if (!(reg & (1 << tag))) {
7038 dev_err(hba->dev,
7039 "%s: cmd was completed, but without a notifying intr, tag = %d",
7040 __func__, tag);
73dc3c4a 7041 __ufshcd_transfer_req_compl(hba, 1UL << tag, /*retry_requests=*/false);
64180742 7042 goto release;
d87a1f6d
BH		 7043 }
7044
7a7e66c6
CG		 7045 /*
7046 * Task abort to the device W-LUN is illegal. When this command
7047 * will fail, due to spec violation, scsi err handling next step
7048 * will be to send LU reset which, again, is a spec violation.
7049 * To avoid these unnecessary/illegal steps, first we clean up
a45f9371 7050 * the lrb taken by this cmd and re-set it in outstanding_reqs,
a113eaaf 7051 * then queue the error handler and bail.
7a7e66c6
CG		 7052 */
7053 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7054 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
64180742 7055
7a7e66c6 7056 spin_lock_irqsave(host->host_lock, flags);
a45f9371 7057 hba->force_reset = true;
7a7e66c6 7058 spin_unlock_irqrestore(host->host_lock, flags);
a113eaaf
BVA		 7059
7060 ufshcd_schedule_eh(hba);
7061
64180742 7062 goto release;
7a7e66c6
CG		 7063 }
7064
e0b299e3 7065 /* Skip task abort in case previous aborts failed and report failure */
64180742
BVA		 7066 if (lrbp->req_abort_skip) {
7067 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7068 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7069 goto release;
7070 }
f20810d8 7071
64180742
BVA		 7072 err = ufshcd_try_to_abort_task(hba, tag);
7073 if (err) {
f20810d8 7074 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 7075 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8 7076 err = FAILED;
64180742 7077 goto release;
f20810d8
SRT		 7078 }
7079
64180742
BVA		 7080 err = SUCCESS;
7081
7082release:
7083 /* Matches the ufshcd_hold() call at the start of this function. */
1ab27c9c 7084 ufshcd_release(hba);
7a3e97b0
SY		 7085 return err;
7086}
7087
3441da7d
SRT		 7088/**
7089 * ufshcd_host_reset_and_restore - reset and restore host controller
7090 * @hba: per-adapter instance
7091 *
7092 * Note that host controller reset may issue DME_RESET to
7093 * local and remote (device) Uni-Pro stack and the attributes
7094 * are reset to default state.
7095 *
7096 * Returns zero on success, non-zero on failure
7097 */
7098static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7099{
7100 int err;
3441da7d 7101
2df74b69
CG		 7102 /*
7103 * Stop the host controller and complete the requests
7104 * cleared by h/w
7105 */
f02bc975 7106 ufshpb_reset_host(hba);
5cac1095 7107 ufshcd_hba_stop(hba);
2df74b69 7108 hba->silence_err_logs = true;
73dc3c4a 7109 ufshcd_retry_aborted_requests(hba);
2df74b69 7110 hba->silence_err_logs = false;
3441da7d 7111
a3cd5ec5 7112 /* scale up clocks to max frequency before full reinitialization */
394b949f 7113 ufshcd_set_clk_freq(hba, true);
a3cd5ec5 7114
3441da7d 7115 err = ufshcd_hba_enable(hba);
3441da7d
SRT		 7116
7117 /* Establish the link again and restore the device */
1918651f 7118 if (!err)
4ee7ee53
JK		 7119 err = ufshcd_probe_hba(hba, false);
7120
3441da7d
SRT		 7121 if (err)
7122 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
e965e5e0 7123 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
3441da7d
SRT		 7124 return err;
7125}
7126
7127/**
7128 * ufshcd_reset_and_restore - reset and re-initialize host/device
7129 * @hba: per-adapter instance
7130 *
7131 * Reset and recover device, host and re-establish link. This
7132 * is helpful to recover the communication in fatal error conditions.
7133 *
7134 * Returns zero on success, non-zero on failure
7135 */
7136static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7137{
4db7a236
CG		 7138 u32 saved_err;
7139 u32 saved_uic_err;
3441da7d 7140 int err = 0;
4db7a236 7141 unsigned long flags;
1d337ec2 7142 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 7143
4db7a236
CG		 7144 /*
7145 * This is a fresh start, cache and clear saved error first,
7146 * in case new error generated during reset and restore.
7147 */
7148 spin_lock_irqsave(hba->host->host_lock, flags);
7149 saved_err = hba->saved_err;
7150 saved_uic_err = hba->saved_uic_err;
7151 hba->saved_err = 0;
7152 hba->saved_uic_err = 0;
7153 spin_unlock_irqrestore(hba->host->host_lock, flags);
7154
1d337ec2 7155 do {
d8d9f793 7156 /* Reset the attached device */
31a5d9ca 7157 ufshcd_device_reset(hba);
d8d9f793 7158
1d337ec2
SRT		 7159 err = ufshcd_host_reset_and_restore(hba);
7160 } while (err && --retries);
3441da7d 7161
4db7a236
CG		 7162 spin_lock_irqsave(hba->host->host_lock, flags);
7163 /*
7164 * Inform scsi mid-layer that we did reset and allow to handle
7165 * Unit Attention properly.
7166 */
7167 scsi_report_bus_reset(hba->host, 0);
7168 if (err) {
88a92d6a 7169 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4db7a236
CG		 7170 hba->saved_err |= saved_err;
7171 hba->saved_uic_err |= saved_uic_err;
7172 }
7173 spin_unlock_irqrestore(hba->host->host_lock, flags);
7174
3441da7d
SRT		 7175 return err;
7176}
7177
7178/**
7179 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 7180 * @cmd: SCSI command pointer
3441da7d
SRT		 7181 *
7182 * Returns SUCCESS/FAILED
7183 */
7184static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7185{
4db7a236 7186 int err = SUCCESS;
3441da7d
SRT		 7187 unsigned long flags;
7188 struct ufs_hba *hba;
7189
7190 hba = shost_priv(cmd->device->host);
7191
4db7a236
CG		 7192 spin_lock_irqsave(hba->host->host_lock, flags);
7193 hba->force_reset = true;
4db7a236 7194 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
3441da7d
SRT		 7195 spin_unlock_irqrestore(hba->host->host_lock, flags);
7196
a113eaaf 7197 ufshcd_err_handler(hba->host);
3441da7d
SRT		 7198
7199 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236 7200 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
3441da7d 7201 err = FAILED;
3441da7d
SRT		 7202 spin_unlock_irqrestore(hba->host->host_lock, flags);
7203
7204 return err;
7205}
7206
3a4bf06d
YG		 7207/**
7208 * ufshcd_get_max_icc_level - calculate the ICC level
7209 * @sup_curr_uA: max. current supported by the regulator
7210 * @start_scan: row at the desc table to start scan from
7211 * @buff: power descriptor buffer
7212 *
7213 * Returns calculated max ICC level for specific regulator
7214 */
7215static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7216{
7217 int i;
7218 int curr_uA;
7219 u16 data;
7220 u16 unit;
7221
7222 for (i = start_scan; i >= 0; i--) {
d79713f9 7223 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 7224 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7225 ATTR_ICC_LVL_UNIT_OFFSET;
7226 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7227 switch (unit) {
7228 case UFSHCD_NANO_AMP:
7229 curr_uA = curr_uA / 1000;
7230 break;
7231 case UFSHCD_MILI_AMP:
7232 curr_uA = curr_uA * 1000;
7233 break;
7234 case UFSHCD_AMP:
7235 curr_uA = curr_uA * 1000 * 1000;
7236 break;
7237 case UFSHCD_MICRO_AMP:
7238 default:
7239 break;
7240 }
7241 if (sup_curr_uA >= curr_uA)
7242 break;
7243 }
7244 if (i < 0) {
7245 i = 0;
7246 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7247 }
7248
7249 return (u32)i;
7250}
7251
7252/**
11eea9b3 7253 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
3a4bf06d
YG		 7254 * In case regulators are not initialized we'll return 0
7255 * @hba: per-adapter instance
7256 * @desc_buf: power descriptor buffer to extract ICC levels from.
7257 * @len: length of desc_buff
7258 *
7259 * Returns calculated ICC level
7260 */
7261static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7262 u8 *desc_buf, int len)
7263{
7264 u32 icc_level = 0;
7265
7266 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7267 !hba->vreg_info.vccq2) {
7268 dev_err(hba->dev,
7269 "%s: Regulator capability was not set, actvIccLevel=%d",
7270 __func__, icc_level);
7271 goto out;
7272 }
7273
0873045f 7274 if (hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 7275 icc_level = ufshcd_get_max_icc_level(
7276 hba->vreg_info.vcc->max_uA,
7277 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7278 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7279
0873045f 7280 if (hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 7281 icc_level = ufshcd_get_max_icc_level(
7282 hba->vreg_info.vccq->max_uA,
7283 icc_level,
7284 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7285
0873045f 7286 if (hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 7287 icc_level = ufshcd_get_max_icc_level(
7288 hba->vreg_info.vccq2->max_uA,
7289 icc_level,
7290 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7291out:
7292 return icc_level;
7293}
7294
e89860f1 7295static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 7296{
7297 int ret;
7a0bf85b 7298 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
bbe21d7a 7299 u8 *desc_buf;
e89860f1 7300 u32 icc_level;
bbe21d7a
KC		 7301
7302 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7303 if (!desc_buf)
7304 return;
3a4bf06d 7305
c4607a09
BH		 7306 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7307 desc_buf, buff_len);
3a4bf06d
YG		 7308 if (ret) {
7309 dev_err(hba->dev,
7310 "%s: Failed reading power descriptor.len = %d ret = %d",
7311 __func__, buff_len, ret);
bbe21d7a 7312 goto out;
3a4bf06d
YG		 7313 }
7314
e89860f1
CG		 7315 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7316 buff_len);
7317 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 7318
dbd34a61 7319 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 7320 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 7321
7322 if (ret)
7323 dev_err(hba->dev,
7324 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 7325 __func__, icc_level, ret);
3a4bf06d 7326
bbe21d7a
KC		 7327out:
7328 kfree(desc_buf);
3a4bf06d
YG		 7329}
7330
fb276f77
CG		 7331static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7332{
7333 scsi_autopm_get_device(sdev);
7334 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7335 if (sdev->rpm_autosuspend)
7336 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7337 RPM_AUTOSUSPEND_DELAY_MS);
7338 scsi_autopm_put_device(sdev);
7339}
7340
2a8fa600
SJ		 7341/**
7342 * ufshcd_scsi_add_wlus - Adds required W-LUs
7343 * @hba: per-adapter instance
7344 *
7345 * UFS device specification requires the UFS devices to support 4 well known
7346 * logical units:
7347 * "REPORT_LUNS" (address: 01h)
7348 * "UFS Device" (address: 50h)
7349 * "RPMB" (address: 44h)
7350 * "BOOT" (address: 30h)
7351 * UFS device's power management needs to be controlled by "POWER CONDITION"
7352 * field of SSU (START STOP UNIT) command. But this "power condition" field
7353 * will take effect only when its sent to "UFS device" well known logical unit
7354 * hence we require the scsi_device instance to represent this logical unit in
7355 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 7356 *
2a8fa600
SJ		 7357 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7358 * Block) LU so user space process can control this LU. User space may also
7359 * want to have access to BOOT LU.
8aa29f19 7360 *
2a8fa600
SJ		 7361 * This function adds scsi device instances for each of all well known LUs
7362 * (except "REPORT LUNS" LU).
7363 *
7364 * Returns zero on success (all required W-LUs are added successfully),
7365 * non-zero error value on failure (if failed to add any of the required W-LU).
7366 */
7367static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7368{
7369 int ret = 0;
7c48bfd0 7370 struct scsi_device *sdev_boot;
2a8fa600
SJ		 7371
7372 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7373 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7374 if (IS_ERR(hba->sdev_ufs_device)) {
7375 ret = PTR_ERR(hba->sdev_ufs_device);
7376 hba->sdev_ufs_device = NULL;
7377 goto out;
7378 }
7c48bfd0 7379 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 7380
4f3e900b 7381 hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7382 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
4f3e900b
JK		 7383 if (IS_ERR(hba->sdev_rpmb)) {
7384 ret = PTR_ERR(hba->sdev_rpmb);
3d21fbde 7385 goto remove_sdev_ufs_device;
2a8fa600 7386 }
4f3e900b
JK		 7387 ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);
7388 scsi_device_put(hba->sdev_rpmb);
3d21fbde
HK		 7389
7390 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7391 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 7392 if (IS_ERR(sdev_boot)) {
3d21fbde 7393 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 7394 } else {
7395 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 7396 scsi_device_put(sdev_boot);
fb276f77 7397 }
2a8fa600
SJ		 7398 goto out;
7399
2a8fa600
SJ		 7400remove_sdev_ufs_device:
7401 scsi_remove_device(hba->sdev_ufs_device);
7402out:
7403 return ret;
7404}
7405
3d17b9b5
AD		 7406static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7407{
a7f1e69d 7408 struct ufs_dev_info *dev_info = &hba->dev_info;
6f8d5a6a
SC		 7409 u8 lun;
7410 u32 d_lu_wb_buf_alloc;
e8d03813 7411 u32 ext_ufs_feature;
6f8d5a6a 7412
817d7e14
SC		 7413 if (!ufshcd_is_wb_allowed(hba))
7414 return;
a7f1e69d
SC		 7415 /*
7416 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7417 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7418 * enabled
7419 */
7420 if (!(dev_info->wspecversion >= 0x310 ||
7421 dev_info->wspecversion == 0x220 ||
7422 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7423 goto wb_disabled;
817d7e14 7424
7a0bf85b
BH		 7425 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7426 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
817d7e14
SC		 7427 goto wb_disabled;
7428
e8d03813
BH		 7429 ext_ufs_feature = get_unaligned_be32(desc_buf +
7430 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
817d7e14 7431
e8d03813 7432 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
817d7e14
SC		 7433 goto wb_disabled;
7434
3d17b9b5 7435 /*
ae1ce1fc
BH		 7436 * WB may be supported but not configured while provisioning. The spec
7437 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7438 * buffer configured.
3d17b9b5 7439 */
4cd48995 7440 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
3d17b9b5 7441
a7f1e69d 7442 dev_info->b_presrv_uspc_en =
3d17b9b5
AD		 7443 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7444
4cd48995 7445 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
e8d03813
BH		 7446 if (!get_unaligned_be32(desc_buf +
7447 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
6f8d5a6a
SC		 7448 goto wb_disabled;
7449 } else {
7450 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7451 d_lu_wb_buf_alloc = 0;
7452 ufshcd_read_unit_desc_param(hba,
7453 lun,
7454 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7455 (u8 *)&d_lu_wb_buf_alloc,
7456 sizeof(d_lu_wb_buf_alloc));
7457 if (d_lu_wb_buf_alloc) {
a7f1e69d 7458 dev_info->wb_dedicated_lu = lun;
6f8d5a6a
SC		 7459 break;
7460 }
7461 }
817d7e14 7462
6f8d5a6a
SC		 7463 if (!d_lu_wb_buf_alloc)
7464 goto wb_disabled;
7465 }
817d7e14
SC		 7466 return;
7467
7468wb_disabled:
7469 hba->caps &= ~UFSHCD_CAP_WB_EN;
7470}
7471
e88e2d32
AA		 7472static void ufshcd_temp_notif_probe(struct ufs_hba *hba, u8 *desc_buf)
7473{
7474 struct ufs_dev_info *dev_info = &hba->dev_info;
7475 u32 ext_ufs_feature;
7476 u8 mask = 0;
7477
7478 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7479 return;
7480
7481 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7482
7483 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7484 mask |= MASK_EE_TOO_LOW_TEMP;
7485
7486 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7487 mask |= MASK_EE_TOO_HIGH_TEMP;
7488
7489 if (mask) {
7490 ufshcd_enable_ee(hba, mask);
7491 ufs_hwmon_probe(hba, mask);
7492 }
7493}
7494
8db269a5 7495void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
817d7e14
SC		 7496{
7497 struct ufs_dev_fix *f;
7498 struct ufs_dev_info *dev_info = &hba->dev_info;
7499
8db269a5
SC		 7500 if (!fixups)
7501 return;
7502
7503 for (f = fixups; f->quirk; f++) {
817d7e14
SC		 7504 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7505 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7506 ((dev_info->model &&
7507 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7508 !strcmp(f->model, UFS_ANY_MODEL)))
7509 hba->dev_quirks |= f->quirk;
7510 }
3d17b9b5 7511}
8db269a5 7512EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
3d17b9b5 7513
c28c00ba
SC		 7514static void ufs_fixup_device_setup(struct ufs_hba *hba)
7515{
7516 /* fix by general quirk table */
8db269a5 7517 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
c28c00ba
SC		 7518
7519 /* allow vendors to fix quirks */
7520 ufshcd_vops_fixup_dev_quirks(hba);
7521}
7522
09750066 7523static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 7524{
7525 int err;
7526 u8 model_index;
f02bc975 7527 u8 b_ufs_feature_sup;
bbe21d7a 7528 u8 *desc_buf;
09750066 7529 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 7530
458a45f5 7531 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 7532 if (!desc_buf) {
7533 err = -ENOMEM;
7534 goto out;
7535 }
c58ab7aa 7536
c4607a09 7537 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7a0bf85b 7538 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
c58ab7aa
YG		 7539 if (err) {
7540 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7541 __func__, err);
7542 goto out;
7543 }
7544
7545 /*
7546 * getting vendor (manufacturerID) and Bank Index in big endian
7547 * format
7548 */
09750066 7549 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 7550 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7551
09f17791
CG		 7552 /* getting Specification Version in big endian format */
7553 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7554 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
f02bc975 7555 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
09f17791 7556
c58ab7aa 7557 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5 7558
f02bc975
DP		 7559 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7560 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
41d8a933
DP		 7561 bool hpb_en = false;
7562
f02bc975 7563 ufshpb_get_dev_info(hba, desc_buf);
41d8a933
DP		 7564
7565 if (!ufshpb_is_legacy(hba))
7566 err = ufshcd_query_flag_retry(hba,
7567 UPIU_QUERY_OPCODE_READ_FLAG,
7568 QUERY_FLAG_IDN_HPB_EN, 0,
7569 &hpb_en);
7570
7571 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7572 dev_info->hpb_enabled = true;
f02bc975
DP		 7573 }
7574
4b828fe1 7575 err = ufshcd_read_string_desc(hba, model_index,
09750066 7576 &dev_info->model, SD_ASCII_STD);
4b828fe1 7577 if (err < 0) {
c58ab7aa
YG		 7578 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7579 __func__, err);
7580 goto out;
7581 }
7582
b294ff3e
AD		 7583 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7584 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7585
817d7e14
SC		 7586 ufs_fixup_device_setup(hba);
7587
a7f1e69d 7588 ufshcd_wb_probe(hba, desc_buf);
817d7e14 7589
e88e2d32
AA		 7590 ufshcd_temp_notif_probe(hba, desc_buf);
7591
4b828fe1
TW		 7592 /*
7593 * ufshcd_read_string_desc returns size of the string
7594 * reset the error value
7595 */
7596 err = 0;
c58ab7aa
YG		 7597
7598out:
bbe21d7a 7599 kfree(desc_buf);
c58ab7aa
YG		 7600 return err;
7601}
7602
09750066 7603static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 7604{
09750066
BH		 7605 struct ufs_dev_info *dev_info = &hba->dev_info;
7606
7607 kfree(dev_info->model);
7608 dev_info->model = NULL;
4b828fe1
TW		 7609}
7610
37113106
YG		 7611/**
7612 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7613 * @hba: per-adapter instance
7614 *
7615 * PA_TActivate parameter can be tuned manually if UniPro version is less than
7616 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7617 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7618 * the hibern8 exit latency.
7619 *
7620 * Returns zero on success, non-zero error value on failure.
7621 */
7622static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7623{
7624 int ret = 0;
7625 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7626
7627 ret = ufshcd_dme_peer_get(hba,
7628 UIC_ARG_MIB_SEL(
7629 RX_MIN_ACTIVATETIME_CAPABILITY,
7630 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7631 &peer_rx_min_activatetime);
7632 if (ret)
7633 goto out;
7634
7635 /* make sure proper unit conversion is applied */
7636 tuned_pa_tactivate =
7637 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7638 / PA_TACTIVATE_TIME_UNIT_US);
7639 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7640 tuned_pa_tactivate);
7641
7642out:
7643 return ret;
7644}
7645
7646/**
7647 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7648 * @hba: per-adapter instance
7649 *
7650 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7651 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7652 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7653 * This optimal value can help reduce the hibern8 exit latency.
7654 *
7655 * Returns zero on success, non-zero error value on failure.
7656 */
7657static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7658{
7659 int ret = 0;
7660 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7661 u32 max_hibern8_time, tuned_pa_hibern8time;
7662
7663 ret = ufshcd_dme_get(hba,
7664 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7665 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7666 &local_tx_hibern8_time_cap);
7667 if (ret)
7668 goto out;
7669
7670 ret = ufshcd_dme_peer_get(hba,
7671 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7672 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7673 &peer_rx_hibern8_time_cap);
7674 if (ret)
7675 goto out;
7676
7677 max_hibern8_time = max(local_tx_hibern8_time_cap,
7678 peer_rx_hibern8_time_cap);
7679 /* make sure proper unit conversion is applied */
7680 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7681 / PA_HIBERN8_TIME_UNIT_US);
7682 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7683 tuned_pa_hibern8time);
7684out:
7685 return ret;
7686}
7687
c6a6db43 7688/**
7689 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7690 * less than device PA_TACTIVATE time.
7691 * @hba: per-adapter instance
7692 *
7693 * Some UFS devices require host PA_TACTIVATE to be lower than device
7694 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7695 * for such devices.
7696 *
7697 * Returns zero on success, non-zero error value on failure.
7698 */
7699static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7700{
7701 int ret = 0;
7702 u32 granularity, peer_granularity;
7703 u32 pa_tactivate, peer_pa_tactivate;
7704 u32 pa_tactivate_us, peer_pa_tactivate_us;
7705 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7706
7707 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7708 &granularity);
7709 if (ret)
7710 goto out;
7711
7712 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7713 &peer_granularity);
7714 if (ret)
7715 goto out;
7716
7717 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7718 (granularity > PA_GRANULARITY_MAX_VAL)) {
7719 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7720 __func__, granularity);
7721 return -EINVAL;
7722 }
7723
7724 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7725 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7726 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7727 __func__, peer_granularity);
7728 return -EINVAL;
7729 }
7730
7731 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7732 if (ret)
7733 goto out;
7734
7735 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7736 &peer_pa_tactivate);
7737 if (ret)
7738 goto out;
7739
7740 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7741 peer_pa_tactivate_us = peer_pa_tactivate *
7742 gran_to_us_table[peer_granularity - 1];
7743
7744 if (pa_tactivate_us > peer_pa_tactivate_us) {
7745 u32 new_peer_pa_tactivate;
7746
7747 new_peer_pa_tactivate = pa_tactivate_us /
7748 gran_to_us_table[peer_granularity - 1];
7749 new_peer_pa_tactivate++;
7750 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7751 new_peer_pa_tactivate);
7752 }
7753
7754out:
7755 return ret;
7756}
7757
09750066 7758static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 7759{
7760 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7761 ufshcd_tune_pa_tactivate(hba);
7762 ufshcd_tune_pa_hibern8time(hba);
7763 }
7764
e91ed9e0
CG		 7765 ufshcd_vops_apply_dev_quirks(hba);
7766
37113106
YG		 7767 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7768 /* set 1ms timeout for PA_TACTIVATE */
7769 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 7770
7771 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7772 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 7773}
7774
ff8e20c6
DR		 7775static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7776{
ff8e20c6
DR		 7777 hba->ufs_stats.hibern8_exit_cnt = 0;
7778 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 7779 hba->req_abort_count = 0;
ff8e20c6
DR		 7780}
7781
731f0621
BH		 7782static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7783{
7784 int err;
7785 size_t buff_len;
7786 u8 *desc_buf;
7787
7a0bf85b 7788 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
731f0621
BH		 7789 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7790 if (!desc_buf) {
7791 err = -ENOMEM;
7792 goto out;
7793 }
7794
c4607a09
BH		 7795 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7796 desc_buf, buff_len);
731f0621
BH		 7797 if (err) {
7798 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7799 __func__, err);
7800 goto out;
7801 }
7802
7803 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7804 hba->dev_info.max_lu_supported = 32;
7805 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7806 hba->dev_info.max_lu_supported = 8;
7807
f02bc975
DP		 7808 if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7809 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7810 ufshpb_get_geo_info(hba, desc_buf);
7811
731f0621
BH		 7812out:
7813 kfree(desc_buf);
7814 return err;
7815}
7816
9e1e8a75
SJ		 7817static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7818 {19200000, REF_CLK_FREQ_19_2_MHZ},
7819 {26000000, REF_CLK_FREQ_26_MHZ},
7820 {38400000, REF_CLK_FREQ_38_4_MHZ},
7821 {52000000, REF_CLK_FREQ_52_MHZ},
7822 {0, REF_CLK_FREQ_INVAL},
7823};
7824
7825static enum ufs_ref_clk_freq
7826ufs_get_bref_clk_from_hz(unsigned long freq)
7827{
7828 int i;
7829
7830 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7831 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7832 return ufs_ref_clk_freqs[i].val;
7833
7834 return REF_CLK_FREQ_INVAL;
7835}
7836
7837void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7838{
7839 unsigned long freq;
7840
7841 freq = clk_get_rate(refclk);
7842
7843 hba->dev_ref_clk_freq =
7844 ufs_get_bref_clk_from_hz(freq);
7845
7846 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7847 dev_err(hba->dev,
7848 "invalid ref_clk setting = %ld\n", freq);
7849}
7850
7851static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7852{
7853 int err;
7854 u32 ref_clk;
7855 u32 freq = hba->dev_ref_clk_freq;
7856
7857 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7858 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7859
7860 if (err) {
7861 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7862 err);
7863 goto out;
7864 }
7865
7866 if (ref_clk == freq)
7867 goto out; /* nothing to update */
7868
7869 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7870 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7871
7872 if (err) {
7873 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7874 ufs_ref_clk_freqs[freq].freq_hz);
7875 goto out;
7876 }
7877
7878 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7879 ufs_ref_clk_freqs[freq].freq_hz);
7880
7881out:
7882 return err;
7883}
7884
1b9e2141
BH		 7885static int ufshcd_device_params_init(struct ufs_hba *hba)
7886{
7887 bool flag;
7a0bf85b 7888 int ret, i;
1b9e2141 7889
7a0bf85b
BH		 7890 /* Init device descriptor sizes */
7891 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7892 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
1b9e2141 7893
731f0621
BH		 7894 /* Init UFS geometry descriptor related parameters */
7895 ret = ufshcd_device_geo_params_init(hba);
7896 if (ret)
7897 goto out;
7898
1b9e2141
BH		 7899 /* Check and apply UFS device quirks */
7900 ret = ufs_get_device_desc(hba);
7901 if (ret) {
7902 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7903 __func__, ret);
7904 goto out;
7905 }
7906
09f17791
CG		 7907 ufshcd_get_ref_clk_gating_wait(hba);
7908
1b9e2141 7909 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 7910 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
1b9e2141
BH		 7911 hba->dev_info.f_power_on_wp_en = flag;
7912
2b35b2ad
BH		 7913 /* Probe maximum power mode co-supported by both UFS host and device */
7914 if (ufshcd_get_max_pwr_mode(hba))
7915 dev_err(hba->dev,
7916 "%s: Failed getting max supported power mode\n",
7917 __func__);
1b9e2141
BH		 7918out:
7919 return ret;
7920}
7921
7922/**
7923 * ufshcd_add_lus - probe and add UFS logical units
7924 * @hba: per-adapter instance
7925 */
7926static int ufshcd_add_lus(struct ufs_hba *hba)
7927{
7928 int ret;
7929
1b9e2141
BH		 7930 /* Add required well known logical units to scsi mid layer */
7931 ret = ufshcd_scsi_add_wlus(hba);
7932 if (ret)
7933 goto out;
7934
4ee7ee53
JK		 7935 ufshcd_clear_ua_wluns(hba);
7936
1b9e2141
BH		 7937 /* Initialize devfreq after UFS device is detected */
7938 if (ufshcd_is_clkscaling_supported(hba)) {
7939 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7940 &hba->pwr_info,
7941 sizeof(struct ufs_pa_layer_attr));
7942 hba->clk_scaling.saved_pwr_info.is_valid = true;
1b9e2141 7943 hba->clk_scaling.is_allowed = true;
1b9e2141 7944
b058fa86
SC		 7945 ret = ufshcd_devfreq_init(hba);
7946 if (ret)
7947 goto out;
7948
7949 hba->clk_scaling.is_enabled = true;
7950 ufshcd_init_clk_scaling_sysfs(hba);
1b9e2141
BH		 7951 }
7952
7953 ufs_bsg_probe(hba);
f02bc975 7954 ufshpb_init(hba);
1b9e2141
BH		 7955 scsi_scan_host(hba->host);
7956 pm_runtime_put_sync(hba->dev);
7957
1b9e2141
BH		 7958out:
7959 return ret;
7960}
7961
ac1bc2ba
BVA		 7962static void ufshcd_request_sense_done(struct request *rq, blk_status_t error)
7963{
7964 if (error != BLK_STS_OK)
9b5ac8ab
AH		 7965 pr_err("%s: REQUEST SENSE failed (%d)\n", __func__, error);
7966 kfree(rq->end_io_data);
ac1bc2ba
BVA		 7967 blk_put_request(rq);
7968}
7969
4f3e900b 7970static int
ac1bc2ba
BVA		 7971ufshcd_request_sense_async(struct ufs_hba *hba, struct scsi_device *sdev)
7972{
7973 /*
9b5ac8ab
AH		 7974 * Some UFS devices clear unit attention condition only if the sense
7975 * size used (UFS_SENSE_SIZE in this case) is non-zero.
ac1bc2ba 7976 */
9b5ac8ab 7977 static const u8 cmd[6] = {REQUEST_SENSE, 0, 0, 0, UFS_SENSE_SIZE, 0};
ac1bc2ba
BVA		 7978 struct scsi_request *rq;
7979 struct request *req;
9b5ac8ab
AH		 7980 char *buffer;
7981 int ret;
ac1bc2ba 7982
9b5ac8ab
AH		 7983 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
7984 if (!buffer)
7985 return -ENOMEM;
7986
7987 req = blk_get_request(sdev->request_queue, REQ_OP_DRV_IN,
7988 /*flags=*/BLK_MQ_REQ_PM);
7989 if (IS_ERR(req)) {
7990 ret = PTR_ERR(req);
7991 goto out_free;
7992 }
7993
7994 ret = blk_rq_map_kern(sdev->request_queue, req,
7995 buffer, UFS_SENSE_SIZE, GFP_NOIO);
7996 if (ret)
7997 goto out_put;
ac1bc2ba
BVA		 7998
7999 rq = scsi_req(req);
8000 rq->cmd_len = ARRAY_SIZE(cmd);
8001 memcpy(rq->cmd, cmd, rq->cmd_len);
8002 rq->retries = 3;
8003 req->timeout = 1 * HZ;
8004 req->rq_flags |= RQF_PM | RQF_QUIET;
9b5ac8ab 8005 req->end_io_data = buffer;
ac1bc2ba
BVA		 8006
8007 blk_execute_rq_nowait(/*bd_disk=*/NULL, req, /*at_head=*/true,
8008 ufshcd_request_sense_done);
8009 return 0;
9b5ac8ab
AH		 8010
8011out_put:
8012 blk_put_request(req);
8013out_free:
8014 kfree(buffer);
8015 return ret;
ac1bc2ba 8016}
4f3e900b
JK		 8017
8018static int ufshcd_clear_ua_wlun(struct ufs_hba *hba, u8 wlun)
8019{
8020 struct scsi_device *sdp;
8021 unsigned long flags;
8022 int ret = 0;
8023
8024 spin_lock_irqsave(hba->host->host_lock, flags);
8025 if (wlun == UFS_UPIU_UFS_DEVICE_WLUN)
8026 sdp = hba->sdev_ufs_device;
8027 else if (wlun == UFS_UPIU_RPMB_WLUN)
8028 sdp = hba->sdev_rpmb;
8029 else
4c60244d 8030 BUG();
4f3e900b
JK		 8031 if (sdp) {
8032 ret = scsi_device_get(sdp);
8033 if (!ret && !scsi_device_online(sdp)) {
8034 ret = -ENODEV;
8035 scsi_device_put(sdp);
8036 }
8037 } else {
8038 ret = -ENODEV;
8039 }
8040 spin_unlock_irqrestore(hba->host->host_lock, flags);
8041 if (ret)
8042 goto out_err;
8043
ac1bc2ba 8044 ret = ufshcd_request_sense_async(hba, sdp);
4f3e900b
JK		 8045 scsi_device_put(sdp);
8046out_err:
8047 if (ret)
8048 dev_err(hba->dev, "%s: UAC clear LU=%x ret = %d\n",
8049 __func__, wlun, ret);
8050 return ret;
8051}
8052
8053static int ufshcd_clear_ua_wluns(struct ufs_hba *hba)
8054{
8055 int ret = 0;
8056
8057 if (!hba->wlun_dev_clr_ua)
8058 goto out;
8059
8060 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8061 if (!ret)
8062 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
8063 if (!ret)
8064 hba->wlun_dev_clr_ua = false;
8065out:
8066 if (ret)
8067 dev_err(hba->dev, "%s: Failed to clear UAC WLUNS ret = %d\n",
8068 __func__, ret);
8069 return ret;
8070}
8071
6ccf44fe 8072/**
568dd995 8073 * ufshcd_probe_hba - probe hba to detect device and initialize it
1d337ec2 8074 * @hba: per-adapter instance
568dd995 8075 * @init_dev_params: whether or not to call ufshcd_device_params_init().
1d337ec2
SRT		 8076 *
8077 * Execute link-startup and verify device initialization
6ccf44fe 8078 */
568dd995 8079static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
6ccf44fe 8080{
6ccf44fe 8081 int ret;
4db7a236 8082 unsigned long flags;
7ff5ab47 8083 ktime_t start = ktime_get();
6ccf44fe 8084
aa53f580
CG		 8085 hba->ufshcd_state = UFSHCD_STATE_RESET;
8086
6ccf44fe 8087 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 8088 if (ret)
8089 goto out;
8090
ff8e20c6
DR		 8091 /* Debug counters initialization */
8092 ufshcd_clear_dbg_ufs_stats(hba);
8093
57d104c1
SJ		 8094 /* UniPro link is active now */
8095 ufshcd_set_link_active(hba);
d3e89bac 8096
1b9e2141 8097 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 8098 ret = ufshcd_verify_dev_init(hba);
8099 if (ret)
8100 goto out;
68078d5c 8101
1b9e2141 8102 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 8103 ret = ufshcd_complete_dev_init(hba);
8104 if (ret)
8105 goto out;
5a0b0cb9 8106
1b9e2141
BH		 8107 /*
8108 * Initialize UFS device parameters used by driver, these
8109 * parameters are associated with UFS descriptors.
8110 */
568dd995 8111 if (init_dev_params) {
1b9e2141
BH		 8112 ret = ufshcd_device_params_init(hba);
8113 if (ret)
8114 goto out;
93fdd5ac
TW		 8115 }
8116
09750066 8117 ufshcd_tune_unipro_params(hba);
4b828fe1 8118
57d104c1
SJ		 8119 /* UFS device is also active now */
8120 ufshcd_set_ufs_dev_active(hba);
66ec6d59 8121 ufshcd_force_reset_auto_bkops(hba);
57d104c1 8122 hba->wlun_dev_clr_ua = true;
b294ff3e 8123 hba->wlun_rpmb_clr_ua = true;
57d104c1 8124
2b35b2ad
BH		 8125 /* Gear up to HS gear if supported */
8126 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 8127 /*
8128 * Set the right value to bRefClkFreq before attempting to
8129 * switch to HS gears.
8130 */
8131 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8132 ufshcd_set_dev_ref_clk(hba);
7eb584db 8133 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 8134 if (ret) {
7eb584db
DR		 8135 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8136 __func__, ret);
8643ae66
DL		 8137 goto out;
8138 }
6a9df818 8139 ufshcd_print_pwr_info(hba);
7eb584db 8140 }
57d104c1 8141
e89860f1
CG		 8142 /*
8143 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8144 * and for removable UFS card as well, hence always set the parameter.
8145 * Note: Error handler may issue the device reset hence resetting
8146 * bActiveICCLevel as well so it is always safe to set this here.
8147 */
8148 ufshcd_set_active_icc_lvl(hba);
8149
3d17b9b5 8150 ufshcd_wb_config(hba);
cd469475
AH		 8151 if (hba->ee_usr_mask)
8152 ufshcd_write_ee_control(hba);
71d848b8
CG		 8153 /* Enable Auto-Hibernate if configured */
8154 ufshcd_auto_hibern8_enable(hba);
8155
f02bc975 8156 ufshpb_reset(hba);
5a0b0cb9 8157out:
4db7a236
CG		 8158 spin_lock_irqsave(hba->host->host_lock, flags);
8159 if (ret)
8160 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8161 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8162 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8163 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d337ec2 8164
7ff5ab47 8165 trace_ufshcd_init(dev_name(hba->dev), ret,
8166 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8167 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 8168 return ret;
8169}
8170
8171/**
8172 * ufshcd_async_scan - asynchronous execution for probing hba
8173 * @data: data pointer to pass to this function
8174 * @cookie: cookie data
8175 */
8176static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8177{
8178 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 8179 int ret;
1d337ec2 8180
9cd20d3f 8181 down(&hba->host_sem);
1b9e2141
BH		 8182 /* Initialize hba, detect and initialize UFS device */
8183 ret = ufshcd_probe_hba(hba, true);
9cd20d3f 8184 up(&hba->host_sem);
1b9e2141
BH		 8185 if (ret)
8186 goto out;
8187
8188 /* Probe and add UFS logical units */
8189 ret = ufshcd_add_lus(hba);
8190out:
8191 /*
8192 * If we failed to initialize the device or the device is not
8193 * present, turn off the power/clocks etc.
8194 */
8195 if (ret) {
8196 pm_runtime_put_sync(hba->dev);
1b9e2141
BH		 8197 ufshcd_hba_exit(hba);
8198 }
6ccf44fe
SJ		 8199}
8200
d829fc8a
SN		 8201static const struct attribute_group *ufshcd_driver_groups[] = {
8202 &ufs_sysfs_unit_descriptor_group,
ec92b59c 8203 &ufs_sysfs_lun_attributes_group,
f02bc975
DP		 8204#ifdef CONFIG_SCSI_UFS_HPB
8205 &ufs_sysfs_hpb_stat_group,
41d8a933 8206 &ufs_sysfs_hpb_param_group,
f02bc975 8207#endif
d829fc8a
SN		 8208 NULL,
8209};
8210
90b8491c
SC		 8211static struct ufs_hba_variant_params ufs_hba_vps = {
8212 .hba_enable_delay_us = 1000,
d14734ae 8213 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
90b8491c
SC		 8214 .devfreq_profile.polling_ms = 100,
8215 .devfreq_profile.target = ufshcd_devfreq_target,
8216 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8217 .ondemand_data.upthreshold = 70,
8218 .ondemand_data.downdifferential = 5,
8219};
8220
7a3e97b0
SY		 8221static struct scsi_host_template ufshcd_driver_template = {
8222 .module = THIS_MODULE,
8223 .name = UFSHCD,
8224 .proc_name = UFSHCD,
8225 .queuecommand = ufshcd_queuecommand,
8226 .slave_alloc = ufshcd_slave_alloc,
eeda4749 8227 .slave_configure = ufshcd_slave_configure,
7a3e97b0 8228 .slave_destroy = ufshcd_slave_destroy,
4264fd61 8229 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 8230 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 8231 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8232 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 8233 .this_id = -1,
8234 .sg_tablesize = SG_ALL,
8235 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8236 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 8237 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 8238 .max_host_blocked = 1,
c40ecc12 8239 .track_queue_depth = 1,
d829fc8a 8240 .sdev_groups = ufshcd_driver_groups,
4af14d11 8241 .dma_boundary = PAGE_SIZE - 1,
49615ba1 8242 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 8243};
8244
57d104c1
SJ		 8245static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8246 int ua)
8247{
7b16a07c 8248 int ret;
57d104c1 8249
7b16a07c
BA		 8250 if (!vreg)
8251 return 0;
57d104c1 8252
0487fff7
SC		 8253 /*
8254 * "set_load" operation shall be required on those regulators
8255 * which specifically configured current limitation. Otherwise
8256 * zero max_uA may cause unexpected behavior when regulator is
8257 * enabled or set as high power mode.
8258 */
8259 if (!vreg->max_uA)
8260 return 0;
8261
7b16a07c
BA		 8262 ret = regulator_set_load(vreg->reg, ua);
8263 if (ret < 0) {
8264 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8265 __func__, vreg->name, ua, ret);
57d104c1
SJ		 8266 }
8267
8268 return ret;
8269}
8270
8271static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8272 struct ufs_vreg *vreg)
8273{
73067981 8274 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 8275}
8276
8277static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8278 struct ufs_vreg *vreg)
8279{
7c7cfdcf
AH		 8280 if (!vreg)
8281 return 0;
8282
73067981 8283 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 8284}
8285
aa497613
SRT		 8286static int ufshcd_config_vreg(struct device *dev,
8287 struct ufs_vreg *vreg, bool on)
8288{
8289 int ret = 0;
72753590
GS		 8290 struct regulator *reg;
8291 const char *name;
aa497613
SRT		 8292 int min_uV, uA_load;
8293
8294 BUG_ON(!vreg);
8295
72753590
GS		 8296 reg = vreg->reg;
8297 name = vreg->name;
8298
aa497613 8299 if (regulator_count_voltages(reg) > 0) {
90d88f47
AD		 8300 uA_load = on ? vreg->max_uA : 0;
8301 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8302 if (ret)
8303 goto out;
8304
3b141e8c
SC		 8305 if (vreg->min_uV && vreg->max_uV) {
8306 min_uV = on ? vreg->min_uV : 0;
8307 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
b0008625 8308 if (ret)
3b141e8c
SC		 8309 dev_err(dev,
8310 "%s: %s set voltage failed, err=%d\n",
aa497613 8311 __func__, name, ret);
aa497613 8312 }
aa497613
SRT		 8313 }
8314out:
8315 return ret;
8316}
8317
8318static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8319{
8320 int ret = 0;
8321
73067981 8322 if (!vreg || vreg->enabled)
aa497613
SRT		 8323 goto out;
8324
8325 ret = ufshcd_config_vreg(dev, vreg, true);
8326 if (!ret)
8327 ret = regulator_enable(vreg->reg);
8328
8329 if (!ret)
8330 vreg->enabled = true;
8331 else
8332 dev_err(dev, "%s: %s enable failed, err=%d\n",
8333 __func__, vreg->name, ret);
8334out:
8335 return ret;
8336}
8337
8338static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8339{
8340 int ret = 0;
8341
f8162ac7 8342 if (!vreg || !vreg->enabled || vreg->always_on)
aa497613
SRT		 8343 goto out;
8344
8345 ret = regulator_disable(vreg->reg);
8346
8347 if (!ret) {
8348 /* ignore errors on applying disable config */
8349 ufshcd_config_vreg(dev, vreg, false);
8350 vreg->enabled = false;
8351 } else {
8352 dev_err(dev, "%s: %s disable failed, err=%d\n",
8353 __func__, vreg->name, ret);
8354 }
8355out:
8356 return ret;
8357}
8358
8359static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8360{
8361 int ret = 0;
8362 struct device *dev = hba->dev;
8363 struct ufs_vreg_info *info = &hba->vreg_info;
8364
aa497613
SRT		 8365 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8366 if (ret)
8367 goto out;
8368
8369 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8370 if (ret)
8371 goto out;
8372
8373 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
aa497613
SRT		 8374
8375out:
8376 if (ret) {
8377 ufshcd_toggle_vreg(dev, info->vccq2, false);
8378 ufshcd_toggle_vreg(dev, info->vccq, false);
8379 ufshcd_toggle_vreg(dev, info->vcc, false);
8380 }
8381 return ret;
8382}
8383
6a771a65
RS		 8384static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8385{
8386 struct ufs_vreg_info *info = &hba->vreg_info;
8387
60b7b823 8388 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 8389}
8390
aa497613
SRT		 8391static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8392{
8393 int ret = 0;
8394
8395 if (!vreg)
8396 goto out;
8397
8398 vreg->reg = devm_regulator_get(dev, vreg->name);
8399 if (IS_ERR(vreg->reg)) {
8400 ret = PTR_ERR(vreg->reg);
8401 dev_err(dev, "%s: %s get failed, err=%d\n",
8402 __func__, vreg->name, ret);
8403 }
8404out:
8405 return ret;
8406}
8407
8408static int ufshcd_init_vreg(struct ufs_hba *hba)
8409{
8410 int ret = 0;
8411 struct device *dev = hba->dev;
8412 struct ufs_vreg_info *info = &hba->vreg_info;
8413
aa497613
SRT		 8414 ret = ufshcd_get_vreg(dev, info->vcc);
8415 if (ret)
8416 goto out;
8417
8418 ret = ufshcd_get_vreg(dev, info->vccq);
b0008625
BH		 8419 if (!ret)
8420 ret = ufshcd_get_vreg(dev, info->vccq2);
aa497613
SRT		 8421out:
8422 return ret;
8423}
8424
6a771a65
RS		 8425static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8426{
8427 struct ufs_vreg_info *info = &hba->vreg_info;
8428
8429 if (info)
8430 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8431
8432 return 0;
8433}
8434
81309c24 8435static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
c6e79dac
SRT		 8436{
8437 int ret = 0;
8438 struct ufs_clk_info *clki;
8439 struct list_head *head = &hba->clk_list_head;
1ab27c9c 8440 unsigned long flags;
911a0771 8441 ktime_t start = ktime_get();
8442 bool clk_state_changed = false;
c6e79dac 8443
566ec9ad 8444 if (list_empty(head))
c6e79dac
SRT		 8445 goto out;
8446
38f3242e
CG		 8447 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8448 if (ret)
8449 return ret;
1e879e8f 8450
c6e79dac
SRT		 8451 list_for_each_entry(clki, head, list) {
8452 if (!IS_ERR_OR_NULL(clki->clk)) {
81309c24
CG		 8453 /*
8454 * Don't disable clocks which are needed
8455 * to keep the link active.
8456 */
8457 if (ufshcd_is_link_active(hba) &&
8458 clki->keep_link_active)
57d104c1
SJ		 8459 continue;
8460
911a0771 8461 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 8462 if (on && !clki->enabled) {
8463 ret = clk_prepare_enable(clki->clk);
8464 if (ret) {
8465 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8466 __func__, clki->name, ret);
8467 goto out;
8468 }
8469 } else if (!on && clki->enabled) {
8470 clk_disable_unprepare(clki->clk);
8471 }
8472 clki->enabled = on;
8473 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8474 clki->name, on ? "en" : "dis");
8475 }
8476 }
1ab27c9c 8477
38f3242e
CG		 8478 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8479 if (ret)
8480 return ret;
1e879e8f 8481
c6e79dac
SRT		 8482out:
8483 if (ret) {
8484 list_for_each_entry(clki, head, list) {
8485 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8486 clk_disable_unprepare(clki->clk);
8487 }
7ff5ab47 8488 } else if (!ret && on) {
1ab27c9c
ST		 8489 spin_lock_irqsave(hba->host->host_lock, flags);
8490 hba->clk_gating.state = CLKS_ON;
7ff5ab47 8491 trace_ufshcd_clk_gating(dev_name(hba->dev),
8492 hba->clk_gating.state);
1ab27c9c 8493 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 8494 }
7ff5ab47 8495
911a0771 8496 if (clk_state_changed)
8497 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8498 (on ? "on" : "off"),
8499 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 8500 return ret;
8501}
8502
8503static int ufshcd_init_clocks(struct ufs_hba *hba)
8504{
8505 int ret = 0;
8506 struct ufs_clk_info *clki;
8507 struct device *dev = hba->dev;
8508 struct list_head *head = &hba->clk_list_head;
8509
566ec9ad 8510 if (list_empty(head))
c6e79dac
SRT		 8511 goto out;
8512
8513 list_for_each_entry(clki, head, list) {
8514 if (!clki->name)
8515 continue;
8516
8517 clki->clk = devm_clk_get(dev, clki->name);
8518 if (IS_ERR(clki->clk)) {
8519 ret = PTR_ERR(clki->clk);
8520 dev_err(dev, "%s: %s clk get failed, %d\n",
8521 __func__, clki->name, ret);
8522 goto out;
8523 }
8524
9e1e8a75
SJ		 8525 /*
8526 * Parse device ref clk freq as per device tree "ref_clk".
8527 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8528 * in ufshcd_alloc_host().
8529 */
8530 if (!strcmp(clki->name, "ref_clk"))
8531 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8532
c6e79dac
SRT		 8533 if (clki->max_freq) {
8534 ret = clk_set_rate(clki->clk, clki->max_freq);
8535 if (ret) {
8536 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8537 __func__, clki->name,
8538 clki->max_freq, ret);
8539 goto out;
8540 }
856b3483 8541 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 8542 }
8543 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8544 clki->name, clk_get_rate(clki->clk));
8545 }
8546out:
8547 return ret;
8548}
8549
5c0c28a8
SRT		 8550static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8551{
8552 int err = 0;
8553
8554 if (!hba->vops)
8555 goto out;
8556
0263bcd0 8557 err = ufshcd_vops_init(hba);
5c0c28a8
SRT		 8558 if (err)
8559 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 8560 __func__, ufshcd_get_var_name(hba), err);
ade921a8 8561out:
5c0c28a8
SRT		 8562 return err;
8563}
8564
8565static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8566{
8567 if (!hba->vops)
8568 return;
8569
0263bcd0 8570 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 8571}
8572
aa497613
SRT		 8573static int ufshcd_hba_init(struct ufs_hba *hba)
8574{
8575 int err;
8576
6a771a65
RS		 8577 /*
8578 * Handle host controller power separately from the UFS device power
8579 * rails as it will help controlling the UFS host controller power
8580 * collapse easily which is different than UFS device power collapse.
8581 * Also, enable the host controller power before we go ahead with rest
8582 * of the initialization here.
8583 */
8584 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 8585 if (err)
8586 goto out;
8587
6a771a65 8588 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 8589 if (err)
8590 goto out;
8591
6a771a65
RS		 8592 err = ufshcd_init_clocks(hba);
8593 if (err)
8594 goto out_disable_hba_vreg;
8595
8596 err = ufshcd_setup_clocks(hba, true);
8597 if (err)
8598 goto out_disable_hba_vreg;
8599
c6e79dac
SRT		 8600 err = ufshcd_init_vreg(hba);
8601 if (err)
8602 goto out_disable_clks;
8603
8604 err = ufshcd_setup_vreg(hba, true);
8605 if (err)
8606 goto out_disable_clks;
8607
aa497613
SRT		 8608 err = ufshcd_variant_hba_init(hba);
8609 if (err)
8610 goto out_disable_vreg;
8611
b6cacaf2
AH		 8612 ufs_debugfs_hba_init(hba);
8613
1d337ec2 8614 hba->is_powered = true;
aa497613
SRT		 8615 goto out;
8616
8617out_disable_vreg:
8618 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 8619out_disable_clks:
8620 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 8621out_disable_hba_vreg:
8622 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 8623out:
8624 return err;
8625}
8626
8627static void ufshcd_hba_exit(struct ufs_hba *hba)
8628{
1d337ec2 8629 if (hba->is_powered) {
4543d9d7
CG		 8630 ufshcd_exit_clk_scaling(hba);
8631 ufshcd_exit_clk_gating(hba);
b6cacaf2 8632 ufs_debugfs_hba_exit(hba);
1d337ec2
SRT		 8633 ufshcd_variant_hba_exit(hba);
8634 ufshcd_setup_vreg(hba, false);
8635 ufshcd_setup_clocks(hba, false);
8636 ufshcd_setup_hba_vreg(hba, false);
8637 hba->is_powered = false;
09750066 8638 ufs_put_device_desc(hba);
1d337ec2 8639 }
aa497613
SRT		 8640}
8641
57d104c1
SJ		 8642/**
8643 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8644 * power mode
8645 * @hba: per adapter instance
8646 * @pwr_mode: device power mode to set
8647 *
8648 * Returns 0 if requested power mode is set successfully
8649 * Returns non-zero if failed to set the requested power mode
8650 */
8651static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8652 enum ufs_dev_pwr_mode pwr_mode)
8653{
8654 unsigned char cmd[6] = { START_STOP };
8655 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 8656 struct scsi_device *sdp;
8657 unsigned long flags;
57d104c1
SJ		 8658 int ret;
8659
7c48bfd0
AM		 8660 spin_lock_irqsave(hba->host->host_lock, flags);
8661 sdp = hba->sdev_ufs_device;
8662 if (sdp) {
8663 ret = scsi_device_get(sdp);
8664 if (!ret && !scsi_device_online(sdp)) {
8665 ret = -ENODEV;
8666 scsi_device_put(sdp);
8667 }
8668 } else {
8669 ret = -ENODEV;
8670 }
8671 spin_unlock_irqrestore(hba->host->host_lock, flags);
8672
8673 if (ret)
8674 return ret;
57d104c1
SJ		 8675
8676 /*
8677 * If scsi commands fail, the scsi mid-layer schedules scsi error-
8678 * handling, which would wait for host to be resumed. Since we know
8679 * we are functional while we are here, skip host resume in error
8680 * handling context.
8681 */
8682 hba->host->eh_noresume = 1;
b294ff3e
AD		 8683 if (hba->wlun_dev_clr_ua)
8684 ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
57d104c1
SJ		 8685
8686 cmd[4] = pwr_mode << 4;
8687
8688 /*
8689 * Current function would be generally called from the power management
e8064021 8690 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 8691 * already suspended childs.
8692 */
fcbfffe2
CH		 8693 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8694 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 8695 if (ret) {
8696 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 8697 "START_STOP failed for power mode: %d, result %x\n",
8698 pwr_mode, ret);
464a00c9 8699 if (ret > 0 && scsi_sense_valid(&sshdr))
21045519 8700 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 8701 }
8702
8703 if (!ret)
8704 hba->curr_dev_pwr_mode = pwr_mode;
1918651f 8705
7c48bfd0 8706 scsi_device_put(sdp);
57d104c1
SJ		 8707 hba->host->eh_noresume = 0;
8708 return ret;
8709}
8710
8711static int ufshcd_link_state_transition(struct ufs_hba *hba,
8712 enum uic_link_state req_link_state,
8713 int check_for_bkops)
8714{
8715 int ret = 0;
8716
8717 if (req_link_state == hba->uic_link_state)
8718 return 0;
8719
8720 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8721 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236 8722 if (!ret) {
57d104c1 8723 ufshcd_set_link_hibern8(hba);
4db7a236
CG		 8724 } else {
8725 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8726 __func__, ret);
57d104c1 8727 goto out;
4db7a236 8728 }
57d104c1
SJ		 8729 }
8730 /*
8731 * If autobkops is enabled, link can't be turned off because
fe1d4c2e
AH		 8732 * turning off the link would also turn off the device, except in the
8733 * case of DeepSleep where the device is expected to remain powered.
57d104c1
SJ		 8734 */
8735 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 8736 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 8737 /*
8738 * Let's make sure that link is in low power mode, we are doing
8739 * this currently by putting the link in Hibern8. Otherway to
8740 * put the link in low power mode is to send the DME end point
8741 * to device and then send the DME reset command to local
8742 * unipro. But putting the link in hibern8 is much faster.
fe1d4c2e
AH		 8743 *
8744 * Note also that putting the link in Hibern8 is a requirement
8745 * for entering DeepSleep.
f3099fbd
YG		 8746 */
8747 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236
CG		 8748 if (ret) {
8749 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8750 __func__, ret);
f3099fbd 8751 goto out;
4db7a236 8752 }
57d104c1
SJ		 8753 /*
8754 * Change controller state to "reset state" which
8755 * should also put the link in off/reset state
8756 */
5cac1095 8757 ufshcd_hba_stop(hba);
57d104c1
SJ		 8758 /*
8759 * TODO: Check if we need any delay to make sure that
8760 * controller is reset
8761 */
8762 ufshcd_set_link_off(hba);
8763 }
8764
8765out:
8766 return ret;
8767}
8768
8769static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8770{
c4df6eed
SC		 8771 bool vcc_off = false;
8772
b799fdf7
YG		 8773 /*
8774 * It seems some UFS devices may keep drawing more than sleep current
8775 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8776 * To avoid this situation, add 2ms delay before putting these UFS
8777 * rails in LPM mode.
8778 */
8779 if (!ufshcd_is_link_active(hba) &&
8780 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8781 usleep_range(2000, 2100);
8782
57d104c1
SJ		 8783 /*
8784 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8785 * power.
8786 *
8787 * If UFS device and link is in OFF state, all power supplies (VCC,
8788 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8789 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8790 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8791 *
8792 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8793 * in low power state which would save some power.
3d17b9b5
AD		 8794 *
8795 * If Write Booster is enabled and the device needs to flush the WB
8796 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 8797 */
8798 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8799 !hba->dev_info.is_lu_power_on_wp) {
8800 ufshcd_setup_vreg(hba, false);
c4df6eed 8801 vcc_off = true;
57d104c1 8802 } else if (!ufshcd_is_ufs_dev_active(hba)) {
51dd905b 8803 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
c4df6eed 8804 vcc_off = true;
23043dd8 8805 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
57d104c1
SJ		 8806 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8807 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8808 }
8809 }
c4df6eed
SC		 8810
8811 /*
8812 * Some UFS devices require delay after VCC power rail is turned-off.
8813 */
8814 if (vcc_off && hba->vreg_info.vcc &&
8815 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8816 usleep_range(5000, 5100);
57d104c1
SJ		 8817}
8818
9bb25e5d 8819#ifdef CONFIG_PM
57d104c1
SJ		 8820static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8821{
8822 int ret = 0;
8823
8824 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8825 !hba->dev_info.is_lu_power_on_wp) {
8826 ret = ufshcd_setup_vreg(hba, true);
8827 } else if (!ufshcd_is_ufs_dev_active(hba)) {
23043dd8 8828 if (!ufshcd_is_link_active(hba)) {
57d104c1
SJ		 8829 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8830 if (ret)
8831 goto vcc_disable;
8832 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8833 if (ret)
8834 goto vccq_lpm;
8835 }
69d72ac8 8836 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 8837 }
8838 goto out;
8839
8840vccq_lpm:
8841 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8842vcc_disable:
8843 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8844out:
8845 return ret;
8846}
9bb25e5d 8847#endif /* CONFIG_PM */
57d104c1
SJ		 8848
8849static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8850{
dd7143e2 8851 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8852 ufshcd_setup_hba_vreg(hba, false);
8853}
8854
8855static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8856{
dd7143e2 8857 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8858 ufshcd_setup_hba_vreg(hba, true);
8859}
8860
b294ff3e 8861static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8862{
57d104c1 8863 int ret = 0;
fe1d4c2e 8864 int check_for_bkops;
57d104c1
SJ		 8865 enum ufs_pm_level pm_lvl;
8866 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8867 enum uic_link_state req_link_state;
8868
b294ff3e 8869 hba->pm_op_in_progress = true;
4c6cb9ed
BVA		 8870 if (pm_op != UFS_SHUTDOWN_PM) {
8871 pm_lvl = pm_op == UFS_RUNTIME_PM ?
57d104c1
SJ		 8872 hba->rpm_lvl : hba->spm_lvl;
8873 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8874 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8875 } else {
8876 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8877 req_link_state = UIC_LINK_OFF_STATE;
8878 }
8879
f02bc975
DP		 8880 ufshpb_suspend(hba);
8881
7a3e97b0 8882 /*
57d104c1
SJ		 8883 * If we can't transition into any of the low power modes
8884 * just gate the clocks.
7a3e97b0 8885 */
1ab27c9c
ST		 8886 ufshcd_hold(hba, false);
8887 hba->clk_gating.is_suspended = true;
8888
348e1bc5
SC		 8889 if (ufshcd_is_clkscaling_supported(hba))
8890 ufshcd_clk_scaling_suspend(hba, true);
d6fcf81a 8891
57d104c1
SJ		 8892 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8893 req_link_state == UIC_LINK_ACTIVE_STATE) {
b294ff3e 8894 goto vops_suspend;
57d104c1 8895 }
7a3e97b0 8896
57d104c1
SJ		 8897 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8898 (req_link_state == hba->uic_link_state))
b294ff3e 8899 goto enable_scaling;
57d104c1
SJ		 8900
8901 /* UFS device & link must be active before we enter in this function */
8902 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8903 ret = -EINVAL;
b294ff3e 8904 goto enable_scaling;
57d104c1
SJ		 8905 }
8906
4c6cb9ed 8907 if (pm_op == UFS_RUNTIME_PM) {
374a246e
SJ		 8908 if (ufshcd_can_autobkops_during_suspend(hba)) {
8909 /*
8910 * The device is idle with no requests in the queue,
8911 * allow background operations if bkops status shows
8912 * that performance might be impacted.
8913 */
8914 ret = ufshcd_urgent_bkops(hba);
8915 if (ret)
b294ff3e 8916 goto enable_scaling;
374a246e
SJ		 8917 } else {
8918 /* make sure that auto bkops is disabled */
8919 ufshcd_disable_auto_bkops(hba);
8920 }
3d17b9b5 8921 /*
51dd905b
SC		 8922 * If device needs to do BKOP or WB buffer flush during
8923 * Hibern8, keep device power mode as "active power mode"
8924 * and VCC supply.
3d17b9b5 8925 */
51dd905b
SC		 8926 hba->dev_info.b_rpm_dev_flush_capable =
8927 hba->auto_bkops_enabled ||
8928 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8929 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8930 ufshcd_is_auto_hibern8_enabled(hba))) &&
8931 ufshcd_wb_need_flush(hba));
8932 }
8933
6948a96a
KK		 8934 flush_work(&hba->eeh_work);
8935
51dd905b 8936 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
4c6cb9ed 8937 if (pm_op != UFS_RUNTIME_PM)
51dd905b
SC		 8938 /* ensure that bkops is disabled */
8939 ufshcd_disable_auto_bkops(hba);
57d104c1 8940
51dd905b
SC		 8941 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8942 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8943 if (ret)
b294ff3e 8944 goto enable_scaling;
51dd905b 8945 }
57d104c1
SJ		 8946 }
8947
fe1d4c2e
AH		 8948 /*
8949 * In the case of DeepSleep, the device is expected to remain powered
8950 * with the link off, so do not check for bkops.
8951 */
8952 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8953 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
57d104c1
SJ		 8954 if (ret)
8955 goto set_dev_active;
8956
b294ff3e 8957vops_suspend:
57d104c1
SJ		 8958 /*
8959 * Call vendor specific suspend callback. As these callbacks may access
8960 * vendor specific host controller register space call them before the
8961 * host clocks are ON.
8962 */
0263bcd0
YG		 8963 ret = ufshcd_vops_suspend(hba, pm_op);
8964 if (ret)
8965 goto set_link_active;
57d104c1
SJ		 8966 goto out;
8967
57d104c1 8968set_link_active:
fe1d4c2e
AH		 8969 /*
8970 * Device hardware reset is required to exit DeepSleep. Also, for
8971 * DeepSleep, the link is off so host reset and restore will be done
8972 * further below.
8973 */
8974 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 8975 ufshcd_device_reset(hba);
fe1d4c2e
AH		 8976 WARN_ON(!ufshcd_is_link_off(hba));
8977 }
57d104c1
SJ		 8978 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8979 ufshcd_set_link_active(hba);
8980 else if (ufshcd_is_link_off(hba))
8981 ufshcd_host_reset_and_restore(hba);
8982set_dev_active:
fe1d4c2e
AH		 8983 /* Can also get here needing to exit DeepSleep */
8984 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 8985 ufshcd_device_reset(hba);
fe1d4c2e
AH		 8986 ufshcd_host_reset_and_restore(hba);
8987 }
57d104c1
SJ		 8988 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8989 ufshcd_disable_auto_bkops(hba);
b294ff3e 8990enable_scaling:
348e1bc5
SC		 8991 if (ufshcd_is_clkscaling_supported(hba))
8992 ufshcd_clk_scaling_suspend(hba, false);
8993
51dd905b 8994 hba->dev_info.b_rpm_dev_flush_capable = false;
57d104c1 8995out:
51dd905b
SC		 8996 if (hba->dev_info.b_rpm_dev_flush_capable) {
8997 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8998 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8999 }
9000
b294ff3e
AD		 9001 if (ret) {
9002 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9003 hba->clk_gating.is_suspended = false;
9004 ufshcd_release(hba);
f02bc975 9005 ufshpb_resume(hba);
b294ff3e
AD		 9006 }
9007 hba->pm_op_in_progress = false;
57d104c1 9008 return ret;
7a3e97b0
SY		 9009}
9010
75d645a6 9011#ifdef CONFIG_PM
b294ff3e 9012static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 9013{
57d104c1 9014 int ret;
b294ff3e 9015 enum uic_link_state old_link_state = hba->uic_link_state;
57d104c1 9016
b294ff3e 9017 hba->pm_op_in_progress = true;
57d104c1 9018
7a3e97b0 9019 /*
57d104c1
SJ		 9020 * Call vendor specific resume callback. As these callbacks may access
9021 * vendor specific host controller register space call them when the
9022 * host clocks are ON.
7a3e97b0 9023 */
0263bcd0
YG		 9024 ret = ufshcd_vops_resume(hba, pm_op);
9025 if (ret)
b294ff3e 9026 goto out;
57d104c1 9027
fe1d4c2e
AH		 9028 /* For DeepSleep, the only supported option is to have the link off */
9029 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9030
57d104c1
SJ		 9031 if (ufshcd_is_link_hibern8(hba)) {
9032 ret = ufshcd_uic_hibern8_exit(hba);
4db7a236 9033 if (!ret) {
57d104c1 9034 ufshcd_set_link_active(hba);
4db7a236
CG		 9035 } else {
9036 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9037 __func__, ret);
57d104c1 9038 goto vendor_suspend;
4db7a236 9039 }
57d104c1 9040 } else if (ufshcd_is_link_off(hba)) {
57d104c1 9041 /*
089f5b64
AD		 9042 * A full initialization of the host and the device is
9043 * required since the link was put to off during suspend.
fe1d4c2e
AH		 9044 * Note, in the case of DeepSleep, the device will exit
9045 * DeepSleep due to device reset.
089f5b64
AD		 9046 */
9047 ret = ufshcd_reset_and_restore(hba);
9048 /*
9049 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 9050 * set the link state as active
9051 */
9052 if (ret || !ufshcd_is_link_active(hba))
9053 goto vendor_suspend;
9054 }
9055
9056 if (!ufshcd_is_ufs_dev_active(hba)) {
9057 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9058 if (ret)
9059 goto set_old_link_state;
9060 }
9061
4e768e76 9062 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9063 ufshcd_enable_auto_bkops(hba);
9064 else
9065 /*
9066 * If BKOPs operations are urgently needed at this moment then
9067 * keep auto-bkops enabled or else disable it.
9068 */
9069 ufshcd_urgent_bkops(hba);
9070
cd469475
AH		 9071 if (hba->ee_usr_mask)
9072 ufshcd_write_ee_control(hba);
9073
348e1bc5
SC		 9074 if (ufshcd_is_clkscaling_supported(hba))
9075 ufshcd_clk_scaling_suspend(hba, false);
856b3483 9076
51dd905b
SC		 9077 if (hba->dev_info.b_rpm_dev_flush_capable) {
9078 hba->dev_info.b_rpm_dev_flush_capable = false;
9079 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9080 }
9081
b294ff3e
AD		 9082 /* Enable Auto-Hibernate if configured */
9083 ufshcd_auto_hibern8_enable(hba);
f02bc975
DP		 9084
9085 ufshpb_resume(hba);
57d104c1
SJ		 9086 goto out;
9087
9088set_old_link_state:
9089 ufshcd_link_state_transition(hba, old_link_state, 0);
9090vendor_suspend:
0263bcd0 9091 ufshcd_vops_suspend(hba, pm_op);
b294ff3e
AD		 9092out:
9093 if (ret)
9094 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9095 hba->clk_gating.is_suspended = false;
9096 ufshcd_release(hba);
9097 hba->pm_op_in_progress = false;
9098 return ret;
9099}
9100
9101static int ufshcd_wl_runtime_suspend(struct device *dev)
9102{
9103 struct scsi_device *sdev = to_scsi_device(dev);
9104 struct ufs_hba *hba;
9105 int ret;
9106 ktime_t start = ktime_get();
9107
9108 hba = shost_priv(sdev->host);
9109
9110 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9111 if (ret)
9112 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9113
9114 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9115 ktime_to_us(ktime_sub(ktime_get(), start)),
9116 hba->curr_dev_pwr_mode, hba->uic_link_state);
9117
9118 return ret;
9119}
9120
9121static int ufshcd_wl_runtime_resume(struct device *dev)
9122{
9123 struct scsi_device *sdev = to_scsi_device(dev);
9124 struct ufs_hba *hba;
9125 int ret = 0;
9126 ktime_t start = ktime_get();
9127
9128 hba = shost_priv(sdev->host);
9129
9130 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9131 if (ret)
9132 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9133
9134 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9135 ktime_to_us(ktime_sub(ktime_get(), start)),
9136 hba->curr_dev_pwr_mode, hba->uic_link_state);
9137
9138 return ret;
9139}
75d645a6 9140#endif
b294ff3e
AD		 9141
9142#ifdef CONFIG_PM_SLEEP
9143static int ufshcd_wl_suspend(struct device *dev)
9144{
9145 struct scsi_device *sdev = to_scsi_device(dev);
9146 struct ufs_hba *hba;
9147 int ret = 0;
9148 ktime_t start = ktime_get();
9149
9150 hba = shost_priv(sdev->host);
9151 down(&hba->host_sem);
9152
9153 if (pm_runtime_suspended(dev))
9154 goto out;
9155
9156 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9157 if (ret) {
9158 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9159 up(&hba->host_sem);
9160 }
9161
9162out:
9163 if (!ret)
9164 hba->is_sys_suspended = true;
9165 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9166 ktime_to_us(ktime_sub(ktime_get(), start)),
9167 hba->curr_dev_pwr_mode, hba->uic_link_state);
9168
9169 return ret;
9170}
9171
9172static int ufshcd_wl_resume(struct device *dev)
9173{
9174 struct scsi_device *sdev = to_scsi_device(dev);
9175 struct ufs_hba *hba;
9176 int ret = 0;
9177 ktime_t start = ktime_get();
9178
9179 hba = shost_priv(sdev->host);
9180
9181 if (pm_runtime_suspended(dev))
9182 goto out;
9183
9184 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9185 if (ret)
9186 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9187out:
9188 trace_ufshcd_wl_resume(dev_name(dev), ret,
9189 ktime_to_us(ktime_sub(ktime_get(), start)),
9190 hba->curr_dev_pwr_mode, hba->uic_link_state);
9191 if (!ret)
9192 hba->is_sys_suspended = false;
9193 up(&hba->host_sem);
9194 return ret;
9195}
9196#endif
9197
9198static void ufshcd_wl_shutdown(struct device *dev)
9199{
9200 struct scsi_device *sdev = to_scsi_device(dev);
9201 struct ufs_hba *hba;
9202
9203 hba = shost_priv(sdev->host);
9204
9205 down(&hba->host_sem);
9206 hba->shutting_down = true;
9207 up(&hba->host_sem);
9208
9209 /* Turn on everything while shutting down */
9210 ufshcd_rpm_get_sync(hba);
9211 scsi_device_quiesce(sdev);
9212 shost_for_each_device(sdev, hba->host) {
9213 if (sdev == hba->sdev_ufs_device)
9214 continue;
9215 scsi_device_quiesce(sdev);
9216 }
9217 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9218}
9219
9220/**
9221 * ufshcd_suspend - helper function for suspend operations
9222 * @hba: per adapter instance
9223 *
9224 * This function will put disable irqs, turn off clocks
9225 * and set vreg and hba-vreg in lpm mode.
b294ff3e
AD		 9226 */
9227static int ufshcd_suspend(struct ufs_hba *hba)
9228{
9229 int ret;
9230
9231 if (!hba->is_powered)
9232 return 0;
9233 /*
9234 * Disable the host irq as host controller as there won't be any
9235 * host controller transaction expected till resume.
9236 */
57d104c1 9237 ufshcd_disable_irq(hba);
b294ff3e
AD		 9238 ret = ufshcd_setup_clocks(hba, false);
9239 if (ret) {
9240 ufshcd_enable_irq(hba);
9241 return ret;
9242 }
2dec9475
CG		 9243 if (ufshcd_is_clkgating_allowed(hba)) {
9244 hba->clk_gating.state = CLKS_OFF;
9245 trace_ufshcd_clk_gating(dev_name(hba->dev),
9246 hba->clk_gating.state);
9247 }
b294ff3e
AD		 9248
9249 ufshcd_vreg_set_lpm(hba);
9250 /* Put the host controller in low power mode if possible */
9251 ufshcd_hba_vreg_set_lpm(hba);
9252 return ret;
9253}
9254
9bb25e5d 9255#ifdef CONFIG_PM
b294ff3e
AD		 9256/**
9257 * ufshcd_resume - helper function for resume operations
9258 * @hba: per adapter instance
9259 *
9260 * This function basically turns on the regulators, clocks and
9261 * irqs of the hba.
b294ff3e
AD		 9262 *
9263 * Returns 0 for success and non-zero for failure
9264 */
9265static int ufshcd_resume(struct ufs_hba *hba)
9266{
9267 int ret;
9268
9269 if (!hba->is_powered)
9270 return 0;
9271
9272 ufshcd_hba_vreg_set_hpm(hba);
9273 ret = ufshcd_vreg_set_hpm(hba);
9274 if (ret)
9275 goto out;
9276
9277 /* Make sure clocks are enabled before accessing controller */
9278 ret = ufshcd_setup_clocks(hba, true);
9279 if (ret)
9280 goto disable_vreg;
9281
9282 /* enable the host irq as host controller would be active soon */
9283 ufshcd_enable_irq(hba);
9284 goto out;
9285
528db9e5
ZC		 9286disable_vreg:
9287 ufshcd_vreg_set_lpm(hba);
57d104c1 9288out:
8808b4e9 9289 if (ret)
e965e5e0 9290 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
57d104c1
SJ		 9291 return ret;
9292}
9bb25e5d 9293#endif /* CONFIG_PM */
57d104c1 9294
9bb25e5d 9295#ifdef CONFIG_PM_SLEEP
57d104c1 9296/**
f1ecbe1e
BVA		 9297 * ufshcd_system_suspend - system suspend callback
9298 * @dev: Device associated with the UFS controller.
57d104c1 9299 *
f1ecbe1e
BVA		 9300 * Executed before putting the system into a sleep state in which the contents
9301 * of main memory are preserved.
57d104c1
SJ		 9302 *
9303 * Returns 0 for success and non-zero for failure
9304 */
f1ecbe1e 9305int ufshcd_system_suspend(struct device *dev)
57d104c1 9306{
f1ecbe1e 9307 struct ufs_hba *hba = dev_get_drvdata(dev);
57d104c1 9308 int ret = 0;
7ff5ab47 9309 ktime_t start = ktime_get();
57d104c1 9310
b294ff3e 9311 if (pm_runtime_suspended(hba->dev))
0b257734 9312 goto out;
57d104c1 9313
b294ff3e 9314 ret = ufshcd_suspend(hba);
57d104c1 9315out:
7ff5ab47 9316 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9317 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9318 hba->curr_dev_pwr_mode, hba->uic_link_state);
57d104c1
SJ		 9319 return ret;
9320}
9321EXPORT_SYMBOL(ufshcd_system_suspend);
9322
9323/**
f1ecbe1e
BVA		 9324 * ufshcd_system_resume - system resume callback
9325 * @dev: Device associated with the UFS controller.
9326 *
9327 * Executed after waking the system up from a sleep state in which the contents
9328 * of main memory were preserved.
57d104c1
SJ		 9329 *
9330 * Returns 0 for success and non-zero for failure
9331 */
f1ecbe1e 9332int ufshcd_system_resume(struct device *dev)
57d104c1 9333{
f1ecbe1e 9334 struct ufs_hba *hba = dev_get_drvdata(dev);
7ff5ab47 9335 ktime_t start = ktime_get();
f1ecbe1e 9336 int ret = 0;
7ff5ab47 9337
b294ff3e 9338 if (pm_runtime_suspended(hba->dev))
7ff5ab47 9339 goto out;
b294ff3e
AD		 9340
9341 ret = ufshcd_resume(hba);
9342
7ff5ab47 9343out:
9344 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9345 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9346 hba->curr_dev_pwr_mode, hba->uic_link_state);
b294ff3e 9347
7ff5ab47 9348 return ret;
7a3e97b0 9349}
57d104c1 9350EXPORT_SYMBOL(ufshcd_system_resume);
9bb25e5d 9351#endif /* CONFIG_PM_SLEEP */
3b1d0580 9352
9bb25e5d 9353#ifdef CONFIG_PM
57d104c1 9354/**
f1ecbe1e
BVA		 9355 * ufshcd_runtime_suspend - runtime suspend callback
9356 * @dev: Device associated with the UFS controller.
57d104c1
SJ		 9357 *
9358 * Check the description of ufshcd_suspend() function for more details.
9359 *
9360 * Returns 0 for success and non-zero for failure
9361 */
f1ecbe1e 9362int ufshcd_runtime_suspend(struct device *dev)
66ec6d59 9363{
f1ecbe1e 9364 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9365 int ret;
7ff5ab47 9366 ktime_t start = ktime_get();
9367
b294ff3e
AD		 9368 ret = ufshcd_suspend(hba);
9369
7ff5ab47 9370 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9371 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9372 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9373 return ret;
66ec6d59
SRT		 9374}
9375EXPORT_SYMBOL(ufshcd_runtime_suspend);
9376
57d104c1
SJ		 9377/**
9378 * ufshcd_runtime_resume - runtime resume routine
f1ecbe1e 9379 * @dev: Device associated with the UFS controller.
57d104c1 9380 *
b294ff3e 9381 * This function basically brings controller
57d104c1
SJ		 9382 * to active state. Following operations are done in this function:
9383 *
9384 * 1. Turn on all the controller related clocks
b294ff3e 9385 * 2. Turn ON VCC rail
57d104c1 9386 */
f1ecbe1e 9387int ufshcd_runtime_resume(struct device *dev)
66ec6d59 9388{
f1ecbe1e 9389 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9390 int ret;
7ff5ab47 9391 ktime_t start = ktime_get();
9392
b294ff3e
AD		 9393 ret = ufshcd_resume(hba);
9394
7ff5ab47 9395 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9396 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9397 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9398 return ret;
66ec6d59
SRT		 9399}
9400EXPORT_SYMBOL(ufshcd_runtime_resume);
9bb25e5d 9401#endif /* CONFIG_PM */
66ec6d59 9402
57d104c1
SJ		 9403/**
9404 * ufshcd_shutdown - shutdown routine
9405 * @hba: per adapter instance
9406 *
b294ff3e
AD		 9407 * This function would turn off both UFS device and UFS hba
9408 * regulators. It would also disable clocks.
57d104c1
SJ		 9409 *
9410 * Returns 0 always to allow force shutdown even in case of errors.
9411 */
9412int ufshcd_shutdown(struct ufs_hba *hba)
9413{
57d104c1
SJ		 9414 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9415 goto out;
9416
e92643db 9417 pm_runtime_get_sync(hba->dev);
57d104c1 9418
b294ff3e 9419 ufshcd_suspend(hba);
57d104c1 9420out:
88a92d6a 9421 hba->is_powered = false;
57d104c1
SJ		 9422 /* allow force shutdown even in case of errors */
9423 return 0;
9424}
9425EXPORT_SYMBOL(ufshcd_shutdown);
9426
7a3e97b0 9427/**
3b1d0580 9428 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 9429 * data structure memory
8aa29f19 9430 * @hba: per adapter instance
7a3e97b0 9431 */
3b1d0580 9432void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 9433{
b294ff3e
AD		 9434 if (hba->sdev_ufs_device)
9435 ufshcd_rpm_get_sync(hba);
e88e2d32 9436 ufs_hwmon_remove(hba);
df032bf2 9437 ufs_bsg_remove(hba);
4b5f4907 9438 ufshpb_remove(hba);
cbb6813e 9439 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 9440 blk_cleanup_queue(hba->tmf_queue);
9441 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360 9442 blk_cleanup_queue(hba->cmd_queue);
cfdf9c91 9443 scsi_remove_host(hba->host);
7a3e97b0 9444 /* disable interrupts */
2fbd009b 9445 ufshcd_disable_intr(hba, hba->intr_mask);
5cac1095 9446 ufshcd_hba_stop(hba);
aa497613 9447 ufshcd_hba_exit(hba);
3b1d0580
VH		 9448}
9449EXPORT_SYMBOL_GPL(ufshcd_remove);
9450
47555a5c
YG		 9451/**
9452 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9453 * @hba: pointer to Host Bus Adapter (HBA)
9454 */
9455void ufshcd_dealloc_host(struct ufs_hba *hba)
9456{
9457 scsi_host_put(hba->host);
9458}
9459EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9460
ca3d7bf9
AM		 9461/**
9462 * ufshcd_set_dma_mask - Set dma mask based on the controller
9463 * addressing capability
9464 * @hba: per adapter instance
9465 *
9466 * Returns 0 for success, non-zero for failure
9467 */
9468static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9469{
9470 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9471 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9472 return 0;
9473 }
9474 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9475}
9476
a113eaaf
BVA		 9477static struct scsi_transport_template ufshcd_transport_template = {
9478 .eh_strategy_handler = ufshcd_err_handler,
9479};
9480
7a3e97b0 9481/**
5c0c28a8 9482 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 9483 * @dev: pointer to device handle
9484 * @hba_handle: driver private handle
7a3e97b0
SY		 9485 * Returns 0 on success, non-zero value on failure
9486 */
5c0c28a8 9487int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 9488{
9489 struct Scsi_Host *host;
9490 struct ufs_hba *hba;
5c0c28a8 9491 int err = 0;
7a3e97b0 9492
3b1d0580
VH		 9493 if (!dev) {
9494 dev_err(dev,
9495 "Invalid memory reference for dev is NULL\n");
9496 err = -ENODEV;
7a3e97b0
SY		 9497 goto out_error;
9498 }
9499
7a3e97b0
SY		 9500 host = scsi_host_alloc(&ufshcd_driver_template,
9501 sizeof(struct ufs_hba));
9502 if (!host) {
3b1d0580 9503 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 9504 err = -ENOMEM;
3b1d0580 9505 goto out_error;
7a3e97b0 9506 }
a113eaaf 9507 host->transportt = &ufshcd_transport_template;
7a3e97b0 9508 hba = shost_priv(host);
7a3e97b0 9509 hba->host = host;
3b1d0580 9510 hba->dev = dev;
9e1e8a75 9511 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
566ec9ad 9512 INIT_LIST_HEAD(&hba->clk_list_head);
169f5eb2
BVA		 9513 spin_lock_init(&hba->outstanding_lock);
9514
9515 *hba_handle = hba;
566ec9ad 9516
5c0c28a8
SRT		 9517out_error:
9518 return err;
9519}
9520EXPORT_SYMBOL(ufshcd_alloc_host);
9521
69a6c269
BVA		 9522/* This function exists because blk_mq_alloc_tag_set() requires this. */
9523static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9524 const struct blk_mq_queue_data *qd)
9525{
9526 WARN_ON_ONCE(true);
9527 return BLK_STS_NOTSUPP;
9528}
9529
9530static const struct blk_mq_ops ufshcd_tmf_ops = {
9531 .queue_rq = ufshcd_queue_tmf,
9532};
9533
5c0c28a8
SRT		 9534/**
9535 * ufshcd_init - Driver initialization routine
9536 * @hba: per-adapter instance
9537 * @mmio_base: base register address
9538 * @irq: Interrupt line of device
9539 * Returns 0 on success, non-zero value on failure
9540 */
9541int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9542{
9543 int err;
9544 struct Scsi_Host *host = hba->host;
9545 struct device *dev = hba->dev;
9546
9547 if (!mmio_base) {
9548 dev_err(hba->dev,
9549 "Invalid memory reference for mmio_base is NULL\n");
9550 err = -ENODEV;
9551 goto out_error;
9552 }
9553
3b1d0580
VH		 9554 hba->mmio_base = mmio_base;
9555 hba->irq = irq;
90b8491c 9556 hba->vps = &ufs_hba_vps;
7a3e97b0 9557
aa497613 9558 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 9559 if (err)
9560 goto out_error;
9561
7a3e97b0 9562 /* Read capabilities registers */
df043c74
ST		 9563 err = ufshcd_hba_capabilities(hba);
9564 if (err)
9565 goto out_disable;
7a3e97b0
SY		 9566
9567 /* Get UFS version supported by the controller */
9568 hba->ufs_version = ufshcd_get_ufs_version(hba);
9569
2fbd009b
SJ		 9570 /* Get Interrupt bit mask per version */
9571 hba->intr_mask = ufshcd_get_intr_mask(hba);
9572
ca3d7bf9
AM		 9573 err = ufshcd_set_dma_mask(hba);
9574 if (err) {
9575 dev_err(hba->dev, "set dma mask failed\n");
9576 goto out_disable;
9577 }
9578
7a3e97b0
SY		 9579 /* Allocate memory for host memory space */
9580 err = ufshcd_memory_alloc(hba);
9581 if (err) {
3b1d0580
VH		 9582 dev_err(hba->dev, "Memory allocation failed\n");
9583 goto out_disable;
7a3e97b0
SY		 9584 }
9585
9586 /* Configure LRB */
9587 ufshcd_host_memory_configure(hba);
9588
9589 host->can_queue = hba->nutrs;
9590 host->cmd_per_lun = hba->nutrs;
9591 host->max_id = UFSHCD_MAX_ID;
0ce147d4 9592 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 9593 host->max_channel = UFSHCD_MAX_CHANNEL;
9594 host->unique_id = host->host_no;
a851b2bd 9595 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 9596
7eb584db
DR		 9597 hba->max_pwr_info.is_valid = false;
9598
66ec6d59 9599 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 9600
9cd20d3f 9601 sema_init(&hba->host_sem, 1);
88a92d6a 9602
6ccf44fe
SJ		 9603 /* Initialize UIC command mutex */
9604 mutex_init(&hba->uic_cmd_mutex);
9605
5a0b0cb9
SRT		 9606 /* Initialize mutex for device management commands */
9607 mutex_init(&hba->dev_cmd.lock);
9608
cd469475
AH		 9609 /* Initialize mutex for exception event control */
9610 mutex_init(&hba->ee_ctrl_mutex);
9611
a3cd5ec5 9612 init_rwsem(&hba->clk_scaling_lock);
9613
1ab27c9c 9614 ufshcd_init_clk_gating(hba);
199ef13c 9615
eebcc196
VG		 9616 ufshcd_init_clk_scaling(hba);
9617
199ef13c
YG		 9618 /*
9619 * In order to avoid any spurious interrupt immediately after
9620 * registering UFS controller interrupt handler, clear any pending UFS
9621 * interrupt status and disable all the UFS interrupts.
9622 */
9623 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9624 REG_INTERRUPT_STATUS);
9625 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9626 /*
9627 * Make sure that UFS interrupts are disabled and any pending interrupt
9628 * status is cleared before registering UFS interrupt handler.
9629 */
9630 mb();
9631
7a3e97b0 9632 /* IRQ registration */
2953f850 9633 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 9634 if (err) {
3b1d0580 9635 dev_err(hba->dev, "request irq failed\n");
4543d9d7 9636 goto out_disable;
57d104c1
SJ		 9637 } else {
9638 hba->is_irq_enabled = true;
7a3e97b0
SY		 9639 }
9640
3b1d0580 9641 err = scsi_add_host(host, hba->dev);
7a3e97b0 9642 if (err) {
3b1d0580 9643 dev_err(hba->dev, "scsi_add_host failed\n");
4543d9d7 9644 goto out_disable;
7a3e97b0
SY		 9645 }
9646
7252a360
BVA		 9647 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9648 if (IS_ERR(hba->cmd_queue)) {
9649 err = PTR_ERR(hba->cmd_queue);
9650 goto out_remove_scsi_host;
9651 }
9652
69a6c269
BVA		 9653 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9654 .nr_hw_queues = 1,
9655 .queue_depth = hba->nutmrs,
9656 .ops = &ufshcd_tmf_ops,
9657 .flags = BLK_MQ_F_NO_SCHED,
9658 };
9659 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9660 if (err < 0)
9661 goto free_cmd_queue;
9662 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9663 if (IS_ERR(hba->tmf_queue)) {
9664 err = PTR_ERR(hba->tmf_queue);
9665 goto free_tmf_tag_set;
9666 }
9667
d8d9f793 9668 /* Reset the attached device */
31a5d9ca 9669 ufshcd_device_reset(hba);
d8d9f793 9670
df043c74
ST		 9671 ufshcd_init_crypto(hba);
9672
6ccf44fe
SJ		 9673 /* Host controller enable */
9674 err = ufshcd_hba_enable(hba);
7a3e97b0 9675 if (err) {
6ccf44fe 9676 dev_err(hba->dev, "Host controller enable failed\n");
e965e5e0 9677 ufshcd_print_evt_hist(hba);
6ba65588 9678 ufshcd_print_host_state(hba);
69a6c269 9679 goto free_tmf_queue;
7a3e97b0 9680 }
6ccf44fe 9681
0c8f7586 9682 /*
9683 * Set the default power management level for runtime and system PM.
9684 * Default power saving mode is to keep UFS link in Hibern8 state
9685 * and UFS device in sleep state.
9686 */
9687 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9688 UFS_SLEEP_PWR_MODE,
9689 UIC_LINK_HIBERN8_STATE);
9690 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9691 UFS_SLEEP_PWR_MODE,
9692 UIC_LINK_HIBERN8_STATE);
9693
51dd905b
SC		 9694 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9695 ufshcd_rpm_dev_flush_recheck_work);
9696
ad448378 9697 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 9698 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 9699 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9700 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9701 }
9702
62694735
SRT		 9703 /* Hold auto suspend until async scan completes */
9704 pm_runtime_get_sync(dev);
38135535 9705 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 9706 /*
7caf489b 9707 * We are assuming that device wasn't put in sleep/power-down
9708 * state exclusively during the boot stage before kernel.
9709 * This assumption helps avoid doing link startup twice during
9710 * ufshcd_probe_hba().
57d104c1 9711 */
7caf489b 9712 ufshcd_set_ufs_dev_active(hba);
57d104c1 9713
6ccf44fe 9714 async_schedule(ufshcd_async_scan, hba);
cbb6813e 9715 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 9716
1084514c 9717 device_enable_async_suspend(dev);
7a3e97b0
SY		 9718 return 0;
9719
69a6c269
BVA		 9720free_tmf_queue:
9721 blk_cleanup_queue(hba->tmf_queue);
9722free_tmf_tag_set:
9723 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360
BVA		 9724free_cmd_queue:
9725 blk_cleanup_queue(hba->cmd_queue);
3b1d0580
VH		 9726out_remove_scsi_host:
9727 scsi_remove_host(hba->host);
3b1d0580 9728out_disable:
57d104c1 9729 hba->is_irq_enabled = false;
aa497613 9730 ufshcd_hba_exit(hba);
3b1d0580
VH		 9731out_error:
9732 return err;
9733}
9734EXPORT_SYMBOL_GPL(ufshcd_init);
9735
b294ff3e
AD		 9736void ufshcd_resume_complete(struct device *dev)
9737{
9738 struct ufs_hba *hba = dev_get_drvdata(dev);
9739
9740 if (hba->complete_put) {
9741 ufshcd_rpm_put(hba);
9742 hba->complete_put = false;
9743 }
9744 if (hba->rpmb_complete_put) {
9745 ufshcd_rpmb_rpm_put(hba);
9746 hba->rpmb_complete_put = false;
9747 }
9748}
9749EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9750
9751int ufshcd_suspend_prepare(struct device *dev)
9752{
9753 struct ufs_hba *hba = dev_get_drvdata(dev);
9754 int ret;
9755
9756 /*
9757 * SCSI assumes that runtime-pm and system-pm for scsi drivers
9758 * are same. And it doesn't wake up the device for system-suspend
9759 * if it's runtime suspended. But ufs doesn't follow that.
9760 * Refer ufshcd_resume_complete()
9761 */
9762 if (hba->sdev_ufs_device) {
9763 ret = ufshcd_rpm_get_sync(hba);
9764 if (ret < 0 && ret != -EACCES) {
9765 ufshcd_rpm_put(hba);
9766 return ret;
9767 }
9768 hba->complete_put = true;
9769 }
9770 if (hba->sdev_rpmb) {
9771 ufshcd_rpmb_rpm_get_sync(hba);
9772 hba->rpmb_complete_put = true;
9773 }
9774 return 0;
9775}
9776EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9777
9778#ifdef CONFIG_PM_SLEEP
9779static int ufshcd_wl_poweroff(struct device *dev)
9780{
9781 struct scsi_device *sdev = to_scsi_device(dev);
9782 struct ufs_hba *hba = shost_priv(sdev->host);
9783
9784 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9785 return 0;
9786}
9787#endif
9788
9789static int ufshcd_wl_probe(struct device *dev)
9790{
9791 struct scsi_device *sdev = to_scsi_device(dev);
9792
9793 if (!is_device_wlun(sdev))
9794 return -ENODEV;
9795
9796 blk_pm_runtime_init(sdev->request_queue, dev);
9797 pm_runtime_set_autosuspend_delay(dev, 0);
9798 pm_runtime_allow(dev);
9799
9800 return 0;
9801}
9802
9803static int ufshcd_wl_remove(struct device *dev)
9804{
9805 pm_runtime_forbid(dev);
9806 return 0;
9807}
9808
9809static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9810#ifdef CONFIG_PM_SLEEP
9811 .suspend = ufshcd_wl_suspend,
9812 .resume = ufshcd_wl_resume,
9813 .freeze = ufshcd_wl_suspend,
9814 .thaw = ufshcd_wl_resume,
9815 .poweroff = ufshcd_wl_poweroff,
9816 .restore = ufshcd_wl_resume,
9817#endif
9818 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9819};
9820
9821/*
9822 * ufs_dev_wlun_template - describes ufs device wlun
9823 * ufs-device wlun - used to send pm commands
9824 * All luns are consumers of ufs-device wlun.
9825 *
9826 * Currently, no sd driver is present for wluns.
9827 * Hence the no specific pm operations are performed.
9828 * With ufs design, SSU should be sent to ufs-device wlun.
9829 * Hence register a scsi driver for ufs wluns only.
9830 */
9831static struct scsi_driver ufs_dev_wlun_template = {
9832 .gendrv = {
9833 .name = "ufs_device_wlun",
9834 .owner = THIS_MODULE,
9835 .probe = ufshcd_wl_probe,
9836 .remove = ufshcd_wl_remove,
9837 .pm = &ufshcd_wl_pm_ops,
9838 .shutdown = ufshcd_wl_shutdown,
9839 },
9840};
9841
9842static int ufshcd_rpmb_probe(struct device *dev)
9843{
9844 return is_rpmb_wlun(to_scsi_device(dev)) ? 0 : -ENODEV;
9845}
9846
9847static inline int ufshcd_clear_rpmb_uac(struct ufs_hba *hba)
9848{
9849 int ret = 0;
9850
9851 if (!hba->wlun_rpmb_clr_ua)
9852 return 0;
9853 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
9854 if (!ret)
9855 hba->wlun_rpmb_clr_ua = 0;
9856 return ret;
9857}
9858
75d645a6 9859#ifdef CONFIG_PM
b294ff3e
AD		 9860static int ufshcd_rpmb_resume(struct device *dev)
9861{
9862 struct ufs_hba *hba = wlun_dev_to_hba(dev);
9863
9864 if (hba->sdev_rpmb)
9865 ufshcd_clear_rpmb_uac(hba);
9866 return 0;
9867}
75d645a6 9868#endif
b294ff3e
AD		 9869
9870static const struct dev_pm_ops ufs_rpmb_pm_ops = {
9871 SET_RUNTIME_PM_OPS(NULL, ufshcd_rpmb_resume, NULL)
9872 SET_SYSTEM_SLEEP_PM_OPS(NULL, ufshcd_rpmb_resume)
9873};
9874
f6b41429 9875/* ufs_rpmb_wlun_template - Describes UFS RPMB WLUN. Used only to send UAC. */
b294ff3e
AD		 9876static struct scsi_driver ufs_rpmb_wlun_template = {
9877 .gendrv = {
9878 .name = "ufs_rpmb_wlun",
9879 .owner = THIS_MODULE,
9880 .probe = ufshcd_rpmb_probe,
9881 .pm = &ufs_rpmb_pm_ops,
9882 },
9883};
9884
b6cacaf2
AH		 9885static int __init ufshcd_core_init(void)
9886{
b294ff3e
AD		 9887 int ret;
9888
b6cacaf2 9889 ufs_debugfs_init();
b294ff3e
AD		 9890
9891 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9892 if (ret)
9893 goto debugfs_exit;
9894
9895 ret = scsi_register_driver(&ufs_rpmb_wlun_template.gendrv);
9896 if (ret)
9897 goto unregister;
9898
9899 return ret;
9900unregister:
9901 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9902debugfs_exit:
9903 ufs_debugfs_exit();
9904 return ret;
b6cacaf2
AH		 9905}
9906
9907static void __exit ufshcd_core_exit(void)
9908{
9909 ufs_debugfs_exit();
b294ff3e
AD		 9910 scsi_unregister_driver(&ufs_rpmb_wlun_template.gendrv);
9911 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
b6cacaf2
AH		 9912}
9913
9914module_init(ufshcd_core_init);
9915module_exit(ufshcd_core_exit);
9916
3b1d0580
VH		 9917MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9918MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 9919MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 9920MODULE_LICENSE("GPL");
9921MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)