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scsi: ufs: fix setting init power mode
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
7ff5ab47 48#define CREATE_TRACE_POINTS
49#include <trace/events/ufs.h>
50
dcea0bfb
GB		 51#define UFSHCD_REQ_SENSE_SIZE 18
52
2fbd009b
SJ		 53#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
54 UTP_TASK_REQ_COMPL |\
55 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 56/* UIC command timeout, unit: ms */
57#define UIC_CMD_TIMEOUT 500
2fbd009b 58
5a0b0cb9
SRT		 59/* NOP OUT retries waiting for NOP IN response */
60#define NOP_OUT_RETRIES 10
61/* Timeout after 30 msecs if NOP OUT hangs without response */
62#define NOP_OUT_TIMEOUT 30 /* msecs */
63
68078d5c 64/* Query request retries */
10fe5888 65#define QUERY_REQ_RETRIES 3
68078d5c 66/* Query request timeout */
10fe5888 67#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 68
e2933132
SRT		 69/* Task management command timeout */
70#define TM_CMD_TIMEOUT 100 /* msecs */
71
64238fbd
YG		 72/* maximum number of retries for a general UIC command */
73#define UFS_UIC_COMMAND_RETRIES 3
74
1d337ec2
SRT		 75/* maximum number of link-startup retries */
76#define DME_LINKSTARTUP_RETRIES 3
77
87d0b4a6
YG		 78/* Maximum retries for Hibern8 enter */
79#define UIC_HIBERN8_ENTER_RETRIES 3
80
1d337ec2
SRT		 81/* maximum number of reset retries before giving up */
82#define MAX_HOST_RESET_RETRIES 5
83
68078d5c
DR		 84/* Expose the flag value from utp_upiu_query.value */
85#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
86
7d568652
SJ		 87/* Interrupt aggregation default timeout, unit: 40us */
88#define INT_AGGR_DEF_TO 0x02
89
aa497613
SRT		 90#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
91 ({ \
92 int _ret; \
93 if (_on) \
94 _ret = ufshcd_enable_vreg(_dev, _vreg); \
95 else \
96 _ret = ufshcd_disable_vreg(_dev, _vreg); \
97 _ret; \
98 })
99
66cc820f
DR		 100#define ufshcd_hex_dump(prefix_str, buf, len) \
101print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
102
da461cec
SJ		 103static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 111 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114};
115
7a3e97b0
SY		 116enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121};
122
123/* UFSHCD states */
124enum {
7a3e97b0
SY		 125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
3441da7d 127 UFSHCD_STATE_OPERATIONAL,
141f8165 128 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 129};
130
131/* UFSHCD error handling flags */
132enum {
133 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 134};
135
e8e7f271
SRT		 136/* UFSHCD UIC layer error flags */
137enum {
138 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 139 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
140 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
141 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
142 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
143 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 144};
145
7a3e97b0
SY		 146/* Interrupt configuration options */
147enum {
148 UFSHCD_INT_DISABLE,
149 UFSHCD_INT_ENABLE,
150 UFSHCD_INT_CLEAR,
151};
152
3441da7d
SRT		 153#define ufshcd_set_eh_in_progress(h) \
154 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
155#define ufshcd_eh_in_progress(h) \
156 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
157#define ufshcd_clear_eh_in_progress(h) \
158 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
159
57d104c1
SJ		 160#define ufshcd_set_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
162#define ufshcd_set_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
164#define ufshcd_set_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
166#define ufshcd_is_ufs_dev_active(h) \
167 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
168#define ufshcd_is_ufs_dev_sleep(h) \
169 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
170#define ufshcd_is_ufs_dev_poweroff(h) \
171 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
172
173static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
175 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
177 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
180};
181
182static inline enum ufs_dev_pwr_mode
183ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].dev_state;
186}
187
188static inline enum uic_link_state
189ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
190{
191 return ufs_pm_lvl_states[lvl].link_state;
192}
193
0c8f7586 194static inline enum ufs_pm_level
195ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
196 enum uic_link_state link_state)
197{
198 enum ufs_pm_level lvl;
199
200 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
201 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
202 (ufs_pm_lvl_states[lvl].link_state == link_state))
203 return lvl;
204 }
205
206 /* if no match found, return the level 0 */
207 return UFS_PM_LVL_0;
208}
209
56d4a186
SJ		 210static struct ufs_dev_fix ufs_fixups[] = {
211 /* UFS cards deviations table */
212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
214 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
218 UFS_DEVICE_NO_FASTAUTO),
219 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
220 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
221 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
222 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
223 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
224 UFS_DEVICE_QUIRK_PA_TACTIVATE),
225 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
226 UFS_DEVICE_QUIRK_PA_TACTIVATE),
227 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
228 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
230
231 END_FIX
232};
233
3441da7d
SRT		 234static void ufshcd_tmc_handler(struct ufs_hba *hba);
235static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 236static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 237static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 238static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 239static void ufshcd_hba_exit(struct ufs_hba *hba);
240static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 241static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
242 bool skip_ref_clk);
243static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 244static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 245static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
246static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 247static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 248static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 249static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
250static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
251static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 252static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 253static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
254 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 255static int ufshcd_change_power_mode(struct ufs_hba *hba,
256 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 257static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
258{
259 return tag >= 0 && tag < hba->nutrs;
260}
57d104c1
SJ		 261
262static inline int ufshcd_enable_irq(struct ufs_hba *hba)
263{
264 int ret = 0;
265
266 if (!hba->is_irq_enabled) {
267 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
268 hba);
269 if (ret)
270 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
271 __func__, ret);
272 hba->is_irq_enabled = true;
273 }
274
275 return ret;
276}
277
278static inline void ufshcd_disable_irq(struct ufs_hba *hba)
279{
280 if (hba->is_irq_enabled) {
281 free_irq(hba->irq, hba);
282 hba->is_irq_enabled = false;
283 }
284}
3441da7d 285
b573d484
YG		 286/* replace non-printable or non-ASCII characters with spaces */
287static inline void ufshcd_remove_non_printable(char *val)
288{
289 if (!val)
290 return;
291
292 if (*val < 0x20 || *val > 0x7e)
293 *val = ' ';
294}
295
66cc820f
DR		 296static void ufshcd_print_host_regs(struct ufs_hba *hba)
297{
298 /*
299 * hex_dump reads its data without the readl macro. This might
300 * cause inconsistency issues on some platform, as the printed
301 * values may be from cache and not the most recent value.
302 * To know whether you are looking at an un-cached version verify
303 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
304 * during platform/pci probe function.
305 */
306 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
307 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
308 hba->ufs_version, hba->capabilities);
309 dev_err(hba->dev,
310 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
311 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
312}
313
314static
315void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
316{
317 struct ufshcd_lrb *lrbp;
318 int tag;
319
320 for_each_set_bit(tag, &bitmap, hba->nutrs) {
321 lrbp = &hba->lrb[tag];
322
323 dev_err(hba->dev, "UPIU[%d] - Transfer Request Descriptor\n",
324 tag);
325 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
326 sizeof(struct utp_transfer_req_desc));
327 dev_err(hba->dev, "UPIU[%d] - Request UPIU\n", tag);
328 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
329 sizeof(struct utp_upiu_req));
330 dev_err(hba->dev, "UPIU[%d] - Response UPIU\n", tag);
331 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
332 sizeof(struct utp_upiu_rsp));
333 if (pr_prdt) {
334 int prdt_length = le16_to_cpu(
335 lrbp->utr_descriptor_ptr->prd_table_length);
336
337 dev_err(hba->dev, "UPIU[%d] - PRDT - %d entries\n", tag,
338 prdt_length);
339 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
340 sizeof(struct ufshcd_sg_entry) *
341 prdt_length);
342 }
343 }
344}
345
346static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
347{
348 struct utp_task_req_desc *tmrdp;
349 int tag;
350
351 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
352 tmrdp = &hba->utmrdl_base_addr[tag];
353 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
354 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
355 sizeof(struct request_desc_header));
356 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
357 tag);
358 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
359 sizeof(struct utp_upiu_req));
360 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
361 tag);
362 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
363 sizeof(struct utp_task_req_desc));
364 }
365}
366
5a0b0cb9
SRT		 367/*
368 * ufshcd_wait_for_register - wait for register value to change
369 * @hba - per-adapter interface
370 * @reg - mmio register offset
371 * @mask - mask to apply to read register value
372 * @val - wait condition
373 * @interval_us - polling interval in microsecs
374 * @timeout_ms - timeout in millisecs
596585a2 375 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 376 *
377 * Returns -ETIMEDOUT on error, zero on success
378 */
596585a2
YG		 379int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
380 u32 val, unsigned long interval_us,
381 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 382{
383 int err = 0;
384 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
385
386 /* ignore bits that we don't intend to wait on */
387 val = val & mask;
388
389 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 390 if (can_sleep)
391 usleep_range(interval_us, interval_us + 50);
392 else
393 udelay(interval_us);
5a0b0cb9
SRT		 394 if (time_after(jiffies, timeout)) {
395 if ((ufshcd_readl(hba, reg) & mask) != val)
396 err = -ETIMEDOUT;
397 break;
398 }
399 }
400
401 return err;
402}
403
2fbd009b
SJ		 404/**
405 * ufshcd_get_intr_mask - Get the interrupt bit mask
406 * @hba - Pointer to adapter instance
407 *
408 * Returns interrupt bit mask per version
409 */
410static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
411{
c01848c6
YG		 412 u32 intr_mask = 0;
413
414 switch (hba->ufs_version) {
415 case UFSHCI_VERSION_10:
416 intr_mask = INTERRUPT_MASK_ALL_VER_10;
417 break;
418 /* allow fall through */
419 case UFSHCI_VERSION_11:
420 case UFSHCI_VERSION_20:
421 intr_mask = INTERRUPT_MASK_ALL_VER_11;
422 break;
423 /* allow fall through */
424 case UFSHCI_VERSION_21:
425 default:
426 intr_mask = INTERRUPT_MASK_ALL_VER_21;
427 }
428
429 return intr_mask;
2fbd009b
SJ		 430}
431
7a3e97b0
SY		 432/**
433 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
434 * @hba - Pointer to adapter instance
435 *
436 * Returns UFSHCI version supported by the controller
437 */
438static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
439{
0263bcd0
YG		 440 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
441 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 442
b873a275 443 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 444}
445
446/**
447 * ufshcd_is_device_present - Check if any device connected to
448 * the host controller
5c0c28a8 449 * @hba: pointer to adapter instance
7a3e97b0 450 *
73ec513a 451 * Returns 1 if device present, 0 if no device detected
7a3e97b0 452 */
5c0c28a8 453static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 454{
5c0c28a8
SRT		 455 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
456 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 457}
458
459/**
460 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
461 * @lrb: pointer to local command reference block
462 *
463 * This function is used to get the OCS field from UTRD
464 * Returns the OCS field in the UTRD
465 */
466static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
467{
e8c8e82a 468 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 469}
470
471/**
472 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
473 * @task_req_descp: pointer to utp_task_req_desc structure
474 *
475 * This function is used to get the OCS field from UTMRD
476 * Returns the OCS field in the UTMRD
477 */
478static inline int
479ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
480{
e8c8e82a 481 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 482}
483
484/**
485 * ufshcd_get_tm_free_slot - get a free slot for task management request
486 * @hba: per adapter instance
e2933132 487 * @free_slot: pointer to variable with available slot value
7a3e97b0 488 *
e2933132
SRT		 489 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
490 * Returns 0 if free slot is not available, else return 1 with tag value
491 * in @free_slot.
7a3e97b0 492 */
e2933132 493static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 494{
e2933132
SRT		 495 int tag;
496 bool ret = false;
497
498 if (!free_slot)
499 goto out;
500
501 do {
502 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
503 if (tag >= hba->nutmrs)
504 goto out;
505 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
506
507 *free_slot = tag;
508 ret = true;
509out:
510 return ret;
511}
512
513static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
514{
515 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 516}
517
518/**
519 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
520 * @hba: per adapter instance
521 * @pos: position of the bit to be cleared
522 */
523static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
524{
b873a275 525 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 526}
527
a48353f6
YG		 528/**
529 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
530 * @hba: per adapter instance
531 * @tag: position of the bit to be cleared
532 */
533static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
534{
535 __clear_bit(tag, &hba->outstanding_reqs);
536}
537
7a3e97b0
SY		 538/**
539 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
540 * @reg: Register value of host controller status
541 *
542 * Returns integer, 0 on Success and positive value if failed
543 */
544static inline int ufshcd_get_lists_status(u32 reg)
545{
546 /*
547 * The mask 0xFF is for the following HCS register bits
548 * Bit Description
549 * 0 Device Present
550 * 1 UTRLRDY
551 * 2 UTMRLRDY
552 * 3 UCRDY
897efe62 553 * 4-7 reserved
7a3e97b0 554 */
897efe62 555 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 556}
557
558/**
559 * ufshcd_get_uic_cmd_result - Get the UIC command result
560 * @hba: Pointer to adapter instance
561 *
562 * This function gets the result of UIC command completion
563 * Returns 0 on success, non zero value on error
564 */
565static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
566{
b873a275 567 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 568 MASK_UIC_COMMAND_RESULT;
569}
570
12b4fdb4
SJ		 571/**
572 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
573 * @hba: Pointer to adapter instance
574 *
575 * This function gets UIC command argument3
576 * Returns 0 on success, non zero value on error
577 */
578static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
579{
580 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
581}
582
7a3e97b0 583/**
5a0b0cb9 584 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 585 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 586 */
587static inline int
5a0b0cb9 588ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 589{
5a0b0cb9 590 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 591}
592
593/**
594 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
595 * @ucd_rsp_ptr: pointer to response UPIU
596 *
597 * This function gets the response status and scsi_status from response UPIU
598 * Returns the response result code.
599 */
600static inline int
601ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
602{
603 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
604}
605
1c2623c5
SJ		 606/*
607 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
608 * from response UPIU
609 * @ucd_rsp_ptr: pointer to response UPIU
610 *
611 * Return the data segment length.
612 */
613static inline unsigned int
614ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
615{
616 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
617 MASK_RSP_UPIU_DATA_SEG_LEN;
618}
619
66ec6d59
SRT		 620/**
621 * ufshcd_is_exception_event - Check if the device raised an exception event
622 * @ucd_rsp_ptr: pointer to response UPIU
623 *
624 * The function checks if the device raised an exception event indicated in
625 * the Device Information field of response UPIU.
626 *
627 * Returns true if exception is raised, false otherwise.
628 */
629static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
630{
631 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
632 MASK_RSP_EXCEPTION_EVENT ? true : false;
633}
634
7a3e97b0 635/**
7d568652 636 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 637 * @hba: per adapter instance
7a3e97b0
SY		 638 */
639static inline void
7d568652 640ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 641{
7d568652
SJ		 642 ufshcd_writel(hba, INT_AGGR_ENABLE |
643 INT_AGGR_COUNTER_AND_TIMER_RESET,
644 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
645}
646
647/**
648 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
649 * @hba: per adapter instance
650 * @cnt: Interrupt aggregation counter threshold
651 * @tmout: Interrupt aggregation timeout value
652 */
653static inline void
654ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
655{
656 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
657 INT_AGGR_COUNTER_THLD_VAL(cnt) |
658 INT_AGGR_TIMEOUT_VAL(tmout),
659 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 660}
661
b852190e
YG		 662/**
663 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
664 * @hba: per adapter instance
665 */
666static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
667{
668 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
669}
670
7a3e97b0
SY		 671/**
672 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
673 * When run-stop registers are set to 1, it indicates the
674 * host controller that it can process the requests
675 * @hba: per adapter instance
676 */
677static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
678{
b873a275
SJ		 679 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
680 REG_UTP_TASK_REQ_LIST_RUN_STOP);
681 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
682 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 683}
684
7a3e97b0
SY		 685/**
686 * ufshcd_hba_start - Start controller initialization sequence
687 * @hba: per adapter instance
688 */
689static inline void ufshcd_hba_start(struct ufs_hba *hba)
690{
b873a275 691 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 692}
693
694/**
695 * ufshcd_is_hba_active - Get controller state
696 * @hba: per adapter instance
697 *
698 * Returns zero if controller is active, 1 otherwise
699 */
700static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
701{
b873a275 702 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 703}
704
09690d5a 705static const char *ufschd_uic_link_state_to_string(
706 enum uic_link_state state)
707{
708 switch (state) {
709 case UIC_LINK_OFF_STATE: return "OFF";
710 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
711 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
712 default: return "UNKNOWN";
713 }
714}
715
716static const char *ufschd_ufs_dev_pwr_mode_to_string(
717 enum ufs_dev_pwr_mode state)
718{
719 switch (state) {
720 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
721 case UFS_SLEEP_PWR_MODE: return "SLEEP";
722 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
723 default: return "UNKNOWN";
724 }
725}
726
37113106
YG		 727u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
728{
729 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
730 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
731 (hba->ufs_version == UFSHCI_VERSION_11))
732 return UFS_UNIPRO_VER_1_41;
733 else
734 return UFS_UNIPRO_VER_1_6;
735}
736EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
737
738static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
739{
740 /*
741 * If both host and device support UniPro ver1.6 or later, PA layer
742 * parameters tuning happens during link startup itself.
743 *
744 * We can manually tune PA layer parameters if either host or device
745 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
746 * logic simple, we will only do manual tuning if local unipro version
747 * doesn't support ver1.6 or later.
748 */
749 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
750 return true;
751 else
752 return false;
753}
754
a508253d
GB		 755static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
756{
fcb0c4b0
ST		 757 if (!ufshcd_is_clkscaling_supported(hba))
758 return;
759
760 devfreq_suspend_device(hba->devfreq);
761 hba->clk_scaling.window_start_t = 0;
a508253d
GB		 762}
763
764static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
765{
fcb0c4b0
ST		 766 devfreq_resume_device(hba->devfreq);
767}
768
769static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
770 struct device_attribute *attr, char *buf)
771{
772 struct ufs_hba *hba = dev_get_drvdata(dev);
773
774 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
775}
776
777static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
778 struct device_attribute *attr, const char *buf, size_t count)
779{
780 struct ufs_hba *hba = dev_get_drvdata(dev);
781 u32 value;
782 int err;
783
784 if (kstrtou32(buf, 0, &value))
785 return -EINVAL;
786
787 value = !!value;
788 if (value == hba->clk_scaling.is_allowed)
789 goto out;
790
791 pm_runtime_get_sync(hba->dev);
792 ufshcd_hold(hba, false);
793
794 if (value) {
795 ufshcd_resume_clkscaling(hba);
796 } else {
797 ufshcd_suspend_clkscaling(hba);
798 err = ufshcd_scale_clks(hba, true);
799 if (err)
800 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
801 __func__, err);
802 }
803 hba->clk_scaling.is_allowed = value;
804
805 ufshcd_release(hba);
806 pm_runtime_put_sync(hba->dev);
807out:
808 return count;
a508253d
GB		 809}
810
1ab27c9c
ST		 811static void ufshcd_ungate_work(struct work_struct *work)
812{
813 int ret;
814 unsigned long flags;
815 struct ufs_hba *hba = container_of(work, struct ufs_hba,
816 clk_gating.ungate_work);
817
818 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
819
820 spin_lock_irqsave(hba->host->host_lock, flags);
821 if (hba->clk_gating.state == CLKS_ON) {
822 spin_unlock_irqrestore(hba->host->host_lock, flags);
823 goto unblock_reqs;
824 }
825
826 spin_unlock_irqrestore(hba->host->host_lock, flags);
827 ufshcd_setup_clocks(hba, true);
828
829 /* Exit from hibern8 */
830 if (ufshcd_can_hibern8_during_gating(hba)) {
831 /* Prevent gating in this path */
832 hba->clk_gating.is_suspended = true;
833 if (ufshcd_is_link_hibern8(hba)) {
834 ret = ufshcd_uic_hibern8_exit(hba);
835 if (ret)
836 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
837 __func__, ret);
838 else
839 ufshcd_set_link_active(hba);
840 }
841 hba->clk_gating.is_suspended = false;
842 }
843unblock_reqs:
fcb0c4b0
ST		 844 if (hba->clk_scaling.is_allowed)
845 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 846 scsi_unblock_requests(hba->host);
847}
848
849/**
850 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
851 * Also, exit from hibern8 mode and set the link as active.
852 * @hba: per adapter instance
853 * @async: This indicates whether caller should ungate clocks asynchronously.
854 */
855int ufshcd_hold(struct ufs_hba *hba, bool async)
856{
857 int rc = 0;
858 unsigned long flags;
859
860 if (!ufshcd_is_clkgating_allowed(hba))
861 goto out;
1ab27c9c
ST		 862 spin_lock_irqsave(hba->host->host_lock, flags);
863 hba->clk_gating.active_reqs++;
864
53c12d0e
YG		 865 if (ufshcd_eh_in_progress(hba)) {
866 spin_unlock_irqrestore(hba->host->host_lock, flags);
867 return 0;
868 }
869
856b3483 870start:
1ab27c9c
ST		 871 switch (hba->clk_gating.state) {
872 case CLKS_ON:
f2a785ac
VG		 873 /*
874 * Wait for the ungate work to complete if in progress.
875 * Though the clocks may be in ON state, the link could
876 * still be in hibner8 state if hibern8 is allowed
877 * during clock gating.
878 * Make sure we exit hibern8 state also in addition to
879 * clocks being ON.
880 */
881 if (ufshcd_can_hibern8_during_gating(hba) &&
882 ufshcd_is_link_hibern8(hba)) {
883 spin_unlock_irqrestore(hba->host->host_lock, flags);
884 flush_work(&hba->clk_gating.ungate_work);
885 spin_lock_irqsave(hba->host->host_lock, flags);
886 goto start;
887 }
1ab27c9c
ST		 888 break;
889 case REQ_CLKS_OFF:
890 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
891 hba->clk_gating.state = CLKS_ON;
7ff5ab47 892 trace_ufshcd_clk_gating(dev_name(hba->dev),
893 hba->clk_gating.state);
1ab27c9c
ST		 894 break;
895 }
896 /*
897 * If we here, it means gating work is either done or
898 * currently running. Hence, fall through to cancel gating
899 * work and to enable clocks.
900 */
901 case CLKS_OFF:
902 scsi_block_requests(hba->host);
903 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 904 trace_ufshcd_clk_gating(dev_name(hba->dev),
905 hba->clk_gating.state);
1ab27c9c
ST		 906 schedule_work(&hba->clk_gating.ungate_work);
907 /*
908 * fall through to check if we should wait for this
909 * work to be done or not.
910 */
911 case REQ_CLKS_ON:
912 if (async) {
913 rc = -EAGAIN;
914 hba->clk_gating.active_reqs--;
915 break;
916 }
917
918 spin_unlock_irqrestore(hba->host->host_lock, flags);
919 flush_work(&hba->clk_gating.ungate_work);
920 /* Make sure state is CLKS_ON before returning */
856b3483 921 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 922 goto start;
923 default:
924 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
925 __func__, hba->clk_gating.state);
926 break;
927 }
928 spin_unlock_irqrestore(hba->host->host_lock, flags);
929out:
930 return rc;
931}
6e3fd44d 932EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 933
934static void ufshcd_gate_work(struct work_struct *work)
935{
936 struct ufs_hba *hba = container_of(work, struct ufs_hba,
937 clk_gating.gate_work.work);
938 unsigned long flags;
939
940 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 941 /*
942 * In case you are here to cancel this work the gating state
943 * would be marked as REQ_CLKS_ON. In this case save time by
944 * skipping the gating work and exit after changing the clock
945 * state to CLKS_ON.
946 */
947 if (hba->clk_gating.is_suspended ||
948 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 949 hba->clk_gating.state = CLKS_ON;
7ff5ab47 950 trace_ufshcd_clk_gating(dev_name(hba->dev),
951 hba->clk_gating.state);
1ab27c9c
ST		 952 goto rel_lock;
953 }
954
955 if (hba->clk_gating.active_reqs
956 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
957 || hba->lrb_in_use || hba->outstanding_tasks
958 || hba->active_uic_cmd || hba->uic_async_done)
959 goto rel_lock;
960
961 spin_unlock_irqrestore(hba->host->host_lock, flags);
962
963 /* put the link into hibern8 mode before turning off clocks */
964 if (ufshcd_can_hibern8_during_gating(hba)) {
965 if (ufshcd_uic_hibern8_enter(hba)) {
966 hba->clk_gating.state = CLKS_ON;
7ff5ab47 967 trace_ufshcd_clk_gating(dev_name(hba->dev),
968 hba->clk_gating.state);
1ab27c9c
ST		 969 goto out;
970 }
971 ufshcd_set_link_hibern8(hba);
972 }
973
a508253d 974 ufshcd_suspend_clkscaling(hba);
856b3483 975
1ab27c9c
ST		 976 if (!ufshcd_is_link_active(hba))
977 ufshcd_setup_clocks(hba, false);
978 else
979 /* If link is active, device ref_clk can't be switched off */
980 __ufshcd_setup_clocks(hba, false, true);
981
982 /*
983 * In case you are here to cancel this work the gating state
984 * would be marked as REQ_CLKS_ON. In this case keep the state
985 * as REQ_CLKS_ON which would anyway imply that clocks are off
986 * and a request to turn them on is pending. By doing this way,
987 * we keep the state machine in tact and this would ultimately
988 * prevent from doing cancel work multiple times when there are
989 * new requests arriving before the current cancel work is done.
990 */
991 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 992 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 993 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 994 trace_ufshcd_clk_gating(dev_name(hba->dev),
995 hba->clk_gating.state);
996 }
1ab27c9c
ST		 997rel_lock:
998 spin_unlock_irqrestore(hba->host->host_lock, flags);
999out:
1000 return;
1001}
1002
1003/* host lock must be held before calling this variant */
1004static void __ufshcd_release(struct ufs_hba *hba)
1005{
1006 if (!ufshcd_is_clkgating_allowed(hba))
1007 return;
1008
1009 hba->clk_gating.active_reqs--;
1010
1011 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1012 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1013 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1014 || hba->active_uic_cmd || hba->uic_async_done
1015 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1016 return;
1017
1018 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1019 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1020 schedule_delayed_work(&hba->clk_gating.gate_work,
1021 msecs_to_jiffies(hba->clk_gating.delay_ms));
1022}
1023
1024void ufshcd_release(struct ufs_hba *hba)
1025{
1026 unsigned long flags;
1027
1028 spin_lock_irqsave(hba->host->host_lock, flags);
1029 __ufshcd_release(hba);
1030 spin_unlock_irqrestore(hba->host->host_lock, flags);
1031}
6e3fd44d 1032EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1033
1034static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1035 struct device_attribute *attr, char *buf)
1036{
1037 struct ufs_hba *hba = dev_get_drvdata(dev);
1038
1039 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1040}
1041
1042static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1043 struct device_attribute *attr, const char *buf, size_t count)
1044{
1045 struct ufs_hba *hba = dev_get_drvdata(dev);
1046 unsigned long flags, value;
1047
1048 if (kstrtoul(buf, 0, &value))
1049 return -EINVAL;
1050
1051 spin_lock_irqsave(hba->host->host_lock, flags);
1052 hba->clk_gating.delay_ms = value;
1053 spin_unlock_irqrestore(hba->host->host_lock, flags);
1054 return count;
1055}
1056
b427411a
ST		 1057static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1058 struct device_attribute *attr, char *buf)
1059{
1060 struct ufs_hba *hba = dev_get_drvdata(dev);
1061
1062 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1063}
1064
1065static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1066 struct device_attribute *attr, const char *buf, size_t count)
1067{
1068 struct ufs_hba *hba = dev_get_drvdata(dev);
1069 unsigned long flags;
1070 u32 value;
1071
1072 if (kstrtou32(buf, 0, &value))
1073 return -EINVAL;
1074
1075 value = !!value;
1076 if (value == hba->clk_gating.is_enabled)
1077 goto out;
1078
1079 if (value) {
1080 ufshcd_release(hba);
1081 } else {
1082 spin_lock_irqsave(hba->host->host_lock, flags);
1083 hba->clk_gating.active_reqs++;
1084 spin_unlock_irqrestore(hba->host->host_lock, flags);
1085 }
1086
1087 hba->clk_gating.is_enabled = value;
1088out:
1089 return count;
1090}
1091
1ab27c9c
ST		 1092static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1093{
1094 if (!ufshcd_is_clkgating_allowed(hba))
1095 return;
1096
1097 hba->clk_gating.delay_ms = 150;
1098 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1099 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1100
b427411a
ST		 1101 hba->clk_gating.is_enabled = true;
1102
1ab27c9c
ST		 1103 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1104 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1105 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1106 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1107 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1108 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1109 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1110
1111 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1112 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1113 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1114 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1115 hba->clk_gating.enable_attr.attr.mode = 0644;
1116 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1117 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1118}
1119
1120static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1121{
1122 if (!ufshcd_is_clkgating_allowed(hba))
1123 return;
1124 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1125 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1126 cancel_work_sync(&hba->clk_gating.ungate_work);
1127 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 1128}
1129
856b3483
ST		 1130/* Must be called with host lock acquired */
1131static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1132{
fcb0c4b0 1133 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1134 return;
1135
1136 if (!hba->clk_scaling.is_busy_started) {
1137 hba->clk_scaling.busy_start_t = ktime_get();
1138 hba->clk_scaling.is_busy_started = true;
1139 }
1140}
1141
1142static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1143{
1144 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1145
fcb0c4b0 1146 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1147 return;
1148
1149 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1150 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1151 scaling->busy_start_t));
8b0e1953 1152 scaling->busy_start_t = 0;
856b3483
ST		 1153 scaling->is_busy_started = false;
1154 }
1155}
7a3e97b0
SY		 1156/**
1157 * ufshcd_send_command - Send SCSI or device management commands
1158 * @hba: per adapter instance
1159 * @task_tag: Task tag of the command
1160 */
1161static inline
1162void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1163{
856b3483 1164 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1165 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1166 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1167 /* Make sure that doorbell is committed immediately */
1168 wmb();
7a3e97b0
SY		 1169}
1170
1171/**
1172 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1173 * @lrb - pointer to local reference block
1174 */
1175static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1176{
1177 int len;
1c2623c5
SJ		 1178 if (lrbp->sense_buffer &&
1179 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1180 int len_to_copy;
1181
5a0b0cb9 1182 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1183 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1184
7a3e97b0 1185 memcpy(lrbp->sense_buffer,
5a0b0cb9 1186 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1187 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1188 }
1189}
1190
68078d5c
DR		 1191/**
1192 * ufshcd_copy_query_response() - Copy the Query Response and the data
1193 * descriptor
1194 * @hba: per adapter instance
1195 * @lrb - pointer to local reference block
1196 */
1197static
c6d4a831 1198int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1199{
1200 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1201
68078d5c 1202 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1203
68078d5c
DR		 1204 /* Get the descriptor */
1205 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1206 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1207 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1208 u16 resp_len;
1209 u16 buf_len;
68078d5c
DR		 1210
1211 /* data segment length */
c6d4a831 1212 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1213 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1214 buf_len = be16_to_cpu(
1215 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1216 if (likely(buf_len >= resp_len)) {
1217 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1218 } else {
1219 dev_warn(hba->dev,
1220 "%s: Response size is bigger than buffer",
1221 __func__);
1222 return -EINVAL;
1223 }
68078d5c 1224 }
c6d4a831
DR		 1225
1226 return 0;
68078d5c
DR		 1227}
1228
7a3e97b0
SY		 1229/**
1230 * ufshcd_hba_capabilities - Read controller capabilities
1231 * @hba: per adapter instance
1232 */
1233static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1234{
b873a275 1235 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1236
1237 /* nutrs and nutmrs are 0 based values */
1238 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1239 hba->nutmrs =
1240 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1241}
1242
1243/**
6ccf44fe
SJ		 1244 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1245 * to accept UIC commands
7a3e97b0 1246 * @hba: per adapter instance
6ccf44fe
SJ		 1247 * Return true on success, else false
1248 */
1249static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1250{
1251 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1252 return true;
1253 else
1254 return false;
1255}
1256
53b3d9c3
SJ		 1257/**
1258 * ufshcd_get_upmcrs - Get the power mode change request status
1259 * @hba: Pointer to adapter instance
1260 *
1261 * This function gets the UPMCRS field of HCS register
1262 * Returns value of UPMCRS field
1263 */
1264static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1265{
1266 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1267}
1268
6ccf44fe
SJ		 1269/**
1270 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1271 * @hba: per adapter instance
1272 * @uic_cmd: UIC command
1273 *
1274 * Mutex must be held.
7a3e97b0
SY		 1275 */
1276static inline void
6ccf44fe 1277ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1278{
6ccf44fe
SJ		 1279 WARN_ON(hba->active_uic_cmd);
1280
1281 hba->active_uic_cmd = uic_cmd;
1282
7a3e97b0 1283 /* Write Args */
6ccf44fe
SJ		 1284 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1285 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1286 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1287
1288 /* Write UIC Cmd */
6ccf44fe 1289 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1290 REG_UIC_COMMAND);
7a3e97b0
SY		 1291}
1292
6ccf44fe
SJ		 1293/**
1294 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1295 * @hba: per adapter instance
1296 * @uic_command: UIC command
1297 *
1298 * Must be called with mutex held.
1299 * Returns 0 only if success.
1300 */
1301static int
1302ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1303{
1304 int ret;
1305 unsigned long flags;
1306
1307 if (wait_for_completion_timeout(&uic_cmd->done,
1308 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1309 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1310 else
1311 ret = -ETIMEDOUT;
1312
1313 spin_lock_irqsave(hba->host->host_lock, flags);
1314 hba->active_uic_cmd = NULL;
1315 spin_unlock_irqrestore(hba->host->host_lock, flags);
1316
1317 return ret;
1318}
1319
1320/**
1321 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1322 * @hba: per adapter instance
1323 * @uic_cmd: UIC command
d75f7fe4 1324 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1325 *
1326 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1327 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1328 * Returns 0 only if success.
1329 */
1330static int
d75f7fe4
YG		 1331__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1332 bool completion)
6ccf44fe 1333{
6ccf44fe
SJ		 1334 if (!ufshcd_ready_for_uic_cmd(hba)) {
1335 dev_err(hba->dev,
1336 "Controller not ready to accept UIC commands\n");
1337 return -EIO;
1338 }
1339
d75f7fe4
YG		 1340 if (completion)
1341 init_completion(&uic_cmd->done);
6ccf44fe 1342
6ccf44fe 1343 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1344
57d104c1 1345 return 0;
6ccf44fe
SJ		 1346}
1347
1348/**
1349 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1350 * @hba: per adapter instance
1351 * @uic_cmd: UIC command
1352 *
1353 * Returns 0 only if success.
1354 */
1355static int
1356ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1357{
1358 int ret;
57d104c1 1359 unsigned long flags;
6ccf44fe 1360
1ab27c9c 1361 ufshcd_hold(hba, false);
6ccf44fe 1362 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1363 ufshcd_add_delay_before_dme_cmd(hba);
1364
57d104c1 1365 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1366 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1367 spin_unlock_irqrestore(hba->host->host_lock, flags);
1368 if (!ret)
1369 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1370
6ccf44fe
SJ		 1371 mutex_unlock(&hba->uic_cmd_mutex);
1372
1ab27c9c 1373 ufshcd_release(hba);
6ccf44fe
SJ		 1374 return ret;
1375}
1376
7a3e97b0
SY		 1377/**
1378 * ufshcd_map_sg - Map scatter-gather list to prdt
1379 * @lrbp - pointer to local reference block
1380 *
1381 * Returns 0 in case of success, non-zero value in case of failure
1382 */
75b1cc4a 1383static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1384{
1385 struct ufshcd_sg_entry *prd_table;
1386 struct scatterlist *sg;
1387 struct scsi_cmnd *cmd;
1388 int sg_segments;
1389 int i;
1390
1391 cmd = lrbp->cmd;
1392 sg_segments = scsi_dma_map(cmd);
1393 if (sg_segments < 0)
1394 return sg_segments;
1395
1396 if (sg_segments) {
75b1cc4a
KK		 1397 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1398 lrbp->utr_descriptor_ptr->prd_table_length =
1399 cpu_to_le16((u16)(sg_segments *
1400 sizeof(struct ufshcd_sg_entry)));
1401 else
1402 lrbp->utr_descriptor_ptr->prd_table_length =
1403 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 1404
1405 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1406
1407 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1408 prd_table[i].size =
1409 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1410 prd_table[i].base_addr =
1411 cpu_to_le32(lower_32_bits(sg->dma_address));
1412 prd_table[i].upper_addr =
1413 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1414 prd_table[i].reserved = 0;
7a3e97b0
SY		 1415 }
1416 } else {
1417 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1418 }
1419
1420 return 0;
1421}
1422
1423/**
2fbd009b 1424 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1425 * @hba: per adapter instance
2fbd009b 1426 * @intrs: interrupt bits
7a3e97b0 1427 */
2fbd009b 1428static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1429{
2fbd009b
SJ		 1430 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1431
1432 if (hba->ufs_version == UFSHCI_VERSION_10) {
1433 u32 rw;
1434 rw = set & INTERRUPT_MASK_RW_VER_10;
1435 set = rw | ((set ^ intrs) & intrs);
1436 } else {
1437 set |= intrs;
1438 }
1439
1440 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1441}
1442
1443/**
1444 * ufshcd_disable_intr - disable interrupts
1445 * @hba: per adapter instance
1446 * @intrs: interrupt bits
1447 */
1448static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1449{
1450 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1451
1452 if (hba->ufs_version == UFSHCI_VERSION_10) {
1453 u32 rw;
1454 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1455 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1456 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1457
1458 } else {
1459 set &= ~intrs;
7a3e97b0 1460 }
2fbd009b
SJ		 1461
1462 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1463}
1464
5a0b0cb9
SRT		 1465/**
1466 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1467 * descriptor according to request
1468 * @lrbp: pointer to local reference block
1469 * @upiu_flags: flags required in the header
1470 * @cmd_dir: requests data direction
1471 */
1472static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1473 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 1474{
1475 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1476 u32 data_direction;
1477 u32 dword_0;
1478
1479 if (cmd_dir == DMA_FROM_DEVICE) {
1480 data_direction = UTP_DEVICE_TO_HOST;
1481 *upiu_flags = UPIU_CMD_FLAGS_READ;
1482 } else if (cmd_dir == DMA_TO_DEVICE) {
1483 data_direction = UTP_HOST_TO_DEVICE;
1484 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1485 } else {
1486 data_direction = UTP_NO_DATA_TRANSFER;
1487 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1488 }
1489
1490 dword_0 = data_direction | (lrbp->command_type
1491 << UPIU_COMMAND_TYPE_OFFSET);
1492 if (lrbp->intr_cmd)
1493 dword_0 |= UTP_REQ_DESC_INT_CMD;
1494
1495 /* Transfer request descriptor header fields */
1496 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1497 /* dword_1 is reserved, hence it is set to 0 */
1498 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1499 /*
1500 * assigning invalid value for command status. Controller
1501 * updates OCS on command completion, with the command
1502 * status
1503 */
1504 req_desc->header.dword_2 =
1505 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1506 /* dword_3 is reserved, hence it is set to 0 */
1507 req_desc->header.dword_3 = 0;
51047266
YG		 1508
1509 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1510}
1511
1512/**
1513 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1514 * for scsi commands
1515 * @lrbp - local reference block pointer
1516 * @upiu_flags - flags
1517 */
1518static
1519void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1520{
1521 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1522 unsigned short cdb_len;
5a0b0cb9
SRT		 1523
1524 /* command descriptor fields */
1525 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1526 UPIU_TRANSACTION_COMMAND, upiu_flags,
1527 lrbp->lun, lrbp->task_tag);
1528 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1529 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1530
1531 /* Total EHS length and Data segment length will be zero */
1532 ucd_req_ptr->header.dword_2 = 0;
1533
1534 ucd_req_ptr->sc.exp_data_transfer_len =
1535 cpu_to_be32(lrbp->cmd->sdb.length);
1536
52ac95fe
YG		 1537 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1538 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1539 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1540
1541 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1542}
1543
68078d5c
DR		 1544/**
1545 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1546 * for query requsts
1547 * @hba: UFS hba
1548 * @lrbp: local reference block pointer
1549 * @upiu_flags: flags
1550 */
1551static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1552 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1553{
1554 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1555 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1556 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1557 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1558
1559 /* Query request header */
1560 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1561 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1562 lrbp->lun, lrbp->task_tag);
1563 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1564 0, query->request.query_func, 0, 0);
1565
6861285c
ZL		 1566 /* Data segment length only need for WRITE_DESC */
1567 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1568 ucd_req_ptr->header.dword_2 =
1569 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
1570 else
1571 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 1572
1573 /* Copy the Query Request buffer as is */
1574 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1575 QUERY_OSF_SIZE);
68078d5c
DR		 1576
1577 /* Copy the Descriptor */
c6d4a831
DR		 1578 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1579 memcpy(descp, query->descriptor, len);
1580
51047266 1581 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1582}
1583
5a0b0cb9
SRT		 1584static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1585{
1586 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1587
1588 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1589
1590 /* command descriptor fields */
1591 ucd_req_ptr->header.dword_0 =
1592 UPIU_HEADER_DWORD(
1593 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1594 /* clear rest of the fields of basic header */
1595 ucd_req_ptr->header.dword_1 = 0;
1596 ucd_req_ptr->header.dword_2 = 0;
1597
1598 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1599}
1600
7a3e97b0 1601/**
300bb13f
JP		 1602 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1603 * for Device Management Purposes
5a0b0cb9 1604 * @hba - per adapter instance
7a3e97b0
SY		 1605 * @lrb - pointer to local reference block
1606 */
300bb13f 1607static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1608{
7a3e97b0 1609 u32 upiu_flags;
5a0b0cb9 1610 int ret = 0;
7a3e97b0 1611
300bb13f
JP		 1612 if (hba->ufs_version == UFSHCI_VERSION_20)
1613 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1614 else
1615 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1616
1617 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1618 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1619 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1620 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1621 ufshcd_prepare_utp_nop_upiu(lrbp);
1622 else
1623 ret = -EINVAL;
1624
1625 return ret;
1626}
1627
1628/**
1629 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1630 * for SCSI Purposes
1631 * @hba - per adapter instance
1632 * @lrb - pointer to local reference block
1633 */
1634static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1635{
1636 u32 upiu_flags;
1637 int ret = 0;
1638
1639 if (hba->ufs_version == UFSHCI_VERSION_20)
1640 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1641 else
1642 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1643
1644 if (likely(lrbp->cmd)) {
1645 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1646 lrbp->cmd->sc_data_direction);
1647 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1648 } else {
1649 ret = -EINVAL;
1650 }
5a0b0cb9
SRT		 1651
1652 return ret;
7a3e97b0
SY		 1653}
1654
0ce147d4
SJ		 1655/*
1656 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1657 * @scsi_lun: scsi LUN id
1658 *
1659 * Returns UPIU LUN id
1660 */
1661static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1662{
1663 if (scsi_is_wlun(scsi_lun))
1664 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1665 | UFS_UPIU_WLUN_ID;
1666 else
1667 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1668}
1669
2a8fa600
SJ		 1670/**
1671 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1672 * @scsi_lun: UPIU W-LUN id
1673 *
1674 * Returns SCSI W-LUN id
1675 */
1676static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1677{
1678 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1679}
1680
7a3e97b0
SY		 1681/**
1682 * ufshcd_queuecommand - main entry point for SCSI requests
1683 * @cmd: command from SCSI Midlayer
1684 * @done: call back function
1685 *
1686 * Returns 0 for success, non-zero in case of failure
1687 */
1688static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1689{
1690 struct ufshcd_lrb *lrbp;
1691 struct ufs_hba *hba;
1692 unsigned long flags;
1693 int tag;
1694 int err = 0;
1695
1696 hba = shost_priv(host);
1697
1698 tag = cmd->request->tag;
14497328
YG		 1699 if (!ufshcd_valid_tag(hba, tag)) {
1700 dev_err(hba->dev,
1701 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1702 __func__, tag, cmd, cmd->request);
1703 BUG();
1704 }
7a3e97b0 1705
3441da7d
SRT		 1706 spin_lock_irqsave(hba->host->host_lock, flags);
1707 switch (hba->ufshcd_state) {
1708 case UFSHCD_STATE_OPERATIONAL:
1709 break;
141f8165 1710 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 1711 case UFSHCD_STATE_RESET:
7a3e97b0 1712 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1713 goto out_unlock;
1714 case UFSHCD_STATE_ERROR:
1715 set_host_byte(cmd, DID_ERROR);
1716 cmd->scsi_done(cmd);
1717 goto out_unlock;
1718 default:
1719 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1720 __func__, hba->ufshcd_state);
1721 set_host_byte(cmd, DID_BAD_TARGET);
1722 cmd->scsi_done(cmd);
1723 goto out_unlock;
7a3e97b0 1724 }
53c12d0e
YG		 1725
1726 /* if error handling is in progress, don't issue commands */
1727 if (ufshcd_eh_in_progress(hba)) {
1728 set_host_byte(cmd, DID_ERROR);
1729 cmd->scsi_done(cmd);
1730 goto out_unlock;
1731 }
3441da7d 1732 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1733
5a0b0cb9
SRT		 1734 /* acquire the tag to make sure device cmds don't use it */
1735 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1736 /*
1737 * Dev manage command in progress, requeue the command.
1738 * Requeuing the command helps in cases where the request *may*
1739 * find different tag instead of waiting for dev manage command
1740 * completion.
1741 */
1742 err = SCSI_MLQUEUE_HOST_BUSY;
1743 goto out;
1744 }
1745
1ab27c9c
ST		 1746 err = ufshcd_hold(hba, true);
1747 if (err) {
1748 err = SCSI_MLQUEUE_HOST_BUSY;
1749 clear_bit_unlock(tag, &hba->lrb_in_use);
1750 goto out;
1751 }
1752 WARN_ON(hba->clk_gating.state != CLKS_ON);
1753
7a3e97b0
SY		 1754 lrbp = &hba->lrb[tag];
1755
5a0b0cb9 1756 WARN_ON(lrbp->cmd);
7a3e97b0 1757 lrbp->cmd = cmd;
dcea0bfb 1758 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 1759 lrbp->sense_buffer = cmd->sense_buffer;
1760 lrbp->task_tag = tag;
0ce147d4 1761 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1762 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1763
300bb13f
JP		 1764 ufshcd_comp_scsi_upiu(hba, lrbp);
1765
75b1cc4a 1766 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 1767 if (err) {
1768 lrbp->cmd = NULL;
1769 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1770 goto out;
5a0b0cb9 1771 }
ad1a1b9c
GB		 1772 /* Make sure descriptors are ready before ringing the doorbell */
1773 wmb();
7a3e97b0
SY		 1774
1775 /* issue command to the controller */
1776 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1777 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 1778 ufshcd_send_command(hba, tag);
3441da7d 1779out_unlock:
7a3e97b0
SY		 1780 spin_unlock_irqrestore(hba->host->host_lock, flags);
1781out:
1782 return err;
1783}
1784
5a0b0cb9
SRT		 1785static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1786 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1787{
1788 lrbp->cmd = NULL;
1789 lrbp->sense_bufflen = 0;
1790 lrbp->sense_buffer = NULL;
1791 lrbp->task_tag = tag;
1792 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 1793 lrbp->intr_cmd = true; /* No interrupt aggregation */
1794 hba->dev_cmd.type = cmd_type;
1795
300bb13f 1796 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 1797}
1798
1799static int
1800ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1801{
1802 int err = 0;
1803 unsigned long flags;
1804 u32 mask = 1 << tag;
1805
1806 /* clear outstanding transaction before retry */
1807 spin_lock_irqsave(hba->host->host_lock, flags);
1808 ufshcd_utrl_clear(hba, tag);
1809 spin_unlock_irqrestore(hba->host->host_lock, flags);
1810
1811 /*
1812 * wait for for h/w to clear corresponding bit in door-bell.
1813 * max. wait is 1 sec.
1814 */
1815 err = ufshcd_wait_for_register(hba,
1816 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1817 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 1818
1819 return err;
1820}
1821
c6d4a831
DR		 1822static int
1823ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1824{
1825 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1826
1827 /* Get the UPIU response */
1828 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1829 UPIU_RSP_CODE_OFFSET;
1830 return query_res->response;
1831}
1832
5a0b0cb9
SRT		 1833/**
1834 * ufshcd_dev_cmd_completion() - handles device management command responses
1835 * @hba: per adapter instance
1836 * @lrbp: pointer to local reference block
1837 */
1838static int
1839ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1840{
1841 int resp;
1842 int err = 0;
1843
1844 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1845
1846 switch (resp) {
1847 case UPIU_TRANSACTION_NOP_IN:
1848 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1849 err = -EINVAL;
1850 dev_err(hba->dev, "%s: unexpected response %x\n",
1851 __func__, resp);
1852 }
1853 break;
68078d5c 1854 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1855 err = ufshcd_check_query_response(hba, lrbp);
1856 if (!err)
1857 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1858 break;
5a0b0cb9
SRT		 1859 case UPIU_TRANSACTION_REJECT_UPIU:
1860 /* TODO: handle Reject UPIU Response */
1861 err = -EPERM;
1862 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1863 __func__);
1864 break;
1865 default:
1866 err = -EINVAL;
1867 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1868 __func__, resp);
1869 break;
1870 }
1871
1872 return err;
1873}
1874
1875static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1876 struct ufshcd_lrb *lrbp, int max_timeout)
1877{
1878 int err = 0;
1879 unsigned long time_left;
1880 unsigned long flags;
1881
1882 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1883 msecs_to_jiffies(max_timeout));
1884
ad1a1b9c
GB		 1885 /* Make sure descriptors are ready before ringing the doorbell */
1886 wmb();
5a0b0cb9
SRT		 1887 spin_lock_irqsave(hba->host->host_lock, flags);
1888 hba->dev_cmd.complete = NULL;
1889 if (likely(time_left)) {
1890 err = ufshcd_get_tr_ocs(lrbp);
1891 if (!err)
1892 err = ufshcd_dev_cmd_completion(hba, lrbp);
1893 }
1894 spin_unlock_irqrestore(hba->host->host_lock, flags);
1895
1896 if (!time_left) {
1897 err = -ETIMEDOUT;
a48353f6
YG		 1898 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1899 __func__, lrbp->task_tag);
5a0b0cb9 1900 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1901 /* successfully cleared the command, retry if needed */
5a0b0cb9 1902 err = -EAGAIN;
a48353f6
YG		 1903 /*
1904 * in case of an error, after clearing the doorbell,
1905 * we also need to clear the outstanding_request
1906 * field in hba
1907 */
1908 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1909 }
1910
1911 return err;
1912}
1913
1914/**
1915 * ufshcd_get_dev_cmd_tag - Get device management command tag
1916 * @hba: per-adapter instance
1917 * @tag: pointer to variable with available slot value
1918 *
1919 * Get a free slot and lock it until device management command
1920 * completes.
1921 *
1922 * Returns false if free slot is unavailable for locking, else
1923 * return true with tag value in @tag.
1924 */
1925static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1926{
1927 int tag;
1928 bool ret = false;
1929 unsigned long tmp;
1930
1931 if (!tag_out)
1932 goto out;
1933
1934 do {
1935 tmp = ~hba->lrb_in_use;
1936 tag = find_last_bit(&tmp, hba->nutrs);
1937 if (tag >= hba->nutrs)
1938 goto out;
1939 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1940
1941 *tag_out = tag;
1942 ret = true;
1943out:
1944 return ret;
1945}
1946
1947static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1948{
1949 clear_bit_unlock(tag, &hba->lrb_in_use);
1950}
1951
1952/**
1953 * ufshcd_exec_dev_cmd - API for sending device management requests
1954 * @hba - UFS hba
1955 * @cmd_type - specifies the type (NOP, Query...)
1956 * @timeout - time in seconds
1957 *
68078d5c
DR		 1958 * NOTE: Since there is only one available tag for device management commands,
1959 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1960 */
1961static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1962 enum dev_cmd_type cmd_type, int timeout)
1963{
1964 struct ufshcd_lrb *lrbp;
1965 int err;
1966 int tag;
1967 struct completion wait;
1968 unsigned long flags;
1969
1970 /*
1971 * Get free slot, sleep if slots are unavailable.
1972 * Even though we use wait_event() which sleeps indefinitely,
1973 * the maximum wait time is bounded by SCSI request timeout.
1974 */
1975 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1976
1977 init_completion(&wait);
1978 lrbp = &hba->lrb[tag];
1979 WARN_ON(lrbp->cmd);
1980 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1981 if (unlikely(err))
1982 goto out_put_tag;
1983
1984 hba->dev_cmd.complete = &wait;
1985
e3dfdc53
YG		 1986 /* Make sure descriptors are ready before ringing the doorbell */
1987 wmb();
5a0b0cb9 1988 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1989 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 1990 ufshcd_send_command(hba, tag);
1991 spin_unlock_irqrestore(hba->host->host_lock, flags);
1992
1993 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1994
1995out_put_tag:
1996 ufshcd_put_dev_cmd_tag(hba, tag);
1997 wake_up(&hba->dev_cmd.tag_wq);
1998 return err;
1999}
2000
d44a5f98
DR		 2001/**
2002 * ufshcd_init_query() - init the query response and request parameters
2003 * @hba: per-adapter instance
2004 * @request: address of the request pointer to be initialized
2005 * @response: address of the response pointer to be initialized
2006 * @opcode: operation to perform
2007 * @idn: flag idn to access
2008 * @index: LU number to access
2009 * @selector: query/flag/descriptor further identification
2010 */
2011static inline void ufshcd_init_query(struct ufs_hba *hba,
2012 struct ufs_query_req **request, struct ufs_query_res **response,
2013 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2014{
2015 *request = &hba->dev_cmd.query.request;
2016 *response = &hba->dev_cmd.query.response;
2017 memset(*request, 0, sizeof(struct ufs_query_req));
2018 memset(*response, 0, sizeof(struct ufs_query_res));
2019 (*request)->upiu_req.opcode = opcode;
2020 (*request)->upiu_req.idn = idn;
2021 (*request)->upiu_req.index = index;
2022 (*request)->upiu_req.selector = selector;
2023}
2024
dc3c8d3a
YG		 2025static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2026 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2027{
2028 int ret;
2029 int retries;
2030
2031 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2032 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2033 if (ret)
2034 dev_dbg(hba->dev,
2035 "%s: failed with error %d, retries %d\n",
2036 __func__, ret, retries);
2037 else
2038 break;
2039 }
2040
2041 if (ret)
2042 dev_err(hba->dev,
2043 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2044 __func__, opcode, idn, ret, retries);
2045 return ret;
2046}
2047
68078d5c
DR		 2048/**
2049 * ufshcd_query_flag() - API function for sending flag query requests
2050 * hba: per-adapter instance
2051 * query_opcode: flag query to perform
2052 * idn: flag idn to access
2053 * flag_res: the flag value after the query request completes
2054 *
2055 * Returns 0 for success, non-zero in case of failure
2056 */
dc3c8d3a 2057int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2058 enum flag_idn idn, bool *flag_res)
2059{
d44a5f98
DR		 2060 struct ufs_query_req *request = NULL;
2061 struct ufs_query_res *response = NULL;
2062 int err, index = 0, selector = 0;
e5ad406c 2063 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2064
2065 BUG_ON(!hba);
2066
1ab27c9c 2067 ufshcd_hold(hba, false);
68078d5c 2068 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2069 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2070 selector);
68078d5c
DR		 2071
2072 switch (opcode) {
2073 case UPIU_QUERY_OPCODE_SET_FLAG:
2074 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2075 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2076 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2077 break;
2078 case UPIU_QUERY_OPCODE_READ_FLAG:
2079 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2080 if (!flag_res) {
2081 /* No dummy reads */
2082 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2083 __func__);
2084 err = -EINVAL;
2085 goto out_unlock;
2086 }
2087 break;
2088 default:
2089 dev_err(hba->dev,
2090 "%s: Expected query flag opcode but got = %d\n",
2091 __func__, opcode);
2092 err = -EINVAL;
2093 goto out_unlock;
2094 }
68078d5c 2095
e5ad406c 2096 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2097
2098 if (err) {
2099 dev_err(hba->dev,
2100 "%s: Sending flag query for idn %d failed, err = %d\n",
2101 __func__, idn, err);
2102 goto out_unlock;
2103 }
2104
2105 if (flag_res)
e8c8e82a 2106 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2107 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2108
2109out_unlock:
2110 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2111 ufshcd_release(hba);
68078d5c
DR		 2112 return err;
2113}
2114
66ec6d59
SRT		 2115/**
2116 * ufshcd_query_attr - API function for sending attribute requests
2117 * hba: per-adapter instance
2118 * opcode: attribute opcode
2119 * idn: attribute idn to access
2120 * index: index field
2121 * selector: selector field
2122 * attr_val: the attribute value after the query request completes
2123 *
2124 * Returns 0 for success, non-zero in case of failure
2125*/
bdbe5d2f 2126static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2127 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2128{
d44a5f98
DR		 2129 struct ufs_query_req *request = NULL;
2130 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2131 int err;
2132
2133 BUG_ON(!hba);
2134
1ab27c9c 2135 ufshcd_hold(hba, false);
66ec6d59
SRT		 2136 if (!attr_val) {
2137 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2138 __func__, opcode);
2139 err = -EINVAL;
2140 goto out;
2141 }
2142
2143 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2144 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2145 selector);
66ec6d59
SRT		 2146
2147 switch (opcode) {
2148 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2149 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2150 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2151 break;
2152 case UPIU_QUERY_OPCODE_READ_ATTR:
2153 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2154 break;
2155 default:
2156 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2157 __func__, opcode);
2158 err = -EINVAL;
2159 goto out_unlock;
2160 }
2161
d44a5f98 2162 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2163
2164 if (err) {
4b761b58
YG		 2165 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2166 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2167 goto out_unlock;
2168 }
2169
e8c8e82a 2170 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2171
2172out_unlock:
2173 mutex_unlock(&hba->dev_cmd.lock);
2174out:
1ab27c9c 2175 ufshcd_release(hba);
66ec6d59
SRT		 2176 return err;
2177}
2178
5e86ae44
YG		 2179/**
2180 * ufshcd_query_attr_retry() - API function for sending query
2181 * attribute with retries
2182 * @hba: per-adapter instance
2183 * @opcode: attribute opcode
2184 * @idn: attribute idn to access
2185 * @index: index field
2186 * @selector: selector field
2187 * @attr_val: the attribute value after the query request
2188 * completes
2189 *
2190 * Returns 0 for success, non-zero in case of failure
2191*/
2192static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2193 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2194 u32 *attr_val)
2195{
2196 int ret = 0;
2197 u32 retries;
2198
2199 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2200 ret = ufshcd_query_attr(hba, opcode, idn, index,
2201 selector, attr_val);
2202 if (ret)
2203 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2204 __func__, ret, retries);
2205 else
2206 break;
2207 }
2208
2209 if (ret)
2210 dev_err(hba->dev,
2211 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2212 __func__, idn, ret, QUERY_REQ_RETRIES);
2213 return ret;
2214}
2215
a70e91b8 2216static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2217 enum query_opcode opcode, enum desc_idn idn, u8 index,
2218 u8 selector, u8 *desc_buf, int *buf_len)
2219{
2220 struct ufs_query_req *request = NULL;
2221 struct ufs_query_res *response = NULL;
2222 int err;
2223
2224 BUG_ON(!hba);
2225
1ab27c9c 2226 ufshcd_hold(hba, false);
d44a5f98
DR		 2227 if (!desc_buf) {
2228 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2229 __func__, opcode);
2230 err = -EINVAL;
2231 goto out;
2232 }
2233
2234 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2235 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2236 __func__, *buf_len);
2237 err = -EINVAL;
2238 goto out;
2239 }
2240
2241 mutex_lock(&hba->dev_cmd.lock);
2242 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2243 selector);
2244 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2245 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2246
2247 switch (opcode) {
2248 case UPIU_QUERY_OPCODE_WRITE_DESC:
2249 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2250 break;
2251 case UPIU_QUERY_OPCODE_READ_DESC:
2252 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2253 break;
2254 default:
2255 dev_err(hba->dev,
2256 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2257 __func__, opcode);
2258 err = -EINVAL;
2259 goto out_unlock;
2260 }
2261
2262 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2263
2264 if (err) {
4b761b58
YG		 2265 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2266 __func__, opcode, idn, index, err);
d44a5f98
DR		 2267 goto out_unlock;
2268 }
2269
2270 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2271 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2272
2273out_unlock:
2274 mutex_unlock(&hba->dev_cmd.lock);
2275out:
1ab27c9c 2276 ufshcd_release(hba);
d44a5f98
DR		 2277 return err;
2278}
2279
a70e91b8
YG		 2280/**
2281 * ufshcd_query_descriptor_retry - API function for sending descriptor
2282 * requests
2283 * hba: per-adapter instance
2284 * opcode: attribute opcode
2285 * idn: attribute idn to access
2286 * index: index field
2287 * selector: selector field
2288 * desc_buf: the buffer that contains the descriptor
2289 * buf_len: length parameter passed to the device
2290 *
2291 * Returns 0 for success, non-zero in case of failure.
2292 * The buf_len parameter will contain, on return, the length parameter
2293 * received on the response.
2294 */
2295int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2296 enum query_opcode opcode, enum desc_idn idn, u8 index,
2297 u8 selector, u8 *desc_buf, int *buf_len)
2298{
2299 int err;
2300 int retries;
2301
2302 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2303 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2304 selector, desc_buf, buf_len);
2305 if (!err || err == -EINVAL)
2306 break;
2307 }
2308
2309 return err;
2310}
2311EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2312
da461cec
SJ		 2313/**
2314 * ufshcd_read_desc_param - read the specified descriptor parameter
2315 * @hba: Pointer to adapter instance
2316 * @desc_id: descriptor idn value
2317 * @desc_index: descriptor index
2318 * @param_offset: offset of the parameter to read
2319 * @param_read_buf: pointer to buffer where parameter would be read
2320 * @param_size: sizeof(param_read_buf)
2321 *
2322 * Return 0 in case of success, non-zero otherwise
2323 */
2324static int ufshcd_read_desc_param(struct ufs_hba *hba,
2325 enum desc_idn desc_id,
2326 int desc_index,
2327 u32 param_offset,
2328 u8 *param_read_buf,
2329 u32 param_size)
2330{
2331 int ret;
2332 u8 *desc_buf;
2333 u32 buff_len;
2334 bool is_kmalloc = true;
2335
2336 /* safety checks */
2337 if (desc_id >= QUERY_DESC_IDN_MAX)
2338 return -EINVAL;
2339
2340 buff_len = ufs_query_desc_max_size[desc_id];
2341 if ((param_offset + param_size) > buff_len)
2342 return -EINVAL;
2343
2344 if (!param_offset && (param_size == buff_len)) {
2345 /* memory space already available to hold full descriptor */
2346 desc_buf = param_read_buf;
2347 is_kmalloc = false;
2348 } else {
2349 /* allocate memory to hold full descriptor */
2350 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2351 if (!desc_buf)
2352 return -ENOMEM;
2353 }
2354
a70e91b8
YG		 2355 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2356 desc_id, desc_index, 0, desc_buf,
2357 &buff_len);
da461cec 2358
bde44bb6 2359 if (ret) {
2360 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2361 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 2362
2363 goto out;
2364 }
2365
bde44bb6 2366 /* Sanity check */
2367 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2368 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2369 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2370 ret = -EINVAL;
2371 goto out;
2372 }
2373
2374 /*
2375 * While reading variable size descriptors (like string descriptor),
2376 * some UFS devices may report the "LENGTH" (field in "Transaction
2377 * Specific fields" of Query Response UPIU) same as what was requested
2378 * in Query Request UPIU instead of reporting the actual size of the
2379 * variable size descriptor.
2380 * Although it's safe to ignore the "LENGTH" field for variable size
2381 * descriptors as we can always derive the length of the descriptor from
2382 * the descriptor header fields. Hence this change impose the length
2383 * match check only for fixed size descriptors (for which we always
2384 * request the correct size as part of Query Request UPIU).
2385 */
2386 if ((desc_id != QUERY_DESC_IDN_STRING) &&
2387 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
2388 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
2389 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
2390 ret = -EINVAL;
2391 goto out;
2392 }
2393
da461cec
SJ		 2394 if (is_kmalloc)
2395 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2396out:
2397 if (is_kmalloc)
2398 kfree(desc_buf);
2399 return ret;
2400}
2401
2402static inline int ufshcd_read_desc(struct ufs_hba *hba,
2403 enum desc_idn desc_id,
2404 int desc_index,
2405 u8 *buf,
2406 u32 size)
2407{
2408 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2409}
2410
2411static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2412 u8 *buf,
2413 u32 size)
2414{
61e07359
DR		 2415 int err = 0;
2416 int retries;
2417
2418 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2419 /* Read descriptor*/
2420 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2421 if (!err)
2422 break;
2423 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2424 }
2425
2426 return err;
da461cec
SJ		 2427}
2428
b573d484
YG		 2429int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2430{
2431 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2432}
2433EXPORT_SYMBOL(ufshcd_read_device_desc);
2434
2435/**
2436 * ufshcd_read_string_desc - read string descriptor
2437 * @hba: pointer to adapter instance
2438 * @desc_index: descriptor index
2439 * @buf: pointer to buffer where descriptor would be read
2440 * @size: size of buf
2441 * @ascii: if true convert from unicode to ascii characters
2442 *
2443 * Return 0 in case of success, non-zero otherwise
2444 */
2445int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2446 u32 size, bool ascii)
2447{
2448 int err = 0;
2449
2450 err = ufshcd_read_desc(hba,
2451 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2452
2453 if (err) {
2454 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2455 __func__, QUERY_REQ_RETRIES, err);
2456 goto out;
2457 }
2458
2459 if (ascii) {
2460 int desc_len;
2461 int ascii_len;
2462 int i;
2463 char *buff_ascii;
2464
2465 desc_len = buf[0];
2466 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2467 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2468 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2469 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2470 __func__);
2471 err = -ENOMEM;
2472 goto out;
2473 }
2474
2475 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2476 if (!buff_ascii) {
2477 err = -ENOMEM;
fcbefc3b 2478 goto out;
b573d484
YG		 2479 }
2480
2481 /*
2482 * the descriptor contains string in UTF16 format
2483 * we need to convert to utf-8 so it can be displayed
2484 */
2485 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2486 desc_len - QUERY_DESC_HDR_SIZE,
2487 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2488
2489 /* replace non-printable or non-ASCII characters with spaces */
2490 for (i = 0; i < ascii_len; i++)
2491 ufshcd_remove_non_printable(&buff_ascii[i]);
2492
2493 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2494 size - QUERY_DESC_HDR_SIZE);
2495 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2496 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 2497 kfree(buff_ascii);
2498 }
2499out:
2500 return err;
2501}
2502EXPORT_SYMBOL(ufshcd_read_string_desc);
2503
da461cec
SJ		 2504/**
2505 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2506 * @hba: Pointer to adapter instance
2507 * @lun: lun id
2508 * @param_offset: offset of the parameter to read
2509 * @param_read_buf: pointer to buffer where parameter would be read
2510 * @param_size: sizeof(param_read_buf)
2511 *
2512 * Return 0 in case of success, non-zero otherwise
2513 */
2514static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2515 int lun,
2516 enum unit_desc_param param_offset,
2517 u8 *param_read_buf,
2518 u32 param_size)
2519{
2520 /*
2521 * Unit descriptors are only available for general purpose LUs (LUN id
2522 * from 0 to 7) and RPMB Well known LU.
2523 */
0ce147d4 2524 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 2525 return -EOPNOTSUPP;
2526
2527 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2528 param_offset, param_read_buf, param_size);
2529}
2530
7a3e97b0
SY		 2531/**
2532 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2533 * @hba: per adapter instance
2534 *
2535 * 1. Allocate DMA memory for Command Descriptor array
2536 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2537 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2538 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2539 * (UTMRDL)
2540 * 4. Allocate memory for local reference block(lrb).
2541 *
2542 * Returns 0 for success, non-zero in case of failure
2543 */
2544static int ufshcd_memory_alloc(struct ufs_hba *hba)
2545{
2546 size_t utmrdl_size, utrdl_size, ucdl_size;
2547
2548 /* Allocate memory for UTP command descriptors */
2549 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 2550 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2551 ucdl_size,
2552 &hba->ucdl_dma_addr,
2553 GFP_KERNEL);
7a3e97b0
SY		 2554
2555 /*
2556 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2557 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2558 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2559 * be aligned to 128 bytes as well
2560 */
2561 if (!hba->ucdl_base_addr ||
2562 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2563 dev_err(hba->dev,
7a3e97b0
SY		 2564 "Command Descriptor Memory allocation failed\n");
2565 goto out;
2566 }
2567
2568 /*
2569 * Allocate memory for UTP Transfer descriptors
2570 * UFSHCI requires 1024 byte alignment of UTRD
2571 */
2572 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2573 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2574 utrdl_size,
2575 &hba->utrdl_dma_addr,
2576 GFP_KERNEL);
7a3e97b0
SY		 2577 if (!hba->utrdl_base_addr ||
2578 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2579 dev_err(hba->dev,
7a3e97b0
SY		 2580 "Transfer Descriptor Memory allocation failed\n");
2581 goto out;
2582 }
2583
2584 /*
2585 * Allocate memory for UTP Task Management descriptors
2586 * UFSHCI requires 1024 byte alignment of UTMRD
2587 */
2588 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2589 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2590 utmrdl_size,
2591 &hba->utmrdl_dma_addr,
2592 GFP_KERNEL);
7a3e97b0
SY		 2593 if (!hba->utmrdl_base_addr ||
2594 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2595 dev_err(hba->dev,
7a3e97b0
SY		 2596 "Task Management Descriptor Memory allocation failed\n");
2597 goto out;
2598 }
2599
2600 /* Allocate memory for local reference block */
2953f850
SJ		 2601 hba->lrb = devm_kzalloc(hba->dev,
2602 hba->nutrs * sizeof(struct ufshcd_lrb),
2603 GFP_KERNEL);
7a3e97b0 2604 if (!hba->lrb) {
3b1d0580 2605 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2606 goto out;
2607 }
2608 return 0;
2609out:
7a3e97b0
SY		 2610 return -ENOMEM;
2611}
2612
66cc820f
DR		 2613/**
2614 * ufshcd_print_pwr_info - print power params as saved in hba
2615 * power info
2616 * @hba: per-adapter instance
2617 */
2618static void ufshcd_print_pwr_info(struct ufs_hba *hba)
2619{
2620 static const char * const names[] = {
2621 "INVALID MODE",
2622 "FAST MODE",
2623 "SLOW_MODE",
2624 "INVALID MODE",
2625 "FASTAUTO_MODE",
2626 "SLOWAUTO_MODE",
2627 "INVALID MODE",
2628 };
2629
2630 dev_info(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
2631 __func__,
2632 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
2633 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
2634 names[hba->pwr_info.pwr_rx],
2635 names[hba->pwr_info.pwr_tx],
2636 hba->pwr_info.hs_rate);
2637}
2638
7a3e97b0
SY		 2639/**
2640 * ufshcd_host_memory_configure - configure local reference block with
2641 * memory offsets
2642 * @hba: per adapter instance
2643 *
2644 * Configure Host memory space
2645 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2646 * address.
2647 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2648 * and PRDT offset.
2649 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2650 * into local reference block.
2651 */
2652static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2653{
2654 struct utp_transfer_cmd_desc *cmd_descp;
2655 struct utp_transfer_req_desc *utrdlp;
2656 dma_addr_t cmd_desc_dma_addr;
2657 dma_addr_t cmd_desc_element_addr;
2658 u16 response_offset;
2659 u16 prdt_offset;
2660 int cmd_desc_size;
2661 int i;
2662
2663 utrdlp = hba->utrdl_base_addr;
2664 cmd_descp = hba->ucdl_base_addr;
2665
2666 response_offset =
2667 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2668 prdt_offset =
2669 offsetof(struct utp_transfer_cmd_desc, prd_table);
2670
2671 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2672 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2673
2674 for (i = 0; i < hba->nutrs; i++) {
2675 /* Configure UTRD with command descriptor base address */
2676 cmd_desc_element_addr =
2677 (cmd_desc_dma_addr + (cmd_desc_size * i));
2678 utrdlp[i].command_desc_base_addr_lo =
2679 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2680 utrdlp[i].command_desc_base_addr_hi =
2681 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2682
2683 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 2684 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
2685 utrdlp[i].response_upiu_offset =
2686 cpu_to_le16(response_offset);
2687 utrdlp[i].prd_table_offset =
2688 cpu_to_le16(prdt_offset);
2689 utrdlp[i].response_upiu_length =
2690 cpu_to_le16(ALIGNED_UPIU_SIZE);
2691 } else {
2692 utrdlp[i].response_upiu_offset =
7a3e97b0 2693 cpu_to_le16((response_offset >> 2));
75b1cc4a 2694 utrdlp[i].prd_table_offset =
7a3e97b0 2695 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 2696 utrdlp[i].response_upiu_length =
3ca316c5 2697 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 2698 }
7a3e97b0
SY		 2699
2700 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2701 hba->lrb[i].ucd_req_ptr =
2702 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2703 hba->lrb[i].ucd_rsp_ptr =
2704 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2705 hba->lrb[i].ucd_prdt_ptr =
2706 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2707 }
2708}
2709
2710/**
2711 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2712 * @hba: per adapter instance
2713 *
2714 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2715 * in order to initialize the Unipro link startup procedure.
2716 * Once the Unipro links are up, the device connected to the controller
2717 * is detected.
2718 *
2719 * Returns 0 on success, non-zero value on failure
2720 */
2721static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2722{
6ccf44fe
SJ		 2723 struct uic_command uic_cmd = {0};
2724 int ret;
7a3e97b0 2725
6ccf44fe 2726 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2727
6ccf44fe
SJ		 2728 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2729 if (ret)
2730 dev_err(hba->dev,
2731 "dme-link-startup: error code %d\n", ret);
2732 return ret;
7a3e97b0
SY		 2733}
2734
cad2e03d
YG		 2735static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2736{
2737 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2738 unsigned long min_sleep_time_us;
2739
2740 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2741 return;
2742
2743 /*
2744 * last_dme_cmd_tstamp will be 0 only for 1st call to
2745 * this function
2746 */
2747 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2748 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2749 } else {
2750 unsigned long delta =
2751 (unsigned long) ktime_to_us(
2752 ktime_sub(ktime_get(),
2753 hba->last_dme_cmd_tstamp));
2754
2755 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2756 min_sleep_time_us =
2757 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2758 else
2759 return; /* no more delay required */
2760 }
2761
2762 /* allow sleep for extra 50us if needed */
2763 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2764}
2765
12b4fdb4
SJ		 2766/**
2767 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2768 * @hba: per adapter instance
2769 * @attr_sel: uic command argument1
2770 * @attr_set: attribute set type as uic command argument2
2771 * @mib_val: setting value as uic command argument3
2772 * @peer: indicate whether peer or local
2773 *
2774 * Returns 0 on success, non-zero value on failure
2775 */
2776int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2777 u8 attr_set, u32 mib_val, u8 peer)
2778{
2779 struct uic_command uic_cmd = {0};
2780 static const char *const action[] = {
2781 "dme-set",
2782 "dme-peer-set"
2783 };
2784 const char *set = action[!!peer];
2785 int ret;
64238fbd 2786 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 2787
2788 uic_cmd.command = peer ?
2789 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2790 uic_cmd.argument1 = attr_sel;
2791 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2792 uic_cmd.argument3 = mib_val;
2793
64238fbd
YG		 2794 do {
2795 /* for peer attributes we retry upon failure */
2796 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2797 if (ret)
2798 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2799 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2800 } while (ret && peer && --retries);
2801
f37e9f8c 2802 if (ret)
64238fbd 2803 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 2804 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2805 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 2806
2807 return ret;
2808}
2809EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2810
2811/**
2812 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2813 * @hba: per adapter instance
2814 * @attr_sel: uic command argument1
2815 * @mib_val: the value of the attribute as returned by the UIC command
2816 * @peer: indicate whether peer or local
2817 *
2818 * Returns 0 on success, non-zero value on failure
2819 */
2820int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2821 u32 *mib_val, u8 peer)
2822{
2823 struct uic_command uic_cmd = {0};
2824 static const char *const action[] = {
2825 "dme-get",
2826 "dme-peer-get"
2827 };
2828 const char *get = action[!!peer];
2829 int ret;
64238fbd 2830 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 2831 struct ufs_pa_layer_attr orig_pwr_info;
2832 struct ufs_pa_layer_attr temp_pwr_info;
2833 bool pwr_mode_change = false;
2834
2835 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2836 orig_pwr_info = hba->pwr_info;
2837 temp_pwr_info = orig_pwr_info;
2838
2839 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2840 orig_pwr_info.pwr_rx == FAST_MODE) {
2841 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2842 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2843 pwr_mode_change = true;
2844 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2845 orig_pwr_info.pwr_rx == SLOW_MODE) {
2846 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2847 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2848 pwr_mode_change = true;
2849 }
2850 if (pwr_mode_change) {
2851 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2852 if (ret)
2853 goto out;
2854 }
2855 }
12b4fdb4
SJ		 2856
2857 uic_cmd.command = peer ?
2858 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2859 uic_cmd.argument1 = attr_sel;
2860
64238fbd
YG		 2861 do {
2862 /* for peer attributes we retry upon failure */
2863 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2864 if (ret)
2865 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2866 get, UIC_GET_ATTR_ID(attr_sel), ret);
2867 } while (ret && peer && --retries);
2868
f37e9f8c 2869 if (ret)
64238fbd 2870 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 2871 get, UIC_GET_ATTR_ID(attr_sel),
2872 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 2873
64238fbd 2874 if (mib_val && !ret)
12b4fdb4 2875 *mib_val = uic_cmd.argument3;
874237f7
YG		 2876
2877 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2878 && pwr_mode_change)
2879 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2880out:
2881 return ret;
2882}
2883EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2884
53b3d9c3 2885/**
57d104c1
SJ		 2886 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2887 * state) and waits for it to take effect.
2888 *
53b3d9c3 2889 * @hba: per adapter instance
57d104c1
SJ		 2890 * @cmd: UIC command to execute
2891 *
2892 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2893 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2894 * and device UniPro link and hence it's final completion would be indicated by
2895 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2896 * addition to normal UIC command completion Status (UCCS). This function only
2897 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2898 *
2899 * Returns 0 on success, non-zero value on failure
2900 */
57d104c1 2901static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2902{
57d104c1 2903 struct completion uic_async_done;
53b3d9c3
SJ		 2904 unsigned long flags;
2905 u8 status;
2906 int ret;
d75f7fe4 2907 bool reenable_intr = false;
53b3d9c3 2908
53b3d9c3 2909 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2910 init_completion(&uic_async_done);
cad2e03d 2911 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2912
2913 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2914 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 2915 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2916 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2917 /*
2918 * Make sure UIC command completion interrupt is disabled before
2919 * issuing UIC command.
2920 */
2921 wmb();
2922 reenable_intr = true;
57d104c1 2923 }
d75f7fe4
YG		 2924 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2925 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 2926 if (ret) {
2927 dev_err(hba->dev,
2928 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2929 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2930 goto out;
2931 }
2932
57d104c1 2933 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2934 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2935 dev_err(hba->dev,
57d104c1
SJ		 2936 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2937 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2938 ret = -ETIMEDOUT;
2939 goto out;
2940 }
2941
2942 status = ufshcd_get_upmcrs(hba);
2943 if (status != PWR_LOCAL) {
2944 dev_err(hba->dev,
73615428 2945 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2946 cmd->command, status);
53b3d9c3
SJ		 2947 ret = (status != PWR_OK) ? status : -1;
2948 }
2949out:
2950 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2951 hba->active_uic_cmd = NULL;
57d104c1 2952 hba->uic_async_done = NULL;
d75f7fe4
YG		 2953 if (reenable_intr)
2954 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 2955 spin_unlock_irqrestore(hba->host->host_lock, flags);
2956 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2957
53b3d9c3
SJ		 2958 return ret;
2959}
2960
57d104c1
SJ		 2961/**
2962 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2963 * using DME_SET primitives.
2964 * @hba: per adapter instance
2965 * @mode: powr mode value
2966 *
2967 * Returns 0 on success, non-zero value on failure
2968 */
2969static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2970{
2971 struct uic_command uic_cmd = {0};
1ab27c9c 2972 int ret;
57d104c1 2973
c3a2f9ee
YG		 2974 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2975 ret = ufshcd_dme_set(hba,
2976 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2977 if (ret) {
2978 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2979 __func__, ret);
2980 goto out;
2981 }
2982 }
2983
57d104c1
SJ		 2984 uic_cmd.command = UIC_CMD_DME_SET;
2985 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2986 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2987 ufshcd_hold(hba, false);
2988 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2989 ufshcd_release(hba);
57d104c1 2990
c3a2f9ee 2991out:
1ab27c9c 2992 return ret;
57d104c1
SJ		 2993}
2994
53c12d0e
YG		 2995static int ufshcd_link_recovery(struct ufs_hba *hba)
2996{
2997 int ret;
2998 unsigned long flags;
2999
3000 spin_lock_irqsave(hba->host->host_lock, flags);
3001 hba->ufshcd_state = UFSHCD_STATE_RESET;
3002 ufshcd_set_eh_in_progress(hba);
3003 spin_unlock_irqrestore(hba->host->host_lock, flags);
3004
3005 ret = ufshcd_host_reset_and_restore(hba);
3006
3007 spin_lock_irqsave(hba->host->host_lock, flags);
3008 if (ret)
3009 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3010 ufshcd_clear_eh_in_progress(hba);
3011 spin_unlock_irqrestore(hba->host->host_lock, flags);
3012
3013 if (ret)
3014 dev_err(hba->dev, "%s: link recovery failed, err %d",
3015 __func__, ret);
3016
3017 return ret;
3018}
3019
87d0b4a6 3020static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3021{
87d0b4a6 3022 int ret;
57d104c1
SJ		 3023 struct uic_command uic_cmd = {0};
3024
ee32c909
KK		 3025 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3026
57d104c1 3027 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG		 3028 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3029
53c12d0e 3030 if (ret) {
87d0b4a6
YG		 3031 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3032 __func__, ret);
3033
53c12d0e
YG		 3034 /*
3035 * If link recovery fails then return error so that caller
3036 * don't retry the hibern8 enter again.
3037 */
3038 if (ufshcd_link_recovery(hba))
3039 ret = -ENOLINK;
ee32c909
KK		 3040 } else
3041 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3042 POST_CHANGE);
53c12d0e 3043
87d0b4a6
YG		 3044 return ret;
3045}
3046
3047static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3048{
3049 int ret = 0, retries;
57d104c1 3050
87d0b4a6
YG		 3051 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3052 ret = __ufshcd_uic_hibern8_enter(hba);
3053 if (!ret || ret == -ENOLINK)
3054 goto out;
3055 }
3056out:
3057 return ret;
57d104c1
SJ		 3058}
3059
3060static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3061{
3062 struct uic_command uic_cmd = {0};
3063 int ret;
3064
ee32c909
KK		 3065 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3066
57d104c1
SJ		 3067 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3068 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3069 if (ret) {
53c12d0e
YG		 3070 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3071 __func__, ret);
3072 ret = ufshcd_link_recovery(hba);
ee32c909
KK		 3073 } else
3074 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3075 POST_CHANGE);
57d104c1
SJ		 3076
3077 return ret;
3078}
3079
5064636c
YG		 3080 /**
3081 * ufshcd_init_pwr_info - setting the POR (power on reset)
3082 * values in hba power info
3083 * @hba: per-adapter instance
3084 */
3085static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3086{
3087 hba->pwr_info.gear_rx = UFS_PWM_G1;
3088 hba->pwr_info.gear_tx = UFS_PWM_G1;
3089 hba->pwr_info.lane_rx = 1;
3090 hba->pwr_info.lane_tx = 1;
3091 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3092 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3093 hba->pwr_info.hs_rate = 0;
3094}
3095
d3e89bac 3096/**
7eb584db
DR		 3097 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3098 * @hba: per-adapter instance
d3e89bac 3099 */
7eb584db 3100static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3101{
7eb584db
DR		 3102 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3103
3104 if (hba->max_pwr_info.is_valid)
3105 return 0;
3106
2349b533 3107 pwr_info->pwr_tx = FAST_MODE;
3108 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3109 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3110
3111 /* Get the connected lane count */
7eb584db
DR		 3112 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3113 &pwr_info->lane_rx);
3114 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3115 &pwr_info->lane_tx);
3116
3117 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3118 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3119 __func__,
3120 pwr_info->lane_rx,
3121 pwr_info->lane_tx);
3122 return -EINVAL;
3123 }
d3e89bac
SJ		 3124
3125 /*
3126 * First, get the maximum gears of HS speed.
3127 * If a zero value, it means there is no HSGEAR capability.
3128 * Then, get the maximum gears of PWM speed.
3129 */
7eb584db
DR		 3130 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3131 if (!pwr_info->gear_rx) {
3132 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3133 &pwr_info->gear_rx);
3134 if (!pwr_info->gear_rx) {
3135 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3136 __func__, pwr_info->gear_rx);
3137 return -EINVAL;
3138 }
2349b533 3139 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3140 }
3141
7eb584db
DR		 3142 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3143 &pwr_info->gear_tx);
3144 if (!pwr_info->gear_tx) {
d3e89bac 3145 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3146 &pwr_info->gear_tx);
3147 if (!pwr_info->gear_tx) {
3148 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3149 __func__, pwr_info->gear_tx);
3150 return -EINVAL;
3151 }
2349b533 3152 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3153 }
3154
3155 hba->max_pwr_info.is_valid = true;
3156 return 0;
3157}
3158
3159static int ufshcd_change_power_mode(struct ufs_hba *hba,
3160 struct ufs_pa_layer_attr *pwr_mode)
3161{
3162 int ret;
3163
3164 /* if already configured to the requested pwr_mode */
3165 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3166 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3167 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3168 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3169 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3170 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3171 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3172 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3173 return 0;
d3e89bac
SJ		 3174 }
3175
3176 /*
3177 * Configure attributes for power mode change with below.
3178 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3179 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3180 * - PA_HSSERIES
3181 */
7eb584db
DR		 3182 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3183 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3184 pwr_mode->lane_rx);
3185 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3186 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3187 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 3188 else
3189 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3190
7eb584db
DR		 3191 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3192 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3193 pwr_mode->lane_tx);
3194 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3195 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 3196 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 3197 else
3198 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 3199
7eb584db
DR		 3200 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3201 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3202 pwr_mode->pwr_rx == FAST_MODE ||
3203 pwr_mode->pwr_tx == FAST_MODE)
3204 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3205 pwr_mode->hs_rate);
d3e89bac 3206
7eb584db
DR		 3207 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3208 | pwr_mode->pwr_tx);
3209
3210 if (ret) {
d3e89bac 3211 dev_err(hba->dev,
7eb584db
DR		 3212 "%s: power mode change failed %d\n", __func__, ret);
3213 } else {
0263bcd0
YG		 3214 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3215 pwr_mode);
7eb584db
DR		 3216
3217 memcpy(&hba->pwr_info, pwr_mode,
3218 sizeof(struct ufs_pa_layer_attr));
3219 }
3220
66cc820f
DR		 3221 ufshcd_print_pwr_info(hba);
3222
7eb584db
DR		 3223 return ret;
3224}
3225
3226/**
3227 * ufshcd_config_pwr_mode - configure a new power mode
3228 * @hba: per-adapter instance
3229 * @desired_pwr_mode: desired power configuration
3230 */
3231static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3232 struct ufs_pa_layer_attr *desired_pwr_mode)
3233{
3234 struct ufs_pa_layer_attr final_params = { 0 };
3235 int ret;
3236
0263bcd0
YG		 3237 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3238 desired_pwr_mode, &final_params);
3239
3240 if (ret)
7eb584db
DR		 3241 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3242
3243 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 3244
3245 return ret;
3246}
3247
68078d5c
DR		 3248/**
3249 * ufshcd_complete_dev_init() - checks device readiness
3250 * hba: per-adapter instance
3251 *
3252 * Set fDeviceInit flag and poll until device toggles it.
3253 */
3254static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3255{
dc3c8d3a
YG		 3256 int i;
3257 int err;
68078d5c
DR		 3258 bool flag_res = 1;
3259
dc3c8d3a
YG		 3260 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3261 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 3262 if (err) {
3263 dev_err(hba->dev,
3264 "%s setting fDeviceInit flag failed with error %d\n",
3265 __func__, err);
3266 goto out;
3267 }
3268
dc3c8d3a
YG		 3269 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3270 for (i = 0; i < 1000 && !err && flag_res; i++)
3271 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3272 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3273
68078d5c
DR		 3274 if (err)
3275 dev_err(hba->dev,
3276 "%s reading fDeviceInit flag failed with error %d\n",
3277 __func__, err);
3278 else if (flag_res)
3279 dev_err(hba->dev,
3280 "%s fDeviceInit was not cleared by the device\n",
3281 __func__);
3282
3283out:
3284 return err;
3285}
3286
7a3e97b0
SY		 3287/**
3288 * ufshcd_make_hba_operational - Make UFS controller operational
3289 * @hba: per adapter instance
3290 *
3291 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3292 * 1. Enable required interrupts
3293 * 2. Configure interrupt aggregation
897efe62 3294 * 3. Program UTRL and UTMRL base address
5c0c28a8 3295 * 4. Configure run-stop-registers
7a3e97b0
SY		 3296 *
3297 * Returns 0 on success, non-zero value on failure
3298 */
3299static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3300{
3301 int err = 0;
3302 u32 reg;
3303
6ccf44fe
SJ		 3304 /* Enable required interrupts */
3305 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3306
3307 /* Configure interrupt aggregation */
b852190e
YG		 3308 if (ufshcd_is_intr_aggr_allowed(hba))
3309 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3310 else
3311 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3312
3313 /* Configure UTRL and UTMRL base address registers */
3314 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3315 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3316 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3317 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3318 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3319 REG_UTP_TASK_REQ_LIST_BASE_L);
3320 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3321 REG_UTP_TASK_REQ_LIST_BASE_H);
3322
897efe62
YG		 3323 /*
3324 * Make sure base address and interrupt setup are updated before
3325 * enabling the run/stop registers below.
3326 */
3327 wmb();
3328
7a3e97b0
SY		 3329 /*
3330 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3331 */
5c0c28a8 3332 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3333 if (!(ufshcd_get_lists_status(reg))) {
3334 ufshcd_enable_run_stop_reg(hba);
3335 } else {
3b1d0580 3336 dev_err(hba->dev,
7a3e97b0
SY		 3337 "Host controller not ready to process requests");
3338 err = -EIO;
3339 goto out;
3340 }
3341
7a3e97b0
SY		 3342out:
3343 return err;
3344}
3345
596585a2
YG		 3346/**
3347 * ufshcd_hba_stop - Send controller to reset state
3348 * @hba: per adapter instance
3349 * @can_sleep: perform sleep or just spin
3350 */
3351static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3352{
3353 int err;
3354
3355 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3356 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3357 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3358 10, 1, can_sleep);
3359 if (err)
3360 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3361}
3362
7a3e97b0
SY		 3363/**
3364 * ufshcd_hba_enable - initialize the controller
3365 * @hba: per adapter instance
3366 *
3367 * The controller resets itself and controller firmware initialization
3368 * sequence kicks off. When controller is ready it will set
3369 * the Host Controller Enable bit to 1.
3370 *
3371 * Returns 0 on success, non-zero value on failure
3372 */
3373static int ufshcd_hba_enable(struct ufs_hba *hba)
3374{
3375 int retry;
3376
3377 /*
3378 * msleep of 1 and 5 used in this function might result in msleep(20),
3379 * but it was necessary to send the UFS FPGA to reset mode during
3380 * development and testing of this driver. msleep can be changed to
3381 * mdelay and retry count can be reduced based on the controller.
3382 */
596585a2 3383 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3384 /* change controller state to "reset state" */
596585a2 3385 ufshcd_hba_stop(hba, true);
7a3e97b0 3386
57d104c1
SJ		 3387 /* UniPro link is disabled at this point */
3388 ufshcd_set_link_off(hba);
3389
0263bcd0 3390 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3391
7a3e97b0
SY		 3392 /* start controller initialization sequence */
3393 ufshcd_hba_start(hba);
3394
3395 /*
3396 * To initialize a UFS host controller HCE bit must be set to 1.
3397 * During initialization the HCE bit value changes from 1->0->1.
3398 * When the host controller completes initialization sequence
3399 * it sets the value of HCE bit to 1. The same HCE bit is read back
3400 * to check if the controller has completed initialization sequence.
3401 * So without this delay the value HCE = 1, set in the previous
3402 * instruction might be read back.
3403 * This delay can be changed based on the controller.
3404 */
3405 msleep(1);
3406
3407 /* wait for the host controller to complete initialization */
3408 retry = 10;
3409 while (ufshcd_is_hba_active(hba)) {
3410 if (retry) {
3411 retry--;
3412 } else {
3b1d0580 3413 dev_err(hba->dev,
7a3e97b0
SY		 3414 "Controller enable failed\n");
3415 return -EIO;
3416 }
3417 msleep(5);
3418 }
5c0c28a8 3419
1d337ec2 3420 /* enable UIC related interrupts */
57d104c1 3421 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3422
0263bcd0 3423 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3424
7a3e97b0
SY		 3425 return 0;
3426}
3427
7ca38cf3
YG		 3428static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3429{
3430 int tx_lanes, i, err = 0;
3431
3432 if (!peer)
3433 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3434 &tx_lanes);
3435 else
3436 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3437 &tx_lanes);
3438 for (i = 0; i < tx_lanes; i++) {
3439 if (!peer)
3440 err = ufshcd_dme_set(hba,
3441 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3442 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3443 0);
3444 else
3445 err = ufshcd_dme_peer_set(hba,
3446 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3447 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3448 0);
3449 if (err) {
3450 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3451 __func__, peer, i, err);
3452 break;
3453 }
3454 }
3455
3456 return err;
3457}
3458
3459static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3460{
3461 return ufshcd_disable_tx_lcc(hba, true);
3462}
3463
7a3e97b0 3464/**
6ccf44fe 3465 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 3466 * @hba: per adapter instance
3467 *
6ccf44fe 3468 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3469 */
6ccf44fe 3470static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3471{
6ccf44fe 3472 int ret;
1d337ec2 3473 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 3474 bool link_startup_again = false;
7a3e97b0 3475
7caf489b 3476 /*
3477 * If UFS device isn't active then we will have to issue link startup
3478 * 2 times to make sure the device state move to active.
3479 */
3480 if (!ufshcd_is_ufs_dev_active(hba))
3481 link_startup_again = true;
7a3e97b0 3482
7caf489b 3483link_startup:
1d337ec2 3484 do {
0263bcd0 3485 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3486
1d337ec2 3487 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3488
1d337ec2
SRT		 3489 /* check if device is detected by inter-connect layer */
3490 if (!ret && !ufshcd_is_device_present(hba)) {
3491 dev_err(hba->dev, "%s: Device not present\n", __func__);
3492 ret = -ENXIO;
3493 goto out;
3494 }
6ccf44fe 3495
1d337ec2
SRT		 3496 /*
3497 * DME link lost indication is only received when link is up,
3498 * but we can't be sure if the link is up until link startup
3499 * succeeds. So reset the local Uni-Pro and try again.
3500 */
3501 if (ret && ufshcd_hba_enable(hba))
3502 goto out;
3503 } while (ret && retries--);
3504
3505 if (ret)
3506 /* failed to get the link up... retire */
5c0c28a8 3507 goto out;
5c0c28a8 3508
7caf489b 3509 if (link_startup_again) {
3510 link_startup_again = false;
3511 retries = DME_LINKSTARTUP_RETRIES;
3512 goto link_startup;
3513 }
3514
d2aebb9b 3515 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
3516 ufshcd_init_pwr_info(hba);
3517 ufshcd_print_pwr_info(hba);
3518
7ca38cf3
YG		 3519 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3520 ret = ufshcd_disable_device_tx_lcc(hba);
3521 if (ret)
3522 goto out;
3523 }
3524
5c0c28a8 3525 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 3526 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3527 if (ret)
3528 goto out;
7a3e97b0 3529
5c0c28a8 3530 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 3531out:
3532 if (ret)
3533 dev_err(hba->dev, "link startup failed %d\n", ret);
3534 return ret;
7a3e97b0
SY		 3535}
3536
5a0b0cb9
SRT		 3537/**
3538 * ufshcd_verify_dev_init() - Verify device initialization
3539 * @hba: per-adapter instance
3540 *
3541 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3542 * device Transport Protocol (UTP) layer is ready after a reset.
3543 * If the UTP layer at the device side is not initialized, it may
3544 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3545 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3546 */
3547static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3548{
3549 int err = 0;
3550 int retries;
3551
1ab27c9c 3552 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 3553 mutex_lock(&hba->dev_cmd.lock);
3554 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3555 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3556 NOP_OUT_TIMEOUT);
3557
3558 if (!err || err == -ETIMEDOUT)
3559 break;
3560
3561 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3562 }
3563 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3564 ufshcd_release(hba);
5a0b0cb9
SRT		 3565
3566 if (err)
3567 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3568 return err;
3569}
3570
0ce147d4
SJ		 3571/**
3572 * ufshcd_set_queue_depth - set lun queue depth
3573 * @sdev: pointer to SCSI device
3574 *
3575 * Read bLUQueueDepth value and activate scsi tagged command
3576 * queueing. For WLUN, queue depth is set to 1. For best-effort
3577 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3578 * value that host can queue.
3579 */
3580static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3581{
3582 int ret = 0;
3583 u8 lun_qdepth;
61e07359 3584 int retries;
0ce147d4
SJ		 3585 struct ufs_hba *hba;
3586
3587 hba = shost_priv(sdev->host);
3588
3589 lun_qdepth = hba->nutrs;
61e07359
DR		 3590 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3591 /* Read descriptor*/
3592 ret = ufshcd_read_unit_desc_param(hba,
3593 ufshcd_scsi_to_upiu_lun(sdev->lun),
3594 UNIT_DESC_PARAM_LU_Q_DEPTH,
3595 &lun_qdepth,
3596 sizeof(lun_qdepth));
3597 if (!ret || ret == -ENOTSUPP)
3598 break;
3599
3600 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
3601 }
0ce147d4
SJ		 3602
3603 /* Some WLUN doesn't support unit descriptor */
3604 if (ret == -EOPNOTSUPP)
3605 lun_qdepth = 1;
3606 else if (!lun_qdepth)
3607 /* eventually, we can figure out the real queue depth */
3608 lun_qdepth = hba->nutrs;
3609 else
3610 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3611
3612 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3613 __func__, lun_qdepth);
db5ed4df 3614 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 3615}
3616
57d104c1
SJ		 3617/*
3618 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3619 * @hba: per-adapter instance
3620 * @lun: UFS device lun id
3621 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3622 *
3623 * Returns 0 in case of success and b_lu_write_protect status would be returned
3624 * @b_lu_write_protect parameter.
3625 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3626 * Returns -EINVAL in case of invalid parameters passed to this function.
3627 */
3628static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3629 u8 lun,
3630 u8 *b_lu_write_protect)
3631{
3632 int ret;
3633
3634 if (!b_lu_write_protect)
3635 ret = -EINVAL;
3636 /*
3637 * According to UFS device spec, RPMB LU can't be write
3638 * protected so skip reading bLUWriteProtect parameter for
3639 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3640 */
3641 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3642 ret = -ENOTSUPP;
3643 else
3644 ret = ufshcd_read_unit_desc_param(hba,
3645 lun,
3646 UNIT_DESC_PARAM_LU_WR_PROTECT,
3647 b_lu_write_protect,
3648 sizeof(*b_lu_write_protect));
3649 return ret;
3650}
3651
3652/**
3653 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3654 * status
3655 * @hba: per-adapter instance
3656 * @sdev: pointer to SCSI device
3657 *
3658 */
3659static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3660 struct scsi_device *sdev)
3661{
3662 if (hba->dev_info.f_power_on_wp_en &&
3663 !hba->dev_info.is_lu_power_on_wp) {
3664 u8 b_lu_write_protect;
3665
3666 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3667 &b_lu_write_protect) &&
3668 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3669 hba->dev_info.is_lu_power_on_wp = true;
3670 }
3671}
3672
7a3e97b0
SY		 3673/**
3674 * ufshcd_slave_alloc - handle initial SCSI device configurations
3675 * @sdev: pointer to SCSI device
3676 *
3677 * Returns success
3678 */
3679static int ufshcd_slave_alloc(struct scsi_device *sdev)
3680{
3681 struct ufs_hba *hba;
3682
3683 hba = shost_priv(sdev->host);
7a3e97b0
SY		 3684
3685 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3686 sdev->use_10_for_ms = 1;
7a3e97b0 3687
e8e7f271
SRT		 3688 /* allow SCSI layer to restart the device in case of errors */
3689 sdev->allow_restart = 1;
4264fd61 3690
b2a6c522
SRT		 3691 /* REPORT SUPPORTED OPERATION CODES is not supported */
3692 sdev->no_report_opcodes = 1;
3693
e8e7f271 3694
0ce147d4 3695 ufshcd_set_queue_depth(sdev);
4264fd61 3696
57d104c1
SJ		 3697 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3698
7a3e97b0
SY		 3699 return 0;
3700}
3701
4264fd61
SRT		 3702/**
3703 * ufshcd_change_queue_depth - change queue depth
3704 * @sdev: pointer to SCSI device
3705 * @depth: required depth to set
4264fd61 3706 *
db5ed4df 3707 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3708 */
db5ed4df 3709static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 3710{
3711 struct ufs_hba *hba = shost_priv(sdev->host);
3712
3713 if (depth > hba->nutrs)
3714 depth = hba->nutrs;
db5ed4df 3715 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3716}
3717
eeda4749
AM		 3718/**
3719 * ufshcd_slave_configure - adjust SCSI device configurations
3720 * @sdev: pointer to SCSI device
3721 */
3722static int ufshcd_slave_configure(struct scsi_device *sdev)
3723{
3724 struct request_queue *q = sdev->request_queue;
3725
3726 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3727 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3728
3729 return 0;
3730}
3731
7a3e97b0
SY		 3732/**
3733 * ufshcd_slave_destroy - remove SCSI device configurations
3734 * @sdev: pointer to SCSI device
3735 */
3736static void ufshcd_slave_destroy(struct scsi_device *sdev)
3737{
3738 struct ufs_hba *hba;
3739
3740 hba = shost_priv(sdev->host);
0ce147d4 3741 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3742 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3743 unsigned long flags;
3744
3745 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3746 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3747 spin_unlock_irqrestore(hba->host->host_lock, flags);
3748 }
7a3e97b0
SY		 3749}
3750
3751/**
3752 * ufshcd_task_req_compl - handle task management request completion
3753 * @hba: per adapter instance
3754 * @index: index of the completed request
e2933132 3755 * @resp: task management service response
7a3e97b0 3756 *
e2933132 3757 * Returns non-zero value on error, zero on success
7a3e97b0 3758 */
e2933132 3759static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3760{
3761 struct utp_task_req_desc *task_req_descp;
3762 struct utp_upiu_task_rsp *task_rsp_upiup;
3763 unsigned long flags;
3764 int ocs_value;
3765 int task_result;
3766
3767 spin_lock_irqsave(hba->host->host_lock, flags);
3768
3769 /* Clear completed tasks from outstanding_tasks */
3770 __clear_bit(index, &hba->outstanding_tasks);
3771
3772 task_req_descp = hba->utmrdl_base_addr;
3773 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3774
3775 if (ocs_value == OCS_SUCCESS) {
3776 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3777 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 3778 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3779 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 3780 if (resp)
3781 *resp = (u8)task_result;
7a3e97b0 3782 } else {
e2933132
SRT		 3783 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3784 __func__, ocs_value);
7a3e97b0
SY		 3785 }
3786 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3787
3788 return ocs_value;
7a3e97b0
SY		 3789}
3790
7a3e97b0
SY		 3791/**
3792 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3793 * @lrb: pointer to local reference block of completed command
3794 * @scsi_status: SCSI command status
3795 *
3796 * Returns value base on SCSI command status
3797 */
3798static inline int
3799ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3800{
3801 int result = 0;
3802
3803 switch (scsi_status) {
7a3e97b0 3804 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3805 ufshcd_copy_sense_data(lrbp);
3806 case SAM_STAT_GOOD:
7a3e97b0
SY		 3807 result |= DID_OK << 16 |
3808 COMMAND_COMPLETE << 8 |
1c2623c5 3809 scsi_status;
7a3e97b0
SY		 3810 break;
3811 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3812 case SAM_STAT_BUSY:
7a3e97b0 3813 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3814 ufshcd_copy_sense_data(lrbp);
3815 result |= scsi_status;
7a3e97b0
SY		 3816 break;
3817 default:
3818 result |= DID_ERROR << 16;
3819 break;
3820 } /* end of switch */
3821
3822 return result;
3823}
3824
3825/**
3826 * ufshcd_transfer_rsp_status - Get overall status of the response
3827 * @hba: per adapter instance
3828 * @lrb: pointer to local reference block of completed command
3829 *
3830 * Returns result of the command to notify SCSI midlayer
3831 */
3832static inline int
3833ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3834{
3835 int result = 0;
3836 int scsi_status;
3837 int ocs;
3838
3839 /* overall command status of utrd */
3840 ocs = ufshcd_get_tr_ocs(lrbp);
3841
3842 switch (ocs) {
3843 case OCS_SUCCESS:
5a0b0cb9 3844 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3845
5a0b0cb9
SRT		 3846 switch (result) {
3847 case UPIU_TRANSACTION_RESPONSE:
3848 /*
3849 * get the response UPIU result to extract
3850 * the SCSI command status
3851 */
3852 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3853
3854 /*
3855 * get the result based on SCSI status response
3856 * to notify the SCSI midlayer of the command status
3857 */
3858 scsi_status = result & MASK_SCSI_STATUS;
3859 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3860
f05ac2e5
YG		 3861 /*
3862 * Currently we are only supporting BKOPs exception
3863 * events hence we can ignore BKOPs exception event
3864 * during power management callbacks. BKOPs exception
3865 * event is not expected to be raised in runtime suspend
3866 * callback as it allows the urgent bkops.
3867 * During system suspend, we are anyway forcefully
3868 * disabling the bkops and if urgent bkops is needed
3869 * it will be enabled on system resume. Long term
3870 * solution could be to abort the system suspend if
3871 * UFS device needs urgent BKOPs.
3872 */
3873 if (!hba->pm_op_in_progress &&
3874 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3875 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3876 break;
3877 case UPIU_TRANSACTION_REJECT_UPIU:
3878 /* TODO: handle Reject UPIU Response */
3879 result = DID_ERROR << 16;
3b1d0580 3880 dev_err(hba->dev,
5a0b0cb9
SRT		 3881 "Reject UPIU not fully implemented\n");
3882 break;
3883 default:
3884 result = DID_ERROR << 16;
3885 dev_err(hba->dev,
3886 "Unexpected request response code = %x\n",
3887 result);
7a3e97b0
SY		 3888 break;
3889 }
7a3e97b0
SY		 3890 break;
3891 case OCS_ABORTED:
3892 result |= DID_ABORT << 16;
3893 break;
e8e7f271
SRT		 3894 case OCS_INVALID_COMMAND_STATUS:
3895 result |= DID_REQUEUE << 16;
3896 break;
7a3e97b0
SY		 3897 case OCS_INVALID_CMD_TABLE_ATTR:
3898 case OCS_INVALID_PRDT_ATTR:
3899 case OCS_MISMATCH_DATA_BUF_SIZE:
3900 case OCS_MISMATCH_RESP_UPIU_SIZE:
3901 case OCS_PEER_COMM_FAILURE:
3902 case OCS_FATAL_ERROR:
3903 default:
3904 result |= DID_ERROR << 16;
3b1d0580 3905 dev_err(hba->dev,
7a3e97b0
SY		 3906 "OCS error from controller = %x\n", ocs);
3907 break;
3908 } /* end of switch */
3909
66cc820f
DR		 3910 if (host_byte(result) != DID_OK)
3911 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 3912 return result;
3913}
3914
6ccf44fe
SJ		 3915/**
3916 * ufshcd_uic_cmd_compl - handle completion of uic command
3917 * @hba: per adapter instance
53b3d9c3 3918 * @intr_status: interrupt status generated by the controller
6ccf44fe 3919 */
53b3d9c3 3920static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3921{
53b3d9c3 3922 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3923 hba->active_uic_cmd->argument2 |=
3924 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3925 hba->active_uic_cmd->argument3 =
3926 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3927 complete(&hba->active_uic_cmd->done);
3928 }
53b3d9c3 3929
57d104c1
SJ		 3930 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3931 complete(hba->uic_async_done);
6ccf44fe
SJ		 3932}
3933
7a3e97b0 3934/**
9a47ec7c 3935 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3936 * @hba: per adapter instance
9a47ec7c 3937 * @completed_reqs: requests to complete
7a3e97b0 3938 */
9a47ec7c
YG		 3939static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3940 unsigned long completed_reqs)
7a3e97b0 3941{
5a0b0cb9
SRT		 3942 struct ufshcd_lrb *lrbp;
3943 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3944 int result;
3945 int index;
e9d501b1 3946
e9d501b1
DR		 3947 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3948 lrbp = &hba->lrb[index];
3949 cmd = lrbp->cmd;
3950 if (cmd) {
3951 result = ufshcd_transfer_rsp_status(hba, lrbp);
3952 scsi_dma_unmap(cmd);
3953 cmd->result = result;
3954 /* Mark completed command as NULL in LRB */
3955 lrbp->cmd = NULL;
3956 clear_bit_unlock(index, &hba->lrb_in_use);
3957 /* Do not touch lrbp after scsi done */
3958 cmd->scsi_done(cmd);
1ab27c9c 3959 __ufshcd_release(hba);
300bb13f
JP		 3960 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3961 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR		 3962 if (hba->dev_cmd.complete)
3963 complete(hba->dev_cmd.complete);
3964 }
3965 }
7a3e97b0
SY		 3966
3967 /* clear corresponding bits of completed commands */
3968 hba->outstanding_reqs ^= completed_reqs;
3969
856b3483
ST		 3970 ufshcd_clk_scaling_update_busy(hba);
3971
5a0b0cb9
SRT		 3972 /* we might have free'd some tags above */
3973 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3974}
3975
9a47ec7c
YG		 3976/**
3977 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3978 * @hba: per adapter instance
3979 */
3980static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3981{
3982 unsigned long completed_reqs;
3983 u32 tr_doorbell;
3984
3985 /* Resetting interrupt aggregation counters first and reading the
3986 * DOOR_BELL afterward allows us to handle all the completed requests.
3987 * In order to prevent other interrupts starvation the DB is read once
3988 * after reset. The down side of this solution is the possibility of
3989 * false interrupt if device completes another request after resetting
3990 * aggregation and before reading the DB.
3991 */
3992 if (ufshcd_is_intr_aggr_allowed(hba))
3993 ufshcd_reset_intr_aggr(hba);
3994
3995 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3996 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3997
3998 __ufshcd_transfer_req_compl(hba, completed_reqs);
3999}
4000
66ec6d59
SRT		 4001/**
4002 * ufshcd_disable_ee - disable exception event
4003 * @hba: per-adapter instance
4004 * @mask: exception event to disable
4005 *
4006 * Disables exception event in the device so that the EVENT_ALERT
4007 * bit is not set.
4008 *
4009 * Returns zero on success, non-zero error value on failure.
4010 */
4011static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4012{
4013 int err = 0;
4014 u32 val;
4015
4016 if (!(hba->ee_ctrl_mask & mask))
4017 goto out;
4018
4019 val = hba->ee_ctrl_mask & ~mask;
4020 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4021 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4022 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4023 if (!err)
4024 hba->ee_ctrl_mask &= ~mask;
4025out:
4026 return err;
4027}
4028
4029/**
4030 * ufshcd_enable_ee - enable exception event
4031 * @hba: per-adapter instance
4032 * @mask: exception event to enable
4033 *
4034 * Enable corresponding exception event in the device to allow
4035 * device to alert host in critical scenarios.
4036 *
4037 * Returns zero on success, non-zero error value on failure.
4038 */
4039static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4040{
4041 int err = 0;
4042 u32 val;
4043
4044 if (hba->ee_ctrl_mask & mask)
4045 goto out;
4046
4047 val = hba->ee_ctrl_mask | mask;
4048 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4049 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4050 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4051 if (!err)
4052 hba->ee_ctrl_mask |= mask;
4053out:
4054 return err;
4055}
4056
4057/**
4058 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4059 * @hba: per-adapter instance
4060 *
4061 * Allow device to manage background operations on its own. Enabling
4062 * this might lead to inconsistent latencies during normal data transfers
4063 * as the device is allowed to manage its own way of handling background
4064 * operations.
4065 *
4066 * Returns zero on success, non-zero on failure.
4067 */
4068static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4069{
4070 int err = 0;
4071
4072 if (hba->auto_bkops_enabled)
4073 goto out;
4074
dc3c8d3a 4075 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4076 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4077 if (err) {
4078 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4079 __func__, err);
4080 goto out;
4081 }
4082
4083 hba->auto_bkops_enabled = true;
7ff5ab47 4084 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4085
4086 /* No need of URGENT_BKOPS exception from the device */
4087 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4088 if (err)
4089 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4090 __func__, err);
4091out:
4092 return err;
4093}
4094
4095/**
4096 * ufshcd_disable_auto_bkops - block device in doing background operations
4097 * @hba: per-adapter instance
4098 *
4099 * Disabling background operations improves command response latency but
4100 * has drawback of device moving into critical state where the device is
4101 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4102 * host is idle so that BKOPS are managed effectively without any negative
4103 * impacts.
4104 *
4105 * Returns zero on success, non-zero on failure.
4106 */
4107static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4108{
4109 int err = 0;
4110
4111 if (!hba->auto_bkops_enabled)
4112 goto out;
4113
4114 /*
4115 * If host assisted BKOPs is to be enabled, make sure
4116 * urgent bkops exception is allowed.
4117 */
4118 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4119 if (err) {
4120 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4121 __func__, err);
4122 goto out;
4123 }
4124
dc3c8d3a 4125 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4126 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4127 if (err) {
4128 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4129 __func__, err);
4130 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4131 goto out;
4132 }
4133
4134 hba->auto_bkops_enabled = false;
7ff5ab47 4135 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4136out:
4137 return err;
4138}
4139
4140/**
4e768e76 4141 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4142 * @hba: per adapter instance
4143 *
4144 * After a device reset the device may toggle the BKOPS_EN flag
4145 * to default value. The s/w tracking variables should be updated
4e768e76 4146 * as well. This function would change the auto-bkops state based on
4147 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4148 */
4e768e76 4149static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4150{
4e768e76 4151 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4152 hba->auto_bkops_enabled = false;
4153 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4154 ufshcd_enable_auto_bkops(hba);
4155 } else {
4156 hba->auto_bkops_enabled = true;
4157 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4158 ufshcd_disable_auto_bkops(hba);
4159 }
66ec6d59
SRT		 4160}
4161
4162static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4163{
5e86ae44 4164 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4165 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4166}
4167
4168/**
57d104c1 4169 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4170 * @hba: per-adapter instance
57d104c1 4171 * @status: bkops_status value
66ec6d59 4172 *
57d104c1
SJ		 4173 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4174 * flag in the device to permit background operations if the device
4175 * bkops_status is greater than or equal to "status" argument passed to
4176 * this function, disable otherwise.
4177 *
4178 * Returns 0 for success, non-zero in case of failure.
4179 *
4180 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4181 * to know whether auto bkops is enabled or disabled after this function
4182 * returns control to it.
66ec6d59 4183 */
57d104c1
SJ		 4184static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4185 enum bkops_status status)
66ec6d59
SRT		 4186{
4187 int err;
57d104c1 4188 u32 curr_status = 0;
66ec6d59 4189
57d104c1 4190 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 4191 if (err) {
4192 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4193 __func__, err);
4194 goto out;
57d104c1
SJ		 4195 } else if (curr_status > BKOPS_STATUS_MAX) {
4196 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4197 __func__, curr_status);
4198 err = -EINVAL;
4199 goto out;
66ec6d59
SRT		 4200 }
4201
57d104c1 4202 if (curr_status >= status)
66ec6d59 4203 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 4204 else
4205 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 4206out:
4207 return err;
4208}
4209
57d104c1
SJ		 4210/**
4211 * ufshcd_urgent_bkops - handle urgent bkops exception event
4212 * @hba: per-adapter instance
4213 *
4214 * Enable fBackgroundOpsEn flag in the device to permit background
4215 * operations.
4216 *
4217 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4218 * and negative error value for any other failure.
4219 */
4220static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4221{
afdfff59 4222 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 4223}
4224
66ec6d59
SRT		 4225static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4226{
5e86ae44 4227 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4228 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4229}
4230
afdfff59
YG		 4231static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4232{
4233 int err;
4234 u32 curr_status = 0;
4235
4236 if (hba->is_urgent_bkops_lvl_checked)
4237 goto enable_auto_bkops;
4238
4239 err = ufshcd_get_bkops_status(hba, &curr_status);
4240 if (err) {
4241 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4242 __func__, err);
4243 goto out;
4244 }
4245
4246 /*
4247 * We are seeing that some devices are raising the urgent bkops
4248 * exception events even when BKOPS status doesn't indicate performace
4249 * impacted or critical. Handle these device by determining their urgent
4250 * bkops status at runtime.
4251 */
4252 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4253 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4254 __func__, curr_status);
4255 /* update the current status as the urgent bkops level */
4256 hba->urgent_bkops_lvl = curr_status;
4257 hba->is_urgent_bkops_lvl_checked = true;
4258 }
4259
4260enable_auto_bkops:
4261 err = ufshcd_enable_auto_bkops(hba);
4262out:
4263 if (err < 0)
4264 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4265 __func__, err);
4266}
4267
66ec6d59
SRT		 4268/**
4269 * ufshcd_exception_event_handler - handle exceptions raised by device
4270 * @work: pointer to work data
4271 *
4272 * Read bExceptionEventStatus attribute from the device and handle the
4273 * exception event accordingly.
4274 */
4275static void ufshcd_exception_event_handler(struct work_struct *work)
4276{
4277 struct ufs_hba *hba;
4278 int err;
4279 u32 status = 0;
4280 hba = container_of(work, struct ufs_hba, eeh_work);
4281
62694735 4282 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 4283 err = ufshcd_get_ee_status(hba, &status);
4284 if (err) {
4285 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4286 __func__, err);
4287 goto out;
4288 }
4289
4290 status &= hba->ee_ctrl_mask;
afdfff59
YG		 4291
4292 if (status & MASK_EE_URGENT_BKOPS)
4293 ufshcd_bkops_exception_event_handler(hba);
4294
66ec6d59 4295out:
62694735 4296 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 4297 return;
4298}
4299
9a47ec7c
YG		 4300/* Complete requests that have door-bell cleared */
4301static void ufshcd_complete_requests(struct ufs_hba *hba)
4302{
4303 ufshcd_transfer_req_compl(hba);
4304 ufshcd_tmc_handler(hba);
4305}
4306
583fa62d
YG		 4307/**
4308 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4309 * to recover from the DL NAC errors or not.
4310 * @hba: per-adapter instance
4311 *
4312 * Returns true if error handling is required, false otherwise
4313 */
4314static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4315{
4316 unsigned long flags;
4317 bool err_handling = true;
4318
4319 spin_lock_irqsave(hba->host->host_lock, flags);
4320 /*
4321 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4322 * device fatal error and/or DL NAC & REPLAY timeout errors.
4323 */
4324 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4325 goto out;
4326
4327 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4328 ((hba->saved_err & UIC_ERROR) &&
4329 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4330 goto out;
4331
4332 if ((hba->saved_err & UIC_ERROR) &&
4333 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4334 int err;
4335 /*
4336 * wait for 50ms to see if we can get any other errors or not.
4337 */
4338 spin_unlock_irqrestore(hba->host->host_lock, flags);
4339 msleep(50);
4340 spin_lock_irqsave(hba->host->host_lock, flags);
4341
4342 /*
4343 * now check if we have got any other severe errors other than
4344 * DL NAC error?
4345 */
4346 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4347 ((hba->saved_err & UIC_ERROR) &&
4348 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4349 goto out;
4350
4351 /*
4352 * As DL NAC is the only error received so far, send out NOP
4353 * command to confirm if link is still active or not.
4354 * - If we don't get any response then do error recovery.
4355 * - If we get response then clear the DL NAC error bit.
4356 */
4357
4358 spin_unlock_irqrestore(hba->host->host_lock, flags);
4359 err = ufshcd_verify_dev_init(hba);
4360 spin_lock_irqsave(hba->host->host_lock, flags);
4361
4362 if (err)
4363 goto out;
4364
4365 /* Link seems to be alive hence ignore the DL NAC errors */
4366 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
4367 hba->saved_err &= ~UIC_ERROR;
4368 /* clear NAC error */
4369 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4370 if (!hba->saved_uic_err) {
4371 err_handling = false;
4372 goto out;
4373 }
4374 }
4375out:
4376 spin_unlock_irqrestore(hba->host->host_lock, flags);
4377 return err_handling;
4378}
4379
7a3e97b0 4380/**
e8e7f271
SRT		 4381 * ufshcd_err_handler - handle UFS errors that require s/w attention
4382 * @work: pointer to work structure
7a3e97b0 4383 */
e8e7f271 4384static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 4385{
4386 struct ufs_hba *hba;
e8e7f271
SRT		 4387 unsigned long flags;
4388 u32 err_xfer = 0;
4389 u32 err_tm = 0;
4390 int err = 0;
4391 int tag;
9a47ec7c 4392 bool needs_reset = false;
e8e7f271
SRT		 4393
4394 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 4395
62694735 4396 pm_runtime_get_sync(hba->dev);
1ab27c9c 4397 ufshcd_hold(hba, false);
e8e7f271
SRT		 4398
4399 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 4400 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 4401 goto out;
e8e7f271
SRT		 4402
4403 hba->ufshcd_state = UFSHCD_STATE_RESET;
4404 ufshcd_set_eh_in_progress(hba);
4405
4406 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 4407 ufshcd_complete_requests(hba);
583fa62d
YG		 4408
4409 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4410 bool ret;
4411
4412 spin_unlock_irqrestore(hba->host->host_lock, flags);
4413 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
4414 ret = ufshcd_quirk_dl_nac_errors(hba);
4415 spin_lock_irqsave(hba->host->host_lock, flags);
4416 if (!ret)
4417 goto skip_err_handling;
4418 }
9a47ec7c
YG		 4419 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4420 ((hba->saved_err & UIC_ERROR) &&
4421 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4422 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4423 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4424 needs_reset = true;
e8e7f271 4425
9a47ec7c
YG		 4426 /*
4427 * if host reset is required then skip clearing the pending
4428 * transfers forcefully because they will automatically get
4429 * cleared after link startup.
4430 */
4431 if (needs_reset)
4432 goto skip_pending_xfer_clear;
4433
4434 /* release lock as clear command might sleep */
4435 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4436 /* Clear pending transfer requests */
9a47ec7c
YG		 4437 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4438 if (ufshcd_clear_cmd(hba, tag)) {
4439 err_xfer = true;
4440 goto lock_skip_pending_xfer_clear;
4441 }
4442 }
e8e7f271
SRT		 4443
4444 /* Clear pending task management requests */
9a47ec7c
YG		 4445 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4446 if (ufshcd_clear_tm_cmd(hba, tag)) {
4447 err_tm = true;
4448 goto lock_skip_pending_xfer_clear;
4449 }
4450 }
e8e7f271 4451
9a47ec7c 4452lock_skip_pending_xfer_clear:
e8e7f271 4453 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4454
9a47ec7c
YG		 4455 /* Complete the requests that are cleared by s/w */
4456 ufshcd_complete_requests(hba);
4457
4458 if (err_xfer || err_tm)
4459 needs_reset = true;
4460
4461skip_pending_xfer_clear:
e8e7f271 4462 /* Fatal errors need reset */
9a47ec7c
YG		 4463 if (needs_reset) {
4464 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4465
4466 /*
4467 * ufshcd_reset_and_restore() does the link reinitialization
4468 * which will need atleast one empty doorbell slot to send the
4469 * device management commands (NOP and query commands).
4470 * If there is no slot empty at this moment then free up last
4471 * slot forcefully.
4472 */
4473 if (hba->outstanding_reqs == max_doorbells)
4474 __ufshcd_transfer_req_compl(hba,
4475 (1UL << (hba->nutrs - 1)));
4476
4477 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4478 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4479 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 4480 if (err) {
4481 dev_err(hba->dev, "%s: reset and restore failed\n",
4482 __func__);
4483 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4484 }
4485 /*
4486 * Inform scsi mid-layer that we did reset and allow to handle
4487 * Unit Attention properly.
4488 */
4489 scsi_report_bus_reset(hba->host, 0);
4490 hba->saved_err = 0;
4491 hba->saved_uic_err = 0;
4492 }
9a47ec7c 4493
583fa62d 4494skip_err_handling:
9a47ec7c
YG		 4495 if (!needs_reset) {
4496 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4497 if (hba->saved_err || hba->saved_uic_err)
4498 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4499 __func__, hba->saved_err, hba->saved_uic_err);
4500 }
4501
e8e7f271
SRT		 4502 ufshcd_clear_eh_in_progress(hba);
4503
4504out:
9a47ec7c 4505 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4506 scsi_unblock_requests(hba->host);
1ab27c9c 4507 ufshcd_release(hba);
62694735 4508 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 4509}
4510
4511/**
e8e7f271
SRT		 4512 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4513 * @hba: per-adapter instance
7a3e97b0 4514 */
e8e7f271 4515static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 4516{
4517 u32 reg;
4518
fb7b45f0
DR		 4519 /* PHY layer lane error */
4520 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4521 /* Ignore LINERESET indication, as this is not an error */
4522 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
4523 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK))
4524 /*
4525 * To know whether this error is fatal or not, DB timeout
4526 * must be checked but this error is handled separately.
4527 */
4528 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
4529
e8e7f271
SRT		 4530 /* PA_INIT_ERROR is fatal and needs UIC reset */
4531 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4532 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4533 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 4534 else if (hba->dev_quirks &
4535 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4536 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4537 hba->uic_error |=
4538 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4539 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4540 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4541 }
e8e7f271
SRT		 4542
4543 /* UIC NL/TL/DME errors needs software retry */
4544 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4545 if (reg)
4546 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4547
4548 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4549 if (reg)
4550 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4551
4552 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4553 if (reg)
4554 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4555
4556 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4557 __func__, hba->uic_error);
4558}
4559
4560/**
4561 * ufshcd_check_errors - Check for errors that need s/w attention
4562 * @hba: per-adapter instance
4563 */
4564static void ufshcd_check_errors(struct ufs_hba *hba)
4565{
4566 bool queue_eh_work = false;
4567
7a3e97b0 4568 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4569 queue_eh_work = true;
7a3e97b0
SY		 4570
4571 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 4572 hba->uic_error = 0;
4573 ufshcd_update_uic_error(hba);
4574 if (hba->uic_error)
4575 queue_eh_work = true;
7a3e97b0 4576 }
e8e7f271
SRT		 4577
4578 if (queue_eh_work) {
9a47ec7c
YG		 4579 /*
4580 * update the transfer error masks to sticky bits, let's do this
4581 * irrespective of current ufshcd_state.
4582 */
4583 hba->saved_err |= hba->errors;
4584 hba->saved_uic_err |= hba->uic_error;
4585
e8e7f271
SRT		 4586 /* handle fatal errors only when link is functional */
4587 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4588 /* block commands from scsi mid-layer */
4589 scsi_block_requests(hba->host);
4590
141f8165 4591 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 4592
4593 /* dump controller state before resetting */
4594 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
4595 bool pr_prdt = !!(hba->saved_err &
4596 SYSTEM_BUS_FATAL_ERROR);
4597
4598 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
4599 __func__, hba->saved_err,
4600 hba->saved_uic_err);
4601
4602 ufshcd_print_host_regs(hba);
4603 ufshcd_print_pwr_info(hba);
4604 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
4605 ufshcd_print_trs(hba, hba->outstanding_reqs,
4606 pr_prdt);
4607 }
e8e7f271
SRT		 4608 schedule_work(&hba->eh_work);
4609 }
3441da7d 4610 }
e8e7f271
SRT		 4611 /*
4612 * if (!queue_eh_work) -
4613 * Other errors are either non-fatal where host recovers
4614 * itself without s/w intervention or errors that will be
4615 * handled by the SCSI core layer.
4616 */
7a3e97b0
SY		 4617}
4618
4619/**
4620 * ufshcd_tmc_handler - handle task management function completion
4621 * @hba: per adapter instance
4622 */
4623static void ufshcd_tmc_handler(struct ufs_hba *hba)
4624{
4625 u32 tm_doorbell;
4626
b873a275 4627 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4628 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4629 wake_up(&hba->tm_wq);
7a3e97b0
SY		 4630}
4631
4632/**
4633 * ufshcd_sl_intr - Interrupt service routine
4634 * @hba: per adapter instance
4635 * @intr_status: contains interrupts generated by the controller
4636 */
4637static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4638{
4639 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4640 if (hba->errors)
e8e7f271 4641 ufshcd_check_errors(hba);
7a3e97b0 4642
53b3d9c3
SJ		 4643 if (intr_status & UFSHCD_UIC_MASK)
4644 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 4645
4646 if (intr_status & UTP_TASK_REQ_COMPL)
4647 ufshcd_tmc_handler(hba);
4648
4649 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4650 ufshcd_transfer_req_compl(hba);
4651}
4652
4653/**
4654 * ufshcd_intr - Main interrupt service routine
4655 * @irq: irq number
4656 * @__hba: pointer to adapter instance
4657 *
4658 * Returns IRQ_HANDLED - If interrupt is valid
4659 * IRQ_NONE - If invalid interrupt
4660 */
4661static irqreturn_t ufshcd_intr(int irq, void *__hba)
4662{
d75f7fe4 4663 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 4664 irqreturn_t retval = IRQ_NONE;
4665 struct ufs_hba *hba = __hba;
4666
4667 spin_lock(hba->host->host_lock);
b873a275 4668 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4669 enabled_intr_status =
4670 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4671
d75f7fe4 4672 if (intr_status)
261ea452 4673 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4674
4675 if (enabled_intr_status) {
4676 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 4677 retval = IRQ_HANDLED;
4678 }
4679 spin_unlock(hba->host->host_lock);
4680 return retval;
4681}
4682
e2933132
SRT		 4683static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4684{
4685 int err = 0;
4686 u32 mask = 1 << tag;
4687 unsigned long flags;
4688
4689 if (!test_bit(tag, &hba->outstanding_tasks))
4690 goto out;
4691
4692 spin_lock_irqsave(hba->host->host_lock, flags);
4693 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4694 spin_unlock_irqrestore(hba->host->host_lock, flags);
4695
4696 /* poll for max. 1 sec to clear door bell register by h/w */
4697 err = ufshcd_wait_for_register(hba,
4698 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4699 mask, 0, 1000, 1000, true);
e2933132
SRT		 4700out:
4701 return err;
4702}
4703
7a3e97b0
SY		 4704/**
4705 * ufshcd_issue_tm_cmd - issues task management commands to controller
4706 * @hba: per adapter instance
e2933132
SRT		 4707 * @lun_id: LUN ID to which TM command is sent
4708 * @task_id: task ID to which the TM command is applicable
4709 * @tm_function: task management function opcode
4710 * @tm_response: task management service response return value
7a3e97b0 4711 *
e2933132 4712 * Returns non-zero value on error, zero on success.
7a3e97b0 4713 */
e2933132
SRT		 4714static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4715 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 4716{
4717 struct utp_task_req_desc *task_req_descp;
4718 struct utp_upiu_task_req *task_req_upiup;
4719 struct Scsi_Host *host;
4720 unsigned long flags;
e2933132 4721 int free_slot;
7a3e97b0 4722 int err;
e2933132 4723 int task_tag;
7a3e97b0
SY		 4724
4725 host = hba->host;
4726
e2933132
SRT		 4727 /*
4728 * Get free slot, sleep if slots are unavailable.
4729 * Even though we use wait_event() which sleeps indefinitely,
4730 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4731 */
4732 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4733 ufshcd_hold(hba, false);
7a3e97b0 4734
e2933132 4735 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 4736 task_req_descp = hba->utmrdl_base_addr;
4737 task_req_descp += free_slot;
4738
4739 /* Configure task request descriptor */
4740 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4741 task_req_descp->header.dword_2 =
4742 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4743
4744 /* Configure task request UPIU */
4745 task_req_upiup =
4746 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4747 task_tag = hba->nutrs + free_slot;
7a3e97b0 4748 task_req_upiup->header.dword_0 =
5a0b0cb9 4749 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4750 lun_id, task_tag);
7a3e97b0 4751 task_req_upiup->header.dword_1 =
5a0b0cb9 4752 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 4753 /*
4754 * The host shall provide the same value for LUN field in the basic
4755 * header and for Input Parameter.
4756 */
e2933132
SRT		 4757 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4758 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 4759
d2877be4
KK		 4760 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
4761
7a3e97b0
SY		 4762 /* send command to the controller */
4763 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 4764
4765 /* Make sure descriptors are ready before ringing the task doorbell */
4766 wmb();
4767
b873a275 4768 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 4769 /* Make sure that doorbell is committed immediately */
4770 wmb();
7a3e97b0
SY		 4771
4772 spin_unlock_irqrestore(host->host_lock, flags);
4773
4774 /* wait until the task management command is completed */
e2933132
SRT		 4775 err = wait_event_timeout(hba->tm_wq,
4776 test_bit(free_slot, &hba->tm_condition),
4777 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4778 if (!err) {
e2933132
SRT		 4779 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4780 __func__, tm_function);
4781 if (ufshcd_clear_tm_cmd(hba, free_slot))
4782 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4783 __func__, free_slot);
4784 err = -ETIMEDOUT;
4785 } else {
4786 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4787 }
e2933132 4788
7a3e97b0 4789 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 4790 ufshcd_put_tm_slot(hba, free_slot);
4791 wake_up(&hba->tm_tag_wq);
4792
1ab27c9c 4793 ufshcd_release(hba);
7a3e97b0
SY		 4794 return err;
4795}
4796
4797/**
3441da7d
SRT		 4798 * ufshcd_eh_device_reset_handler - device reset handler registered to
4799 * scsi layer.
7a3e97b0
SY		 4800 * @cmd: SCSI command pointer
4801 *
4802 * Returns SUCCESS/FAILED
4803 */
3441da7d 4804static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 4805{
4806 struct Scsi_Host *host;
4807 struct ufs_hba *hba;
4808 unsigned int tag;
4809 u32 pos;
4810 int err;
e2933132
SRT		 4811 u8 resp = 0xF;
4812 struct ufshcd_lrb *lrbp;
3441da7d 4813 unsigned long flags;
7a3e97b0
SY		 4814
4815 host = cmd->device->host;
4816 hba = shost_priv(host);
4817 tag = cmd->request->tag;
4818
e2933132
SRT		 4819 lrbp = &hba->lrb[tag];
4820 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4821 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 4822 if (!err)
4823 err = resp;
7a3e97b0 4824 goto out;
e2933132 4825 }
7a3e97b0 4826
3441da7d
SRT		 4827 /* clear the commands that were pending for corresponding LUN */
4828 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4829 if (hba->lrb[pos].lun == lrbp->lun) {
4830 err = ufshcd_clear_cmd(hba, pos);
4831 if (err)
4832 break;
7a3e97b0 4833 }
3441da7d
SRT		 4834 }
4835 spin_lock_irqsave(host->host_lock, flags);
4836 ufshcd_transfer_req_compl(hba);
4837 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4838out:
3441da7d
SRT		 4839 if (!err) {
4840 err = SUCCESS;
4841 } else {
4842 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4843 err = FAILED;
4844 }
7a3e97b0
SY		 4845 return err;
4846}
4847
7a3e97b0
SY		 4848/**
4849 * ufshcd_abort - abort a specific command
4850 * @cmd: SCSI command pointer
4851 *
f20810d8
SRT		 4852 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4853 * command, and in host controller by clearing the door-bell register. There can
4854 * be race between controller sending the command to the device while abort is
4855 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4856 * really issued and then try to abort it.
4857 *
7a3e97b0
SY		 4858 * Returns SUCCESS/FAILED
4859 */
4860static int ufshcd_abort(struct scsi_cmnd *cmd)
4861{
4862 struct Scsi_Host *host;
4863 struct ufs_hba *hba;
4864 unsigned long flags;
4865 unsigned int tag;
f20810d8
SRT		 4866 int err = 0;
4867 int poll_cnt;
e2933132
SRT		 4868 u8 resp = 0xF;
4869 struct ufshcd_lrb *lrbp;
e9d501b1 4870 u32 reg;
7a3e97b0
SY		 4871
4872 host = cmd->device->host;
4873 hba = shost_priv(host);
4874 tag = cmd->request->tag;
e7d38257 4875 lrbp = &hba->lrb[tag];
14497328
YG		 4876 if (!ufshcd_valid_tag(hba, tag)) {
4877 dev_err(hba->dev,
4878 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4879 __func__, tag, cmd, cmd->request);
4880 BUG();
4881 }
7a3e97b0 4882
e7d38257
DR		 4883 /*
4884 * Task abort to the device W-LUN is illegal. When this command
4885 * will fail, due to spec violation, scsi err handling next step
4886 * will be to send LU reset which, again, is a spec violation.
4887 * To avoid these unnecessary/illegal step we skip to the last error
4888 * handling stage: reset and restore.
4889 */
4890 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
4891 return ufshcd_eh_host_reset_handler(cmd);
4892
1ab27c9c 4893 ufshcd_hold(hba, false);
14497328 4894 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4895 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 4896 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4897 dev_err(hba->dev,
4898 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4899 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4900 goto out;
14497328 4901 }
7a3e97b0 4902
e9d501b1
DR		 4903 if (!(reg & (1 << tag))) {
4904 dev_err(hba->dev,
4905 "%s: cmd was completed, but without a notifying intr, tag = %d",
4906 __func__, tag);
4907 }
4908
66cc820f
DR		 4909 /* Print Transfer Request of aborted task */
4910 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
4911 scsi_print_command(hba->lrb[tag].cmd);
4912 ufshcd_print_host_regs(hba);
4913 ufshcd_print_pwr_info(hba);
4914 ufshcd_print_trs(hba, 1 << tag, true);
4915
f20810d8
SRT		 4916 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4917 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4918 UFS_QUERY_TASK, &resp);
4919 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4920 /* cmd pending in the device */
4921 break;
4922 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4923 /*
4924 * cmd not pending in the device, check if it is
4925 * in transition.
4926 */
4927 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4928 if (reg & (1 << tag)) {
4929 /* sleep for max. 200us to stabilize */
4930 usleep_range(100, 200);
4931 continue;
4932 }
4933 /* command completed already */
4934 goto out;
4935 } else {
4936 if (!err)
4937 err = resp; /* service response error */
4938 goto out;
4939 }
4940 }
4941
4942 if (!poll_cnt) {
4943 err = -EBUSY;
7a3e97b0
SY		 4944 goto out;
4945 }
7a3e97b0 4946
e2933132
SRT		 4947 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4948 UFS_ABORT_TASK, &resp);
4949 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4950 if (!err)
4951 err = resp; /* service response error */
7a3e97b0 4952 goto out;
e2933132 4953 }
7a3e97b0 4954
f20810d8
SRT		 4955 err = ufshcd_clear_cmd(hba, tag);
4956 if (err)
4957 goto out;
4958
7a3e97b0
SY		 4959 scsi_dma_unmap(cmd);
4960
4961 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4962 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 4963 hba->lrb[tag].cmd = NULL;
4964 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 4965
4966 clear_bit_unlock(tag, &hba->lrb_in_use);
4967 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4968
7a3e97b0 4969out:
f20810d8
SRT		 4970 if (!err) {
4971 err = SUCCESS;
4972 } else {
4973 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4974 err = FAILED;
4975 }
4976
1ab27c9c
ST		 4977 /*
4978 * This ufshcd_release() corresponds to the original scsi cmd that got
4979 * aborted here (as we won't get any IRQ for it).
4980 */
4981 ufshcd_release(hba);
7a3e97b0
SY		 4982 return err;
4983}
4984
3441da7d
SRT		 4985/**
4986 * ufshcd_host_reset_and_restore - reset and restore host controller
4987 * @hba: per-adapter instance
4988 *
4989 * Note that host controller reset may issue DME_RESET to
4990 * local and remote (device) Uni-Pro stack and the attributes
4991 * are reset to default state.
4992 *
4993 * Returns zero on success, non-zero on failure
4994 */
4995static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4996{
4997 int err;
3441da7d
SRT		 4998 unsigned long flags;
4999
5000 /* Reset the host controller */
5001 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5002 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5003 spin_unlock_irqrestore(hba->host->host_lock, flags);
5004
5005 err = ufshcd_hba_enable(hba);
5006 if (err)
5007 goto out;
5008
5009 /* Establish the link again and restore the device */
1d337ec2
SRT		 5010 err = ufshcd_probe_hba(hba);
5011
5012 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5013 err = -EIO;
5014out:
5015 if (err)
5016 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5017
5018 return err;
5019}
5020
5021/**
5022 * ufshcd_reset_and_restore - reset and re-initialize host/device
5023 * @hba: per-adapter instance
5024 *
5025 * Reset and recover device, host and re-establish link. This
5026 * is helpful to recover the communication in fatal error conditions.
5027 *
5028 * Returns zero on success, non-zero on failure
5029 */
5030static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5031{
5032 int err = 0;
5033 unsigned long flags;
1d337ec2 5034 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5035
1d337ec2
SRT		 5036 do {
5037 err = ufshcd_host_reset_and_restore(hba);
5038 } while (err && --retries);
3441da7d
SRT		 5039
5040 /*
5041 * After reset the door-bell might be cleared, complete
5042 * outstanding requests in s/w here.
5043 */
5044 spin_lock_irqsave(hba->host->host_lock, flags);
5045 ufshcd_transfer_req_compl(hba);
5046 ufshcd_tmc_handler(hba);
5047 spin_unlock_irqrestore(hba->host->host_lock, flags);
5048
5049 return err;
5050}
5051
5052/**
5053 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
5054 * @cmd - SCSI command pointer
5055 *
5056 * Returns SUCCESS/FAILED
5057 */
5058static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5059{
5060 int err;
5061 unsigned long flags;
5062 struct ufs_hba *hba;
5063
5064 hba = shost_priv(cmd->device->host);
5065
1ab27c9c 5066 ufshcd_hold(hba, false);
3441da7d
SRT		 5067 /*
5068 * Check if there is any race with fatal error handling.
5069 * If so, wait for it to complete. Even though fatal error
5070 * handling does reset and restore in some cases, don't assume
5071 * anything out of it. We are just avoiding race here.
5072 */
5073 do {
5074 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5075 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 5076 hba->ufshcd_state == UFSHCD_STATE_RESET))
5077 break;
5078 spin_unlock_irqrestore(hba->host->host_lock, flags);
5079 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 5080 flush_work(&hba->eh_work);
3441da7d
SRT		 5081 } while (1);
5082
5083 hba->ufshcd_state = UFSHCD_STATE_RESET;
5084 ufshcd_set_eh_in_progress(hba);
5085 spin_unlock_irqrestore(hba->host->host_lock, flags);
5086
5087 err = ufshcd_reset_and_restore(hba);
5088
5089 spin_lock_irqsave(hba->host->host_lock, flags);
5090 if (!err) {
5091 err = SUCCESS;
5092 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5093 } else {
5094 err = FAILED;
5095 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5096 }
5097 ufshcd_clear_eh_in_progress(hba);
5098 spin_unlock_irqrestore(hba->host->host_lock, flags);
5099
1ab27c9c 5100 ufshcd_release(hba);
3441da7d
SRT		 5101 return err;
5102}
5103
3a4bf06d
YG		 5104/**
5105 * ufshcd_get_max_icc_level - calculate the ICC level
5106 * @sup_curr_uA: max. current supported by the regulator
5107 * @start_scan: row at the desc table to start scan from
5108 * @buff: power descriptor buffer
5109 *
5110 * Returns calculated max ICC level for specific regulator
5111 */
5112static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5113{
5114 int i;
5115 int curr_uA;
5116 u16 data;
5117 u16 unit;
5118
5119 for (i = start_scan; i >= 0; i--) {
5120 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
5121 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5122 ATTR_ICC_LVL_UNIT_OFFSET;
5123 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5124 switch (unit) {
5125 case UFSHCD_NANO_AMP:
5126 curr_uA = curr_uA / 1000;
5127 break;
5128 case UFSHCD_MILI_AMP:
5129 curr_uA = curr_uA * 1000;
5130 break;
5131 case UFSHCD_AMP:
5132 curr_uA = curr_uA * 1000 * 1000;
5133 break;
5134 case UFSHCD_MICRO_AMP:
5135 default:
5136 break;
5137 }
5138 if (sup_curr_uA >= curr_uA)
5139 break;
5140 }
5141 if (i < 0) {
5142 i = 0;
5143 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5144 }
5145
5146 return (u32)i;
5147}
5148
5149/**
5150 * ufshcd_calc_icc_level - calculate the max ICC level
5151 * In case regulators are not initialized we'll return 0
5152 * @hba: per-adapter instance
5153 * @desc_buf: power descriptor buffer to extract ICC levels from.
5154 * @len: length of desc_buff
5155 *
5156 * Returns calculated ICC level
5157 */
5158static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5159 u8 *desc_buf, int len)
5160{
5161 u32 icc_level = 0;
5162
5163 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5164 !hba->vreg_info.vccq2) {
5165 dev_err(hba->dev,
5166 "%s: Regulator capability was not set, actvIccLevel=%d",
5167 __func__, icc_level);
5168 goto out;
5169 }
5170
5171 if (hba->vreg_info.vcc)
5172 icc_level = ufshcd_get_max_icc_level(
5173 hba->vreg_info.vcc->max_uA,
5174 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5175 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5176
5177 if (hba->vreg_info.vccq)
5178 icc_level = ufshcd_get_max_icc_level(
5179 hba->vreg_info.vccq->max_uA,
5180 icc_level,
5181 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5182
5183 if (hba->vreg_info.vccq2)
5184 icc_level = ufshcd_get_max_icc_level(
5185 hba->vreg_info.vccq2->max_uA,
5186 icc_level,
5187 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5188out:
5189 return icc_level;
5190}
5191
61e07359
DR		 5192static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
5193{
5194 int ret = 0;
5195 int retries;
5196
5197 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5198 /* write attribute */
5199 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5200 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
5201 if (!ret)
5202 break;
5203
5204 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
5205 }
5206
5207 return ret;
5208}
5209
3a4bf06d
YG		 5210static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5211{
5212 int ret;
5213 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
5214 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
5215
5216 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5217 if (ret) {
5218 dev_err(hba->dev,
5219 "%s: Failed reading power descriptor.len = %d ret = %d",
5220 __func__, buff_len, ret);
5221 return;
5222 }
5223
5224 hba->init_prefetch_data.icc_level =
5225 ufshcd_find_max_sup_active_icc_level(hba,
5226 desc_buf, buff_len);
5227 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5228 __func__, hba->init_prefetch_data.icc_level);
5229
61e07359
DR		 5230 ret = ufshcd_set_icc_levels_attr(hba,
5231 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 5232
5233 if (ret)
5234 dev_err(hba->dev,
5235 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5236 __func__, hba->init_prefetch_data.icc_level , ret);
5237
5238}
5239
2a8fa600
SJ		 5240/**
5241 * ufshcd_scsi_add_wlus - Adds required W-LUs
5242 * @hba: per-adapter instance
5243 *
5244 * UFS device specification requires the UFS devices to support 4 well known
5245 * logical units:
5246 * "REPORT_LUNS" (address: 01h)
5247 * "UFS Device" (address: 50h)
5248 * "RPMB" (address: 44h)
5249 * "BOOT" (address: 30h)
5250 * UFS device's power management needs to be controlled by "POWER CONDITION"
5251 * field of SSU (START STOP UNIT) command. But this "power condition" field
5252 * will take effect only when its sent to "UFS device" well known logical unit
5253 * hence we require the scsi_device instance to represent this logical unit in
5254 * order for the UFS host driver to send the SSU command for power management.
5255
5256 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5257 * Block) LU so user space process can control this LU. User space may also
5258 * want to have access to BOOT LU.
5259
5260 * This function adds scsi device instances for each of all well known LUs
5261 * (except "REPORT LUNS" LU).
5262 *
5263 * Returns zero on success (all required W-LUs are added successfully),
5264 * non-zero error value on failure (if failed to add any of the required W-LU).
5265 */
5266static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5267{
5268 int ret = 0;
7c48bfd0
AM		 5269 struct scsi_device *sdev_rpmb;
5270 struct scsi_device *sdev_boot;
2a8fa600
SJ		 5271
5272 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5273 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5274 if (IS_ERR(hba->sdev_ufs_device)) {
5275 ret = PTR_ERR(hba->sdev_ufs_device);
5276 hba->sdev_ufs_device = NULL;
5277 goto out;
5278 }
7c48bfd0 5279 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 5280
7c48bfd0 5281 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5282 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 5283 if (IS_ERR(sdev_boot)) {
5284 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 5285 goto remove_sdev_ufs_device;
5286 }
7c48bfd0 5287 scsi_device_put(sdev_boot);
2a8fa600 5288
7c48bfd0 5289 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5290 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 5291 if (IS_ERR(sdev_rpmb)) {
5292 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 5293 goto remove_sdev_boot;
5294 }
7c48bfd0 5295 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 5296 goto out;
5297
5298remove_sdev_boot:
7c48bfd0 5299 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 5300remove_sdev_ufs_device:
5301 scsi_remove_device(hba->sdev_ufs_device);
5302out:
5303 return ret;
5304}
5305
c58ab7aa
YG		 5306static int ufs_get_device_info(struct ufs_hba *hba,
5307 struct ufs_device_info *card_data)
5308{
5309 int err;
5310 u8 model_index;
5311 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
5312 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
5313
5314 err = ufshcd_read_device_desc(hba, desc_buf,
5315 QUERY_DESC_DEVICE_MAX_SIZE);
5316 if (err) {
5317 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
5318 __func__, err);
5319 goto out;
5320 }
5321
5322 /*
5323 * getting vendor (manufacturerID) and Bank Index in big endian
5324 * format
5325 */
5326 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
5327 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
5328
5329 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
5330
5331 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
5332 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
5333 if (err) {
5334 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
5335 __func__, err);
5336 goto out;
5337 }
5338
5339 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
5340 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
5341 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
5342 MAX_MODEL_LEN));
5343
5344 /* Null terminate the model string */
5345 card_data->model[MAX_MODEL_LEN] = '\0';
5346
5347out:
5348 return err;
5349}
5350
5351void ufs_advertise_fixup_device(struct ufs_hba *hba)
5352{
5353 int err;
5354 struct ufs_dev_fix *f;
5355 struct ufs_device_info card_data;
5356
5357 card_data.wmanufacturerid = 0;
5358
5359 err = ufs_get_device_info(hba, &card_data);
5360 if (err) {
5361 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
5362 __func__, err);
5363 return;
5364 }
5365
5366 for (f = ufs_fixups; f->quirk; f++) {
5367 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
5368 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
5369 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
5370 !strcmp(f->card.model, UFS_ANY_MODEL)))
5371 hba->dev_quirks |= f->quirk;
5372 }
5373}
5374
37113106
YG		 5375/**
5376 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
5377 * @hba: per-adapter instance
5378 *
5379 * PA_TActivate parameter can be tuned manually if UniPro version is less than
5380 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
5381 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
5382 * the hibern8 exit latency.
5383 *
5384 * Returns zero on success, non-zero error value on failure.
5385 */
5386static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
5387{
5388 int ret = 0;
5389 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
5390
5391 ret = ufshcd_dme_peer_get(hba,
5392 UIC_ARG_MIB_SEL(
5393 RX_MIN_ACTIVATETIME_CAPABILITY,
5394 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5395 &peer_rx_min_activatetime);
5396 if (ret)
5397 goto out;
5398
5399 /* make sure proper unit conversion is applied */
5400 tuned_pa_tactivate =
5401 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
5402 / PA_TACTIVATE_TIME_UNIT_US);
5403 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5404 tuned_pa_tactivate);
5405
5406out:
5407 return ret;
5408}
5409
5410/**
5411 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
5412 * @hba: per-adapter instance
5413 *
5414 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
5415 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
5416 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
5417 * This optimal value can help reduce the hibern8 exit latency.
5418 *
5419 * Returns zero on success, non-zero error value on failure.
5420 */
5421static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
5422{
5423 int ret = 0;
5424 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
5425 u32 max_hibern8_time, tuned_pa_hibern8time;
5426
5427 ret = ufshcd_dme_get(hba,
5428 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
5429 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
5430 &local_tx_hibern8_time_cap);
5431 if (ret)
5432 goto out;
5433
5434 ret = ufshcd_dme_peer_get(hba,
5435 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
5436 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5437 &peer_rx_hibern8_time_cap);
5438 if (ret)
5439 goto out;
5440
5441 max_hibern8_time = max(local_tx_hibern8_time_cap,
5442 peer_rx_hibern8_time_cap);
5443 /* make sure proper unit conversion is applied */
5444 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
5445 / PA_HIBERN8_TIME_UNIT_US);
5446 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
5447 tuned_pa_hibern8time);
5448out:
5449 return ret;
5450}
5451
c6a6db43 5452/**
5453 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
5454 * less than device PA_TACTIVATE time.
5455 * @hba: per-adapter instance
5456 *
5457 * Some UFS devices require host PA_TACTIVATE to be lower than device
5458 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
5459 * for such devices.
5460 *
5461 * Returns zero on success, non-zero error value on failure.
5462 */
5463static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
5464{
5465 int ret = 0;
5466 u32 granularity, peer_granularity;
5467 u32 pa_tactivate, peer_pa_tactivate;
5468 u32 pa_tactivate_us, peer_pa_tactivate_us;
5469 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
5470
5471 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5472 &granularity);
5473 if (ret)
5474 goto out;
5475
5476 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5477 &peer_granularity);
5478 if (ret)
5479 goto out;
5480
5481 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
5482 (granularity > PA_GRANULARITY_MAX_VAL)) {
5483 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
5484 __func__, granularity);
5485 return -EINVAL;
5486 }
5487
5488 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
5489 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
5490 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
5491 __func__, peer_granularity);
5492 return -EINVAL;
5493 }
5494
5495 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
5496 if (ret)
5497 goto out;
5498
5499 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
5500 &peer_pa_tactivate);
5501 if (ret)
5502 goto out;
5503
5504 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
5505 peer_pa_tactivate_us = peer_pa_tactivate *
5506 gran_to_us_table[peer_granularity - 1];
5507
5508 if (pa_tactivate_us > peer_pa_tactivate_us) {
5509 u32 new_peer_pa_tactivate;
5510
5511 new_peer_pa_tactivate = pa_tactivate_us /
5512 gran_to_us_table[peer_granularity - 1];
5513 new_peer_pa_tactivate++;
5514 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5515 new_peer_pa_tactivate);
5516 }
5517
5518out:
5519 return ret;
5520}
5521
37113106
YG		 5522static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
5523{
5524 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
5525 ufshcd_tune_pa_tactivate(hba);
5526 ufshcd_tune_pa_hibern8time(hba);
5527 }
5528
5529 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
5530 /* set 1ms timeout for PA_TACTIVATE */
5531 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 5532
5533 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
5534 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 5535
5536 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 5537}
5538
6ccf44fe 5539/**
1d337ec2
SRT		 5540 * ufshcd_probe_hba - probe hba to detect device and initialize
5541 * @hba: per-adapter instance
5542 *
5543 * Execute link-startup and verify device initialization
6ccf44fe 5544 */
1d337ec2 5545static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 5546{
6ccf44fe 5547 int ret;
7ff5ab47 5548 ktime_t start = ktime_get();
6ccf44fe
SJ		 5549
5550 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 5551 if (ret)
5552 goto out;
5553
afdfff59
YG		 5554 /* set the default level for urgent bkops */
5555 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5556 hba->is_urgent_bkops_lvl_checked = false;
5557
57d104c1
SJ		 5558 /* UniPro link is active now */
5559 ufshcd_set_link_active(hba);
d3e89bac 5560
5a0b0cb9
SRT		 5561 ret = ufshcd_verify_dev_init(hba);
5562 if (ret)
5563 goto out;
68078d5c
DR		 5564
5565 ret = ufshcd_complete_dev_init(hba);
5566 if (ret)
5567 goto out;
5a0b0cb9 5568
c58ab7aa 5569 ufs_advertise_fixup_device(hba);
37113106 5570 ufshcd_tune_unipro_params(hba);
60f01870
YG		 5571
5572 ret = ufshcd_set_vccq_rail_unused(hba,
5573 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5574 if (ret)
5575 goto out;
5576
57d104c1
SJ		 5577 /* UFS device is also active now */
5578 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5579 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 5580 hba->wlun_dev_clr_ua = true;
5581
7eb584db
DR		 5582 if (ufshcd_get_max_pwr_mode(hba)) {
5583 dev_err(hba->dev,
5584 "%s: Failed getting max supported power mode\n",
5585 __func__);
5586 } else {
5587 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 5588 if (ret) {
7eb584db
DR		 5589 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5590 __func__, ret);
8643ae66
DL		 5591 goto out;
5592 }
7eb584db 5593 }
57d104c1 5594
53c12d0e
YG		 5595 /* set the state as operational after switching to desired gear */
5596 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 5597 /*
5598 * If we are in error handling context or in power management callbacks
5599 * context, no need to scan the host
5600 */
5601 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5602 bool flag;
5603
5604 /* clear any previous UFS device information */
5605 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 5606 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5607 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5608 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5609
3a4bf06d
YG		 5610 if (!hba->is_init_prefetch)
5611 ufshcd_init_icc_levels(hba);
5612
2a8fa600
SJ		 5613 /* Add required well known logical units to scsi mid layer */
5614 if (ufshcd_scsi_add_wlus(hba))
5615 goto out;
5616
3441da7d
SRT		 5617 scsi_scan_host(hba->host);
5618 pm_runtime_put_sync(hba->dev);
5619 }
3a4bf06d 5620
fcb0c4b0
ST		 5621 /* Resume devfreq after UFS device is detected */
5622 if (ufshcd_is_clkscaling_supported(hba)) {
5623 ufshcd_resume_clkscaling(hba);
5624 hba->clk_scaling.is_allowed = true;
5625 }
5626
3a4bf06d
YG		 5627 if (!hba->is_init_prefetch)
5628 hba->is_init_prefetch = true;
5629
5a0b0cb9 5630out:
1d337ec2
SRT		 5631 /*
5632 * If we failed to initialize the device or the device is not
5633 * present, turn off the power/clocks etc.
5634 */
57d104c1
SJ		 5635 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5636 pm_runtime_put_sync(hba->dev);
1d337ec2 5637 ufshcd_hba_exit(hba);
57d104c1 5638 }
1d337ec2 5639
7ff5ab47 5640 trace_ufshcd_init(dev_name(hba->dev), ret,
5641 ktime_to_us(ktime_sub(ktime_get(), start)),
5642 hba->uic_link_state, hba->curr_dev_pwr_mode);
1d337ec2
SRT		 5643 return ret;
5644}
5645
5646/**
5647 * ufshcd_async_scan - asynchronous execution for probing hba
5648 * @data: data pointer to pass to this function
5649 * @cookie: cookie data
5650 */
5651static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5652{
5653 struct ufs_hba *hba = (struct ufs_hba *)data;
5654
5655 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 5656}
5657
f550c65b
YG		 5658static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5659{
5660 unsigned long flags;
5661 struct Scsi_Host *host;
5662 struct ufs_hba *hba;
5663 int index;
5664 bool found = false;
5665
5666 if (!scmd || !scmd->device || !scmd->device->host)
5667 return BLK_EH_NOT_HANDLED;
5668
5669 host = scmd->device->host;
5670 hba = shost_priv(host);
5671 if (!hba)
5672 return BLK_EH_NOT_HANDLED;
5673
5674 spin_lock_irqsave(host->host_lock, flags);
5675
5676 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5677 if (hba->lrb[index].cmd == scmd) {
5678 found = true;
5679 break;
5680 }
5681 }
5682
5683 spin_unlock_irqrestore(host->host_lock, flags);
5684
5685 /*
5686 * Bypass SCSI error handling and reset the block layer timer if this
5687 * SCSI command was not actually dispatched to UFS driver, otherwise
5688 * let SCSI layer handle the error as usual.
5689 */
5690 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5691}
5692
7a3e97b0
SY		 5693static struct scsi_host_template ufshcd_driver_template = {
5694 .module = THIS_MODULE,
5695 .name = UFSHCD,
5696 .proc_name = UFSHCD,
5697 .queuecommand = ufshcd_queuecommand,
5698 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5699 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5700 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5701 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5702 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 5703 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5704 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5705 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 5706 .this_id = -1,
5707 .sg_tablesize = SG_ALL,
5708 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5709 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5710 .max_host_blocked = 1,
c40ecc12 5711 .track_queue_depth = 1,
7a3e97b0
SY		 5712};
5713
57d104c1
SJ		 5714static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5715 int ua)
5716{
7b16a07c 5717 int ret;
57d104c1 5718
7b16a07c
BA		 5719 if (!vreg)
5720 return 0;
57d104c1 5721
7b16a07c
BA		 5722 ret = regulator_set_load(vreg->reg, ua);
5723 if (ret < 0) {
5724 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5725 __func__, vreg->name, ua, ret);
57d104c1
SJ		 5726 }
5727
5728 return ret;
5729}
5730
5731static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5732 struct ufs_vreg *vreg)
5733{
60f01870
YG		 5734 if (!vreg)
5735 return 0;
5736 else if (vreg->unused)
5737 return 0;
5738 else
5739 return ufshcd_config_vreg_load(hba->dev, vreg,
5740 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 5741}
5742
5743static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5744 struct ufs_vreg *vreg)
5745{
60f01870
YG		 5746 if (!vreg)
5747 return 0;
5748 else if (vreg->unused)
5749 return 0;
5750 else
5751 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 5752}
5753
aa497613
SRT		 5754static int ufshcd_config_vreg(struct device *dev,
5755 struct ufs_vreg *vreg, bool on)
5756{
5757 int ret = 0;
5758 struct regulator *reg = vreg->reg;
5759 const char *name = vreg->name;
5760 int min_uV, uA_load;
5761
5762 BUG_ON(!vreg);
5763
5764 if (regulator_count_voltages(reg) > 0) {
5765 min_uV = on ? vreg->min_uV : 0;
5766 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5767 if (ret) {
5768 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5769 __func__, name, ret);
5770 goto out;
5771 }
5772
5773 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 5774 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5775 if (ret)
aa497613 5776 goto out;
aa497613
SRT		 5777 }
5778out:
5779 return ret;
5780}
5781
5782static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5783{
5784 int ret = 0;
5785
60f01870
YG		 5786 if (!vreg)
5787 goto out;
5788 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 5789 goto out;
5790
5791 ret = ufshcd_config_vreg(dev, vreg, true);
5792 if (!ret)
5793 ret = regulator_enable(vreg->reg);
5794
5795 if (!ret)
5796 vreg->enabled = true;
5797 else
5798 dev_err(dev, "%s: %s enable failed, err=%d\n",
5799 __func__, vreg->name, ret);
5800out:
5801 return ret;
5802}
5803
5804static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5805{
5806 int ret = 0;
5807
60f01870
YG		 5808 if (!vreg)
5809 goto out;
5810 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 5811 goto out;
5812
5813 ret = regulator_disable(vreg->reg);
5814
5815 if (!ret) {
5816 /* ignore errors on applying disable config */
5817 ufshcd_config_vreg(dev, vreg, false);
5818 vreg->enabled = false;
5819 } else {
5820 dev_err(dev, "%s: %s disable failed, err=%d\n",
5821 __func__, vreg->name, ret);
5822 }
5823out:
5824 return ret;
5825}
5826
5827static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5828{
5829 int ret = 0;
5830 struct device *dev = hba->dev;
5831 struct ufs_vreg_info *info = &hba->vreg_info;
5832
5833 if (!info)
5834 goto out;
5835
5836 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5837 if (ret)
5838 goto out;
5839
5840 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5841 if (ret)
5842 goto out;
5843
5844 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5845 if (ret)
5846 goto out;
5847
5848out:
5849 if (ret) {
5850 ufshcd_toggle_vreg(dev, info->vccq2, false);
5851 ufshcd_toggle_vreg(dev, info->vccq, false);
5852 ufshcd_toggle_vreg(dev, info->vcc, false);
5853 }
5854 return ret;
5855}
5856
6a771a65
RS		 5857static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5858{
5859 struct ufs_vreg_info *info = &hba->vreg_info;
5860
5861 if (info)
5862 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5863
5864 return 0;
5865}
5866
aa497613
SRT		 5867static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5868{
5869 int ret = 0;
5870
5871 if (!vreg)
5872 goto out;
5873
5874 vreg->reg = devm_regulator_get(dev, vreg->name);
5875 if (IS_ERR(vreg->reg)) {
5876 ret = PTR_ERR(vreg->reg);
5877 dev_err(dev, "%s: %s get failed, err=%d\n",
5878 __func__, vreg->name, ret);
5879 }
5880out:
5881 return ret;
5882}
5883
5884static int ufshcd_init_vreg(struct ufs_hba *hba)
5885{
5886 int ret = 0;
5887 struct device *dev = hba->dev;
5888 struct ufs_vreg_info *info = &hba->vreg_info;
5889
5890 if (!info)
5891 goto out;
5892
5893 ret = ufshcd_get_vreg(dev, info->vcc);
5894 if (ret)
5895 goto out;
5896
5897 ret = ufshcd_get_vreg(dev, info->vccq);
5898 if (ret)
5899 goto out;
5900
5901 ret = ufshcd_get_vreg(dev, info->vccq2);
5902out:
5903 return ret;
5904}
5905
6a771a65
RS		 5906static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5907{
5908 struct ufs_vreg_info *info = &hba->vreg_info;
5909
5910 if (info)
5911 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5912
5913 return 0;
5914}
5915
60f01870
YG		 5916static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5917{
5918 int ret = 0;
5919 struct ufs_vreg_info *info = &hba->vreg_info;
5920
5921 if (!info)
5922 goto out;
5923 else if (!info->vccq)
5924 goto out;
5925
5926 if (unused) {
5927 /* shut off the rail here */
5928 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5929 /*
5930 * Mark this rail as no longer used, so it doesn't get enabled
5931 * later by mistake
5932 */
5933 if (!ret)
5934 info->vccq->unused = true;
5935 } else {
5936 /*
5937 * rail should have been already enabled hence just make sure
5938 * that unused flag is cleared.
5939 */
5940 info->vccq->unused = false;
5941 }
5942out:
5943 return ret;
5944}
5945
57d104c1
SJ		 5946static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5947 bool skip_ref_clk)
c6e79dac
SRT		 5948{
5949 int ret = 0;
5950 struct ufs_clk_info *clki;
5951 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5952 unsigned long flags;
c6e79dac
SRT		 5953
5954 if (!head || list_empty(head))
5955 goto out;
5956
1e879e8f
SJ		 5957 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
5958 if (ret)
5959 return ret;
5960
c6e79dac
SRT		 5961 list_for_each_entry(clki, head, list) {
5962 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 5963 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5964 continue;
5965
c6e79dac
SRT		 5966 if (on && !clki->enabled) {
5967 ret = clk_prepare_enable(clki->clk);
5968 if (ret) {
5969 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5970 __func__, clki->name, ret);
5971 goto out;
5972 }
5973 } else if (!on && clki->enabled) {
5974 clk_disable_unprepare(clki->clk);
5975 }
5976 clki->enabled = on;
5977 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5978 clki->name, on ? "en" : "dis");
5979 }
5980 }
1ab27c9c 5981
1e879e8f
SJ		 5982 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
5983 if (ret)
5984 return ret;
5985
c6e79dac
SRT		 5986out:
5987 if (ret) {
5988 list_for_each_entry(clki, head, list) {
5989 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5990 clk_disable_unprepare(clki->clk);
5991 }
7ff5ab47 5992 } else if (!ret && on) {
1ab27c9c
ST		 5993 spin_lock_irqsave(hba->host->host_lock, flags);
5994 hba->clk_gating.state = CLKS_ON;
7ff5ab47 5995 trace_ufshcd_clk_gating(dev_name(hba->dev),
5996 hba->clk_gating.state);
1ab27c9c 5997 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 5998 }
7ff5ab47 5999
c6e79dac
SRT		 6000 return ret;
6001}
6002
57d104c1
SJ		 6003static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6004{
6005 return __ufshcd_setup_clocks(hba, on, false);
6006}
6007
c6e79dac
SRT		 6008static int ufshcd_init_clocks(struct ufs_hba *hba)
6009{
6010 int ret = 0;
6011 struct ufs_clk_info *clki;
6012 struct device *dev = hba->dev;
6013 struct list_head *head = &hba->clk_list_head;
6014
6015 if (!head || list_empty(head))
6016 goto out;
6017
6018 list_for_each_entry(clki, head, list) {
6019 if (!clki->name)
6020 continue;
6021
6022 clki->clk = devm_clk_get(dev, clki->name);
6023 if (IS_ERR(clki->clk)) {
6024 ret = PTR_ERR(clki->clk);
6025 dev_err(dev, "%s: %s clk get failed, %d\n",
6026 __func__, clki->name, ret);
6027 goto out;
6028 }
6029
6030 if (clki->max_freq) {
6031 ret = clk_set_rate(clki->clk, clki->max_freq);
6032 if (ret) {
6033 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6034 __func__, clki->name,
6035 clki->max_freq, ret);
6036 goto out;
6037 }
856b3483 6038 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 6039 }
6040 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6041 clki->name, clk_get_rate(clki->clk));
6042 }
6043out:
6044 return ret;
6045}
6046
5c0c28a8
SRT		 6047static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6048{
6049 int err = 0;
6050
6051 if (!hba->vops)
6052 goto out;
6053
0263bcd0
YG		 6054 err = ufshcd_vops_init(hba);
6055 if (err)
6056 goto out;
5c0c28a8 6057
0263bcd0
YG		 6058 err = ufshcd_vops_setup_regulators(hba, true);
6059 if (err)
6060 goto out_exit;
5c0c28a8
SRT		 6061
6062 goto out;
6063
5c0c28a8 6064out_exit:
0263bcd0 6065 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6066out:
6067 if (err)
6068 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 6069 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 6070 return err;
6071}
6072
6073static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6074{
6075 if (!hba->vops)
6076 return;
6077
0263bcd0 6078 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 6079
0263bcd0 6080 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6081}
6082
aa497613
SRT		 6083static int ufshcd_hba_init(struct ufs_hba *hba)
6084{
6085 int err;
6086
6a771a65
RS		 6087 /*
6088 * Handle host controller power separately from the UFS device power
6089 * rails as it will help controlling the UFS host controller power
6090 * collapse easily which is different than UFS device power collapse.
6091 * Also, enable the host controller power before we go ahead with rest
6092 * of the initialization here.
6093 */
6094 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 6095 if (err)
6096 goto out;
6097
6a771a65 6098 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 6099 if (err)
6100 goto out;
6101
6a771a65
RS		 6102 err = ufshcd_init_clocks(hba);
6103 if (err)
6104 goto out_disable_hba_vreg;
6105
6106 err = ufshcd_setup_clocks(hba, true);
6107 if (err)
6108 goto out_disable_hba_vreg;
6109
c6e79dac
SRT		 6110 err = ufshcd_init_vreg(hba);
6111 if (err)
6112 goto out_disable_clks;
6113
6114 err = ufshcd_setup_vreg(hba, true);
6115 if (err)
6116 goto out_disable_clks;
6117
aa497613
SRT		 6118 err = ufshcd_variant_hba_init(hba);
6119 if (err)
6120 goto out_disable_vreg;
6121
1d337ec2 6122 hba->is_powered = true;
aa497613
SRT		 6123 goto out;
6124
6125out_disable_vreg:
6126 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 6127out_disable_clks:
6128 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 6129out_disable_hba_vreg:
6130 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 6131out:
6132 return err;
6133}
6134
6135static void ufshcd_hba_exit(struct ufs_hba *hba)
6136{
1d337ec2
SRT		 6137 if (hba->is_powered) {
6138 ufshcd_variant_hba_exit(hba);
6139 ufshcd_setup_vreg(hba, false);
a508253d 6140 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 6141 ufshcd_setup_clocks(hba, false);
6142 ufshcd_setup_hba_vreg(hba, false);
6143 hba->is_powered = false;
6144 }
aa497613
SRT		 6145}
6146
57d104c1
SJ		 6147static int
6148ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6149{
6150 unsigned char cmd[6] = {REQUEST_SENSE,
6151 0,
6152 0,
6153 0,
dcea0bfb 6154 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 6155 0};
6156 char *buffer;
6157 int ret;
6158
dcea0bfb 6159 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 6160 if (!buffer) {
6161 ret = -ENOMEM;
6162 goto out;
6163 }
6164
6165 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 6166 UFSHCD_REQ_SENSE_SIZE, NULL,
e8064021 6167 msecs_to_jiffies(1000), 3, NULL, 0, RQF_PM);
57d104c1
SJ		 6168 if (ret)
6169 pr_err("%s: failed with err %d\n", __func__, ret);
6170
6171 kfree(buffer);
6172out:
6173 return ret;
6174}
6175
6176/**
6177 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6178 * power mode
6179 * @hba: per adapter instance
6180 * @pwr_mode: device power mode to set
6181 *
6182 * Returns 0 if requested power mode is set successfully
6183 * Returns non-zero if failed to set the requested power mode
6184 */
6185static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
6186 enum ufs_dev_pwr_mode pwr_mode)
6187{
6188 unsigned char cmd[6] = { START_STOP };
6189 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 6190 struct scsi_device *sdp;
6191 unsigned long flags;
57d104c1
SJ		 6192 int ret;
6193
7c48bfd0
AM		 6194 spin_lock_irqsave(hba->host->host_lock, flags);
6195 sdp = hba->sdev_ufs_device;
6196 if (sdp) {
6197 ret = scsi_device_get(sdp);
6198 if (!ret && !scsi_device_online(sdp)) {
6199 ret = -ENODEV;
6200 scsi_device_put(sdp);
6201 }
6202 } else {
6203 ret = -ENODEV;
6204 }
6205 spin_unlock_irqrestore(hba->host->host_lock, flags);
6206
6207 if (ret)
6208 return ret;
57d104c1
SJ		 6209
6210 /*
6211 * If scsi commands fail, the scsi mid-layer schedules scsi error-
6212 * handling, which would wait for host to be resumed. Since we know
6213 * we are functional while we are here, skip host resume in error
6214 * handling context.
6215 */
6216 hba->host->eh_noresume = 1;
6217 if (hba->wlun_dev_clr_ua) {
6218 ret = ufshcd_send_request_sense(hba, sdp);
6219 if (ret)
6220 goto out;
6221 /* Unit attention condition is cleared now */
6222 hba->wlun_dev_clr_ua = false;
6223 }
6224
6225 cmd[4] = pwr_mode << 4;
6226
6227 /*
6228 * Current function would be generally called from the power management
e8064021 6229 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 6230 * already suspended childs.
6231 */
6232 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
e8064021 6233 START_STOP_TIMEOUT, 0, NULL, 0, RQF_PM);
57d104c1
SJ		 6234 if (ret) {
6235 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 6236 "START_STOP failed for power mode: %d, result %x\n",
6237 pwr_mode, ret);
21045519
HR		 6238 if (driver_byte(ret) & DRIVER_SENSE)
6239 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 6240 }
6241
6242 if (!ret)
6243 hba->curr_dev_pwr_mode = pwr_mode;
6244out:
7c48bfd0 6245 scsi_device_put(sdp);
57d104c1
SJ		 6246 hba->host->eh_noresume = 0;
6247 return ret;
6248}
6249
6250static int ufshcd_link_state_transition(struct ufs_hba *hba,
6251 enum uic_link_state req_link_state,
6252 int check_for_bkops)
6253{
6254 int ret = 0;
6255
6256 if (req_link_state == hba->uic_link_state)
6257 return 0;
6258
6259 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
6260 ret = ufshcd_uic_hibern8_enter(hba);
6261 if (!ret)
6262 ufshcd_set_link_hibern8(hba);
6263 else
6264 goto out;
6265 }
6266 /*
6267 * If autobkops is enabled, link can't be turned off because
6268 * turning off the link would also turn off the device.
6269 */
6270 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
6271 (!check_for_bkops || (check_for_bkops &&
6272 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 6273 /*
6274 * Let's make sure that link is in low power mode, we are doing
6275 * this currently by putting the link in Hibern8. Otherway to
6276 * put the link in low power mode is to send the DME end point
6277 * to device and then send the DME reset command to local
6278 * unipro. But putting the link in hibern8 is much faster.
6279 */
6280 ret = ufshcd_uic_hibern8_enter(hba);
6281 if (ret)
6282 goto out;
57d104c1
SJ		 6283 /*
6284 * Change controller state to "reset state" which
6285 * should also put the link in off/reset state
6286 */
596585a2 6287 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 6288 /*
6289 * TODO: Check if we need any delay to make sure that
6290 * controller is reset
6291 */
6292 ufshcd_set_link_off(hba);
6293 }
6294
6295out:
6296 return ret;
6297}
6298
6299static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
6300{
b799fdf7
YG		 6301 /*
6302 * It seems some UFS devices may keep drawing more than sleep current
6303 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
6304 * To avoid this situation, add 2ms delay before putting these UFS
6305 * rails in LPM mode.
6306 */
6307 if (!ufshcd_is_link_active(hba) &&
6308 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
6309 usleep_range(2000, 2100);
6310
57d104c1
SJ		 6311 /*
6312 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
6313 * power.
6314 *
6315 * If UFS device and link is in OFF state, all power supplies (VCC,
6316 * VCCQ, VCCQ2) can be turned off if power on write protect is not
6317 * required. If UFS link is inactive (Hibern8 or OFF state) and device
6318 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
6319 *
6320 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
6321 * in low power state which would save some power.
6322 */
6323 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
6324 !hba->dev_info.is_lu_power_on_wp) {
6325 ufshcd_setup_vreg(hba, false);
6326 } else if (!ufshcd_is_ufs_dev_active(hba)) {
6327 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
6328 if (!ufshcd_is_link_active(hba)) {
6329 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
6330 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
6331 }
6332 }
6333}
6334
6335static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
6336{
6337 int ret = 0;
6338
6339 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
6340 !hba->dev_info.is_lu_power_on_wp) {
6341 ret = ufshcd_setup_vreg(hba, true);
6342 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 6343 if (!ret && !ufshcd_is_link_active(hba)) {
6344 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6345 if (ret)
6346 goto vcc_disable;
6347 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6348 if (ret)
6349 goto vccq_lpm;
6350 }
69d72ac8 6351 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 6352 }
6353 goto out;
6354
6355vccq_lpm:
6356 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
6357vcc_disable:
6358 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
6359out:
6360 return ret;
6361}
6362
6363static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
6364{
6365 if (ufshcd_is_link_off(hba))
6366 ufshcd_setup_hba_vreg(hba, false);
6367}
6368
6369static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
6370{
6371 if (ufshcd_is_link_off(hba))
6372 ufshcd_setup_hba_vreg(hba, true);
6373}
6374
7a3e97b0 6375/**
57d104c1 6376 * ufshcd_suspend - helper function for suspend operations
3b1d0580 6377 * @hba: per adapter instance
57d104c1
SJ		 6378 * @pm_op: desired low power operation type
6379 *
6380 * This function will try to put the UFS device and link into low power
6381 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
6382 * (System PM level).
6383 *
6384 * If this function is called during shutdown, it will make sure that
6385 * both UFS device and UFS link is powered off.
7a3e97b0 6386 *
57d104c1
SJ		 6387 * NOTE: UFS device & link must be active before we enter in this function.
6388 *
6389 * Returns 0 for success and non-zero for failure
7a3e97b0 6390 */
57d104c1 6391static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6392{
57d104c1
SJ		 6393 int ret = 0;
6394 enum ufs_pm_level pm_lvl;
6395 enum ufs_dev_pwr_mode req_dev_pwr_mode;
6396 enum uic_link_state req_link_state;
6397
6398 hba->pm_op_in_progress = 1;
6399 if (!ufshcd_is_shutdown_pm(pm_op)) {
6400 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
6401 hba->rpm_lvl : hba->spm_lvl;
6402 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
6403 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
6404 } else {
6405 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
6406 req_link_state = UIC_LINK_OFF_STATE;
6407 }
6408
7a3e97b0 6409 /*
57d104c1
SJ		 6410 * If we can't transition into any of the low power modes
6411 * just gate the clocks.
7a3e97b0 6412 */
1ab27c9c
ST		 6413 ufshcd_hold(hba, false);
6414 hba->clk_gating.is_suspended = true;
6415
d6fcf81a
SJ		 6416 ufshcd_suspend_clkscaling(hba);
6417
57d104c1
SJ		 6418 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
6419 req_link_state == UIC_LINK_ACTIVE_STATE) {
6420 goto disable_clks;
6421 }
7a3e97b0 6422
57d104c1
SJ		 6423 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
6424 (req_link_state == hba->uic_link_state))
d6fcf81a 6425 goto enable_gating;
57d104c1
SJ		 6426
6427 /* UFS device & link must be active before we enter in this function */
6428 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
6429 ret = -EINVAL;
d6fcf81a 6430 goto enable_gating;
57d104c1
SJ		 6431 }
6432
6433 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 6434 if (ufshcd_can_autobkops_during_suspend(hba)) {
6435 /*
6436 * The device is idle with no requests in the queue,
6437 * allow background operations if bkops status shows
6438 * that performance might be impacted.
6439 */
6440 ret = ufshcd_urgent_bkops(hba);
6441 if (ret)
6442 goto enable_gating;
6443 } else {
6444 /* make sure that auto bkops is disabled */
6445 ufshcd_disable_auto_bkops(hba);
6446 }
57d104c1
SJ		 6447 }
6448
6449 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
6450 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
6451 !ufshcd_is_runtime_pm(pm_op))) {
6452 /* ensure that bkops is disabled */
6453 ufshcd_disable_auto_bkops(hba);
6454 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
6455 if (ret)
1ab27c9c 6456 goto enable_gating;
57d104c1
SJ		 6457 }
6458
6459 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
6460 if (ret)
6461 goto set_dev_active;
6462
6463 ufshcd_vreg_set_lpm(hba);
6464
6465disable_clks:
6466 /*
6467 * Call vendor specific suspend callback. As these callbacks may access
6468 * vendor specific host controller register space call them before the
6469 * host clocks are ON.
6470 */
0263bcd0
YG		 6471 ret = ufshcd_vops_suspend(hba, pm_op);
6472 if (ret)
6473 goto set_link_active;
57d104c1 6474
57d104c1
SJ		 6475 if (!ufshcd_is_link_active(hba))
6476 ufshcd_setup_clocks(hba, false);
6477 else
6478 /* If link is active, device ref_clk can't be switched off */
6479 __ufshcd_setup_clocks(hba, false, true);
6480
1ab27c9c 6481 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 6482 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 6483 /*
6484 * Disable the host irq as host controller as there won't be any
0263bcd0 6485 * host controller transaction expected till resume.
57d104c1
SJ		 6486 */
6487 ufshcd_disable_irq(hba);
6488 /* Put the host controller in low power mode if possible */
6489 ufshcd_hba_vreg_set_lpm(hba);
6490 goto out;
6491
57d104c1 6492set_link_active:
a508253d 6493 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 6494 ufshcd_vreg_set_hpm(hba);
6495 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
6496 ufshcd_set_link_active(hba);
6497 else if (ufshcd_is_link_off(hba))
6498 ufshcd_host_reset_and_restore(hba);
6499set_dev_active:
6500 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
6501 ufshcd_disable_auto_bkops(hba);
1ab27c9c 6502enable_gating:
d6fcf81a 6503 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 6504 hba->clk_gating.is_suspended = false;
6505 ufshcd_release(hba);
57d104c1
SJ		 6506out:
6507 hba->pm_op_in_progress = 0;
6508 return ret;
7a3e97b0
SY		 6509}
6510
6511/**
57d104c1 6512 * ufshcd_resume - helper function for resume operations
3b1d0580 6513 * @hba: per adapter instance
57d104c1 6514 * @pm_op: runtime PM or system PM
7a3e97b0 6515 *
57d104c1
SJ		 6516 * This function basically brings the UFS device, UniPro link and controller
6517 * to active state.
6518 *
6519 * Returns 0 for success and non-zero for failure
7a3e97b0 6520 */
57d104c1 6521static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6522{
57d104c1
SJ		 6523 int ret;
6524 enum uic_link_state old_link_state;
6525
6526 hba->pm_op_in_progress = 1;
6527 old_link_state = hba->uic_link_state;
6528
6529 ufshcd_hba_vreg_set_hpm(hba);
6530 /* Make sure clocks are enabled before accessing controller */
6531 ret = ufshcd_setup_clocks(hba, true);
6532 if (ret)
6533 goto out;
6534
57d104c1
SJ		 6535 /* enable the host irq as host controller would be active soon */
6536 ret = ufshcd_enable_irq(hba);
6537 if (ret)
6538 goto disable_irq_and_vops_clks;
6539
6540 ret = ufshcd_vreg_set_hpm(hba);
6541 if (ret)
6542 goto disable_irq_and_vops_clks;
6543
7a3e97b0 6544 /*
57d104c1
SJ		 6545 * Call vendor specific resume callback. As these callbacks may access
6546 * vendor specific host controller register space call them when the
6547 * host clocks are ON.
7a3e97b0 6548 */
0263bcd0
YG		 6549 ret = ufshcd_vops_resume(hba, pm_op);
6550 if (ret)
6551 goto disable_vreg;
57d104c1
SJ		 6552
6553 if (ufshcd_is_link_hibern8(hba)) {
6554 ret = ufshcd_uic_hibern8_exit(hba);
6555 if (!ret)
6556 ufshcd_set_link_active(hba);
6557 else
6558 goto vendor_suspend;
6559 } else if (ufshcd_is_link_off(hba)) {
6560 ret = ufshcd_host_reset_and_restore(hba);
6561 /*
6562 * ufshcd_host_reset_and_restore() should have already
6563 * set the link state as active
6564 */
6565 if (ret || !ufshcd_is_link_active(hba))
6566 goto vendor_suspend;
6567 }
6568
6569 if (!ufshcd_is_ufs_dev_active(hba)) {
6570 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6571 if (ret)
6572 goto set_old_link_state;
6573 }
6574
4e768e76 6575 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
6576 ufshcd_enable_auto_bkops(hba);
6577 else
6578 /*
6579 * If BKOPs operations are urgently needed at this moment then
6580 * keep auto-bkops enabled or else disable it.
6581 */
6582 ufshcd_urgent_bkops(hba);
6583
1ab27c9c
ST		 6584 hba->clk_gating.is_suspended = false;
6585
fcb0c4b0
ST		 6586 if (hba->clk_scaling.is_allowed)
6587 ufshcd_resume_clkscaling(hba);
856b3483 6588
1ab27c9c
ST		 6589 /* Schedule clock gating in case of no access to UFS device yet */
6590 ufshcd_release(hba);
57d104c1
SJ		 6591 goto out;
6592
6593set_old_link_state:
6594 ufshcd_link_state_transition(hba, old_link_state, 0);
6595vendor_suspend:
0263bcd0 6596 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 6597disable_vreg:
6598 ufshcd_vreg_set_lpm(hba);
6599disable_irq_and_vops_clks:
6600 ufshcd_disable_irq(hba);
a508253d 6601 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 6602 ufshcd_setup_clocks(hba, false);
6603out:
6604 hba->pm_op_in_progress = 0;
6605 return ret;
6606}
6607
6608/**
6609 * ufshcd_system_suspend - system suspend routine
6610 * @hba: per adapter instance
6611 * @pm_op: runtime PM or system PM
6612 *
6613 * Check the description of ufshcd_suspend() function for more details.
6614 *
6615 * Returns 0 for success and non-zero for failure
6616 */
6617int ufshcd_system_suspend(struct ufs_hba *hba)
6618{
6619 int ret = 0;
7ff5ab47 6620 ktime_t start = ktime_get();
57d104c1
SJ		 6621
6622 if (!hba || !hba->is_powered)
233b594b 6623 return 0;
57d104c1 6624
0b257734 6625 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6626 hba->curr_dev_pwr_mode) &&
6627 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
6628 hba->uic_link_state))
6629 goto out;
57d104c1 6630
0b257734 6631 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 6632 /*
6633 * UFS device and/or UFS link low power states during runtime
6634 * suspend seems to be different than what is expected during
6635 * system suspend. Hence runtime resume the devic & link and
6636 * let the system suspend low power states to take effect.
6637 * TODO: If resume takes longer time, we might have optimize
6638 * it in future by not resuming everything if possible.
6639 */
6640 ret = ufshcd_runtime_resume(hba);
6641 if (ret)
6642 goto out;
6643 }
6644
6645 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6646out:
7ff5ab47 6647 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
6648 ktime_to_us(ktime_sub(ktime_get(), start)),
6649 hba->uic_link_state, hba->curr_dev_pwr_mode);
e785060e
DR		 6650 if (!ret)
6651 hba->is_sys_suspended = true;
57d104c1
SJ		 6652 return ret;
6653}
6654EXPORT_SYMBOL(ufshcd_system_suspend);
6655
6656/**
6657 * ufshcd_system_resume - system resume routine
6658 * @hba: per adapter instance
6659 *
6660 * Returns 0 for success and non-zero for failure
6661 */
7a3e97b0 6662
57d104c1
SJ		 6663int ufshcd_system_resume(struct ufs_hba *hba)
6664{
7ff5ab47 6665 int ret = 0;
6666 ktime_t start = ktime_get();
6667
e3ce73d6
YG		 6668 if (!hba)
6669 return -EINVAL;
6670
6671 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 6672 /*
6673 * Let the runtime resume take care of resuming
6674 * if runtime suspended.
6675 */
7ff5ab47 6676 goto out;
6677 else
6678 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
6679out:
6680 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
6681 ktime_to_us(ktime_sub(ktime_get(), start)),
6682 hba->uic_link_state, hba->curr_dev_pwr_mode);
6683 return ret;
7a3e97b0 6684}
57d104c1 6685EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6686
57d104c1
SJ		 6687/**
6688 * ufshcd_runtime_suspend - runtime suspend routine
6689 * @hba: per adapter instance
6690 *
6691 * Check the description of ufshcd_suspend() function for more details.
6692 *
6693 * Returns 0 for success and non-zero for failure
6694 */
66ec6d59
SRT		 6695int ufshcd_runtime_suspend(struct ufs_hba *hba)
6696{
7ff5ab47 6697 int ret = 0;
6698 ktime_t start = ktime_get();
6699
e3ce73d6
YG		 6700 if (!hba)
6701 return -EINVAL;
6702
6703 if (!hba->is_powered)
7ff5ab47 6704 goto out;
6705 else
6706 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
6707out:
6708 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
6709 ktime_to_us(ktime_sub(ktime_get(), start)),
6710 hba->uic_link_state, hba->curr_dev_pwr_mode);
6711 return ret;
66ec6d59
SRT		 6712}
6713EXPORT_SYMBOL(ufshcd_runtime_suspend);
6714
57d104c1
SJ		 6715/**
6716 * ufshcd_runtime_resume - runtime resume routine
6717 * @hba: per adapter instance
6718 *
6719 * This function basically brings the UFS device, UniPro link and controller
6720 * to active state. Following operations are done in this function:
6721 *
6722 * 1. Turn on all the controller related clocks
6723 * 2. Bring the UniPro link out of Hibernate state
6724 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6725 * to active state.
6726 * 4. If auto-bkops is enabled on the device, disable it.
6727 *
6728 * So following would be the possible power state after this function return
6729 * successfully:
6730 * S1: UFS device in Active state with VCC rail ON
6731 * UniPro link in Active state
6732 * All the UFS/UniPro controller clocks are ON
6733 *
6734 * Returns 0 for success and non-zero for failure
6735 */
66ec6d59
SRT		 6736int ufshcd_runtime_resume(struct ufs_hba *hba)
6737{
7ff5ab47 6738 int ret = 0;
6739 ktime_t start = ktime_get();
6740
e3ce73d6
YG		 6741 if (!hba)
6742 return -EINVAL;
6743
6744 if (!hba->is_powered)
7ff5ab47 6745 goto out;
6746 else
6747 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
6748out:
6749 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
6750 ktime_to_us(ktime_sub(ktime_get(), start)),
6751 hba->uic_link_state, hba->curr_dev_pwr_mode);
6752 return ret;
66ec6d59
SRT		 6753}
6754EXPORT_SYMBOL(ufshcd_runtime_resume);
6755
6756int ufshcd_runtime_idle(struct ufs_hba *hba)
6757{
6758 return 0;
6759}
6760EXPORT_SYMBOL(ufshcd_runtime_idle);
6761
09690d5a 6762static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
6763 struct device_attribute *attr,
6764 const char *buf, size_t count,
6765 bool rpm)
6766{
6767 struct ufs_hba *hba = dev_get_drvdata(dev);
6768 unsigned long flags, value;
6769
6770 if (kstrtoul(buf, 0, &value))
6771 return -EINVAL;
6772
6773 if ((value < UFS_PM_LVL_0) || (value >= UFS_PM_LVL_MAX))
6774 return -EINVAL;
6775
6776 spin_lock_irqsave(hba->host->host_lock, flags);
6777 if (rpm)
6778 hba->rpm_lvl = value;
6779 else
6780 hba->spm_lvl = value;
6781 spin_unlock_irqrestore(hba->host->host_lock, flags);
6782 return count;
6783}
6784
6785static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
6786 struct device_attribute *attr, char *buf)
6787{
6788 struct ufs_hba *hba = dev_get_drvdata(dev);
6789 int curr_len;
6790 u8 lvl;
6791
6792 curr_len = snprintf(buf, PAGE_SIZE,
6793 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
6794 hba->rpm_lvl,
6795 ufschd_ufs_dev_pwr_mode_to_string(
6796 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
6797 ufschd_uic_link_state_to_string(
6798 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
6799
6800 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
6801 "\nAll available Runtime PM levels info:\n");
6802 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
6803 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
6804 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
6805 lvl,
6806 ufschd_ufs_dev_pwr_mode_to_string(
6807 ufs_pm_lvl_states[lvl].dev_state),
6808 ufschd_uic_link_state_to_string(
6809 ufs_pm_lvl_states[lvl].link_state));
6810
6811 return curr_len;
6812}
6813
6814static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
6815 struct device_attribute *attr, const char *buf, size_t count)
6816{
6817 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
6818}
6819
6820static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
6821{
6822 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
6823 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
6824 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
6825 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
6826 hba->rpm_lvl_attr.attr.mode = 0644;
6827 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
6828 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
6829}
6830
6831static ssize_t ufshcd_spm_lvl_show(struct device *dev,
6832 struct device_attribute *attr, char *buf)
6833{
6834 struct ufs_hba *hba = dev_get_drvdata(dev);
6835 int curr_len;
6836 u8 lvl;
6837
6838 curr_len = snprintf(buf, PAGE_SIZE,
6839 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
6840 hba->spm_lvl,
6841 ufschd_ufs_dev_pwr_mode_to_string(
6842 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
6843 ufschd_uic_link_state_to_string(
6844 ufs_pm_lvl_states[hba->spm_lvl].link_state));
6845
6846 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
6847 "\nAll available System PM levels info:\n");
6848 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
6849 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
6850 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
6851 lvl,
6852 ufschd_ufs_dev_pwr_mode_to_string(
6853 ufs_pm_lvl_states[lvl].dev_state),
6854 ufschd_uic_link_state_to_string(
6855 ufs_pm_lvl_states[lvl].link_state));
6856
6857 return curr_len;
6858}
6859
6860static ssize_t ufshcd_spm_lvl_store(struct device *dev,
6861 struct device_attribute *attr, const char *buf, size_t count)
6862{
6863 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
6864}
6865
6866static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
6867{
6868 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
6869 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
6870 sysfs_attr_init(&hba->spm_lvl_attr.attr);
6871 hba->spm_lvl_attr.attr.name = "spm_lvl";
6872 hba->spm_lvl_attr.attr.mode = 0644;
6873 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
6874 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
6875}
6876
6877static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
6878{
6879 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
6880 ufshcd_add_spm_lvl_sysfs_nodes(hba);
6881}
6882
57d104c1
SJ		 6883/**
6884 * ufshcd_shutdown - shutdown routine
6885 * @hba: per adapter instance
6886 *
6887 * This function would power off both UFS device and UFS link.
6888 *
6889 * Returns 0 always to allow force shutdown even in case of errors.
6890 */
6891int ufshcd_shutdown(struct ufs_hba *hba)
6892{
6893 int ret = 0;
6894
6895 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6896 goto out;
6897
6898 if (pm_runtime_suspended(hba->dev)) {
6899 ret = ufshcd_runtime_resume(hba);
6900 if (ret)
6901 goto out;
6902 }
6903
6904 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6905out:
6906 if (ret)
6907 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6908 /* allow force shutdown even in case of errors */
6909 return 0;
6910}
6911EXPORT_SYMBOL(ufshcd_shutdown);
6912
7a3e97b0 6913/**
3b1d0580 6914 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6915 * data structure memory
3b1d0580 6916 * @hba - per adapter instance
7a3e97b0 6917 */
3b1d0580 6918void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6919{
cfdf9c91 6920 scsi_remove_host(hba->host);
7a3e97b0 6921 /* disable interrupts */
2fbd009b 6922 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6923 ufshcd_hba_stop(hba, true);
7a3e97b0 6924
1ab27c9c 6925 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 6926 if (ufshcd_is_clkscaling_supported(hba))
6927 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 6928 ufshcd_hba_exit(hba);
3b1d0580
VH		 6929}
6930EXPORT_SYMBOL_GPL(ufshcd_remove);
6931
47555a5c
YG		 6932/**
6933 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6934 * @hba: pointer to Host Bus Adapter (HBA)
6935 */
6936void ufshcd_dealloc_host(struct ufs_hba *hba)
6937{
6938 scsi_host_put(hba->host);
6939}
6940EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6941
ca3d7bf9
AM		 6942/**
6943 * ufshcd_set_dma_mask - Set dma mask based on the controller
6944 * addressing capability
6945 * @hba: per adapter instance
6946 *
6947 * Returns 0 for success, non-zero for failure
6948 */
6949static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6950{
6951 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6952 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6953 return 0;
6954 }
6955 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6956}
6957
7a3e97b0 6958/**
5c0c28a8 6959 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 6960 * @dev: pointer to device handle
6961 * @hba_handle: driver private handle
7a3e97b0
SY		 6962 * Returns 0 on success, non-zero value on failure
6963 */
5c0c28a8 6964int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 6965{
6966 struct Scsi_Host *host;
6967 struct ufs_hba *hba;
5c0c28a8 6968 int err = 0;
7a3e97b0 6969
3b1d0580
VH		 6970 if (!dev) {
6971 dev_err(dev,
6972 "Invalid memory reference for dev is NULL\n");
6973 err = -ENODEV;
7a3e97b0
SY		 6974 goto out_error;
6975 }
6976
7a3e97b0
SY		 6977 host = scsi_host_alloc(&ufshcd_driver_template,
6978 sizeof(struct ufs_hba));
6979 if (!host) {
3b1d0580 6980 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6981 err = -ENOMEM;
3b1d0580 6982 goto out_error;
7a3e97b0
SY		 6983 }
6984 hba = shost_priv(host);
7a3e97b0 6985 hba->host = host;
3b1d0580 6986 hba->dev = dev;
5c0c28a8
SRT		 6987 *hba_handle = hba;
6988
6989out_error:
6990 return err;
6991}
6992EXPORT_SYMBOL(ufshcd_alloc_host);
6993
856b3483
ST		 6994static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6995{
6996 int ret = 0;
6997 struct ufs_clk_info *clki;
6998 struct list_head *head = &hba->clk_list_head;
6999
7000 if (!head || list_empty(head))
7001 goto out;
7002
f06fcc71
YG		 7003 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
7004 if (ret)
7005 return ret;
7006
856b3483
ST		 7007 list_for_each_entry(clki, head, list) {
7008 if (!IS_ERR_OR_NULL(clki->clk)) {
7009 if (scale_up && clki->max_freq) {
7010 if (clki->curr_freq == clki->max_freq)
7011 continue;
7012 ret = clk_set_rate(clki->clk, clki->max_freq);
7013 if (ret) {
7014 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7015 __func__, clki->name,
7016 clki->max_freq, ret);
7017 break;
7018 }
7ff5ab47 7019 trace_ufshcd_clk_scaling(dev_name(hba->dev),
7020 "scaled up", clki->name,
7021 clki->curr_freq,
7022 clki->max_freq);
7023
856b3483
ST		 7024 clki->curr_freq = clki->max_freq;
7025
7026 } else if (!scale_up && clki->min_freq) {
7027 if (clki->curr_freq == clki->min_freq)
7028 continue;
7029 ret = clk_set_rate(clki->clk, clki->min_freq);
7030 if (ret) {
7031 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7032 __func__, clki->name,
7033 clki->min_freq, ret);
7034 break;
7035 }
7ff5ab47 7036 trace_ufshcd_clk_scaling(dev_name(hba->dev),
7037 "scaled down", clki->name,
7038 clki->curr_freq,
7039 clki->min_freq);
856b3483
ST		 7040 clki->curr_freq = clki->min_freq;
7041 }
7042 }
7043 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
7044 clki->name, clk_get_rate(clki->clk));
7045 }
f06fcc71
YG		 7046
7047 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
7048
856b3483
ST		 7049out:
7050 return ret;
7051}
7052
7053static int ufshcd_devfreq_target(struct device *dev,
7054 unsigned long *freq, u32 flags)
7055{
7056 int err = 0;
7057 struct ufs_hba *hba = dev_get_drvdata(dev);
30fc33f1
SJ		 7058 bool release_clk_hold = false;
7059 unsigned long irq_flags;
856b3483 7060
fcb0c4b0 7061 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 7062 return -EINVAL;
7063
30fc33f1
SJ		 7064 spin_lock_irqsave(hba->host->host_lock, irq_flags);
7065 if (ufshcd_eh_in_progress(hba)) {
7066 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
7067 return 0;
7068 }
7069
7070 if (ufshcd_is_clkgating_allowed(hba) &&
7071 (hba->clk_gating.state != CLKS_ON)) {
7072 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
7073 /* hold the vote until the scaling work is completed */
7074 hba->clk_gating.active_reqs++;
7075 release_clk_hold = true;
7076 hba->clk_gating.state = CLKS_ON;
7077 } else {
7078 /*
7079 * Clock gating work seems to be running in parallel
7080 * hence skip scaling work to avoid deadlock between
7081 * current scaling work and gating work.
7082 */
7083 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
7084 return 0;
7085 }
7086 }
7087 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
7088
856b3483
ST		 7089 if (*freq == UINT_MAX)
7090 err = ufshcd_scale_clks(hba, true);
7091 else if (*freq == 0)
7092 err = ufshcd_scale_clks(hba, false);
7093
30fc33f1
SJ		 7094 spin_lock_irqsave(hba->host->host_lock, irq_flags);
7095 if (release_clk_hold)
7096 __ufshcd_release(hba);
7097 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
7098
856b3483
ST		 7099 return err;
7100}
7101
7102static int ufshcd_devfreq_get_dev_status(struct device *dev,
7103 struct devfreq_dev_status *stat)
7104{
7105 struct ufs_hba *hba = dev_get_drvdata(dev);
7106 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
7107 unsigned long flags;
7108
fcb0c4b0 7109 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 7110 return -EINVAL;
7111
7112 memset(stat, 0, sizeof(*stat));
7113
7114 spin_lock_irqsave(hba->host->host_lock, flags);
7115 if (!scaling->window_start_t)
7116 goto start_window;
7117
7118 if (scaling->is_busy_started)
7119 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
7120 scaling->busy_start_t));
7121
7122 stat->total_time = jiffies_to_usecs((long)jiffies -
7123 (long)scaling->window_start_t);
7124 stat->busy_time = scaling->tot_busy_t;
7125start_window:
7126 scaling->window_start_t = jiffies;
7127 scaling->tot_busy_t = 0;
7128
7129 if (hba->outstanding_reqs) {
7130 scaling->busy_start_t = ktime_get();
7131 scaling->is_busy_started = true;
7132 } else {
8b0e1953 7133 scaling->busy_start_t = 0;
856b3483
ST		 7134 scaling->is_busy_started = false;
7135 }
7136 spin_unlock_irqrestore(hba->host->host_lock, flags);
7137 return 0;
7138}
7139
7140static struct devfreq_dev_profile ufs_devfreq_profile = {
7141 .polling_ms = 100,
7142 .target = ufshcd_devfreq_target,
7143 .get_dev_status = ufshcd_devfreq_get_dev_status,
7144};
fcb0c4b0
ST		 7145static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
7146{
7147 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
7148 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
7149 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
7150 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
7151 hba->clk_scaling.enable_attr.attr.mode = 0644;
7152 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
7153 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
7154}
856b3483 7155
5c0c28a8
SRT		 7156/**
7157 * ufshcd_init - Driver initialization routine
7158 * @hba: per-adapter instance
7159 * @mmio_base: base register address
7160 * @irq: Interrupt line of device
7161 * Returns 0 on success, non-zero value on failure
7162 */
7163int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7164{
7165 int err;
7166 struct Scsi_Host *host = hba->host;
7167 struct device *dev = hba->dev;
7168
7169 if (!mmio_base) {
7170 dev_err(hba->dev,
7171 "Invalid memory reference for mmio_base is NULL\n");
7172 err = -ENODEV;
7173 goto out_error;
7174 }
7175
3b1d0580
VH		 7176 hba->mmio_base = mmio_base;
7177 hba->irq = irq;
7a3e97b0 7178
aa497613 7179 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7180 if (err)
7181 goto out_error;
7182
7a3e97b0
SY		 7183 /* Read capabilities registers */
7184 ufshcd_hba_capabilities(hba);
7185
7186 /* Get UFS version supported by the controller */
7187 hba->ufs_version = ufshcd_get_ufs_version(hba);
7188
c01848c6
YG		 7189 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7190 (hba->ufs_version != UFSHCI_VERSION_11) &&
7191 (hba->ufs_version != UFSHCI_VERSION_20) &&
7192 (hba->ufs_version != UFSHCI_VERSION_21))
7193 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7194 hba->ufs_version);
7195
2fbd009b
SJ		 7196 /* Get Interrupt bit mask per version */
7197 hba->intr_mask = ufshcd_get_intr_mask(hba);
7198
ca3d7bf9
AM		 7199 err = ufshcd_set_dma_mask(hba);
7200 if (err) {
7201 dev_err(hba->dev, "set dma mask failed\n");
7202 goto out_disable;
7203 }
7204
7a3e97b0
SY		 7205 /* Allocate memory for host memory space */
7206 err = ufshcd_memory_alloc(hba);
7207 if (err) {
3b1d0580
VH		 7208 dev_err(hba->dev, "Memory allocation failed\n");
7209 goto out_disable;
7a3e97b0
SY		 7210 }
7211
7212 /* Configure LRB */
7213 ufshcd_host_memory_configure(hba);
7214
7215 host->can_queue = hba->nutrs;
7216 host->cmd_per_lun = hba->nutrs;
7217 host->max_id = UFSHCD_MAX_ID;
0ce147d4 7218 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 7219 host->max_channel = UFSHCD_MAX_CHANNEL;
7220 host->unique_id = host->host_no;
7221 host->max_cmd_len = MAX_CDB_SIZE;
7222
7eb584db
DR		 7223 hba->max_pwr_info.is_valid = false;
7224
7a3e97b0 7225 /* Initailize wait queue for task management */
e2933132
SRT		 7226 init_waitqueue_head(&hba->tm_wq);
7227 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 7228
7229 /* Initialize work queues */
e8e7f271 7230 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 7231 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 7232
6ccf44fe
SJ		 7233 /* Initialize UIC command mutex */
7234 mutex_init(&hba->uic_cmd_mutex);
7235
5a0b0cb9
SRT		 7236 /* Initialize mutex for device management commands */
7237 mutex_init(&hba->dev_cmd.lock);
7238
7239 /* Initialize device management tag acquire wait queue */
7240 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7241
1ab27c9c 7242 ufshcd_init_clk_gating(hba);
199ef13c
YG		 7243
7244 /*
7245 * In order to avoid any spurious interrupt immediately after
7246 * registering UFS controller interrupt handler, clear any pending UFS
7247 * interrupt status and disable all the UFS interrupts.
7248 */
7249 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7250 REG_INTERRUPT_STATUS);
7251 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7252 /*
7253 * Make sure that UFS interrupts are disabled and any pending interrupt
7254 * status is cleared before registering UFS interrupt handler.
7255 */
7256 mb();
7257
7a3e97b0 7258 /* IRQ registration */
2953f850 7259 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 7260 if (err) {
3b1d0580 7261 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 7262 goto exit_gating;
57d104c1
SJ		 7263 } else {
7264 hba->is_irq_enabled = true;
7a3e97b0
SY		 7265 }
7266
3b1d0580 7267 err = scsi_add_host(host, hba->dev);
7a3e97b0 7268 if (err) {
3b1d0580 7269 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 7270 goto exit_gating;
7a3e97b0
SY		 7271 }
7272
6ccf44fe
SJ		 7273 /* Host controller enable */
7274 err = ufshcd_hba_enable(hba);
7a3e97b0 7275 if (err) {
6ccf44fe 7276 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 7277 ufshcd_print_host_regs(hba);
3b1d0580 7278 goto out_remove_scsi_host;
7a3e97b0 7279 }
6ccf44fe 7280
fcb0c4b0 7281 if (ufshcd_is_clkscaling_supported(hba)) {
4861ee15 7282 hba->devfreq = devm_devfreq_add_device(dev, &ufs_devfreq_profile,
856b3483
ST		 7283 "simple_ondemand", NULL);
7284 if (IS_ERR(hba->devfreq)) {
7285 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
7286 PTR_ERR(hba->devfreq));
73811c94 7287 err = PTR_ERR(hba->devfreq);
856b3483
ST		 7288 goto out_remove_scsi_host;
7289 }
7290 /* Suspend devfreq until the UFS device is detected */
a508253d 7291 ufshcd_suspend_clkscaling(hba);
fcb0c4b0 7292 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 7293 }
7294
0c8f7586 7295 /*
7296 * Set the default power management level for runtime and system PM.
7297 * Default power saving mode is to keep UFS link in Hibern8 state
7298 * and UFS device in sleep state.
7299 */
7300 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7301 UFS_SLEEP_PWR_MODE,
7302 UIC_LINK_HIBERN8_STATE);
7303 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7304 UFS_SLEEP_PWR_MODE,
7305 UIC_LINK_HIBERN8_STATE);
7306
62694735
SRT		 7307 /* Hold auto suspend until async scan completes */
7308 pm_runtime_get_sync(dev);
7309
57d104c1 7310 /*
7caf489b 7311 * We are assuming that device wasn't put in sleep/power-down
7312 * state exclusively during the boot stage before kernel.
7313 * This assumption helps avoid doing link startup twice during
7314 * ufshcd_probe_hba().
57d104c1 7315 */
7caf489b 7316 ufshcd_set_ufs_dev_active(hba);
57d104c1 7317
6ccf44fe 7318 async_schedule(ufshcd_async_scan, hba);
09690d5a 7319 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 7320
7a3e97b0
SY		 7321 return 0;
7322
3b1d0580
VH		 7323out_remove_scsi_host:
7324 scsi_remove_host(hba->host);
1ab27c9c
ST		 7325exit_gating:
7326 ufshcd_exit_clk_gating(hba);
3b1d0580 7327out_disable:
57d104c1 7328 hba->is_irq_enabled = false;
aa497613 7329 ufshcd_hba_exit(hba);
3b1d0580
VH		 7330out_error:
7331 return err;
7332}
7333EXPORT_SYMBOL_GPL(ufshcd_init);
7334
3b1d0580
VH		 7335MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
7336MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 7337MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 7338MODULE_LICENSE("GPL");
7339MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)