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scsi: uapi: ufs: Make utp_upiu_req visible to user space
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
e0eca63e 45#include "ufshcd.h"
c58ab7aa 46#include "ufs_quirks.h"
53b3d9c3 47#include "unipro.h"
cbb6813e 48#include "ufs-sysfs.h"
7a3e97b0 49
7ff5ab47 50#define CREATE_TRACE_POINTS
51#include <trace/events/ufs.h>
52
dcea0bfb
GB		 53#define UFSHCD_REQ_SENSE_SIZE 18
54
2fbd009b
SJ		 55#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
56 UTP_TASK_REQ_COMPL |\
57 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 58/* UIC command timeout, unit: ms */
59#define UIC_CMD_TIMEOUT 500
2fbd009b 60
5a0b0cb9
SRT		 61/* NOP OUT retries waiting for NOP IN response */
62#define NOP_OUT_RETRIES 10
63/* Timeout after 30 msecs if NOP OUT hangs without response */
64#define NOP_OUT_TIMEOUT 30 /* msecs */
65
68078d5c 66/* Query request retries */
10fe5888 67#define QUERY_REQ_RETRIES 3
68078d5c 68/* Query request timeout */
10fe5888 69#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 70
e2933132
SRT		 71/* Task management command timeout */
72#define TM_CMD_TIMEOUT 100 /* msecs */
73
64238fbd
YG		 74/* maximum number of retries for a general UIC command */
75#define UFS_UIC_COMMAND_RETRIES 3
76
1d337ec2
SRT		 77/* maximum number of link-startup retries */
78#define DME_LINKSTARTUP_RETRIES 3
79
87d0b4a6
YG		 80/* Maximum retries for Hibern8 enter */
81#define UIC_HIBERN8_ENTER_RETRIES 3
82
1d337ec2
SRT		 83/* maximum number of reset retries before giving up */
84#define MAX_HOST_RESET_RETRIES 5
85
68078d5c
DR		 86/* Expose the flag value from utp_upiu_query.value */
87#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
88
7d568652
SJ		 89/* Interrupt aggregation default timeout, unit: 40us */
90#define INT_AGGR_DEF_TO 0x02
91
aa497613
SRT		 92#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
93 ({ \
94 int _ret; \
95 if (_on) \
96 _ret = ufshcd_enable_vreg(_dev, _vreg); \
97 else \
98 _ret = ufshcd_disable_vreg(_dev, _vreg); \
99 _ret; \
100 })
101
ba80917d
TW		 102#define ufshcd_hex_dump(prefix_str, buf, len) do { \
103 size_t __len = (len); \
104 print_hex_dump(KERN_ERR, prefix_str, \
105 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
106 16, 4, buf, __len, false); \
107} while (0)
108
109int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
110 const char *prefix)
111{
112 u8 *regs;
113
114 regs = kzalloc(len, GFP_KERNEL);
115 if (!regs)
116 return -ENOMEM;
117
118 memcpy_fromio(regs, hba->mmio_base + offset, len);
119 ufshcd_hex_dump(prefix, regs, len);
120 kfree(regs);
121
122 return 0;
123}
124EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 125
7a3e97b0
SY		 126enum {
127 UFSHCD_MAX_CHANNEL = 0,
128 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 129 UFSHCD_CMD_PER_LUN = 32,
130 UFSHCD_CAN_QUEUE = 32,
131};
132
133/* UFSHCD states */
134enum {
7a3e97b0
SY		 135 UFSHCD_STATE_RESET,
136 UFSHCD_STATE_ERROR,
3441da7d 137 UFSHCD_STATE_OPERATIONAL,
141f8165 138 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 139};
140
141/* UFSHCD error handling flags */
142enum {
143 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 144};
145
e8e7f271
SRT		 146/* UFSHCD UIC layer error flags */
147enum {
148 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 149 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
150 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
151 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
152 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
153 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 154};
155
3441da7d 156#define ufshcd_set_eh_in_progress(h) \
9c490d2d 157 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 158#define ufshcd_eh_in_progress(h) \
9c490d2d 159 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 160#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 161 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 162
57d104c1
SJ		 163#define ufshcd_set_ufs_dev_active(h) \
164 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
165#define ufshcd_set_ufs_dev_sleep(h) \
166 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
167#define ufshcd_set_ufs_dev_poweroff(h) \
168 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
169#define ufshcd_is_ufs_dev_active(h) \
170 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
171#define ufshcd_is_ufs_dev_sleep(h) \
172 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
173#define ufshcd_is_ufs_dev_poweroff(h) \
174 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
175
cbb6813e 176struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 177 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
178 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
180 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
181 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
182 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
183};
184
185static inline enum ufs_dev_pwr_mode
186ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
187{
188 return ufs_pm_lvl_states[lvl].dev_state;
189}
190
191static inline enum uic_link_state
192ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
193{
194 return ufs_pm_lvl_states[lvl].link_state;
195}
196
0c8f7586 197static inline enum ufs_pm_level
198ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
199 enum uic_link_state link_state)
200{
201 enum ufs_pm_level lvl;
202
203 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
204 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
205 (ufs_pm_lvl_states[lvl].link_state == link_state))
206 return lvl;
207 }
208
209 /* if no match found, return the level 0 */
210 return UFS_PM_LVL_0;
211}
212
56d4a186
SJ		 213static struct ufs_dev_fix ufs_fixups[] = {
214 /* UFS cards deviations table */
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
218 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
219 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
220 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
221 UFS_DEVICE_NO_FASTAUTO),
222 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
223 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
224 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
225 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
226 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
227 UFS_DEVICE_QUIRK_PA_TACTIVATE),
228 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
229 UFS_DEVICE_QUIRK_PA_TACTIVATE),
230 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
231 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
232 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
233
234 END_FIX
235};
236
3441da7d
SRT		 237static void ufshcd_tmc_handler(struct ufs_hba *hba);
238static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 239static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 240static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 241static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 242static void ufshcd_hba_exit(struct ufs_hba *hba);
243static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 244static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
245 bool skip_ref_clk);
246static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 247static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 248static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
249static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 250static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 251static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 252static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
253static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 254static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 255static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 256static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 257static int ufshcd_change_power_mode(struct ufs_hba *hba,
258 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 259static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
260{
261 return tag >= 0 && tag < hba->nutrs;
262}
57d104c1
SJ		 263
264static inline int ufshcd_enable_irq(struct ufs_hba *hba)
265{
266 int ret = 0;
267
268 if (!hba->is_irq_enabled) {
269 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
270 hba);
271 if (ret)
272 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
273 __func__, ret);
274 hba->is_irq_enabled = true;
275 }
276
277 return ret;
278}
279
280static inline void ufshcd_disable_irq(struct ufs_hba *hba)
281{
282 if (hba->is_irq_enabled) {
283 free_irq(hba->irq, hba);
284 hba->is_irq_enabled = false;
285 }
286}
3441da7d 287
38135535
SJ		 288static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
289{
290 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
291 scsi_unblock_requests(hba->host);
292}
293
294static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
295{
296 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
297 scsi_block_requests(hba->host);
298}
299
b573d484
YG		 300/* replace non-printable or non-ASCII characters with spaces */
301static inline void ufshcd_remove_non_printable(char *val)
302{
303 if (!val)
304 return;
305
306 if (*val < 0x20 || *val > 0x7e)
307 *val = ' ';
308}
309
6667e6d9
OS		 310static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
311 const char *str)
312{
313 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
314
315 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
316}
317
318static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
319 const char *str)
320{
321 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
322
323 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
324}
325
326static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
327 const char *str)
328{
6667e6d9 329 int off = (int)tag - hba->nutrs;
391e388f 330 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 331
391e388f
CH		 332 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
333 &descp->input_param1);
6667e6d9
OS		 334}
335
1a07f2d9
LS		 336static void ufshcd_add_command_trace(struct ufs_hba *hba,
337 unsigned int tag, const char *str)
338{
339 sector_t lba = -1;
340 u8 opcode = 0;
341 u32 intr, doorbell;
e7c3b379 342 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
1a07f2d9
LS		 343 int transfer_len = -1;
344
e7c3b379
OS		 345 if (!trace_ufshcd_command_enabled()) {
346 /* trace UPIU W/O tracing command */
347 if (lrbp->cmd)
348 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 349 return;
e7c3b379 350 }
1a07f2d9
LS		 351
352 if (lrbp->cmd) { /* data phase exists */
e7c3b379
OS		 353 /* trace UPIU also */
354 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9
LS		 355 opcode = (u8)(*lrbp->cmd->cmnd);
356 if ((opcode == READ_10) || (opcode == WRITE_10)) {
357 /*
358 * Currently we only fully trace read(10) and write(10)
359 * commands
360 */
361 if (lrbp->cmd->request && lrbp->cmd->request->bio)
362 lba =
363 lrbp->cmd->request->bio->bi_iter.bi_sector;
364 transfer_len = be32_to_cpu(
365 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
366 }
367 }
368
369 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
370 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
371 trace_ufshcd_command(dev_name(hba->dev), str, tag,
372 doorbell, transfer_len, intr, lba, opcode);
373}
374
ff8e20c6
DR		 375static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
376{
377 struct ufs_clk_info *clki;
378 struct list_head *head = &hba->clk_list_head;
379
566ec9ad 380 if (list_empty(head))
ff8e20c6
DR		 381 return;
382
383 list_for_each_entry(clki, head, list) {
384 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
385 clki->max_freq)
386 dev_err(hba->dev, "clk: %s, rate: %u\n",
387 clki->name, clki->curr_freq);
388 }
389}
390
391static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
392 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
393{
394 int i;
395
396 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
397 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
398
399 if (err_hist->reg[p] == 0)
400 continue;
401 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
402 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
403 }
404}
405
66cc820f
DR		 406static void ufshcd_print_host_regs(struct ufs_hba *hba)
407{
ba80917d 408 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 409 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
410 hba->ufs_version, hba->capabilities);
411 dev_err(hba->dev,
412 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
413 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 414 dev_err(hba->dev,
415 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
416 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
417 hba->ufs_stats.hibern8_exit_cnt);
418
419 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
420 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
421 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
422 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
423 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
424
425 ufshcd_print_clk_freqs(hba);
426
427 if (hba->vops && hba->vops->dbg_register_dump)
428 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 429}
430
431static
432void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
433{
434 struct ufshcd_lrb *lrbp;
7fabb77b 435 int prdt_length;
66cc820f
DR		 436 int tag;
437
438 for_each_set_bit(tag, &bitmap, hba->nutrs) {
439 lrbp = &hba->lrb[tag];
440
ff8e20c6
DR		 441 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
442 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 443 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
444 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 445 dev_err(hba->dev,
446 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
447 tag, (u64)lrbp->utrd_dma_addr);
448
66cc820f
DR		 449 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
450 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 451 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
452 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 453 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
454 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 455 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
456 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 457 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
458 sizeof(struct utp_upiu_rsp));
66cc820f 459
7fabb77b
GB		 460 prdt_length = le16_to_cpu(
461 lrbp->utr_descriptor_ptr->prd_table_length);
462 dev_err(hba->dev,
463 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
464 tag, prdt_length,
465 (u64)lrbp->ucd_prdt_dma_addr);
466
467 if (pr_prdt)
66cc820f 468 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 469 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 470 }
471}
472
473static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
474{
66cc820f
DR		 475 int tag;
476
477 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 478 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
479
66cc820f 480 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 481 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 482 }
483}
484
6ba65588
GB		 485static void ufshcd_print_host_state(struct ufs_hba *hba)
486{
487 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
488 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 489 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 490 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
491 hba->saved_err, hba->saved_uic_err);
492 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
493 hba->curr_dev_pwr_mode, hba->uic_link_state);
494 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
495 hba->pm_op_in_progress, hba->is_sys_suspended);
496 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
497 hba->auto_bkops_enabled, hba->host->host_self_blocked);
498 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
499 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
500 hba->eh_flags, hba->req_abort_count);
501 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
502 hba->capabilities, hba->caps);
503 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
504 hba->dev_quirks);
505}
506
ff8e20c6
DR		 507/**
508 * ufshcd_print_pwr_info - print power params as saved in hba
509 * power info
510 * @hba: per-adapter instance
511 */
512static void ufshcd_print_pwr_info(struct ufs_hba *hba)
513{
514 static const char * const names[] = {
515 "INVALID MODE",
516 "FAST MODE",
517 "SLOW_MODE",
518 "INVALID MODE",
519 "FASTAUTO_MODE",
520 "SLOWAUTO_MODE",
521 "INVALID MODE",
522 };
523
524 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
525 __func__,
526 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
527 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
528 names[hba->pwr_info.pwr_rx],
529 names[hba->pwr_info.pwr_tx],
530 hba->pwr_info.hs_rate);
531}
532
5a0b0cb9
SRT		 533/*
534 * ufshcd_wait_for_register - wait for register value to change
535 * @hba - per-adapter interface
536 * @reg - mmio register offset
537 * @mask - mask to apply to read register value
538 * @val - wait condition
539 * @interval_us - polling interval in microsecs
540 * @timeout_ms - timeout in millisecs
596585a2 541 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 542 *
543 * Returns -ETIMEDOUT on error, zero on success
544 */
596585a2
YG		 545int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
546 u32 val, unsigned long interval_us,
547 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 548{
549 int err = 0;
550 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
551
552 /* ignore bits that we don't intend to wait on */
553 val = val & mask;
554
555 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 556 if (can_sleep)
557 usleep_range(interval_us, interval_us + 50);
558 else
559 udelay(interval_us);
5a0b0cb9
SRT		 560 if (time_after(jiffies, timeout)) {
561 if ((ufshcd_readl(hba, reg) & mask) != val)
562 err = -ETIMEDOUT;
563 break;
564 }
565 }
566
567 return err;
568}
569
2fbd009b
SJ		 570/**
571 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 572 * @hba: Pointer to adapter instance
2fbd009b
SJ		 573 *
574 * Returns interrupt bit mask per version
575 */
576static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
577{
c01848c6
YG		 578 u32 intr_mask = 0;
579
580 switch (hba->ufs_version) {
581 case UFSHCI_VERSION_10:
582 intr_mask = INTERRUPT_MASK_ALL_VER_10;
583 break;
c01848c6
YG		 584 case UFSHCI_VERSION_11:
585 case UFSHCI_VERSION_20:
586 intr_mask = INTERRUPT_MASK_ALL_VER_11;
587 break;
c01848c6
YG		 588 case UFSHCI_VERSION_21:
589 default:
590 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 591 break;
c01848c6
YG		 592 }
593
594 return intr_mask;
2fbd009b
SJ		 595}
596
7a3e97b0
SY		 597/**
598 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 599 * @hba: Pointer to adapter instance
7a3e97b0
SY		 600 *
601 * Returns UFSHCI version supported by the controller
602 */
603static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
604{
0263bcd0
YG		 605 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
606 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 607
b873a275 608 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 609}
610
611/**
612 * ufshcd_is_device_present - Check if any device connected to
613 * the host controller
5c0c28a8 614 * @hba: pointer to adapter instance
7a3e97b0 615 *
c9e6010b 616 * Returns true if device present, false if no device detected
7a3e97b0 617 */
c9e6010b 618static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 619{
5c0c28a8 620 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 621 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 622}
623
624/**
625 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 626 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 627 *
628 * This function is used to get the OCS field from UTRD
629 * Returns the OCS field in the UTRD
630 */
631static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
632{
e8c8e82a 633 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 634}
635
7a3e97b0
SY		 636/**
637 * ufshcd_get_tm_free_slot - get a free slot for task management request
638 * @hba: per adapter instance
e2933132 639 * @free_slot: pointer to variable with available slot value
7a3e97b0 640 *
e2933132
SRT		 641 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
642 * Returns 0 if free slot is not available, else return 1 with tag value
643 * in @free_slot.
7a3e97b0 644 */
e2933132 645static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 646{
e2933132
SRT		 647 int tag;
648 bool ret = false;
649
650 if (!free_slot)
651 goto out;
652
653 do {
654 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
655 if (tag >= hba->nutmrs)
656 goto out;
657 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
658
659 *free_slot = tag;
660 ret = true;
661out:
662 return ret;
663}
664
665static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
666{
667 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 668}
669
670/**
671 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
672 * @hba: per adapter instance
673 * @pos: position of the bit to be cleared
674 */
675static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
676{
1399c5b0
AA		 677 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
678 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
679 else
680 ufshcd_writel(hba, ~(1 << pos),
681 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
682}
683
684/**
685 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
686 * @hba: per adapter instance
687 * @pos: position of the bit to be cleared
688 */
689static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
690{
691 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
692 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
693 else
694 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 695}
696
a48353f6
YG		 697/**
698 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
699 * @hba: per adapter instance
700 * @tag: position of the bit to be cleared
701 */
702static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
703{
704 __clear_bit(tag, &hba->outstanding_reqs);
705}
706
7a3e97b0
SY		 707/**
708 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
709 * @reg: Register value of host controller status
710 *
711 * Returns integer, 0 on Success and positive value if failed
712 */
713static inline int ufshcd_get_lists_status(u32 reg)
714{
6cf16115 715 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 716}
717
718/**
719 * ufshcd_get_uic_cmd_result - Get the UIC command result
720 * @hba: Pointer to adapter instance
721 *
722 * This function gets the result of UIC command completion
723 * Returns 0 on success, non zero value on error
724 */
725static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
726{
b873a275 727 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 728 MASK_UIC_COMMAND_RESULT;
729}
730
12b4fdb4
SJ		 731/**
732 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
733 * @hba: Pointer to adapter instance
734 *
735 * This function gets UIC command argument3
736 * Returns 0 on success, non zero value on error
737 */
738static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
739{
740 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
741}
742
7a3e97b0 743/**
5a0b0cb9 744 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 745 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 746 */
747static inline int
5a0b0cb9 748ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 749{
5a0b0cb9 750 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 751}
752
753/**
754 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
755 * @ucd_rsp_ptr: pointer to response UPIU
756 *
757 * This function gets the response status and scsi_status from response UPIU
758 * Returns the response result code.
759 */
760static inline int
761ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
762{
763 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
764}
765
1c2623c5
SJ		 766/*
767 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
768 * from response UPIU
769 * @ucd_rsp_ptr: pointer to response UPIU
770 *
771 * Return the data segment length.
772 */
773static inline unsigned int
774ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
775{
776 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
777 MASK_RSP_UPIU_DATA_SEG_LEN;
778}
779
66ec6d59
SRT		 780/**
781 * ufshcd_is_exception_event - Check if the device raised an exception event
782 * @ucd_rsp_ptr: pointer to response UPIU
783 *
784 * The function checks if the device raised an exception event indicated in
785 * the Device Information field of response UPIU.
786 *
787 * Returns true if exception is raised, false otherwise.
788 */
789static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
790{
791 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
792 MASK_RSP_EXCEPTION_EVENT ? true : false;
793}
794
7a3e97b0 795/**
7d568652 796 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 797 * @hba: per adapter instance
7a3e97b0
SY		 798 */
799static inline void
7d568652 800ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 801{
7d568652
SJ		 802 ufshcd_writel(hba, INT_AGGR_ENABLE |
803 INT_AGGR_COUNTER_AND_TIMER_RESET,
804 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
805}
806
807/**
808 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
809 * @hba: per adapter instance
810 * @cnt: Interrupt aggregation counter threshold
811 * @tmout: Interrupt aggregation timeout value
812 */
813static inline void
814ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
815{
816 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
817 INT_AGGR_COUNTER_THLD_VAL(cnt) |
818 INT_AGGR_TIMEOUT_VAL(tmout),
819 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 820}
821
b852190e
YG		 822/**
823 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
824 * @hba: per adapter instance
825 */
826static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
827{
828 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
829}
830
7a3e97b0
SY		 831/**
832 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
833 * When run-stop registers are set to 1, it indicates the
834 * host controller that it can process the requests
835 * @hba: per adapter instance
836 */
837static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
838{
b873a275
SJ		 839 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
840 REG_UTP_TASK_REQ_LIST_RUN_STOP);
841 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
842 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 843}
844
7a3e97b0
SY		 845/**
846 * ufshcd_hba_start - Start controller initialization sequence
847 * @hba: per adapter instance
848 */
849static inline void ufshcd_hba_start(struct ufs_hba *hba)
850{
b873a275 851 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 852}
853
854/**
855 * ufshcd_is_hba_active - Get controller state
856 * @hba: per adapter instance
857 *
c9e6010b 858 * Returns false if controller is active, true otherwise
7a3e97b0 859 */
c9e6010b 860static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 861{
4a8eec2b
TK		 862 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
863 ? false : true;
7a3e97b0
SY		 864}
865
37113106
YG		 866u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
867{
868 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
869 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
870 (hba->ufs_version == UFSHCI_VERSION_11))
871 return UFS_UNIPRO_VER_1_41;
872 else
873 return UFS_UNIPRO_VER_1_6;
874}
875EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
876
877static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
878{
879 /*
880 * If both host and device support UniPro ver1.6 or later, PA layer
881 * parameters tuning happens during link startup itself.
882 *
883 * We can manually tune PA layer parameters if either host or device
884 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
885 * logic simple, we will only do manual tuning if local unipro version
886 * doesn't support ver1.6 or later.
887 */
888 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
889 return true;
890 else
891 return false;
892}
893
a3cd5ec5 894static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
895{
896 int ret = 0;
897 struct ufs_clk_info *clki;
898 struct list_head *head = &hba->clk_list_head;
899 ktime_t start = ktime_get();
900 bool clk_state_changed = false;
901
566ec9ad 902 if (list_empty(head))
a3cd5ec5 903 goto out;
904
905 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
906 if (ret)
907 return ret;
908
909 list_for_each_entry(clki, head, list) {
910 if (!IS_ERR_OR_NULL(clki->clk)) {
911 if (scale_up && clki->max_freq) {
912 if (clki->curr_freq == clki->max_freq)
913 continue;
914
915 clk_state_changed = true;
916 ret = clk_set_rate(clki->clk, clki->max_freq);
917 if (ret) {
918 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
919 __func__, clki->name,
920 clki->max_freq, ret);
921 break;
922 }
923 trace_ufshcd_clk_scaling(dev_name(hba->dev),
924 "scaled up", clki->name,
925 clki->curr_freq,
926 clki->max_freq);
927
928 clki->curr_freq = clki->max_freq;
929
930 } else if (!scale_up && clki->min_freq) {
931 if (clki->curr_freq == clki->min_freq)
932 continue;
933
934 clk_state_changed = true;
935 ret = clk_set_rate(clki->clk, clki->min_freq);
936 if (ret) {
937 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
938 __func__, clki->name,
939 clki->min_freq, ret);
940 break;
941 }
942 trace_ufshcd_clk_scaling(dev_name(hba->dev),
943 "scaled down", clki->name,
944 clki->curr_freq,
945 clki->min_freq);
946 clki->curr_freq = clki->min_freq;
947 }
948 }
949 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
950 clki->name, clk_get_rate(clki->clk));
951 }
952
953 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
954
955out:
956 if (clk_state_changed)
957 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
958 (scale_up ? "up" : "down"),
959 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
960 return ret;
961}
962
963/**
964 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
965 * @hba: per adapter instance
966 * @scale_up: True if scaling up and false if scaling down
967 *
968 * Returns true if scaling is required, false otherwise.
969 */
970static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
971 bool scale_up)
972{
973 struct ufs_clk_info *clki;
974 struct list_head *head = &hba->clk_list_head;
975
566ec9ad 976 if (list_empty(head))
a3cd5ec5 977 return false;
978
979 list_for_each_entry(clki, head, list) {
980 if (!IS_ERR_OR_NULL(clki->clk)) {
981 if (scale_up && clki->max_freq) {
982 if (clki->curr_freq == clki->max_freq)
983 continue;
984 return true;
985 } else if (!scale_up && clki->min_freq) {
986 if (clki->curr_freq == clki->min_freq)
987 continue;
988 return true;
989 }
990 }
991 }
992
993 return false;
994}
995
996static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
997 u64 wait_timeout_us)
998{
999 unsigned long flags;
1000 int ret = 0;
1001 u32 tm_doorbell;
1002 u32 tr_doorbell;
1003 bool timeout = false, do_last_check = false;
1004 ktime_t start;
1005
1006 ufshcd_hold(hba, false);
1007 spin_lock_irqsave(hba->host->host_lock, flags);
1008 /*
1009 * Wait for all the outstanding tasks/transfer requests.
1010 * Verify by checking the doorbell registers are clear.
1011 */
1012 start = ktime_get();
1013 do {
1014 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1015 ret = -EBUSY;
1016 goto out;
1017 }
1018
1019 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1020 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1021 if (!tm_doorbell && !tr_doorbell) {
1022 timeout = false;
1023 break;
1024 } else if (do_last_check) {
1025 break;
1026 }
1027
1028 spin_unlock_irqrestore(hba->host->host_lock, flags);
1029 schedule();
1030 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1031 wait_timeout_us) {
1032 timeout = true;
1033 /*
1034 * We might have scheduled out for long time so make
1035 * sure to check if doorbells are cleared by this time
1036 * or not.
1037 */
1038 do_last_check = true;
1039 }
1040 spin_lock_irqsave(hba->host->host_lock, flags);
1041 } while (tm_doorbell || tr_doorbell);
1042
1043 if (timeout) {
1044 dev_err(hba->dev,
1045 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1046 __func__, tm_doorbell, tr_doorbell);
1047 ret = -EBUSY;
1048 }
1049out:
1050 spin_unlock_irqrestore(hba->host->host_lock, flags);
1051 ufshcd_release(hba);
1052 return ret;
1053}
1054
1055/**
1056 * ufshcd_scale_gear - scale up/down UFS gear
1057 * @hba: per adapter instance
1058 * @scale_up: True for scaling up gear and false for scaling down
1059 *
1060 * Returns 0 for success,
1061 * Returns -EBUSY if scaling can't happen at this time
1062 * Returns non-zero for any other errors
1063 */
1064static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1065{
1066 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1067 int ret = 0;
1068 struct ufs_pa_layer_attr new_pwr_info;
1069
1070 if (scale_up) {
1071 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1072 sizeof(struct ufs_pa_layer_attr));
1073 } else {
1074 memcpy(&new_pwr_info, &hba->pwr_info,
1075 sizeof(struct ufs_pa_layer_attr));
1076
1077 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1078 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1079 /* save the current power mode */
1080 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1081 &hba->pwr_info,
1082 sizeof(struct ufs_pa_layer_attr));
1083
1084 /* scale down gear */
1085 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1086 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1087 }
1088 }
1089
1090 /* check if the power mode needs to be changed or not? */
1091 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1092
1093 if (ret)
1094 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1095 __func__, ret,
1096 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1097 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1098
1099 return ret;
1100}
1101
1102static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1103{
1104 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1105 int ret = 0;
1106 /*
1107 * make sure that there are no outstanding requests when
1108 * clock scaling is in progress
1109 */
38135535 1110 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1111 down_write(&hba->clk_scaling_lock);
1112 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1113 ret = -EBUSY;
1114 up_write(&hba->clk_scaling_lock);
38135535 1115 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1116 }
1117
1118 return ret;
1119}
1120
1121static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1122{
1123 up_write(&hba->clk_scaling_lock);
38135535 1124 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1125}
1126
1127/**
1128 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1129 * @hba: per adapter instance
1130 * @scale_up: True for scaling up and false for scalin down
1131 *
1132 * Returns 0 for success,
1133 * Returns -EBUSY if scaling can't happen at this time
1134 * Returns non-zero for any other errors
1135 */
1136static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1137{
1138 int ret = 0;
1139
401f1e44 1140 /* let's not get into low power until clock scaling is completed */
1141 ufshcd_hold(hba, false);
1142
a3cd5ec5 1143 ret = ufshcd_clock_scaling_prepare(hba);
1144 if (ret)
1145 return ret;
1146
1147 /* scale down the gear before scaling down clocks */
1148 if (!scale_up) {
1149 ret = ufshcd_scale_gear(hba, false);
1150 if (ret)
1151 goto out;
1152 }
1153
1154 ret = ufshcd_scale_clks(hba, scale_up);
1155 if (ret) {
1156 if (!scale_up)
1157 ufshcd_scale_gear(hba, true);
1158 goto out;
1159 }
1160
1161 /* scale up the gear after scaling up clocks */
1162 if (scale_up) {
1163 ret = ufshcd_scale_gear(hba, true);
1164 if (ret) {
1165 ufshcd_scale_clks(hba, false);
1166 goto out;
1167 }
1168 }
1169
1170 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1171
1172out:
1173 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1174 ufshcd_release(hba);
a3cd5ec5 1175 return ret;
1176}
1177
401f1e44 1178static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1179{
1180 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1181 clk_scaling.suspend_work);
1182 unsigned long irq_flags;
1183
1184 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1185 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1186 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1187 return;
1188 }
1189 hba->clk_scaling.is_suspended = true;
1190 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1191
1192 __ufshcd_suspend_clkscaling(hba);
1193}
1194
1195static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1196{
1197 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1198 clk_scaling.resume_work);
1199 unsigned long irq_flags;
1200
1201 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1202 if (!hba->clk_scaling.is_suspended) {
1203 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1204 return;
1205 }
1206 hba->clk_scaling.is_suspended = false;
1207 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1208
1209 devfreq_resume_device(hba->devfreq);
1210}
1211
a3cd5ec5 1212static int ufshcd_devfreq_target(struct device *dev,
1213 unsigned long *freq, u32 flags)
1214{
1215 int ret = 0;
1216 struct ufs_hba *hba = dev_get_drvdata(dev);
1217 ktime_t start;
401f1e44 1218 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1219 struct list_head *clk_list = &hba->clk_list_head;
1220 struct ufs_clk_info *clki;
a3cd5ec5 1221 unsigned long irq_flags;
1222
1223 if (!ufshcd_is_clkscaling_supported(hba))
1224 return -EINVAL;
1225
a3cd5ec5 1226 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1227 if (ufshcd_eh_in_progress(hba)) {
1228 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1229 return 0;
1230 }
1231
401f1e44 1232 if (!hba->clk_scaling.active_reqs)
1233 sched_clk_scaling_suspend_work = true;
1234
092b4558
BA		 1235 if (list_empty(clk_list)) {
1236 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1237 goto out;
1238 }
1239
1240 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1241 scale_up = (*freq == clki->max_freq) ? true : false;
401f1e44 1242 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1243 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1244 ret = 0;
1245 goto out; /* no state change required */
a3cd5ec5 1246 }
1247 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1248
1249 start = ktime_get();
a3cd5ec5 1250 ret = ufshcd_devfreq_scale(hba, scale_up);
1251
a3cd5ec5 1252 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1253 (scale_up ? "up" : "down"),
1254 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1255
401f1e44 1256out:
1257 if (sched_clk_scaling_suspend_work)
1258 queue_work(hba->clk_scaling.workq,
1259 &hba->clk_scaling.suspend_work);
1260
a3cd5ec5 1261 return ret;
1262}
1263
1264
1265static int ufshcd_devfreq_get_dev_status(struct device *dev,
1266 struct devfreq_dev_status *stat)
1267{
1268 struct ufs_hba *hba = dev_get_drvdata(dev);
1269 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1270 unsigned long flags;
1271
1272 if (!ufshcd_is_clkscaling_supported(hba))
1273 return -EINVAL;
1274
1275 memset(stat, 0, sizeof(*stat));
1276
1277 spin_lock_irqsave(hba->host->host_lock, flags);
1278 if (!scaling->window_start_t)
1279 goto start_window;
1280
1281 if (scaling->is_busy_started)
1282 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1283 scaling->busy_start_t));
1284
1285 stat->total_time = jiffies_to_usecs((long)jiffies -
1286 (long)scaling->window_start_t);
1287 stat->busy_time = scaling->tot_busy_t;
1288start_window:
1289 scaling->window_start_t = jiffies;
1290 scaling->tot_busy_t = 0;
1291
1292 if (hba->outstanding_reqs) {
1293 scaling->busy_start_t = ktime_get();
1294 scaling->is_busy_started = true;
1295 } else {
1296 scaling->busy_start_t = 0;
1297 scaling->is_busy_started = false;
1298 }
1299 spin_unlock_irqrestore(hba->host->host_lock, flags);
1300 return 0;
1301}
1302
1303static struct devfreq_dev_profile ufs_devfreq_profile = {
1304 .polling_ms = 100,
1305 .target = ufshcd_devfreq_target,
1306 .get_dev_status = ufshcd_devfreq_get_dev_status,
1307};
1308
deac444f
BA		 1309static int ufshcd_devfreq_init(struct ufs_hba *hba)
1310{
092b4558
BA		 1311 struct list_head *clk_list = &hba->clk_list_head;
1312 struct ufs_clk_info *clki;
deac444f
BA		 1313 struct devfreq *devfreq;
1314 int ret;
1315
092b4558
BA		 1316 /* Skip devfreq if we don't have any clocks in the list */
1317 if (list_empty(clk_list))
1318 return 0;
1319
1320 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1321 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1322 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1323
1324 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1325 &ufs_devfreq_profile,
1326 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1327 NULL);
1328 if (IS_ERR(devfreq)) {
1329 ret = PTR_ERR(devfreq);
1330 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1331
1332 dev_pm_opp_remove(hba->dev, clki->min_freq);
1333 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1334 return ret;
1335 }
1336
1337 hba->devfreq = devfreq;
1338
1339 return 0;
1340}
1341
092b4558
BA		 1342static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1343{
1344 struct list_head *clk_list = &hba->clk_list_head;
1345 struct ufs_clk_info *clki;
1346
1347 if (!hba->devfreq)
1348 return;
1349
1350 devfreq_remove_device(hba->devfreq);
1351 hba->devfreq = NULL;
1352
1353 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1354 dev_pm_opp_remove(hba->dev, clki->min_freq);
1355 dev_pm_opp_remove(hba->dev, clki->max_freq);
1356}
1357
401f1e44 1358static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1359{
1360 unsigned long flags;
1361
1362 devfreq_suspend_device(hba->devfreq);
1363 spin_lock_irqsave(hba->host->host_lock, flags);
1364 hba->clk_scaling.window_start_t = 0;
1365 spin_unlock_irqrestore(hba->host->host_lock, flags);
1366}
a3cd5ec5 1367
a508253d
GB		 1368static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1369{
401f1e44 1370 unsigned long flags;
1371 bool suspend = false;
1372
fcb0c4b0
ST		 1373 if (!ufshcd_is_clkscaling_supported(hba))
1374 return;
1375
401f1e44 1376 spin_lock_irqsave(hba->host->host_lock, flags);
1377 if (!hba->clk_scaling.is_suspended) {
1378 suspend = true;
1379 hba->clk_scaling.is_suspended = true;
1380 }
1381 spin_unlock_irqrestore(hba->host->host_lock, flags);
1382
1383 if (suspend)
1384 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1385}
1386
1387static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1388{
401f1e44 1389 unsigned long flags;
1390 bool resume = false;
1391
1392 if (!ufshcd_is_clkscaling_supported(hba))
1393 return;
1394
1395 spin_lock_irqsave(hba->host->host_lock, flags);
1396 if (hba->clk_scaling.is_suspended) {
1397 resume = true;
1398 hba->clk_scaling.is_suspended = false;
1399 }
1400 spin_unlock_irqrestore(hba->host->host_lock, flags);
1401
1402 if (resume)
1403 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1404}
1405
1406static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1407 struct device_attribute *attr, char *buf)
1408{
1409 struct ufs_hba *hba = dev_get_drvdata(dev);
1410
1411 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1412}
1413
1414static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1415 struct device_attribute *attr, const char *buf, size_t count)
1416{
1417 struct ufs_hba *hba = dev_get_drvdata(dev);
1418 u32 value;
1419 int err;
1420
1421 if (kstrtou32(buf, 0, &value))
1422 return -EINVAL;
1423
1424 value = !!value;
1425 if (value == hba->clk_scaling.is_allowed)
1426 goto out;
1427
1428 pm_runtime_get_sync(hba->dev);
1429 ufshcd_hold(hba, false);
1430
401f1e44 1431 cancel_work_sync(&hba->clk_scaling.suspend_work);
1432 cancel_work_sync(&hba->clk_scaling.resume_work);
1433
1434 hba->clk_scaling.is_allowed = value;
1435
fcb0c4b0
ST		 1436 if (value) {
1437 ufshcd_resume_clkscaling(hba);
1438 } else {
1439 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1440 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1441 if (err)
1442 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1443 __func__, err);
1444 }
fcb0c4b0
ST		 1445
1446 ufshcd_release(hba);
1447 pm_runtime_put_sync(hba->dev);
1448out:
1449 return count;
a508253d
GB		 1450}
1451
a3cd5ec5 1452static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1453{
1454 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1455 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1456 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1457 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1458 hba->clk_scaling.enable_attr.attr.mode = 0644;
1459 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1460 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1461}
1462
1ab27c9c
ST		 1463static void ufshcd_ungate_work(struct work_struct *work)
1464{
1465 int ret;
1466 unsigned long flags;
1467 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1468 clk_gating.ungate_work);
1469
1470 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1471
1472 spin_lock_irqsave(hba->host->host_lock, flags);
1473 if (hba->clk_gating.state == CLKS_ON) {
1474 spin_unlock_irqrestore(hba->host->host_lock, flags);
1475 goto unblock_reqs;
1476 }
1477
1478 spin_unlock_irqrestore(hba->host->host_lock, flags);
1479 ufshcd_setup_clocks(hba, true);
1480
1481 /* Exit from hibern8 */
1482 if (ufshcd_can_hibern8_during_gating(hba)) {
1483 /* Prevent gating in this path */
1484 hba->clk_gating.is_suspended = true;
1485 if (ufshcd_is_link_hibern8(hba)) {
1486 ret = ufshcd_uic_hibern8_exit(hba);
1487 if (ret)
1488 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1489 __func__, ret);
1490 else
1491 ufshcd_set_link_active(hba);
1492 }
1493 hba->clk_gating.is_suspended = false;
1494 }
1495unblock_reqs:
38135535 1496 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1497}
1498
1499/**
1500 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1501 * Also, exit from hibern8 mode and set the link as active.
1502 * @hba: per adapter instance
1503 * @async: This indicates whether caller should ungate clocks asynchronously.
1504 */
1505int ufshcd_hold(struct ufs_hba *hba, bool async)
1506{
1507 int rc = 0;
1508 unsigned long flags;
1509
1510 if (!ufshcd_is_clkgating_allowed(hba))
1511 goto out;
1ab27c9c
ST		 1512 spin_lock_irqsave(hba->host->host_lock, flags);
1513 hba->clk_gating.active_reqs++;
1514
53c12d0e
YG		 1515 if (ufshcd_eh_in_progress(hba)) {
1516 spin_unlock_irqrestore(hba->host->host_lock, flags);
1517 return 0;
1518 }
1519
856b3483 1520start:
1ab27c9c
ST		 1521 switch (hba->clk_gating.state) {
1522 case CLKS_ON:
f2a785ac
VG		 1523 /*
1524 * Wait for the ungate work to complete if in progress.
1525 * Though the clocks may be in ON state, the link could
1526 * still be in hibner8 state if hibern8 is allowed
1527 * during clock gating.
1528 * Make sure we exit hibern8 state also in addition to
1529 * clocks being ON.
1530 */
1531 if (ufshcd_can_hibern8_during_gating(hba) &&
1532 ufshcd_is_link_hibern8(hba)) {
1533 spin_unlock_irqrestore(hba->host->host_lock, flags);
1534 flush_work(&hba->clk_gating.ungate_work);
1535 spin_lock_irqsave(hba->host->host_lock, flags);
1536 goto start;
1537 }
1ab27c9c
ST		 1538 break;
1539 case REQ_CLKS_OFF:
1540 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1541 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1542 trace_ufshcd_clk_gating(dev_name(hba->dev),
1543 hba->clk_gating.state);
1ab27c9c
ST		 1544 break;
1545 }
1546 /*
9c490d2d 1547 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1548 * currently running. Hence, fall through to cancel gating
1549 * work and to enable clocks.
1550 */
1551 case CLKS_OFF:
38135535 1552 ufshcd_scsi_block_requests(hba);
1ab27c9c 1553 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1554 trace_ufshcd_clk_gating(dev_name(hba->dev),
1555 hba->clk_gating.state);
10e5e375
VV		 1556 queue_work(hba->clk_gating.clk_gating_workq,
1557 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1558 /*
1559 * fall through to check if we should wait for this
1560 * work to be done or not.
1561 */
1562 case REQ_CLKS_ON:
1563 if (async) {
1564 rc = -EAGAIN;
1565 hba->clk_gating.active_reqs--;
1566 break;
1567 }
1568
1569 spin_unlock_irqrestore(hba->host->host_lock, flags);
1570 flush_work(&hba->clk_gating.ungate_work);
1571 /* Make sure state is CLKS_ON before returning */
856b3483 1572 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1573 goto start;
1574 default:
1575 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1576 __func__, hba->clk_gating.state);
1577 break;
1578 }
1579 spin_unlock_irqrestore(hba->host->host_lock, flags);
1580out:
1581 return rc;
1582}
6e3fd44d 1583EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1584
1585static void ufshcd_gate_work(struct work_struct *work)
1586{
1587 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1588 clk_gating.gate_work.work);
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1592 /*
1593 * In case you are here to cancel this work the gating state
1594 * would be marked as REQ_CLKS_ON. In this case save time by
1595 * skipping the gating work and exit after changing the clock
1596 * state to CLKS_ON.
1597 */
1598 if (hba->clk_gating.is_suspended ||
1599 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1600 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1601 trace_ufshcd_clk_gating(dev_name(hba->dev),
1602 hba->clk_gating.state);
1ab27c9c
ST		 1603 goto rel_lock;
1604 }
1605
1606 if (hba->clk_gating.active_reqs
1607 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1608 || hba->lrb_in_use || hba->outstanding_tasks
1609 || hba->active_uic_cmd || hba->uic_async_done)
1610 goto rel_lock;
1611
1612 spin_unlock_irqrestore(hba->host->host_lock, flags);
1613
1614 /* put the link into hibern8 mode before turning off clocks */
1615 if (ufshcd_can_hibern8_during_gating(hba)) {
1616 if (ufshcd_uic_hibern8_enter(hba)) {
1617 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1618 trace_ufshcd_clk_gating(dev_name(hba->dev),
1619 hba->clk_gating.state);
1ab27c9c
ST		 1620 goto out;
1621 }
1622 ufshcd_set_link_hibern8(hba);
1623 }
1624
1625 if (!ufshcd_is_link_active(hba))
1626 ufshcd_setup_clocks(hba, false);
1627 else
1628 /* If link is active, device ref_clk can't be switched off */
1629 __ufshcd_setup_clocks(hba, false, true);
1630
1631 /*
1632 * In case you are here to cancel this work the gating state
1633 * would be marked as REQ_CLKS_ON. In this case keep the state
1634 * as REQ_CLKS_ON which would anyway imply that clocks are off
1635 * and a request to turn them on is pending. By doing this way,
1636 * we keep the state machine in tact and this would ultimately
1637 * prevent from doing cancel work multiple times when there are
1638 * new requests arriving before the current cancel work is done.
1639 */
1640 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1641 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1642 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1643 trace_ufshcd_clk_gating(dev_name(hba->dev),
1644 hba->clk_gating.state);
1645 }
1ab27c9c
ST		 1646rel_lock:
1647 spin_unlock_irqrestore(hba->host->host_lock, flags);
1648out:
1649 return;
1650}
1651
1652/* host lock must be held before calling this variant */
1653static void __ufshcd_release(struct ufs_hba *hba)
1654{
1655 if (!ufshcd_is_clkgating_allowed(hba))
1656 return;
1657
1658 hba->clk_gating.active_reqs--;
1659
1660 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1661 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1662 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1663 || hba->active_uic_cmd || hba->uic_async_done
1664 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1665 return;
1666
1667 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1668 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1669 schedule_delayed_work(&hba->clk_gating.gate_work,
1670 msecs_to_jiffies(hba->clk_gating.delay_ms));
1671}
1672
1673void ufshcd_release(struct ufs_hba *hba)
1674{
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(hba->host->host_lock, flags);
1678 __ufshcd_release(hba);
1679 spin_unlock_irqrestore(hba->host->host_lock, flags);
1680}
6e3fd44d 1681EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1682
1683static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1684 struct device_attribute *attr, char *buf)
1685{
1686 struct ufs_hba *hba = dev_get_drvdata(dev);
1687
1688 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1689}
1690
1691static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1692 struct device_attribute *attr, const char *buf, size_t count)
1693{
1694 struct ufs_hba *hba = dev_get_drvdata(dev);
1695 unsigned long flags, value;
1696
1697 if (kstrtoul(buf, 0, &value))
1698 return -EINVAL;
1699
1700 spin_lock_irqsave(hba->host->host_lock, flags);
1701 hba->clk_gating.delay_ms = value;
1702 spin_unlock_irqrestore(hba->host->host_lock, flags);
1703 return count;
1704}
1705
b427411a
ST		 1706static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1707 struct device_attribute *attr, char *buf)
1708{
1709 struct ufs_hba *hba = dev_get_drvdata(dev);
1710
1711 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1712}
1713
1714static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1715 struct device_attribute *attr, const char *buf, size_t count)
1716{
1717 struct ufs_hba *hba = dev_get_drvdata(dev);
1718 unsigned long flags;
1719 u32 value;
1720
1721 if (kstrtou32(buf, 0, &value))
1722 return -EINVAL;
1723
1724 value = !!value;
1725 if (value == hba->clk_gating.is_enabled)
1726 goto out;
1727
1728 if (value) {
1729 ufshcd_release(hba);
1730 } else {
1731 spin_lock_irqsave(hba->host->host_lock, flags);
1732 hba->clk_gating.active_reqs++;
1733 spin_unlock_irqrestore(hba->host->host_lock, flags);
1734 }
1735
1736 hba->clk_gating.is_enabled = value;
1737out:
1738 return count;
1739}
1740
eebcc196
VG		 1741static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1742{
1743 char wq_name[sizeof("ufs_clkscaling_00")];
1744
1745 if (!ufshcd_is_clkscaling_supported(hba))
1746 return;
1747
1748 INIT_WORK(&hba->clk_scaling.suspend_work,
1749 ufshcd_clk_scaling_suspend_work);
1750 INIT_WORK(&hba->clk_scaling.resume_work,
1751 ufshcd_clk_scaling_resume_work);
1752
1753 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1754 hba->host->host_no);
1755 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1756
1757 ufshcd_clkscaling_init_sysfs(hba);
1758}
1759
1760static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1761{
1762 if (!ufshcd_is_clkscaling_supported(hba))
1763 return;
1764
1765 destroy_workqueue(hba->clk_scaling.workq);
1766 ufshcd_devfreq_remove(hba);
1767}
1768
1ab27c9c
ST		 1769static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1770{
10e5e375
VV		 1771 char wq_name[sizeof("ufs_clk_gating_00")];
1772
1ab27c9c
ST		 1773 if (!ufshcd_is_clkgating_allowed(hba))
1774 return;
1775
1776 hba->clk_gating.delay_ms = 150;
1777 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1778 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1779
10e5e375
VV		 1780 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1781 hba->host->host_no);
1782 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1783 WQ_MEM_RECLAIM);
1784
b427411a
ST		 1785 hba->clk_gating.is_enabled = true;
1786
1ab27c9c
ST		 1787 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1788 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1789 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1790 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1791 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1792 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1793 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1794
1795 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1796 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1797 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1798 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1799 hba->clk_gating.enable_attr.attr.mode = 0644;
1800 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1801 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1802}
1803
1804static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1805{
1806 if (!ufshcd_is_clkgating_allowed(hba))
1807 return;
1808 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1809 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1810 cancel_work_sync(&hba->clk_gating.ungate_work);
1811 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1812 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1813}
1814
856b3483
ST		 1815/* Must be called with host lock acquired */
1816static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1817{
401f1e44 1818 bool queue_resume_work = false;
1819
fcb0c4b0 1820 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1821 return;
1822
401f1e44 1823 if (!hba->clk_scaling.active_reqs++)
1824 queue_resume_work = true;
1825
1826 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1827 return;
1828
1829 if (queue_resume_work)
1830 queue_work(hba->clk_scaling.workq,
1831 &hba->clk_scaling.resume_work);
1832
1833 if (!hba->clk_scaling.window_start_t) {
1834 hba->clk_scaling.window_start_t = jiffies;
1835 hba->clk_scaling.tot_busy_t = 0;
1836 hba->clk_scaling.is_busy_started = false;
1837 }
1838
856b3483
ST		 1839 if (!hba->clk_scaling.is_busy_started) {
1840 hba->clk_scaling.busy_start_t = ktime_get();
1841 hba->clk_scaling.is_busy_started = true;
1842 }
1843}
1844
1845static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1846{
1847 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1848
fcb0c4b0 1849 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1850 return;
1851
1852 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1853 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1854 scaling->busy_start_t));
8b0e1953 1855 scaling->busy_start_t = 0;
856b3483
ST		 1856 scaling->is_busy_started = false;
1857 }
1858}
7a3e97b0
SY		 1859/**
1860 * ufshcd_send_command - Send SCSI or device management commands
1861 * @hba: per adapter instance
1862 * @task_tag: Task tag of the command
1863 */
1864static inline
1865void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1866{
ff8e20c6 1867 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1868 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
856b3483 1869 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1870 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1871 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1872 /* Make sure that doorbell is committed immediately */
1873 wmb();
1a07f2d9 1874 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1875}
1876
1877/**
1878 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1879 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1880 */
1881static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1882{
1883 int len;
1c2623c5
SJ		 1884 if (lrbp->sense_buffer &&
1885 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1886 int len_to_copy;
1887
5a0b0cb9 1888 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1889 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1890
7a3e97b0 1891 memcpy(lrbp->sense_buffer,
5a0b0cb9 1892 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1893 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1894 }
1895}
1896
68078d5c
DR		 1897/**
1898 * ufshcd_copy_query_response() - Copy the Query Response and the data
1899 * descriptor
1900 * @hba: per adapter instance
8aa29f19 1901 * @lrbp: pointer to local reference block
68078d5c
DR		 1902 */
1903static
c6d4a831 1904int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1905{
1906 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1907
68078d5c 1908 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1909
68078d5c
DR		 1910 /* Get the descriptor */
1911 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1912 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1913 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1914 u16 resp_len;
1915 u16 buf_len;
68078d5c
DR		 1916
1917 /* data segment length */
c6d4a831 1918 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1919 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1920 buf_len = be16_to_cpu(
1921 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1922 if (likely(buf_len >= resp_len)) {
1923 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1924 } else {
1925 dev_warn(hba->dev,
1926 "%s: Response size is bigger than buffer",
1927 __func__);
1928 return -EINVAL;
1929 }
68078d5c 1930 }
c6d4a831
DR		 1931
1932 return 0;
68078d5c
DR		 1933}
1934
7a3e97b0
SY		 1935/**
1936 * ufshcd_hba_capabilities - Read controller capabilities
1937 * @hba: per adapter instance
1938 */
1939static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1940{
b873a275 1941 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1942
1943 /* nutrs and nutmrs are 0 based values */
1944 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1945 hba->nutmrs =
1946 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1947}
1948
1949/**
6ccf44fe
SJ		 1950 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1951 * to accept UIC commands
7a3e97b0 1952 * @hba: per adapter instance
6ccf44fe
SJ		 1953 * Return true on success, else false
1954 */
1955static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1956{
1957 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1958 return true;
1959 else
1960 return false;
1961}
1962
53b3d9c3
SJ		 1963/**
1964 * ufshcd_get_upmcrs - Get the power mode change request status
1965 * @hba: Pointer to adapter instance
1966 *
1967 * This function gets the UPMCRS field of HCS register
1968 * Returns value of UPMCRS field
1969 */
1970static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1971{
1972 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1973}
1974
6ccf44fe
SJ		 1975/**
1976 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1977 * @hba: per adapter instance
1978 * @uic_cmd: UIC command
1979 *
1980 * Mutex must be held.
7a3e97b0
SY		 1981 */
1982static inline void
6ccf44fe 1983ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1984{
6ccf44fe
SJ		 1985 WARN_ON(hba->active_uic_cmd);
1986
1987 hba->active_uic_cmd = uic_cmd;
1988
7a3e97b0 1989 /* Write Args */
6ccf44fe
SJ		 1990 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1991 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1992 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1993
1994 /* Write UIC Cmd */
6ccf44fe 1995 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1996 REG_UIC_COMMAND);
7a3e97b0
SY		 1997}
1998
6ccf44fe
SJ		 1999/**
2000 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2001 * @hba: per adapter instance
8aa29f19 2002 * @uic_cmd: UIC command
6ccf44fe
SJ		 2003 *
2004 * Must be called with mutex held.
2005 * Returns 0 only if success.
2006 */
2007static int
2008ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2009{
2010 int ret;
2011 unsigned long flags;
2012
2013 if (wait_for_completion_timeout(&uic_cmd->done,
2014 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2015 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2016 else
2017 ret = -ETIMEDOUT;
2018
2019 spin_lock_irqsave(hba->host->host_lock, flags);
2020 hba->active_uic_cmd = NULL;
2021 spin_unlock_irqrestore(hba->host->host_lock, flags);
2022
2023 return ret;
2024}
2025
2026/**
2027 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2028 * @hba: per adapter instance
2029 * @uic_cmd: UIC command
d75f7fe4 2030 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2031 *
2032 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2033 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2034 * Returns 0 only if success.
2035 */
2036static int
d75f7fe4
YG		 2037__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2038 bool completion)
6ccf44fe 2039{
6ccf44fe
SJ		 2040 if (!ufshcd_ready_for_uic_cmd(hba)) {
2041 dev_err(hba->dev,
2042 "Controller not ready to accept UIC commands\n");
2043 return -EIO;
2044 }
2045
d75f7fe4
YG		 2046 if (completion)
2047 init_completion(&uic_cmd->done);
6ccf44fe 2048
6ccf44fe 2049 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2050
57d104c1 2051 return 0;
6ccf44fe
SJ		 2052}
2053
2054/**
2055 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2056 * @hba: per adapter instance
2057 * @uic_cmd: UIC command
2058 *
2059 * Returns 0 only if success.
2060 */
2061static int
2062ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2063{
2064 int ret;
57d104c1 2065 unsigned long flags;
6ccf44fe 2066
1ab27c9c 2067 ufshcd_hold(hba, false);
6ccf44fe 2068 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2069 ufshcd_add_delay_before_dme_cmd(hba);
2070
57d104c1 2071 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2072 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2073 spin_unlock_irqrestore(hba->host->host_lock, flags);
2074 if (!ret)
2075 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2076
6ccf44fe
SJ		 2077 mutex_unlock(&hba->uic_cmd_mutex);
2078
1ab27c9c 2079 ufshcd_release(hba);
6ccf44fe
SJ		 2080 return ret;
2081}
2082
7a3e97b0
SY		 2083/**
2084 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2085 * @hba: per adapter instance
2086 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2087 *
2088 * Returns 0 in case of success, non-zero value in case of failure
2089 */
75b1cc4a 2090static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2091{
2092 struct ufshcd_sg_entry *prd_table;
2093 struct scatterlist *sg;
2094 struct scsi_cmnd *cmd;
2095 int sg_segments;
2096 int i;
2097
2098 cmd = lrbp->cmd;
2099 sg_segments = scsi_dma_map(cmd);
2100 if (sg_segments < 0)
2101 return sg_segments;
2102
2103 if (sg_segments) {
75b1cc4a
KK		 2104 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2105 lrbp->utr_descriptor_ptr->prd_table_length =
2106 cpu_to_le16((u16)(sg_segments *
2107 sizeof(struct ufshcd_sg_entry)));
2108 else
2109 lrbp->utr_descriptor_ptr->prd_table_length =
2110 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2111
2112 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2113
2114 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2115 prd_table[i].size =
2116 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2117 prd_table[i].base_addr =
2118 cpu_to_le32(lower_32_bits(sg->dma_address));
2119 prd_table[i].upper_addr =
2120 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2121 prd_table[i].reserved = 0;
7a3e97b0
SY		 2122 }
2123 } else {
2124 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2125 }
2126
2127 return 0;
2128}
2129
2130/**
2fbd009b 2131 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2132 * @hba: per adapter instance
2fbd009b 2133 * @intrs: interrupt bits
7a3e97b0 2134 */
2fbd009b 2135static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2136{
2fbd009b
SJ		 2137 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2138
2139 if (hba->ufs_version == UFSHCI_VERSION_10) {
2140 u32 rw;
2141 rw = set & INTERRUPT_MASK_RW_VER_10;
2142 set = rw | ((set ^ intrs) & intrs);
2143 } else {
2144 set |= intrs;
2145 }
2146
2147 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2148}
2149
2150/**
2151 * ufshcd_disable_intr - disable interrupts
2152 * @hba: per adapter instance
2153 * @intrs: interrupt bits
2154 */
2155static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2156{
2157 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2158
2159 if (hba->ufs_version == UFSHCI_VERSION_10) {
2160 u32 rw;
2161 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2162 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2163 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2164
2165 } else {
2166 set &= ~intrs;
7a3e97b0 2167 }
2fbd009b
SJ		 2168
2169 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2170}
2171
5a0b0cb9
SRT		 2172/**
2173 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2174 * descriptor according to request
2175 * @lrbp: pointer to local reference block
2176 * @upiu_flags: flags required in the header
2177 * @cmd_dir: requests data direction
2178 */
2179static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2180 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2181{
2182 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2183 u32 data_direction;
2184 u32 dword_0;
2185
2186 if (cmd_dir == DMA_FROM_DEVICE) {
2187 data_direction = UTP_DEVICE_TO_HOST;
2188 *upiu_flags = UPIU_CMD_FLAGS_READ;
2189 } else if (cmd_dir == DMA_TO_DEVICE) {
2190 data_direction = UTP_HOST_TO_DEVICE;
2191 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2192 } else {
2193 data_direction = UTP_NO_DATA_TRANSFER;
2194 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2195 }
2196
2197 dword_0 = data_direction | (lrbp->command_type
2198 << UPIU_COMMAND_TYPE_OFFSET);
2199 if (lrbp->intr_cmd)
2200 dword_0 |= UTP_REQ_DESC_INT_CMD;
2201
2202 /* Transfer request descriptor header fields */
2203 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2204 /* dword_1 is reserved, hence it is set to 0 */
2205 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2206 /*
2207 * assigning invalid value for command status. Controller
2208 * updates OCS on command completion, with the command
2209 * status
2210 */
2211 req_desc->header.dword_2 =
2212 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2213 /* dword_3 is reserved, hence it is set to 0 */
2214 req_desc->header.dword_3 = 0;
51047266
YG		 2215
2216 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2217}
2218
2219/**
2220 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2221 * for scsi commands
8aa29f19
BVA		 2222 * @lrbp: local reference block pointer
2223 * @upiu_flags: flags
5a0b0cb9
SRT		 2224 */
2225static
2226void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2227{
2228 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2229 unsigned short cdb_len;
5a0b0cb9
SRT		 2230
2231 /* command descriptor fields */
2232 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2233 UPIU_TRANSACTION_COMMAND, upiu_flags,
2234 lrbp->lun, lrbp->task_tag);
2235 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2236 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2237
2238 /* Total EHS length and Data segment length will be zero */
2239 ucd_req_ptr->header.dword_2 = 0;
2240
2241 ucd_req_ptr->sc.exp_data_transfer_len =
2242 cpu_to_be32(lrbp->cmd->sdb.length);
2243
a851b2bd
AA		 2244 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, UFS_CDB_SIZE);
2245 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
52ac95fe
YG		 2246 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2247
2248 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2249}
2250
68078d5c
DR		 2251/**
2252 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2253 * for query requsts
2254 * @hba: UFS hba
2255 * @lrbp: local reference block pointer
2256 * @upiu_flags: flags
2257 */
2258static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2259 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2260{
2261 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2262 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2263 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2264 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2265
2266 /* Query request header */
2267 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2268 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2269 lrbp->lun, lrbp->task_tag);
2270 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2271 0, query->request.query_func, 0, 0);
2272
6861285c
ZL		 2273 /* Data segment length only need for WRITE_DESC */
2274 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2275 ucd_req_ptr->header.dword_2 =
2276 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2277 else
2278 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2279
2280 /* Copy the Query Request buffer as is */
2281 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2282 QUERY_OSF_SIZE);
68078d5c
DR		 2283
2284 /* Copy the Descriptor */
c6d4a831
DR		 2285 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2286 memcpy(descp, query->descriptor, len);
2287
51047266 2288 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2289}
2290
5a0b0cb9
SRT		 2291static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2292{
2293 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2294
2295 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2296
2297 /* command descriptor fields */
2298 ucd_req_ptr->header.dword_0 =
2299 UPIU_HEADER_DWORD(
2300 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2301 /* clear rest of the fields of basic header */
2302 ucd_req_ptr->header.dword_1 = 0;
2303 ucd_req_ptr->header.dword_2 = 0;
2304
2305 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2306}
2307
7a3e97b0 2308/**
300bb13f
JP		 2309 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2310 * for Device Management Purposes
8aa29f19
BVA		 2311 * @hba: per adapter instance
2312 * @lrbp: pointer to local reference block
7a3e97b0 2313 */
300bb13f 2314static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2315{
7a3e97b0 2316 u32 upiu_flags;
5a0b0cb9 2317 int ret = 0;
7a3e97b0 2318
83dc7e3d 2319 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2320 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2321 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2322 else
2323 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2324
2325 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2326 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2327 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2328 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2329 ufshcd_prepare_utp_nop_upiu(lrbp);
2330 else
2331 ret = -EINVAL;
2332
2333 return ret;
2334}
2335
2336/**
2337 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2338 * for SCSI Purposes
8aa29f19
BVA		 2339 * @hba: per adapter instance
2340 * @lrbp: pointer to local reference block
300bb13f
JP		 2341 */
2342static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2343{
2344 u32 upiu_flags;
2345 int ret = 0;
2346
83dc7e3d 2347 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2348 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2349 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2350 else
2351 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2352
2353 if (likely(lrbp->cmd)) {
2354 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2355 lrbp->cmd->sc_data_direction);
2356 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2357 } else {
2358 ret = -EINVAL;
2359 }
5a0b0cb9
SRT		 2360
2361 return ret;
7a3e97b0
SY		 2362}
2363
2a8fa600
SJ		 2364/**
2365 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2366 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2367 *
2368 * Returns SCSI W-LUN id
2369 */
2370static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2371{
2372 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2373}
2374
7a3e97b0
SY		 2375/**
2376 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2377 * @host: SCSI host pointer
7a3e97b0 2378 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2379 *
2380 * Returns 0 for success, non-zero in case of failure
2381 */
2382static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2383{
2384 struct ufshcd_lrb *lrbp;
2385 struct ufs_hba *hba;
2386 unsigned long flags;
2387 int tag;
2388 int err = 0;
2389
2390 hba = shost_priv(host);
2391
2392 tag = cmd->request->tag;
14497328
YG		 2393 if (!ufshcd_valid_tag(hba, tag)) {
2394 dev_err(hba->dev,
2395 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2396 __func__, tag, cmd, cmd->request);
2397 BUG();
2398 }
7a3e97b0 2399
a3cd5ec5 2400 if (!down_read_trylock(&hba->clk_scaling_lock))
2401 return SCSI_MLQUEUE_HOST_BUSY;
2402
3441da7d
SRT		 2403 spin_lock_irqsave(hba->host->host_lock, flags);
2404 switch (hba->ufshcd_state) {
2405 case UFSHCD_STATE_OPERATIONAL:
2406 break;
141f8165 2407 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2408 case UFSHCD_STATE_RESET:
7a3e97b0 2409 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2410 goto out_unlock;
2411 case UFSHCD_STATE_ERROR:
2412 set_host_byte(cmd, DID_ERROR);
2413 cmd->scsi_done(cmd);
2414 goto out_unlock;
2415 default:
2416 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2417 __func__, hba->ufshcd_state);
2418 set_host_byte(cmd, DID_BAD_TARGET);
2419 cmd->scsi_done(cmd);
2420 goto out_unlock;
7a3e97b0 2421 }
53c12d0e
YG		 2422
2423 /* if error handling is in progress, don't issue commands */
2424 if (ufshcd_eh_in_progress(hba)) {
2425 set_host_byte(cmd, DID_ERROR);
2426 cmd->scsi_done(cmd);
2427 goto out_unlock;
2428 }
3441da7d 2429 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2430
7fabb77b
GB		 2431 hba->req_abort_count = 0;
2432
5a0b0cb9
SRT		 2433 /* acquire the tag to make sure device cmds don't use it */
2434 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2435 /*
2436 * Dev manage command in progress, requeue the command.
2437 * Requeuing the command helps in cases where the request *may*
2438 * find different tag instead of waiting for dev manage command
2439 * completion.
2440 */
2441 err = SCSI_MLQUEUE_HOST_BUSY;
2442 goto out;
2443 }
2444
1ab27c9c
ST		 2445 err = ufshcd_hold(hba, true);
2446 if (err) {
2447 err = SCSI_MLQUEUE_HOST_BUSY;
2448 clear_bit_unlock(tag, &hba->lrb_in_use);
2449 goto out;
2450 }
2451 WARN_ON(hba->clk_gating.state != CLKS_ON);
2452
7a3e97b0
SY		 2453 lrbp = &hba->lrb[tag];
2454
5a0b0cb9 2455 WARN_ON(lrbp->cmd);
7a3e97b0 2456 lrbp->cmd = cmd;
dcea0bfb 2457 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2458 lrbp->sense_buffer = cmd->sense_buffer;
2459 lrbp->task_tag = tag;
0ce147d4 2460 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2461 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2462 lrbp->req_abort_skip = false;
7a3e97b0 2463
300bb13f
JP		 2464 ufshcd_comp_scsi_upiu(hba, lrbp);
2465
75b1cc4a 2466 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2467 if (err) {
2468 lrbp->cmd = NULL;
2469 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2470 goto out;
5a0b0cb9 2471 }
ad1a1b9c
GB		 2472 /* Make sure descriptors are ready before ringing the doorbell */
2473 wmb();
7a3e97b0
SY		 2474
2475 /* issue command to the controller */
2476 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2477 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2478 ufshcd_send_command(hba, tag);
3441da7d 2479out_unlock:
7a3e97b0
SY		 2480 spin_unlock_irqrestore(hba->host->host_lock, flags);
2481out:
a3cd5ec5 2482 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2483 return err;
2484}
2485
5a0b0cb9
SRT		 2486static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2487 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2488{
2489 lrbp->cmd = NULL;
2490 lrbp->sense_bufflen = 0;
2491 lrbp->sense_buffer = NULL;
2492 lrbp->task_tag = tag;
2493 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2494 lrbp->intr_cmd = true; /* No interrupt aggregation */
2495 hba->dev_cmd.type = cmd_type;
2496
300bb13f 2497 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2498}
2499
2500static int
2501ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2502{
2503 int err = 0;
2504 unsigned long flags;
2505 u32 mask = 1 << tag;
2506
2507 /* clear outstanding transaction before retry */
2508 spin_lock_irqsave(hba->host->host_lock, flags);
2509 ufshcd_utrl_clear(hba, tag);
2510 spin_unlock_irqrestore(hba->host->host_lock, flags);
2511
2512 /*
2513 * wait for for h/w to clear corresponding bit in door-bell.
2514 * max. wait is 1 sec.
2515 */
2516 err = ufshcd_wait_for_register(hba,
2517 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2518 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2519
2520 return err;
2521}
2522
c6d4a831
DR		 2523static int
2524ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2525{
2526 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2527
2528 /* Get the UPIU response */
2529 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2530 UPIU_RSP_CODE_OFFSET;
2531 return query_res->response;
2532}
2533
5a0b0cb9
SRT		 2534/**
2535 * ufshcd_dev_cmd_completion() - handles device management command responses
2536 * @hba: per adapter instance
2537 * @lrbp: pointer to local reference block
2538 */
2539static int
2540ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2541{
2542 int resp;
2543 int err = 0;
2544
ff8e20c6 2545 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2546 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2547
2548 switch (resp) {
2549 case UPIU_TRANSACTION_NOP_IN:
2550 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2551 err = -EINVAL;
2552 dev_err(hba->dev, "%s: unexpected response %x\n",
2553 __func__, resp);
2554 }
2555 break;
68078d5c 2556 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2557 err = ufshcd_check_query_response(hba, lrbp);
2558 if (!err)
2559 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2560 break;
5a0b0cb9
SRT		 2561 case UPIU_TRANSACTION_REJECT_UPIU:
2562 /* TODO: handle Reject UPIU Response */
2563 err = -EPERM;
2564 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2565 __func__);
2566 break;
2567 default:
2568 err = -EINVAL;
2569 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2570 __func__, resp);
2571 break;
2572 }
2573
2574 return err;
2575}
2576
2577static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2578 struct ufshcd_lrb *lrbp, int max_timeout)
2579{
2580 int err = 0;
2581 unsigned long time_left;
2582 unsigned long flags;
2583
2584 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2585 msecs_to_jiffies(max_timeout));
2586
ad1a1b9c
GB		 2587 /* Make sure descriptors are ready before ringing the doorbell */
2588 wmb();
5a0b0cb9
SRT		 2589 spin_lock_irqsave(hba->host->host_lock, flags);
2590 hba->dev_cmd.complete = NULL;
2591 if (likely(time_left)) {
2592 err = ufshcd_get_tr_ocs(lrbp);
2593 if (!err)
2594 err = ufshcd_dev_cmd_completion(hba, lrbp);
2595 }
2596 spin_unlock_irqrestore(hba->host->host_lock, flags);
2597
2598 if (!time_left) {
2599 err = -ETIMEDOUT;
a48353f6
YG		 2600 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2601 __func__, lrbp->task_tag);
5a0b0cb9 2602 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2603 /* successfully cleared the command, retry if needed */
5a0b0cb9 2604 err = -EAGAIN;
a48353f6
YG		 2605 /*
2606 * in case of an error, after clearing the doorbell,
2607 * we also need to clear the outstanding_request
2608 * field in hba
2609 */
2610 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2611 }
2612
2613 return err;
2614}
2615
2616/**
2617 * ufshcd_get_dev_cmd_tag - Get device management command tag
2618 * @hba: per-adapter instance
8aa29f19 2619 * @tag_out: pointer to variable with available slot value
5a0b0cb9
SRT		 2620 *
2621 * Get a free slot and lock it until device management command
2622 * completes.
2623 *
2624 * Returns false if free slot is unavailable for locking, else
2625 * return true with tag value in @tag.
2626 */
2627static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2628{
2629 int tag;
2630 bool ret = false;
2631 unsigned long tmp;
2632
2633 if (!tag_out)
2634 goto out;
2635
2636 do {
2637 tmp = ~hba->lrb_in_use;
2638 tag = find_last_bit(&tmp, hba->nutrs);
2639 if (tag >= hba->nutrs)
2640 goto out;
2641 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2642
2643 *tag_out = tag;
2644 ret = true;
2645out:
2646 return ret;
2647}
2648
2649static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2650{
2651 clear_bit_unlock(tag, &hba->lrb_in_use);
2652}
2653
2654/**
2655 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2656 * @hba: UFS hba
2657 * @cmd_type: specifies the type (NOP, Query...)
2658 * @timeout: time in seconds
5a0b0cb9 2659 *
68078d5c
DR		 2660 * NOTE: Since there is only one available tag for device management commands,
2661 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2662 */
2663static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2664 enum dev_cmd_type cmd_type, int timeout)
2665{
2666 struct ufshcd_lrb *lrbp;
2667 int err;
2668 int tag;
2669 struct completion wait;
2670 unsigned long flags;
2671
a3cd5ec5 2672 down_read(&hba->clk_scaling_lock);
2673
5a0b0cb9
SRT		 2674 /*
2675 * Get free slot, sleep if slots are unavailable.
2676 * Even though we use wait_event() which sleeps indefinitely,
2677 * the maximum wait time is bounded by SCSI request timeout.
2678 */
2679 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2680
2681 init_completion(&wait);
2682 lrbp = &hba->lrb[tag];
2683 WARN_ON(lrbp->cmd);
2684 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2685 if (unlikely(err))
2686 goto out_put_tag;
2687
2688 hba->dev_cmd.complete = &wait;
2689
6667e6d9 2690 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2691 /* Make sure descriptors are ready before ringing the doorbell */
2692 wmb();
5a0b0cb9 2693 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2694 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2695 ufshcd_send_command(hba, tag);
2696 spin_unlock_irqrestore(hba->host->host_lock, flags);
2697
2698 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2699
6667e6d9
OS		 2700 ufshcd_add_query_upiu_trace(hba, tag,
2701 err ? "query_complete_err" : "query_complete");
2702
5a0b0cb9
SRT		 2703out_put_tag:
2704 ufshcd_put_dev_cmd_tag(hba, tag);
2705 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2706 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2707 return err;
2708}
2709
d44a5f98
DR		 2710/**
2711 * ufshcd_init_query() - init the query response and request parameters
2712 * @hba: per-adapter instance
2713 * @request: address of the request pointer to be initialized
2714 * @response: address of the response pointer to be initialized
2715 * @opcode: operation to perform
2716 * @idn: flag idn to access
2717 * @index: LU number to access
2718 * @selector: query/flag/descriptor further identification
2719 */
2720static inline void ufshcd_init_query(struct ufs_hba *hba,
2721 struct ufs_query_req **request, struct ufs_query_res **response,
2722 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2723{
2724 *request = &hba->dev_cmd.query.request;
2725 *response = &hba->dev_cmd.query.response;
2726 memset(*request, 0, sizeof(struct ufs_query_req));
2727 memset(*response, 0, sizeof(struct ufs_query_res));
2728 (*request)->upiu_req.opcode = opcode;
2729 (*request)->upiu_req.idn = idn;
2730 (*request)->upiu_req.index = index;
2731 (*request)->upiu_req.selector = selector;
2732}
2733
dc3c8d3a
YG		 2734static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2735 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2736{
2737 int ret;
2738 int retries;
2739
2740 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2741 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2742 if (ret)
2743 dev_dbg(hba->dev,
2744 "%s: failed with error %d, retries %d\n",
2745 __func__, ret, retries);
2746 else
2747 break;
2748 }
2749
2750 if (ret)
2751 dev_err(hba->dev,
2752 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2753 __func__, opcode, idn, ret, retries);
2754 return ret;
2755}
2756
68078d5c
DR		 2757/**
2758 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2759 * @hba: per-adapter instance
2760 * @opcode: flag query to perform
2761 * @idn: flag idn to access
2762 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2763 *
2764 * Returns 0 for success, non-zero in case of failure
2765 */
dc3c8d3a 2766int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2767 enum flag_idn idn, bool *flag_res)
2768{
d44a5f98
DR		 2769 struct ufs_query_req *request = NULL;
2770 struct ufs_query_res *response = NULL;
2771 int err, index = 0, selector = 0;
e5ad406c 2772 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2773
2774 BUG_ON(!hba);
2775
1ab27c9c 2776 ufshcd_hold(hba, false);
68078d5c 2777 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2778 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2779 selector);
68078d5c
DR		 2780
2781 switch (opcode) {
2782 case UPIU_QUERY_OPCODE_SET_FLAG:
2783 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2784 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2785 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2786 break;
2787 case UPIU_QUERY_OPCODE_READ_FLAG:
2788 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2789 if (!flag_res) {
2790 /* No dummy reads */
2791 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2792 __func__);
2793 err = -EINVAL;
2794 goto out_unlock;
2795 }
2796 break;
2797 default:
2798 dev_err(hba->dev,
2799 "%s: Expected query flag opcode but got = %d\n",
2800 __func__, opcode);
2801 err = -EINVAL;
2802 goto out_unlock;
2803 }
68078d5c 2804
e5ad406c 2805 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2806
2807 if (err) {
2808 dev_err(hba->dev,
2809 "%s: Sending flag query for idn %d failed, err = %d\n",
2810 __func__, idn, err);
2811 goto out_unlock;
2812 }
2813
2814 if (flag_res)
e8c8e82a 2815 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2816 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2817
2818out_unlock:
2819 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2820 ufshcd_release(hba);
68078d5c
DR		 2821 return err;
2822}
2823
66ec6d59
SRT		 2824/**
2825 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2826 * @hba: per-adapter instance
2827 * @opcode: attribute opcode
2828 * @idn: attribute idn to access
2829 * @index: index field
2830 * @selector: selector field
2831 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2832 *
2833 * Returns 0 for success, non-zero in case of failure
2834*/
ec92b59c
SN		 2835int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2836 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2837{
d44a5f98
DR		 2838 struct ufs_query_req *request = NULL;
2839 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2840 int err;
2841
2842 BUG_ON(!hba);
2843
1ab27c9c 2844 ufshcd_hold(hba, false);
66ec6d59
SRT		 2845 if (!attr_val) {
2846 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2847 __func__, opcode);
2848 err = -EINVAL;
2849 goto out;
2850 }
2851
2852 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2853 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2854 selector);
66ec6d59
SRT		 2855
2856 switch (opcode) {
2857 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2858 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2859 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2860 break;
2861 case UPIU_QUERY_OPCODE_READ_ATTR:
2862 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2863 break;
2864 default:
2865 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2866 __func__, opcode);
2867 err = -EINVAL;
2868 goto out_unlock;
2869 }
2870
d44a5f98 2871 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2872
2873 if (err) {
4b761b58
YG		 2874 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2875 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2876 goto out_unlock;
2877 }
2878
e8c8e82a 2879 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2880
2881out_unlock:
2882 mutex_unlock(&hba->dev_cmd.lock);
2883out:
1ab27c9c 2884 ufshcd_release(hba);
66ec6d59
SRT		 2885 return err;
2886}
2887
5e86ae44
YG		 2888/**
2889 * ufshcd_query_attr_retry() - API function for sending query
2890 * attribute with retries
2891 * @hba: per-adapter instance
2892 * @opcode: attribute opcode
2893 * @idn: attribute idn to access
2894 * @index: index field
2895 * @selector: selector field
2896 * @attr_val: the attribute value after the query request
2897 * completes
2898 *
2899 * Returns 0 for success, non-zero in case of failure
2900*/
2901static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2902 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2903 u32 *attr_val)
2904{
2905 int ret = 0;
2906 u32 retries;
2907
2908 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2909 ret = ufshcd_query_attr(hba, opcode, idn, index,
2910 selector, attr_val);
2911 if (ret)
2912 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2913 __func__, ret, retries);
2914 else
2915 break;
2916 }
2917
2918 if (ret)
2919 dev_err(hba->dev,
2920 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2921 __func__, idn, ret, QUERY_REQ_RETRIES);
2922 return ret;
2923}
2924
a70e91b8 2925static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2926 enum query_opcode opcode, enum desc_idn idn, u8 index,
2927 u8 selector, u8 *desc_buf, int *buf_len)
2928{
2929 struct ufs_query_req *request = NULL;
2930 struct ufs_query_res *response = NULL;
2931 int err;
2932
2933 BUG_ON(!hba);
2934
1ab27c9c 2935 ufshcd_hold(hba, false);
d44a5f98
DR		 2936 if (!desc_buf) {
2937 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2938 __func__, opcode);
2939 err = -EINVAL;
2940 goto out;
2941 }
2942
a4b0e8a4 2943 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2944 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2945 __func__, *buf_len);
2946 err = -EINVAL;
2947 goto out;
2948 }
2949
2950 mutex_lock(&hba->dev_cmd.lock);
2951 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2952 selector);
2953 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2954 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2955
2956 switch (opcode) {
2957 case UPIU_QUERY_OPCODE_WRITE_DESC:
2958 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2959 break;
2960 case UPIU_QUERY_OPCODE_READ_DESC:
2961 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2962 break;
2963 default:
2964 dev_err(hba->dev,
2965 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2966 __func__, opcode);
2967 err = -EINVAL;
2968 goto out_unlock;
2969 }
2970
2971 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2972
2973 if (err) {
4b761b58
YG		 2974 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2975 __func__, opcode, idn, index, err);
d44a5f98
DR		 2976 goto out_unlock;
2977 }
2978
2979 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2980 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2981
2982out_unlock:
2983 mutex_unlock(&hba->dev_cmd.lock);
2984out:
1ab27c9c 2985 ufshcd_release(hba);
d44a5f98
DR		 2986 return err;
2987}
2988
a70e91b8 2989/**
8aa29f19
BVA		 2990 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2991 * @hba: per-adapter instance
2992 * @opcode: attribute opcode
2993 * @idn: attribute idn to access
2994 * @index: index field
2995 * @selector: selector field
2996 * @desc_buf: the buffer that contains the descriptor
2997 * @buf_len: length parameter passed to the device
a70e91b8
YG		 2998 *
2999 * Returns 0 for success, non-zero in case of failure.
3000 * The buf_len parameter will contain, on return, the length parameter
3001 * received on the response.
3002 */
2238d31c
SN		 3003int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3004 enum query_opcode opcode,
3005 enum desc_idn idn, u8 index,
3006 u8 selector,
3007 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3008{
3009 int err;
3010 int retries;
3011
3012 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3013 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3014 selector, desc_buf, buf_len);
3015 if (!err || err == -EINVAL)
3016 break;
3017 }
3018
3019 return err;
3020}
a70e91b8 3021
a4b0e8a4
PM		 3022/**
3023 * ufshcd_read_desc_length - read the specified descriptor length from header
3024 * @hba: Pointer to adapter instance
3025 * @desc_id: descriptor idn value
3026 * @desc_index: descriptor index
3027 * @desc_length: pointer to variable to read the length of descriptor
3028 *
3029 * Return 0 in case of success, non-zero otherwise
3030 */
3031static int ufshcd_read_desc_length(struct ufs_hba *hba,
3032 enum desc_idn desc_id,
3033 int desc_index,
3034 int *desc_length)
3035{
3036 int ret;
3037 u8 header[QUERY_DESC_HDR_SIZE];
3038 int header_len = QUERY_DESC_HDR_SIZE;
3039
3040 if (desc_id >= QUERY_DESC_IDN_MAX)
3041 return -EINVAL;
3042
3043 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3044 desc_id, desc_index, 0, header,
3045 &header_len);
3046
3047 if (ret) {
3048 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3049 __func__, desc_id);
3050 return ret;
3051 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3052 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3053 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3054 desc_id);
3055 ret = -EINVAL;
3056 }
3057
3058 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3059 return ret;
3060
3061}
3062
3063/**
3064 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3065 * @hba: Pointer to adapter instance
3066 * @desc_id: descriptor idn value
3067 * @desc_len: mapped desc length (out)
3068 *
3069 * Return 0 in case of success, non-zero otherwise
3070 */
3071int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3072 enum desc_idn desc_id, int *desc_len)
3073{
3074 switch (desc_id) {
3075 case QUERY_DESC_IDN_DEVICE:
3076 *desc_len = hba->desc_size.dev_desc;
3077 break;
3078 case QUERY_DESC_IDN_POWER:
3079 *desc_len = hba->desc_size.pwr_desc;
3080 break;
3081 case QUERY_DESC_IDN_GEOMETRY:
3082 *desc_len = hba->desc_size.geom_desc;
3083 break;
3084 case QUERY_DESC_IDN_CONFIGURATION:
3085 *desc_len = hba->desc_size.conf_desc;
3086 break;
3087 case QUERY_DESC_IDN_UNIT:
3088 *desc_len = hba->desc_size.unit_desc;
3089 break;
3090 case QUERY_DESC_IDN_INTERCONNECT:
3091 *desc_len = hba->desc_size.interc_desc;
3092 break;
3093 case QUERY_DESC_IDN_STRING:
3094 *desc_len = QUERY_DESC_MAX_SIZE;
3095 break;
c648c2d2
SN		 3096 case QUERY_DESC_IDN_HEALTH:
3097 *desc_len = hba->desc_size.hlth_desc;
3098 break;
a4b0e8a4
PM		 3099 case QUERY_DESC_IDN_RFU_0:
3100 case QUERY_DESC_IDN_RFU_1:
3101 *desc_len = 0;
3102 break;
3103 default:
3104 *desc_len = 0;
3105 return -EINVAL;
3106 }
3107 return 0;
3108}
3109EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3110
da461cec
SJ		 3111/**
3112 * ufshcd_read_desc_param - read the specified descriptor parameter
3113 * @hba: Pointer to adapter instance
3114 * @desc_id: descriptor idn value
3115 * @desc_index: descriptor index
3116 * @param_offset: offset of the parameter to read
3117 * @param_read_buf: pointer to buffer where parameter would be read
3118 * @param_size: sizeof(param_read_buf)
3119 *
3120 * Return 0 in case of success, non-zero otherwise
3121 */
45bced87
SN		 3122int ufshcd_read_desc_param(struct ufs_hba *hba,
3123 enum desc_idn desc_id,
3124 int desc_index,
3125 u8 param_offset,
3126 u8 *param_read_buf,
3127 u8 param_size)
da461cec
SJ		 3128{
3129 int ret;
3130 u8 *desc_buf;
a4b0e8a4 3131 int buff_len;
da461cec
SJ		 3132 bool is_kmalloc = true;
3133
a4b0e8a4
PM		 3134 /* Safety check */
3135 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3136 return -EINVAL;
3137
a4b0e8a4
PM		 3138 /* Get the max length of descriptor from structure filled up at probe
3139 * time.
3140 */
3141 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3142
a4b0e8a4
PM		 3143 /* Sanity checks */
3144 if (ret || !buff_len) {
3145 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3146 __func__);
3147 return ret;
3148 }
3149
3150 /* Check whether we need temp memory */
3151 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3152 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3153 if (!desc_buf)
3154 return -ENOMEM;
a4b0e8a4
PM		 3155 } else {
3156 desc_buf = param_read_buf;
3157 is_kmalloc = false;
da461cec
SJ		 3158 }
3159
a4b0e8a4 3160 /* Request for full descriptor */
a70e91b8 3161 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3162 desc_id, desc_index, 0,
3163 desc_buf, &buff_len);
da461cec 3164
bde44bb6 3165 if (ret) {
3166 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3167 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3168 goto out;
3169 }
3170
bde44bb6 3171 /* Sanity check */
3172 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3173 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3174 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3175 ret = -EINVAL;
3176 goto out;
3177 }
3178
a4b0e8a4
PM		 3179 /* Check wherher we will not copy more data, than available */
3180 if (is_kmalloc && param_size > buff_len)
3181 param_size = buff_len;
bde44bb6 3182
da461cec
SJ		 3183 if (is_kmalloc)
3184 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3185out:
3186 if (is_kmalloc)
3187 kfree(desc_buf);
3188 return ret;
3189}
3190
3191static inline int ufshcd_read_desc(struct ufs_hba *hba,
3192 enum desc_idn desc_id,
3193 int desc_index,
3194 u8 *buf,
3195 u32 size)
3196{
3197 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3198}
3199
3200static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3201 u8 *buf,
3202 u32 size)
3203{
dbd34a61 3204 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3205}
3206
8209b6d5 3207static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3208{
3209 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3210}
b573d484
YG		 3211
3212/**
3213 * ufshcd_read_string_desc - read string descriptor
3214 * @hba: pointer to adapter instance
3215 * @desc_index: descriptor index
3216 * @buf: pointer to buffer where descriptor would be read
3217 * @size: size of buf
3218 * @ascii: if true convert from unicode to ascii characters
3219 *
3220 * Return 0 in case of success, non-zero otherwise
3221 */
2238d31c
SN		 3222int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3223 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3224{
3225 int err = 0;
3226
3227 err = ufshcd_read_desc(hba,
3228 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3229
3230 if (err) {
3231 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3232 __func__, QUERY_REQ_RETRIES, err);
3233 goto out;
3234 }
3235
3236 if (ascii) {
3237 int desc_len;
3238 int ascii_len;
3239 int i;
3240 char *buff_ascii;
3241
3242 desc_len = buf[0];
3243 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3244 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3245 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3246 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3247 __func__);
3248 err = -ENOMEM;
3249 goto out;
3250 }
3251
3252 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3253 if (!buff_ascii) {
3254 err = -ENOMEM;
fcbefc3b 3255 goto out;
b573d484
YG		 3256 }
3257
3258 /*
3259 * the descriptor contains string in UTF16 format
3260 * we need to convert to utf-8 so it can be displayed
3261 */
3262 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3263 desc_len - QUERY_DESC_HDR_SIZE,
3264 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3265
3266 /* replace non-printable or non-ASCII characters with spaces */
3267 for (i = 0; i < ascii_len; i++)
3268 ufshcd_remove_non_printable(&buff_ascii[i]);
3269
3270 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3271 size - QUERY_DESC_HDR_SIZE);
3272 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3273 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3274 kfree(buff_ascii);
3275 }
3276out:
3277 return err;
3278}
b573d484 3279
da461cec
SJ		 3280/**
3281 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3282 * @hba: Pointer to adapter instance
3283 * @lun: lun id
3284 * @param_offset: offset of the parameter to read
3285 * @param_read_buf: pointer to buffer where parameter would be read
3286 * @param_size: sizeof(param_read_buf)
3287 *
3288 * Return 0 in case of success, non-zero otherwise
3289 */
3290static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3291 int lun,
3292 enum unit_desc_param param_offset,
3293 u8 *param_read_buf,
3294 u32 param_size)
3295{
3296 /*
3297 * Unit descriptors are only available for general purpose LUs (LUN id
3298 * from 0 to 7) and RPMB Well known LU.
3299 */
d829fc8a 3300 if (!ufs_is_valid_unit_desc_lun(lun))
da461cec
SJ		 3301 return -EOPNOTSUPP;
3302
3303 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3304 param_offset, param_read_buf, param_size);
3305}
3306
7a3e97b0
SY		 3307/**
3308 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3309 * @hba: per adapter instance
3310 *
3311 * 1. Allocate DMA memory for Command Descriptor array
3312 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3313 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3314 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3315 * (UTMRDL)
3316 * 4. Allocate memory for local reference block(lrb).
3317 *
3318 * Returns 0 for success, non-zero in case of failure
3319 */
3320static int ufshcd_memory_alloc(struct ufs_hba *hba)
3321{
3322 size_t utmrdl_size, utrdl_size, ucdl_size;
3323
3324 /* Allocate memory for UTP command descriptors */
3325 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3326 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3327 ucdl_size,
3328 &hba->ucdl_dma_addr,
3329 GFP_KERNEL);
7a3e97b0
SY		 3330
3331 /*
3332 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3333 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3334 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3335 * be aligned to 128 bytes as well
3336 */
3337 if (!hba->ucdl_base_addr ||
3338 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3339 dev_err(hba->dev,
7a3e97b0
SY		 3340 "Command Descriptor Memory allocation failed\n");
3341 goto out;
3342 }
3343
3344 /*
3345 * Allocate memory for UTP Transfer descriptors
3346 * UFSHCI requires 1024 byte alignment of UTRD
3347 */
3348 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3349 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3350 utrdl_size,
3351 &hba->utrdl_dma_addr,
3352 GFP_KERNEL);
7a3e97b0
SY		 3353 if (!hba->utrdl_base_addr ||
3354 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3355 dev_err(hba->dev,
7a3e97b0
SY		 3356 "Transfer Descriptor Memory allocation failed\n");
3357 goto out;
3358 }
3359
3360 /*
3361 * Allocate memory for UTP Task Management descriptors
3362 * UFSHCI requires 1024 byte alignment of UTMRD
3363 */
3364 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3365 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3366 utmrdl_size,
3367 &hba->utmrdl_dma_addr,
3368 GFP_KERNEL);
7a3e97b0
SY		 3369 if (!hba->utmrdl_base_addr ||
3370 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3371 dev_err(hba->dev,
7a3e97b0
SY		 3372 "Task Management Descriptor Memory allocation failed\n");
3373 goto out;
3374 }
3375
3376 /* Allocate memory for local reference block */
a86854d0
KC		 3377 hba->lrb = devm_kcalloc(hba->dev,
3378 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3379 GFP_KERNEL);
7a3e97b0 3380 if (!hba->lrb) {
3b1d0580 3381 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3382 goto out;
3383 }
3384 return 0;
3385out:
7a3e97b0
SY		 3386 return -ENOMEM;
3387}
3388
3389/**
3390 * ufshcd_host_memory_configure - configure local reference block with
3391 * memory offsets
3392 * @hba: per adapter instance
3393 *
3394 * Configure Host memory space
3395 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3396 * address.
3397 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3398 * and PRDT offset.
3399 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3400 * into local reference block.
3401 */
3402static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3403{
3404 struct utp_transfer_cmd_desc *cmd_descp;
3405 struct utp_transfer_req_desc *utrdlp;
3406 dma_addr_t cmd_desc_dma_addr;
3407 dma_addr_t cmd_desc_element_addr;
3408 u16 response_offset;
3409 u16 prdt_offset;
3410 int cmd_desc_size;
3411 int i;
3412
3413 utrdlp = hba->utrdl_base_addr;
3414 cmd_descp = hba->ucdl_base_addr;
3415
3416 response_offset =
3417 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3418 prdt_offset =
3419 offsetof(struct utp_transfer_cmd_desc, prd_table);
3420
3421 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3422 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3423
3424 for (i = 0; i < hba->nutrs; i++) {
3425 /* Configure UTRD with command descriptor base address */
3426 cmd_desc_element_addr =
3427 (cmd_desc_dma_addr + (cmd_desc_size * i));
3428 utrdlp[i].command_desc_base_addr_lo =
3429 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3430 utrdlp[i].command_desc_base_addr_hi =
3431 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3432
3433 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3434 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3435 utrdlp[i].response_upiu_offset =
3436 cpu_to_le16(response_offset);
3437 utrdlp[i].prd_table_offset =
3438 cpu_to_le16(prdt_offset);
3439 utrdlp[i].response_upiu_length =
3440 cpu_to_le16(ALIGNED_UPIU_SIZE);
3441 } else {
3442 utrdlp[i].response_upiu_offset =
7a3e97b0 3443 cpu_to_le16((response_offset >> 2));
75b1cc4a 3444 utrdlp[i].prd_table_offset =
7a3e97b0 3445 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3446 utrdlp[i].response_upiu_length =
3ca316c5 3447 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3448 }
7a3e97b0
SY		 3449
3450 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3451 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3452 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3453 hba->lrb[i].ucd_req_ptr =
3454 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3455 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3456 hba->lrb[i].ucd_rsp_ptr =
3457 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3458 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3459 response_offset;
7a3e97b0
SY		 3460 hba->lrb[i].ucd_prdt_ptr =
3461 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3462 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3463 prdt_offset;
7a3e97b0
SY		 3464 }
3465}
3466
3467/**
3468 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3469 * @hba: per adapter instance
3470 *
3471 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3472 * in order to initialize the Unipro link startup procedure.
3473 * Once the Unipro links are up, the device connected to the controller
3474 * is detected.
3475 *
3476 * Returns 0 on success, non-zero value on failure
3477 */
3478static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3479{
6ccf44fe
SJ		 3480 struct uic_command uic_cmd = {0};
3481 int ret;
7a3e97b0 3482
6ccf44fe 3483 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3484
6ccf44fe
SJ		 3485 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3486 if (ret)
ff8e20c6 3487 dev_dbg(hba->dev,
6ccf44fe
SJ		 3488 "dme-link-startup: error code %d\n", ret);
3489 return ret;
7a3e97b0 3490}
4404c5de
AA		 3491/**
3492 * ufshcd_dme_reset - UIC command for DME_RESET
3493 * @hba: per adapter instance
3494 *
3495 * DME_RESET command is issued in order to reset UniPro stack.
3496 * This function now deal with cold reset.
3497 *
3498 * Returns 0 on success, non-zero value on failure
3499 */
3500static int ufshcd_dme_reset(struct ufs_hba *hba)
3501{
3502 struct uic_command uic_cmd = {0};
3503 int ret;
3504
3505 uic_cmd.command = UIC_CMD_DME_RESET;
3506
3507 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3508 if (ret)
3509 dev_err(hba->dev,
3510 "dme-reset: error code %d\n", ret);
3511
3512 return ret;
3513}
3514
3515/**
3516 * ufshcd_dme_enable - UIC command for DME_ENABLE
3517 * @hba: per adapter instance
3518 *
3519 * DME_ENABLE command is issued in order to enable UniPro stack.
3520 *
3521 * Returns 0 on success, non-zero value on failure
3522 */
3523static int ufshcd_dme_enable(struct ufs_hba *hba)
3524{
3525 struct uic_command uic_cmd = {0};
3526 int ret;
3527
3528 uic_cmd.command = UIC_CMD_DME_ENABLE;
3529
3530 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3531 if (ret)
3532 dev_err(hba->dev,
3533 "dme-reset: error code %d\n", ret);
3534
3535 return ret;
3536}
7a3e97b0 3537
cad2e03d
YG		 3538static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3539{
3540 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3541 unsigned long min_sleep_time_us;
3542
3543 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3544 return;
3545
3546 /*
3547 * last_dme_cmd_tstamp will be 0 only for 1st call to
3548 * this function
3549 */
3550 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3551 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3552 } else {
3553 unsigned long delta =
3554 (unsigned long) ktime_to_us(
3555 ktime_sub(ktime_get(),
3556 hba->last_dme_cmd_tstamp));
3557
3558 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3559 min_sleep_time_us =
3560 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3561 else
3562 return; /* no more delay required */
3563 }
3564
3565 /* allow sleep for extra 50us if needed */
3566 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3567}
3568
12b4fdb4
SJ		 3569/**
3570 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3571 * @hba: per adapter instance
3572 * @attr_sel: uic command argument1
3573 * @attr_set: attribute set type as uic command argument2
3574 * @mib_val: setting value as uic command argument3
3575 * @peer: indicate whether peer or local
3576 *
3577 * Returns 0 on success, non-zero value on failure
3578 */
3579int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3580 u8 attr_set, u32 mib_val, u8 peer)
3581{
3582 struct uic_command uic_cmd = {0};
3583 static const char *const action[] = {
3584 "dme-set",
3585 "dme-peer-set"
3586 };
3587 const char *set = action[!!peer];
3588 int ret;
64238fbd 3589 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3590
3591 uic_cmd.command = peer ?
3592 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3593 uic_cmd.argument1 = attr_sel;
3594 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3595 uic_cmd.argument3 = mib_val;
3596
64238fbd
YG		 3597 do {
3598 /* for peer attributes we retry upon failure */
3599 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3600 if (ret)
3601 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3602 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3603 } while (ret && peer && --retries);
3604
f37e9f8c 3605 if (ret)
64238fbd 3606 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3607 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3608 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3609
3610 return ret;
3611}
3612EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3613
3614/**
3615 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3616 * @hba: per adapter instance
3617 * @attr_sel: uic command argument1
3618 * @mib_val: the value of the attribute as returned by the UIC command
3619 * @peer: indicate whether peer or local
3620 *
3621 * Returns 0 on success, non-zero value on failure
3622 */
3623int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3624 u32 *mib_val, u8 peer)
3625{
3626 struct uic_command uic_cmd = {0};
3627 static const char *const action[] = {
3628 "dme-get",
3629 "dme-peer-get"
3630 };
3631 const char *get = action[!!peer];
3632 int ret;
64238fbd 3633 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3634 struct ufs_pa_layer_attr orig_pwr_info;
3635 struct ufs_pa_layer_attr temp_pwr_info;
3636 bool pwr_mode_change = false;
3637
3638 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3639 orig_pwr_info = hba->pwr_info;
3640 temp_pwr_info = orig_pwr_info;
3641
3642 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3643 orig_pwr_info.pwr_rx == FAST_MODE) {
3644 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3645 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3646 pwr_mode_change = true;
3647 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3648 orig_pwr_info.pwr_rx == SLOW_MODE) {
3649 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3650 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3651 pwr_mode_change = true;
3652 }
3653 if (pwr_mode_change) {
3654 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3655 if (ret)
3656 goto out;
3657 }
3658 }
12b4fdb4
SJ		 3659
3660 uic_cmd.command = peer ?
3661 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3662 uic_cmd.argument1 = attr_sel;
3663
64238fbd
YG		 3664 do {
3665 /* for peer attributes we retry upon failure */
3666 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3667 if (ret)
3668 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3669 get, UIC_GET_ATTR_ID(attr_sel), ret);
3670 } while (ret && peer && --retries);
3671
f37e9f8c 3672 if (ret)
64238fbd 3673 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3674 get, UIC_GET_ATTR_ID(attr_sel),
3675 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3676
64238fbd 3677 if (mib_val && !ret)
12b4fdb4 3678 *mib_val = uic_cmd.argument3;
874237f7
YG		 3679
3680 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3681 && pwr_mode_change)
3682 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3683out:
3684 return ret;
3685}
3686EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3687
53b3d9c3 3688/**
57d104c1
SJ		 3689 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3690 * state) and waits for it to take effect.
3691 *
53b3d9c3 3692 * @hba: per adapter instance
57d104c1
SJ		 3693 * @cmd: UIC command to execute
3694 *
3695 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3696 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3697 * and device UniPro link and hence it's final completion would be indicated by
3698 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3699 * addition to normal UIC command completion Status (UCCS). This function only
3700 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3701 *
3702 * Returns 0 on success, non-zero value on failure
3703 */
57d104c1 3704static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3705{
57d104c1 3706 struct completion uic_async_done;
53b3d9c3
SJ		 3707 unsigned long flags;
3708 u8 status;
3709 int ret;
d75f7fe4 3710 bool reenable_intr = false;
53b3d9c3 3711
53b3d9c3 3712 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3713 init_completion(&uic_async_done);
cad2e03d 3714 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3715
3716 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3717 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3718 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3719 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3720 /*
3721 * Make sure UIC command completion interrupt is disabled before
3722 * issuing UIC command.
3723 */
3724 wmb();
3725 reenable_intr = true;
57d104c1 3726 }
d75f7fe4
YG		 3727 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3728 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3729 if (ret) {
3730 dev_err(hba->dev,
3731 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3732 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3733 goto out;
3734 }
3735
57d104c1 3736 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3737 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3738 dev_err(hba->dev,
57d104c1
SJ		 3739 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3740 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3741 ret = -ETIMEDOUT;
3742 goto out;
3743 }
3744
3745 status = ufshcd_get_upmcrs(hba);
3746 if (status != PWR_LOCAL) {
3747 dev_err(hba->dev,
479da360 3748 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3749 cmd->command, status);
53b3d9c3
SJ		 3750 ret = (status != PWR_OK) ? status : -1;
3751 }
3752out:
7942f7b5
VG		 3753 if (ret) {
3754 ufshcd_print_host_state(hba);
3755 ufshcd_print_pwr_info(hba);
3756 ufshcd_print_host_regs(hba);
3757 }
3758
53b3d9c3 3759 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3760 hba->active_uic_cmd = NULL;
57d104c1 3761 hba->uic_async_done = NULL;
d75f7fe4
YG		 3762 if (reenable_intr)
3763 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3764 spin_unlock_irqrestore(hba->host->host_lock, flags);
3765 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3766
53b3d9c3
SJ		 3767 return ret;
3768}
3769
57d104c1
SJ		 3770/**
3771 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3772 * using DME_SET primitives.
3773 * @hba: per adapter instance
3774 * @mode: powr mode value
3775 *
3776 * Returns 0 on success, non-zero value on failure
3777 */
3778static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3779{
3780 struct uic_command uic_cmd = {0};
1ab27c9c 3781 int ret;
57d104c1 3782
c3a2f9ee
YG		 3783 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3784 ret = ufshcd_dme_set(hba,
3785 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3786 if (ret) {
3787 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3788 __func__, ret);
3789 goto out;
3790 }
3791 }
3792
57d104c1
SJ		 3793 uic_cmd.command = UIC_CMD_DME_SET;
3794 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3795 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3796 ufshcd_hold(hba, false);
3797 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3798 ufshcd_release(hba);
57d104c1 3799
c3a2f9ee 3800out:
1ab27c9c 3801 return ret;
57d104c1
SJ		 3802}
3803
53c12d0e
YG		 3804static int ufshcd_link_recovery(struct ufs_hba *hba)
3805{
3806 int ret;
3807 unsigned long flags;
3808
3809 spin_lock_irqsave(hba->host->host_lock, flags);
3810 hba->ufshcd_state = UFSHCD_STATE_RESET;
3811 ufshcd_set_eh_in_progress(hba);
3812 spin_unlock_irqrestore(hba->host->host_lock, flags);
3813
3814 ret = ufshcd_host_reset_and_restore(hba);
3815
3816 spin_lock_irqsave(hba->host->host_lock, flags);
3817 if (ret)
3818 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3819 ufshcd_clear_eh_in_progress(hba);
3820 spin_unlock_irqrestore(hba->host->host_lock, flags);
3821
3822 if (ret)
3823 dev_err(hba->dev, "%s: link recovery failed, err %d",
3824 __func__, ret);
3825
3826 return ret;
3827}
3828
87d0b4a6 3829static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3830{
87d0b4a6 3831 int ret;
57d104c1 3832 struct uic_command uic_cmd = {0};
911a0771 3833 ktime_t start = ktime_get();
57d104c1 3834
ee32c909
KK		 3835 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3836
57d104c1 3837 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3838 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3839 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3840 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3841
53c12d0e 3842 if (ret) {
87d0b4a6
YG		 3843 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3844 __func__, ret);
3845
53c12d0e
YG		 3846 /*
3847 * If link recovery fails then return error so that caller
3848 * don't retry the hibern8 enter again.
3849 */
3850 if (ufshcd_link_recovery(hba))
3851 ret = -ENOLINK;
ee32c909
KK		 3852 } else
3853 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3854 POST_CHANGE);
53c12d0e 3855
87d0b4a6
YG		 3856 return ret;
3857}
3858
3859static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3860{
3861 int ret = 0, retries;
57d104c1 3862
87d0b4a6
YG		 3863 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3864 ret = __ufshcd_uic_hibern8_enter(hba);
3865 if (!ret || ret == -ENOLINK)
3866 goto out;
3867 }
3868out:
3869 return ret;
57d104c1
SJ		 3870}
3871
3872static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3873{
3874 struct uic_command uic_cmd = {0};
3875 int ret;
911a0771 3876 ktime_t start = ktime_get();
57d104c1 3877
ee32c909
KK		 3878 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3879
57d104c1
SJ		 3880 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3881 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3882 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3883 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3884
57d104c1 3885 if (ret) {
53c12d0e
YG		 3886 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3887 __func__, ret);
3888 ret = ufshcd_link_recovery(hba);
ff8e20c6 3889 } else {
ee32c909
KK		 3890 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3891 POST_CHANGE);
ff8e20c6
DR		 3892 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3893 hba->ufs_stats.hibern8_exit_cnt++;
3894 }
57d104c1
SJ		 3895
3896 return ret;
3897}
3898
ad448378
AH		 3899static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3900{
3901 unsigned long flags;
3902
3903 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
3904 return;
3905
3906 spin_lock_irqsave(hba->host->host_lock, flags);
3907 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3908 spin_unlock_irqrestore(hba->host->host_lock, flags);
3909}
3910
5064636c
YG		 3911 /**
3912 * ufshcd_init_pwr_info - setting the POR (power on reset)
3913 * values in hba power info
3914 * @hba: per-adapter instance
3915 */
3916static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3917{
3918 hba->pwr_info.gear_rx = UFS_PWM_G1;
3919 hba->pwr_info.gear_tx = UFS_PWM_G1;
3920 hba->pwr_info.lane_rx = 1;
3921 hba->pwr_info.lane_tx = 1;
3922 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3923 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3924 hba->pwr_info.hs_rate = 0;
3925}
3926
d3e89bac 3927/**
7eb584db
DR		 3928 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3929 * @hba: per-adapter instance
d3e89bac 3930 */
7eb584db 3931static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3932{
7eb584db
DR		 3933 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3934
3935 if (hba->max_pwr_info.is_valid)
3936 return 0;
3937
2349b533 3938 pwr_info->pwr_tx = FAST_MODE;
3939 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3940 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3941
3942 /* Get the connected lane count */
7eb584db
DR		 3943 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3944 &pwr_info->lane_rx);
3945 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3946 &pwr_info->lane_tx);
3947
3948 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3949 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3950 __func__,
3951 pwr_info->lane_rx,
3952 pwr_info->lane_tx);
3953 return -EINVAL;
3954 }
d3e89bac
SJ		 3955
3956 /*
3957 * First, get the maximum gears of HS speed.
3958 * If a zero value, it means there is no HSGEAR capability.
3959 * Then, get the maximum gears of PWM speed.
3960 */
7eb584db
DR		 3961 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3962 if (!pwr_info->gear_rx) {
3963 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3964 &pwr_info->gear_rx);
3965 if (!pwr_info->gear_rx) {
3966 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3967 __func__, pwr_info->gear_rx);
3968 return -EINVAL;
3969 }
2349b533 3970 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3971 }
3972
7eb584db
DR		 3973 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3974 &pwr_info->gear_tx);
3975 if (!pwr_info->gear_tx) {
d3e89bac 3976 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3977 &pwr_info->gear_tx);
3978 if (!pwr_info->gear_tx) {
3979 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3980 __func__, pwr_info->gear_tx);
3981 return -EINVAL;
3982 }
2349b533 3983 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3984 }
3985
3986 hba->max_pwr_info.is_valid = true;
3987 return 0;
3988}
3989
3990static int ufshcd_change_power_mode(struct ufs_hba *hba,
3991 struct ufs_pa_layer_attr *pwr_mode)
3992{
3993 int ret;
3994
3995 /* if already configured to the requested pwr_mode */
3996 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3997 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3998 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3999 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4000 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4001 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4002 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4003 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4004 return 0;
d3e89bac
SJ		 4005 }
4006
4007 /*
4008 * Configure attributes for power mode change with below.
4009 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4010 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4011 * - PA_HSSERIES
4012 */
7eb584db
DR		 4013 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4014 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4015 pwr_mode->lane_rx);
4016 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4017 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4018 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4019 else
4020 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4021
7eb584db
DR		 4022 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4023 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4024 pwr_mode->lane_tx);
4025 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4026 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4027 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4028 else
4029 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4030
7eb584db
DR		 4031 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4032 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4033 pwr_mode->pwr_rx == FAST_MODE ||
4034 pwr_mode->pwr_tx == FAST_MODE)
4035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4036 pwr_mode->hs_rate);
d3e89bac 4037
7eb584db
DR		 4038 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4039 | pwr_mode->pwr_tx);
4040
4041 if (ret) {
d3e89bac 4042 dev_err(hba->dev,
7eb584db
DR		 4043 "%s: power mode change failed %d\n", __func__, ret);
4044 } else {
0263bcd0
YG		 4045 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4046 pwr_mode);
7eb584db
DR		 4047
4048 memcpy(&hba->pwr_info, pwr_mode,
4049 sizeof(struct ufs_pa_layer_attr));
4050 }
4051
4052 return ret;
4053}
4054
4055/**
4056 * ufshcd_config_pwr_mode - configure a new power mode
4057 * @hba: per-adapter instance
4058 * @desired_pwr_mode: desired power configuration
4059 */
0d846e70 4060int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4061 struct ufs_pa_layer_attr *desired_pwr_mode)
4062{
4063 struct ufs_pa_layer_attr final_params = { 0 };
4064 int ret;
4065
0263bcd0
YG		 4066 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4067 desired_pwr_mode, &final_params);
4068
4069 if (ret)
7eb584db
DR		 4070 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4071
4072 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5 4073 if (!ret)
4074 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 4075
4076 return ret;
4077}
0d846e70 4078EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4079
68078d5c
DR		 4080/**
4081 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4082 * @hba: per-adapter instance
68078d5c
DR		 4083 *
4084 * Set fDeviceInit flag and poll until device toggles it.
4085 */
4086static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4087{
dc3c8d3a
YG		 4088 int i;
4089 int err;
68078d5c
DR		 4090 bool flag_res = 1;
4091
dc3c8d3a
YG		 4092 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4093 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4094 if (err) {
4095 dev_err(hba->dev,
4096 "%s setting fDeviceInit flag failed with error %d\n",
4097 __func__, err);
4098 goto out;
4099 }
4100
dc3c8d3a
YG		 4101 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4102 for (i = 0; i < 1000 && !err && flag_res; i++)
4103 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4104 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4105
68078d5c
DR		 4106 if (err)
4107 dev_err(hba->dev,
4108 "%s reading fDeviceInit flag failed with error %d\n",
4109 __func__, err);
4110 else if (flag_res)
4111 dev_err(hba->dev,
4112 "%s fDeviceInit was not cleared by the device\n",
4113 __func__);
4114
4115out:
4116 return err;
4117}
4118
7a3e97b0
SY		 4119/**
4120 * ufshcd_make_hba_operational - Make UFS controller operational
4121 * @hba: per adapter instance
4122 *
4123 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4124 * 1. Enable required interrupts
4125 * 2. Configure interrupt aggregation
897efe62 4126 * 3. Program UTRL and UTMRL base address
5c0c28a8 4127 * 4. Configure run-stop-registers
7a3e97b0
SY		 4128 *
4129 * Returns 0 on success, non-zero value on failure
4130 */
4131static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4132{
4133 int err = 0;
4134 u32 reg;
4135
6ccf44fe
SJ		 4136 /* Enable required interrupts */
4137 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4138
4139 /* Configure interrupt aggregation */
b852190e
YG		 4140 if (ufshcd_is_intr_aggr_allowed(hba))
4141 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4142 else
4143 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4144
4145 /* Configure UTRL and UTMRL base address registers */
4146 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4147 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4148 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4149 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4150 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4151 REG_UTP_TASK_REQ_LIST_BASE_L);
4152 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4153 REG_UTP_TASK_REQ_LIST_BASE_H);
4154
897efe62
YG		 4155 /*
4156 * Make sure base address and interrupt setup are updated before
4157 * enabling the run/stop registers below.
4158 */
4159 wmb();
4160
7a3e97b0
SY		 4161 /*
4162 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4163 */
5c0c28a8 4164 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4165 if (!(ufshcd_get_lists_status(reg))) {
4166 ufshcd_enable_run_stop_reg(hba);
4167 } else {
3b1d0580 4168 dev_err(hba->dev,
7a3e97b0
SY		 4169 "Host controller not ready to process requests");
4170 err = -EIO;
4171 goto out;
4172 }
4173
7a3e97b0
SY		 4174out:
4175 return err;
4176}
4177
596585a2
YG		 4178/**
4179 * ufshcd_hba_stop - Send controller to reset state
4180 * @hba: per adapter instance
4181 * @can_sleep: perform sleep or just spin
4182 */
4183static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4184{
4185 int err;
4186
4187 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4188 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4189 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4190 10, 1, can_sleep);
4191 if (err)
4192 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4193}
4194
7a3e97b0 4195/**
4404c5de 4196 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4197 * @hba: per adapter instance
4198 *
4199 * The controller resets itself and controller firmware initialization
4200 * sequence kicks off. When controller is ready it will set
4201 * the Host Controller Enable bit to 1.
4202 *
4203 * Returns 0 on success, non-zero value on failure
4204 */
4404c5de 4205static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0
SY		 4206{
4207 int retry;
4208
4209 /*
4210 * msleep of 1 and 5 used in this function might result in msleep(20),
4211 * but it was necessary to send the UFS FPGA to reset mode during
4212 * development and testing of this driver. msleep can be changed to
4213 * mdelay and retry count can be reduced based on the controller.
4214 */
596585a2 4215 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4216 /* change controller state to "reset state" */
596585a2 4217 ufshcd_hba_stop(hba, true);
7a3e97b0 4218
57d104c1
SJ		 4219 /* UniPro link is disabled at this point */
4220 ufshcd_set_link_off(hba);
4221
0263bcd0 4222 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4223
7a3e97b0
SY		 4224 /* start controller initialization sequence */
4225 ufshcd_hba_start(hba);
4226
4227 /*
4228 * To initialize a UFS host controller HCE bit must be set to 1.
4229 * During initialization the HCE bit value changes from 1->0->1.
4230 * When the host controller completes initialization sequence
4231 * it sets the value of HCE bit to 1. The same HCE bit is read back
4232 * to check if the controller has completed initialization sequence.
4233 * So without this delay the value HCE = 1, set in the previous
4234 * instruction might be read back.
4235 * This delay can be changed based on the controller.
4236 */
4237 msleep(1);
4238
4239 /* wait for the host controller to complete initialization */
4240 retry = 10;
4241 while (ufshcd_is_hba_active(hba)) {
4242 if (retry) {
4243 retry--;
4244 } else {
3b1d0580 4245 dev_err(hba->dev,
7a3e97b0
SY		 4246 "Controller enable failed\n");
4247 return -EIO;
4248 }
4249 msleep(5);
4250 }
5c0c28a8 4251
1d337ec2 4252 /* enable UIC related interrupts */
57d104c1 4253 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4254
0263bcd0 4255 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4256
7a3e97b0
SY		 4257 return 0;
4258}
4259
4404c5de
AA		 4260static int ufshcd_hba_enable(struct ufs_hba *hba)
4261{
4262 int ret;
4263
4264 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4265 ufshcd_set_link_off(hba);
4266 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4267
4268 /* enable UIC related interrupts */
4269 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4270 ret = ufshcd_dme_reset(hba);
4271 if (!ret) {
4272 ret = ufshcd_dme_enable(hba);
4273 if (!ret)
4274 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4275 if (ret)
4276 dev_err(hba->dev,
4277 "Host controller enable failed with non-hce\n");
4278 }
4279 } else {
4280 ret = ufshcd_hba_execute_hce(hba);
4281 }
4282
4283 return ret;
4284}
7ca38cf3
YG		 4285static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4286{
4287 int tx_lanes, i, err = 0;
4288
4289 if (!peer)
4290 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4291 &tx_lanes);
4292 else
4293 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4294 &tx_lanes);
4295 for (i = 0; i < tx_lanes; i++) {
4296 if (!peer)
4297 err = ufshcd_dme_set(hba,
4298 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4299 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4300 0);
4301 else
4302 err = ufshcd_dme_peer_set(hba,
4303 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4304 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4305 0);
4306 if (err) {
4307 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4308 __func__, peer, i, err);
4309 break;
4310 }
4311 }
4312
4313 return err;
4314}
4315
4316static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4317{
4318 return ufshcd_disable_tx_lcc(hba, true);
4319}
4320
7a3e97b0 4321/**
6ccf44fe 4322 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4323 * @hba: per adapter instance
4324 *
6ccf44fe 4325 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4326 */
6ccf44fe 4327static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4328{
6ccf44fe 4329 int ret;
1d337ec2 4330 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4331 bool link_startup_again = false;
7a3e97b0 4332
7caf489b 4333 /*
4334 * If UFS device isn't active then we will have to issue link startup
4335 * 2 times to make sure the device state move to active.
4336 */
4337 if (!ufshcd_is_ufs_dev_active(hba))
4338 link_startup_again = true;
7a3e97b0 4339
7caf489b 4340link_startup:
1d337ec2 4341 do {
0263bcd0 4342 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4343
1d337ec2 4344 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4345
1d337ec2
SRT		 4346 /* check if device is detected by inter-connect layer */
4347 if (!ret && !ufshcd_is_device_present(hba)) {
4348 dev_err(hba->dev, "%s: Device not present\n", __func__);
4349 ret = -ENXIO;
4350 goto out;
4351 }
6ccf44fe 4352
1d337ec2
SRT		 4353 /*
4354 * DME link lost indication is only received when link is up,
4355 * but we can't be sure if the link is up until link startup
4356 * succeeds. So reset the local Uni-Pro and try again.
4357 */
4358 if (ret && ufshcd_hba_enable(hba))
4359 goto out;
4360 } while (ret && retries--);
4361
4362 if (ret)
4363 /* failed to get the link up... retire */
5c0c28a8 4364 goto out;
5c0c28a8 4365
7caf489b 4366 if (link_startup_again) {
4367 link_startup_again = false;
4368 retries = DME_LINKSTARTUP_RETRIES;
4369 goto link_startup;
4370 }
4371
d2aebb9b 4372 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4373 ufshcd_init_pwr_info(hba);
4374 ufshcd_print_pwr_info(hba);
4375
7ca38cf3
YG		 4376 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4377 ret = ufshcd_disable_device_tx_lcc(hba);
4378 if (ret)
4379 goto out;
4380 }
4381
5c0c28a8 4382 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4383 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4384 if (ret)
4385 goto out;
7a3e97b0 4386
5c0c28a8 4387 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4388out:
7942f7b5 4389 if (ret) {
6ccf44fe 4390 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4391 ufshcd_print_host_state(hba);
4392 ufshcd_print_pwr_info(hba);
4393 ufshcd_print_host_regs(hba);
4394 }
6ccf44fe 4395 return ret;
7a3e97b0
SY		 4396}
4397
5a0b0cb9
SRT		 4398/**
4399 * ufshcd_verify_dev_init() - Verify device initialization
4400 * @hba: per-adapter instance
4401 *
4402 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4403 * device Transport Protocol (UTP) layer is ready after a reset.
4404 * If the UTP layer at the device side is not initialized, it may
4405 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4406 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4407 */
4408static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4409{
4410 int err = 0;
4411 int retries;
4412
1ab27c9c 4413 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4414 mutex_lock(&hba->dev_cmd.lock);
4415 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4416 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4417 NOP_OUT_TIMEOUT);
4418
4419 if (!err || err == -ETIMEDOUT)
4420 break;
4421
4422 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4423 }
4424 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4425 ufshcd_release(hba);
5a0b0cb9
SRT		 4426
4427 if (err)
4428 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4429 return err;
4430}
4431
0ce147d4
SJ		 4432/**
4433 * ufshcd_set_queue_depth - set lun queue depth
4434 * @sdev: pointer to SCSI device
4435 *
4436 * Read bLUQueueDepth value and activate scsi tagged command
4437 * queueing. For WLUN, queue depth is set to 1. For best-effort
4438 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4439 * value that host can queue.
4440 */
4441static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4442{
4443 int ret = 0;
4444 u8 lun_qdepth;
4445 struct ufs_hba *hba;
4446
4447 hba = shost_priv(sdev->host);
4448
4449 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4450 ret = ufshcd_read_unit_desc_param(hba,
4451 ufshcd_scsi_to_upiu_lun(sdev->lun),
4452 UNIT_DESC_PARAM_LU_Q_DEPTH,
4453 &lun_qdepth,
4454 sizeof(lun_qdepth));
0ce147d4
SJ		 4455
4456 /* Some WLUN doesn't support unit descriptor */
4457 if (ret == -EOPNOTSUPP)
4458 lun_qdepth = 1;
4459 else if (!lun_qdepth)
4460 /* eventually, we can figure out the real queue depth */
4461 lun_qdepth = hba->nutrs;
4462 else
4463 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4464
4465 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4466 __func__, lun_qdepth);
db5ed4df 4467 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4468}
4469
57d104c1
SJ		 4470/*
4471 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4472 * @hba: per-adapter instance
4473 * @lun: UFS device lun id
4474 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4475 *
4476 * Returns 0 in case of success and b_lu_write_protect status would be returned
4477 * @b_lu_write_protect parameter.
4478 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4479 * Returns -EINVAL in case of invalid parameters passed to this function.
4480 */
4481static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4482 u8 lun,
4483 u8 *b_lu_write_protect)
4484{
4485 int ret;
4486
4487 if (!b_lu_write_protect)
4488 ret = -EINVAL;
4489 /*
4490 * According to UFS device spec, RPMB LU can't be write
4491 * protected so skip reading bLUWriteProtect parameter for
4492 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4493 */
4494 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4495 ret = -ENOTSUPP;
4496 else
4497 ret = ufshcd_read_unit_desc_param(hba,
4498 lun,
4499 UNIT_DESC_PARAM_LU_WR_PROTECT,
4500 b_lu_write_protect,
4501 sizeof(*b_lu_write_protect));
4502 return ret;
4503}
4504
4505/**
4506 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4507 * status
4508 * @hba: per-adapter instance
4509 * @sdev: pointer to SCSI device
4510 *
4511 */
4512static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4513 struct scsi_device *sdev)
4514{
4515 if (hba->dev_info.f_power_on_wp_en &&
4516 !hba->dev_info.is_lu_power_on_wp) {
4517 u8 b_lu_write_protect;
4518
4519 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4520 &b_lu_write_protect) &&
4521 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4522 hba->dev_info.is_lu_power_on_wp = true;
4523 }
4524}
4525
7a3e97b0
SY		 4526/**
4527 * ufshcd_slave_alloc - handle initial SCSI device configurations
4528 * @sdev: pointer to SCSI device
4529 *
4530 * Returns success
4531 */
4532static int ufshcd_slave_alloc(struct scsi_device *sdev)
4533{
4534 struct ufs_hba *hba;
4535
4536 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4537
4538 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4539 sdev->use_10_for_ms = 1;
7a3e97b0 4540
e8e7f271
SRT		 4541 /* allow SCSI layer to restart the device in case of errors */
4542 sdev->allow_restart = 1;
4264fd61 4543
b2a6c522
SRT		 4544 /* REPORT SUPPORTED OPERATION CODES is not supported */
4545 sdev->no_report_opcodes = 1;
4546
84af7e8b
SRT		 4547 /* WRITE_SAME command is not supported */
4548 sdev->no_write_same = 1;
e8e7f271 4549
0ce147d4 4550 ufshcd_set_queue_depth(sdev);
4264fd61 4551
57d104c1
SJ		 4552 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4553
7a3e97b0
SY		 4554 return 0;
4555}
4556
4264fd61
SRT		 4557/**
4558 * ufshcd_change_queue_depth - change queue depth
4559 * @sdev: pointer to SCSI device
4560 * @depth: required depth to set
4264fd61 4561 *
db5ed4df 4562 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4563 */
db5ed4df 4564static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4565{
4566 struct ufs_hba *hba = shost_priv(sdev->host);
4567
4568 if (depth > hba->nutrs)
4569 depth = hba->nutrs;
db5ed4df 4570 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4571}
4572
eeda4749
AM		 4573/**
4574 * ufshcd_slave_configure - adjust SCSI device configurations
4575 * @sdev: pointer to SCSI device
4576 */
4577static int ufshcd_slave_configure(struct scsi_device *sdev)
4578{
4579 struct request_queue *q = sdev->request_queue;
4580
4581 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4582 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4583
4584 return 0;
4585}
4586
7a3e97b0
SY		 4587/**
4588 * ufshcd_slave_destroy - remove SCSI device configurations
4589 * @sdev: pointer to SCSI device
4590 */
4591static void ufshcd_slave_destroy(struct scsi_device *sdev)
4592{
4593 struct ufs_hba *hba;
4594
4595 hba = shost_priv(sdev->host);
0ce147d4 4596 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4597 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4598 unsigned long flags;
4599
4600 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4601 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4602 spin_unlock_irqrestore(hba->host->host_lock, flags);
4603 }
7a3e97b0
SY		 4604}
4605
7a3e97b0
SY		 4606/**
4607 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4608 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4609 * @scsi_status: SCSI command status
4610 *
4611 * Returns value base on SCSI command status
4612 */
4613static inline int
4614ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4615{
4616 int result = 0;
4617
4618 switch (scsi_status) {
7a3e97b0 4619 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4620 ufshcd_copy_sense_data(lrbp);
4621 case SAM_STAT_GOOD:
7a3e97b0
SY		 4622 result |= DID_OK << 16 |
4623 COMMAND_COMPLETE << 8 |
1c2623c5 4624 scsi_status;
7a3e97b0
SY		 4625 break;
4626 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4627 case SAM_STAT_BUSY:
7a3e97b0 4628 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4629 ufshcd_copy_sense_data(lrbp);
4630 result |= scsi_status;
7a3e97b0
SY		 4631 break;
4632 default:
4633 result |= DID_ERROR << 16;
4634 break;
4635 } /* end of switch */
4636
4637 return result;
4638}
4639
4640/**
4641 * ufshcd_transfer_rsp_status - Get overall status of the response
4642 * @hba: per adapter instance
8aa29f19 4643 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4644 *
4645 * Returns result of the command to notify SCSI midlayer
4646 */
4647static inline int
4648ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4649{
4650 int result = 0;
4651 int scsi_status;
4652 int ocs;
4653
4654 /* overall command status of utrd */
4655 ocs = ufshcd_get_tr_ocs(lrbp);
4656
4657 switch (ocs) {
4658 case OCS_SUCCESS:
5a0b0cb9 4659 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4660 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4661 switch (result) {
4662 case UPIU_TRANSACTION_RESPONSE:
4663 /*
4664 * get the response UPIU result to extract
4665 * the SCSI command status
4666 */
4667 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4668
4669 /*
4670 * get the result based on SCSI status response
4671 * to notify the SCSI midlayer of the command status
4672 */
4673 scsi_status = result & MASK_SCSI_STATUS;
4674 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4675
f05ac2e5
YG		 4676 /*
4677 * Currently we are only supporting BKOPs exception
4678 * events hence we can ignore BKOPs exception event
4679 * during power management callbacks. BKOPs exception
4680 * event is not expected to be raised in runtime suspend
4681 * callback as it allows the urgent bkops.
4682 * During system suspend, we are anyway forcefully
4683 * disabling the bkops and if urgent bkops is needed
4684 * it will be enabled on system resume. Long term
4685 * solution could be to abort the system suspend if
4686 * UFS device needs urgent BKOPs.
4687 */
4688 if (!hba->pm_op_in_progress &&
4689 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4690 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4691 break;
4692 case UPIU_TRANSACTION_REJECT_UPIU:
4693 /* TODO: handle Reject UPIU Response */
4694 result = DID_ERROR << 16;
3b1d0580 4695 dev_err(hba->dev,
5a0b0cb9
SRT		 4696 "Reject UPIU not fully implemented\n");
4697 break;
4698 default:
4699 result = DID_ERROR << 16;
4700 dev_err(hba->dev,
4701 "Unexpected request response code = %x\n",
4702 result);
7a3e97b0
SY		 4703 break;
4704 }
7a3e97b0
SY		 4705 break;
4706 case OCS_ABORTED:
4707 result |= DID_ABORT << 16;
4708 break;
e8e7f271
SRT		 4709 case OCS_INVALID_COMMAND_STATUS:
4710 result |= DID_REQUEUE << 16;
4711 break;
7a3e97b0
SY		 4712 case OCS_INVALID_CMD_TABLE_ATTR:
4713 case OCS_INVALID_PRDT_ATTR:
4714 case OCS_MISMATCH_DATA_BUF_SIZE:
4715 case OCS_MISMATCH_RESP_UPIU_SIZE:
4716 case OCS_PEER_COMM_FAILURE:
4717 case OCS_FATAL_ERROR:
4718 default:
4719 result |= DID_ERROR << 16;
3b1d0580 4720 dev_err(hba->dev,
ff8e20c6
DR		 4721 "OCS error from controller = %x for tag %d\n",
4722 ocs, lrbp->task_tag);
4723 ufshcd_print_host_regs(hba);
6ba65588 4724 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4725 break;
4726 } /* end of switch */
4727
66cc820f
DR		 4728 if (host_byte(result) != DID_OK)
4729 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4730 return result;
4731}
4732
6ccf44fe
SJ		 4733/**
4734 * ufshcd_uic_cmd_compl - handle completion of uic command
4735 * @hba: per adapter instance
53b3d9c3 4736 * @intr_status: interrupt status generated by the controller
6ccf44fe 4737 */
53b3d9c3 4738static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4739{
53b3d9c3 4740 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4741 hba->active_uic_cmd->argument2 |=
4742 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4743 hba->active_uic_cmd->argument3 =
4744 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4745 complete(&hba->active_uic_cmd->done);
4746 }
53b3d9c3 4747
57d104c1
SJ		 4748 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4749 complete(hba->uic_async_done);
6ccf44fe
SJ		 4750}
4751
7a3e97b0 4752/**
9a47ec7c 4753 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4754 * @hba: per adapter instance
9a47ec7c 4755 * @completed_reqs: requests to complete
7a3e97b0 4756 */
9a47ec7c
YG		 4757static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4758 unsigned long completed_reqs)
7a3e97b0 4759{
5a0b0cb9
SRT		 4760 struct ufshcd_lrb *lrbp;
4761 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4762 int result;
4763 int index;
e9d501b1 4764
e9d501b1
DR		 4765 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4766 lrbp = &hba->lrb[index];
4767 cmd = lrbp->cmd;
4768 if (cmd) {
1a07f2d9 4769 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4770 result = ufshcd_transfer_rsp_status(hba, lrbp);
4771 scsi_dma_unmap(cmd);
4772 cmd->result = result;
4773 /* Mark completed command as NULL in LRB */
4774 lrbp->cmd = NULL;
4775 clear_bit_unlock(index, &hba->lrb_in_use);
4776 /* Do not touch lrbp after scsi done */
4777 cmd->scsi_done(cmd);
1ab27c9c 4778 __ufshcd_release(hba);
300bb13f
JP		 4779 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4780 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4781 if (hba->dev_cmd.complete) {
4782 ufshcd_add_command_trace(hba, index,
4783 "dev_complete");
e9d501b1 4784 complete(hba->dev_cmd.complete);
1a07f2d9 4785 }
e9d501b1 4786 }
401f1e44 4787 if (ufshcd_is_clkscaling_supported(hba))
4788 hba->clk_scaling.active_reqs--;
09017188
ZL		 4789
4790 lrbp->compl_time_stamp = ktime_get();
e9d501b1 4791 }
7a3e97b0
SY		 4792
4793 /* clear corresponding bits of completed commands */
4794 hba->outstanding_reqs ^= completed_reqs;
4795
856b3483
ST		 4796 ufshcd_clk_scaling_update_busy(hba);
4797
5a0b0cb9
SRT		 4798 /* we might have free'd some tags above */
4799 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4800}
4801
9a47ec7c
YG		 4802/**
4803 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4804 * @hba: per adapter instance
4805 */
4806static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4807{
4808 unsigned long completed_reqs;
4809 u32 tr_doorbell;
4810
4811 /* Resetting interrupt aggregation counters first and reading the
4812 * DOOR_BELL afterward allows us to handle all the completed requests.
4813 * In order to prevent other interrupts starvation the DB is read once
4814 * after reset. The down side of this solution is the possibility of
4815 * false interrupt if device completes another request after resetting
4816 * aggregation and before reading the DB.
4817 */
5ac6abc9
AA		 4818 if (ufshcd_is_intr_aggr_allowed(hba) &&
4819 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 4820 ufshcd_reset_intr_aggr(hba);
4821
4822 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4823 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4824
4825 __ufshcd_transfer_req_compl(hba, completed_reqs);
4826}
4827
66ec6d59
SRT		 4828/**
4829 * ufshcd_disable_ee - disable exception event
4830 * @hba: per-adapter instance
4831 * @mask: exception event to disable
4832 *
4833 * Disables exception event in the device so that the EVENT_ALERT
4834 * bit is not set.
4835 *
4836 * Returns zero on success, non-zero error value on failure.
4837 */
4838static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4839{
4840 int err = 0;
4841 u32 val;
4842
4843 if (!(hba->ee_ctrl_mask & mask))
4844 goto out;
4845
4846 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4847 val &= MASK_EE_STATUS;
5e86ae44 4848 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4849 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4850 if (!err)
4851 hba->ee_ctrl_mask &= ~mask;
4852out:
4853 return err;
4854}
4855
4856/**
4857 * ufshcd_enable_ee - enable exception event
4858 * @hba: per-adapter instance
4859 * @mask: exception event to enable
4860 *
4861 * Enable corresponding exception event in the device to allow
4862 * device to alert host in critical scenarios.
4863 *
4864 * Returns zero on success, non-zero error value on failure.
4865 */
4866static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4867{
4868 int err = 0;
4869 u32 val;
4870
4871 if (hba->ee_ctrl_mask & mask)
4872 goto out;
4873
4874 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4875 val &= MASK_EE_STATUS;
5e86ae44 4876 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4877 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4878 if (!err)
4879 hba->ee_ctrl_mask |= mask;
4880out:
4881 return err;
4882}
4883
4884/**
4885 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4886 * @hba: per-adapter instance
4887 *
4888 * Allow device to manage background operations on its own. Enabling
4889 * this might lead to inconsistent latencies during normal data transfers
4890 * as the device is allowed to manage its own way of handling background
4891 * operations.
4892 *
4893 * Returns zero on success, non-zero on failure.
4894 */
4895static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4896{
4897 int err = 0;
4898
4899 if (hba->auto_bkops_enabled)
4900 goto out;
4901
dc3c8d3a 4902 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4903 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4904 if (err) {
4905 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4906 __func__, err);
4907 goto out;
4908 }
4909
4910 hba->auto_bkops_enabled = true;
7ff5ab47 4911 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4912
4913 /* No need of URGENT_BKOPS exception from the device */
4914 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4915 if (err)
4916 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4917 __func__, err);
4918out:
4919 return err;
4920}
4921
4922/**
4923 * ufshcd_disable_auto_bkops - block device in doing background operations
4924 * @hba: per-adapter instance
4925 *
4926 * Disabling background operations improves command response latency but
4927 * has drawback of device moving into critical state where the device is
4928 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4929 * host is idle so that BKOPS are managed effectively without any negative
4930 * impacts.
4931 *
4932 * Returns zero on success, non-zero on failure.
4933 */
4934static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4935{
4936 int err = 0;
4937
4938 if (!hba->auto_bkops_enabled)
4939 goto out;
4940
4941 /*
4942 * If host assisted BKOPs is to be enabled, make sure
4943 * urgent bkops exception is allowed.
4944 */
4945 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4946 if (err) {
4947 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4948 __func__, err);
4949 goto out;
4950 }
4951
dc3c8d3a 4952 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4953 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4954 if (err) {
4955 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4956 __func__, err);
4957 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4958 goto out;
4959 }
4960
4961 hba->auto_bkops_enabled = false;
7ff5ab47 4962 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4963out:
4964 return err;
4965}
4966
4967/**
4e768e76 4968 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4969 * @hba: per adapter instance
4970 *
4971 * After a device reset the device may toggle the BKOPS_EN flag
4972 * to default value. The s/w tracking variables should be updated
4e768e76 4973 * as well. This function would change the auto-bkops state based on
4974 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4975 */
4e768e76 4976static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4977{
4e768e76 4978 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4979 hba->auto_bkops_enabled = false;
4980 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4981 ufshcd_enable_auto_bkops(hba);
4982 } else {
4983 hba->auto_bkops_enabled = true;
4984 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4985 ufshcd_disable_auto_bkops(hba);
4986 }
66ec6d59
SRT		 4987}
4988
4989static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4990{
5e86ae44 4991 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4992 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4993}
4994
4995/**
57d104c1 4996 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4997 * @hba: per-adapter instance
57d104c1 4998 * @status: bkops_status value
66ec6d59 4999 *
57d104c1
SJ		 5000 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5001 * flag in the device to permit background operations if the device
5002 * bkops_status is greater than or equal to "status" argument passed to
5003 * this function, disable otherwise.
5004 *
5005 * Returns 0 for success, non-zero in case of failure.
5006 *
5007 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5008 * to know whether auto bkops is enabled or disabled after this function
5009 * returns control to it.
66ec6d59 5010 */
57d104c1
SJ		 5011static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5012 enum bkops_status status)
66ec6d59
SRT		 5013{
5014 int err;
57d104c1 5015 u32 curr_status = 0;
66ec6d59 5016
57d104c1 5017 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5018 if (err) {
5019 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5020 __func__, err);
5021 goto out;
57d104c1
SJ		 5022 } else if (curr_status > BKOPS_STATUS_MAX) {
5023 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5024 __func__, curr_status);
5025 err = -EINVAL;
5026 goto out;
66ec6d59
SRT		 5027 }
5028
57d104c1 5029 if (curr_status >= status)
66ec6d59 5030 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5031 else
5032 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5033out:
5034 return err;
5035}
5036
57d104c1
SJ		 5037/**
5038 * ufshcd_urgent_bkops - handle urgent bkops exception event
5039 * @hba: per-adapter instance
5040 *
5041 * Enable fBackgroundOpsEn flag in the device to permit background
5042 * operations.
5043 *
5044 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5045 * and negative error value for any other failure.
5046 */
5047static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5048{
afdfff59 5049 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5050}
5051
66ec6d59
SRT		 5052static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5053{
5e86ae44 5054 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5055 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5056}
5057
afdfff59
YG		 5058static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5059{
5060 int err;
5061 u32 curr_status = 0;
5062
5063 if (hba->is_urgent_bkops_lvl_checked)
5064 goto enable_auto_bkops;
5065
5066 err = ufshcd_get_bkops_status(hba, &curr_status);
5067 if (err) {
5068 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5069 __func__, err);
5070 goto out;
5071 }
5072
5073 /*
5074 * We are seeing that some devices are raising the urgent bkops
5075 * exception events even when BKOPS status doesn't indicate performace
5076 * impacted or critical. Handle these device by determining their urgent
5077 * bkops status at runtime.
5078 */
5079 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5080 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5081 __func__, curr_status);
5082 /* update the current status as the urgent bkops level */
5083 hba->urgent_bkops_lvl = curr_status;
5084 hba->is_urgent_bkops_lvl_checked = true;
5085 }
5086
5087enable_auto_bkops:
5088 err = ufshcd_enable_auto_bkops(hba);
5089out:
5090 if (err < 0)
5091 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5092 __func__, err);
5093}
5094
66ec6d59
SRT		 5095/**
5096 * ufshcd_exception_event_handler - handle exceptions raised by device
5097 * @work: pointer to work data
5098 *
5099 * Read bExceptionEventStatus attribute from the device and handle the
5100 * exception event accordingly.
5101 */
5102static void ufshcd_exception_event_handler(struct work_struct *work)
5103{
5104 struct ufs_hba *hba;
5105 int err;
5106 u32 status = 0;
5107 hba = container_of(work, struct ufs_hba, eeh_work);
5108
62694735 5109 pm_runtime_get_sync(hba->dev);
2e3611e9 5110 scsi_block_requests(hba->host);
66ec6d59
SRT		 5111 err = ufshcd_get_ee_status(hba, &status);
5112 if (err) {
5113 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5114 __func__, err);
5115 goto out;
5116 }
5117
5118 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5119
5120 if (status & MASK_EE_URGENT_BKOPS)
5121 ufshcd_bkops_exception_event_handler(hba);
5122
66ec6d59 5123out:
2e3611e9 5124 scsi_unblock_requests(hba->host);
62694735 5125 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5126 return;
5127}
5128
9a47ec7c
YG		 5129/* Complete requests that have door-bell cleared */
5130static void ufshcd_complete_requests(struct ufs_hba *hba)
5131{
5132 ufshcd_transfer_req_compl(hba);
5133 ufshcd_tmc_handler(hba);
5134}
5135
583fa62d
YG		 5136/**
5137 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5138 * to recover from the DL NAC errors or not.
5139 * @hba: per-adapter instance
5140 *
5141 * Returns true if error handling is required, false otherwise
5142 */
5143static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5144{
5145 unsigned long flags;
5146 bool err_handling = true;
5147
5148 spin_lock_irqsave(hba->host->host_lock, flags);
5149 /*
5150 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5151 * device fatal error and/or DL NAC & REPLAY timeout errors.
5152 */
5153 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5154 goto out;
5155
5156 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5157 ((hba->saved_err & UIC_ERROR) &&
5158 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5159 goto out;
5160
5161 if ((hba->saved_err & UIC_ERROR) &&
5162 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5163 int err;
5164 /*
5165 * wait for 50ms to see if we can get any other errors or not.
5166 */
5167 spin_unlock_irqrestore(hba->host->host_lock, flags);
5168 msleep(50);
5169 spin_lock_irqsave(hba->host->host_lock, flags);
5170
5171 /*
5172 * now check if we have got any other severe errors other than
5173 * DL NAC error?
5174 */
5175 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5176 ((hba->saved_err & UIC_ERROR) &&
5177 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5178 goto out;
5179
5180 /*
5181 * As DL NAC is the only error received so far, send out NOP
5182 * command to confirm if link is still active or not.
5183 * - If we don't get any response then do error recovery.
5184 * - If we get response then clear the DL NAC error bit.
5185 */
5186
5187 spin_unlock_irqrestore(hba->host->host_lock, flags);
5188 err = ufshcd_verify_dev_init(hba);
5189 spin_lock_irqsave(hba->host->host_lock, flags);
5190
5191 if (err)
5192 goto out;
5193
5194 /* Link seems to be alive hence ignore the DL NAC errors */
5195 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5196 hba->saved_err &= ~UIC_ERROR;
5197 /* clear NAC error */
5198 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5199 if (!hba->saved_uic_err) {
5200 err_handling = false;
5201 goto out;
5202 }
5203 }
5204out:
5205 spin_unlock_irqrestore(hba->host->host_lock, flags);
5206 return err_handling;
5207}
5208
7a3e97b0 5209/**
e8e7f271
SRT		 5210 * ufshcd_err_handler - handle UFS errors that require s/w attention
5211 * @work: pointer to work structure
7a3e97b0 5212 */
e8e7f271 5213static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5214{
5215 struct ufs_hba *hba;
e8e7f271
SRT		 5216 unsigned long flags;
5217 u32 err_xfer = 0;
5218 u32 err_tm = 0;
5219 int err = 0;
5220 int tag;
9a47ec7c 5221 bool needs_reset = false;
e8e7f271
SRT		 5222
5223 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5224
62694735 5225 pm_runtime_get_sync(hba->dev);
1ab27c9c 5226 ufshcd_hold(hba, false);
e8e7f271
SRT		 5227
5228 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5229 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5230 goto out;
e8e7f271
SRT		 5231
5232 hba->ufshcd_state = UFSHCD_STATE_RESET;
5233 ufshcd_set_eh_in_progress(hba);
5234
5235 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5236 ufshcd_complete_requests(hba);
583fa62d
YG		 5237
5238 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5239 bool ret;
5240
5241 spin_unlock_irqrestore(hba->host->host_lock, flags);
5242 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5243 ret = ufshcd_quirk_dl_nac_errors(hba);
5244 spin_lock_irqsave(hba->host->host_lock, flags);
5245 if (!ret)
5246 goto skip_err_handling;
5247 }
9a47ec7c
YG		 5248 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5249 ((hba->saved_err & UIC_ERROR) &&
5250 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5251 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5252 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5253 needs_reset = true;
e8e7f271 5254
9a47ec7c
YG		 5255 /*
5256 * if host reset is required then skip clearing the pending
5257 * transfers forcefully because they will automatically get
5258 * cleared after link startup.
5259 */
5260 if (needs_reset)
5261 goto skip_pending_xfer_clear;
5262
5263 /* release lock as clear command might sleep */
5264 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5265 /* Clear pending transfer requests */
9a47ec7c
YG		 5266 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5267 if (ufshcd_clear_cmd(hba, tag)) {
5268 err_xfer = true;
5269 goto lock_skip_pending_xfer_clear;
5270 }
5271 }
e8e7f271
SRT		 5272
5273 /* Clear pending task management requests */
9a47ec7c
YG		 5274 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5275 if (ufshcd_clear_tm_cmd(hba, tag)) {
5276 err_tm = true;
5277 goto lock_skip_pending_xfer_clear;
5278 }
5279 }
e8e7f271 5280
9a47ec7c 5281lock_skip_pending_xfer_clear:
e8e7f271 5282 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5283
9a47ec7c
YG		 5284 /* Complete the requests that are cleared by s/w */
5285 ufshcd_complete_requests(hba);
5286
5287 if (err_xfer || err_tm)
5288 needs_reset = true;
5289
5290skip_pending_xfer_clear:
e8e7f271 5291 /* Fatal errors need reset */
9a47ec7c
YG		 5292 if (needs_reset) {
5293 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5294
5295 /*
5296 * ufshcd_reset_and_restore() does the link reinitialization
5297 * which will need atleast one empty doorbell slot to send the
5298 * device management commands (NOP and query commands).
5299 * If there is no slot empty at this moment then free up last
5300 * slot forcefully.
5301 */
5302 if (hba->outstanding_reqs == max_doorbells)
5303 __ufshcd_transfer_req_compl(hba,
5304 (1UL << (hba->nutrs - 1)));
5305
5306 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5307 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5308 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5309 if (err) {
5310 dev_err(hba->dev, "%s: reset and restore failed\n",
5311 __func__);
5312 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5313 }
5314 /*
5315 * Inform scsi mid-layer that we did reset and allow to handle
5316 * Unit Attention properly.
5317 */
5318 scsi_report_bus_reset(hba->host, 0);
5319 hba->saved_err = 0;
5320 hba->saved_uic_err = 0;
5321 }
9a47ec7c 5322
583fa62d 5323skip_err_handling:
9a47ec7c
YG		 5324 if (!needs_reset) {
5325 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5326 if (hba->saved_err || hba->saved_uic_err)
5327 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5328 __func__, hba->saved_err, hba->saved_uic_err);
5329 }
5330
e8e7f271
SRT		 5331 ufshcd_clear_eh_in_progress(hba);
5332
5333out:
9a47ec7c 5334 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5335 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5336 ufshcd_release(hba);
62694735 5337 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5338}
5339
ff8e20c6
DR		 5340static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5341 u32 reg)
5342{
5343 reg_hist->reg[reg_hist->pos] = reg;
5344 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5345 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5346}
5347
7a3e97b0 5348/**
e8e7f271
SRT		 5349 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5350 * @hba: per-adapter instance
7a3e97b0 5351 */
e8e7f271 5352static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5353{
5354 u32 reg;
5355
fb7b45f0
DR		 5356 /* PHY layer lane error */
5357 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5358 /* Ignore LINERESET indication, as this is not an error */
5359 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5360 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5361 /*
5362 * To know whether this error is fatal or not, DB timeout
5363 * must be checked but this error is handled separately.
5364 */
5365 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5366 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5367 }
fb7b45f0 5368
e8e7f271
SRT		 5369 /* PA_INIT_ERROR is fatal and needs UIC reset */
5370 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5371 if (reg)
5372 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5373
e8e7f271
SRT		 5374 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5375 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5376 else if (hba->dev_quirks &
5377 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5378 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5379 hba->uic_error |=
5380 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5381 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5382 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5383 }
e8e7f271
SRT		 5384
5385 /* UIC NL/TL/DME errors needs software retry */
5386 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5387 if (reg) {
5388 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5389 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5390 }
e8e7f271
SRT		 5391
5392 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5393 if (reg) {
5394 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5395 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5396 }
e8e7f271
SRT		 5397
5398 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5399 if (reg) {
5400 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5401 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5402 }
e8e7f271
SRT		 5403
5404 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5405 __func__, hba->uic_error);
5406}
5407
5408/**
5409 * ufshcd_check_errors - Check for errors that need s/w attention
5410 * @hba: per-adapter instance
5411 */
5412static void ufshcd_check_errors(struct ufs_hba *hba)
5413{
5414 bool queue_eh_work = false;
5415
7a3e97b0 5416 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5417 queue_eh_work = true;
7a3e97b0
SY		 5418
5419 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5420 hba->uic_error = 0;
5421 ufshcd_update_uic_error(hba);
5422 if (hba->uic_error)
5423 queue_eh_work = true;
7a3e97b0 5424 }
e8e7f271
SRT		 5425
5426 if (queue_eh_work) {
9a47ec7c
YG		 5427 /*
5428 * update the transfer error masks to sticky bits, let's do this
5429 * irrespective of current ufshcd_state.
5430 */
5431 hba->saved_err |= hba->errors;
5432 hba->saved_uic_err |= hba->uic_error;
5433
e8e7f271
SRT		 5434 /* handle fatal errors only when link is functional */
5435 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5436 /* block commands from scsi mid-layer */
38135535 5437 ufshcd_scsi_block_requests(hba);
e8e7f271 5438
141f8165 5439 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5440
5441 /* dump controller state before resetting */
5442 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5443 bool pr_prdt = !!(hba->saved_err &
5444 SYSTEM_BUS_FATAL_ERROR);
5445
5446 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5447 __func__, hba->saved_err,
5448 hba->saved_uic_err);
5449
5450 ufshcd_print_host_regs(hba);
5451 ufshcd_print_pwr_info(hba);
5452 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5453 ufshcd_print_trs(hba, hba->outstanding_reqs,
5454 pr_prdt);
5455 }
e8e7f271
SRT		 5456 schedule_work(&hba->eh_work);
5457 }
3441da7d 5458 }
e8e7f271
SRT		 5459 /*
5460 * if (!queue_eh_work) -
5461 * Other errors are either non-fatal where host recovers
5462 * itself without s/w intervention or errors that will be
5463 * handled by the SCSI core layer.
5464 */
7a3e97b0
SY		 5465}
5466
5467/**
5468 * ufshcd_tmc_handler - handle task management function completion
5469 * @hba: per adapter instance
5470 */
5471static void ufshcd_tmc_handler(struct ufs_hba *hba)
5472{
5473 u32 tm_doorbell;
5474
b873a275 5475 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5476 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5477 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5478}
5479
5480/**
5481 * ufshcd_sl_intr - Interrupt service routine
5482 * @hba: per adapter instance
5483 * @intr_status: contains interrupts generated by the controller
5484 */
5485static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5486{
5487 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5488 if (hba->errors)
e8e7f271 5489 ufshcd_check_errors(hba);
7a3e97b0 5490
53b3d9c3
SJ		 5491 if (intr_status & UFSHCD_UIC_MASK)
5492 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5493
5494 if (intr_status & UTP_TASK_REQ_COMPL)
5495 ufshcd_tmc_handler(hba);
5496
5497 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5498 ufshcd_transfer_req_compl(hba);
5499}
5500
5501/**
5502 * ufshcd_intr - Main interrupt service routine
5503 * @irq: irq number
5504 * @__hba: pointer to adapter instance
5505 *
5506 * Returns IRQ_HANDLED - If interrupt is valid
5507 * IRQ_NONE - If invalid interrupt
5508 */
5509static irqreturn_t ufshcd_intr(int irq, void *__hba)
5510{
d75f7fe4 5511 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5512 irqreturn_t retval = IRQ_NONE;
5513 struct ufs_hba *hba = __hba;
7f6ba4f1 5514 int retries = hba->nutrs;
7a3e97b0
SY		 5515
5516 spin_lock(hba->host->host_lock);
b873a275 5517 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5518
7f6ba4f1
VG		 5519 /*
5520 * There could be max of hba->nutrs reqs in flight and in worst case
5521 * if the reqs get finished 1 by 1 after the interrupt status is
5522 * read, make sure we handle them by checking the interrupt status
5523 * again in a loop until we process all of the reqs before returning.
5524 */
5525 do {
5526 enabled_intr_status =
5527 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5528 if (intr_status)
5529 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5530 if (enabled_intr_status) {
5531 ufshcd_sl_intr(hba, enabled_intr_status);
5532 retval = IRQ_HANDLED;
5533 }
5534
5535 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5536 } while (intr_status && --retries);
d75f7fe4 5537
7a3e97b0
SY		 5538 spin_unlock(hba->host->host_lock);
5539 return retval;
5540}
5541
e2933132
SRT		 5542static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5543{
5544 int err = 0;
5545 u32 mask = 1 << tag;
5546 unsigned long flags;
5547
5548 if (!test_bit(tag, &hba->outstanding_tasks))
5549 goto out;
5550
5551 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5552 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5553 spin_unlock_irqrestore(hba->host->host_lock, flags);
5554
5555 /* poll for max. 1 sec to clear door bell register by h/w */
5556 err = ufshcd_wait_for_register(hba,
5557 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5558 mask, 0, 1000, 1000, true);
e2933132
SRT		 5559out:
5560 return err;
5561}
5562
c6049cd9
CH		 5563static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5564 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5565{
c6049cd9 5566 struct Scsi_Host *host = hba->host;
7a3e97b0 5567 unsigned long flags;
c6049cd9 5568 int free_slot, task_tag, err;
7a3e97b0 5569
e2933132
SRT		 5570 /*
5571 * Get free slot, sleep if slots are unavailable.
5572 * Even though we use wait_event() which sleeps indefinitely,
5573 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5574 */
5575 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5576 ufshcd_hold(hba, false);
7a3e97b0 5577
e2933132 5578 spin_lock_irqsave(host->host_lock, flags);
e2933132 5579 task_tag = hba->nutrs + free_slot;
7a3e97b0 5580
c6049cd9
CH		 5581 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5582
5583 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5584 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5585
7a3e97b0
SY		 5586 /* send command to the controller */
5587 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5588
5589 /* Make sure descriptors are ready before ringing the task doorbell */
5590 wmb();
5591
b873a275 5592 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5593 /* Make sure that doorbell is committed immediately */
5594 wmb();
7a3e97b0
SY		 5595
5596 spin_unlock_irqrestore(host->host_lock, flags);
5597
6667e6d9
OS		 5598 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5599
7a3e97b0 5600 /* wait until the task management command is completed */
e2933132
SRT		 5601 err = wait_event_timeout(hba->tm_wq,
5602 test_bit(free_slot, &hba->tm_condition),
5603 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5604 if (!err) {
6667e6d9 5605 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5606 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5607 __func__, tm_function);
5608 if (ufshcd_clear_tm_cmd(hba, free_slot))
5609 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5610 __func__, free_slot);
5611 err = -ETIMEDOUT;
5612 } else {
c6049cd9
CH		 5613 err = 0;
5614 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5615
6667e6d9 5616 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
c6049cd9
CH		 5617
5618 spin_lock_irqsave(hba->host->host_lock, flags);
5619 __clear_bit(free_slot, &hba->outstanding_tasks);
5620 spin_unlock_irqrestore(hba->host->host_lock, flags);
5621
7a3e97b0 5622 }
e2933132 5623
7a3e97b0 5624 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5625 ufshcd_put_tm_slot(hba, free_slot);
5626 wake_up(&hba->tm_tag_wq);
5627
1ab27c9c 5628 ufshcd_release(hba);
7a3e97b0
SY		 5629 return err;
5630}
5631
c6049cd9
CH		 5632/**
5633 * ufshcd_issue_tm_cmd - issues task management commands to controller
5634 * @hba: per adapter instance
5635 * @lun_id: LUN ID to which TM command is sent
5636 * @task_id: task ID to which the TM command is applicable
5637 * @tm_function: task management function opcode
5638 * @tm_response: task management service response return value
5639 *
5640 * Returns non-zero value on error, zero on success.
5641 */
5642static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5643 u8 tm_function, u8 *tm_response)
5644{
5645 struct utp_task_req_desc treq = { { 0 }, };
5646 int ocs_value, err;
5647
5648 /* Configure task request descriptor */
5649 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5650 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5651
5652 /* Configure task request UPIU */
5653 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5654 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5655 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5656
5657 /*
5658 * The host shall provide the same value for LUN field in the basic
5659 * header and for Input Parameter.
5660 */
5661 treq.input_param1 = cpu_to_be32(lun_id);
5662 treq.input_param2 = cpu_to_be32(task_id);
5663
5664 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5665 if (err == -ETIMEDOUT)
5666 return err;
5667
5668 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5669 if (ocs_value != OCS_SUCCESS)
5670 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5671 __func__, ocs_value);
5672 else if (tm_response)
5673 *tm_response = be32_to_cpu(treq.output_param1) &
5674 MASK_TM_SERVICE_RESP;
5675 return err;
5676}
5677
7a3e97b0 5678/**
3441da7d
SRT		 5679 * ufshcd_eh_device_reset_handler - device reset handler registered to
5680 * scsi layer.
7a3e97b0
SY		 5681 * @cmd: SCSI command pointer
5682 *
5683 * Returns SUCCESS/FAILED
5684 */
3441da7d 5685static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5686{
5687 struct Scsi_Host *host;
5688 struct ufs_hba *hba;
5689 unsigned int tag;
5690 u32 pos;
5691 int err;
e2933132
SRT		 5692 u8 resp = 0xF;
5693 struct ufshcd_lrb *lrbp;
3441da7d 5694 unsigned long flags;
7a3e97b0
SY		 5695
5696 host = cmd->device->host;
5697 hba = shost_priv(host);
5698 tag = cmd->request->tag;
5699
e2933132
SRT		 5700 lrbp = &hba->lrb[tag];
5701 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5702 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5703 if (!err)
5704 err = resp;
7a3e97b0 5705 goto out;
e2933132 5706 }
7a3e97b0 5707
3441da7d
SRT		 5708 /* clear the commands that were pending for corresponding LUN */
5709 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5710 if (hba->lrb[pos].lun == lrbp->lun) {
5711 err = ufshcd_clear_cmd(hba, pos);
5712 if (err)
5713 break;
7a3e97b0 5714 }
3441da7d
SRT		 5715 }
5716 spin_lock_irqsave(host->host_lock, flags);
5717 ufshcd_transfer_req_compl(hba);
5718 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5719
7a3e97b0 5720out:
7fabb77b 5721 hba->req_abort_count = 0;
3441da7d
SRT		 5722 if (!err) {
5723 err = SUCCESS;
5724 } else {
5725 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5726 err = FAILED;
5727 }
7a3e97b0
SY		 5728 return err;
5729}
5730
e0b299e3
GB		 5731static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5732{
5733 struct ufshcd_lrb *lrbp;
5734 int tag;
5735
5736 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5737 lrbp = &hba->lrb[tag];
5738 lrbp->req_abort_skip = true;
5739 }
5740}
5741
7a3e97b0
SY		 5742/**
5743 * ufshcd_abort - abort a specific command
5744 * @cmd: SCSI command pointer
5745 *
f20810d8
SRT		 5746 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5747 * command, and in host controller by clearing the door-bell register. There can
5748 * be race between controller sending the command to the device while abort is
5749 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5750 * really issued and then try to abort it.
5751 *
7a3e97b0
SY		 5752 * Returns SUCCESS/FAILED
5753 */
5754static int ufshcd_abort(struct scsi_cmnd *cmd)
5755{
5756 struct Scsi_Host *host;
5757 struct ufs_hba *hba;
5758 unsigned long flags;
5759 unsigned int tag;
f20810d8
SRT		 5760 int err = 0;
5761 int poll_cnt;
e2933132
SRT		 5762 u8 resp = 0xF;
5763 struct ufshcd_lrb *lrbp;
e9d501b1 5764 u32 reg;
7a3e97b0
SY		 5765
5766 host = cmd->device->host;
5767 hba = shost_priv(host);
5768 tag = cmd->request->tag;
e7d38257 5769 lrbp = &hba->lrb[tag];
14497328
YG		 5770 if (!ufshcd_valid_tag(hba, tag)) {
5771 dev_err(hba->dev,
5772 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5773 __func__, tag, cmd, cmd->request);
5774 BUG();
5775 }
7a3e97b0 5776
e7d38257
DR		 5777 /*
5778 * Task abort to the device W-LUN is illegal. When this command
5779 * will fail, due to spec violation, scsi err handling next step
5780 * will be to send LU reset which, again, is a spec violation.
5781 * To avoid these unnecessary/illegal step we skip to the last error
5782 * handling stage: reset and restore.
5783 */
5784 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5785 return ufshcd_eh_host_reset_handler(cmd);
5786
1ab27c9c 5787 ufshcd_hold(hba, false);
14497328 5788 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5789 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5790 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5791 dev_err(hba->dev,
5792 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5793 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5794 goto out;
14497328 5795 }
7a3e97b0 5796
e9d501b1
DR		 5797 if (!(reg & (1 << tag))) {
5798 dev_err(hba->dev,
5799 "%s: cmd was completed, but without a notifying intr, tag = %d",
5800 __func__, tag);
5801 }
5802
66cc820f
DR		 5803 /* Print Transfer Request of aborted task */
5804 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5805
7fabb77b
GB		 5806 /*
5807 * Print detailed info about aborted request.
5808 * As more than one request might get aborted at the same time,
5809 * print full information only for the first aborted request in order
5810 * to reduce repeated printouts. For other aborted requests only print
5811 * basic details.
5812 */
5813 scsi_print_command(hba->lrb[tag].cmd);
5814 if (!hba->req_abort_count) {
5815 ufshcd_print_host_regs(hba);
6ba65588 5816 ufshcd_print_host_state(hba);
7fabb77b
GB		 5817 ufshcd_print_pwr_info(hba);
5818 ufshcd_print_trs(hba, 1 << tag, true);
5819 } else {
5820 ufshcd_print_trs(hba, 1 << tag, false);
5821 }
5822 hba->req_abort_count++;
e0b299e3
GB		 5823
5824 /* Skip task abort in case previous aborts failed and report failure */
5825 if (lrbp->req_abort_skip) {
5826 err = -EIO;
5827 goto out;
5828 }
5829
f20810d8
SRT		 5830 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5831 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5832 UFS_QUERY_TASK, &resp);
5833 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5834 /* cmd pending in the device */
ff8e20c6
DR		 5835 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5836 __func__, tag);
f20810d8
SRT		 5837 break;
5838 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5839 /*
5840 * cmd not pending in the device, check if it is
5841 * in transition.
5842 */
ff8e20c6
DR		 5843 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5844 __func__, tag);
f20810d8
SRT		 5845 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5846 if (reg & (1 << tag)) {
5847 /* sleep for max. 200us to stabilize */
5848 usleep_range(100, 200);
5849 continue;
5850 }
5851 /* command completed already */
ff8e20c6
DR		 5852 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5853 __func__, tag);
f20810d8
SRT		 5854 goto out;
5855 } else {
ff8e20c6
DR		 5856 dev_err(hba->dev,
5857 "%s: no response from device. tag = %d, err %d\n",
5858 __func__, tag, err);
f20810d8
SRT		 5859 if (!err)
5860 err = resp; /* service response error */
5861 goto out;
5862 }
5863 }
5864
5865 if (!poll_cnt) {
5866 err = -EBUSY;
7a3e97b0
SY		 5867 goto out;
5868 }
7a3e97b0 5869
e2933132
SRT		 5870 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5871 UFS_ABORT_TASK, &resp);
5872 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5873 if (!err) {
f20810d8 5874 err = resp; /* service response error */
ff8e20c6
DR		 5875 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5876 __func__, tag, err);
5877 }
7a3e97b0 5878 goto out;
e2933132 5879 }
7a3e97b0 5880
f20810d8 5881 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5882 if (err) {
5883 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5884 __func__, tag, err);
f20810d8 5885 goto out;
ff8e20c6 5886 }
f20810d8 5887
7a3e97b0
SY		 5888 scsi_dma_unmap(cmd);
5889
5890 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5891 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5892 hba->lrb[tag].cmd = NULL;
5893 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5894
5895 clear_bit_unlock(tag, &hba->lrb_in_use);
5896 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5897
7a3e97b0 5898out:
f20810d8
SRT		 5899 if (!err) {
5900 err = SUCCESS;
5901 } else {
5902 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5903 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5904 err = FAILED;
5905 }
5906
1ab27c9c
ST		 5907 /*
5908 * This ufshcd_release() corresponds to the original scsi cmd that got
5909 * aborted here (as we won't get any IRQ for it).
5910 */
5911 ufshcd_release(hba);
7a3e97b0
SY		 5912 return err;
5913}
5914
3441da7d
SRT		 5915/**
5916 * ufshcd_host_reset_and_restore - reset and restore host controller
5917 * @hba: per-adapter instance
5918 *
5919 * Note that host controller reset may issue DME_RESET to
5920 * local and remote (device) Uni-Pro stack and the attributes
5921 * are reset to default state.
5922 *
5923 * Returns zero on success, non-zero on failure
5924 */
5925static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5926{
5927 int err;
3441da7d
SRT		 5928 unsigned long flags;
5929
5930 /* Reset the host controller */
5931 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5932 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5933 spin_unlock_irqrestore(hba->host->host_lock, flags);
5934
a3cd5ec5 5935 /* scale up clocks to max frequency before full reinitialization */
5936 ufshcd_scale_clks(hba, true);
5937
3441da7d
SRT		 5938 err = ufshcd_hba_enable(hba);
5939 if (err)
5940 goto out;
5941
5942 /* Establish the link again and restore the device */
1d337ec2
SRT		 5943 err = ufshcd_probe_hba(hba);
5944
5945 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5946 err = -EIO;
5947out:
5948 if (err)
5949 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5950
5951 return err;
5952}
5953
5954/**
5955 * ufshcd_reset_and_restore - reset and re-initialize host/device
5956 * @hba: per-adapter instance
5957 *
5958 * Reset and recover device, host and re-establish link. This
5959 * is helpful to recover the communication in fatal error conditions.
5960 *
5961 * Returns zero on success, non-zero on failure
5962 */
5963static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5964{
5965 int err = 0;
5966 unsigned long flags;
1d337ec2 5967 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5968
1d337ec2
SRT		 5969 do {
5970 err = ufshcd_host_reset_and_restore(hba);
5971 } while (err && --retries);
3441da7d
SRT		 5972
5973 /*
5974 * After reset the door-bell might be cleared, complete
5975 * outstanding requests in s/w here.
5976 */
5977 spin_lock_irqsave(hba->host->host_lock, flags);
5978 ufshcd_transfer_req_compl(hba);
5979 ufshcd_tmc_handler(hba);
5980 spin_unlock_irqrestore(hba->host->host_lock, flags);
5981
5982 return err;
5983}
5984
5985/**
5986 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 5987 * @cmd: SCSI command pointer
3441da7d
SRT		 5988 *
5989 * Returns SUCCESS/FAILED
5990 */
5991static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5992{
5993 int err;
5994 unsigned long flags;
5995 struct ufs_hba *hba;
5996
5997 hba = shost_priv(cmd->device->host);
5998
1ab27c9c 5999 ufshcd_hold(hba, false);
3441da7d
SRT		 6000 /*
6001 * Check if there is any race with fatal error handling.
6002 * If so, wait for it to complete. Even though fatal error
6003 * handling does reset and restore in some cases, don't assume
6004 * anything out of it. We are just avoiding race here.
6005 */
6006 do {
6007 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6008 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6009 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6010 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6011 break;
6012 spin_unlock_irqrestore(hba->host->host_lock, flags);
6013 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6014 flush_work(&hba->eh_work);
3441da7d
SRT		 6015 } while (1);
6016
6017 hba->ufshcd_state = UFSHCD_STATE_RESET;
6018 ufshcd_set_eh_in_progress(hba);
6019 spin_unlock_irqrestore(hba->host->host_lock, flags);
6020
6021 err = ufshcd_reset_and_restore(hba);
6022
6023 spin_lock_irqsave(hba->host->host_lock, flags);
6024 if (!err) {
6025 err = SUCCESS;
6026 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6027 } else {
6028 err = FAILED;
6029 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6030 }
6031 ufshcd_clear_eh_in_progress(hba);
6032 spin_unlock_irqrestore(hba->host->host_lock, flags);
6033
1ab27c9c 6034 ufshcd_release(hba);
3441da7d
SRT		 6035 return err;
6036}
6037
3a4bf06d
YG		 6038/**
6039 * ufshcd_get_max_icc_level - calculate the ICC level
6040 * @sup_curr_uA: max. current supported by the regulator
6041 * @start_scan: row at the desc table to start scan from
6042 * @buff: power descriptor buffer
6043 *
6044 * Returns calculated max ICC level for specific regulator
6045 */
6046static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6047{
6048 int i;
6049 int curr_uA;
6050 u16 data;
6051 u16 unit;
6052
6053 for (i = start_scan; i >= 0; i--) {
d79713f9 6054 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6055 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6056 ATTR_ICC_LVL_UNIT_OFFSET;
6057 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6058 switch (unit) {
6059 case UFSHCD_NANO_AMP:
6060 curr_uA = curr_uA / 1000;
6061 break;
6062 case UFSHCD_MILI_AMP:
6063 curr_uA = curr_uA * 1000;
6064 break;
6065 case UFSHCD_AMP:
6066 curr_uA = curr_uA * 1000 * 1000;
6067 break;
6068 case UFSHCD_MICRO_AMP:
6069 default:
6070 break;
6071 }
6072 if (sup_curr_uA >= curr_uA)
6073 break;
6074 }
6075 if (i < 0) {
6076 i = 0;
6077 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6078 }
6079
6080 return (u32)i;
6081}
6082
6083/**
6084 * ufshcd_calc_icc_level - calculate the max ICC level
6085 * In case regulators are not initialized we'll return 0
6086 * @hba: per-adapter instance
6087 * @desc_buf: power descriptor buffer to extract ICC levels from.
6088 * @len: length of desc_buff
6089 *
6090 * Returns calculated ICC level
6091 */
6092static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6093 u8 *desc_buf, int len)
6094{
6095 u32 icc_level = 0;
6096
6097 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6098 !hba->vreg_info.vccq2) {
6099 dev_err(hba->dev,
6100 "%s: Regulator capability was not set, actvIccLevel=%d",
6101 __func__, icc_level);
6102 goto out;
6103 }
6104
6105 if (hba->vreg_info.vcc)
6106 icc_level = ufshcd_get_max_icc_level(
6107 hba->vreg_info.vcc->max_uA,
6108 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6109 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6110
6111 if (hba->vreg_info.vccq)
6112 icc_level = ufshcd_get_max_icc_level(
6113 hba->vreg_info.vccq->max_uA,
6114 icc_level,
6115 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6116
6117 if (hba->vreg_info.vccq2)
6118 icc_level = ufshcd_get_max_icc_level(
6119 hba->vreg_info.vccq2->max_uA,
6120 icc_level,
6121 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6122out:
6123 return icc_level;
6124}
6125
6126static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6127{
6128 int ret;
a4b0e8a4 6129 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a
KC		 6130 u8 *desc_buf;
6131
6132 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6133 if (!desc_buf)
6134 return;
3a4bf06d
YG		 6135
6136 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6137 if (ret) {
6138 dev_err(hba->dev,
6139 "%s: Failed reading power descriptor.len = %d ret = %d",
6140 __func__, buff_len, ret);
bbe21d7a 6141 goto out;
3a4bf06d
YG		 6142 }
6143
6144 hba->init_prefetch_data.icc_level =
6145 ufshcd_find_max_sup_active_icc_level(hba,
6146 desc_buf, buff_len);
6147 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6148 __func__, hba->init_prefetch_data.icc_level);
6149
dbd34a61
SM		 6150 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6151 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6152 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6153
6154 if (ret)
6155 dev_err(hba->dev,
6156 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6157 __func__, hba->init_prefetch_data.icc_level , ret);
6158
bbe21d7a
KC		 6159out:
6160 kfree(desc_buf);
3a4bf06d
YG		 6161}
6162
2a8fa600
SJ		 6163/**
6164 * ufshcd_scsi_add_wlus - Adds required W-LUs
6165 * @hba: per-adapter instance
6166 *
6167 * UFS device specification requires the UFS devices to support 4 well known
6168 * logical units:
6169 * "REPORT_LUNS" (address: 01h)
6170 * "UFS Device" (address: 50h)
6171 * "RPMB" (address: 44h)
6172 * "BOOT" (address: 30h)
6173 * UFS device's power management needs to be controlled by "POWER CONDITION"
6174 * field of SSU (START STOP UNIT) command. But this "power condition" field
6175 * will take effect only when its sent to "UFS device" well known logical unit
6176 * hence we require the scsi_device instance to represent this logical unit in
6177 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6178 *
2a8fa600
SJ		 6179 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6180 * Block) LU so user space process can control this LU. User space may also
6181 * want to have access to BOOT LU.
8aa29f19 6182 *
2a8fa600
SJ		 6183 * This function adds scsi device instances for each of all well known LUs
6184 * (except "REPORT LUNS" LU).
6185 *
6186 * Returns zero on success (all required W-LUs are added successfully),
6187 * non-zero error value on failure (if failed to add any of the required W-LU).
6188 */
6189static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6190{
6191 int ret = 0;
7c48bfd0
AM		 6192 struct scsi_device *sdev_rpmb;
6193 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6194
6195 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6196 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6197 if (IS_ERR(hba->sdev_ufs_device)) {
6198 ret = PTR_ERR(hba->sdev_ufs_device);
6199 hba->sdev_ufs_device = NULL;
6200 goto out;
6201 }
7c48bfd0 6202 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6203
7c48bfd0 6204 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6205 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6206 if (IS_ERR(sdev_rpmb)) {
6207 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6208 goto remove_sdev_ufs_device;
2a8fa600 6209 }
7c48bfd0 6210 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6211
6212 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6213 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6214 if (IS_ERR(sdev_boot))
6215 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6216 else
6217 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6218 goto out;
6219
2a8fa600
SJ		 6220remove_sdev_ufs_device:
6221 scsi_remove_device(hba->sdev_ufs_device);
6222out:
6223 return ret;
6224}
6225
93fdd5ac
TW		 6226static int ufs_get_device_desc(struct ufs_hba *hba,
6227 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6228{
6229 int err;
bbe21d7a 6230 size_t buff_len;
c58ab7aa 6231 u8 model_index;
bbe21d7a
KC		 6232 u8 *desc_buf;
6233
6234 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6235 QUERY_DESC_MAX_SIZE + 1);
6236 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6237 if (!desc_buf) {
6238 err = -ENOMEM;
6239 goto out;
6240 }
c58ab7aa 6241
a4b0e8a4 6242 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6243 if (err) {
6244 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6245 __func__, err);
6246 goto out;
6247 }
6248
6249 /*
6250 * getting vendor (manufacturerID) and Bank Index in big endian
6251 * format
6252 */
93fdd5ac 6253 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6254 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6255
6256 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6257
bbe21d7a
KC		 6258 /* Zero-pad entire buffer for string termination. */
6259 memset(desc_buf, 0, buff_len);
6260
6261 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
8aa29f19 6262 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
c58ab7aa
YG		 6263 if (err) {
6264 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6265 __func__, err);
6266 goto out;
6267 }
6268
bbe21d7a
KC		 6269 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
6270 strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
6271 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
c58ab7aa
YG		 6272 MAX_MODEL_LEN));
6273
6274 /* Null terminate the model string */
93fdd5ac 6275 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6276
6277out:
bbe21d7a 6278 kfree(desc_buf);
c58ab7aa
YG		 6279 return err;
6280}
6281
93fdd5ac
TW		 6282static void ufs_fixup_device_setup(struct ufs_hba *hba,
6283 struct ufs_dev_desc *dev_desc)
c58ab7aa 6284{
c58ab7aa 6285 struct ufs_dev_fix *f;
c58ab7aa
YG		 6286
6287 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6288 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6289 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6290 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6291 !strcmp(f->card.model, UFS_ANY_MODEL)))
6292 hba->dev_quirks |= f->quirk;
6293 }
6294}
6295
37113106
YG		 6296/**
6297 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6298 * @hba: per-adapter instance
6299 *
6300 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6301 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6302 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6303 * the hibern8 exit latency.
6304 *
6305 * Returns zero on success, non-zero error value on failure.
6306 */
6307static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6308{
6309 int ret = 0;
6310 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6311
6312 ret = ufshcd_dme_peer_get(hba,
6313 UIC_ARG_MIB_SEL(
6314 RX_MIN_ACTIVATETIME_CAPABILITY,
6315 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6316 &peer_rx_min_activatetime);
6317 if (ret)
6318 goto out;
6319
6320 /* make sure proper unit conversion is applied */
6321 tuned_pa_tactivate =
6322 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6323 / PA_TACTIVATE_TIME_UNIT_US);
6324 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6325 tuned_pa_tactivate);
6326
6327out:
6328 return ret;
6329}
6330
6331/**
6332 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6333 * @hba: per-adapter instance
6334 *
6335 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6336 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6337 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6338 * This optimal value can help reduce the hibern8 exit latency.
6339 *
6340 * Returns zero on success, non-zero error value on failure.
6341 */
6342static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6343{
6344 int ret = 0;
6345 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6346 u32 max_hibern8_time, tuned_pa_hibern8time;
6347
6348 ret = ufshcd_dme_get(hba,
6349 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6350 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6351 &local_tx_hibern8_time_cap);
6352 if (ret)
6353 goto out;
6354
6355 ret = ufshcd_dme_peer_get(hba,
6356 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6357 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6358 &peer_rx_hibern8_time_cap);
6359 if (ret)
6360 goto out;
6361
6362 max_hibern8_time = max(local_tx_hibern8_time_cap,
6363 peer_rx_hibern8_time_cap);
6364 /* make sure proper unit conversion is applied */
6365 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6366 / PA_HIBERN8_TIME_UNIT_US);
6367 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6368 tuned_pa_hibern8time);
6369out:
6370 return ret;
6371}
6372
c6a6db43 6373/**
6374 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6375 * less than device PA_TACTIVATE time.
6376 * @hba: per-adapter instance
6377 *
6378 * Some UFS devices require host PA_TACTIVATE to be lower than device
6379 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6380 * for such devices.
6381 *
6382 * Returns zero on success, non-zero error value on failure.
6383 */
6384static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6385{
6386 int ret = 0;
6387 u32 granularity, peer_granularity;
6388 u32 pa_tactivate, peer_pa_tactivate;
6389 u32 pa_tactivate_us, peer_pa_tactivate_us;
6390 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6391
6392 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6393 &granularity);
6394 if (ret)
6395 goto out;
6396
6397 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6398 &peer_granularity);
6399 if (ret)
6400 goto out;
6401
6402 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6403 (granularity > PA_GRANULARITY_MAX_VAL)) {
6404 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6405 __func__, granularity);
6406 return -EINVAL;
6407 }
6408
6409 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6410 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6411 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6412 __func__, peer_granularity);
6413 return -EINVAL;
6414 }
6415
6416 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6417 if (ret)
6418 goto out;
6419
6420 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6421 &peer_pa_tactivate);
6422 if (ret)
6423 goto out;
6424
6425 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6426 peer_pa_tactivate_us = peer_pa_tactivate *
6427 gran_to_us_table[peer_granularity - 1];
6428
6429 if (pa_tactivate_us > peer_pa_tactivate_us) {
6430 u32 new_peer_pa_tactivate;
6431
6432 new_peer_pa_tactivate = pa_tactivate_us /
6433 gran_to_us_table[peer_granularity - 1];
6434 new_peer_pa_tactivate++;
6435 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6436 new_peer_pa_tactivate);
6437 }
6438
6439out:
6440 return ret;
6441}
6442
37113106
YG		 6443static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6444{
6445 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6446 ufshcd_tune_pa_tactivate(hba);
6447 ufshcd_tune_pa_hibern8time(hba);
6448 }
6449
6450 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6451 /* set 1ms timeout for PA_TACTIVATE */
6452 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 6453
6454 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6455 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6456
6457 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6458}
6459
ff8e20c6
DR		 6460static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6461{
6462 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6463
6464 hba->ufs_stats.hibern8_exit_cnt = 0;
6465 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6466
6467 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6468 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6469 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6470 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6471 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6472
6473 hba->req_abort_count = 0;
ff8e20c6
DR		 6474}
6475
a4b0e8a4
PM		 6476static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6477{
6478 int err;
6479
6480 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6481 &hba->desc_size.dev_desc);
6482 if (err)
6483 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6484
6485 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6486 &hba->desc_size.pwr_desc);
6487 if (err)
6488 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6489
6490 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6491 &hba->desc_size.interc_desc);
6492 if (err)
6493 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6494
6495 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6496 &hba->desc_size.conf_desc);
6497 if (err)
6498 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6499
6500 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6501 &hba->desc_size.unit_desc);
6502 if (err)
6503 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6504
6505 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6506 &hba->desc_size.geom_desc);
6507 if (err)
6508 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2
SN		 6509 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6510 &hba->desc_size.hlth_desc);
6511 if (err)
6512 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6513}
6514
6515static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6516{
6517 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6518 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6519 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6520 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6521 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6522 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2 6523 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6524}
6525
6ccf44fe 6526/**
1d337ec2
SRT		 6527 * ufshcd_probe_hba - probe hba to detect device and initialize
6528 * @hba: per-adapter instance
6529 *
6530 * Execute link-startup and verify device initialization
6ccf44fe 6531 */
1d337ec2 6532static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6533{
93fdd5ac 6534 struct ufs_dev_desc card = {0};
6ccf44fe 6535 int ret;
7ff5ab47 6536 ktime_t start = ktime_get();
6ccf44fe
SJ		 6537
6538 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6539 if (ret)
6540 goto out;
6541
afdfff59
YG		 6542 /* set the default level for urgent bkops */
6543 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6544 hba->is_urgent_bkops_lvl_checked = false;
6545
ff8e20c6
DR		 6546 /* Debug counters initialization */
6547 ufshcd_clear_dbg_ufs_stats(hba);
6548
57d104c1
SJ		 6549 /* UniPro link is active now */
6550 ufshcd_set_link_active(hba);
d3e89bac 6551
ad448378
AH		 6552 /* Enable Auto-Hibernate if configured */
6553 ufshcd_auto_hibern8_enable(hba);
6554
5a0b0cb9
SRT		 6555 ret = ufshcd_verify_dev_init(hba);
6556 if (ret)
6557 goto out;
68078d5c
DR		 6558
6559 ret = ufshcd_complete_dev_init(hba);
6560 if (ret)
6561 goto out;
5a0b0cb9 6562
a4b0e8a4
PM		 6563 /* Init check for device descriptor sizes */
6564 ufshcd_init_desc_sizes(hba);
6565
93fdd5ac
TW		 6566 ret = ufs_get_device_desc(hba, &card);
6567 if (ret) {
6568 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6569 __func__, ret);
6570 goto out;
6571 }
6572
6573 ufs_fixup_device_setup(hba, &card);
37113106 6574 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6575
6576 ret = ufshcd_set_vccq_rail_unused(hba,
6577 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6578 if (ret)
6579 goto out;
6580
57d104c1
SJ		 6581 /* UFS device is also active now */
6582 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6583 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6584 hba->wlun_dev_clr_ua = true;
6585
7eb584db
DR		 6586 if (ufshcd_get_max_pwr_mode(hba)) {
6587 dev_err(hba->dev,
6588 "%s: Failed getting max supported power mode\n",
6589 __func__);
6590 } else {
6591 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6592 if (ret) {
7eb584db
DR		 6593 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6594 __func__, ret);
8643ae66
DL		 6595 goto out;
6596 }
7eb584db 6597 }
57d104c1 6598
53c12d0e
YG		 6599 /* set the state as operational after switching to desired gear */
6600 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6601
57d104c1
SJ		 6602 /*
6603 * If we are in error handling context or in power management callbacks
6604 * context, no need to scan the host
6605 */
6606 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6607 bool flag;
6608
6609 /* clear any previous UFS device information */
6610 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6611 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6612 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6613 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6614
3a4bf06d
YG		 6615 if (!hba->is_init_prefetch)
6616 ufshcd_init_icc_levels(hba);
6617
2a8fa600
SJ		 6618 /* Add required well known logical units to scsi mid layer */
6619 if (ufshcd_scsi_add_wlus(hba))
6620 goto out;
6621
0701e49d 6622 /* Initialize devfreq after UFS device is detected */
6623 if (ufshcd_is_clkscaling_supported(hba)) {
6624 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6625 &hba->pwr_info,
6626 sizeof(struct ufs_pa_layer_attr));
6627 hba->clk_scaling.saved_pwr_info.is_valid = true;
6628 if (!hba->devfreq) {
deac444f
BA		 6629 ret = ufshcd_devfreq_init(hba);
6630 if (ret)
0701e49d 6631 goto out;
0701e49d 6632 }
6633 hba->clk_scaling.is_allowed = true;
6634 }
6635
3441da7d
SRT		 6636 scsi_scan_host(hba->host);
6637 pm_runtime_put_sync(hba->dev);
6638 }
3a4bf06d
YG		 6639
6640 if (!hba->is_init_prefetch)
6641 hba->is_init_prefetch = true;
6642
5a0b0cb9 6643out:
1d337ec2
SRT		 6644 /*
6645 * If we failed to initialize the device or the device is not
6646 * present, turn off the power/clocks etc.
6647 */
57d104c1
SJ		 6648 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6649 pm_runtime_put_sync(hba->dev);
eebcc196 6650 ufshcd_exit_clk_scaling(hba);
1d337ec2 6651 ufshcd_hba_exit(hba);
57d104c1 6652 }
1d337ec2 6653
7ff5ab47 6654 trace_ufshcd_init(dev_name(hba->dev), ret,
6655 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6656 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6657 return ret;
6658}
6659
6660/**
6661 * ufshcd_async_scan - asynchronous execution for probing hba
6662 * @data: data pointer to pass to this function
6663 * @cookie: cookie data
6664 */
6665static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6666{
6667 struct ufs_hba *hba = (struct ufs_hba *)data;
6668
6669 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6670}
6671
f550c65b
YG		 6672static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6673{
6674 unsigned long flags;
6675 struct Scsi_Host *host;
6676 struct ufs_hba *hba;
6677 int index;
6678 bool found = false;
6679
6680 if (!scmd || !scmd->device || !scmd->device->host)
6600593c 6681 return BLK_EH_DONE;
f550c65b
YG		 6682
6683 host = scmd->device->host;
6684 hba = shost_priv(host);
6685 if (!hba)
6600593c 6686 return BLK_EH_DONE;
f550c65b
YG		 6687
6688 spin_lock_irqsave(host->host_lock, flags);
6689
6690 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6691 if (hba->lrb[index].cmd == scmd) {
6692 found = true;
6693 break;
6694 }
6695 }
6696
6697 spin_unlock_irqrestore(host->host_lock, flags);
6698
6699 /*
6700 * Bypass SCSI error handling and reset the block layer timer if this
6701 * SCSI command was not actually dispatched to UFS driver, otherwise
6702 * let SCSI layer handle the error as usual.
6703 */
6600593c 6704 return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
f550c65b
YG		 6705}
6706
d829fc8a
SN		 6707static const struct attribute_group *ufshcd_driver_groups[] = {
6708 &ufs_sysfs_unit_descriptor_group,
ec92b59c 6709 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 6710 NULL,
6711};
6712
7a3e97b0
SY		 6713static struct scsi_host_template ufshcd_driver_template = {
6714 .module = THIS_MODULE,
6715 .name = UFSHCD,
6716 .proc_name = UFSHCD,
6717 .queuecommand = ufshcd_queuecommand,
6718 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6719 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6720 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6721 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6722 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6723 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6724 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6725 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6726 .this_id = -1,
6727 .sg_tablesize = SG_ALL,
6728 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6729 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6730 .max_host_blocked = 1,
c40ecc12 6731 .track_queue_depth = 1,
d829fc8a 6732 .sdev_groups = ufshcd_driver_groups,
7a3e97b0
SY		 6733};
6734
57d104c1
SJ		 6735static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6736 int ua)
6737{
7b16a07c 6738 int ret;
57d104c1 6739
7b16a07c
BA		 6740 if (!vreg)
6741 return 0;
57d104c1 6742
7b16a07c
BA		 6743 ret = regulator_set_load(vreg->reg, ua);
6744 if (ret < 0) {
6745 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6746 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6747 }
6748
6749 return ret;
6750}
6751
6752static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6753 struct ufs_vreg *vreg)
6754{
60f01870
YG		 6755 if (!vreg)
6756 return 0;
6757 else if (vreg->unused)
6758 return 0;
6759 else
6760 return ufshcd_config_vreg_load(hba->dev, vreg,
6761 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6762}
6763
6764static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6765 struct ufs_vreg *vreg)
6766{
60f01870
YG		 6767 if (!vreg)
6768 return 0;
6769 else if (vreg->unused)
6770 return 0;
6771 else
6772 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6773}
6774
aa497613
SRT		 6775static int ufshcd_config_vreg(struct device *dev,
6776 struct ufs_vreg *vreg, bool on)
6777{
6778 int ret = 0;
72753590
GS		 6779 struct regulator *reg;
6780 const char *name;
aa497613
SRT		 6781 int min_uV, uA_load;
6782
6783 BUG_ON(!vreg);
6784
72753590
GS		 6785 reg = vreg->reg;
6786 name = vreg->name;
6787
aa497613
SRT		 6788 if (regulator_count_voltages(reg) > 0) {
6789 min_uV = on ? vreg->min_uV : 0;
6790 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6791 if (ret) {
6792 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6793 __func__, name, ret);
6794 goto out;
6795 }
6796
6797 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6798 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6799 if (ret)
aa497613 6800 goto out;
aa497613
SRT		 6801 }
6802out:
6803 return ret;
6804}
6805
6806static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6807{
6808 int ret = 0;
6809
60f01870
YG		 6810 if (!vreg)
6811 goto out;
6812 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6813 goto out;
6814
6815 ret = ufshcd_config_vreg(dev, vreg, true);
6816 if (!ret)
6817 ret = regulator_enable(vreg->reg);
6818
6819 if (!ret)
6820 vreg->enabled = true;
6821 else
6822 dev_err(dev, "%s: %s enable failed, err=%d\n",
6823 __func__, vreg->name, ret);
6824out:
6825 return ret;
6826}
6827
6828static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6829{
6830 int ret = 0;
6831
60f01870
YG		 6832 if (!vreg)
6833 goto out;
6834 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6835 goto out;
6836
6837 ret = regulator_disable(vreg->reg);
6838
6839 if (!ret) {
6840 /* ignore errors on applying disable config */
6841 ufshcd_config_vreg(dev, vreg, false);
6842 vreg->enabled = false;
6843 } else {
6844 dev_err(dev, "%s: %s disable failed, err=%d\n",
6845 __func__, vreg->name, ret);
6846 }
6847out:
6848 return ret;
6849}
6850
6851static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6852{
6853 int ret = 0;
6854 struct device *dev = hba->dev;
6855 struct ufs_vreg_info *info = &hba->vreg_info;
6856
6857 if (!info)
6858 goto out;
6859
6860 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6861 if (ret)
6862 goto out;
6863
6864 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6865 if (ret)
6866 goto out;
6867
6868 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6869 if (ret)
6870 goto out;
6871
6872out:
6873 if (ret) {
6874 ufshcd_toggle_vreg(dev, info->vccq2, false);
6875 ufshcd_toggle_vreg(dev, info->vccq, false);
6876 ufshcd_toggle_vreg(dev, info->vcc, false);
6877 }
6878 return ret;
6879}
6880
6a771a65
RS		 6881static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6882{
6883 struct ufs_vreg_info *info = &hba->vreg_info;
6884
6885 if (info)
6886 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6887
6888 return 0;
6889}
6890
aa497613
SRT		 6891static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6892{
6893 int ret = 0;
6894
6895 if (!vreg)
6896 goto out;
6897
6898 vreg->reg = devm_regulator_get(dev, vreg->name);
6899 if (IS_ERR(vreg->reg)) {
6900 ret = PTR_ERR(vreg->reg);
6901 dev_err(dev, "%s: %s get failed, err=%d\n",
6902 __func__, vreg->name, ret);
6903 }
6904out:
6905 return ret;
6906}
6907
6908static int ufshcd_init_vreg(struct ufs_hba *hba)
6909{
6910 int ret = 0;
6911 struct device *dev = hba->dev;
6912 struct ufs_vreg_info *info = &hba->vreg_info;
6913
6914 if (!info)
6915 goto out;
6916
6917 ret = ufshcd_get_vreg(dev, info->vcc);
6918 if (ret)
6919 goto out;
6920
6921 ret = ufshcd_get_vreg(dev, info->vccq);
6922 if (ret)
6923 goto out;
6924
6925 ret = ufshcd_get_vreg(dev, info->vccq2);
6926out:
6927 return ret;
6928}
6929
6a771a65
RS		 6930static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6931{
6932 struct ufs_vreg_info *info = &hba->vreg_info;
6933
6934 if (info)
6935 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6936
6937 return 0;
6938}
6939
60f01870
YG		 6940static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6941{
6942 int ret = 0;
6943 struct ufs_vreg_info *info = &hba->vreg_info;
6944
6945 if (!info)
6946 goto out;
6947 else if (!info->vccq)
6948 goto out;
6949
6950 if (unused) {
6951 /* shut off the rail here */
6952 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6953 /*
6954 * Mark this rail as no longer used, so it doesn't get enabled
6955 * later by mistake
6956 */
6957 if (!ret)
6958 info->vccq->unused = true;
6959 } else {
6960 /*
6961 * rail should have been already enabled hence just make sure
6962 * that unused flag is cleared.
6963 */
6964 info->vccq->unused = false;
6965 }
6966out:
6967 return ret;
6968}
6969
57d104c1
SJ		 6970static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6971 bool skip_ref_clk)
c6e79dac
SRT		 6972{
6973 int ret = 0;
6974 struct ufs_clk_info *clki;
6975 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6976 unsigned long flags;
911a0771 6977 ktime_t start = ktime_get();
6978 bool clk_state_changed = false;
c6e79dac 6979
566ec9ad 6980 if (list_empty(head))
c6e79dac
SRT		 6981 goto out;
6982
b334456e
SJ		 6983 /*
6984 * vendor specific setup_clocks ops may depend on clocks managed by
6985 * this standard driver hence call the vendor specific setup_clocks
6986 * before disabling the clocks managed here.
6987 */
6988 if (!on) {
6989 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6990 if (ret)
6991 return ret;
6992 }
1e879e8f 6993
c6e79dac
SRT		 6994 list_for_each_entry(clki, head, list) {
6995 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 6996 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6997 continue;
6998
911a0771 6999 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7000 if (on && !clki->enabled) {
7001 ret = clk_prepare_enable(clki->clk);
7002 if (ret) {
7003 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7004 __func__, clki->name, ret);
7005 goto out;
7006 }
7007 } else if (!on && clki->enabled) {
7008 clk_disable_unprepare(clki->clk);
7009 }
7010 clki->enabled = on;
7011 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7012 clki->name, on ? "en" : "dis");
7013 }
7014 }
1ab27c9c 7015
b334456e
SJ		 7016 /*
7017 * vendor specific setup_clocks ops may depend on clocks managed by
7018 * this standard driver hence call the vendor specific setup_clocks
7019 * after enabling the clocks managed here.
7020 */
7021 if (on) {
7022 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7023 if (ret)
7024 return ret;
7025 }
1e879e8f 7026
c6e79dac
SRT		 7027out:
7028 if (ret) {
7029 list_for_each_entry(clki, head, list) {
7030 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7031 clk_disable_unprepare(clki->clk);
7032 }
7ff5ab47 7033 } else if (!ret && on) {
1ab27c9c
ST		 7034 spin_lock_irqsave(hba->host->host_lock, flags);
7035 hba->clk_gating.state = CLKS_ON;
7ff5ab47 7036 trace_ufshcd_clk_gating(dev_name(hba->dev),
7037 hba->clk_gating.state);
1ab27c9c 7038 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7039 }
7ff5ab47 7040
911a0771 7041 if (clk_state_changed)
7042 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7043 (on ? "on" : "off"),
7044 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7045 return ret;
7046}
7047
57d104c1
SJ		 7048static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7049{
7050 return __ufshcd_setup_clocks(hba, on, false);
7051}
7052
c6e79dac
SRT		 7053static int ufshcd_init_clocks(struct ufs_hba *hba)
7054{
7055 int ret = 0;
7056 struct ufs_clk_info *clki;
7057 struct device *dev = hba->dev;
7058 struct list_head *head = &hba->clk_list_head;
7059
566ec9ad 7060 if (list_empty(head))
c6e79dac
SRT		 7061 goto out;
7062
7063 list_for_each_entry(clki, head, list) {
7064 if (!clki->name)
7065 continue;
7066
7067 clki->clk = devm_clk_get(dev, clki->name);
7068 if (IS_ERR(clki->clk)) {
7069 ret = PTR_ERR(clki->clk);
7070 dev_err(dev, "%s: %s clk get failed, %d\n",
7071 __func__, clki->name, ret);
7072 goto out;
7073 }
7074
7075 if (clki->max_freq) {
7076 ret = clk_set_rate(clki->clk, clki->max_freq);
7077 if (ret) {
7078 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7079 __func__, clki->name,
7080 clki->max_freq, ret);
7081 goto out;
7082 }
856b3483 7083 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7084 }
7085 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7086 clki->name, clk_get_rate(clki->clk));
7087 }
7088out:
7089 return ret;
7090}
7091
5c0c28a8
SRT		 7092static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7093{
7094 int err = 0;
7095
7096 if (!hba->vops)
7097 goto out;
7098
0263bcd0
YG		 7099 err = ufshcd_vops_init(hba);
7100 if (err)
7101 goto out;
5c0c28a8 7102
0263bcd0
YG		 7103 err = ufshcd_vops_setup_regulators(hba, true);
7104 if (err)
7105 goto out_exit;
5c0c28a8
SRT		 7106
7107 goto out;
7108
5c0c28a8 7109out_exit:
0263bcd0 7110 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7111out:
7112 if (err)
7113 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7114 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7115 return err;
7116}
7117
7118static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7119{
7120 if (!hba->vops)
7121 return;
7122
0263bcd0 7123 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7124
0263bcd0 7125 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7126}
7127
aa497613
SRT		 7128static int ufshcd_hba_init(struct ufs_hba *hba)
7129{
7130 int err;
7131
6a771a65
RS		 7132 /*
7133 * Handle host controller power separately from the UFS device power
7134 * rails as it will help controlling the UFS host controller power
7135 * collapse easily which is different than UFS device power collapse.
7136 * Also, enable the host controller power before we go ahead with rest
7137 * of the initialization here.
7138 */
7139 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7140 if (err)
7141 goto out;
7142
6a771a65 7143 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7144 if (err)
7145 goto out;
7146
6a771a65
RS		 7147 err = ufshcd_init_clocks(hba);
7148 if (err)
7149 goto out_disable_hba_vreg;
7150
7151 err = ufshcd_setup_clocks(hba, true);
7152 if (err)
7153 goto out_disable_hba_vreg;
7154
c6e79dac
SRT		 7155 err = ufshcd_init_vreg(hba);
7156 if (err)
7157 goto out_disable_clks;
7158
7159 err = ufshcd_setup_vreg(hba, true);
7160 if (err)
7161 goto out_disable_clks;
7162
aa497613
SRT		 7163 err = ufshcd_variant_hba_init(hba);
7164 if (err)
7165 goto out_disable_vreg;
7166
1d337ec2 7167 hba->is_powered = true;
aa497613
SRT		 7168 goto out;
7169
7170out_disable_vreg:
7171 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7172out_disable_clks:
7173 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7174out_disable_hba_vreg:
7175 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7176out:
7177 return err;
7178}
7179
7180static void ufshcd_hba_exit(struct ufs_hba *hba)
7181{
1d337ec2
SRT		 7182 if (hba->is_powered) {
7183 ufshcd_variant_hba_exit(hba);
7184 ufshcd_setup_vreg(hba, false);
a508253d 7185 ufshcd_suspend_clkscaling(hba);
eebcc196 7186 if (ufshcd_is_clkscaling_supported(hba))
0701e49d 7187 if (hba->devfreq)
7188 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7189 ufshcd_setup_clocks(hba, false);
7190 ufshcd_setup_hba_vreg(hba, false);
7191 hba->is_powered = false;
7192 }
aa497613
SRT		 7193}
7194
57d104c1
SJ		 7195static int
7196ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7197{
7198 unsigned char cmd[6] = {REQUEST_SENSE,
7199 0,
7200 0,
7201 0,
dcea0bfb 7202 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 7203 0};
7204 char *buffer;
7205 int ret;
7206
dcea0bfb 7207 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7208 if (!buffer) {
7209 ret = -ENOMEM;
7210 goto out;
7211 }
7212
fcbfffe2
CH		 7213 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7214 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
7215 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7216 if (ret)
7217 pr_err("%s: failed with err %d\n", __func__, ret);
7218
7219 kfree(buffer);
7220out:
7221 return ret;
7222}
7223
7224/**
7225 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7226 * power mode
7227 * @hba: per adapter instance
7228 * @pwr_mode: device power mode to set
7229 *
7230 * Returns 0 if requested power mode is set successfully
7231 * Returns non-zero if failed to set the requested power mode
7232 */
7233static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7234 enum ufs_dev_pwr_mode pwr_mode)
7235{
7236 unsigned char cmd[6] = { START_STOP };
7237 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7238 struct scsi_device *sdp;
7239 unsigned long flags;
57d104c1
SJ		 7240 int ret;
7241
7c48bfd0
AM		 7242 spin_lock_irqsave(hba->host->host_lock, flags);
7243 sdp = hba->sdev_ufs_device;
7244 if (sdp) {
7245 ret = scsi_device_get(sdp);
7246 if (!ret && !scsi_device_online(sdp)) {
7247 ret = -ENODEV;
7248 scsi_device_put(sdp);
7249 }
7250 } else {
7251 ret = -ENODEV;
7252 }
7253 spin_unlock_irqrestore(hba->host->host_lock, flags);
7254
7255 if (ret)
7256 return ret;
57d104c1
SJ		 7257
7258 /*
7259 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7260 * handling, which would wait for host to be resumed. Since we know
7261 * we are functional while we are here, skip host resume in error
7262 * handling context.
7263 */
7264 hba->host->eh_noresume = 1;
7265 if (hba->wlun_dev_clr_ua) {
7266 ret = ufshcd_send_request_sense(hba, sdp);
7267 if (ret)
7268 goto out;
7269 /* Unit attention condition is cleared now */
7270 hba->wlun_dev_clr_ua = false;
7271 }
7272
7273 cmd[4] = pwr_mode << 4;
7274
7275 /*
7276 * Current function would be generally called from the power management
e8064021 7277 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7278 * already suspended childs.
7279 */
fcbfffe2
CH		 7280 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7281 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7282 if (ret) {
7283 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7284 "START_STOP failed for power mode: %d, result %x\n",
7285 pwr_mode, ret);
c65be1a6 7286 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7287 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7288 }
7289
7290 if (!ret)
7291 hba->curr_dev_pwr_mode = pwr_mode;
7292out:
7c48bfd0 7293 scsi_device_put(sdp);
57d104c1
SJ		 7294 hba->host->eh_noresume = 0;
7295 return ret;
7296}
7297
7298static int ufshcd_link_state_transition(struct ufs_hba *hba,
7299 enum uic_link_state req_link_state,
7300 int check_for_bkops)
7301{
7302 int ret = 0;
7303
7304 if (req_link_state == hba->uic_link_state)
7305 return 0;
7306
7307 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7308 ret = ufshcd_uic_hibern8_enter(hba);
7309 if (!ret)
7310 ufshcd_set_link_hibern8(hba);
7311 else
7312 goto out;
7313 }
7314 /*
7315 * If autobkops is enabled, link can't be turned off because
7316 * turning off the link would also turn off the device.
7317 */
7318 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7319 (!check_for_bkops || (check_for_bkops &&
7320 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7321 /*
7322 * Let's make sure that link is in low power mode, we are doing
7323 * this currently by putting the link in Hibern8. Otherway to
7324 * put the link in low power mode is to send the DME end point
7325 * to device and then send the DME reset command to local
7326 * unipro. But putting the link in hibern8 is much faster.
7327 */
7328 ret = ufshcd_uic_hibern8_enter(hba);
7329 if (ret)
7330 goto out;
57d104c1
SJ		 7331 /*
7332 * Change controller state to "reset state" which
7333 * should also put the link in off/reset state
7334 */
596585a2 7335 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7336 /*
7337 * TODO: Check if we need any delay to make sure that
7338 * controller is reset
7339 */
7340 ufshcd_set_link_off(hba);
7341 }
7342
7343out:
7344 return ret;
7345}
7346
7347static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7348{
b799fdf7
YG		 7349 /*
7350 * It seems some UFS devices may keep drawing more than sleep current
7351 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7352 * To avoid this situation, add 2ms delay before putting these UFS
7353 * rails in LPM mode.
7354 */
7355 if (!ufshcd_is_link_active(hba) &&
7356 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7357 usleep_range(2000, 2100);
7358
57d104c1
SJ		 7359 /*
7360 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7361 * power.
7362 *
7363 * If UFS device and link is in OFF state, all power supplies (VCC,
7364 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7365 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7366 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7367 *
7368 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7369 * in low power state which would save some power.
7370 */
7371 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7372 !hba->dev_info.is_lu_power_on_wp) {
7373 ufshcd_setup_vreg(hba, false);
7374 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7375 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7376 if (!ufshcd_is_link_active(hba)) {
7377 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7378 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7379 }
7380 }
7381}
7382
7383static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7384{
7385 int ret = 0;
7386
7387 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7388 !hba->dev_info.is_lu_power_on_wp) {
7389 ret = ufshcd_setup_vreg(hba, true);
7390 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7391 if (!ret && !ufshcd_is_link_active(hba)) {
7392 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7393 if (ret)
7394 goto vcc_disable;
7395 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7396 if (ret)
7397 goto vccq_lpm;
7398 }
69d72ac8 7399 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7400 }
7401 goto out;
7402
7403vccq_lpm:
7404 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7405vcc_disable:
7406 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7407out:
7408 return ret;
7409}
7410
7411static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7412{
7413 if (ufshcd_is_link_off(hba))
7414 ufshcd_setup_hba_vreg(hba, false);
7415}
7416
7417static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7418{
7419 if (ufshcd_is_link_off(hba))
7420 ufshcd_setup_hba_vreg(hba, true);
7421}
7422
7a3e97b0 7423/**
57d104c1 7424 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7425 * @hba: per adapter instance
57d104c1
SJ		 7426 * @pm_op: desired low power operation type
7427 *
7428 * This function will try to put the UFS device and link into low power
7429 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7430 * (System PM level).
7431 *
7432 * If this function is called during shutdown, it will make sure that
7433 * both UFS device and UFS link is powered off.
7a3e97b0 7434 *
57d104c1
SJ		 7435 * NOTE: UFS device & link must be active before we enter in this function.
7436 *
7437 * Returns 0 for success and non-zero for failure
7a3e97b0 7438 */
57d104c1 7439static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7440{
57d104c1
SJ		 7441 int ret = 0;
7442 enum ufs_pm_level pm_lvl;
7443 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7444 enum uic_link_state req_link_state;
7445
7446 hba->pm_op_in_progress = 1;
7447 if (!ufshcd_is_shutdown_pm(pm_op)) {
7448 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7449 hba->rpm_lvl : hba->spm_lvl;
7450 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7451 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7452 } else {
7453 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7454 req_link_state = UIC_LINK_OFF_STATE;
7455 }
7456
7a3e97b0 7457 /*
57d104c1
SJ		 7458 * If we can't transition into any of the low power modes
7459 * just gate the clocks.
7a3e97b0 7460 */
1ab27c9c
ST		 7461 ufshcd_hold(hba, false);
7462 hba->clk_gating.is_suspended = true;
7463
401f1e44 7464 if (hba->clk_scaling.is_allowed) {
7465 cancel_work_sync(&hba->clk_scaling.suspend_work);
7466 cancel_work_sync(&hba->clk_scaling.resume_work);
7467 ufshcd_suspend_clkscaling(hba);
7468 }
d6fcf81a 7469
57d104c1
SJ		 7470 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7471 req_link_state == UIC_LINK_ACTIVE_STATE) {
7472 goto disable_clks;
7473 }
7a3e97b0 7474
57d104c1
SJ		 7475 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7476 (req_link_state == hba->uic_link_state))
d6fcf81a 7477 goto enable_gating;
57d104c1
SJ		 7478
7479 /* UFS device & link must be active before we enter in this function */
7480 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7481 ret = -EINVAL;
d6fcf81a 7482 goto enable_gating;
57d104c1
SJ		 7483 }
7484
7485 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7486 if (ufshcd_can_autobkops_during_suspend(hba)) {
7487 /*
7488 * The device is idle with no requests in the queue,
7489 * allow background operations if bkops status shows
7490 * that performance might be impacted.
7491 */
7492 ret = ufshcd_urgent_bkops(hba);
7493 if (ret)
7494 goto enable_gating;
7495 } else {
7496 /* make sure that auto bkops is disabled */
7497 ufshcd_disable_auto_bkops(hba);
7498 }
57d104c1
SJ		 7499 }
7500
7501 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7502 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7503 !ufshcd_is_runtime_pm(pm_op))) {
7504 /* ensure that bkops is disabled */
7505 ufshcd_disable_auto_bkops(hba);
7506 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7507 if (ret)
1ab27c9c 7508 goto enable_gating;
57d104c1
SJ		 7509 }
7510
7511 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7512 if (ret)
7513 goto set_dev_active;
7514
7515 ufshcd_vreg_set_lpm(hba);
7516
7517disable_clks:
7518 /*
7519 * Call vendor specific suspend callback. As these callbacks may access
7520 * vendor specific host controller register space call them before the
7521 * host clocks are ON.
7522 */
0263bcd0
YG		 7523 ret = ufshcd_vops_suspend(hba, pm_op);
7524 if (ret)
7525 goto set_link_active;
57d104c1 7526
57d104c1
SJ		 7527 if (!ufshcd_is_link_active(hba))
7528 ufshcd_setup_clocks(hba, false);
7529 else
7530 /* If link is active, device ref_clk can't be switched off */
7531 __ufshcd_setup_clocks(hba, false, true);
7532
1ab27c9c 7533 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7534 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7535 /*
7536 * Disable the host irq as host controller as there won't be any
0263bcd0 7537 * host controller transaction expected till resume.
57d104c1
SJ		 7538 */
7539 ufshcd_disable_irq(hba);
7540 /* Put the host controller in low power mode if possible */
7541 ufshcd_hba_vreg_set_lpm(hba);
7542 goto out;
7543
57d104c1 7544set_link_active:
401f1e44 7545 if (hba->clk_scaling.is_allowed)
7546 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7547 ufshcd_vreg_set_hpm(hba);
7548 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7549 ufshcd_set_link_active(hba);
7550 else if (ufshcd_is_link_off(hba))
7551 ufshcd_host_reset_and_restore(hba);
7552set_dev_active:
7553 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7554 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7555enable_gating:
401f1e44 7556 if (hba->clk_scaling.is_allowed)
7557 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7558 hba->clk_gating.is_suspended = false;
7559 ufshcd_release(hba);
57d104c1
SJ		 7560out:
7561 hba->pm_op_in_progress = 0;
7562 return ret;
7a3e97b0
SY		 7563}
7564
7565/**
57d104c1 7566 * ufshcd_resume - helper function for resume operations
3b1d0580 7567 * @hba: per adapter instance
57d104c1 7568 * @pm_op: runtime PM or system PM
7a3e97b0 7569 *
57d104c1
SJ		 7570 * This function basically brings the UFS device, UniPro link and controller
7571 * to active state.
7572 *
7573 * Returns 0 for success and non-zero for failure
7a3e97b0 7574 */
57d104c1 7575static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7576{
57d104c1
SJ		 7577 int ret;
7578 enum uic_link_state old_link_state;
7579
7580 hba->pm_op_in_progress = 1;
7581 old_link_state = hba->uic_link_state;
7582
7583 ufshcd_hba_vreg_set_hpm(hba);
7584 /* Make sure clocks are enabled before accessing controller */
7585 ret = ufshcd_setup_clocks(hba, true);
7586 if (ret)
7587 goto out;
7588
57d104c1
SJ		 7589 /* enable the host irq as host controller would be active soon */
7590 ret = ufshcd_enable_irq(hba);
7591 if (ret)
7592 goto disable_irq_and_vops_clks;
7593
7594 ret = ufshcd_vreg_set_hpm(hba);
7595 if (ret)
7596 goto disable_irq_and_vops_clks;
7597
7a3e97b0 7598 /*
57d104c1
SJ		 7599 * Call vendor specific resume callback. As these callbacks may access
7600 * vendor specific host controller register space call them when the
7601 * host clocks are ON.
7a3e97b0 7602 */
0263bcd0
YG		 7603 ret = ufshcd_vops_resume(hba, pm_op);
7604 if (ret)
7605 goto disable_vreg;
57d104c1
SJ		 7606
7607 if (ufshcd_is_link_hibern8(hba)) {
7608 ret = ufshcd_uic_hibern8_exit(hba);
7609 if (!ret)
7610 ufshcd_set_link_active(hba);
7611 else
7612 goto vendor_suspend;
7613 } else if (ufshcd_is_link_off(hba)) {
7614 ret = ufshcd_host_reset_and_restore(hba);
7615 /*
7616 * ufshcd_host_reset_and_restore() should have already
7617 * set the link state as active
7618 */
7619 if (ret || !ufshcd_is_link_active(hba))
7620 goto vendor_suspend;
7621 }
7622
7623 if (!ufshcd_is_ufs_dev_active(hba)) {
7624 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7625 if (ret)
7626 goto set_old_link_state;
7627 }
7628
4e768e76 7629 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7630 ufshcd_enable_auto_bkops(hba);
7631 else
7632 /*
7633 * If BKOPs operations are urgently needed at this moment then
7634 * keep auto-bkops enabled or else disable it.
7635 */
7636 ufshcd_urgent_bkops(hba);
7637
1ab27c9c
ST		 7638 hba->clk_gating.is_suspended = false;
7639
fcb0c4b0
ST		 7640 if (hba->clk_scaling.is_allowed)
7641 ufshcd_resume_clkscaling(hba);
856b3483 7642
1ab27c9c
ST		 7643 /* Schedule clock gating in case of no access to UFS device yet */
7644 ufshcd_release(hba);
ad448378
AH		 7645
7646 /* Enable Auto-Hibernate if configured */
7647 ufshcd_auto_hibern8_enable(hba);
7648
57d104c1
SJ		 7649 goto out;
7650
7651set_old_link_state:
7652 ufshcd_link_state_transition(hba, old_link_state, 0);
7653vendor_suspend:
0263bcd0 7654 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7655disable_vreg:
7656 ufshcd_vreg_set_lpm(hba);
7657disable_irq_and_vops_clks:
7658 ufshcd_disable_irq(hba);
401f1e44 7659 if (hba->clk_scaling.is_allowed)
7660 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7661 ufshcd_setup_clocks(hba, false);
7662out:
7663 hba->pm_op_in_progress = 0;
7664 return ret;
7665}
7666
7667/**
7668 * ufshcd_system_suspend - system suspend routine
7669 * @hba: per adapter instance
57d104c1
SJ		 7670 *
7671 * Check the description of ufshcd_suspend() function for more details.
7672 *
7673 * Returns 0 for success and non-zero for failure
7674 */
7675int ufshcd_system_suspend(struct ufs_hba *hba)
7676{
7677 int ret = 0;
7ff5ab47 7678 ktime_t start = ktime_get();
57d104c1
SJ		 7679
7680 if (!hba || !hba->is_powered)
233b594b 7681 return 0;
57d104c1 7682
0b257734 7683 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7684 hba->curr_dev_pwr_mode) &&
7685 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7686 hba->uic_link_state))
7687 goto out;
57d104c1 7688
0b257734 7689 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7690 /*
7691 * UFS device and/or UFS link low power states during runtime
7692 * suspend seems to be different than what is expected during
7693 * system suspend. Hence runtime resume the devic & link and
7694 * let the system suspend low power states to take effect.
7695 * TODO: If resume takes longer time, we might have optimize
7696 * it in future by not resuming everything if possible.
7697 */
7698 ret = ufshcd_runtime_resume(hba);
7699 if (ret)
7700 goto out;
7701 }
7702
7703 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7704out:
7ff5ab47 7705 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7706 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7707 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7708 if (!ret)
7709 hba->is_sys_suspended = true;
57d104c1
SJ		 7710 return ret;
7711}
7712EXPORT_SYMBOL(ufshcd_system_suspend);
7713
7714/**
7715 * ufshcd_system_resume - system resume routine
7716 * @hba: per adapter instance
7717 *
7718 * Returns 0 for success and non-zero for failure
7719 */
7a3e97b0 7720
57d104c1
SJ		 7721int ufshcd_system_resume(struct ufs_hba *hba)
7722{
7ff5ab47 7723 int ret = 0;
7724 ktime_t start = ktime_get();
7725
e3ce73d6
YG		 7726 if (!hba)
7727 return -EINVAL;
7728
7729 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7730 /*
7731 * Let the runtime resume take care of resuming
7732 * if runtime suspended.
7733 */
7ff5ab47 7734 goto out;
7735 else
7736 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7737out:
7738 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7739 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7740 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7741 return ret;
7a3e97b0 7742}
57d104c1 7743EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7744
57d104c1
SJ		 7745/**
7746 * ufshcd_runtime_suspend - runtime suspend routine
7747 * @hba: per adapter instance
7748 *
7749 * Check the description of ufshcd_suspend() function for more details.
7750 *
7751 * Returns 0 for success and non-zero for failure
7752 */
66ec6d59
SRT		 7753int ufshcd_runtime_suspend(struct ufs_hba *hba)
7754{
7ff5ab47 7755 int ret = 0;
7756 ktime_t start = ktime_get();
7757
e3ce73d6
YG		 7758 if (!hba)
7759 return -EINVAL;
7760
7761 if (!hba->is_powered)
7ff5ab47 7762 goto out;
7763 else
7764 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7765out:
7766 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7767 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7768 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7769 return ret;
66ec6d59
SRT		 7770}
7771EXPORT_SYMBOL(ufshcd_runtime_suspend);
7772
57d104c1
SJ		 7773/**
7774 * ufshcd_runtime_resume - runtime resume routine
7775 * @hba: per adapter instance
7776 *
7777 * This function basically brings the UFS device, UniPro link and controller
7778 * to active state. Following operations are done in this function:
7779 *
7780 * 1. Turn on all the controller related clocks
7781 * 2. Bring the UniPro link out of Hibernate state
7782 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7783 * to active state.
7784 * 4. If auto-bkops is enabled on the device, disable it.
7785 *
7786 * So following would be the possible power state after this function return
7787 * successfully:
7788 * S1: UFS device in Active state with VCC rail ON
7789 * UniPro link in Active state
7790 * All the UFS/UniPro controller clocks are ON
7791 *
7792 * Returns 0 for success and non-zero for failure
7793 */
66ec6d59
SRT		 7794int ufshcd_runtime_resume(struct ufs_hba *hba)
7795{
7ff5ab47 7796 int ret = 0;
7797 ktime_t start = ktime_get();
7798
e3ce73d6
YG		 7799 if (!hba)
7800 return -EINVAL;
7801
7802 if (!hba->is_powered)
7ff5ab47 7803 goto out;
7804 else
7805 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7806out:
7807 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7808 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7809 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7810 return ret;
66ec6d59
SRT		 7811}
7812EXPORT_SYMBOL(ufshcd_runtime_resume);
7813
7814int ufshcd_runtime_idle(struct ufs_hba *hba)
7815{
7816 return 0;
7817}
7818EXPORT_SYMBOL(ufshcd_runtime_idle);
7819
57d104c1
SJ		 7820/**
7821 * ufshcd_shutdown - shutdown routine
7822 * @hba: per adapter instance
7823 *
7824 * This function would power off both UFS device and UFS link.
7825 *
7826 * Returns 0 always to allow force shutdown even in case of errors.
7827 */
7828int ufshcd_shutdown(struct ufs_hba *hba)
7829{
7830 int ret = 0;
7831
7832 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7833 goto out;
7834
7835 if (pm_runtime_suspended(hba->dev)) {
7836 ret = ufshcd_runtime_resume(hba);
7837 if (ret)
7838 goto out;
7839 }
7840
7841 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7842out:
7843 if (ret)
7844 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7845 /* allow force shutdown even in case of errors */
7846 return 0;
7847}
7848EXPORT_SYMBOL(ufshcd_shutdown);
7849
7a3e97b0 7850/**
3b1d0580 7851 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7852 * data structure memory
8aa29f19 7853 * @hba: per adapter instance
7a3e97b0 7854 */
3b1d0580 7855void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7856{
cbb6813e 7857 ufs_sysfs_remove_nodes(hba->dev);
cfdf9c91 7858 scsi_remove_host(hba->host);
7a3e97b0 7859 /* disable interrupts */
2fbd009b 7860 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7861 ufshcd_hba_stop(hba, true);
7a3e97b0 7862
eebcc196 7863 ufshcd_exit_clk_scaling(hba);
1ab27c9c 7864 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 7865 if (ufshcd_is_clkscaling_supported(hba))
7866 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7867 ufshcd_hba_exit(hba);
3b1d0580
VH		 7868}
7869EXPORT_SYMBOL_GPL(ufshcd_remove);
7870
47555a5c
YG		 7871/**
7872 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7873 * @hba: pointer to Host Bus Adapter (HBA)
7874 */
7875void ufshcd_dealloc_host(struct ufs_hba *hba)
7876{
7877 scsi_host_put(hba->host);
7878}
7879EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7880
ca3d7bf9
AM		 7881/**
7882 * ufshcd_set_dma_mask - Set dma mask based on the controller
7883 * addressing capability
7884 * @hba: per adapter instance
7885 *
7886 * Returns 0 for success, non-zero for failure
7887 */
7888static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7889{
7890 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7891 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7892 return 0;
7893 }
7894 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7895}
7896
7a3e97b0 7897/**
5c0c28a8 7898 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 7899 * @dev: pointer to device handle
7900 * @hba_handle: driver private handle
7a3e97b0
SY		 7901 * Returns 0 on success, non-zero value on failure
7902 */
5c0c28a8 7903int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 7904{
7905 struct Scsi_Host *host;
7906 struct ufs_hba *hba;
5c0c28a8 7907 int err = 0;
7a3e97b0 7908
3b1d0580
VH		 7909 if (!dev) {
7910 dev_err(dev,
7911 "Invalid memory reference for dev is NULL\n");
7912 err = -ENODEV;
7a3e97b0
SY		 7913 goto out_error;
7914 }
7915
7a3e97b0
SY		 7916 host = scsi_host_alloc(&ufshcd_driver_template,
7917 sizeof(struct ufs_hba));
7918 if (!host) {
3b1d0580 7919 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7920 err = -ENOMEM;
3b1d0580 7921 goto out_error;
7a3e97b0
SY		 7922 }
7923 hba = shost_priv(host);
7a3e97b0 7924 hba->host = host;
3b1d0580 7925 hba->dev = dev;
5c0c28a8
SRT		 7926 *hba_handle = hba;
7927
566ec9ad
SM		 7928 INIT_LIST_HEAD(&hba->clk_list_head);
7929
5c0c28a8
SRT		 7930out_error:
7931 return err;
7932}
7933EXPORT_SYMBOL(ufshcd_alloc_host);
7934
7935/**
7936 * ufshcd_init - Driver initialization routine
7937 * @hba: per-adapter instance
7938 * @mmio_base: base register address
7939 * @irq: Interrupt line of device
7940 * Returns 0 on success, non-zero value on failure
7941 */
7942int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7943{
7944 int err;
7945 struct Scsi_Host *host = hba->host;
7946 struct device *dev = hba->dev;
7947
7948 if (!mmio_base) {
7949 dev_err(hba->dev,
7950 "Invalid memory reference for mmio_base is NULL\n");
7951 err = -ENODEV;
7952 goto out_error;
7953 }
7954
3b1d0580
VH		 7955 hba->mmio_base = mmio_base;
7956 hba->irq = irq;
7a3e97b0 7957
a4b0e8a4
PM		 7958 /* Set descriptor lengths to specification defaults */
7959 ufshcd_def_desc_sizes(hba);
7960
aa497613 7961 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7962 if (err)
7963 goto out_error;
7964
7a3e97b0
SY		 7965 /* Read capabilities registers */
7966 ufshcd_hba_capabilities(hba);
7967
7968 /* Get UFS version supported by the controller */
7969 hba->ufs_version = ufshcd_get_ufs_version(hba);
7970
c01848c6
YG		 7971 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7972 (hba->ufs_version != UFSHCI_VERSION_11) &&
7973 (hba->ufs_version != UFSHCI_VERSION_20) &&
7974 (hba->ufs_version != UFSHCI_VERSION_21))
7975 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7976 hba->ufs_version);
7977
2fbd009b
SJ		 7978 /* Get Interrupt bit mask per version */
7979 hba->intr_mask = ufshcd_get_intr_mask(hba);
7980
ca3d7bf9
AM		 7981 err = ufshcd_set_dma_mask(hba);
7982 if (err) {
7983 dev_err(hba->dev, "set dma mask failed\n");
7984 goto out_disable;
7985 }
7986
7a3e97b0
SY		 7987 /* Allocate memory for host memory space */
7988 err = ufshcd_memory_alloc(hba);
7989 if (err) {
3b1d0580
VH		 7990 dev_err(hba->dev, "Memory allocation failed\n");
7991 goto out_disable;
7a3e97b0
SY		 7992 }
7993
7994 /* Configure LRB */
7995 ufshcd_host_memory_configure(hba);
7996
7997 host->can_queue = hba->nutrs;
7998 host->cmd_per_lun = hba->nutrs;
7999 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8000 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8001 host->max_channel = UFSHCD_MAX_CHANNEL;
8002 host->unique_id = host->host_no;
a851b2bd 8003 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8004
7eb584db
DR		 8005 hba->max_pwr_info.is_valid = false;
8006
7a3e97b0 8007 /* Initailize wait queue for task management */
e2933132
SRT		 8008 init_waitqueue_head(&hba->tm_wq);
8009 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 8010
8011 /* Initialize work queues */
e8e7f271 8012 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8013 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8014
6ccf44fe
SJ		 8015 /* Initialize UIC command mutex */
8016 mutex_init(&hba->uic_cmd_mutex);
8017
5a0b0cb9
SRT		 8018 /* Initialize mutex for device management commands */
8019 mutex_init(&hba->dev_cmd.lock);
8020
a3cd5ec5 8021 init_rwsem(&hba->clk_scaling_lock);
8022
5a0b0cb9
SRT		 8023 /* Initialize device management tag acquire wait queue */
8024 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8025
1ab27c9c 8026 ufshcd_init_clk_gating(hba);
199ef13c 8027
eebcc196
VG		 8028 ufshcd_init_clk_scaling(hba);
8029
199ef13c
YG		 8030 /*
8031 * In order to avoid any spurious interrupt immediately after
8032 * registering UFS controller interrupt handler, clear any pending UFS
8033 * interrupt status and disable all the UFS interrupts.
8034 */
8035 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8036 REG_INTERRUPT_STATUS);
8037 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8038 /*
8039 * Make sure that UFS interrupts are disabled and any pending interrupt
8040 * status is cleared before registering UFS interrupt handler.
8041 */
8042 mb();
8043
7a3e97b0 8044 /* IRQ registration */
2953f850 8045 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8046 if (err) {
3b1d0580 8047 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8048 goto exit_gating;
57d104c1
SJ		 8049 } else {
8050 hba->is_irq_enabled = true;
7a3e97b0
SY		 8051 }
8052
3b1d0580 8053 err = scsi_add_host(host, hba->dev);
7a3e97b0 8054 if (err) {
3b1d0580 8055 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8056 goto exit_gating;
7a3e97b0
SY		 8057 }
8058
6ccf44fe
SJ		 8059 /* Host controller enable */
8060 err = ufshcd_hba_enable(hba);
7a3e97b0 8061 if (err) {
6ccf44fe 8062 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8063 ufshcd_print_host_regs(hba);
6ba65588 8064 ufshcd_print_host_state(hba);
3b1d0580 8065 goto out_remove_scsi_host;
7a3e97b0 8066 }
6ccf44fe 8067
0c8f7586 8068 /*
8069 * Set the default power management level for runtime and system PM.
8070 * Default power saving mode is to keep UFS link in Hibern8 state
8071 * and UFS device in sleep state.
8072 */
8073 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8074 UFS_SLEEP_PWR_MODE,
8075 UIC_LINK_HIBERN8_STATE);
8076 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8077 UFS_SLEEP_PWR_MODE,
8078 UIC_LINK_HIBERN8_STATE);
8079
ad448378
AH		 8080 /* Set the default auto-hiberate idle timer value to 150 ms */
8081 if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
8082 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8083 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8084 }
8085
62694735
SRT		 8086 /* Hold auto suspend until async scan completes */
8087 pm_runtime_get_sync(dev);
38135535 8088 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8089 /*
7caf489b 8090 * We are assuming that device wasn't put in sleep/power-down
8091 * state exclusively during the boot stage before kernel.
8092 * This assumption helps avoid doing link startup twice during
8093 * ufshcd_probe_hba().
57d104c1 8094 */
7caf489b 8095 ufshcd_set_ufs_dev_active(hba);
57d104c1 8096
6ccf44fe 8097 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8098 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8099
7a3e97b0
SY		 8100 return 0;
8101
3b1d0580
VH		 8102out_remove_scsi_host:
8103 scsi_remove_host(hba->host);
1ab27c9c 8104exit_gating:
eebcc196 8105 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8106 ufshcd_exit_clk_gating(hba);
3b1d0580 8107out_disable:
57d104c1 8108 hba->is_irq_enabled = false;
aa497613 8109 ufshcd_hba_exit(hba);
3b1d0580
VH		 8110out_error:
8111 return err;
8112}
8113EXPORT_SYMBOL_GPL(ufshcd_init);
8114
3b1d0580
VH		 8115MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8116MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8117MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8118MODULE_LICENSE("GPL");
8119MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)