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scsi: mpt3sas: Fix spelling mistake
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
67351119 1// SPDX-License-Identifier: GPL-2.0-or-later
7a3e97b0 2/*
e0eca63e 3 * Universal Flash Storage Host controller driver Core
3b1d0580 4 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 */
11
6ccf44fe 12#include <linux/async.h>
856b3483 13#include <linux/devfreq.h>
b573d484 14#include <linux/nls.h>
54b879b7 15#include <linux/of.h>
ad448378 16#include <linux/bitfield.h>
fb276f77 17#include <linux/blk-pm.h>
e0eca63e 18#include "ufshcd.h"
c58ab7aa 19#include "ufs_quirks.h"
53b3d9c3 20#include "unipro.h"
cbb6813e 21#include "ufs-sysfs.h"
df032bf2 22#include "ufs_bsg.h"
3d17b9b5
AD		 23#include <asm/unaligned.h>
24#include <linux/blkdev.h>
7a3e97b0 25
7ff5ab47 26#define CREATE_TRACE_POINTS
27#include <trace/events/ufs.h>
28
2fbd009b
SJ		 29#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
30 UTP_TASK_REQ_COMPL |\
31 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 32/* UIC command timeout, unit: ms */
33#define UIC_CMD_TIMEOUT 500
2fbd009b 34
5a0b0cb9
SRT		 35/* NOP OUT retries waiting for NOP IN response */
36#define NOP_OUT_RETRIES 10
37/* Timeout after 30 msecs if NOP OUT hangs without response */
38#define NOP_OUT_TIMEOUT 30 /* msecs */
39
68078d5c 40/* Query request retries */
10fe5888 41#define QUERY_REQ_RETRIES 3
68078d5c 42/* Query request timeout */
10fe5888 43#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 44
e2933132
SRT		 45/* Task management command timeout */
46#define TM_CMD_TIMEOUT 100 /* msecs */
47
64238fbd
YG		 48/* maximum number of retries for a general UIC command */
49#define UFS_UIC_COMMAND_RETRIES 3
50
1d337ec2
SRT		 51/* maximum number of link-startup retries */
52#define DME_LINKSTARTUP_RETRIES 3
53
87d0b4a6
YG		 54/* Maximum retries for Hibern8 enter */
55#define UIC_HIBERN8_ENTER_RETRIES 3
56
1d337ec2
SRT		 57/* maximum number of reset retries before giving up */
58#define MAX_HOST_RESET_RETRIES 5
59
68078d5c
DR		 60/* Expose the flag value from utp_upiu_query.value */
61#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
62
7d568652
SJ		 63/* Interrupt aggregation default timeout, unit: 40us */
64#define INT_AGGR_DEF_TO 0x02
65
49615ba1
SC		 66/* default delay of autosuspend: 2000 ms */
67#define RPM_AUTOSUSPEND_DELAY_MS 2000
68
51dd905b
SC		 69/* Default delay of RPM device flush delayed work */
70#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
71
09f17791
CG		 72/* Default value of wait time before gating device ref clock */
73#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
74
aa497613
SRT		 75#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
76 ({ \
77 int _ret; \
78 if (_on) \
79 _ret = ufshcd_enable_vreg(_dev, _vreg); \
80 else \
81 _ret = ufshcd_disable_vreg(_dev, _vreg); \
82 _ret; \
83 })
84
ba80917d
TW		 85#define ufshcd_hex_dump(prefix_str, buf, len) do { \
86 size_t __len = (len); \
87 print_hex_dump(KERN_ERR, prefix_str, \
88 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
89 16, 4, buf, __len, false); \
90} while (0)
91
92int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
93 const char *prefix)
94{
d6724756
MG		 95 u32 *regs;
96 size_t pos;
97
98 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
99 return -EINVAL;
ba80917d 100
cddaebaf 101 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 102 if (!regs)
103 return -ENOMEM;
104
d6724756
MG		 105 for (pos = 0; pos < len; pos += 4)
106 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
107
ba80917d
TW		 108 ufshcd_hex_dump(prefix, regs, len);
109 kfree(regs);
110
111 return 0;
112}
113EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 114
7a3e97b0
SY		 115enum {
116 UFSHCD_MAX_CHANNEL = 0,
117 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 118 UFSHCD_CMD_PER_LUN = 32,
119 UFSHCD_CAN_QUEUE = 32,
120};
121
122/* UFSHCD states */
123enum {
7a3e97b0
SY		 124 UFSHCD_STATE_RESET,
125 UFSHCD_STATE_ERROR,
3441da7d 126 UFSHCD_STATE_OPERATIONAL,
141f8165 127 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 128};
129
130/* UFSHCD error handling flags */
131enum {
132 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 133};
134
e8e7f271
SRT		 135/* UFSHCD UIC layer error flags */
136enum {
137 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 138 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
139 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
140 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
141 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
142 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 143};
144
3441da7d 145#define ufshcd_set_eh_in_progress(h) \
9c490d2d 146 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 147#define ufshcd_eh_in_progress(h) \
9c490d2d 148 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 149#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 150 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 151
cbb6813e 152struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 153 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
154 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
155 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
156 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
157 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
158 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
159};
160
161static inline enum ufs_dev_pwr_mode
162ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
163{
164 return ufs_pm_lvl_states[lvl].dev_state;
165}
166
167static inline enum uic_link_state
168ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
169{
170 return ufs_pm_lvl_states[lvl].link_state;
171}
172
0c8f7586 173static inline enum ufs_pm_level
174ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
175 enum uic_link_state link_state)
176{
177 enum ufs_pm_level lvl;
178
179 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
180 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
181 (ufs_pm_lvl_states[lvl].link_state == link_state))
182 return lvl;
183 }
184
185 /* if no match found, return the level 0 */
186 return UFS_PM_LVL_0;
187}
188
56d4a186
SJ		 189static struct ufs_dev_fix ufs_fixups[] = {
190 /* UFS cards deviations table */
191 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
192 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
56d4a186
SJ		 193 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
194 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
56d4a186
SJ		 195 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
196 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
197 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
198 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
199 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
200 UFS_DEVICE_QUIRK_PA_TACTIVATE),
201 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
202 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 203 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
204 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
8e4829c6
WL		 205 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
206 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 207
208 END_FIX
209};
210
9333d775 211static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 212static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 213static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 214static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 215static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 216static void ufshcd_hba_exit(struct ufs_hba *hba);
1b9e2141 217static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
1ab27c9c
ST		 218static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
219 bool skip_ref_clk);
220static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
1ab27c9c 221static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 222static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 223static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 224static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
225static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 226static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 227static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 228static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 229static int ufshcd_change_power_mode(struct ufs_hba *hba,
230 struct ufs_pa_layer_attr *pwr_mode);
3d17b9b5
AD		 231static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba);
232static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba);
233static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable);
234static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
235static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
236
14497328
YG		 237static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
238{
239 return tag >= 0 && tag < hba->nutrs;
240}
57d104c1 241
5231d38c 242static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 243{
57d104c1 244 if (!hba->is_irq_enabled) {
5231d38c 245 enable_irq(hba->irq);
57d104c1
SJ		 246 hba->is_irq_enabled = true;
247 }
57d104c1
SJ		 248}
249
250static inline void ufshcd_disable_irq(struct ufs_hba *hba)
251{
252 if (hba->is_irq_enabled) {
5231d38c 253 disable_irq(hba->irq);
57d104c1
SJ		 254 hba->is_irq_enabled = false;
255 }
256}
3441da7d 257
3d17b9b5
AD		 258static inline void ufshcd_wb_config(struct ufs_hba *hba)
259{
260 int ret;
261
79e3520f 262 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 263 return;
264
265 ret = ufshcd_wb_ctrl(hba, true);
266 if (ret)
267 dev_err(hba->dev, "%s: Enable WB failed: %d\n", __func__, ret);
268 else
269 dev_info(hba->dev, "%s: Write Booster Configured\n", __func__);
270 ret = ufshcd_wb_toggle_flush_during_h8(hba, true);
271 if (ret)
272 dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
273 __func__, ret);
274 ufshcd_wb_toggle_flush(hba, true);
275}
276
38135535
SJ		 277static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
278{
279 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
280 scsi_unblock_requests(hba->host);
281}
282
283static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
284{
285 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
286 scsi_block_requests(hba->host);
287}
288
6667e6d9
OS		 289static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
290 const char *str)
291{
292 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
293
294 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
295}
296
297static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
298 const char *str)
299{
300 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
301
302 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
303}
304
305static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
306 const char *str)
307{
6667e6d9 308 int off = (int)tag - hba->nutrs;
391e388f 309 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 310
391e388f
CH		 311 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
312 &descp->input_param1);
6667e6d9
OS		 313}
314
1a07f2d9
LS		 315static void ufshcd_add_command_trace(struct ufs_hba *hba,
316 unsigned int tag, const char *str)
317{
318 sector_t lba = -1;
319 u8 opcode = 0;
320 u32 intr, doorbell;
e7c3b379 321 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 322 struct scsi_cmnd *cmd = lrbp->cmd;
1a07f2d9
LS		 323 int transfer_len = -1;
324
e7c3b379
OS		 325 if (!trace_ufshcd_command_enabled()) {
326 /* trace UPIU W/O tracing command */
e4d2add7 327 if (cmd)
e7c3b379 328 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 329 return;
e7c3b379 330 }
1a07f2d9 331
e4d2add7 332 if (cmd) { /* data phase exists */
e7c3b379
OS		 333 /* trace UPIU also */
334 ufshcd_add_cmd_upiu_trace(hba, tag, str);
e4d2add7 335 opcode = cmd->cmnd[0];
1a07f2d9
LS		 336 if ((opcode == READ_10) || (opcode == WRITE_10)) {
337 /*
338 * Currently we only fully trace read(10) and write(10)
339 * commands
340 */
e4d2add7
BVA		 341 if (cmd->request && cmd->request->bio)
342 lba = cmd->request->bio->bi_iter.bi_sector;
1a07f2d9
LS		 343 transfer_len = be32_to_cpu(
344 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
345 }
346 }
347
348 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
349 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
350 trace_ufshcd_command(dev_name(hba->dev), str, tag,
351 doorbell, transfer_len, intr, lba, opcode);
352}
353
ff8e20c6
DR		 354static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
355{
356 struct ufs_clk_info *clki;
357 struct list_head *head = &hba->clk_list_head;
358
566ec9ad 359 if (list_empty(head))
ff8e20c6
DR		 360 return;
361
362 list_for_each_entry(clki, head, list) {
363 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
364 clki->max_freq)
365 dev_err(hba->dev, "clk: %s, rate: %u\n",
366 clki->name, clki->curr_freq);
367 }
368}
369
48d5b973
SC		 370static void ufshcd_print_err_hist(struct ufs_hba *hba,
371 struct ufs_err_reg_hist *err_hist,
372 char *err_name)
ff8e20c6
DR		 373{
374 int i;
27752647 375 bool found = false;
ff8e20c6 376
48d5b973
SC		 377 for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
378 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
ff8e20c6 379
645728a6 380 if (err_hist->tstamp[p] == 0)
ff8e20c6 381 continue;
c5397f13 382 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
ff8e20c6 383 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
27752647 384 found = true;
ff8e20c6 385 }
27752647
SC		 386
387 if (!found)
fd1fb4d5 388 dev_err(hba->dev, "No record of %s\n", err_name);
ff8e20c6
DR		 389}
390
66cc820f
DR		 391static void ufshcd_print_host_regs(struct ufs_hba *hba)
392{
ba80917d 393 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 394 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
395 hba->ufs_version, hba->capabilities);
396 dev_err(hba->dev,
397 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
398 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 399 dev_err(hba->dev,
400 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
401 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
402 hba->ufs_stats.hibern8_exit_cnt);
403
48d5b973
SC		 404 ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
405 ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
406 ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
407 ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
408 ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
d3c615bf
SC		 409 ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
410 "auto_hibern8_err");
8808b4e9
SC		 411 ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
412 ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
413 "link_startup_fail");
414 ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
415 ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
416 "suspend_fail");
417 ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
418 ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
419 ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
ff8e20c6
DR		 420
421 ufshcd_print_clk_freqs(hba);
422
7c486d91 423 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 424}
425
426static
427void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
428{
429 struct ufshcd_lrb *lrbp;
7fabb77b 430 int prdt_length;
66cc820f
DR		 431 int tag;
432
433 for_each_set_bit(tag, &bitmap, hba->nutrs) {
434 lrbp = &hba->lrb[tag];
435
ff8e20c6
DR		 436 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
437 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 438 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
439 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 440 dev_err(hba->dev,
441 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
442 tag, (u64)lrbp->utrd_dma_addr);
443
66cc820f
DR		 444 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
445 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 446 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
447 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 448 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
449 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 450 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
451 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 452 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
453 sizeof(struct utp_upiu_rsp));
66cc820f 454
7fabb77b
GB		 455 prdt_length = le16_to_cpu(
456 lrbp->utr_descriptor_ptr->prd_table_length);
457 dev_err(hba->dev,
458 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
459 tag, prdt_length,
460 (u64)lrbp->ucd_prdt_dma_addr);
461
462 if (pr_prdt)
66cc820f 463 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 464 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 465 }
466}
467
468static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
469{
66cc820f
DR		 470 int tag;
471
472 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 473 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
474
66cc820f 475 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 476 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 477 }
478}
479
6ba65588
GB		 480static void ufshcd_print_host_state(struct ufs_hba *hba)
481{
482 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 483 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
484 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 485 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
486 hba->saved_err, hba->saved_uic_err);
487 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
488 hba->curr_dev_pwr_mode, hba->uic_link_state);
489 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
490 hba->pm_op_in_progress, hba->is_sys_suspended);
491 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
492 hba->auto_bkops_enabled, hba->host->host_self_blocked);
493 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
494 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
495 hba->eh_flags, hba->req_abort_count);
496 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
497 hba->capabilities, hba->caps);
498 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
499 hba->dev_quirks);
500}
501
ff8e20c6
DR		 502/**
503 * ufshcd_print_pwr_info - print power params as saved in hba
504 * power info
505 * @hba: per-adapter instance
506 */
507static void ufshcd_print_pwr_info(struct ufs_hba *hba)
508{
509 static const char * const names[] = {
510 "INVALID MODE",
511 "FAST MODE",
512 "SLOW_MODE",
513 "INVALID MODE",
514 "FASTAUTO_MODE",
515 "SLOWAUTO_MODE",
516 "INVALID MODE",
517 };
518
519 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
520 __func__,
521 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
522 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
523 names[hba->pwr_info.pwr_rx],
524 names[hba->pwr_info.pwr_tx],
525 hba->pwr_info.hs_rate);
526}
527
5c955c10
SC		 528void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
529{
530 if (!us)
531 return;
532
533 if (us < 10)
534 udelay(us);
535 else
536 usleep_range(us, us + tolerance);
537}
538EXPORT_SYMBOL_GPL(ufshcd_delay_us);
539
5cac1095 540/**
5a0b0cb9 541 * ufshcd_wait_for_register - wait for register value to change
5cac1095
BVA		 542 * @hba: per-adapter interface
543 * @reg: mmio register offset
544 * @mask: mask to apply to the read register value
545 * @val: value to wait for
546 * @interval_us: polling interval in microseconds
547 * @timeout_ms: timeout in milliseconds
5a0b0cb9 548 *
5cac1095
BVA		 549 * Return:
550 * -ETIMEDOUT on error, zero on success.
5a0b0cb9 551 */
596585a2
YG		 552int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
553 u32 val, unsigned long interval_us,
5cac1095 554 unsigned long timeout_ms)
5a0b0cb9
SRT		 555{
556 int err = 0;
557 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
558
559 /* ignore bits that we don't intend to wait on */
560 val = val & mask;
561
562 while ((ufshcd_readl(hba, reg) & mask) != val) {
5cac1095 563 usleep_range(interval_us, interval_us + 50);
5a0b0cb9
SRT		 564 if (time_after(jiffies, timeout)) {
565 if ((ufshcd_readl(hba, reg) & mask) != val)
566 err = -ETIMEDOUT;
567 break;
568 }
569 }
570
571 return err;
572}
573
2fbd009b
SJ		 574/**
575 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 576 * @hba: Pointer to adapter instance
2fbd009b
SJ		 577 *
578 * Returns interrupt bit mask per version
579 */
580static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
581{
c01848c6
YG		 582 u32 intr_mask = 0;
583
584 switch (hba->ufs_version) {
585 case UFSHCI_VERSION_10:
586 intr_mask = INTERRUPT_MASK_ALL_VER_10;
587 break;
c01848c6
YG		 588 case UFSHCI_VERSION_11:
589 case UFSHCI_VERSION_20:
590 intr_mask = INTERRUPT_MASK_ALL_VER_11;
591 break;
c01848c6
YG		 592 case UFSHCI_VERSION_21:
593 default:
594 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 595 break;
c01848c6
YG		 596 }
597
598 return intr_mask;
2fbd009b
SJ		 599}
600
7a3e97b0
SY		 601/**
602 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 603 * @hba: Pointer to adapter instance
7a3e97b0
SY		 604 *
605 * Returns UFSHCI version supported by the controller
606 */
607static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
608{
0263bcd0
YG		 609 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
610 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 611
b873a275 612 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 613}
614
615/**
616 * ufshcd_is_device_present - Check if any device connected to
617 * the host controller
5c0c28a8 618 * @hba: pointer to adapter instance
7a3e97b0 619 *
c9e6010b 620 * Returns true if device present, false if no device detected
7a3e97b0 621 */
c9e6010b 622static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 623{
5c0c28a8 624 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 625 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 626}
627
628/**
629 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 630 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 631 *
632 * This function is used to get the OCS field from UTRD
633 * Returns the OCS field in the UTRD
634 */
635static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
636{
e8c8e82a 637 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 638}
639
7a3e97b0
SY		 640/**
641 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
642 * @hba: per adapter instance
643 * @pos: position of the bit to be cleared
644 */
645static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
646{
87183841
AA		 647 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
648 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
649 else
650 ufshcd_writel(hba, ~(1 << pos),
651 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 652}
653
654/**
655 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
656 * @hba: per adapter instance
657 * @pos: position of the bit to be cleared
658 */
659static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
660{
87183841
AA		 661 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
662 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
663 else
664 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 665}
666
a48353f6
YG		 667/**
668 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
669 * @hba: per adapter instance
670 * @tag: position of the bit to be cleared
671 */
672static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
673{
674 __clear_bit(tag, &hba->outstanding_reqs);
675}
676
7a3e97b0
SY		 677/**
678 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
679 * @reg: Register value of host controller status
680 *
681 * Returns integer, 0 on Success and positive value if failed
682 */
683static inline int ufshcd_get_lists_status(u32 reg)
684{
6cf16115 685 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 686}
687
688/**
689 * ufshcd_get_uic_cmd_result - Get the UIC command result
690 * @hba: Pointer to adapter instance
691 *
692 * This function gets the result of UIC command completion
693 * Returns 0 on success, non zero value on error
694 */
695static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
696{
b873a275 697 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 698 MASK_UIC_COMMAND_RESULT;
699}
700
12b4fdb4
SJ		 701/**
702 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
703 * @hba: Pointer to adapter instance
704 *
705 * This function gets UIC command argument3
706 * Returns 0 on success, non zero value on error
707 */
708static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
709{
710 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
711}
712
7a3e97b0 713/**
5a0b0cb9 714 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 715 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 716 */
717static inline int
5a0b0cb9 718ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 719{
5a0b0cb9 720 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 721}
722
723/**
724 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
725 * @ucd_rsp_ptr: pointer to response UPIU
726 *
727 * This function gets the response status and scsi_status from response UPIU
728 * Returns the response result code.
729 */
730static inline int
731ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
732{
733 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
734}
735
1c2623c5
SJ		 736/*
737 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
738 * from response UPIU
739 * @ucd_rsp_ptr: pointer to response UPIU
740 *
741 * Return the data segment length.
742 */
743static inline unsigned int
744ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
745{
746 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
747 MASK_RSP_UPIU_DATA_SEG_LEN;
748}
749
66ec6d59
SRT		 750/**
751 * ufshcd_is_exception_event - Check if the device raised an exception event
752 * @ucd_rsp_ptr: pointer to response UPIU
753 *
754 * The function checks if the device raised an exception event indicated in
755 * the Device Information field of response UPIU.
756 *
757 * Returns true if exception is raised, false otherwise.
758 */
759static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
760{
761 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
762 MASK_RSP_EXCEPTION_EVENT ? true : false;
763}
764
7a3e97b0 765/**
7d568652 766 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 767 * @hba: per adapter instance
7a3e97b0
SY		 768 */
769static inline void
7d568652 770ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 771{
7d568652
SJ		 772 ufshcd_writel(hba, INT_AGGR_ENABLE |
773 INT_AGGR_COUNTER_AND_TIMER_RESET,
774 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
775}
776
777/**
778 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
779 * @hba: per adapter instance
780 * @cnt: Interrupt aggregation counter threshold
781 * @tmout: Interrupt aggregation timeout value
782 */
783static inline void
784ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
785{
786 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
787 INT_AGGR_COUNTER_THLD_VAL(cnt) |
788 INT_AGGR_TIMEOUT_VAL(tmout),
789 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 790}
791
b852190e
YG		 792/**
793 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
794 * @hba: per adapter instance
795 */
796static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
797{
798 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
799}
800
7a3e97b0
SY		 801/**
802 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
803 * When run-stop registers are set to 1, it indicates the
804 * host controller that it can process the requests
805 * @hba: per adapter instance
806 */
807static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
808{
b873a275
SJ		 809 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
810 REG_UTP_TASK_REQ_LIST_RUN_STOP);
811 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
812 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 813}
814
7a3e97b0
SY		 815/**
816 * ufshcd_hba_start - Start controller initialization sequence
817 * @hba: per adapter instance
818 */
819static inline void ufshcd_hba_start(struct ufs_hba *hba)
820{
b873a275 821 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 822}
823
824/**
825 * ufshcd_is_hba_active - Get controller state
826 * @hba: per adapter instance
827 *
c9e6010b 828 * Returns false if controller is active, true otherwise
7a3e97b0 829 */
c9e6010b 830static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 831{
4a8eec2b
TK		 832 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
833 ? false : true;
7a3e97b0
SY		 834}
835
37113106
YG		 836u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
837{
838 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
839 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
840 (hba->ufs_version == UFSHCI_VERSION_11))
841 return UFS_UNIPRO_VER_1_41;
842 else
843 return UFS_UNIPRO_VER_1_6;
844}
845EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
846
847static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
848{
849 /*
850 * If both host and device support UniPro ver1.6 or later, PA layer
851 * parameters tuning happens during link startup itself.
852 *
853 * We can manually tune PA layer parameters if either host or device
854 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
855 * logic simple, we will only do manual tuning if local unipro version
856 * doesn't support ver1.6 or later.
857 */
858 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
859 return true;
860 else
861 return false;
862}
863
394b949f
SJ		 864/**
865 * ufshcd_set_clk_freq - set UFS controller clock frequencies
866 * @hba: per adapter instance
867 * @scale_up: If True, set max possible frequency othewise set low frequency
868 *
869 * Returns 0 if successful
870 * Returns < 0 for any other errors
871 */
872static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 873{
874 int ret = 0;
875 struct ufs_clk_info *clki;
876 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 877
566ec9ad 878 if (list_empty(head))
a3cd5ec5 879 goto out;
880
a3cd5ec5 881 list_for_each_entry(clki, head, list) {
882 if (!IS_ERR_OR_NULL(clki->clk)) {
883 if (scale_up && clki->max_freq) {
884 if (clki->curr_freq == clki->max_freq)
885 continue;
886
a3cd5ec5 887 ret = clk_set_rate(clki->clk, clki->max_freq);
888 if (ret) {
889 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
890 __func__, clki->name,
891 clki->max_freq, ret);
892 break;
893 }
894 trace_ufshcd_clk_scaling(dev_name(hba->dev),
895 "scaled up", clki->name,
896 clki->curr_freq,
897 clki->max_freq);
898
899 clki->curr_freq = clki->max_freq;
900
901 } else if (!scale_up && clki->min_freq) {
902 if (clki->curr_freq == clki->min_freq)
903 continue;
904
a3cd5ec5 905 ret = clk_set_rate(clki->clk, clki->min_freq);
906 if (ret) {
907 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
908 __func__, clki->name,
909 clki->min_freq, ret);
910 break;
911 }
912 trace_ufshcd_clk_scaling(dev_name(hba->dev),
913 "scaled down", clki->name,
914 clki->curr_freq,
915 clki->min_freq);
916 clki->curr_freq = clki->min_freq;
917 }
918 }
919 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
920 clki->name, clk_get_rate(clki->clk));
921 }
922
394b949f
SJ		 923out:
924 return ret;
925}
926
927/**
928 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
929 * @hba: per adapter instance
930 * @scale_up: True if scaling up and false if scaling down
931 *
932 * Returns 0 if successful
933 * Returns < 0 for any other errors
934 */
935static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
936{
937 int ret = 0;
938 ktime_t start = ktime_get();
939
940 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
941 if (ret)
942 goto out;
943
944 ret = ufshcd_set_clk_freq(hba, scale_up);
945 if (ret)
946 goto out;
947
a3cd5ec5 948 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 949 if (ret)
950 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 951
952out:
394b949f 953 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 954 (scale_up ? "up" : "down"),
955 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
956 return ret;
957}
958
959/**
960 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
961 * @hba: per adapter instance
962 * @scale_up: True if scaling up and false if scaling down
963 *
964 * Returns true if scaling is required, false otherwise.
965 */
966static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
967 bool scale_up)
968{
969 struct ufs_clk_info *clki;
970 struct list_head *head = &hba->clk_list_head;
971
566ec9ad 972 if (list_empty(head))
a3cd5ec5 973 return false;
974
975 list_for_each_entry(clki, head, list) {
976 if (!IS_ERR_OR_NULL(clki->clk)) {
977 if (scale_up && clki->max_freq) {
978 if (clki->curr_freq == clki->max_freq)
979 continue;
980 return true;
981 } else if (!scale_up && clki->min_freq) {
982 if (clki->curr_freq == clki->min_freq)
983 continue;
984 return true;
985 }
986 }
987 }
988
989 return false;
990}
991
992static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
993 u64 wait_timeout_us)
994{
995 unsigned long flags;
996 int ret = 0;
997 u32 tm_doorbell;
998 u32 tr_doorbell;
999 bool timeout = false, do_last_check = false;
1000 ktime_t start;
1001
1002 ufshcd_hold(hba, false);
1003 spin_lock_irqsave(hba->host->host_lock, flags);
1004 /*
1005 * Wait for all the outstanding tasks/transfer requests.
1006 * Verify by checking the doorbell registers are clear.
1007 */
1008 start = ktime_get();
1009 do {
1010 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1011 ret = -EBUSY;
1012 goto out;
1013 }
1014
1015 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1016 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1017 if (!tm_doorbell && !tr_doorbell) {
1018 timeout = false;
1019 break;
1020 } else if (do_last_check) {
1021 break;
1022 }
1023
1024 spin_unlock_irqrestore(hba->host->host_lock, flags);
1025 schedule();
1026 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1027 wait_timeout_us) {
1028 timeout = true;
1029 /*
1030 * We might have scheduled out for long time so make
1031 * sure to check if doorbells are cleared by this time
1032 * or not.
1033 */
1034 do_last_check = true;
1035 }
1036 spin_lock_irqsave(hba->host->host_lock, flags);
1037 } while (tm_doorbell || tr_doorbell);
1038
1039 if (timeout) {
1040 dev_err(hba->dev,
1041 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1042 __func__, tm_doorbell, tr_doorbell);
1043 ret = -EBUSY;
1044 }
1045out:
1046 spin_unlock_irqrestore(hba->host->host_lock, flags);
1047 ufshcd_release(hba);
1048 return ret;
1049}
1050
1051/**
1052 * ufshcd_scale_gear - scale up/down UFS gear
1053 * @hba: per adapter instance
1054 * @scale_up: True for scaling up gear and false for scaling down
1055 *
1056 * Returns 0 for success,
1057 * Returns -EBUSY if scaling can't happen at this time
1058 * Returns non-zero for any other errors
1059 */
1060static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1061{
1062 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1063 int ret = 0;
1064 struct ufs_pa_layer_attr new_pwr_info;
1065
1066 if (scale_up) {
1067 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1068 sizeof(struct ufs_pa_layer_attr));
1069 } else {
1070 memcpy(&new_pwr_info, &hba->pwr_info,
1071 sizeof(struct ufs_pa_layer_attr));
1072
1073 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1074 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1075 /* save the current power mode */
1076 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1077 &hba->pwr_info,
1078 sizeof(struct ufs_pa_layer_attr));
1079
1080 /* scale down gear */
1081 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1082 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1083 }
1084 }
1085
1086 /* check if the power mode needs to be changed or not? */
6a9df818 1087 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1088 if (ret)
1089 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1090 __func__, ret,
1091 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1092 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1093
1094 return ret;
1095}
1096
1097static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1098{
1099 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1100 int ret = 0;
1101 /*
1102 * make sure that there are no outstanding requests when
1103 * clock scaling is in progress
1104 */
38135535 1105 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1106 down_write(&hba->clk_scaling_lock);
1107 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1108 ret = -EBUSY;
1109 up_write(&hba->clk_scaling_lock);
38135535 1110 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1111 }
1112
1113 return ret;
1114}
1115
1116static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1117{
1118 up_write(&hba->clk_scaling_lock);
38135535 1119 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1120}
1121
1122/**
1123 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1124 * @hba: per adapter instance
1125 * @scale_up: True for scaling up and false for scalin down
1126 *
1127 * Returns 0 for success,
1128 * Returns -EBUSY if scaling can't happen at this time
1129 * Returns non-zero for any other errors
1130 */
1131static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1132{
1133 int ret = 0;
1134
401f1e44 1135 /* let's not get into low power until clock scaling is completed */
1136 ufshcd_hold(hba, false);
1137
a3cd5ec5 1138 ret = ufshcd_clock_scaling_prepare(hba);
1139 if (ret)
394b949f 1140 goto out;
a3cd5ec5 1141
1142 /* scale down the gear before scaling down clocks */
1143 if (!scale_up) {
1144 ret = ufshcd_scale_gear(hba, false);
1145 if (ret)
394b949f 1146 goto out_unprepare;
a3cd5ec5 1147 }
1148
1149 ret = ufshcd_scale_clks(hba, scale_up);
1150 if (ret) {
1151 if (!scale_up)
1152 ufshcd_scale_gear(hba, true);
394b949f 1153 goto out_unprepare;
a3cd5ec5 1154 }
1155
1156 /* scale up the gear after scaling up clocks */
1157 if (scale_up) {
1158 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1159 if (ret) {
a3cd5ec5 1160 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1161 goto out_unprepare;
1162 }
a3cd5ec5 1163 }
1164
3d17b9b5
AD		 1165 /* Enable Write Booster if we have scaled up else disable it */
1166 up_write(&hba->clk_scaling_lock);
1167 ufshcd_wb_ctrl(hba, scale_up);
1168 down_write(&hba->clk_scaling_lock);
1169
394b949f 1170out_unprepare:
a3cd5ec5 1171 ufshcd_clock_scaling_unprepare(hba);
394b949f 1172out:
401f1e44 1173 ufshcd_release(hba);
a3cd5ec5 1174 return ret;
1175}
1176
401f1e44 1177static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1178{
1179 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1180 clk_scaling.suspend_work);
1181 unsigned long irq_flags;
1182
1183 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1184 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1185 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1186 return;
1187 }
1188 hba->clk_scaling.is_suspended = true;
1189 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1190
1191 __ufshcd_suspend_clkscaling(hba);
1192}
1193
1194static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1195{
1196 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1197 clk_scaling.resume_work);
1198 unsigned long irq_flags;
1199
1200 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1201 if (!hba->clk_scaling.is_suspended) {
1202 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1203 return;
1204 }
1205 hba->clk_scaling.is_suspended = false;
1206 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1207
1208 devfreq_resume_device(hba->devfreq);
1209}
1210
a3cd5ec5 1211static int ufshcd_devfreq_target(struct device *dev,
1212 unsigned long *freq, u32 flags)
1213{
1214 int ret = 0;
1215 struct ufs_hba *hba = dev_get_drvdata(dev);
1216 ktime_t start;
401f1e44 1217 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1218 struct list_head *clk_list = &hba->clk_list_head;
1219 struct ufs_clk_info *clki;
a3cd5ec5 1220 unsigned long irq_flags;
1221
1222 if (!ufshcd_is_clkscaling_supported(hba))
1223 return -EINVAL;
1224
91831d33
AD		 1225 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1226 /* Override with the closest supported frequency */
1227 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1228 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1229 if (ufshcd_eh_in_progress(hba)) {
1230 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1231 return 0;
1232 }
1233
401f1e44 1234 if (!hba->clk_scaling.active_reqs)
1235 sched_clk_scaling_suspend_work = true;
1236
092b4558
BA		 1237 if (list_empty(clk_list)) {
1238 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1239 goto out;
1240 }
1241
91831d33 1242 /* Decide based on the rounded-off frequency and update */
092b4558 1243 scale_up = (*freq == clki->max_freq) ? true : false;
91831d33
AD		 1244 if (!scale_up)
1245 *freq = clki->min_freq;
1246 /* Update the frequency */
401f1e44 1247 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1248 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1249 ret = 0;
1250 goto out; /* no state change required */
a3cd5ec5 1251 }
1252 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1253
1254 start = ktime_get();
a3cd5ec5 1255 ret = ufshcd_devfreq_scale(hba, scale_up);
1256
a3cd5ec5 1257 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1258 (scale_up ? "up" : "down"),
1259 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1260
401f1e44 1261out:
1262 if (sched_clk_scaling_suspend_work)
1263 queue_work(hba->clk_scaling.workq,
1264 &hba->clk_scaling.suspend_work);
1265
a3cd5ec5 1266 return ret;
1267}
1268
7252a360
BVA		 1269static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1270{
1271 int *busy = priv;
1272
1273 WARN_ON_ONCE(reserved);
1274 (*busy)++;
1275 return false;
1276}
1277
1278/* Whether or not any tag is in use by a request that is in progress. */
1279static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1280{
1281 struct request_queue *q = hba->cmd_queue;
1282 int busy = 0;
1283
1284 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1285 return busy;
1286}
a3cd5ec5 1287
1288static int ufshcd_devfreq_get_dev_status(struct device *dev,
1289 struct devfreq_dev_status *stat)
1290{
1291 struct ufs_hba *hba = dev_get_drvdata(dev);
1292 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1293 unsigned long flags;
91831d33
AD		 1294 struct list_head *clk_list = &hba->clk_list_head;
1295 struct ufs_clk_info *clki;
a3cd5ec5 1296
1297 if (!ufshcd_is_clkscaling_supported(hba))
1298 return -EINVAL;
1299
1300 memset(stat, 0, sizeof(*stat));
1301
1302 spin_lock_irqsave(hba->host->host_lock, flags);
1303 if (!scaling->window_start_t)
1304 goto start_window;
1305
91831d33
AD		 1306 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1307 /*
1308 * If current frequency is 0, then the ondemand governor considers
1309 * there's no initial frequency set. And it always requests to set
1310 * to max. frequency.
1311 */
1312 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1313 if (scaling->is_busy_started)
1314 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1315 scaling->busy_start_t));
1316
1317 stat->total_time = jiffies_to_usecs((long)jiffies -
1318 (long)scaling->window_start_t);
1319 stat->busy_time = scaling->tot_busy_t;
1320start_window:
1321 scaling->window_start_t = jiffies;
1322 scaling->tot_busy_t = 0;
1323
1324 if (hba->outstanding_reqs) {
1325 scaling->busy_start_t = ktime_get();
1326 scaling->is_busy_started = true;
1327 } else {
1328 scaling->busy_start_t = 0;
1329 scaling->is_busy_started = false;
1330 }
1331 spin_unlock_irqrestore(hba->host->host_lock, flags);
1332 return 0;
1333}
1334
deac444f
BA		 1335static int ufshcd_devfreq_init(struct ufs_hba *hba)
1336{
092b4558
BA		 1337 struct list_head *clk_list = &hba->clk_list_head;
1338 struct ufs_clk_info *clki;
deac444f
BA		 1339 struct devfreq *devfreq;
1340 int ret;
1341
092b4558
BA		 1342 /* Skip devfreq if we don't have any clocks in the list */
1343 if (list_empty(clk_list))
1344 return 0;
1345
1346 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1347 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1348 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1349
90b8491c
SC		 1350 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1351 &hba->vps->ondemand_data);
092b4558 1352 devfreq = devfreq_add_device(hba->dev,
90b8491c 1353 &hba->vps->devfreq_profile,
deac444f 1354 DEVFREQ_GOV_SIMPLE_ONDEMAND,
90b8491c 1355 &hba->vps->ondemand_data);
deac444f
BA		 1356 if (IS_ERR(devfreq)) {
1357 ret = PTR_ERR(devfreq);
1358 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1359
1360 dev_pm_opp_remove(hba->dev, clki->min_freq);
1361 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1362 return ret;
1363 }
1364
1365 hba->devfreq = devfreq;
1366
1367 return 0;
1368}
1369
092b4558
BA		 1370static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1371{
1372 struct list_head *clk_list = &hba->clk_list_head;
1373 struct ufs_clk_info *clki;
1374
1375 if (!hba->devfreq)
1376 return;
1377
1378 devfreq_remove_device(hba->devfreq);
1379 hba->devfreq = NULL;
1380
1381 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1382 dev_pm_opp_remove(hba->dev, clki->min_freq);
1383 dev_pm_opp_remove(hba->dev, clki->max_freq);
1384}
1385
401f1e44 1386static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1387{
1388 unsigned long flags;
1389
1390 devfreq_suspend_device(hba->devfreq);
1391 spin_lock_irqsave(hba->host->host_lock, flags);
1392 hba->clk_scaling.window_start_t = 0;
1393 spin_unlock_irqrestore(hba->host->host_lock, flags);
1394}
a3cd5ec5 1395
a508253d
GB		 1396static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1397{
401f1e44 1398 unsigned long flags;
1399 bool suspend = false;
1400
fcb0c4b0
ST		 1401 if (!ufshcd_is_clkscaling_supported(hba))
1402 return;
1403
401f1e44 1404 spin_lock_irqsave(hba->host->host_lock, flags);
1405 if (!hba->clk_scaling.is_suspended) {
1406 suspend = true;
1407 hba->clk_scaling.is_suspended = true;
1408 }
1409 spin_unlock_irqrestore(hba->host->host_lock, flags);
1410
1411 if (suspend)
1412 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1413}
1414
1415static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1416{
401f1e44 1417 unsigned long flags;
1418 bool resume = false;
1419
1420 if (!ufshcd_is_clkscaling_supported(hba))
1421 return;
1422
1423 spin_lock_irqsave(hba->host->host_lock, flags);
1424 if (hba->clk_scaling.is_suspended) {
1425 resume = true;
1426 hba->clk_scaling.is_suspended = false;
1427 }
1428 spin_unlock_irqrestore(hba->host->host_lock, flags);
1429
1430 if (resume)
1431 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1432}
1433
1434static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1435 struct device_attribute *attr, char *buf)
1436{
1437 struct ufs_hba *hba = dev_get_drvdata(dev);
1438
1439 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1440}
1441
1442static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1443 struct device_attribute *attr, const char *buf, size_t count)
1444{
1445 struct ufs_hba *hba = dev_get_drvdata(dev);
1446 u32 value;
1447 int err;
1448
1449 if (kstrtou32(buf, 0, &value))
1450 return -EINVAL;
1451
1452 value = !!value;
1453 if (value == hba->clk_scaling.is_allowed)
1454 goto out;
1455
1456 pm_runtime_get_sync(hba->dev);
1457 ufshcd_hold(hba, false);
1458
401f1e44 1459 cancel_work_sync(&hba->clk_scaling.suspend_work);
1460 cancel_work_sync(&hba->clk_scaling.resume_work);
1461
1462 hba->clk_scaling.is_allowed = value;
1463
fcb0c4b0
ST		 1464 if (value) {
1465 ufshcd_resume_clkscaling(hba);
1466 } else {
1467 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1468 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1469 if (err)
1470 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1471 __func__, err);
1472 }
fcb0c4b0
ST		 1473
1474 ufshcd_release(hba);
1475 pm_runtime_put_sync(hba->dev);
1476out:
1477 return count;
a508253d
GB		 1478}
1479
a3cd5ec5 1480static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1481{
1482 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1483 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1484 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1485 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1486 hba->clk_scaling.enable_attr.attr.mode = 0644;
1487 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1488 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1489}
1490
1ab27c9c
ST		 1491static void ufshcd_ungate_work(struct work_struct *work)
1492{
1493 int ret;
1494 unsigned long flags;
1495 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1496 clk_gating.ungate_work);
1497
1498 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1499
1500 spin_lock_irqsave(hba->host->host_lock, flags);
1501 if (hba->clk_gating.state == CLKS_ON) {
1502 spin_unlock_irqrestore(hba->host->host_lock, flags);
1503 goto unblock_reqs;
1504 }
1505
1506 spin_unlock_irqrestore(hba->host->host_lock, flags);
1507 ufshcd_setup_clocks(hba, true);
1508
8b0bbf00
SC		 1509 ufshcd_enable_irq(hba);
1510
1ab27c9c
ST		 1511 /* Exit from hibern8 */
1512 if (ufshcd_can_hibern8_during_gating(hba)) {
1513 /* Prevent gating in this path */
1514 hba->clk_gating.is_suspended = true;
1515 if (ufshcd_is_link_hibern8(hba)) {
1516 ret = ufshcd_uic_hibern8_exit(hba);
1517 if (ret)
1518 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1519 __func__, ret);
1520 else
1521 ufshcd_set_link_active(hba);
1522 }
1523 hba->clk_gating.is_suspended = false;
1524 }
1525unblock_reqs:
38135535 1526 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1527}
1528
1529/**
1530 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1531 * Also, exit from hibern8 mode and set the link as active.
1532 * @hba: per adapter instance
1533 * @async: This indicates whether caller should ungate clocks asynchronously.
1534 */
1535int ufshcd_hold(struct ufs_hba *hba, bool async)
1536{
1537 int rc = 0;
1538 unsigned long flags;
1539
1540 if (!ufshcd_is_clkgating_allowed(hba))
1541 goto out;
1ab27c9c
ST		 1542 spin_lock_irqsave(hba->host->host_lock, flags);
1543 hba->clk_gating.active_reqs++;
1544
53c12d0e
YG		 1545 if (ufshcd_eh_in_progress(hba)) {
1546 spin_unlock_irqrestore(hba->host->host_lock, flags);
1547 return 0;
1548 }
1549
856b3483 1550start:
1ab27c9c
ST		 1551 switch (hba->clk_gating.state) {
1552 case CLKS_ON:
f2a785ac
VG		 1553 /*
1554 * Wait for the ungate work to complete if in progress.
1555 * Though the clocks may be in ON state, the link could
1556 * still be in hibner8 state if hibern8 is allowed
1557 * during clock gating.
1558 * Make sure we exit hibern8 state also in addition to
1559 * clocks being ON.
1560 */
1561 if (ufshcd_can_hibern8_during_gating(hba) &&
1562 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1563 if (async) {
1564 rc = -EAGAIN;
1565 hba->clk_gating.active_reqs--;
1566 break;
1567 }
f2a785ac
VG		 1568 spin_unlock_irqrestore(hba->host->host_lock, flags);
1569 flush_work(&hba->clk_gating.ungate_work);
1570 spin_lock_irqsave(hba->host->host_lock, flags);
1571 goto start;
1572 }
1ab27c9c
ST		 1573 break;
1574 case REQ_CLKS_OFF:
1575 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1576 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1577 trace_ufshcd_clk_gating(dev_name(hba->dev),
1578 hba->clk_gating.state);
1ab27c9c
ST		 1579 break;
1580 }
1581 /*
9c490d2d 1582 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1583 * currently running. Hence, fall through to cancel gating
1584 * work and to enable clocks.
1585 */
30eb2e4c 1586 /* fallthrough */
1ab27c9c 1587 case CLKS_OFF:
38135535 1588 ufshcd_scsi_block_requests(hba);
1ab27c9c 1589 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1590 trace_ufshcd_clk_gating(dev_name(hba->dev),
1591 hba->clk_gating.state);
10e5e375
VV		 1592 queue_work(hba->clk_gating.clk_gating_workq,
1593 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1594 /*
1595 * fall through to check if we should wait for this
1596 * work to be done or not.
1597 */
30eb2e4c 1598 /* fallthrough */
1ab27c9c
ST		 1599 case REQ_CLKS_ON:
1600 if (async) {
1601 rc = -EAGAIN;
1602 hba->clk_gating.active_reqs--;
1603 break;
1604 }
1605
1606 spin_unlock_irqrestore(hba->host->host_lock, flags);
1607 flush_work(&hba->clk_gating.ungate_work);
1608 /* Make sure state is CLKS_ON before returning */
856b3483 1609 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1610 goto start;
1611 default:
1612 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1613 __func__, hba->clk_gating.state);
1614 break;
1615 }
1616 spin_unlock_irqrestore(hba->host->host_lock, flags);
1617out:
1618 return rc;
1619}
6e3fd44d 1620EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1621
1622static void ufshcd_gate_work(struct work_struct *work)
1623{
1624 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1625 clk_gating.gate_work.work);
1626 unsigned long flags;
1627
1628 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1629 /*
1630 * In case you are here to cancel this work the gating state
1631 * would be marked as REQ_CLKS_ON. In this case save time by
1632 * skipping the gating work and exit after changing the clock
1633 * state to CLKS_ON.
1634 */
1635 if (hba->clk_gating.is_suspended ||
18f01374 1636 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1637 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1638 trace_ufshcd_clk_gating(dev_name(hba->dev),
1639 hba->clk_gating.state);
1ab27c9c
ST		 1640 goto rel_lock;
1641 }
1642
1643 if (hba->clk_gating.active_reqs
1644 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1645 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1ab27c9c
ST		 1646 || hba->active_uic_cmd || hba->uic_async_done)
1647 goto rel_lock;
1648
1649 spin_unlock_irqrestore(hba->host->host_lock, flags);
1650
1651 /* put the link into hibern8 mode before turning off clocks */
1652 if (ufshcd_can_hibern8_during_gating(hba)) {
1653 if (ufshcd_uic_hibern8_enter(hba)) {
1654 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1655 trace_ufshcd_clk_gating(dev_name(hba->dev),
1656 hba->clk_gating.state);
1ab27c9c
ST		 1657 goto out;
1658 }
1659 ufshcd_set_link_hibern8(hba);
1660 }
1661
8b0bbf00
SC		 1662 ufshcd_disable_irq(hba);
1663
1ab27c9c
ST		 1664 if (!ufshcd_is_link_active(hba))
1665 ufshcd_setup_clocks(hba, false);
1666 else
1667 /* If link is active, device ref_clk can't be switched off */
1668 __ufshcd_setup_clocks(hba, false, true);
1669
1670 /*
1671 * In case you are here to cancel this work the gating state
1672 * would be marked as REQ_CLKS_ON. In this case keep the state
1673 * as REQ_CLKS_ON which would anyway imply that clocks are off
1674 * and a request to turn them on is pending. By doing this way,
1675 * we keep the state machine in tact and this would ultimately
1676 * prevent from doing cancel work multiple times when there are
1677 * new requests arriving before the current cancel work is done.
1678 */
1679 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1680 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1681 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1682 trace_ufshcd_clk_gating(dev_name(hba->dev),
1683 hba->clk_gating.state);
1684 }
1ab27c9c
ST		 1685rel_lock:
1686 spin_unlock_irqrestore(hba->host->host_lock, flags);
1687out:
1688 return;
1689}
1690
1691/* host lock must be held before calling this variant */
1692static void __ufshcd_release(struct ufs_hba *hba)
1693{
1694 if (!ufshcd_is_clkgating_allowed(hba))
1695 return;
1696
1697 hba->clk_gating.active_reqs--;
1698
1699 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1700 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1701 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
53c12d0e
YG		 1702 || hba->active_uic_cmd || hba->uic_async_done
1703 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1704 return;
1705
1706 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1707 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1708 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1709 &hba->clk_gating.gate_work,
1710 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1711}
1712
1713void ufshcd_release(struct ufs_hba *hba)
1714{
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(hba->host->host_lock, flags);
1718 __ufshcd_release(hba);
1719 spin_unlock_irqrestore(hba->host->host_lock, flags);
1720}
6e3fd44d 1721EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1722
1723static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1724 struct device_attribute *attr, char *buf)
1725{
1726 struct ufs_hba *hba = dev_get_drvdata(dev);
1727
1728 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1729}
1730
1731static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1732 struct device_attribute *attr, const char *buf, size_t count)
1733{
1734 struct ufs_hba *hba = dev_get_drvdata(dev);
1735 unsigned long flags, value;
1736
1737 if (kstrtoul(buf, 0, &value))
1738 return -EINVAL;
1739
1740 spin_lock_irqsave(hba->host->host_lock, flags);
1741 hba->clk_gating.delay_ms = value;
1742 spin_unlock_irqrestore(hba->host->host_lock, flags);
1743 return count;
1744}
1745
b427411a
ST		 1746static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1747 struct device_attribute *attr, char *buf)
1748{
1749 struct ufs_hba *hba = dev_get_drvdata(dev);
1750
1751 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1752}
1753
1754static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1755 struct device_attribute *attr, const char *buf, size_t count)
1756{
1757 struct ufs_hba *hba = dev_get_drvdata(dev);
1758 unsigned long flags;
1759 u32 value;
1760
1761 if (kstrtou32(buf, 0, &value))
1762 return -EINVAL;
1763
1764 value = !!value;
1765 if (value == hba->clk_gating.is_enabled)
1766 goto out;
1767
1768 if (value) {
1769 ufshcd_release(hba);
1770 } else {
1771 spin_lock_irqsave(hba->host->host_lock, flags);
1772 hba->clk_gating.active_reqs++;
1773 spin_unlock_irqrestore(hba->host->host_lock, flags);
1774 }
1775
1776 hba->clk_gating.is_enabled = value;
1777out:
1778 return count;
1779}
1780
eebcc196
VG		 1781static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1782{
1783 char wq_name[sizeof("ufs_clkscaling_00")];
1784
1785 if (!ufshcd_is_clkscaling_supported(hba))
1786 return;
1787
1788 INIT_WORK(&hba->clk_scaling.suspend_work,
1789 ufshcd_clk_scaling_suspend_work);
1790 INIT_WORK(&hba->clk_scaling.resume_work,
1791 ufshcd_clk_scaling_resume_work);
1792
1793 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1794 hba->host->host_no);
1795 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1796
1797 ufshcd_clkscaling_init_sysfs(hba);
1798}
1799
1800static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1801{
1802 if (!ufshcd_is_clkscaling_supported(hba))
1803 return;
1804
1805 destroy_workqueue(hba->clk_scaling.workq);
1806 ufshcd_devfreq_remove(hba);
1807}
1808
1ab27c9c
ST		 1809static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1810{
10e5e375
VV		 1811 char wq_name[sizeof("ufs_clk_gating_00")];
1812
1ab27c9c
ST		 1813 if (!ufshcd_is_clkgating_allowed(hba))
1814 return;
1815
1816 hba->clk_gating.delay_ms = 150;
1817 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1818 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1819
10e5e375
VV		 1820 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1821 hba->host->host_no);
1822 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1823 WQ_MEM_RECLAIM);
1824
b427411a
ST		 1825 hba->clk_gating.is_enabled = true;
1826
1ab27c9c
ST		 1827 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1828 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1829 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1830 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1831 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1832 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1833 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1834
1835 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1836 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1837 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1838 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1839 hba->clk_gating.enable_attr.attr.mode = 0644;
1840 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1841 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1842}
1843
1844static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1845{
1846 if (!ufshcd_is_clkgating_allowed(hba))
1847 return;
1848 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1849 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1850 cancel_work_sync(&hba->clk_gating.ungate_work);
1851 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1852 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1853}
1854
856b3483
ST		 1855/* Must be called with host lock acquired */
1856static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1857{
401f1e44 1858 bool queue_resume_work = false;
1859
fcb0c4b0 1860 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1861 return;
1862
401f1e44 1863 if (!hba->clk_scaling.active_reqs++)
1864 queue_resume_work = true;
1865
1866 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1867 return;
1868
1869 if (queue_resume_work)
1870 queue_work(hba->clk_scaling.workq,
1871 &hba->clk_scaling.resume_work);
1872
1873 if (!hba->clk_scaling.window_start_t) {
1874 hba->clk_scaling.window_start_t = jiffies;
1875 hba->clk_scaling.tot_busy_t = 0;
1876 hba->clk_scaling.is_busy_started = false;
1877 }
1878
856b3483
ST		 1879 if (!hba->clk_scaling.is_busy_started) {
1880 hba->clk_scaling.busy_start_t = ktime_get();
1881 hba->clk_scaling.is_busy_started = true;
1882 }
1883}
1884
1885static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1886{
1887 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1888
fcb0c4b0 1889 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1890 return;
1891
1892 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1893 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1894 scaling->busy_start_t));
8b0e1953 1895 scaling->busy_start_t = 0;
856b3483
ST		 1896 scaling->is_busy_started = false;
1897 }
1898}
7a3e97b0
SY		 1899/**
1900 * ufshcd_send_command - Send SCSI or device management commands
1901 * @hba: per adapter instance
1902 * @task_tag: Task tag of the command
1903 */
1904static inline
1905void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1906{
ff8e20c6 1907 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1908 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
eacf36f5 1909 ufshcd_add_command_trace(hba, task_tag, "send");
856b3483 1910 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1911 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1912 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1913 /* Make sure that doorbell is committed immediately */
1914 wmb();
7a3e97b0
SY		 1915}
1916
1917/**
1918 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1919 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1920 */
1921static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1922{
1923 int len;
1c2623c5
SJ		 1924 if (lrbp->sense_buffer &&
1925 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1926 int len_to_copy;
1927
5a0b0cb9 1928 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 1929 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 1930
09a5a24f
AA		 1931 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1932 len_to_copy);
7a3e97b0
SY		 1933 }
1934}
1935
68078d5c
DR		 1936/**
1937 * ufshcd_copy_query_response() - Copy the Query Response and the data
1938 * descriptor
1939 * @hba: per adapter instance
8aa29f19 1940 * @lrbp: pointer to local reference block
68078d5c
DR		 1941 */
1942static
c6d4a831 1943int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1944{
1945 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1946
68078d5c 1947 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1948
68078d5c 1949 /* Get the descriptor */
1c90836f
AA		 1950 if (hba->dev_cmd.query.descriptor &&
1951 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1952 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1953 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1954 u16 resp_len;
1955 u16 buf_len;
68078d5c
DR		 1956
1957 /* data segment length */
c6d4a831 1958 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1959 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1960 buf_len = be16_to_cpu(
1961 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1962 if (likely(buf_len >= resp_len)) {
1963 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1964 } else {
1965 dev_warn(hba->dev,
3d4881d1
BH		 1966 "%s: rsp size %d is bigger than buffer size %d",
1967 __func__, resp_len, buf_len);
c6d4a831
DR		 1968 return -EINVAL;
1969 }
68078d5c 1970 }
c6d4a831
DR		 1971
1972 return 0;
68078d5c
DR		 1973}
1974
7a3e97b0
SY		 1975/**
1976 * ufshcd_hba_capabilities - Read controller capabilities
1977 * @hba: per adapter instance
1978 */
1979static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1980{
b873a275 1981 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1982
1983 /* nutrs and nutmrs are 0 based values */
1984 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1985 hba->nutmrs =
1986 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1987}
1988
1989/**
6ccf44fe
SJ		 1990 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1991 * to accept UIC commands
7a3e97b0 1992 * @hba: per adapter instance
6ccf44fe
SJ		 1993 * Return true on success, else false
1994 */
1995static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1996{
1997 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1998 return true;
1999 else
2000 return false;
2001}
2002
53b3d9c3
SJ		 2003/**
2004 * ufshcd_get_upmcrs - Get the power mode change request status
2005 * @hba: Pointer to adapter instance
2006 *
2007 * This function gets the UPMCRS field of HCS register
2008 * Returns value of UPMCRS field
2009 */
2010static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2011{
2012 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2013}
2014
6ccf44fe
SJ		 2015/**
2016 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
2017 * @hba: per adapter instance
2018 * @uic_cmd: UIC command
2019 *
2020 * Mutex must be held.
7a3e97b0
SY		 2021 */
2022static inline void
6ccf44fe 2023ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2024{
6ccf44fe
SJ		 2025 WARN_ON(hba->active_uic_cmd);
2026
2027 hba->active_uic_cmd = uic_cmd;
2028
7a3e97b0 2029 /* Write Args */
6ccf44fe
SJ		 2030 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2031 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2032 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 2033
2034 /* Write UIC Cmd */
6ccf44fe 2035 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2036 REG_UIC_COMMAND);
7a3e97b0
SY		 2037}
2038
6ccf44fe
SJ		 2039/**
2040 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2041 * @hba: per adapter instance
8aa29f19 2042 * @uic_cmd: UIC command
6ccf44fe
SJ		 2043 *
2044 * Must be called with mutex held.
2045 * Returns 0 only if success.
2046 */
2047static int
2048ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2049{
2050 int ret;
2051 unsigned long flags;
2052
2053 if (wait_for_completion_timeout(&uic_cmd->done,
2054 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2055 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2056 else
2057 ret = -ETIMEDOUT;
2058
2059 spin_lock_irqsave(hba->host->host_lock, flags);
2060 hba->active_uic_cmd = NULL;
2061 spin_unlock_irqrestore(hba->host->host_lock, flags);
2062
2063 return ret;
2064}
2065
2066/**
2067 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2068 * @hba: per adapter instance
2069 * @uic_cmd: UIC command
d75f7fe4 2070 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2071 *
2072 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2073 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2074 * Returns 0 only if success.
2075 */
2076static int
d75f7fe4
YG		 2077__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2078 bool completion)
6ccf44fe 2079{
6ccf44fe
SJ		 2080 if (!ufshcd_ready_for_uic_cmd(hba)) {
2081 dev_err(hba->dev,
2082 "Controller not ready to accept UIC commands\n");
2083 return -EIO;
2084 }
2085
d75f7fe4
YG		 2086 if (completion)
2087 init_completion(&uic_cmd->done);
6ccf44fe 2088
6ccf44fe 2089 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2090
57d104c1 2091 return 0;
6ccf44fe
SJ		 2092}
2093
2094/**
2095 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2096 * @hba: per adapter instance
2097 * @uic_cmd: UIC command
2098 *
2099 * Returns 0 only if success.
2100 */
e77044c5 2101int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2102{
2103 int ret;
57d104c1 2104 unsigned long flags;
6ccf44fe 2105
1ab27c9c 2106 ufshcd_hold(hba, false);
6ccf44fe 2107 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2108 ufshcd_add_delay_before_dme_cmd(hba);
2109
57d104c1 2110 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2111 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2112 spin_unlock_irqrestore(hba->host->host_lock, flags);
2113 if (!ret)
2114 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2115
6ccf44fe
SJ		 2116 mutex_unlock(&hba->uic_cmd_mutex);
2117
1ab27c9c 2118 ufshcd_release(hba);
6ccf44fe
SJ		 2119 return ret;
2120}
2121
7a3e97b0
SY		 2122/**
2123 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2124 * @hba: per adapter instance
2125 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2126 *
2127 * Returns 0 in case of success, non-zero value in case of failure
2128 */
75b1cc4a 2129static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2130{
2131 struct ufshcd_sg_entry *prd_table;
2132 struct scatterlist *sg;
2133 struct scsi_cmnd *cmd;
2134 int sg_segments;
2135 int i;
2136
2137 cmd = lrbp->cmd;
2138 sg_segments = scsi_dma_map(cmd);
2139 if (sg_segments < 0)
2140 return sg_segments;
2141
2142 if (sg_segments) {
26f968d7
AA		 2143
2144 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2145 lrbp->utr_descriptor_ptr->prd_table_length =
2146 cpu_to_le16((sg_segments *
2147 sizeof(struct ufshcd_sg_entry)));
2148 else
2149 lrbp->utr_descriptor_ptr->prd_table_length =
2150 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2151
2152 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2153
2154 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2155 prd_table[i].size =
2156 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2157 prd_table[i].base_addr =
2158 cpu_to_le32(lower_32_bits(sg->dma_address));
2159 prd_table[i].upper_addr =
2160 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2161 prd_table[i].reserved = 0;
7a3e97b0
SY		 2162 }
2163 } else {
2164 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2165 }
2166
2167 return 0;
2168}
2169
2170/**
2fbd009b 2171 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2172 * @hba: per adapter instance
2fbd009b 2173 * @intrs: interrupt bits
7a3e97b0 2174 */
2fbd009b 2175static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2176{
2fbd009b
SJ		 2177 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2178
2179 if (hba->ufs_version == UFSHCI_VERSION_10) {
2180 u32 rw;
2181 rw = set & INTERRUPT_MASK_RW_VER_10;
2182 set = rw | ((set ^ intrs) & intrs);
2183 } else {
2184 set |= intrs;
2185 }
2186
2187 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2188}
2189
2190/**
2191 * ufshcd_disable_intr - disable interrupts
2192 * @hba: per adapter instance
2193 * @intrs: interrupt bits
2194 */
2195static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2196{
2197 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2198
2199 if (hba->ufs_version == UFSHCI_VERSION_10) {
2200 u32 rw;
2201 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2202 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2203 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2204
2205 } else {
2206 set &= ~intrs;
7a3e97b0 2207 }
2fbd009b
SJ		 2208
2209 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2210}
2211
5a0b0cb9
SRT		 2212/**
2213 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2214 * descriptor according to request
2215 * @lrbp: pointer to local reference block
2216 * @upiu_flags: flags required in the header
2217 * @cmd_dir: requests data direction
2218 */
2219static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2220 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2221{
2222 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2223 u32 data_direction;
2224 u32 dword_0;
2225
2226 if (cmd_dir == DMA_FROM_DEVICE) {
2227 data_direction = UTP_DEVICE_TO_HOST;
2228 *upiu_flags = UPIU_CMD_FLAGS_READ;
2229 } else if (cmd_dir == DMA_TO_DEVICE) {
2230 data_direction = UTP_HOST_TO_DEVICE;
2231 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2232 } else {
2233 data_direction = UTP_NO_DATA_TRANSFER;
2234 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2235 }
2236
2237 dword_0 = data_direction | (lrbp->command_type
2238 << UPIU_COMMAND_TYPE_OFFSET);
2239 if (lrbp->intr_cmd)
2240 dword_0 |= UTP_REQ_DESC_INT_CMD;
2241
2242 /* Transfer request descriptor header fields */
2243 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2244 /* dword_1 is reserved, hence it is set to 0 */
2245 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2246 /*
2247 * assigning invalid value for command status. Controller
2248 * updates OCS on command completion, with the command
2249 * status
2250 */
2251 req_desc->header.dword_2 =
2252 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2253 /* dword_3 is reserved, hence it is set to 0 */
2254 req_desc->header.dword_3 = 0;
51047266
YG		 2255
2256 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2257}
2258
2259/**
2260 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2261 * for scsi commands
8aa29f19
BVA		 2262 * @lrbp: local reference block pointer
2263 * @upiu_flags: flags
5a0b0cb9
SRT		 2264 */
2265static
2266void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2267{
1b21b8f0 2268 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2269 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2270 unsigned short cdb_len;
5a0b0cb9
SRT		 2271
2272 /* command descriptor fields */
2273 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2274 UPIU_TRANSACTION_COMMAND, upiu_flags,
2275 lrbp->lun, lrbp->task_tag);
2276 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2277 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2278
2279 /* Total EHS length and Data segment length will be zero */
2280 ucd_req_ptr->header.dword_2 = 0;
2281
1b21b8f0 2282 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2283
1b21b8f0 2284 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2285 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2286 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2287
2288 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2289}
2290
68078d5c
DR		 2291/**
2292 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2293 * for query requsts
2294 * @hba: UFS hba
2295 * @lrbp: local reference block pointer
2296 * @upiu_flags: flags
2297 */
2298static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2299 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2300{
2301 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2302 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2303 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2304
2305 /* Query request header */
2306 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2307 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2308 lrbp->lun, lrbp->task_tag);
2309 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2310 0, query->request.query_func, 0, 0);
2311
6861285c
ZL		 2312 /* Data segment length only need for WRITE_DESC */
2313 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2314 ucd_req_ptr->header.dword_2 =
2315 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2316 else
2317 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2318
2319 /* Copy the Query Request buffer as is */
2320 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2321 QUERY_OSF_SIZE);
68078d5c
DR		 2322
2323 /* Copy the Descriptor */
c6d4a831 2324 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2325 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2326
51047266 2327 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2328}
2329
5a0b0cb9
SRT		 2330static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2331{
2332 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2333
2334 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2335
2336 /* command descriptor fields */
2337 ucd_req_ptr->header.dword_0 =
2338 UPIU_HEADER_DWORD(
2339 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2340 /* clear rest of the fields of basic header */
2341 ucd_req_ptr->header.dword_1 = 0;
2342 ucd_req_ptr->header.dword_2 = 0;
2343
2344 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2345}
2346
7a3e97b0 2347/**
300bb13f
JP		 2348 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2349 * for Device Management Purposes
8aa29f19
BVA		 2350 * @hba: per adapter instance
2351 * @lrbp: pointer to local reference block
7a3e97b0 2352 */
300bb13f 2353static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2354{
7a3e97b0 2355 u32 upiu_flags;
5a0b0cb9 2356 int ret = 0;
7a3e97b0 2357
83dc7e3d 2358 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2359 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2360 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2361 else
2362 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2363
2364 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2365 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2366 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2367 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2368 ufshcd_prepare_utp_nop_upiu(lrbp);
2369 else
2370 ret = -EINVAL;
2371
2372 return ret;
2373}
2374
2375/**
2376 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2377 * for SCSI Purposes
8aa29f19
BVA		 2378 * @hba: per adapter instance
2379 * @lrbp: pointer to local reference block
300bb13f
JP		 2380 */
2381static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2382{
2383 u32 upiu_flags;
2384 int ret = 0;
2385
83dc7e3d 2386 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2387 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2388 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2389 else
2390 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2391
2392 if (likely(lrbp->cmd)) {
2393 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2394 lrbp->cmd->sc_data_direction);
2395 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2396 } else {
2397 ret = -EINVAL;
2398 }
5a0b0cb9
SRT		 2399
2400 return ret;
7a3e97b0
SY		 2401}
2402
2a8fa600
SJ		 2403/**
2404 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2405 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2406 *
2407 * Returns SCSI W-LUN id
2408 */
2409static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2410{
2411 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2412}
2413
4d2b8d40
BVA		 2414static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2415{
2416 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2417 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2418 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2419 i * sizeof(struct utp_transfer_cmd_desc);
2420 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2421 response_upiu);
2422 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2423
2424 lrb->utr_descriptor_ptr = utrdlp + i;
2425 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2426 i * sizeof(struct utp_transfer_req_desc);
2427 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2428 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2429 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2430 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2431 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2432 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2433}
2434
7a3e97b0
SY		 2435/**
2436 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2437 * @host: SCSI host pointer
7a3e97b0 2438 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2439 *
2440 * Returns 0 for success, non-zero in case of failure
2441 */
2442static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2443{
2444 struct ufshcd_lrb *lrbp;
2445 struct ufs_hba *hba;
2446 unsigned long flags;
2447 int tag;
2448 int err = 0;
2449
2450 hba = shost_priv(host);
2451
2452 tag = cmd->request->tag;
14497328
YG		 2453 if (!ufshcd_valid_tag(hba, tag)) {
2454 dev_err(hba->dev,
2455 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2456 __func__, tag, cmd, cmd->request);
2457 BUG();
2458 }
7a3e97b0 2459
a3cd5ec5 2460 if (!down_read_trylock(&hba->clk_scaling_lock))
2461 return SCSI_MLQUEUE_HOST_BUSY;
2462
3441da7d
SRT		 2463 spin_lock_irqsave(hba->host->host_lock, flags);
2464 switch (hba->ufshcd_state) {
2465 case UFSHCD_STATE_OPERATIONAL:
2466 break;
141f8165 2467 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2468 case UFSHCD_STATE_RESET:
7a3e97b0 2469 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2470 goto out_unlock;
2471 case UFSHCD_STATE_ERROR:
2472 set_host_byte(cmd, DID_ERROR);
2473 cmd->scsi_done(cmd);
2474 goto out_unlock;
2475 default:
2476 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2477 __func__, hba->ufshcd_state);
2478 set_host_byte(cmd, DID_BAD_TARGET);
2479 cmd->scsi_done(cmd);
2480 goto out_unlock;
7a3e97b0 2481 }
53c12d0e
YG		 2482
2483 /* if error handling is in progress, don't issue commands */
2484 if (ufshcd_eh_in_progress(hba)) {
2485 set_host_byte(cmd, DID_ERROR);
2486 cmd->scsi_done(cmd);
2487 goto out_unlock;
2488 }
3441da7d 2489 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2490
7fabb77b
GB		 2491 hba->req_abort_count = 0;
2492
1ab27c9c
ST		 2493 err = ufshcd_hold(hba, true);
2494 if (err) {
2495 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2496 goto out;
2497 }
2498 WARN_ON(hba->clk_gating.state != CLKS_ON);
2499
7a3e97b0
SY		 2500 lrbp = &hba->lrb[tag];
2501
5a0b0cb9 2502 WARN_ON(lrbp->cmd);
7a3e97b0 2503 lrbp->cmd = cmd;
09a5a24f 2504 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2505 lrbp->sense_buffer = cmd->sense_buffer;
2506 lrbp->task_tag = tag;
0ce147d4 2507 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2508 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2509 lrbp->req_abort_skip = false;
7a3e97b0 2510
300bb13f
JP		 2511 ufshcd_comp_scsi_upiu(hba, lrbp);
2512
75b1cc4a 2513 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2514 if (err) {
2515 lrbp->cmd = NULL;
17c7d35f 2516 ufshcd_release(hba);
7a3e97b0 2517 goto out;
5a0b0cb9 2518 }
ad1a1b9c
GB		 2519 /* Make sure descriptors are ready before ringing the doorbell */
2520 wmb();
7a3e97b0
SY		 2521
2522 /* issue command to the controller */
2523 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2524 ufshcd_vops_setup_xfer_req(hba, tag, true);
7a3e97b0 2525 ufshcd_send_command(hba, tag);
3441da7d 2526out_unlock:
7a3e97b0
SY		 2527 spin_unlock_irqrestore(hba->host->host_lock, flags);
2528out:
a3cd5ec5 2529 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2530 return err;
2531}
2532
5a0b0cb9
SRT		 2533static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2534 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2535{
2536 lrbp->cmd = NULL;
2537 lrbp->sense_bufflen = 0;
2538 lrbp->sense_buffer = NULL;
2539 lrbp->task_tag = tag;
2540 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2541 lrbp->intr_cmd = true; /* No interrupt aggregation */
2542 hba->dev_cmd.type = cmd_type;
2543
300bb13f 2544 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2545}
2546
2547static int
2548ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2549{
2550 int err = 0;
2551 unsigned long flags;
2552 u32 mask = 1 << tag;
2553
2554 /* clear outstanding transaction before retry */
2555 spin_lock_irqsave(hba->host->host_lock, flags);
2556 ufshcd_utrl_clear(hba, tag);
2557 spin_unlock_irqrestore(hba->host->host_lock, flags);
2558
2559 /*
2560 * wait for for h/w to clear corresponding bit in door-bell.
2561 * max. wait is 1 sec.
2562 */
2563 err = ufshcd_wait_for_register(hba,
2564 REG_UTP_TRANSFER_REQ_DOOR_BELL,
5cac1095 2565 mask, ~mask, 1000, 1000);
5a0b0cb9
SRT		 2566
2567 return err;
2568}
2569
c6d4a831
DR		 2570static int
2571ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2572{
2573 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2574
2575 /* Get the UPIU response */
2576 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2577 UPIU_RSP_CODE_OFFSET;
2578 return query_res->response;
2579}
2580
5a0b0cb9
SRT		 2581/**
2582 * ufshcd_dev_cmd_completion() - handles device management command responses
2583 * @hba: per adapter instance
2584 * @lrbp: pointer to local reference block
2585 */
2586static int
2587ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2588{
2589 int resp;
2590 int err = 0;
2591
ff8e20c6 2592 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2593 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2594
2595 switch (resp) {
2596 case UPIU_TRANSACTION_NOP_IN:
2597 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2598 err = -EINVAL;
2599 dev_err(hba->dev, "%s: unexpected response %x\n",
2600 __func__, resp);
2601 }
2602 break;
68078d5c 2603 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2604 err = ufshcd_check_query_response(hba, lrbp);
2605 if (!err)
2606 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2607 break;
5a0b0cb9
SRT		 2608 case UPIU_TRANSACTION_REJECT_UPIU:
2609 /* TODO: handle Reject UPIU Response */
2610 err = -EPERM;
2611 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2612 __func__);
2613 break;
2614 default:
2615 err = -EINVAL;
2616 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2617 __func__, resp);
2618 break;
2619 }
2620
2621 return err;
2622}
2623
2624static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2625 struct ufshcd_lrb *lrbp, int max_timeout)
2626{
2627 int err = 0;
2628 unsigned long time_left;
2629 unsigned long flags;
2630
2631 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2632 msecs_to_jiffies(max_timeout));
2633
ad1a1b9c
GB		 2634 /* Make sure descriptors are ready before ringing the doorbell */
2635 wmb();
5a0b0cb9
SRT		 2636 spin_lock_irqsave(hba->host->host_lock, flags);
2637 hba->dev_cmd.complete = NULL;
2638 if (likely(time_left)) {
2639 err = ufshcd_get_tr_ocs(lrbp);
2640 if (!err)
2641 err = ufshcd_dev_cmd_completion(hba, lrbp);
2642 }
2643 spin_unlock_irqrestore(hba->host->host_lock, flags);
2644
2645 if (!time_left) {
2646 err = -ETIMEDOUT;
a48353f6
YG		 2647 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2648 __func__, lrbp->task_tag);
5a0b0cb9 2649 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2650 /* successfully cleared the command, retry if needed */
5a0b0cb9 2651 err = -EAGAIN;
a48353f6
YG		 2652 /*
2653 * in case of an error, after clearing the doorbell,
2654 * we also need to clear the outstanding_request
2655 * field in hba
2656 */
2657 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2658 }
2659
2660 return err;
2661}
2662
5a0b0cb9
SRT		 2663/**
2664 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2665 * @hba: UFS hba
2666 * @cmd_type: specifies the type (NOP, Query...)
2667 * @timeout: time in seconds
5a0b0cb9 2668 *
68078d5c
DR		 2669 * NOTE: Since there is only one available tag for device management commands,
2670 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2671 */
2672static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2673 enum dev_cmd_type cmd_type, int timeout)
2674{
7252a360
BVA		 2675 struct request_queue *q = hba->cmd_queue;
2676 struct request *req;
5a0b0cb9
SRT		 2677 struct ufshcd_lrb *lrbp;
2678 int err;
2679 int tag;
2680 struct completion wait;
2681 unsigned long flags;
2682
a3cd5ec5 2683 down_read(&hba->clk_scaling_lock);
2684
5a0b0cb9
SRT		 2685 /*
2686 * Get free slot, sleep if slots are unavailable.
2687 * Even though we use wait_event() which sleeps indefinitely,
2688 * the maximum wait time is bounded by SCSI request timeout.
2689 */
7252a360 2690 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 2691 if (IS_ERR(req)) {
2692 err = PTR_ERR(req);
2693 goto out_unlock;
2694 }
7252a360
BVA		 2695 tag = req->tag;
2696 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5a0b0cb9
SRT		 2697
2698 init_completion(&wait);
2699 lrbp = &hba->lrb[tag];
2700 WARN_ON(lrbp->cmd);
2701 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2702 if (unlikely(err))
2703 goto out_put_tag;
2704
2705 hba->dev_cmd.complete = &wait;
2706
6667e6d9 2707 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2708 /* Make sure descriptors are ready before ringing the doorbell */
2709 wmb();
5a0b0cb9 2710 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2711 ufshcd_vops_setup_xfer_req(hba, tag, false);
5a0b0cb9
SRT		 2712 ufshcd_send_command(hba, tag);
2713 spin_unlock_irqrestore(hba->host->host_lock, flags);
2714
2715 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2716
6667e6d9
OS		 2717 ufshcd_add_query_upiu_trace(hba, tag,
2718 err ? "query_complete_err" : "query_complete");
2719
5a0b0cb9 2720out_put_tag:
7252a360 2721 blk_put_request(req);
bb14dd15 2722out_unlock:
a3cd5ec5 2723 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2724 return err;
2725}
2726
d44a5f98
DR		 2727/**
2728 * ufshcd_init_query() - init the query response and request parameters
2729 * @hba: per-adapter instance
2730 * @request: address of the request pointer to be initialized
2731 * @response: address of the response pointer to be initialized
2732 * @opcode: operation to perform
2733 * @idn: flag idn to access
2734 * @index: LU number to access
2735 * @selector: query/flag/descriptor further identification
2736 */
2737static inline void ufshcd_init_query(struct ufs_hba *hba,
2738 struct ufs_query_req **request, struct ufs_query_res **response,
2739 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2740{
2741 *request = &hba->dev_cmd.query.request;
2742 *response = &hba->dev_cmd.query.response;
2743 memset(*request, 0, sizeof(struct ufs_query_req));
2744 memset(*response, 0, sizeof(struct ufs_query_res));
2745 (*request)->upiu_req.opcode = opcode;
2746 (*request)->upiu_req.idn = idn;
2747 (*request)->upiu_req.index = index;
2748 (*request)->upiu_req.selector = selector;
2749}
2750
dc3c8d3a 2751static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1f34eedf 2752 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
dc3c8d3a
YG		 2753{
2754 int ret;
2755 int retries;
2756
2757 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1f34eedf 2758 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
dc3c8d3a
YG		 2759 if (ret)
2760 dev_dbg(hba->dev,
2761 "%s: failed with error %d, retries %d\n",
2762 __func__, ret, retries);
2763 else
2764 break;
2765 }
2766
2767 if (ret)
2768 dev_err(hba->dev,
2769 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2770 __func__, opcode, idn, ret, retries);
2771 return ret;
2772}
2773
68078d5c
DR		 2774/**
2775 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2776 * @hba: per-adapter instance
2777 * @opcode: flag query to perform
2778 * @idn: flag idn to access
1f34eedf 2779 * @index: flag index to access
8aa29f19 2780 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2781 *
2782 * Returns 0 for success, non-zero in case of failure
2783 */
dc3c8d3a 2784int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 2785 enum flag_idn idn, u8 index, bool *flag_res)
68078d5c 2786{
d44a5f98
DR		 2787 struct ufs_query_req *request = NULL;
2788 struct ufs_query_res *response = NULL;
1f34eedf 2789 int err, selector = 0;
e5ad406c 2790 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2791
2792 BUG_ON(!hba);
2793
1ab27c9c 2794 ufshcd_hold(hba, false);
68078d5c 2795 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2796 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2797 selector);
68078d5c
DR		 2798
2799 switch (opcode) {
2800 case UPIU_QUERY_OPCODE_SET_FLAG:
2801 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2802 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2803 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2804 break;
2805 case UPIU_QUERY_OPCODE_READ_FLAG:
2806 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2807 if (!flag_res) {
2808 /* No dummy reads */
2809 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2810 __func__);
2811 err = -EINVAL;
2812 goto out_unlock;
2813 }
2814 break;
2815 default:
2816 dev_err(hba->dev,
2817 "%s: Expected query flag opcode but got = %d\n",
2818 __func__, opcode);
2819 err = -EINVAL;
2820 goto out_unlock;
2821 }
68078d5c 2822
e5ad406c 2823 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2824
2825 if (err) {
2826 dev_err(hba->dev,
2827 "%s: Sending flag query for idn %d failed, err = %d\n",
2828 __func__, idn, err);
2829 goto out_unlock;
2830 }
2831
2832 if (flag_res)
e8c8e82a 2833 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2834 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2835
2836out_unlock:
2837 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2838 ufshcd_release(hba);
68078d5c
DR		 2839 return err;
2840}
2841
66ec6d59
SRT		 2842/**
2843 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2844 * @hba: per-adapter instance
2845 * @opcode: attribute opcode
2846 * @idn: attribute idn to access
2847 * @index: index field
2848 * @selector: selector field
2849 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2850 *
2851 * Returns 0 for success, non-zero in case of failure
2852*/
ec92b59c
SN		 2853int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2854 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2855{
d44a5f98
DR		 2856 struct ufs_query_req *request = NULL;
2857 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2858 int err;
2859
2860 BUG_ON(!hba);
2861
1ab27c9c 2862 ufshcd_hold(hba, false);
66ec6d59
SRT		 2863 if (!attr_val) {
2864 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2865 __func__, opcode);
2866 err = -EINVAL;
2867 goto out;
2868 }
2869
2870 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2871 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2872 selector);
66ec6d59
SRT		 2873
2874 switch (opcode) {
2875 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2876 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2877 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2878 break;
2879 case UPIU_QUERY_OPCODE_READ_ATTR:
2880 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2881 break;
2882 default:
2883 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2884 __func__, opcode);
2885 err = -EINVAL;
2886 goto out_unlock;
2887 }
2888
d44a5f98 2889 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2890
2891 if (err) {
4b761b58
YG		 2892 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2893 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2894 goto out_unlock;
2895 }
2896
e8c8e82a 2897 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2898
2899out_unlock:
2900 mutex_unlock(&hba->dev_cmd.lock);
2901out:
1ab27c9c 2902 ufshcd_release(hba);
66ec6d59
SRT		 2903 return err;
2904}
2905
5e86ae44
YG		 2906/**
2907 * ufshcd_query_attr_retry() - API function for sending query
2908 * attribute with retries
2909 * @hba: per-adapter instance
2910 * @opcode: attribute opcode
2911 * @idn: attribute idn to access
2912 * @index: index field
2913 * @selector: selector field
2914 * @attr_val: the attribute value after the query request
2915 * completes
2916 *
2917 * Returns 0 for success, non-zero in case of failure
2918*/
2919static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2920 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2921 u32 *attr_val)
2922{
2923 int ret = 0;
2924 u32 retries;
2925
68c9fcfd 2926 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 2927 ret = ufshcd_query_attr(hba, opcode, idn, index,
2928 selector, attr_val);
2929 if (ret)
2930 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2931 __func__, ret, retries);
2932 else
2933 break;
2934 }
2935
2936 if (ret)
2937 dev_err(hba->dev,
2938 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2939 __func__, idn, ret, QUERY_REQ_RETRIES);
2940 return ret;
2941}
2942
a70e91b8 2943static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2944 enum query_opcode opcode, enum desc_idn idn, u8 index,
2945 u8 selector, u8 *desc_buf, int *buf_len)
2946{
2947 struct ufs_query_req *request = NULL;
2948 struct ufs_query_res *response = NULL;
2949 int err;
2950
2951 BUG_ON(!hba);
2952
1ab27c9c 2953 ufshcd_hold(hba, false);
d44a5f98
DR		 2954 if (!desc_buf) {
2955 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2956 __func__, opcode);
2957 err = -EINVAL;
2958 goto out;
2959 }
2960
a4b0e8a4 2961 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2962 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2963 __func__, *buf_len);
2964 err = -EINVAL;
2965 goto out;
2966 }
2967
2968 mutex_lock(&hba->dev_cmd.lock);
2969 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2970 selector);
2971 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2972 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2973
2974 switch (opcode) {
2975 case UPIU_QUERY_OPCODE_WRITE_DESC:
2976 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2977 break;
2978 case UPIU_QUERY_OPCODE_READ_DESC:
2979 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2980 break;
2981 default:
2982 dev_err(hba->dev,
2983 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2984 __func__, opcode);
2985 err = -EINVAL;
2986 goto out_unlock;
2987 }
2988
2989 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2990
2991 if (err) {
4b761b58
YG		 2992 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2993 __func__, opcode, idn, index, err);
d44a5f98
DR		 2994 goto out_unlock;
2995 }
2996
ea2aab24 2997 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2998
2999out_unlock:
cfcbae38 3000 hba->dev_cmd.query.descriptor = NULL;
d44a5f98
DR		 3001 mutex_unlock(&hba->dev_cmd.lock);
3002out:
1ab27c9c 3003 ufshcd_release(hba);
d44a5f98
DR		 3004 return err;
3005}
3006
a70e91b8 3007/**
8aa29f19
BVA		 3008 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3009 * @hba: per-adapter instance
3010 * @opcode: attribute opcode
3011 * @idn: attribute idn to access
3012 * @index: index field
3013 * @selector: selector field
3014 * @desc_buf: the buffer that contains the descriptor
3015 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3016 *
3017 * Returns 0 for success, non-zero in case of failure.
3018 * The buf_len parameter will contain, on return, the length parameter
3019 * received on the response.
3020 */
2238d31c
SN		 3021int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3022 enum query_opcode opcode,
3023 enum desc_idn idn, u8 index,
3024 u8 selector,
3025 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3026{
3027 int err;
3028 int retries;
3029
3030 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3031 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3032 selector, desc_buf, buf_len);
3033 if (!err || err == -EINVAL)
3034 break;
3035 }
3036
3037 return err;
3038}
a70e91b8 3039
a4b0e8a4
PM		 3040/**
3041 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3042 * @hba: Pointer to adapter instance
3043 * @desc_id: descriptor idn value
3044 * @desc_len: mapped desc length (out)
a4b0e8a4 3045 */
7a0bf85b
BH		 3046void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3047 int *desc_len)
a4b0e8a4 3048{
7a0bf85b
BH		 3049 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3050 desc_id == QUERY_DESC_IDN_RFU_1)
a4b0e8a4 3051 *desc_len = 0;
7a0bf85b
BH		 3052 else
3053 *desc_len = hba->desc_size[desc_id];
a4b0e8a4
PM		 3054}
3055EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3056
7a0bf85b 3057static void ufshcd_update_desc_length(struct ufs_hba *hba,
72fb690e 3058 enum desc_idn desc_id, int desc_index,
7a0bf85b
BH		 3059 unsigned char desc_len)
3060{
3061 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
72fb690e
BH		 3062 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3063 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3064 * than the RPMB unit, however, both descriptors share the same
3065 * desc_idn, to cover both unit descriptors with one length, we
3066 * choose the normal unit descriptor length by desc_index.
3067 */
7a0bf85b
BH		 3068 hba->desc_size[desc_id] = desc_len;
3069}
3070
da461cec
SJ		 3071/**
3072 * ufshcd_read_desc_param - read the specified descriptor parameter
3073 * @hba: Pointer to adapter instance
3074 * @desc_id: descriptor idn value
3075 * @desc_index: descriptor index
3076 * @param_offset: offset of the parameter to read
3077 * @param_read_buf: pointer to buffer where parameter would be read
3078 * @param_size: sizeof(param_read_buf)
3079 *
3080 * Return 0 in case of success, non-zero otherwise
3081 */
45bced87
SN		 3082int ufshcd_read_desc_param(struct ufs_hba *hba,
3083 enum desc_idn desc_id,
3084 int desc_index,
3085 u8 param_offset,
3086 u8 *param_read_buf,
3087 u8 param_size)
da461cec
SJ		 3088{
3089 int ret;
3090 u8 *desc_buf;
a4b0e8a4 3091 int buff_len;
da461cec
SJ		 3092 bool is_kmalloc = true;
3093
a4b0e8a4
PM		 3094 /* Safety check */
3095 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3096 return -EINVAL;
3097
7a0bf85b
BH		 3098 /* Get the length of descriptor */
3099 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3100 if (!buff_len) {
3101 dev_err(hba->dev, "%s: Failed to get desc length", __func__);
3102 return -EINVAL;
a4b0e8a4
PM		 3103 }
3104
3105 /* Check whether we need temp memory */
3106 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3107 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3108 if (!desc_buf)
3109 return -ENOMEM;
a4b0e8a4
PM		 3110 } else {
3111 desc_buf = param_read_buf;
3112 is_kmalloc = false;
da461cec
SJ		 3113 }
3114
a4b0e8a4 3115 /* Request for full descriptor */
a70e91b8 3116 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3117 desc_id, desc_index, 0,
3118 desc_buf, &buff_len);
da461cec 3119
bde44bb6 3120 if (ret) {
3121 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3122 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3123 goto out;
3124 }
3125
bde44bb6 3126 /* Sanity check */
3127 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3128 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3129 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3130 ret = -EINVAL;
3131 goto out;
3132 }
3133
7a0bf85b
BH		 3134 /* Update descriptor length */
3135 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
72fb690e 3136 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
7a0bf85b 3137
a4b0e8a4 3138 /* Check wherher we will not copy more data, than available */
cbe193f6
BH		 3139 if (is_kmalloc && (param_offset + param_size) > buff_len)
3140 param_size = buff_len - param_offset;
bde44bb6 3141
da461cec
SJ		 3142 if (is_kmalloc)
3143 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3144out:
3145 if (is_kmalloc)
3146 kfree(desc_buf);
3147 return ret;
3148}
3149
4b828fe1
TW		 3150/**
3151 * struct uc_string_id - unicode string
3152 *
3153 * @len: size of this descriptor inclusive
3154 * @type: descriptor type
3155 * @uc: unicode string character
3156 */
3157struct uc_string_id {
3158 u8 len;
3159 u8 type;
ec38c0ad 3160 wchar_t uc[];
4b828fe1
TW		 3161} __packed;
3162
3163/* replace non-printable or non-ASCII characters with spaces */
3164static inline char ufshcd_remove_non_printable(u8 ch)
3165{
3166 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3167}
3168
b573d484
YG		 3169/**
3170 * ufshcd_read_string_desc - read string descriptor
3171 * @hba: pointer to adapter instance
3172 * @desc_index: descriptor index
4b828fe1
TW		 3173 * @buf: pointer to buffer where descriptor would be read,
3174 * the caller should free the memory.
b573d484 3175 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3176 * null terminated string.
b573d484 3177 *
4b828fe1
TW		 3178 * Return:
3179 * * string size on success.
3180 * * -ENOMEM: on allocation failure
3181 * * -EINVAL: on a wrong parameter
b573d484 3182 */
4b828fe1
TW		 3183int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3184 u8 **buf, bool ascii)
b573d484 3185{
4b828fe1
TW		 3186 struct uc_string_id *uc_str;
3187 u8 *str;
3188 int ret;
b573d484 3189
4b828fe1
TW		 3190 if (!buf)
3191 return -EINVAL;
b573d484 3192
4b828fe1
TW		 3193 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3194 if (!uc_str)
3195 return -ENOMEM;
b573d484 3196
c4607a09
BH		 3197 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3198 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
4b828fe1
TW		 3199 if (ret < 0) {
3200 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3201 QUERY_REQ_RETRIES, ret);
3202 str = NULL;
3203 goto out;
3204 }
3205
3206 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3207 dev_dbg(hba->dev, "String Desc is of zero length\n");
3208 str = NULL;
3209 ret = 0;
b573d484
YG		 3210 goto out;
3211 }
3212
3213 if (ascii) {
4b828fe1 3214 ssize_t ascii_len;
b573d484 3215 int i;
b573d484 3216 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3217 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3218 str = kzalloc(ascii_len, GFP_KERNEL);
3219 if (!str) {
3220 ret = -ENOMEM;
fcbefc3b 3221 goto out;
b573d484
YG		 3222 }
3223
3224 /*
3225 * the descriptor contains string in UTF16 format
3226 * we need to convert to utf-8 so it can be displayed
3227 */
4b828fe1
TW		 3228 ret = utf16s_to_utf8s(uc_str->uc,
3229 uc_str->len - QUERY_DESC_HDR_SIZE,
3230 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3231
3232 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3233 for (i = 0; i < ret; i++)
3234 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3235
4b828fe1
TW		 3236 str[ret++] = '\0';
3237
3238 } else {
5f57704d 3239 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3240 if (!str) {
3241 ret = -ENOMEM;
3242 goto out;
3243 }
4b828fe1 3244 ret = uc_str->len;
b573d484
YG		 3245 }
3246out:
4b828fe1
TW		 3247 *buf = str;
3248 kfree(uc_str);
3249 return ret;
b573d484 3250}
b573d484 3251
da461cec
SJ		 3252/**
3253 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3254 * @hba: Pointer to adapter instance
3255 * @lun: lun id
3256 * @param_offset: offset of the parameter to read
3257 * @param_read_buf: pointer to buffer where parameter would be read
3258 * @param_size: sizeof(param_read_buf)
3259 *
3260 * Return 0 in case of success, non-zero otherwise
3261 */
3262static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3263 int lun,
3264 enum unit_desc_param param_offset,
3265 u8 *param_read_buf,
3266 u32 param_size)
3267{
3268 /*
3269 * Unit descriptors are only available for general purpose LUs (LUN id
3270 * from 0 to 7) and RPMB Well known LU.
3271 */
1baa8011 3272 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
da461cec
SJ		 3273 return -EOPNOTSUPP;
3274
3275 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3276 param_offset, param_read_buf, param_size);
3277}
3278
09f17791
CG		 3279static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3280{
3281 int err = 0;
3282 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3283
3284 if (hba->dev_info.wspecversion >= 0x300) {
3285 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3286 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3287 &gating_wait);
3288 if (err)
3289 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3290 err, gating_wait);
3291
3292 if (gating_wait == 0) {
3293 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3294 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3295 gating_wait);
3296 }
3297
3298 hba->dev_info.clk_gating_wait_us = gating_wait;
3299 }
3300
3301 return err;
3302}
3303
7a3e97b0
SY		 3304/**
3305 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3306 * @hba: per adapter instance
3307 *
3308 * 1. Allocate DMA memory for Command Descriptor array
3309 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3310 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3311 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3312 * (UTMRDL)
3313 * 4. Allocate memory for local reference block(lrb).
3314 *
3315 * Returns 0 for success, non-zero in case of failure
3316 */
3317static int ufshcd_memory_alloc(struct ufs_hba *hba)
3318{
3319 size_t utmrdl_size, utrdl_size, ucdl_size;
3320
3321 /* Allocate memory for UTP command descriptors */
3322 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3323 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3324 ucdl_size,
3325 &hba->ucdl_dma_addr,
3326 GFP_KERNEL);
7a3e97b0
SY		 3327
3328 /*
3329 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3330 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3331 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3332 * be aligned to 128 bytes as well
3333 */
3334 if (!hba->ucdl_base_addr ||
3335 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3336 dev_err(hba->dev,
7a3e97b0
SY		 3337 "Command Descriptor Memory allocation failed\n");
3338 goto out;
3339 }
3340
3341 /*
3342 * Allocate memory for UTP Transfer descriptors
3343 * UFSHCI requires 1024 byte alignment of UTRD
3344 */
3345 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3346 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3347 utrdl_size,
3348 &hba->utrdl_dma_addr,
3349 GFP_KERNEL);
7a3e97b0
SY		 3350 if (!hba->utrdl_base_addr ||
3351 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3352 dev_err(hba->dev,
7a3e97b0
SY		 3353 "Transfer Descriptor Memory allocation failed\n");
3354 goto out;
3355 }
3356
3357 /*
3358 * Allocate memory for UTP Task Management descriptors
3359 * UFSHCI requires 1024 byte alignment of UTMRD
3360 */
3361 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3362 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3363 utmrdl_size,
3364 &hba->utmrdl_dma_addr,
3365 GFP_KERNEL);
7a3e97b0
SY		 3366 if (!hba->utmrdl_base_addr ||
3367 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3368 dev_err(hba->dev,
7a3e97b0
SY		 3369 "Task Management Descriptor Memory allocation failed\n");
3370 goto out;
3371 }
3372
3373 /* Allocate memory for local reference block */
a86854d0
KC		 3374 hba->lrb = devm_kcalloc(hba->dev,
3375 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3376 GFP_KERNEL);
7a3e97b0 3377 if (!hba->lrb) {
3b1d0580 3378 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3379 goto out;
3380 }
3381 return 0;
3382out:
7a3e97b0
SY		 3383 return -ENOMEM;
3384}
3385
3386/**
3387 * ufshcd_host_memory_configure - configure local reference block with
3388 * memory offsets
3389 * @hba: per adapter instance
3390 *
3391 * Configure Host memory space
3392 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3393 * address.
3394 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3395 * and PRDT offset.
3396 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3397 * into local reference block.
3398 */
3399static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3400{
7a3e97b0
SY		 3401 struct utp_transfer_req_desc *utrdlp;
3402 dma_addr_t cmd_desc_dma_addr;
3403 dma_addr_t cmd_desc_element_addr;
3404 u16 response_offset;
3405 u16 prdt_offset;
3406 int cmd_desc_size;
3407 int i;
3408
3409 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3410
3411 response_offset =
3412 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3413 prdt_offset =
3414 offsetof(struct utp_transfer_cmd_desc, prd_table);
3415
3416 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3417 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3418
3419 for (i = 0; i < hba->nutrs; i++) {
3420 /* Configure UTRD with command descriptor base address */
3421 cmd_desc_element_addr =
3422 (cmd_desc_dma_addr + (cmd_desc_size * i));
3423 utrdlp[i].command_desc_base_addr_lo =
3424 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3425 utrdlp[i].command_desc_base_addr_hi =
3426 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3427
3428 /* Response upiu and prdt offset should be in double words */
26f968d7
AA		 3429 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3430 utrdlp[i].response_upiu_offset =
3431 cpu_to_le16(response_offset);
3432 utrdlp[i].prd_table_offset =
3433 cpu_to_le16(prdt_offset);
3434 utrdlp[i].response_upiu_length =
3435 cpu_to_le16(ALIGNED_UPIU_SIZE);
3436 } else {
3437 utrdlp[i].response_upiu_offset =
3438 cpu_to_le16(response_offset >> 2);
3439 utrdlp[i].prd_table_offset =
3440 cpu_to_le16(prdt_offset >> 2);
3441 utrdlp[i].response_upiu_length =
3442 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3443 }
7a3e97b0 3444
4d2b8d40 3445 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3446 }
3447}
3448
3449/**
3450 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3451 * @hba: per adapter instance
3452 *
3453 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3454 * in order to initialize the Unipro link startup procedure.
3455 * Once the Unipro links are up, the device connected to the controller
3456 * is detected.
3457 *
3458 * Returns 0 on success, non-zero value on failure
3459 */
3460static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3461{
6ccf44fe
SJ		 3462 struct uic_command uic_cmd = {0};
3463 int ret;
7a3e97b0 3464
6ccf44fe 3465 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3466
6ccf44fe
SJ		 3467 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3468 if (ret)
ff8e20c6 3469 dev_dbg(hba->dev,
6ccf44fe
SJ		 3470 "dme-link-startup: error code %d\n", ret);
3471 return ret;
7a3e97b0 3472}
39bf2d83
AA		 3473/**
3474 * ufshcd_dme_reset - UIC command for DME_RESET
3475 * @hba: per adapter instance
3476 *
3477 * DME_RESET command is issued in order to reset UniPro stack.
3478 * This function now deals with cold reset.
3479 *
3480 * Returns 0 on success, non-zero value on failure
3481 */
3482static int ufshcd_dme_reset(struct ufs_hba *hba)
3483{
3484 struct uic_command uic_cmd = {0};
3485 int ret;
3486
3487 uic_cmd.command = UIC_CMD_DME_RESET;
3488
3489 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3490 if (ret)
3491 dev_err(hba->dev,
3492 "dme-reset: error code %d\n", ret);
3493
3494 return ret;
3495}
3496
3497/**
3498 * ufshcd_dme_enable - UIC command for DME_ENABLE
3499 * @hba: per adapter instance
3500 *
3501 * DME_ENABLE command is issued in order to enable UniPro stack.
3502 *
3503 * Returns 0 on success, non-zero value on failure
3504 */
3505static int ufshcd_dme_enable(struct ufs_hba *hba)
3506{
3507 struct uic_command uic_cmd = {0};
3508 int ret;
3509
3510 uic_cmd.command = UIC_CMD_DME_ENABLE;
3511
3512 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3513 if (ret)
3514 dev_err(hba->dev,
3515 "dme-reset: error code %d\n", ret);
3516
3517 return ret;
3518}
7a3e97b0 3519
cad2e03d
YG		 3520static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3521{
3522 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3523 unsigned long min_sleep_time_us;
3524
3525 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3526 return;
3527
3528 /*
3529 * last_dme_cmd_tstamp will be 0 only for 1st call to
3530 * this function
3531 */
3532 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3533 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3534 } else {
3535 unsigned long delta =
3536 (unsigned long) ktime_to_us(
3537 ktime_sub(ktime_get(),
3538 hba->last_dme_cmd_tstamp));
3539
3540 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3541 min_sleep_time_us =
3542 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3543 else
3544 return; /* no more delay required */
3545 }
3546
3547 /* allow sleep for extra 50us if needed */
3548 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3549}
3550
12b4fdb4
SJ		 3551/**
3552 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3553 * @hba: per adapter instance
3554 * @attr_sel: uic command argument1
3555 * @attr_set: attribute set type as uic command argument2
3556 * @mib_val: setting value as uic command argument3
3557 * @peer: indicate whether peer or local
3558 *
3559 * Returns 0 on success, non-zero value on failure
3560 */
3561int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3562 u8 attr_set, u32 mib_val, u8 peer)
3563{
3564 struct uic_command uic_cmd = {0};
3565 static const char *const action[] = {
3566 "dme-set",
3567 "dme-peer-set"
3568 };
3569 const char *set = action[!!peer];
3570 int ret;
64238fbd 3571 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3572
3573 uic_cmd.command = peer ?
3574 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3575 uic_cmd.argument1 = attr_sel;
3576 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3577 uic_cmd.argument3 = mib_val;
3578
64238fbd
YG		 3579 do {
3580 /* for peer attributes we retry upon failure */
3581 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3582 if (ret)
3583 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3584 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3585 } while (ret && peer && --retries);
3586
f37e9f8c 3587 if (ret)
64238fbd 3588 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3589 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3590 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3591
3592 return ret;
3593}
3594EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3595
3596/**
3597 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3598 * @hba: per adapter instance
3599 * @attr_sel: uic command argument1
3600 * @mib_val: the value of the attribute as returned by the UIC command
3601 * @peer: indicate whether peer or local
3602 *
3603 * Returns 0 on success, non-zero value on failure
3604 */
3605int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3606 u32 *mib_val, u8 peer)
3607{
3608 struct uic_command uic_cmd = {0};
3609 static const char *const action[] = {
3610 "dme-get",
3611 "dme-peer-get"
3612 };
3613 const char *get = action[!!peer];
3614 int ret;
64238fbd 3615 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3616 struct ufs_pa_layer_attr orig_pwr_info;
3617 struct ufs_pa_layer_attr temp_pwr_info;
3618 bool pwr_mode_change = false;
3619
3620 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3621 orig_pwr_info = hba->pwr_info;
3622 temp_pwr_info = orig_pwr_info;
3623
3624 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3625 orig_pwr_info.pwr_rx == FAST_MODE) {
3626 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3627 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3628 pwr_mode_change = true;
3629 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3630 orig_pwr_info.pwr_rx == SLOW_MODE) {
3631 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3632 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3633 pwr_mode_change = true;
3634 }
3635 if (pwr_mode_change) {
3636 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3637 if (ret)
3638 goto out;
3639 }
3640 }
12b4fdb4
SJ		 3641
3642 uic_cmd.command = peer ?
3643 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3644 uic_cmd.argument1 = attr_sel;
3645
64238fbd
YG		 3646 do {
3647 /* for peer attributes we retry upon failure */
3648 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3649 if (ret)
3650 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3651 get, UIC_GET_ATTR_ID(attr_sel), ret);
3652 } while (ret && peer && --retries);
3653
f37e9f8c 3654 if (ret)
64238fbd 3655 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3656 get, UIC_GET_ATTR_ID(attr_sel),
3657 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3658
64238fbd 3659 if (mib_val && !ret)
12b4fdb4 3660 *mib_val = uic_cmd.argument3;
874237f7
YG		 3661
3662 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3663 && pwr_mode_change)
3664 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3665out:
3666 return ret;
3667}
3668EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3669
53b3d9c3 3670/**
57d104c1
SJ		 3671 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3672 * state) and waits for it to take effect.
3673 *
53b3d9c3 3674 * @hba: per adapter instance
57d104c1
SJ		 3675 * @cmd: UIC command to execute
3676 *
3677 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3678 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3679 * and device UniPro link and hence it's final completion would be indicated by
3680 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3681 * addition to normal UIC command completion Status (UCCS). This function only
3682 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3683 *
3684 * Returns 0 on success, non-zero value on failure
3685 */
57d104c1 3686static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3687{
57d104c1 3688 struct completion uic_async_done;
53b3d9c3
SJ		 3689 unsigned long flags;
3690 u8 status;
3691 int ret;
d75f7fe4 3692 bool reenable_intr = false;
53b3d9c3 3693
53b3d9c3 3694 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3695 init_completion(&uic_async_done);
cad2e03d 3696 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3697
3698 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3699 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3700 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3701 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3702 /*
3703 * Make sure UIC command completion interrupt is disabled before
3704 * issuing UIC command.
3705 */
3706 wmb();
3707 reenable_intr = true;
57d104c1 3708 }
d75f7fe4
YG		 3709 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3710 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3711 if (ret) {
3712 dev_err(hba->dev,
3713 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3714 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3715 goto out;
3716 }
3717
57d104c1 3718 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3719 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3720 dev_err(hba->dev,
57d104c1
SJ		 3721 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3722 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3723 ret = -ETIMEDOUT;
3724 goto out;
3725 }
3726
3727 status = ufshcd_get_upmcrs(hba);
3728 if (status != PWR_LOCAL) {
3729 dev_err(hba->dev,
479da360 3730 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3731 cmd->command, status);
53b3d9c3
SJ		 3732 ret = (status != PWR_OK) ? status : -1;
3733 }
3734out:
7942f7b5
VG		 3735 if (ret) {
3736 ufshcd_print_host_state(hba);
3737 ufshcd_print_pwr_info(hba);
3738 ufshcd_print_host_regs(hba);
3739 }
3740
53b3d9c3 3741 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3742 hba->active_uic_cmd = NULL;
57d104c1 3743 hba->uic_async_done = NULL;
d75f7fe4
YG		 3744 if (reenable_intr)
3745 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3746 spin_unlock_irqrestore(hba->host->host_lock, flags);
3747 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3748
53b3d9c3
SJ		 3749 return ret;
3750}
3751
57d104c1
SJ		 3752/**
3753 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3754 * using DME_SET primitives.
3755 * @hba: per adapter instance
3756 * @mode: powr mode value
3757 *
3758 * Returns 0 on success, non-zero value on failure
3759 */
3760static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3761{
3762 struct uic_command uic_cmd = {0};
1ab27c9c 3763 int ret;
57d104c1 3764
c3a2f9ee
YG		 3765 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3766 ret = ufshcd_dme_set(hba,
3767 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3768 if (ret) {
3769 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3770 __func__, ret);
3771 goto out;
3772 }
3773 }
3774
57d104c1
SJ		 3775 uic_cmd.command = UIC_CMD_DME_SET;
3776 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3777 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3778 ufshcd_hold(hba, false);
3779 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3780 ufshcd_release(hba);
57d104c1 3781
c3a2f9ee 3782out:
1ab27c9c 3783 return ret;
57d104c1
SJ		 3784}
3785
087c5efa 3786int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 3787{
3788 int ret;
3789 unsigned long flags;
3790
3791 spin_lock_irqsave(hba->host->host_lock, flags);
3792 hba->ufshcd_state = UFSHCD_STATE_RESET;
3793 ufshcd_set_eh_in_progress(hba);
3794 spin_unlock_irqrestore(hba->host->host_lock, flags);
3795
ebdd1dfd
CG		 3796 /* Reset the attached device */
3797 ufshcd_vops_device_reset(hba);
3798
53c12d0e
YG		 3799 ret = ufshcd_host_reset_and_restore(hba);
3800
3801 spin_lock_irqsave(hba->host->host_lock, flags);
3802 if (ret)
3803 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3804 ufshcd_clear_eh_in_progress(hba);
3805 spin_unlock_irqrestore(hba->host->host_lock, flags);
3806
3807 if (ret)
3808 dev_err(hba->dev, "%s: link recovery failed, err %d",
3809 __func__, ret);
3810
3811 return ret;
3812}
087c5efa 3813EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 3814
87d0b4a6 3815static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3816{
87d0b4a6 3817 int ret;
57d104c1 3818 struct uic_command uic_cmd = {0};
911a0771 3819 ktime_t start = ktime_get();
57d104c1 3820
ee32c909
KK		 3821 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3822
57d104c1 3823 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3824 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3825 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3826 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3827
53c12d0e 3828 if (ret) {
6d303e4b
SJ		 3829 int err;
3830
87d0b4a6
YG		 3831 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3832 __func__, ret);
3833
53c12d0e 3834 /*
6d303e4b
SJ		 3835 * If link recovery fails then return error code returned from
3836 * ufshcd_link_recovery().
3837 * If link recovery succeeds then return -EAGAIN to attempt
3838 * hibern8 enter retry again.
53c12d0e 3839 */
6d303e4b
SJ		 3840 err = ufshcd_link_recovery(hba);
3841 if (err) {
3842 dev_err(hba->dev, "%s: link recovery failed", __func__);
3843 ret = err;
3844 } else {
3845 ret = -EAGAIN;
3846 }
ee32c909
KK		 3847 } else
3848 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3849 POST_CHANGE);
53c12d0e 3850
87d0b4a6
YG		 3851 return ret;
3852}
3853
3854static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3855{
3856 int ret = 0, retries;
57d104c1 3857
87d0b4a6
YG		 3858 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3859 ret = __ufshcd_uic_hibern8_enter(hba);
6d303e4b 3860 if (!ret)
87d0b4a6
YG		 3861 goto out;
3862 }
3863out:
3864 return ret;
57d104c1
SJ		 3865}
3866
9d19bf7a 3867int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 3868{
3869 struct uic_command uic_cmd = {0};
3870 int ret;
911a0771 3871 ktime_t start = ktime_get();
57d104c1 3872
ee32c909
KK		 3873 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3874
57d104c1
SJ		 3875 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3876 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3877 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3878 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3879
57d104c1 3880 if (ret) {
53c12d0e
YG		 3881 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3882 __func__, ret);
3883 ret = ufshcd_link_recovery(hba);
ff8e20c6 3884 } else {
ee32c909
KK		 3885 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3886 POST_CHANGE);
ff8e20c6
DR		 3887 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3888 hba->ufs_stats.hibern8_exit_cnt++;
3889 }
57d104c1
SJ		 3890
3891 return ret;
3892}
9d19bf7a 3893EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 3894
ba7af5ec
SC		 3895void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
3896{
3897 unsigned long flags;
be7594a4 3898 bool update = false;
ba7af5ec 3899
be7594a4 3900 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 3901 return;
3902
3903 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 3904 if (hba->ahit != ahit) {
3905 hba->ahit = ahit;
3906 update = true;
3907 }
ba7af5ec 3908 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4
CG		 3909
3910 if (update && !pm_runtime_suspended(hba->dev)) {
3911 pm_runtime_get_sync(hba->dev);
3912 ufshcd_hold(hba, false);
3913 ufshcd_auto_hibern8_enable(hba);
3914 ufshcd_release(hba);
3915 pm_runtime_put(hba->dev);
3916 }
ba7af5ec
SC		 3917}
3918EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
3919
71d848b8 3920void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 3921{
3922 unsigned long flags;
3923
ee5f1042 3924 if (!ufshcd_is_auto_hibern8_supported(hba) || !hba->ahit)
ad448378
AH		 3925 return;
3926
3927 spin_lock_irqsave(hba->host->host_lock, flags);
3928 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3929 spin_unlock_irqrestore(hba->host->host_lock, flags);
3930}
3931
5064636c
YG		 3932 /**
3933 * ufshcd_init_pwr_info - setting the POR (power on reset)
3934 * values in hba power info
3935 * @hba: per-adapter instance
3936 */
3937static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3938{
3939 hba->pwr_info.gear_rx = UFS_PWM_G1;
3940 hba->pwr_info.gear_tx = UFS_PWM_G1;
3941 hba->pwr_info.lane_rx = 1;
3942 hba->pwr_info.lane_tx = 1;
3943 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3944 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3945 hba->pwr_info.hs_rate = 0;
3946}
3947
d3e89bac 3948/**
7eb584db
DR		 3949 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3950 * @hba: per-adapter instance
d3e89bac 3951 */
7eb584db 3952static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3953{
7eb584db
DR		 3954 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3955
3956 if (hba->max_pwr_info.is_valid)
3957 return 0;
3958
2349b533 3959 pwr_info->pwr_tx = FAST_MODE;
3960 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3961 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3962
3963 /* Get the connected lane count */
7eb584db
DR		 3964 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3965 &pwr_info->lane_rx);
3966 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3967 &pwr_info->lane_tx);
3968
3969 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3970 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3971 __func__,
3972 pwr_info->lane_rx,
3973 pwr_info->lane_tx);
3974 return -EINVAL;
3975 }
d3e89bac
SJ		 3976
3977 /*
3978 * First, get the maximum gears of HS speed.
3979 * If a zero value, it means there is no HSGEAR capability.
3980 * Then, get the maximum gears of PWM speed.
3981 */
7eb584db
DR		 3982 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3983 if (!pwr_info->gear_rx) {
3984 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3985 &pwr_info->gear_rx);
3986 if (!pwr_info->gear_rx) {
3987 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3988 __func__, pwr_info->gear_rx);
3989 return -EINVAL;
3990 }
2349b533 3991 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3992 }
3993
7eb584db
DR		 3994 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3995 &pwr_info->gear_tx);
3996 if (!pwr_info->gear_tx) {
d3e89bac 3997 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3998 &pwr_info->gear_tx);
3999 if (!pwr_info->gear_tx) {
4000 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4001 __func__, pwr_info->gear_tx);
4002 return -EINVAL;
4003 }
2349b533 4004 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4005 }
4006
4007 hba->max_pwr_info.is_valid = true;
4008 return 0;
4009}
4010
4011static int ufshcd_change_power_mode(struct ufs_hba *hba,
4012 struct ufs_pa_layer_attr *pwr_mode)
4013{
4014 int ret;
4015
4016 /* if already configured to the requested pwr_mode */
4017 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4018 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4019 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4020 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4021 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4022 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4023 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4024 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4025 return 0;
d3e89bac
SJ		 4026 }
4027
4028 /*
4029 * Configure attributes for power mode change with below.
4030 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4031 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4032 * - PA_HSSERIES
4033 */
7eb584db
DR		 4034 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4036 pwr_mode->lane_rx);
4037 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4038 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4039 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4040 else
4041 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4042
7eb584db
DR		 4043 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4044 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4045 pwr_mode->lane_tx);
4046 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4047 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4048 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4049 else
4050 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4051
7eb584db
DR		 4052 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4053 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4054 pwr_mode->pwr_rx == FAST_MODE ||
4055 pwr_mode->pwr_tx == FAST_MODE)
4056 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4057 pwr_mode->hs_rate);
d3e89bac 4058
08342537
CG		 4059 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4060 DL_FC0ProtectionTimeOutVal_Default);
4061 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4062 DL_TC0ReplayTimeOutVal_Default);
4063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4064 DL_AFC0ReqTimeOutVal_Default);
4065 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4066 DL_FC1ProtectionTimeOutVal_Default);
4067 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4068 DL_TC1ReplayTimeOutVal_Default);
4069 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4070 DL_AFC1ReqTimeOutVal_Default);
4071
4072 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4073 DL_FC0ProtectionTimeOutVal_Default);
4074 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4075 DL_TC0ReplayTimeOutVal_Default);
4076 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4077 DL_AFC0ReqTimeOutVal_Default);
4078
7eb584db
DR		 4079 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4080 | pwr_mode->pwr_tx);
4081
4082 if (ret) {
d3e89bac 4083 dev_err(hba->dev,
7eb584db
DR		 4084 "%s: power mode change failed %d\n", __func__, ret);
4085 } else {
0263bcd0
YG		 4086 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4087 pwr_mode);
7eb584db
DR		 4088
4089 memcpy(&hba->pwr_info, pwr_mode,
4090 sizeof(struct ufs_pa_layer_attr));
4091 }
4092
4093 return ret;
4094}
4095
4096/**
4097 * ufshcd_config_pwr_mode - configure a new power mode
4098 * @hba: per-adapter instance
4099 * @desired_pwr_mode: desired power configuration
4100 */
0d846e70 4101int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4102 struct ufs_pa_layer_attr *desired_pwr_mode)
4103{
4104 struct ufs_pa_layer_attr final_params = { 0 };
4105 int ret;
4106
0263bcd0
YG		 4107 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4108 desired_pwr_mode, &final_params);
4109
4110 if (ret)
7eb584db
DR		 4111 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4112
4113 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4114
4115 return ret;
4116}
0d846e70 4117EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4118
68078d5c
DR		 4119/**
4120 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4121 * @hba: per-adapter instance
68078d5c
DR		 4122 *
4123 * Set fDeviceInit flag and poll until device toggles it.
4124 */
4125static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4126{
dc3c8d3a
YG		 4127 int i;
4128 int err;
7dfdcc39 4129 bool flag_res = true;
68078d5c 4130
dc3c8d3a 4131 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4132 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
68078d5c
DR		 4133 if (err) {
4134 dev_err(hba->dev,
4135 "%s setting fDeviceInit flag failed with error %d\n",
4136 __func__, err);
4137 goto out;
4138 }
4139
dc3c8d3a
YG		 4140 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4141 for (i = 0; i < 1000 && !err && flag_res; i++)
4142 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 4143 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
dc3c8d3a 4144
68078d5c
DR		 4145 if (err)
4146 dev_err(hba->dev,
4147 "%s reading fDeviceInit flag failed with error %d\n",
4148 __func__, err);
4149 else if (flag_res)
4150 dev_err(hba->dev,
4151 "%s fDeviceInit was not cleared by the device\n",
4152 __func__);
4153
4154out:
4155 return err;
4156}
4157
7a3e97b0
SY		 4158/**
4159 * ufshcd_make_hba_operational - Make UFS controller operational
4160 * @hba: per adapter instance
4161 *
4162 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4163 * 1. Enable required interrupts
4164 * 2. Configure interrupt aggregation
897efe62 4165 * 3. Program UTRL and UTMRL base address
5c0c28a8 4166 * 4. Configure run-stop-registers
7a3e97b0
SY		 4167 *
4168 * Returns 0 on success, non-zero value on failure
4169 */
9d19bf7a 4170int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4171{
4172 int err = 0;
4173 u32 reg;
4174
6ccf44fe
SJ		 4175 /* Enable required interrupts */
4176 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4177
4178 /* Configure interrupt aggregation */
b852190e
YG		 4179 if (ufshcd_is_intr_aggr_allowed(hba))
4180 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4181 else
4182 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4183
4184 /* Configure UTRL and UTMRL base address registers */
4185 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4186 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4187 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4188 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4189 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4190 REG_UTP_TASK_REQ_LIST_BASE_L);
4191 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4192 REG_UTP_TASK_REQ_LIST_BASE_H);
4193
897efe62
YG		 4194 /*
4195 * Make sure base address and interrupt setup are updated before
4196 * enabling the run/stop registers below.
4197 */
4198 wmb();
4199
7a3e97b0
SY		 4200 /*
4201 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4202 */
5c0c28a8 4203 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4204 if (!(ufshcd_get_lists_status(reg))) {
4205 ufshcd_enable_run_stop_reg(hba);
4206 } else {
3b1d0580 4207 dev_err(hba->dev,
7a3e97b0
SY		 4208 "Host controller not ready to process requests");
4209 err = -EIO;
4210 goto out;
4211 }
4212
7a3e97b0
SY		 4213out:
4214 return err;
4215}
9d19bf7a 4216EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4217
596585a2
YG		 4218/**
4219 * ufshcd_hba_stop - Send controller to reset state
4220 * @hba: per adapter instance
596585a2 4221 */
5cac1095 4222static inline void ufshcd_hba_stop(struct ufs_hba *hba)
596585a2 4223{
5cac1095 4224 unsigned long flags;
596585a2
YG		 4225 int err;
4226
5cac1095
BVA		 4227 /*
4228 * Obtain the host lock to prevent that the controller is disabled
4229 * while the UFS interrupt handler is active on another CPU.
4230 */
4231 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4232 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
5cac1095
BVA		 4233 spin_unlock_irqrestore(hba->host->host_lock, flags);
4234
596585a2
YG		 4235 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4236 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
5cac1095 4237 10, 1);
596585a2
YG		 4238 if (err)
4239 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4240}
4241
7a3e97b0 4242/**
39bf2d83 4243 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4244 * @hba: per adapter instance
4245 *
4246 * The controller resets itself and controller firmware initialization
4247 * sequence kicks off. When controller is ready it will set
4248 * the Host Controller Enable bit to 1.
4249 *
4250 * Returns 0 on success, non-zero value on failure
4251 */
39bf2d83 4252static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0
SY		 4253{
4254 int retry;
4255
596585a2 4256 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4257 /* change controller state to "reset state" */
5cac1095 4258 ufshcd_hba_stop(hba);
7a3e97b0 4259
57d104c1
SJ		 4260 /* UniPro link is disabled at this point */
4261 ufshcd_set_link_off(hba);
4262
0263bcd0 4263 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4264
7a3e97b0
SY		 4265 /* start controller initialization sequence */
4266 ufshcd_hba_start(hba);
4267
4268 /*
4269 * To initialize a UFS host controller HCE bit must be set to 1.
4270 * During initialization the HCE bit value changes from 1->0->1.
4271 * When the host controller completes initialization sequence
4272 * it sets the value of HCE bit to 1. The same HCE bit is read back
4273 * to check if the controller has completed initialization sequence.
4274 * So without this delay the value HCE = 1, set in the previous
4275 * instruction might be read back.
4276 * This delay can be changed based on the controller.
4277 */
90b8491c 4278 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
7a3e97b0
SY		 4279
4280 /* wait for the host controller to complete initialization */
9fc305ef 4281 retry = 50;
7a3e97b0
SY		 4282 while (ufshcd_is_hba_active(hba)) {
4283 if (retry) {
4284 retry--;
4285 } else {
3b1d0580 4286 dev_err(hba->dev,
7a3e97b0
SY		 4287 "Controller enable failed\n");
4288 return -EIO;
4289 }
9fc305ef 4290 usleep_range(1000, 1100);
7a3e97b0 4291 }
5c0c28a8 4292
1d337ec2 4293 /* enable UIC related interrupts */
57d104c1 4294 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4295
0263bcd0 4296 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4297
7a3e97b0
SY		 4298 return 0;
4299}
39bf2d83
AA		 4300
4301int ufshcd_hba_enable(struct ufs_hba *hba)
4302{
4303 int ret;
4304
4305 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4306 ufshcd_set_link_off(hba);
4307 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4308
4309 /* enable UIC related interrupts */
4310 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4311 ret = ufshcd_dme_reset(hba);
4312 if (!ret) {
4313 ret = ufshcd_dme_enable(hba);
4314 if (!ret)
4315 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4316 if (ret)
4317 dev_err(hba->dev,
4318 "Host controller enable failed with non-hce\n");
4319 }
4320 } else {
4321 ret = ufshcd_hba_execute_hce(hba);
4322 }
4323
4324 return ret;
4325}
9d19bf7a
SC		 4326EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4327
7ca38cf3
YG		 4328static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4329{
ba0320fb 4330 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4331
4332 if (!peer)
4333 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4334 &tx_lanes);
4335 else
4336 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4337 &tx_lanes);
4338 for (i = 0; i < tx_lanes; i++) {
4339 if (!peer)
4340 err = ufshcd_dme_set(hba,
4341 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4342 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4343 0);
4344 else
4345 err = ufshcd_dme_peer_set(hba,
4346 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4347 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4348 0);
4349 if (err) {
4350 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4351 __func__, peer, i, err);
4352 break;
4353 }
4354 }
4355
4356 return err;
4357}
4358
4359static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4360{
4361 return ufshcd_disable_tx_lcc(hba, true);
4362}
4363
a5fe372d
SC		 4364void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4365 u32 reg)
8808b4e9
SC		 4366{
4367 reg_hist->reg[reg_hist->pos] = reg;
4368 reg_hist->tstamp[reg_hist->pos] = ktime_get();
4369 reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4370}
a5fe372d 4371EXPORT_SYMBOL_GPL(ufshcd_update_reg_hist);
8808b4e9 4372
7a3e97b0 4373/**
6ccf44fe 4374 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4375 * @hba: per adapter instance
4376 *
6ccf44fe 4377 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4378 */
6ccf44fe 4379static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4380{
6ccf44fe 4381 int ret;
1d337ec2 4382 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4383 bool link_startup_again = false;
7a3e97b0 4384
7caf489b 4385 /*
4386 * If UFS device isn't active then we will have to issue link startup
4387 * 2 times to make sure the device state move to active.
4388 */
4389 if (!ufshcd_is_ufs_dev_active(hba))
4390 link_startup_again = true;
7a3e97b0 4391
7caf489b 4392link_startup:
1d337ec2 4393 do {
0263bcd0 4394 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4395
1d337ec2 4396 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4397
1d337ec2
SRT		 4398 /* check if device is detected by inter-connect layer */
4399 if (!ret && !ufshcd_is_device_present(hba)) {
8808b4e9
SC		 4400 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4401 0);
1d337ec2
SRT		 4402 dev_err(hba->dev, "%s: Device not present\n", __func__);
4403 ret = -ENXIO;
4404 goto out;
4405 }
6ccf44fe 4406
1d337ec2
SRT		 4407 /*
4408 * DME link lost indication is only received when link is up,
4409 * but we can't be sure if the link is up until link startup
4410 * succeeds. So reset the local Uni-Pro and try again.
4411 */
8808b4e9
SC		 4412 if (ret && ufshcd_hba_enable(hba)) {
4413 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4414 (u32)ret);
1d337ec2 4415 goto out;
8808b4e9 4416 }
1d337ec2
SRT		 4417 } while (ret && retries--);
4418
8808b4e9 4419 if (ret) {
1d337ec2 4420 /* failed to get the link up... retire */
8808b4e9
SC		 4421 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4422 (u32)ret);
5c0c28a8 4423 goto out;
8808b4e9 4424 }
5c0c28a8 4425
7caf489b 4426 if (link_startup_again) {
4427 link_startup_again = false;
4428 retries = DME_LINKSTARTUP_RETRIES;
4429 goto link_startup;
4430 }
4431
d2aebb9b 4432 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4433 ufshcd_init_pwr_info(hba);
4434 ufshcd_print_pwr_info(hba);
4435
7ca38cf3
YG		 4436 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4437 ret = ufshcd_disable_device_tx_lcc(hba);
4438 if (ret)
4439 goto out;
4440 }
4441
5c0c28a8 4442 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4443 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4444 if (ret)
4445 goto out;
7a3e97b0 4446
5c0c28a8 4447 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4448out:
7942f7b5 4449 if (ret) {
6ccf44fe 4450 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4451 ufshcd_print_host_state(hba);
4452 ufshcd_print_pwr_info(hba);
4453 ufshcd_print_host_regs(hba);
4454 }
6ccf44fe 4455 return ret;
7a3e97b0
SY		 4456}
4457
5a0b0cb9
SRT		 4458/**
4459 * ufshcd_verify_dev_init() - Verify device initialization
4460 * @hba: per-adapter instance
4461 *
4462 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4463 * device Transport Protocol (UTP) layer is ready after a reset.
4464 * If the UTP layer at the device side is not initialized, it may
4465 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4466 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4467 */
4468static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4469{
4470 int err = 0;
4471 int retries;
4472
1ab27c9c 4473 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4474 mutex_lock(&hba->dev_cmd.lock);
4475 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4476 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4477 NOP_OUT_TIMEOUT);
4478
4479 if (!err || err == -ETIMEDOUT)
4480 break;
4481
4482 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4483 }
4484 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4485 ufshcd_release(hba);
5a0b0cb9
SRT		 4486
4487 if (err)
4488 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4489 return err;
4490}
4491
0ce147d4
SJ		 4492/**
4493 * ufshcd_set_queue_depth - set lun queue depth
4494 * @sdev: pointer to SCSI device
4495 *
4496 * Read bLUQueueDepth value and activate scsi tagged command
4497 * queueing. For WLUN, queue depth is set to 1. For best-effort
4498 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4499 * value that host can queue.
4500 */
4501static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4502{
4503 int ret = 0;
4504 u8 lun_qdepth;
4505 struct ufs_hba *hba;
4506
4507 hba = shost_priv(sdev->host);
4508
4509 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4510 ret = ufshcd_read_unit_desc_param(hba,
4511 ufshcd_scsi_to_upiu_lun(sdev->lun),
4512 UNIT_DESC_PARAM_LU_Q_DEPTH,
4513 &lun_qdepth,
4514 sizeof(lun_qdepth));
0ce147d4
SJ		 4515
4516 /* Some WLUN doesn't support unit descriptor */
4517 if (ret == -EOPNOTSUPP)
4518 lun_qdepth = 1;
4519 else if (!lun_qdepth)
4520 /* eventually, we can figure out the real queue depth */
4521 lun_qdepth = hba->nutrs;
4522 else
4523 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4524
4525 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4526 __func__, lun_qdepth);
db5ed4df 4527 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4528}
4529
57d104c1
SJ		 4530/*
4531 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4532 * @hba: per-adapter instance
4533 * @lun: UFS device lun id
4534 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4535 *
4536 * Returns 0 in case of success and b_lu_write_protect status would be returned
4537 * @b_lu_write_protect parameter.
4538 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4539 * Returns -EINVAL in case of invalid parameters passed to this function.
4540 */
4541static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4542 u8 lun,
4543 u8 *b_lu_write_protect)
4544{
4545 int ret;
4546
4547 if (!b_lu_write_protect)
4548 ret = -EINVAL;
4549 /*
4550 * According to UFS device spec, RPMB LU can't be write
4551 * protected so skip reading bLUWriteProtect parameter for
4552 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4553 */
1baa8011 4554 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4555 ret = -ENOTSUPP;
4556 else
4557 ret = ufshcd_read_unit_desc_param(hba,
4558 lun,
4559 UNIT_DESC_PARAM_LU_WR_PROTECT,
4560 b_lu_write_protect,
4561 sizeof(*b_lu_write_protect));
4562 return ret;
4563}
4564
4565/**
4566 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4567 * status
4568 * @hba: per-adapter instance
4569 * @sdev: pointer to SCSI device
4570 *
4571 */
4572static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4573 struct scsi_device *sdev)
4574{
4575 if (hba->dev_info.f_power_on_wp_en &&
4576 !hba->dev_info.is_lu_power_on_wp) {
4577 u8 b_lu_write_protect;
4578
4579 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4580 &b_lu_write_protect) &&
4581 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4582 hba->dev_info.is_lu_power_on_wp = true;
4583 }
4584}
4585
7a3e97b0
SY		 4586/**
4587 * ufshcd_slave_alloc - handle initial SCSI device configurations
4588 * @sdev: pointer to SCSI device
4589 *
4590 * Returns success
4591 */
4592static int ufshcd_slave_alloc(struct scsi_device *sdev)
4593{
4594 struct ufs_hba *hba;
4595
4596 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4597
4598 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4599 sdev->use_10_for_ms = 1;
a3a76391
CG		 4600
4601 /* DBD field should be set to 1 in mode sense(10) */
4602 sdev->set_dbd_for_ms = 1;
7a3e97b0 4603
e8e7f271
SRT		 4604 /* allow SCSI layer to restart the device in case of errors */
4605 sdev->allow_restart = 1;
4264fd61 4606
b2a6c522
SRT		 4607 /* REPORT SUPPORTED OPERATION CODES is not supported */
4608 sdev->no_report_opcodes = 1;
4609
84af7e8b
SRT		 4610 /* WRITE_SAME command is not supported */
4611 sdev->no_write_same = 1;
e8e7f271 4612
0ce147d4 4613 ufshcd_set_queue_depth(sdev);
4264fd61 4614
57d104c1
SJ		 4615 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4616
7a3e97b0
SY		 4617 return 0;
4618}
4619
4264fd61
SRT		 4620/**
4621 * ufshcd_change_queue_depth - change queue depth
4622 * @sdev: pointer to SCSI device
4623 * @depth: required depth to set
4264fd61 4624 *
db5ed4df 4625 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4626 */
db5ed4df 4627static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4628{
4629 struct ufs_hba *hba = shost_priv(sdev->host);
4630
4631 if (depth > hba->nutrs)
4632 depth = hba->nutrs;
db5ed4df 4633 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4634}
4635
eeda4749
AM		 4636/**
4637 * ufshcd_slave_configure - adjust SCSI device configurations
4638 * @sdev: pointer to SCSI device
4639 */
4640static int ufshcd_slave_configure(struct scsi_device *sdev)
4641{
49615ba1 4642 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 4643 struct request_queue *q = sdev->request_queue;
4644
4645 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
49615ba1
SC		 4646
4647 if (ufshcd_is_rpm_autosuspend_allowed(hba))
4648 sdev->rpm_autosuspend = 1;
4649
eeda4749
AM		 4650 return 0;
4651}
4652
7a3e97b0
SY		 4653/**
4654 * ufshcd_slave_destroy - remove SCSI device configurations
4655 * @sdev: pointer to SCSI device
4656 */
4657static void ufshcd_slave_destroy(struct scsi_device *sdev)
4658{
4659 struct ufs_hba *hba;
4660
4661 hba = shost_priv(sdev->host);
0ce147d4 4662 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4663 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4664 unsigned long flags;
4665
4666 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4667 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4668 spin_unlock_irqrestore(hba->host->host_lock, flags);
4669 }
7a3e97b0
SY		 4670}
4671
7a3e97b0
SY		 4672/**
4673 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4674 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4675 * @scsi_status: SCSI command status
4676 *
4677 * Returns value base on SCSI command status
4678 */
4679static inline int
4680ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4681{
4682 int result = 0;
4683
4684 switch (scsi_status) {
7a3e97b0 4685 case SAM_STAT_CHECK_CONDITION:
1c2623c5 4686 ufshcd_copy_sense_data(lrbp);
30eb2e4c 4687 /* fallthrough */
1c2623c5 4688 case SAM_STAT_GOOD:
7a3e97b0
SY		 4689 result |= DID_OK << 16 |
4690 COMMAND_COMPLETE << 8 |
1c2623c5 4691 scsi_status;
7a3e97b0
SY		 4692 break;
4693 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4694 case SAM_STAT_BUSY:
7a3e97b0 4695 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4696 ufshcd_copy_sense_data(lrbp);
4697 result |= scsi_status;
7a3e97b0
SY		 4698 break;
4699 default:
4700 result |= DID_ERROR << 16;
4701 break;
4702 } /* end of switch */
4703
4704 return result;
4705}
4706
4707/**
4708 * ufshcd_transfer_rsp_status - Get overall status of the response
4709 * @hba: per adapter instance
8aa29f19 4710 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4711 *
4712 * Returns result of the command to notify SCSI midlayer
4713 */
4714static inline int
4715ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4716{
4717 int result = 0;
4718 int scsi_status;
4719 int ocs;
4720
4721 /* overall command status of utrd */
4722 ocs = ufshcd_get_tr_ocs(lrbp);
4723
d779a6e9
KK		 4724 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
4725 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
4726 MASK_RSP_UPIU_RESULT)
4727 ocs = OCS_SUCCESS;
4728 }
4729
7a3e97b0
SY		 4730 switch (ocs) {
4731 case OCS_SUCCESS:
5a0b0cb9 4732 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4733 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4734 switch (result) {
4735 case UPIU_TRANSACTION_RESPONSE:
4736 /*
4737 * get the response UPIU result to extract
4738 * the SCSI command status
4739 */
4740 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4741
4742 /*
4743 * get the result based on SCSI status response
4744 * to notify the SCSI midlayer of the command status
4745 */
4746 scsi_status = result & MASK_SCSI_STATUS;
4747 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4748
f05ac2e5
YG		 4749 /*
4750 * Currently we are only supporting BKOPs exception
4751 * events hence we can ignore BKOPs exception event
4752 * during power management callbacks. BKOPs exception
4753 * event is not expected to be raised in runtime suspend
4754 * callback as it allows the urgent bkops.
4755 * During system suspend, we are anyway forcefully
4756 * disabling the bkops and if urgent bkops is needed
4757 * it will be enabled on system resume. Long term
4758 * solution could be to abort the system suspend if
4759 * UFS device needs urgent BKOPs.
4760 */
4761 if (!hba->pm_op_in_progress &&
2824ec9f
SL		 4762 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4763 schedule_work(&hba->eeh_work)) {
4764 /*
4765 * Prevent suspend once eeh_work is scheduled
4766 * to avoid deadlock between ufshcd_suspend
4767 * and exception event handler.
4768 */
4769 pm_runtime_get_noresume(hba->dev);
4770 }
5a0b0cb9
SRT		 4771 break;
4772 case UPIU_TRANSACTION_REJECT_UPIU:
4773 /* TODO: handle Reject UPIU Response */
4774 result = DID_ERROR << 16;
3b1d0580 4775 dev_err(hba->dev,
5a0b0cb9
SRT		 4776 "Reject UPIU not fully implemented\n");
4777 break;
4778 default:
5a0b0cb9
SRT		 4779 dev_err(hba->dev,
4780 "Unexpected request response code = %x\n",
4781 result);
e0347d89 4782 result = DID_ERROR << 16;
7a3e97b0
SY		 4783 break;
4784 }
7a3e97b0
SY		 4785 break;
4786 case OCS_ABORTED:
4787 result |= DID_ABORT << 16;
4788 break;
e8e7f271
SRT		 4789 case OCS_INVALID_COMMAND_STATUS:
4790 result |= DID_REQUEUE << 16;
4791 break;
7a3e97b0
SY		 4792 case OCS_INVALID_CMD_TABLE_ATTR:
4793 case OCS_INVALID_PRDT_ATTR:
4794 case OCS_MISMATCH_DATA_BUF_SIZE:
4795 case OCS_MISMATCH_RESP_UPIU_SIZE:
4796 case OCS_PEER_COMM_FAILURE:
4797 case OCS_FATAL_ERROR:
4798 default:
4799 result |= DID_ERROR << 16;
3b1d0580 4800 dev_err(hba->dev,
ff8e20c6
DR		 4801 "OCS error from controller = %x for tag %d\n",
4802 ocs, lrbp->task_tag);
4803 ufshcd_print_host_regs(hba);
6ba65588 4804 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4805 break;
4806 } /* end of switch */
4807
2df74b69 4808 if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
66cc820f 4809 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4810 return result;
4811}
4812
6ccf44fe
SJ		 4813/**
4814 * ufshcd_uic_cmd_compl - handle completion of uic command
4815 * @hba: per adapter instance
53b3d9c3 4816 * @intr_status: interrupt status generated by the controller
9333d775
VG		 4817 *
4818 * Returns
4819 * IRQ_HANDLED - If interrupt is valid
4820 * IRQ_NONE - If invalid interrupt
6ccf44fe 4821 */
9333d775 4822static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4823{
9333d775
VG		 4824 irqreturn_t retval = IRQ_NONE;
4825
53b3d9c3 4826 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4827 hba->active_uic_cmd->argument2 |=
4828 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4829 hba->active_uic_cmd->argument3 =
4830 ufshcd_get_dme_attr_val(hba);
6ccf44fe 4831 complete(&hba->active_uic_cmd->done);
9333d775 4832 retval = IRQ_HANDLED;
6ccf44fe 4833 }
53b3d9c3 4834
9333d775 4835 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
57d104c1 4836 complete(hba->uic_async_done);
9333d775
VG		 4837 retval = IRQ_HANDLED;
4838 }
4839 return retval;
6ccf44fe
SJ		 4840}
4841
7a3e97b0 4842/**
9a47ec7c 4843 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4844 * @hba: per adapter instance
9a47ec7c 4845 * @completed_reqs: requests to complete
7a3e97b0 4846 */
9a47ec7c
YG		 4847static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4848 unsigned long completed_reqs)
7a3e97b0 4849{
5a0b0cb9
SRT		 4850 struct ufshcd_lrb *lrbp;
4851 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4852 int result;
4853 int index;
e9d501b1 4854
e9d501b1
DR		 4855 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4856 lrbp = &hba->lrb[index];
4857 cmd = lrbp->cmd;
4858 if (cmd) {
1a07f2d9 4859 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4860 result = ufshcd_transfer_rsp_status(hba, lrbp);
4861 scsi_dma_unmap(cmd);
4862 cmd->result = result;
4863 /* Mark completed command as NULL in LRB */
4864 lrbp->cmd = NULL;
74a527a2 4865 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 4866 /* Do not touch lrbp after scsi done */
4867 cmd->scsi_done(cmd);
1ab27c9c 4868 __ufshcd_release(hba);
300bb13f
JP		 4869 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4870 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
74a527a2 4871 lrbp->compl_time_stamp = ktime_get();
1a07f2d9
LS		 4872 if (hba->dev_cmd.complete) {
4873 ufshcd_add_command_trace(hba, index,
4874 "dev_complete");
e9d501b1 4875 complete(hba->dev_cmd.complete);
1a07f2d9 4876 }
e9d501b1 4877 }
401f1e44 4878 if (ufshcd_is_clkscaling_supported(hba))
4879 hba->clk_scaling.active_reqs--;
e9d501b1 4880 }
7a3e97b0
SY		 4881
4882 /* clear corresponding bits of completed commands */
4883 hba->outstanding_reqs ^= completed_reqs;
4884
856b3483 4885 ufshcd_clk_scaling_update_busy(hba);
7a3e97b0
SY		 4886}
4887
9a47ec7c
YG		 4888/**
4889 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4890 * @hba: per adapter instance
9333d775
VG		 4891 *
4892 * Returns
4893 * IRQ_HANDLED - If interrupt is valid
4894 * IRQ_NONE - If invalid interrupt
9a47ec7c 4895 */
9333d775 4896static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c
YG		 4897{
4898 unsigned long completed_reqs;
4899 u32 tr_doorbell;
4900
4901 /* Resetting interrupt aggregation counters first and reading the
4902 * DOOR_BELL afterward allows us to handle all the completed requests.
4903 * In order to prevent other interrupts starvation the DB is read once
4904 * after reset. The down side of this solution is the possibility of
4905 * false interrupt if device completes another request after resetting
4906 * aggregation and before reading the DB.
4907 */
b638b5eb
AA		 4908 if (ufshcd_is_intr_aggr_allowed(hba) &&
4909 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 4910 ufshcd_reset_intr_aggr(hba);
4911
4912 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4913 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4914
9333d775
VG		 4915 if (completed_reqs) {
4916 __ufshcd_transfer_req_compl(hba, completed_reqs);
4917 return IRQ_HANDLED;
4918 } else {
4919 return IRQ_NONE;
4920 }
9a47ec7c
YG		 4921}
4922
66ec6d59
SRT		 4923/**
4924 * ufshcd_disable_ee - disable exception event
4925 * @hba: per-adapter instance
4926 * @mask: exception event to disable
4927 *
4928 * Disables exception event in the device so that the EVENT_ALERT
4929 * bit is not set.
4930 *
4931 * Returns zero on success, non-zero error value on failure.
4932 */
4933static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4934{
4935 int err = 0;
4936 u32 val;
4937
4938 if (!(hba->ee_ctrl_mask & mask))
4939 goto out;
4940
4941 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4942 val &= MASK_EE_STATUS;
5e86ae44 4943 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4944 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4945 if (!err)
4946 hba->ee_ctrl_mask &= ~mask;
4947out:
4948 return err;
4949}
4950
4951/**
4952 * ufshcd_enable_ee - enable exception event
4953 * @hba: per-adapter instance
4954 * @mask: exception event to enable
4955 *
4956 * Enable corresponding exception event in the device to allow
4957 * device to alert host in critical scenarios.
4958 *
4959 * Returns zero on success, non-zero error value on failure.
4960 */
4961static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4962{
4963 int err = 0;
4964 u32 val;
4965
4966 if (hba->ee_ctrl_mask & mask)
4967 goto out;
4968
4969 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4970 val &= MASK_EE_STATUS;
5e86ae44 4971 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4972 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4973 if (!err)
4974 hba->ee_ctrl_mask |= mask;
4975out:
4976 return err;
4977}
4978
4979/**
4980 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4981 * @hba: per-adapter instance
4982 *
4983 * Allow device to manage background operations on its own. Enabling
4984 * this might lead to inconsistent latencies during normal data transfers
4985 * as the device is allowed to manage its own way of handling background
4986 * operations.
4987 *
4988 * Returns zero on success, non-zero on failure.
4989 */
4990static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4991{
4992 int err = 0;
4993
4994 if (hba->auto_bkops_enabled)
4995 goto out;
4996
dc3c8d3a 4997 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4998 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 4999 if (err) {
5000 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5001 __func__, err);
5002 goto out;
5003 }
5004
5005 hba->auto_bkops_enabled = true;
7ff5ab47 5006 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5007
5008 /* No need of URGENT_BKOPS exception from the device */
5009 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5010 if (err)
5011 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5012 __func__, err);
5013out:
5014 return err;
5015}
5016
5017/**
5018 * ufshcd_disable_auto_bkops - block device in doing background operations
5019 * @hba: per-adapter instance
5020 *
5021 * Disabling background operations improves command response latency but
5022 * has drawback of device moving into critical state where the device is
5023 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5024 * host is idle so that BKOPS are managed effectively without any negative
5025 * impacts.
5026 *
5027 * Returns zero on success, non-zero on failure.
5028 */
5029static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5030{
5031 int err = 0;
5032
5033 if (!hba->auto_bkops_enabled)
5034 goto out;
5035
5036 /*
5037 * If host assisted BKOPs is to be enabled, make sure
5038 * urgent bkops exception is allowed.
5039 */
5040 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5041 if (err) {
5042 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5043 __func__, err);
5044 goto out;
5045 }
5046
dc3c8d3a 5047 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
1f34eedf 5048 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5049 if (err) {
5050 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5051 __func__, err);
5052 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5053 goto out;
5054 }
5055
5056 hba->auto_bkops_enabled = false;
7ff5ab47 5057 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5058 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5059out:
5060 return err;
5061}
5062
5063/**
4e768e76 5064 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5065 * @hba: per adapter instance
5066 *
5067 * After a device reset the device may toggle the BKOPS_EN flag
5068 * to default value. The s/w tracking variables should be updated
4e768e76 5069 * as well. This function would change the auto-bkops state based on
5070 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5071 */
4e768e76 5072static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5073{
4e768e76 5074 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5075 hba->auto_bkops_enabled = false;
5076 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5077 ufshcd_enable_auto_bkops(hba);
5078 } else {
5079 hba->auto_bkops_enabled = true;
5080 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5081 ufshcd_disable_auto_bkops(hba);
5082 }
7b6668d8 5083 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
24366c2a 5084 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5085}
5086
5087static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5088{
5e86ae44 5089 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5090 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5091}
5092
5093/**
57d104c1 5094 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5095 * @hba: per-adapter instance
57d104c1 5096 * @status: bkops_status value
66ec6d59 5097 *
57d104c1
SJ		 5098 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5099 * flag in the device to permit background operations if the device
5100 * bkops_status is greater than or equal to "status" argument passed to
5101 * this function, disable otherwise.
5102 *
5103 * Returns 0 for success, non-zero in case of failure.
5104 *
5105 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5106 * to know whether auto bkops is enabled or disabled after this function
5107 * returns control to it.
66ec6d59 5108 */
57d104c1
SJ		 5109static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5110 enum bkops_status status)
66ec6d59
SRT		 5111{
5112 int err;
57d104c1 5113 u32 curr_status = 0;
66ec6d59 5114
57d104c1 5115 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5116 if (err) {
5117 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5118 __func__, err);
5119 goto out;
57d104c1
SJ		 5120 } else if (curr_status > BKOPS_STATUS_MAX) {
5121 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5122 __func__, curr_status);
5123 err = -EINVAL;
5124 goto out;
66ec6d59
SRT		 5125 }
5126
57d104c1 5127 if (curr_status >= status)
66ec6d59 5128 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5129 else
5130 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5131out:
5132 return err;
5133}
5134
57d104c1
SJ		 5135/**
5136 * ufshcd_urgent_bkops - handle urgent bkops exception event
5137 * @hba: per-adapter instance
5138 *
5139 * Enable fBackgroundOpsEn flag in the device to permit background
5140 * operations.
5141 *
5142 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5143 * and negative error value for any other failure.
5144 */
5145static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5146{
afdfff59 5147 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5148}
5149
66ec6d59
SRT		 5150static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5151{
5e86ae44 5152 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5153 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5154}
5155
afdfff59
YG		 5156static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5157{
5158 int err;
5159 u32 curr_status = 0;
5160
5161 if (hba->is_urgent_bkops_lvl_checked)
5162 goto enable_auto_bkops;
5163
5164 err = ufshcd_get_bkops_status(hba, &curr_status);
5165 if (err) {
5166 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5167 __func__, err);
5168 goto out;
5169 }
5170
5171 /*
5172 * We are seeing that some devices are raising the urgent bkops
5173 * exception events even when BKOPS status doesn't indicate performace
5174 * impacted or critical. Handle these device by determining their urgent
5175 * bkops status at runtime.
5176 */
5177 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5178 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5179 __func__, curr_status);
5180 /* update the current status as the urgent bkops level */
5181 hba->urgent_bkops_lvl = curr_status;
5182 hba->is_urgent_bkops_lvl_checked = true;
5183 }
5184
5185enable_auto_bkops:
5186 err = ufshcd_enable_auto_bkops(hba);
5187out:
5188 if (err < 0)
5189 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5190 __func__, err);
5191}
5192
3d17b9b5
AD		 5193static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable)
5194{
5195 int ret;
6f8d5a6a 5196 u8 index;
3d17b9b5
AD		 5197 enum query_opcode opcode;
5198
79e3520f 5199 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5200 return 0;
5201
5202 if (!(enable ^ hba->wb_enabled))
5203 return 0;
5204 if (enable)
5205 opcode = UPIU_QUERY_OPCODE_SET_FLAG;
5206 else
5207 opcode = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5208
e31011ab 5209 index = ufshcd_wb_get_query_index(hba);
3d17b9b5 5210 ret = ufshcd_query_flag_retry(hba, opcode,
6f8d5a6a 5211 QUERY_FLAG_IDN_WB_EN, index, NULL);
3d17b9b5
AD		 5212 if (ret) {
5213 dev_err(hba->dev, "%s write booster %s failed %d\n",
5214 __func__, enable ? "enable" : "disable", ret);
5215 return ret;
5216 }
5217
5218 hba->wb_enabled = enable;
5219 dev_dbg(hba->dev, "%s write booster %s %d\n",
5220 __func__, enable ? "enable" : "disable", ret);
5221
5222 return ret;
5223}
5224
5225static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5226{
5227 int val;
6f8d5a6a 5228 u8 index;
3d17b9b5
AD		 5229
5230 if (set)
5231 val = UPIU_QUERY_OPCODE_SET_FLAG;
5232 else
5233 val = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5234
e31011ab 5235 index = ufshcd_wb_get_query_index(hba);
3d17b9b5 5236 return ufshcd_query_flag_retry(hba, val,
6f8d5a6a
SC		 5237 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8,
5238 index, NULL);
3d17b9b5
AD		 5239}
5240
5241static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5242{
5243 if (enable)
5244 ufshcd_wb_buf_flush_enable(hba);
5245 else
5246 ufshcd_wb_buf_flush_disable(hba);
5247
5248}
5249
5250static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba)
5251{
5252 int ret;
6f8d5a6a 5253 u8 index;
3d17b9b5 5254
79e3520f 5255 if (!ufshcd_is_wb_allowed(hba) || hba->wb_buf_flush_enabled)
3d17b9b5
AD		 5256 return 0;
5257
e31011ab 5258 index = ufshcd_wb_get_query_index(hba);
3d17b9b5 5259 ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 5260 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
6f8d5a6a 5261 index, NULL);
3d17b9b5
AD		 5262 if (ret)
5263 dev_err(hba->dev, "%s WB - buf flush enable failed %d\n",
5264 __func__, ret);
5265 else
5266 hba->wb_buf_flush_enabled = true;
5267
5268 dev_dbg(hba->dev, "WB - Flush enabled: %d\n", ret);
5269 return ret;
5270}
5271
5272static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba)
5273{
5274 int ret;
6f8d5a6a 5275 u8 index;
3d17b9b5 5276
79e3520f 5277 if (!ufshcd_is_wb_allowed(hba) || !hba->wb_buf_flush_enabled)
3d17b9b5
AD		 5278 return 0;
5279
e31011ab 5280 index = ufshcd_wb_get_query_index(hba);
3d17b9b5 5281 ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
6f8d5a6a
SC		 5282 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
5283 index, NULL);
3d17b9b5
AD		 5284 if (ret) {
5285 dev_warn(hba->dev, "%s: WB - buf flush disable failed %d\n",
5286 __func__, ret);
5287 } else {
5288 hba->wb_buf_flush_enabled = false;
5289 dev_dbg(hba->dev, "WB - Flush disabled: %d\n", ret);
5290 }
5291
5292 return ret;
5293}
5294
5295static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5296 u32 avail_buf)
5297{
5298 u32 cur_buf;
5299 int ret;
e31011ab 5300 u8 index;
3d17b9b5 5301
e31011ab 5302 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5303 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5304 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
e31011ab 5305 index, 0, &cur_buf);
3d17b9b5
AD		 5306 if (ret) {
5307 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5308 __func__, ret);
5309 return false;
5310 }
5311
5312 if (!cur_buf) {
5313 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5314 cur_buf);
5315 return false;
5316 }
d14734ae
SC		 5317 /* Let it continue to flush when available buffer exceeds threshold */
5318 if (avail_buf < hba->vps->wb_flush_threshold)
3d17b9b5
AD		 5319 return true;
5320
5321 return false;
5322}
5323
51dd905b 5324static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
3d17b9b5
AD		 5325{
5326 int ret;
5327 u32 avail_buf;
e31011ab 5328 u8 index;
3d17b9b5 5329
79e3520f 5330 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5331 return false;
5332 /*
5333 * The ufs device needs the vcc to be ON to flush.
5334 * With user-space reduction enabled, it's enough to enable flush
5335 * by checking only the available buffer. The threshold
5336 * defined here is > 90% full.
5337 * With user-space preserved enabled, the current-buffer
5338 * should be checked too because the wb buffer size can reduce
5339 * when disk tends to be full. This info is provided by current
5340 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5341 * keeping vcc on when current buffer is empty.
5342 */
e31011ab 5343 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5344 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5345 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
e31011ab 5346 index, 0, &avail_buf);
3d17b9b5
AD		 5347 if (ret) {
5348 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5349 __func__, ret);
5350 return false;
5351 }
5352
5353 if (!hba->dev_info.b_presrv_uspc_en) {
d14734ae 5354 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
3d17b9b5
AD		 5355 return true;
5356 return false;
5357 }
5358
5359 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5360}
5361
51dd905b
SC		 5362static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5363{
5364 struct ufs_hba *hba = container_of(to_delayed_work(work),
5365 struct ufs_hba,
5366 rpm_dev_flush_recheck_work);
5367 /*
5368 * To prevent unnecessary VCC power drain after device finishes
5369 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5370 * after a certain delay to recheck the threshold by next runtime
5371 * suspend.
5372 */
5373 pm_runtime_get_sync(hba->dev);
5374 pm_runtime_put_sync(hba->dev);
5375}
5376
66ec6d59
SRT		 5377/**
5378 * ufshcd_exception_event_handler - handle exceptions raised by device
5379 * @work: pointer to work data
5380 *
5381 * Read bExceptionEventStatus attribute from the device and handle the
5382 * exception event accordingly.
5383 */
5384static void ufshcd_exception_event_handler(struct work_struct *work)
5385{
5386 struct ufs_hba *hba;
5387 int err;
5388 u32 status = 0;
5389 hba = container_of(work, struct ufs_hba, eeh_work);
5390
62694735 5391 pm_runtime_get_sync(hba->dev);
03e1d28e 5392 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5393 err = ufshcd_get_ee_status(hba, &status);
5394 if (err) {
5395 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5396 __func__, err);
5397 goto out;
5398 }
5399
5400 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5401
5402 if (status & MASK_EE_URGENT_BKOPS)
5403 ufshcd_bkops_exception_event_handler(hba);
5404
66ec6d59 5405out:
03e1d28e 5406 ufshcd_scsi_unblock_requests(hba);
2824ec9f
SL		 5407 /*
5408 * pm_runtime_get_noresume is called while scheduling
5409 * eeh_work to avoid suspend racing with exception work.
5410 * Hence decrement usage counter using pm_runtime_put_noidle
5411 * to allow suspend on completion of exception event handler.
5412 */
5413 pm_runtime_put_noidle(hba->dev);
5414 pm_runtime_put(hba->dev);
66ec6d59
SRT		 5415 return;
5416}
5417
9a47ec7c
YG		 5418/* Complete requests that have door-bell cleared */
5419static void ufshcd_complete_requests(struct ufs_hba *hba)
5420{
5421 ufshcd_transfer_req_compl(hba);
5422 ufshcd_tmc_handler(hba);
5423}
5424
583fa62d
YG		 5425/**
5426 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5427 * to recover from the DL NAC errors or not.
5428 * @hba: per-adapter instance
5429 *
5430 * Returns true if error handling is required, false otherwise
5431 */
5432static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5433{
5434 unsigned long flags;
5435 bool err_handling = true;
5436
5437 spin_lock_irqsave(hba->host->host_lock, flags);
5438 /*
5439 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5440 * device fatal error and/or DL NAC & REPLAY timeout errors.
5441 */
5442 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5443 goto out;
5444
5445 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5446 ((hba->saved_err & UIC_ERROR) &&
5447 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5448 goto out;
5449
5450 if ((hba->saved_err & UIC_ERROR) &&
5451 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5452 int err;
5453 /*
5454 * wait for 50ms to see if we can get any other errors or not.
5455 */
5456 spin_unlock_irqrestore(hba->host->host_lock, flags);
5457 msleep(50);
5458 spin_lock_irqsave(hba->host->host_lock, flags);
5459
5460 /*
5461 * now check if we have got any other severe errors other than
5462 * DL NAC error?
5463 */
5464 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5465 ((hba->saved_err & UIC_ERROR) &&
5466 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5467 goto out;
5468
5469 /*
5470 * As DL NAC is the only error received so far, send out NOP
5471 * command to confirm if link is still active or not.
5472 * - If we don't get any response then do error recovery.
5473 * - If we get response then clear the DL NAC error bit.
5474 */
5475
5476 spin_unlock_irqrestore(hba->host->host_lock, flags);
5477 err = ufshcd_verify_dev_init(hba);
5478 spin_lock_irqsave(hba->host->host_lock, flags);
5479
5480 if (err)
5481 goto out;
5482
5483 /* Link seems to be alive hence ignore the DL NAC errors */
5484 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5485 hba->saved_err &= ~UIC_ERROR;
5486 /* clear NAC error */
5487 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5488 if (!hba->saved_uic_err) {
5489 err_handling = false;
5490 goto out;
5491 }
5492 }
5493out:
5494 spin_unlock_irqrestore(hba->host->host_lock, flags);
5495 return err_handling;
5496}
5497
7a3e97b0 5498/**
e8e7f271
SRT		 5499 * ufshcd_err_handler - handle UFS errors that require s/w attention
5500 * @work: pointer to work structure
7a3e97b0 5501 */
e8e7f271 5502static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5503{
5504 struct ufs_hba *hba;
e8e7f271
SRT		 5505 unsigned long flags;
5506 u32 err_xfer = 0;
5507 u32 err_tm = 0;
5508 int err = 0;
5509 int tag;
9a47ec7c 5510 bool needs_reset = false;
e8e7f271
SRT		 5511
5512 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5513
62694735 5514 pm_runtime_get_sync(hba->dev);
1ab27c9c 5515 ufshcd_hold(hba, false);
e8e7f271
SRT		 5516
5517 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5518 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5519 goto out;
e8e7f271
SRT		 5520
5521 hba->ufshcd_state = UFSHCD_STATE_RESET;
5522 ufshcd_set_eh_in_progress(hba);
5523
5524 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5525 ufshcd_complete_requests(hba);
583fa62d
YG		 5526
5527 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5528 bool ret;
5529
5530 spin_unlock_irqrestore(hba->host->host_lock, flags);
5531 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5532 ret = ufshcd_quirk_dl_nac_errors(hba);
5533 spin_lock_irqsave(hba->host->host_lock, flags);
5534 if (!ret)
5535 goto skip_err_handling;
5536 }
9a47ec7c 5537 if ((hba->saved_err & INT_FATAL_ERRORS) ||
82174440 5538 (hba->saved_err & UFSHCD_UIC_HIBERN8_MASK) ||
9a47ec7c
YG		 5539 ((hba->saved_err & UIC_ERROR) &&
5540 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5541 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5542 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5543 needs_reset = true;
e8e7f271 5544
9a47ec7c
YG		 5545 /*
5546 * if host reset is required then skip clearing the pending
2df74b69
CG		 5547 * transfers forcefully because they will get cleared during
5548 * host reset and restore
9a47ec7c
YG		 5549 */
5550 if (needs_reset)
5551 goto skip_pending_xfer_clear;
5552
5553 /* release lock as clear command might sleep */
5554 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5555 /* Clear pending transfer requests */
9a47ec7c
YG		 5556 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5557 if (ufshcd_clear_cmd(hba, tag)) {
5558 err_xfer = true;
5559 goto lock_skip_pending_xfer_clear;
5560 }
5561 }
e8e7f271
SRT		 5562
5563 /* Clear pending task management requests */
9a47ec7c
YG		 5564 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5565 if (ufshcd_clear_tm_cmd(hba, tag)) {
5566 err_tm = true;
5567 goto lock_skip_pending_xfer_clear;
5568 }
5569 }
e8e7f271 5570
9a47ec7c 5571lock_skip_pending_xfer_clear:
e8e7f271 5572 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5573
9a47ec7c
YG		 5574 /* Complete the requests that are cleared by s/w */
5575 ufshcd_complete_requests(hba);
5576
5577 if (err_xfer || err_tm)
5578 needs_reset = true;
5579
5580skip_pending_xfer_clear:
e8e7f271 5581 /* Fatal errors need reset */
9a47ec7c
YG		 5582 if (needs_reset) {
5583 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5584
5585 /*
5586 * ufshcd_reset_and_restore() does the link reinitialization
5587 * which will need atleast one empty doorbell slot to send the
5588 * device management commands (NOP and query commands).
5589 * If there is no slot empty at this moment then free up last
5590 * slot forcefully.
5591 */
5592 if (hba->outstanding_reqs == max_doorbells)
5593 __ufshcd_transfer_req_compl(hba,
5594 (1UL << (hba->nutrs - 1)));
5595
5596 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5597 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5598 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5599 if (err) {
5600 dev_err(hba->dev, "%s: reset and restore failed\n",
5601 __func__);
5602 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5603 }
5604 /*
5605 * Inform scsi mid-layer that we did reset and allow to handle
5606 * Unit Attention properly.
5607 */
5608 scsi_report_bus_reset(hba->host, 0);
5609 hba->saved_err = 0;
5610 hba->saved_uic_err = 0;
5611 }
9a47ec7c 5612
583fa62d 5613skip_err_handling:
9a47ec7c
YG		 5614 if (!needs_reset) {
5615 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5616 if (hba->saved_err || hba->saved_uic_err)
5617 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5618 __func__, hba->saved_err, hba->saved_uic_err);
5619 }
5620
e8e7f271
SRT		 5621 ufshcd_clear_eh_in_progress(hba);
5622
5623out:
9a47ec7c 5624 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5625 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5626 ufshcd_release(hba);
62694735 5627 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5628}
5629
5630/**
e8e7f271
SRT		 5631 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5632 * @hba: per-adapter instance
9333d775
VG		 5633 *
5634 * Returns
5635 * IRQ_HANDLED - If interrupt is valid
5636 * IRQ_NONE - If invalid interrupt
7a3e97b0 5637 */
9333d775 5638static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5639{
5640 u32 reg;
9333d775 5641 irqreturn_t retval = IRQ_NONE;
7a3e97b0 5642
fb7b45f0
DR		 5643 /* PHY layer lane error */
5644 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5645 /* Ignore LINERESET indication, as this is not an error */
5646 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
9333d775 5647 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5648 /*
5649 * To know whether this error is fatal or not, DB timeout
5650 * must be checked but this error is handled separately.
5651 */
5652 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
48d5b973 5653 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
9333d775 5654 retval |= IRQ_HANDLED;
ff8e20c6 5655 }
fb7b45f0 5656
e8e7f271
SRT		 5657 /* PA_INIT_ERROR is fatal and needs UIC reset */
5658 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 5659 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
5660 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5661 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
ff8e20c6 5662
9333d775
VG		 5663 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5664 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5665 else if (hba->dev_quirks &
5666 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5667 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5668 hba->uic_error |=
5669 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5670 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5671 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5672 }
5673 retval |= IRQ_HANDLED;
583fa62d 5674 }
e8e7f271
SRT		 5675
5676 /* UIC NL/TL/DME errors needs software retry */
5677 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 5678 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
5679 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5680 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5681 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 5682 retval |= IRQ_HANDLED;
ff8e20c6 5683 }
e8e7f271
SRT		 5684
5685 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 5686 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
5687 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
48d5b973 5688 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5689 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 5690 retval |= IRQ_HANDLED;
ff8e20c6 5691 }
e8e7f271
SRT		 5692
5693 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 5694 if ((reg & UIC_DME_ERROR) &&
5695 (reg & UIC_DME_ERROR_CODE_MASK)) {
48d5b973 5696 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5697 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 5698 retval |= IRQ_HANDLED;
ff8e20c6 5699 }
e8e7f271
SRT		 5700
5701 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5702 __func__, hba->uic_error);
9333d775 5703 return retval;
e8e7f271
SRT		 5704}
5705
82174440
SC		 5706static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5707 u32 intr_mask)
5708{
5a244e0e
SC		 5709 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5710 !ufshcd_is_auto_hibern8_enabled(hba))
82174440
SC		 5711 return false;
5712
5713 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5714 return false;
5715
5716 if (hba->active_uic_cmd &&
5717 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5718 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5719 return false;
5720
5721 return true;
5722}
5723
e8e7f271
SRT		 5724/**
5725 * ufshcd_check_errors - Check for errors that need s/w attention
5726 * @hba: per-adapter instance
9333d775
VG		 5727 *
5728 * Returns
5729 * IRQ_HANDLED - If interrupt is valid
5730 * IRQ_NONE - If invalid interrupt
e8e7f271 5731 */
9333d775 5732static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
e8e7f271
SRT		 5733{
5734 bool queue_eh_work = false;
9333d775 5735 irqreturn_t retval = IRQ_NONE;
e8e7f271 5736
d3c615bf
SC		 5737 if (hba->errors & INT_FATAL_ERRORS) {
5738 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
e8e7f271 5739 queue_eh_work = true;
d3c615bf 5740 }
7a3e97b0
SY		 5741
5742 if (hba->errors & UIC_ERROR) {
e8e7f271 5743 hba->uic_error = 0;
9333d775 5744 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 5745 if (hba->uic_error)
5746 queue_eh_work = true;
7a3e97b0 5747 }
e8e7f271 5748
82174440
SC		 5749 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
5750 dev_err(hba->dev,
5751 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
5752 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
5753 "Enter" : "Exit",
5754 hba->errors, ufshcd_get_upmcrs(hba));
d3c615bf
SC		 5755 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
5756 hba->errors);
82174440
SC		 5757 queue_eh_work = true;
5758 }
5759
e8e7f271 5760 if (queue_eh_work) {
9a47ec7c
YG		 5761 /*
5762 * update the transfer error masks to sticky bits, let's do this
5763 * irrespective of current ufshcd_state.
5764 */
5765 hba->saved_err |= hba->errors;
5766 hba->saved_uic_err |= hba->uic_error;
5767
e8e7f271
SRT		 5768 /* handle fatal errors only when link is functional */
5769 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5770 /* block commands from scsi mid-layer */
38135535 5771 ufshcd_scsi_block_requests(hba);
e8e7f271 5772
141f8165 5773 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5774
5775 /* dump controller state before resetting */
5776 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5777 bool pr_prdt = !!(hba->saved_err &
5778 SYSTEM_BUS_FATAL_ERROR);
5779
5780 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5781 __func__, hba->saved_err,
5782 hba->saved_uic_err);
5783
5784 ufshcd_print_host_regs(hba);
5785 ufshcd_print_pwr_info(hba);
5786 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5787 ufshcd_print_trs(hba, hba->outstanding_reqs,
5788 pr_prdt);
5789 }
e8e7f271
SRT		 5790 schedule_work(&hba->eh_work);
5791 }
9333d775 5792 retval |= IRQ_HANDLED;
3441da7d 5793 }
e8e7f271
SRT		 5794 /*
5795 * if (!queue_eh_work) -
5796 * Other errors are either non-fatal where host recovers
5797 * itself without s/w intervention or errors that will be
5798 * handled by the SCSI core layer.
5799 */
9333d775 5800 return retval;
7a3e97b0
SY		 5801}
5802
69a6c269
BVA		 5803struct ctm_info {
5804 struct ufs_hba *hba;
5805 unsigned long pending;
5806 unsigned int ncpl;
5807};
5808
5809static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
5810{
5811 struct ctm_info *const ci = priv;
5812 struct completion *c;
5813
5814 WARN_ON_ONCE(reserved);
5815 if (test_bit(req->tag, &ci->pending))
5816 return true;
5817 ci->ncpl++;
5818 c = req->end_io_data;
5819 if (c)
5820 complete(c);
5821 return true;
5822}
5823
7a3e97b0
SY		 5824/**
5825 * ufshcd_tmc_handler - handle task management function completion
5826 * @hba: per adapter instance
9333d775
VG		 5827 *
5828 * Returns
5829 * IRQ_HANDLED - If interrupt is valid
5830 * IRQ_NONE - If invalid interrupt
7a3e97b0 5831 */
9333d775 5832static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 5833{
69a6c269
BVA		 5834 struct request_queue *q = hba->tmf_queue;
5835 struct ctm_info ci = {
5836 .hba = hba,
5837 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
5838 };
7a3e97b0 5839
69a6c269
BVA		 5840 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
5841 return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
7a3e97b0
SY		 5842}
5843
5844/**
5845 * ufshcd_sl_intr - Interrupt service routine
5846 * @hba: per adapter instance
5847 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 5848 *
5849 * Returns
5850 * IRQ_HANDLED - If interrupt is valid
5851 * IRQ_NONE - If invalid interrupt
7a3e97b0 5852 */
9333d775 5853static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 5854{
9333d775
VG		 5855 irqreturn_t retval = IRQ_NONE;
5856
7a3e97b0 5857 hba->errors = UFSHCD_ERROR_MASK & intr_status;
82174440
SC		 5858
5859 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5860 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5861
7a3e97b0 5862 if (hba->errors)
9333d775 5863 retval |= ufshcd_check_errors(hba);
7a3e97b0 5864
53b3d9c3 5865 if (intr_status & UFSHCD_UIC_MASK)
9333d775 5866 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5867
5868 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 5869 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 5870
5871 if (intr_status & UTP_TRANSFER_REQ_COMPL)
9333d775
VG		 5872 retval |= ufshcd_transfer_req_compl(hba);
5873
5874 return retval;
7a3e97b0
SY		 5875}
5876
5877/**
5878 * ufshcd_intr - Main interrupt service routine
5879 * @irq: irq number
5880 * @__hba: pointer to adapter instance
5881 *
9333d775
VG		 5882 * Returns
5883 * IRQ_HANDLED - If interrupt is valid
5884 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 5885 */
5886static irqreturn_t ufshcd_intr(int irq, void *__hba)
5887{
d75f7fe4 5888 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5889 irqreturn_t retval = IRQ_NONE;
5890 struct ufs_hba *hba = __hba;
7f6ba4f1 5891 int retries = hba->nutrs;
7a3e97b0
SY		 5892
5893 spin_lock(hba->host->host_lock);
b873a275 5894 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5895
7f6ba4f1
VG		 5896 /*
5897 * There could be max of hba->nutrs reqs in flight and in worst case
5898 * if the reqs get finished 1 by 1 after the interrupt status is
5899 * read, make sure we handle them by checking the interrupt status
5900 * again in a loop until we process all of the reqs before returning.
5901 */
5902 do {
5903 enabled_intr_status =
5904 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5905 if (intr_status)
5906 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 5907 if (enabled_intr_status)
5908 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 5909
5910 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5911 } while (intr_status && --retries);
d75f7fe4 5912
9333d775
VG		 5913 if (retval == IRQ_NONE) {
5914 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
5915 __func__, intr_status);
5916 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
5917 }
5918
7a3e97b0
SY		 5919 spin_unlock(hba->host->host_lock);
5920 return retval;
5921}
5922
e2933132
SRT		 5923static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5924{
5925 int err = 0;
5926 u32 mask = 1 << tag;
5927 unsigned long flags;
5928
5929 if (!test_bit(tag, &hba->outstanding_tasks))
5930 goto out;
5931
5932 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5933 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5934 spin_unlock_irqrestore(hba->host->host_lock, flags);
5935
5936 /* poll for max. 1 sec to clear door bell register by h/w */
5937 err = ufshcd_wait_for_register(hba,
5938 REG_UTP_TASK_REQ_DOOR_BELL,
5cac1095 5939 mask, 0, 1000, 1000);
e2933132
SRT		 5940out:
5941 return err;
5942}
5943
c6049cd9
CH		 5944static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5945 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5946{
69a6c269 5947 struct request_queue *q = hba->tmf_queue;
c6049cd9 5948 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 5949 DECLARE_COMPLETION_ONSTACK(wait);
5950 struct request *req;
7a3e97b0 5951 unsigned long flags;
c6049cd9 5952 int free_slot, task_tag, err;
7a3e97b0 5953
e2933132
SRT		 5954 /*
5955 * Get free slot, sleep if slots are unavailable.
5956 * Even though we use wait_event() which sleeps indefinitely,
5957 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5958 */
69a6c269
BVA		 5959 req = blk_get_request(q, REQ_OP_DRV_OUT, BLK_MQ_REQ_RESERVED);
5960 req->end_io_data = &wait;
5961 free_slot = req->tag;
5962 WARN_ON_ONCE(free_slot < 0 || free_slot >= hba->nutmrs);
1ab27c9c 5963 ufshcd_hold(hba, false);
7a3e97b0 5964
e2933132 5965 spin_lock_irqsave(host->host_lock, flags);
e2933132 5966 task_tag = hba->nutrs + free_slot;
7a3e97b0 5967
c6049cd9
CH		 5968 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5969
5970 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5971 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5972
7a3e97b0
SY		 5973 /* send command to the controller */
5974 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5975
5976 /* Make sure descriptors are ready before ringing the task doorbell */
5977 wmb();
5978
b873a275 5979 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5980 /* Make sure that doorbell is committed immediately */
5981 wmb();
7a3e97b0
SY		 5982
5983 spin_unlock_irqrestore(host->host_lock, flags);
5984
6667e6d9
OS		 5985 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5986
7a3e97b0 5987 /* wait until the task management command is completed */
69a6c269 5988 err = wait_for_completion_io_timeout(&wait,
e2933132 5989 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5990 if (!err) {
69a6c269
BVA		 5991 /*
5992 * Make sure that ufshcd_compl_tm() does not trigger a
5993 * use-after-free.
5994 */
5995 req->end_io_data = NULL;
6667e6d9 5996 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5997 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5998 __func__, tm_function);
5999 if (ufshcd_clear_tm_cmd(hba, free_slot))
6000 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
6001 __func__, free_slot);
6002 err = -ETIMEDOUT;
6003 } else {
c6049cd9
CH		 6004 err = 0;
6005 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
6006
6667e6d9 6007 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
7a3e97b0 6008 }
e2933132 6009
b557217c
SC		 6010 spin_lock_irqsave(hba->host->host_lock, flags);
6011 __clear_bit(free_slot, &hba->outstanding_tasks);
6012 spin_unlock_irqrestore(hba->host->host_lock, flags);
6013
69a6c269 6014 blk_put_request(req);
e2933132 6015
1ab27c9c 6016 ufshcd_release(hba);
7a3e97b0
SY		 6017 return err;
6018}
6019
c6049cd9
CH		 6020/**
6021 * ufshcd_issue_tm_cmd - issues task management commands to controller
6022 * @hba: per adapter instance
6023 * @lun_id: LUN ID to which TM command is sent
6024 * @task_id: task ID to which the TM command is applicable
6025 * @tm_function: task management function opcode
6026 * @tm_response: task management service response return value
6027 *
6028 * Returns non-zero value on error, zero on success.
6029 */
6030static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6031 u8 tm_function, u8 *tm_response)
6032{
6033 struct utp_task_req_desc treq = { { 0 }, };
6034 int ocs_value, err;
6035
6036 /* Configure task request descriptor */
6037 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6038 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6039
6040 /* Configure task request UPIU */
6041 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6042 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6043 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6044
6045 /*
6046 * The host shall provide the same value for LUN field in the basic
6047 * header and for Input Parameter.
6048 */
6049 treq.input_param1 = cpu_to_be32(lun_id);
6050 treq.input_param2 = cpu_to_be32(task_id);
6051
6052 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6053 if (err == -ETIMEDOUT)
6054 return err;
6055
6056 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6057 if (ocs_value != OCS_SUCCESS)
6058 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6059 __func__, ocs_value);
6060 else if (tm_response)
6061 *tm_response = be32_to_cpu(treq.output_param1) &
6062 MASK_TM_SERVICE_RESP;
6063 return err;
6064}
6065
5e0a86ee
AA		 6066/**
6067 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6068 * @hba: per-adapter instance
6069 * @req_upiu: upiu request
6070 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6071 * @desc_buff: pointer to descriptor buffer, NULL if NA
6072 * @buff_len: descriptor size, 0 if NA
d0e9760d 6073 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6074 * @desc_op: descriptor operation
6075 *
6076 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6077 * Therefore, it "rides" the device management infrastructure: uses its tag and
6078 * tasks work queues.
6079 *
6080 * Since there is only one available tag for device management commands,
6081 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6082 */
6083static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6084 struct utp_upiu_req *req_upiu,
6085 struct utp_upiu_req *rsp_upiu,
6086 u8 *desc_buff, int *buff_len,
7f674c38 6087 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6088 enum query_opcode desc_op)
6089{
7252a360
BVA		 6090 struct request_queue *q = hba->cmd_queue;
6091 struct request *req;
5e0a86ee
AA		 6092 struct ufshcd_lrb *lrbp;
6093 int err = 0;
6094 int tag;
6095 struct completion wait;
6096 unsigned long flags;
6097 u32 upiu_flags;
6098
6099 down_read(&hba->clk_scaling_lock);
6100
7252a360 6101 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 6102 if (IS_ERR(req)) {
6103 err = PTR_ERR(req);
6104 goto out_unlock;
6105 }
7252a360
BVA		 6106 tag = req->tag;
6107 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5e0a86ee
AA		 6108
6109 init_completion(&wait);
6110 lrbp = &hba->lrb[tag];
6111 WARN_ON(lrbp->cmd);
6112
6113 lrbp->cmd = NULL;
6114 lrbp->sense_bufflen = 0;
6115 lrbp->sense_buffer = NULL;
6116 lrbp->task_tag = tag;
6117 lrbp->lun = 0;
6118 lrbp->intr_cmd = true;
6119 hba->dev_cmd.type = cmd_type;
6120
6121 switch (hba->ufs_version) {
6122 case UFSHCI_VERSION_10:
6123 case UFSHCI_VERSION_11:
6124 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6125 break;
6126 default:
6127 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6128 break;
6129 }
6130
6131 /* update the task tag in the request upiu */
6132 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6133
6134 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6135
6136 /* just copy the upiu request as it is */
6137 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6138 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6139 /* The Data Segment Area is optional depending upon the query
6140 * function value. for WRITE DESCRIPTOR, the data segment
6141 * follows right after the tsf.
6142 */
6143 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6144 *buff_len = 0;
6145 }
6146
6147 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6148
6149 hba->dev_cmd.complete = &wait;
6150
6151 /* Make sure descriptors are ready before ringing the doorbell */
6152 wmb();
6153 spin_lock_irqsave(hba->host->host_lock, flags);
6154 ufshcd_send_command(hba, tag);
6155 spin_unlock_irqrestore(hba->host->host_lock, flags);
6156
6157 /*
6158 * ignore the returning value here - ufshcd_check_query_response is
6159 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6160 * read the response directly ignoring all errors.
6161 */
6162 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6163
6164 /* just copy the upiu response as it is */
6165 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6166 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6167 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6168 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6169 MASK_QUERY_DATA_SEG_LEN;
6170
6171 if (*buff_len >= resp_len) {
6172 memcpy(desc_buff, descp, resp_len);
6173 *buff_len = resp_len;
6174 } else {
3d4881d1
BH		 6175 dev_warn(hba->dev,
6176 "%s: rsp size %d is bigger than buffer size %d",
6177 __func__, resp_len, *buff_len);
4bbbe242
AA		 6178 *buff_len = 0;
6179 err = -EINVAL;
6180 }
6181 }
5e0a86ee 6182
7252a360 6183 blk_put_request(req);
bb14dd15 6184out_unlock:
5e0a86ee
AA		 6185 up_read(&hba->clk_scaling_lock);
6186 return err;
6187}
6188
6189/**
6190 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6191 * @hba: per-adapter instance
6192 * @req_upiu: upiu request
6193 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6194 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6195 * @desc_buff: pointer to descriptor buffer, NULL if NA
6196 * @buff_len: descriptor size, 0 if NA
6197 * @desc_op: descriptor operation
6198 *
6199 * Supports UTP Transfer requests (nop and query), and UTP Task
6200 * Management requests.
6201 * It is up to the caller to fill the upiu conent properly, as it will
6202 * be copied without any further input validations.
6203 */
6204int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6205 struct utp_upiu_req *req_upiu,
6206 struct utp_upiu_req *rsp_upiu,
6207 int msgcode,
6208 u8 *desc_buff, int *buff_len,
6209 enum query_opcode desc_op)
6210{
6211 int err;
7f674c38 6212 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee
AA		 6213 struct utp_task_req_desc treq = { { 0 }, };
6214 int ocs_value;
6215 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6216
5e0a86ee
AA		 6217 switch (msgcode) {
6218 case UPIU_TRANSACTION_NOP_OUT:
6219 cmd_type = DEV_CMD_TYPE_NOP;
6220 /* fall through */
6221 case UPIU_TRANSACTION_QUERY_REQ:
6222 ufshcd_hold(hba, false);
6223 mutex_lock(&hba->dev_cmd.lock);
6224 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6225 desc_buff, buff_len,
6226 cmd_type, desc_op);
6227 mutex_unlock(&hba->dev_cmd.lock);
6228 ufshcd_release(hba);
6229
6230 break;
6231 case UPIU_TRANSACTION_TASK_REQ:
6232 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6233 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6234
6235 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
6236
6237 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6238 if (err == -ETIMEDOUT)
6239 break;
6240
6241 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6242 if (ocs_value != OCS_SUCCESS) {
6243 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6244 ocs_value);
6245 break;
6246 }
6247
6248 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
6249
6250 break;
6251 default:
6252 err = -EINVAL;
6253
6254 break;
6255 }
6256
5e0a86ee
AA		 6257 return err;
6258}
6259
7a3e97b0 6260/**
3441da7d
SRT		 6261 * ufshcd_eh_device_reset_handler - device reset handler registered to
6262 * scsi layer.
7a3e97b0
SY		 6263 * @cmd: SCSI command pointer
6264 *
6265 * Returns SUCCESS/FAILED
6266 */
3441da7d 6267static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6268{
6269 struct Scsi_Host *host;
6270 struct ufs_hba *hba;
6271 unsigned int tag;
6272 u32 pos;
6273 int err;
e2933132
SRT		 6274 u8 resp = 0xF;
6275 struct ufshcd_lrb *lrbp;
3441da7d 6276 unsigned long flags;
7a3e97b0
SY		 6277
6278 host = cmd->device->host;
6279 hba = shost_priv(host);
6280 tag = cmd->request->tag;
6281
e2933132
SRT		 6282 lrbp = &hba->lrb[tag];
6283 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
6284 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6285 if (!err)
6286 err = resp;
7a3e97b0 6287 goto out;
e2933132 6288 }
7a3e97b0 6289
3441da7d
SRT		 6290 /* clear the commands that were pending for corresponding LUN */
6291 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6292 if (hba->lrb[pos].lun == lrbp->lun) {
6293 err = ufshcd_clear_cmd(hba, pos);
6294 if (err)
6295 break;
7a3e97b0 6296 }
3441da7d
SRT		 6297 }
6298 spin_lock_irqsave(host->host_lock, flags);
6299 ufshcd_transfer_req_compl(hba);
6300 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 6301
7a3e97b0 6302out:
7fabb77b 6303 hba->req_abort_count = 0;
8808b4e9 6304 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
3441da7d
SRT		 6305 if (!err) {
6306 err = SUCCESS;
6307 } else {
6308 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6309 err = FAILED;
6310 }
7a3e97b0
SY		 6311 return err;
6312}
6313
e0b299e3
GB		 6314static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6315{
6316 struct ufshcd_lrb *lrbp;
6317 int tag;
6318
6319 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6320 lrbp = &hba->lrb[tag];
6321 lrbp->req_abort_skip = true;
6322 }
6323}
6324
7a3e97b0
SY		 6325/**
6326 * ufshcd_abort - abort a specific command
6327 * @cmd: SCSI command pointer
6328 *
f20810d8
SRT		 6329 * Abort the pending command in device by sending UFS_ABORT_TASK task management
6330 * command, and in host controller by clearing the door-bell register. There can
6331 * be race between controller sending the command to the device while abort is
6332 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6333 * really issued and then try to abort it.
6334 *
7a3e97b0
SY		 6335 * Returns SUCCESS/FAILED
6336 */
6337static int ufshcd_abort(struct scsi_cmnd *cmd)
6338{
6339 struct Scsi_Host *host;
6340 struct ufs_hba *hba;
6341 unsigned long flags;
6342 unsigned int tag;
f20810d8
SRT		 6343 int err = 0;
6344 int poll_cnt;
e2933132
SRT		 6345 u8 resp = 0xF;
6346 struct ufshcd_lrb *lrbp;
e9d501b1 6347 u32 reg;
7a3e97b0
SY		 6348
6349 host = cmd->device->host;
6350 hba = shost_priv(host);
6351 tag = cmd->request->tag;
e7d38257 6352 lrbp = &hba->lrb[tag];
14497328
YG		 6353 if (!ufshcd_valid_tag(hba, tag)) {
6354 dev_err(hba->dev,
6355 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6356 __func__, tag, cmd, cmd->request);
6357 BUG();
6358 }
7a3e97b0 6359
e7d38257
DR		 6360 /*
6361 * Task abort to the device W-LUN is illegal. When this command
6362 * will fail, due to spec violation, scsi err handling next step
6363 * will be to send LU reset which, again, is a spec violation.
6364 * To avoid these unnecessary/illegal step we skip to the last error
6365 * handling stage: reset and restore.
6366 */
6367 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6368 return ufshcd_eh_host_reset_handler(cmd);
6369
1ab27c9c 6370 ufshcd_hold(hba, false);
14497328 6371 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 6372 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 6373 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6374 dev_err(hba->dev,
6375 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6376 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 6377 goto out;
14497328 6378 }
7a3e97b0 6379
e9d501b1
DR		 6380 if (!(reg & (1 << tag))) {
6381 dev_err(hba->dev,
6382 "%s: cmd was completed, but without a notifying intr, tag = %d",
6383 __func__, tag);
6384 }
6385
66cc820f
DR		 6386 /* Print Transfer Request of aborted task */
6387 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 6388
7fabb77b
GB		 6389 /*
6390 * Print detailed info about aborted request.
6391 * As more than one request might get aborted at the same time,
6392 * print full information only for the first aborted request in order
6393 * to reduce repeated printouts. For other aborted requests only print
6394 * basic details.
6395 */
6396 scsi_print_command(hba->lrb[tag].cmd);
6397 if (!hba->req_abort_count) {
8808b4e9 6398 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
7fabb77b 6399 ufshcd_print_host_regs(hba);
6ba65588 6400 ufshcd_print_host_state(hba);
7fabb77b
GB		 6401 ufshcd_print_pwr_info(hba);
6402 ufshcd_print_trs(hba, 1 << tag, true);
6403 } else {
6404 ufshcd_print_trs(hba, 1 << tag, false);
6405 }
6406 hba->req_abort_count++;
e0b299e3
GB		 6407
6408 /* Skip task abort in case previous aborts failed and report failure */
6409 if (lrbp->req_abort_skip) {
6410 err = -EIO;
6411 goto out;
6412 }
6413
f20810d8
SRT		 6414 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6415 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6416 UFS_QUERY_TASK, &resp);
6417 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6418 /* cmd pending in the device */
ff8e20c6
DR		 6419 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6420 __func__, tag);
f20810d8
SRT		 6421 break;
6422 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6423 /*
6424 * cmd not pending in the device, check if it is
6425 * in transition.
6426 */
ff8e20c6
DR		 6427 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6428 __func__, tag);
f20810d8
SRT		 6429 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6430 if (reg & (1 << tag)) {
6431 /* sleep for max. 200us to stabilize */
6432 usleep_range(100, 200);
6433 continue;
6434 }
6435 /* command completed already */
ff8e20c6
DR		 6436 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6437 __func__, tag);
f20810d8
SRT		 6438 goto out;
6439 } else {
ff8e20c6
DR		 6440 dev_err(hba->dev,
6441 "%s: no response from device. tag = %d, err %d\n",
6442 __func__, tag, err);
f20810d8
SRT		 6443 if (!err)
6444 err = resp; /* service response error */
6445 goto out;
6446 }
6447 }
6448
6449 if (!poll_cnt) {
6450 err = -EBUSY;
7a3e97b0
SY		 6451 goto out;
6452 }
7a3e97b0 6453
e2933132
SRT		 6454 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6455 UFS_ABORT_TASK, &resp);
6456 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6457 if (!err) {
f20810d8 6458 err = resp; /* service response error */
ff8e20c6
DR		 6459 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6460 __func__, tag, err);
6461 }
7a3e97b0 6462 goto out;
e2933132 6463 }
7a3e97b0 6464
f20810d8 6465 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6466 if (err) {
6467 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6468 __func__, tag, err);
f20810d8 6469 goto out;
ff8e20c6 6470 }
f20810d8 6471
7a3e97b0
SY		 6472 scsi_dma_unmap(cmd);
6473
6474 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6475 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6476 hba->lrb[tag].cmd = NULL;
6477 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9 6478
7a3e97b0 6479out:
f20810d8
SRT		 6480 if (!err) {
6481 err = SUCCESS;
6482 } else {
6483 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6484 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6485 err = FAILED;
6486 }
6487
1ab27c9c
ST		 6488 /*
6489 * This ufshcd_release() corresponds to the original scsi cmd that got
6490 * aborted here (as we won't get any IRQ for it).
6491 */
6492 ufshcd_release(hba);
7a3e97b0
SY		 6493 return err;
6494}
6495
3441da7d
SRT		 6496/**
6497 * ufshcd_host_reset_and_restore - reset and restore host controller
6498 * @hba: per-adapter instance
6499 *
6500 * Note that host controller reset may issue DME_RESET to
6501 * local and remote (device) Uni-Pro stack and the attributes
6502 * are reset to default state.
6503 *
6504 * Returns zero on success, non-zero on failure
6505 */
6506static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6507{
6508 int err;
3441da7d
SRT		 6509 unsigned long flags;
6510
2df74b69
CG		 6511 /*
6512 * Stop the host controller and complete the requests
6513 * cleared by h/w
6514 */
5cac1095
BVA		 6515 ufshcd_hba_stop(hba);
6516
3441da7d 6517 spin_lock_irqsave(hba->host->host_lock, flags);
2df74b69
CG		 6518 hba->silence_err_logs = true;
6519 ufshcd_complete_requests(hba);
6520 hba->silence_err_logs = false;
3441da7d
SRT		 6521 spin_unlock_irqrestore(hba->host->host_lock, flags);
6522
a3cd5ec5 6523 /* scale up clocks to max frequency before full reinitialization */
394b949f 6524 ufshcd_set_clk_freq(hba, true);
a3cd5ec5 6525
3441da7d
SRT		 6526 err = ufshcd_hba_enable(hba);
6527 if (err)
6528 goto out;
6529
6530 /* Establish the link again and restore the device */
1b9e2141 6531 err = ufshcd_probe_hba(hba, false);
1d337ec2
SRT		 6532
6533 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 6534 err = -EIO;
6535out:
6536 if (err)
6537 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
8808b4e9 6538 ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
3441da7d
SRT		 6539 return err;
6540}
6541
6542/**
6543 * ufshcd_reset_and_restore - reset and re-initialize host/device
6544 * @hba: per-adapter instance
6545 *
6546 * Reset and recover device, host and re-establish link. This
6547 * is helpful to recover the communication in fatal error conditions.
6548 *
6549 * Returns zero on success, non-zero on failure
6550 */
6551static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6552{
6553 int err = 0;
1d337ec2 6554 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6555
1d337ec2 6556 do {
d8d9f793
BA		 6557 /* Reset the attached device */
6558 ufshcd_vops_device_reset(hba);
6559
1d337ec2
SRT		 6560 err = ufshcd_host_reset_and_restore(hba);
6561 } while (err && --retries);
3441da7d 6562
3441da7d
SRT		 6563 return err;
6564}
6565
6566/**
6567 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6568 * @cmd: SCSI command pointer
3441da7d
SRT		 6569 *
6570 * Returns SUCCESS/FAILED
6571 */
6572static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6573{
6574 int err;
6575 unsigned long flags;
6576 struct ufs_hba *hba;
6577
6578 hba = shost_priv(cmd->device->host);
6579
1ab27c9c 6580 ufshcd_hold(hba, false);
3441da7d
SRT		 6581 /*
6582 * Check if there is any race with fatal error handling.
6583 * If so, wait for it to complete. Even though fatal error
6584 * handling does reset and restore in some cases, don't assume
6585 * anything out of it. We are just avoiding race here.
6586 */
6587 do {
6588 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6589 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6590 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6591 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6592 break;
6593 spin_unlock_irqrestore(hba->host->host_lock, flags);
6594 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6595 flush_work(&hba->eh_work);
3441da7d
SRT		 6596 } while (1);
6597
6598 hba->ufshcd_state = UFSHCD_STATE_RESET;
6599 ufshcd_set_eh_in_progress(hba);
6600 spin_unlock_irqrestore(hba->host->host_lock, flags);
6601
6602 err = ufshcd_reset_and_restore(hba);
6603
6604 spin_lock_irqsave(hba->host->host_lock, flags);
6605 if (!err) {
6606 err = SUCCESS;
6607 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6608 } else {
6609 err = FAILED;
6610 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6611 }
6612 ufshcd_clear_eh_in_progress(hba);
6613 spin_unlock_irqrestore(hba->host->host_lock, flags);
6614
1ab27c9c 6615 ufshcd_release(hba);
3441da7d
SRT		 6616 return err;
6617}
6618
3a4bf06d
YG		 6619/**
6620 * ufshcd_get_max_icc_level - calculate the ICC level
6621 * @sup_curr_uA: max. current supported by the regulator
6622 * @start_scan: row at the desc table to start scan from
6623 * @buff: power descriptor buffer
6624 *
6625 * Returns calculated max ICC level for specific regulator
6626 */
6627static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6628{
6629 int i;
6630 int curr_uA;
6631 u16 data;
6632 u16 unit;
6633
6634 for (i = start_scan; i >= 0; i--) {
d79713f9 6635 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6636 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6637 ATTR_ICC_LVL_UNIT_OFFSET;
6638 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6639 switch (unit) {
6640 case UFSHCD_NANO_AMP:
6641 curr_uA = curr_uA / 1000;
6642 break;
6643 case UFSHCD_MILI_AMP:
6644 curr_uA = curr_uA * 1000;
6645 break;
6646 case UFSHCD_AMP:
6647 curr_uA = curr_uA * 1000 * 1000;
6648 break;
6649 case UFSHCD_MICRO_AMP:
6650 default:
6651 break;
6652 }
6653 if (sup_curr_uA >= curr_uA)
6654 break;
6655 }
6656 if (i < 0) {
6657 i = 0;
6658 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6659 }
6660
6661 return (u32)i;
6662}
6663
6664/**
6665 * ufshcd_calc_icc_level - calculate the max ICC level
6666 * In case regulators are not initialized we'll return 0
6667 * @hba: per-adapter instance
6668 * @desc_buf: power descriptor buffer to extract ICC levels from.
6669 * @len: length of desc_buff
6670 *
6671 * Returns calculated ICC level
6672 */
6673static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6674 u8 *desc_buf, int len)
6675{
6676 u32 icc_level = 0;
6677
6678 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6679 !hba->vreg_info.vccq2) {
6680 dev_err(hba->dev,
6681 "%s: Regulator capability was not set, actvIccLevel=%d",
6682 __func__, icc_level);
6683 goto out;
6684 }
6685
0487fff7 6686 if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 6687 icc_level = ufshcd_get_max_icc_level(
6688 hba->vreg_info.vcc->max_uA,
6689 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6690 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6691
0487fff7 6692 if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 6693 icc_level = ufshcd_get_max_icc_level(
6694 hba->vreg_info.vccq->max_uA,
6695 icc_level,
6696 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6697
0487fff7 6698 if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 6699 icc_level = ufshcd_get_max_icc_level(
6700 hba->vreg_info.vccq2->max_uA,
6701 icc_level,
6702 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6703out:
6704 return icc_level;
6705}
6706
e89860f1 6707static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 6708{
6709 int ret;
7a0bf85b 6710 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
bbe21d7a 6711 u8 *desc_buf;
e89860f1 6712 u32 icc_level;
bbe21d7a
KC		 6713
6714 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6715 if (!desc_buf)
6716 return;
3a4bf06d 6717
c4607a09
BH		 6718 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
6719 desc_buf, buff_len);
3a4bf06d
YG		 6720 if (ret) {
6721 dev_err(hba->dev,
6722 "%s: Failed reading power descriptor.len = %d ret = %d",
6723 __func__, buff_len, ret);
bbe21d7a 6724 goto out;
3a4bf06d
YG		 6725 }
6726
e89860f1
CG		 6727 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
6728 buff_len);
6729 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 6730
dbd34a61 6731 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 6732 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 6733
6734 if (ret)
6735 dev_err(hba->dev,
6736 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 6737 __func__, icc_level, ret);
3a4bf06d 6738
bbe21d7a
KC		 6739out:
6740 kfree(desc_buf);
3a4bf06d
YG		 6741}
6742
fb276f77
CG		 6743static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
6744{
6745 scsi_autopm_get_device(sdev);
6746 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
6747 if (sdev->rpm_autosuspend)
6748 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
6749 RPM_AUTOSUSPEND_DELAY_MS);
6750 scsi_autopm_put_device(sdev);
6751}
6752
2a8fa600
SJ		 6753/**
6754 * ufshcd_scsi_add_wlus - Adds required W-LUs
6755 * @hba: per-adapter instance
6756 *
6757 * UFS device specification requires the UFS devices to support 4 well known
6758 * logical units:
6759 * "REPORT_LUNS" (address: 01h)
6760 * "UFS Device" (address: 50h)
6761 * "RPMB" (address: 44h)
6762 * "BOOT" (address: 30h)
6763 * UFS device's power management needs to be controlled by "POWER CONDITION"
6764 * field of SSU (START STOP UNIT) command. But this "power condition" field
6765 * will take effect only when its sent to "UFS device" well known logical unit
6766 * hence we require the scsi_device instance to represent this logical unit in
6767 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6768 *
2a8fa600
SJ		 6769 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6770 * Block) LU so user space process can control this LU. User space may also
6771 * want to have access to BOOT LU.
8aa29f19 6772 *
2a8fa600
SJ		 6773 * This function adds scsi device instances for each of all well known LUs
6774 * (except "REPORT LUNS" LU).
6775 *
6776 * Returns zero on success (all required W-LUs are added successfully),
6777 * non-zero error value on failure (if failed to add any of the required W-LU).
6778 */
6779static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6780{
6781 int ret = 0;
7c48bfd0
AM		 6782 struct scsi_device *sdev_rpmb;
6783 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6784
6785 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6786 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6787 if (IS_ERR(hba->sdev_ufs_device)) {
6788 ret = PTR_ERR(hba->sdev_ufs_device);
6789 hba->sdev_ufs_device = NULL;
6790 goto out;
6791 }
fb276f77 6792 ufshcd_blk_pm_runtime_init(hba->sdev_ufs_device);
7c48bfd0 6793 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6794
7c48bfd0 6795 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6796 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6797 if (IS_ERR(sdev_rpmb)) {
6798 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6799 goto remove_sdev_ufs_device;
2a8fa600 6800 }
fb276f77 6801 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7c48bfd0 6802 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6803
6804 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6805 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 6806 if (IS_ERR(sdev_boot)) {
3d21fbde 6807 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 6808 } else {
6809 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 6810 scsi_device_put(sdev_boot);
fb276f77 6811 }
2a8fa600
SJ		 6812 goto out;
6813
2a8fa600
SJ		 6814remove_sdev_ufs_device:
6815 scsi_remove_device(hba->sdev_ufs_device);
6816out:
6817 return ret;
6818}
6819
3d17b9b5
AD		 6820static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
6821{
6f8d5a6a
SC		 6822 u8 lun;
6823 u32 d_lu_wb_buf_alloc;
6824
817d7e14
SC		 6825 if (!ufshcd_is_wb_allowed(hba))
6826 return;
6827
7a0bf85b
BH		 6828 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
6829 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
817d7e14
SC		 6830 goto wb_disabled;
6831
3d17b9b5
AD		 6832 hba->dev_info.d_ext_ufs_feature_sup =
6833 get_unaligned_be32(desc_buf +
6834 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
817d7e14
SC		 6835
6836 if (!(hba->dev_info.d_ext_ufs_feature_sup & UFS_DEV_WRITE_BOOSTER_SUP))
6837 goto wb_disabled;
6838
3d17b9b5
AD		 6839 /*
6840 * WB may be supported but not configured while provisioning.
6841 * The spec says, in dedicated wb buffer mode,
6842 * a max of 1 lun would have wb buffer configured.
6843 * Now only shared buffer mode is supported.
6844 */
6845 hba->dev_info.b_wb_buffer_type =
6846 desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
6847
3d17b9b5
AD		 6848 hba->dev_info.b_presrv_uspc_en =
6849 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
6850
6f8d5a6a
SC		 6851 if (hba->dev_info.b_wb_buffer_type == WB_BUF_MODE_SHARED) {
6852 hba->dev_info.d_wb_alloc_units =
6853 get_unaligned_be32(desc_buf +
6854 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS);
6855 if (!hba->dev_info.d_wb_alloc_units)
6856 goto wb_disabled;
6857 } else {
6858 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
6859 d_lu_wb_buf_alloc = 0;
6860 ufshcd_read_unit_desc_param(hba,
6861 lun,
6862 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
6863 (u8 *)&d_lu_wb_buf_alloc,
6864 sizeof(d_lu_wb_buf_alloc));
6865 if (d_lu_wb_buf_alloc) {
6866 hba->dev_info.wb_dedicated_lu = lun;
6867 break;
6868 }
6869 }
817d7e14 6870
6f8d5a6a
SC		 6871 if (!d_lu_wb_buf_alloc)
6872 goto wb_disabled;
6873 }
817d7e14
SC		 6874 return;
6875
6876wb_disabled:
6877 hba->caps &= ~UFSHCD_CAP_WB_EN;
6878}
6879
8db269a5 6880void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
817d7e14
SC		 6881{
6882 struct ufs_dev_fix *f;
6883 struct ufs_dev_info *dev_info = &hba->dev_info;
6884
8db269a5
SC		 6885 if (!fixups)
6886 return;
6887
6888 for (f = fixups; f->quirk; f++) {
817d7e14
SC		 6889 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
6890 f->wmanufacturerid == UFS_ANY_VENDOR) &&
6891 ((dev_info->model &&
6892 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
6893 !strcmp(f->model, UFS_ANY_MODEL)))
6894 hba->dev_quirks |= f->quirk;
6895 }
3d17b9b5 6896}
8db269a5 6897EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
3d17b9b5 6898
c28c00ba
SC		 6899static void ufs_fixup_device_setup(struct ufs_hba *hba)
6900{
6901 /* fix by general quirk table */
8db269a5 6902 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
c28c00ba
SC		 6903
6904 /* allow vendors to fix quirks */
6905 ufshcd_vops_fixup_dev_quirks(hba);
6906}
6907
09750066 6908static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 6909{
6910 int err;
6911 u8 model_index;
bbe21d7a 6912 u8 *desc_buf;
09750066 6913 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 6914
458a45f5 6915 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 6916 if (!desc_buf) {
6917 err = -ENOMEM;
6918 goto out;
6919 }
c58ab7aa 6920
c4607a09 6921 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7a0bf85b 6922 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
c58ab7aa
YG		 6923 if (err) {
6924 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6925 __func__, err);
6926 goto out;
6927 }
6928
6929 /*
6930 * getting vendor (manufacturerID) and Bank Index in big endian
6931 * format
6932 */
09750066 6933 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6934 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6935
09f17791
CG		 6936 /* getting Specification Version in big endian format */
6937 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
6938 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
6939
c58ab7aa 6940 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5 6941
4b828fe1 6942 err = ufshcd_read_string_desc(hba, model_index,
09750066 6943 &dev_info->model, SD_ASCII_STD);
4b828fe1 6944 if (err < 0) {
c58ab7aa
YG		 6945 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6946 __func__, err);
6947 goto out;
6948 }
6949
817d7e14
SC		 6950 ufs_fixup_device_setup(hba);
6951
6952 /*
6953 * Probe WB only for UFS-3.1 devices or UFS devices with quirk
6954 * UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES enabled
6955 */
6956 if (dev_info->wspecversion >= 0x310 ||
c7cee3e7 6957 dev_info->wspecversion == 0x220 ||
817d7e14
SC		 6958 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))
6959 ufshcd_wb_probe(hba, desc_buf);
6960
4b828fe1
TW		 6961 /*
6962 * ufshcd_read_string_desc returns size of the string
6963 * reset the error value
6964 */
6965 err = 0;
c58ab7aa
YG		 6966
6967out:
bbe21d7a 6968 kfree(desc_buf);
c58ab7aa
YG		 6969 return err;
6970}
6971
09750066 6972static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 6973{
09750066
BH		 6974 struct ufs_dev_info *dev_info = &hba->dev_info;
6975
6976 kfree(dev_info->model);
6977 dev_info->model = NULL;
4b828fe1
TW		 6978}
6979
37113106
YG		 6980/**
6981 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6982 * @hba: per-adapter instance
6983 *
6984 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6985 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6986 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6987 * the hibern8 exit latency.
6988 *
6989 * Returns zero on success, non-zero error value on failure.
6990 */
6991static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6992{
6993 int ret = 0;
6994 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6995
6996 ret = ufshcd_dme_peer_get(hba,
6997 UIC_ARG_MIB_SEL(
6998 RX_MIN_ACTIVATETIME_CAPABILITY,
6999 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7000 &peer_rx_min_activatetime);
7001 if (ret)
7002 goto out;
7003
7004 /* make sure proper unit conversion is applied */
7005 tuned_pa_tactivate =
7006 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7007 / PA_TACTIVATE_TIME_UNIT_US);
7008 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7009 tuned_pa_tactivate);
7010
7011out:
7012 return ret;
7013}
7014
7015/**
7016 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7017 * @hba: per-adapter instance
7018 *
7019 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7020 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7021 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7022 * This optimal value can help reduce the hibern8 exit latency.
7023 *
7024 * Returns zero on success, non-zero error value on failure.
7025 */
7026static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7027{
7028 int ret = 0;
7029 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7030 u32 max_hibern8_time, tuned_pa_hibern8time;
7031
7032 ret = ufshcd_dme_get(hba,
7033 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7034 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7035 &local_tx_hibern8_time_cap);
7036 if (ret)
7037 goto out;
7038
7039 ret = ufshcd_dme_peer_get(hba,
7040 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7041 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7042 &peer_rx_hibern8_time_cap);
7043 if (ret)
7044 goto out;
7045
7046 max_hibern8_time = max(local_tx_hibern8_time_cap,
7047 peer_rx_hibern8_time_cap);
7048 /* make sure proper unit conversion is applied */
7049 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7050 / PA_HIBERN8_TIME_UNIT_US);
7051 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7052 tuned_pa_hibern8time);
7053out:
7054 return ret;
7055}
7056
c6a6db43 7057/**
7058 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7059 * less than device PA_TACTIVATE time.
7060 * @hba: per-adapter instance
7061 *
7062 * Some UFS devices require host PA_TACTIVATE to be lower than device
7063 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7064 * for such devices.
7065 *
7066 * Returns zero on success, non-zero error value on failure.
7067 */
7068static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7069{
7070 int ret = 0;
7071 u32 granularity, peer_granularity;
7072 u32 pa_tactivate, peer_pa_tactivate;
7073 u32 pa_tactivate_us, peer_pa_tactivate_us;
7074 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7075
7076 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7077 &granularity);
7078 if (ret)
7079 goto out;
7080
7081 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7082 &peer_granularity);
7083 if (ret)
7084 goto out;
7085
7086 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7087 (granularity > PA_GRANULARITY_MAX_VAL)) {
7088 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7089 __func__, granularity);
7090 return -EINVAL;
7091 }
7092
7093 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7094 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7095 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7096 __func__, peer_granularity);
7097 return -EINVAL;
7098 }
7099
7100 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7101 if (ret)
7102 goto out;
7103
7104 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7105 &peer_pa_tactivate);
7106 if (ret)
7107 goto out;
7108
7109 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7110 peer_pa_tactivate_us = peer_pa_tactivate *
7111 gran_to_us_table[peer_granularity - 1];
7112
7113 if (pa_tactivate_us > peer_pa_tactivate_us) {
7114 u32 new_peer_pa_tactivate;
7115
7116 new_peer_pa_tactivate = pa_tactivate_us /
7117 gran_to_us_table[peer_granularity - 1];
7118 new_peer_pa_tactivate++;
7119 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7120 new_peer_pa_tactivate);
7121 }
7122
7123out:
7124 return ret;
7125}
7126
09750066 7127static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 7128{
7129 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7130 ufshcd_tune_pa_tactivate(hba);
7131 ufshcd_tune_pa_hibern8time(hba);
7132 }
7133
e91ed9e0
CG		 7134 ufshcd_vops_apply_dev_quirks(hba);
7135
37113106
YG		 7136 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7137 /* set 1ms timeout for PA_TACTIVATE */
7138 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 7139
7140 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7141 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 7142}
7143
ff8e20c6
DR		 7144static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7145{
ff8e20c6
DR		 7146 hba->ufs_stats.hibern8_exit_cnt = 0;
7147 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 7148 hba->req_abort_count = 0;
ff8e20c6
DR		 7149}
7150
731f0621
BH		 7151static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7152{
7153 int err;
7154 size_t buff_len;
7155 u8 *desc_buf;
7156
7a0bf85b 7157 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
731f0621
BH		 7158 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7159 if (!desc_buf) {
7160 err = -ENOMEM;
7161 goto out;
7162 }
7163
c4607a09
BH		 7164 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7165 desc_buf, buff_len);
731f0621
BH		 7166 if (err) {
7167 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7168 __func__, err);
7169 goto out;
7170 }
7171
7172 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7173 hba->dev_info.max_lu_supported = 32;
7174 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7175 hba->dev_info.max_lu_supported = 8;
7176
7177out:
7178 kfree(desc_buf);
7179 return err;
7180}
7181
9e1e8a75
SJ		 7182static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7183 {19200000, REF_CLK_FREQ_19_2_MHZ},
7184 {26000000, REF_CLK_FREQ_26_MHZ},
7185 {38400000, REF_CLK_FREQ_38_4_MHZ},
7186 {52000000, REF_CLK_FREQ_52_MHZ},
7187 {0, REF_CLK_FREQ_INVAL},
7188};
7189
7190static enum ufs_ref_clk_freq
7191ufs_get_bref_clk_from_hz(unsigned long freq)
7192{
7193 int i;
7194
7195 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7196 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7197 return ufs_ref_clk_freqs[i].val;
7198
7199 return REF_CLK_FREQ_INVAL;
7200}
7201
7202void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7203{
7204 unsigned long freq;
7205
7206 freq = clk_get_rate(refclk);
7207
7208 hba->dev_ref_clk_freq =
7209 ufs_get_bref_clk_from_hz(freq);
7210
7211 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7212 dev_err(hba->dev,
7213 "invalid ref_clk setting = %ld\n", freq);
7214}
7215
7216static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7217{
7218 int err;
7219 u32 ref_clk;
7220 u32 freq = hba->dev_ref_clk_freq;
7221
7222 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7223 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7224
7225 if (err) {
7226 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7227 err);
7228 goto out;
7229 }
7230
7231 if (ref_clk == freq)
7232 goto out; /* nothing to update */
7233
7234 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7235 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7236
7237 if (err) {
7238 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7239 ufs_ref_clk_freqs[freq].freq_hz);
7240 goto out;
7241 }
7242
7243 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7244 ufs_ref_clk_freqs[freq].freq_hz);
7245
7246out:
7247 return err;
7248}
7249
1b9e2141
BH		 7250static int ufshcd_device_params_init(struct ufs_hba *hba)
7251{
7252 bool flag;
7a0bf85b 7253 int ret, i;
1b9e2141 7254
7a0bf85b
BH		 7255 /* Init device descriptor sizes */
7256 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7257 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
1b9e2141 7258
731f0621
BH		 7259 /* Init UFS geometry descriptor related parameters */
7260 ret = ufshcd_device_geo_params_init(hba);
7261 if (ret)
7262 goto out;
7263
1b9e2141
BH		 7264 /* Check and apply UFS device quirks */
7265 ret = ufs_get_device_desc(hba);
7266 if (ret) {
7267 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7268 __func__, ret);
7269 goto out;
7270 }
7271
09f17791
CG		 7272 ufshcd_get_ref_clk_gating_wait(hba);
7273
1b9e2141 7274 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 7275 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
1b9e2141
BH		 7276 hba->dev_info.f_power_on_wp_en = flag;
7277
2b35b2ad
BH		 7278 /* Probe maximum power mode co-supported by both UFS host and device */
7279 if (ufshcd_get_max_pwr_mode(hba))
7280 dev_err(hba->dev,
7281 "%s: Failed getting max supported power mode\n",
7282 __func__);
1b9e2141
BH		 7283out:
7284 return ret;
7285}
7286
7287/**
7288 * ufshcd_add_lus - probe and add UFS logical units
7289 * @hba: per-adapter instance
7290 */
7291static int ufshcd_add_lus(struct ufs_hba *hba)
7292{
7293 int ret;
7294
1b9e2141
BH		 7295 /* Add required well known logical units to scsi mid layer */
7296 ret = ufshcd_scsi_add_wlus(hba);
7297 if (ret)
7298 goto out;
7299
7300 /* Initialize devfreq after UFS device is detected */
7301 if (ufshcd_is_clkscaling_supported(hba)) {
7302 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7303 &hba->pwr_info,
7304 sizeof(struct ufs_pa_layer_attr));
7305 hba->clk_scaling.saved_pwr_info.is_valid = true;
7306 if (!hba->devfreq) {
7307 ret = ufshcd_devfreq_init(hba);
7308 if (ret)
7309 goto out;
7310 }
7311
7312 hba->clk_scaling.is_allowed = true;
7313 }
7314
7315 ufs_bsg_probe(hba);
7316 scsi_scan_host(hba->host);
7317 pm_runtime_put_sync(hba->dev);
7318
1b9e2141
BH		 7319out:
7320 return ret;
7321}
7322
6ccf44fe 7323/**
1d337ec2
SRT		 7324 * ufshcd_probe_hba - probe hba to detect device and initialize
7325 * @hba: per-adapter instance
1b9e2141 7326 * @async: asynchronous execution or not
1d337ec2
SRT		 7327 *
7328 * Execute link-startup and verify device initialization
6ccf44fe 7329 */
1b9e2141 7330static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
6ccf44fe 7331{
6ccf44fe 7332 int ret;
7ff5ab47 7333 ktime_t start = ktime_get();
6ccf44fe
SJ		 7334
7335 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 7336 if (ret)
7337 goto out;
7338
ff8e20c6
DR		 7339 /* Debug counters initialization */
7340 ufshcd_clear_dbg_ufs_stats(hba);
7341
57d104c1
SJ		 7342 /* UniPro link is active now */
7343 ufshcd_set_link_active(hba);
d3e89bac 7344
1b9e2141 7345 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 7346 ret = ufshcd_verify_dev_init(hba);
7347 if (ret)
7348 goto out;
68078d5c 7349
1b9e2141 7350 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 7351 ret = ufshcd_complete_dev_init(hba);
7352 if (ret)
7353 goto out;
5a0b0cb9 7354
1b9e2141
BH		 7355 /*
7356 * Initialize UFS device parameters used by driver, these
7357 * parameters are associated with UFS descriptors.
7358 */
7359 if (async) {
7360 ret = ufshcd_device_params_init(hba);
7361 if (ret)
7362 goto out;
93fdd5ac
TW		 7363 }
7364
09750066 7365 ufshcd_tune_unipro_params(hba);
4b828fe1 7366
57d104c1
SJ		 7367 /* UFS device is also active now */
7368 ufshcd_set_ufs_dev_active(hba);
66ec6d59 7369 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 7370 hba->wlun_dev_clr_ua = true;
7371
2b35b2ad
BH		 7372 /* Gear up to HS gear if supported */
7373 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 7374 /*
7375 * Set the right value to bRefClkFreq before attempting to
7376 * switch to HS gears.
7377 */
7378 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
7379 ufshcd_set_dev_ref_clk(hba);
7eb584db 7380 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 7381 if (ret) {
7eb584db
DR		 7382 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
7383 __func__, ret);
8643ae66
DL		 7384 goto out;
7385 }
6a9df818 7386 ufshcd_print_pwr_info(hba);
7eb584db 7387 }
57d104c1 7388
e89860f1
CG		 7389 /*
7390 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
7391 * and for removable UFS card as well, hence always set the parameter.
7392 * Note: Error handler may issue the device reset hence resetting
7393 * bActiveICCLevel as well so it is always safe to set this here.
7394 */
7395 ufshcd_set_active_icc_lvl(hba);
7396
53c12d0e
YG		 7397 /* set the state as operational after switching to desired gear */
7398 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 7399
3d17b9b5 7400 ufshcd_wb_config(hba);
71d848b8
CG		 7401 /* Enable Auto-Hibernate if configured */
7402 ufshcd_auto_hibern8_enable(hba);
7403
5a0b0cb9 7404out:
1d337ec2 7405
7ff5ab47 7406 trace_ufshcd_init(dev_name(hba->dev), ret,
7407 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7408 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 7409 return ret;
7410}
7411
7412/**
7413 * ufshcd_async_scan - asynchronous execution for probing hba
7414 * @data: data pointer to pass to this function
7415 * @cookie: cookie data
7416 */
7417static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7418{
7419 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 7420 int ret;
1d337ec2 7421
1b9e2141
BH		 7422 /* Initialize hba, detect and initialize UFS device */
7423 ret = ufshcd_probe_hba(hba, true);
7424 if (ret)
7425 goto out;
7426
7427 /* Probe and add UFS logical units */
7428 ret = ufshcd_add_lus(hba);
7429out:
7430 /*
7431 * If we failed to initialize the device or the device is not
7432 * present, turn off the power/clocks etc.
7433 */
7434 if (ret) {
7435 pm_runtime_put_sync(hba->dev);
7436 ufshcd_exit_clk_scaling(hba);
7437 ufshcd_hba_exit(hba);
7438 }
6ccf44fe
SJ		 7439}
7440
d829fc8a
SN		 7441static const struct attribute_group *ufshcd_driver_groups[] = {
7442 &ufs_sysfs_unit_descriptor_group,
ec92b59c 7443 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 7444 NULL,
7445};
7446
90b8491c
SC		 7447static struct ufs_hba_variant_params ufs_hba_vps = {
7448 .hba_enable_delay_us = 1000,
d14734ae 7449 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
90b8491c
SC		 7450 .devfreq_profile.polling_ms = 100,
7451 .devfreq_profile.target = ufshcd_devfreq_target,
7452 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
7453 .ondemand_data.upthreshold = 70,
7454 .ondemand_data.downdifferential = 5,
7455};
7456
7a3e97b0
SY		 7457static struct scsi_host_template ufshcd_driver_template = {
7458 .module = THIS_MODULE,
7459 .name = UFSHCD,
7460 .proc_name = UFSHCD,
7461 .queuecommand = ufshcd_queuecommand,
7462 .slave_alloc = ufshcd_slave_alloc,
eeda4749 7463 .slave_configure = ufshcd_slave_configure,
7a3e97b0 7464 .slave_destroy = ufshcd_slave_destroy,
4264fd61 7465 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 7466 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 7467 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7468 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 7469 .this_id = -1,
7470 .sg_tablesize = SG_ALL,
7471 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7472 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 7473 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 7474 .max_host_blocked = 1,
c40ecc12 7475 .track_queue_depth = 1,
d829fc8a 7476 .sdev_groups = ufshcd_driver_groups,
4af14d11 7477 .dma_boundary = PAGE_SIZE - 1,
49615ba1 7478 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 7479};
7480
57d104c1
SJ		 7481static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7482 int ua)
7483{
7b16a07c 7484 int ret;
57d104c1 7485
7b16a07c
BA		 7486 if (!vreg)
7487 return 0;
57d104c1 7488
0487fff7
SC		 7489 /*
7490 * "set_load" operation shall be required on those regulators
7491 * which specifically configured current limitation. Otherwise
7492 * zero max_uA may cause unexpected behavior when regulator is
7493 * enabled or set as high power mode.
7494 */
7495 if (!vreg->max_uA)
7496 return 0;
7497
7b16a07c
BA		 7498 ret = regulator_set_load(vreg->reg, ua);
7499 if (ret < 0) {
7500 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7501 __func__, vreg->name, ua, ret);
57d104c1
SJ		 7502 }
7503
7504 return ret;
7505}
7506
7507static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7508 struct ufs_vreg *vreg)
7509{
73067981 7510 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 7511}
7512
7513static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7514 struct ufs_vreg *vreg)
7515{
7c7cfdcf
AH		 7516 if (!vreg)
7517 return 0;
7518
73067981 7519 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 7520}
7521
aa497613
SRT		 7522static int ufshcd_config_vreg(struct device *dev,
7523 struct ufs_vreg *vreg, bool on)
7524{
7525 int ret = 0;
72753590
GS		 7526 struct regulator *reg;
7527 const char *name;
aa497613
SRT		 7528 int min_uV, uA_load;
7529
7530 BUG_ON(!vreg);
7531
72753590
GS		 7532 reg = vreg->reg;
7533 name = vreg->name;
7534
aa497613 7535 if (regulator_count_voltages(reg) > 0) {
90d88f47
AD		 7536 uA_load = on ? vreg->max_uA : 0;
7537 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7538 if (ret)
7539 goto out;
7540
3b141e8c
SC		 7541 if (vreg->min_uV && vreg->max_uV) {
7542 min_uV = on ? vreg->min_uV : 0;
7543 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7544 if (ret) {
7545 dev_err(dev,
7546 "%s: %s set voltage failed, err=%d\n",
aa497613 7547 __func__, name, ret);
3b141e8c
SC		 7548 goto out;
7549 }
aa497613 7550 }
aa497613
SRT		 7551 }
7552out:
7553 return ret;
7554}
7555
7556static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7557{
7558 int ret = 0;
7559
73067981 7560 if (!vreg || vreg->enabled)
aa497613
SRT		 7561 goto out;
7562
7563 ret = ufshcd_config_vreg(dev, vreg, true);
7564 if (!ret)
7565 ret = regulator_enable(vreg->reg);
7566
7567 if (!ret)
7568 vreg->enabled = true;
7569 else
7570 dev_err(dev, "%s: %s enable failed, err=%d\n",
7571 __func__, vreg->name, ret);
7572out:
7573 return ret;
7574}
7575
7576static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7577{
7578 int ret = 0;
7579
73067981 7580 if (!vreg || !vreg->enabled)
aa497613
SRT		 7581 goto out;
7582
7583 ret = regulator_disable(vreg->reg);
7584
7585 if (!ret) {
7586 /* ignore errors on applying disable config */
7587 ufshcd_config_vreg(dev, vreg, false);
7588 vreg->enabled = false;
7589 } else {
7590 dev_err(dev, "%s: %s disable failed, err=%d\n",
7591 __func__, vreg->name, ret);
7592 }
7593out:
7594 return ret;
7595}
7596
7597static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7598{
7599 int ret = 0;
7600 struct device *dev = hba->dev;
7601 struct ufs_vreg_info *info = &hba->vreg_info;
7602
aa497613
SRT		 7603 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7604 if (ret)
7605 goto out;
7606
7607 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7608 if (ret)
7609 goto out;
7610
7611 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7612 if (ret)
7613 goto out;
7614
7615out:
7616 if (ret) {
7617 ufshcd_toggle_vreg(dev, info->vccq2, false);
7618 ufshcd_toggle_vreg(dev, info->vccq, false);
7619 ufshcd_toggle_vreg(dev, info->vcc, false);
7620 }
7621 return ret;
7622}
7623
6a771a65
RS		 7624static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7625{
7626 struct ufs_vreg_info *info = &hba->vreg_info;
7627
60b7b823 7628 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 7629}
7630
aa497613
SRT		 7631static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7632{
7633 int ret = 0;
7634
7635 if (!vreg)
7636 goto out;
7637
7638 vreg->reg = devm_regulator_get(dev, vreg->name);
7639 if (IS_ERR(vreg->reg)) {
7640 ret = PTR_ERR(vreg->reg);
7641 dev_err(dev, "%s: %s get failed, err=%d\n",
7642 __func__, vreg->name, ret);
7643 }
7644out:
7645 return ret;
7646}
7647
7648static int ufshcd_init_vreg(struct ufs_hba *hba)
7649{
7650 int ret = 0;
7651 struct device *dev = hba->dev;
7652 struct ufs_vreg_info *info = &hba->vreg_info;
7653
aa497613
SRT		 7654 ret = ufshcd_get_vreg(dev, info->vcc);
7655 if (ret)
7656 goto out;
7657
7658 ret = ufshcd_get_vreg(dev, info->vccq);
7659 if (ret)
7660 goto out;
7661
7662 ret = ufshcd_get_vreg(dev, info->vccq2);
7663out:
7664 return ret;
7665}
7666
6a771a65
RS		 7667static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7668{
7669 struct ufs_vreg_info *info = &hba->vreg_info;
7670
7671 if (info)
7672 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7673
7674 return 0;
7675}
7676
57d104c1
SJ		 7677static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7678 bool skip_ref_clk)
c6e79dac
SRT		 7679{
7680 int ret = 0;
7681 struct ufs_clk_info *clki;
7682 struct list_head *head = &hba->clk_list_head;
1ab27c9c 7683 unsigned long flags;
911a0771 7684 ktime_t start = ktime_get();
7685 bool clk_state_changed = false;
c6e79dac 7686
566ec9ad 7687 if (list_empty(head))
c6e79dac
SRT		 7688 goto out;
7689
38f3242e
CG		 7690 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7691 if (ret)
7692 return ret;
1e879e8f 7693
c6e79dac
SRT		 7694 list_for_each_entry(clki, head, list) {
7695 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7696 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7697 continue;
7698
911a0771 7699 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7700 if (on && !clki->enabled) {
7701 ret = clk_prepare_enable(clki->clk);
7702 if (ret) {
7703 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7704 __func__, clki->name, ret);
7705 goto out;
7706 }
7707 } else if (!on && clki->enabled) {
7708 clk_disable_unprepare(clki->clk);
7709 }
7710 clki->enabled = on;
7711 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7712 clki->name, on ? "en" : "dis");
7713 }
7714 }
1ab27c9c 7715
38f3242e
CG		 7716 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7717 if (ret)
7718 return ret;
1e879e8f 7719
c6e79dac
SRT		 7720out:
7721 if (ret) {
7722 list_for_each_entry(clki, head, list) {
7723 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7724 clk_disable_unprepare(clki->clk);
7725 }
7ff5ab47 7726 } else if (!ret && on) {
1ab27c9c
ST		 7727 spin_lock_irqsave(hba->host->host_lock, flags);
7728 hba->clk_gating.state = CLKS_ON;
7ff5ab47 7729 trace_ufshcd_clk_gating(dev_name(hba->dev),
7730 hba->clk_gating.state);
1ab27c9c 7731 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7732 }
7ff5ab47 7733
911a0771 7734 if (clk_state_changed)
7735 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7736 (on ? "on" : "off"),
7737 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7738 return ret;
7739}
7740
57d104c1
SJ		 7741static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7742{
7743 return __ufshcd_setup_clocks(hba, on, false);
7744}
7745
c6e79dac
SRT		 7746static int ufshcd_init_clocks(struct ufs_hba *hba)
7747{
7748 int ret = 0;
7749 struct ufs_clk_info *clki;
7750 struct device *dev = hba->dev;
7751 struct list_head *head = &hba->clk_list_head;
7752
566ec9ad 7753 if (list_empty(head))
c6e79dac
SRT		 7754 goto out;
7755
7756 list_for_each_entry(clki, head, list) {
7757 if (!clki->name)
7758 continue;
7759
7760 clki->clk = devm_clk_get(dev, clki->name);
7761 if (IS_ERR(clki->clk)) {
7762 ret = PTR_ERR(clki->clk);
7763 dev_err(dev, "%s: %s clk get failed, %d\n",
7764 __func__, clki->name, ret);
7765 goto out;
7766 }
7767
9e1e8a75
SJ		 7768 /*
7769 * Parse device ref clk freq as per device tree "ref_clk".
7770 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
7771 * in ufshcd_alloc_host().
7772 */
7773 if (!strcmp(clki->name, "ref_clk"))
7774 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7775
c6e79dac
SRT		 7776 if (clki->max_freq) {
7777 ret = clk_set_rate(clki->clk, clki->max_freq);
7778 if (ret) {
7779 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7780 __func__, clki->name,
7781 clki->max_freq, ret);
7782 goto out;
7783 }
856b3483 7784 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7785 }
7786 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7787 clki->name, clk_get_rate(clki->clk));
7788 }
7789out:
7790 return ret;
7791}
7792
5c0c28a8
SRT		 7793static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7794{
7795 int err = 0;
7796
7797 if (!hba->vops)
7798 goto out;
7799
0263bcd0
YG		 7800 err = ufshcd_vops_init(hba);
7801 if (err)
7802 goto out;
5c0c28a8 7803
0263bcd0
YG		 7804 err = ufshcd_vops_setup_regulators(hba, true);
7805 if (err)
7806 goto out_exit;
5c0c28a8
SRT		 7807
7808 goto out;
7809
5c0c28a8 7810out_exit:
0263bcd0 7811 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7812out:
7813 if (err)
7814 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7815 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7816 return err;
7817}
7818
7819static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7820{
7821 if (!hba->vops)
7822 return;
7823
0263bcd0 7824 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7825
0263bcd0 7826 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7827}
7828
aa497613
SRT		 7829static int ufshcd_hba_init(struct ufs_hba *hba)
7830{
7831 int err;
7832
6a771a65
RS		 7833 /*
7834 * Handle host controller power separately from the UFS device power
7835 * rails as it will help controlling the UFS host controller power
7836 * collapse easily which is different than UFS device power collapse.
7837 * Also, enable the host controller power before we go ahead with rest
7838 * of the initialization here.
7839 */
7840 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7841 if (err)
7842 goto out;
7843
6a771a65 7844 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7845 if (err)
7846 goto out;
7847
6a771a65
RS		 7848 err = ufshcd_init_clocks(hba);
7849 if (err)
7850 goto out_disable_hba_vreg;
7851
7852 err = ufshcd_setup_clocks(hba, true);
7853 if (err)
7854 goto out_disable_hba_vreg;
7855
c6e79dac
SRT		 7856 err = ufshcd_init_vreg(hba);
7857 if (err)
7858 goto out_disable_clks;
7859
7860 err = ufshcd_setup_vreg(hba, true);
7861 if (err)
7862 goto out_disable_clks;
7863
aa497613
SRT		 7864 err = ufshcd_variant_hba_init(hba);
7865 if (err)
7866 goto out_disable_vreg;
7867
1d337ec2 7868 hba->is_powered = true;
aa497613
SRT		 7869 goto out;
7870
7871out_disable_vreg:
7872 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7873out_disable_clks:
7874 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7875out_disable_hba_vreg:
7876 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7877out:
7878 return err;
7879}
7880
7881static void ufshcd_hba_exit(struct ufs_hba *hba)
7882{
1d337ec2
SRT		 7883 if (hba->is_powered) {
7884 ufshcd_variant_hba_exit(hba);
7885 ufshcd_setup_vreg(hba, false);
a508253d 7886 ufshcd_suspend_clkscaling(hba);
eebcc196 7887 if (ufshcd_is_clkscaling_supported(hba))
0701e49d 7888 if (hba->devfreq)
7889 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7890 ufshcd_setup_clocks(hba, false);
7891 ufshcd_setup_hba_vreg(hba, false);
7892 hba->is_powered = false;
09750066 7893 ufs_put_device_desc(hba);
1d337ec2 7894 }
aa497613
SRT		 7895}
7896
57d104c1
SJ		 7897static int
7898ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7899{
7900 unsigned char cmd[6] = {REQUEST_SENSE,
7901 0,
7902 0,
7903 0,
09a5a24f 7904 UFS_SENSE_SIZE,
57d104c1
SJ		 7905 0};
7906 char *buffer;
7907 int ret;
7908
09a5a24f 7909 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7910 if (!buffer) {
7911 ret = -ENOMEM;
7912 goto out;
7913 }
7914
fcbfffe2 7915 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
09a5a24f 7916 UFS_SENSE_SIZE, NULL, NULL,
fcbfffe2 7917 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7918 if (ret)
7919 pr_err("%s: failed with err %d\n", __func__, ret);
7920
7921 kfree(buffer);
7922out:
7923 return ret;
7924}
7925
7926/**
7927 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7928 * power mode
7929 * @hba: per adapter instance
7930 * @pwr_mode: device power mode to set
7931 *
7932 * Returns 0 if requested power mode is set successfully
7933 * Returns non-zero if failed to set the requested power mode
7934 */
7935static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7936 enum ufs_dev_pwr_mode pwr_mode)
7937{
7938 unsigned char cmd[6] = { START_STOP };
7939 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7940 struct scsi_device *sdp;
7941 unsigned long flags;
57d104c1
SJ		 7942 int ret;
7943
7c48bfd0
AM		 7944 spin_lock_irqsave(hba->host->host_lock, flags);
7945 sdp = hba->sdev_ufs_device;
7946 if (sdp) {
7947 ret = scsi_device_get(sdp);
7948 if (!ret && !scsi_device_online(sdp)) {
7949 ret = -ENODEV;
7950 scsi_device_put(sdp);
7951 }
7952 } else {
7953 ret = -ENODEV;
7954 }
7955 spin_unlock_irqrestore(hba->host->host_lock, flags);
7956
7957 if (ret)
7958 return ret;
57d104c1
SJ		 7959
7960 /*
7961 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7962 * handling, which would wait for host to be resumed. Since we know
7963 * we are functional while we are here, skip host resume in error
7964 * handling context.
7965 */
7966 hba->host->eh_noresume = 1;
7967 if (hba->wlun_dev_clr_ua) {
7968 ret = ufshcd_send_request_sense(hba, sdp);
7969 if (ret)
7970 goto out;
7971 /* Unit attention condition is cleared now */
7972 hba->wlun_dev_clr_ua = false;
7973 }
7974
7975 cmd[4] = pwr_mode << 4;
7976
7977 /*
7978 * Current function would be generally called from the power management
e8064021 7979 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7980 * already suspended childs.
7981 */
fcbfffe2
CH		 7982 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7983 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7984 if (ret) {
7985 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7986 "START_STOP failed for power mode: %d, result %x\n",
7987 pwr_mode, ret);
c65be1a6 7988 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7989 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7990 }
7991
7992 if (!ret)
7993 hba->curr_dev_pwr_mode = pwr_mode;
7994out:
7c48bfd0 7995 scsi_device_put(sdp);
57d104c1
SJ		 7996 hba->host->eh_noresume = 0;
7997 return ret;
7998}
7999
8000static int ufshcd_link_state_transition(struct ufs_hba *hba,
8001 enum uic_link_state req_link_state,
8002 int check_for_bkops)
8003{
8004 int ret = 0;
8005
8006 if (req_link_state == hba->uic_link_state)
8007 return 0;
8008
8009 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8010 ret = ufshcd_uic_hibern8_enter(hba);
8011 if (!ret)
8012 ufshcd_set_link_hibern8(hba);
8013 else
8014 goto out;
8015 }
8016 /*
8017 * If autobkops is enabled, link can't be turned off because
8018 * turning off the link would also turn off the device.
8019 */
8020 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 8021 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 8022 /*
8023 * Let's make sure that link is in low power mode, we are doing
8024 * this currently by putting the link in Hibern8. Otherway to
8025 * put the link in low power mode is to send the DME end point
8026 * to device and then send the DME reset command to local
8027 * unipro. But putting the link in hibern8 is much faster.
8028 */
8029 ret = ufshcd_uic_hibern8_enter(hba);
8030 if (ret)
8031 goto out;
57d104c1
SJ		 8032 /*
8033 * Change controller state to "reset state" which
8034 * should also put the link in off/reset state
8035 */
5cac1095 8036 ufshcd_hba_stop(hba);
57d104c1
SJ		 8037 /*
8038 * TODO: Check if we need any delay to make sure that
8039 * controller is reset
8040 */
8041 ufshcd_set_link_off(hba);
8042 }
8043
8044out:
8045 return ret;
8046}
8047
8048static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8049{
b799fdf7
YG		 8050 /*
8051 * It seems some UFS devices may keep drawing more than sleep current
8052 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8053 * To avoid this situation, add 2ms delay before putting these UFS
8054 * rails in LPM mode.
8055 */
8056 if (!ufshcd_is_link_active(hba) &&
8057 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8058 usleep_range(2000, 2100);
8059
57d104c1
SJ		 8060 /*
8061 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8062 * power.
8063 *
8064 * If UFS device and link is in OFF state, all power supplies (VCC,
8065 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8066 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8067 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8068 *
8069 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8070 * in low power state which would save some power.
3d17b9b5
AD		 8071 *
8072 * If Write Booster is enabled and the device needs to flush the WB
8073 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 8074 */
8075 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8076 !hba->dev_info.is_lu_power_on_wp) {
8077 ufshcd_setup_vreg(hba, false);
8078 } else if (!ufshcd_is_ufs_dev_active(hba)) {
51dd905b 8079 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
57d104c1
SJ		 8080 if (!ufshcd_is_link_active(hba)) {
8081 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8082 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8083 }
8084 }
8085}
8086
8087static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8088{
8089 int ret = 0;
8090
8091 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8092 !hba->dev_info.is_lu_power_on_wp) {
8093 ret = ufshcd_setup_vreg(hba, true);
8094 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 8095 if (!ret && !ufshcd_is_link_active(hba)) {
8096 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8097 if (ret)
8098 goto vcc_disable;
8099 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8100 if (ret)
8101 goto vccq_lpm;
8102 }
69d72ac8 8103 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 8104 }
8105 goto out;
8106
8107vccq_lpm:
8108 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8109vcc_disable:
8110 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8111out:
8112 return ret;
8113}
8114
8115static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8116{
8117 if (ufshcd_is_link_off(hba))
8118 ufshcd_setup_hba_vreg(hba, false);
8119}
8120
8121static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8122{
8123 if (ufshcd_is_link_off(hba))
8124 ufshcd_setup_hba_vreg(hba, true);
8125}
8126
7a3e97b0 8127/**
57d104c1 8128 * ufshcd_suspend - helper function for suspend operations
3b1d0580 8129 * @hba: per adapter instance
57d104c1
SJ		 8130 * @pm_op: desired low power operation type
8131 *
8132 * This function will try to put the UFS device and link into low power
8133 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
8134 * (System PM level).
8135 *
8136 * If this function is called during shutdown, it will make sure that
8137 * both UFS device and UFS link is powered off.
7a3e97b0 8138 *
57d104c1
SJ		 8139 * NOTE: UFS device & link must be active before we enter in this function.
8140 *
8141 * Returns 0 for success and non-zero for failure
7a3e97b0 8142 */
57d104c1 8143static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8144{
57d104c1
SJ		 8145 int ret = 0;
8146 enum ufs_pm_level pm_lvl;
8147 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8148 enum uic_link_state req_link_state;
8149
8150 hba->pm_op_in_progress = 1;
8151 if (!ufshcd_is_shutdown_pm(pm_op)) {
8152 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
8153 hba->rpm_lvl : hba->spm_lvl;
8154 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8155 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8156 } else {
8157 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8158 req_link_state = UIC_LINK_OFF_STATE;
8159 }
8160
7a3e97b0 8161 /*
57d104c1
SJ		 8162 * If we can't transition into any of the low power modes
8163 * just gate the clocks.
7a3e97b0 8164 */
1ab27c9c
ST		 8165 ufshcd_hold(hba, false);
8166 hba->clk_gating.is_suspended = true;
8167
401f1e44 8168 if (hba->clk_scaling.is_allowed) {
8169 cancel_work_sync(&hba->clk_scaling.suspend_work);
8170 cancel_work_sync(&hba->clk_scaling.resume_work);
8171 ufshcd_suspend_clkscaling(hba);
8172 }
d6fcf81a 8173
57d104c1
SJ		 8174 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8175 req_link_state == UIC_LINK_ACTIVE_STATE) {
8176 goto disable_clks;
8177 }
7a3e97b0 8178
57d104c1
SJ		 8179 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8180 (req_link_state == hba->uic_link_state))
d6fcf81a 8181 goto enable_gating;
57d104c1
SJ		 8182
8183 /* UFS device & link must be active before we enter in this function */
8184 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8185 ret = -EINVAL;
d6fcf81a 8186 goto enable_gating;
57d104c1
SJ		 8187 }
8188
8189 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 8190 if (ufshcd_can_autobkops_during_suspend(hba)) {
8191 /*
8192 * The device is idle with no requests in the queue,
8193 * allow background operations if bkops status shows
8194 * that performance might be impacted.
8195 */
8196 ret = ufshcd_urgent_bkops(hba);
8197 if (ret)
8198 goto enable_gating;
8199 } else {
8200 /* make sure that auto bkops is disabled */
8201 ufshcd_disable_auto_bkops(hba);
8202 }
3d17b9b5 8203 /*
51dd905b
SC		 8204 * If device needs to do BKOP or WB buffer flush during
8205 * Hibern8, keep device power mode as "active power mode"
8206 * and VCC supply.
3d17b9b5 8207 */
51dd905b
SC		 8208 hba->dev_info.b_rpm_dev_flush_capable =
8209 hba->auto_bkops_enabled ||
8210 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8211 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8212 ufshcd_is_auto_hibern8_enabled(hba))) &&
8213 ufshcd_wb_need_flush(hba));
8214 }
8215
8216 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8217 if ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
8218 !ufshcd_is_runtime_pm(pm_op)) {
8219 /* ensure that bkops is disabled */
8220 ufshcd_disable_auto_bkops(hba);
8221 }
57d104c1 8222
51dd905b
SC		 8223 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8224 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8225 if (ret)
8226 goto enable_gating;
8227 }
57d104c1
SJ		 8228 }
8229
2824ec9f 8230 flush_work(&hba->eeh_work);
57d104c1
SJ		 8231 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
8232 if (ret)
8233 goto set_dev_active;
8234
8235 ufshcd_vreg_set_lpm(hba);
8236
8237disable_clks:
8238 /*
8239 * Call vendor specific suspend callback. As these callbacks may access
8240 * vendor specific host controller register space call them before the
8241 * host clocks are ON.
8242 */
0263bcd0
YG		 8243 ret = ufshcd_vops_suspend(hba, pm_op);
8244 if (ret)
8245 goto set_link_active;
dcb6cec5
SC		 8246 /*
8247 * Disable the host irq as host controller as there won't be any
8248 * host controller transaction expected till resume.
8249 */
8250 ufshcd_disable_irq(hba);
57d104c1 8251
57d104c1
SJ		 8252 if (!ufshcd_is_link_active(hba))
8253 ufshcd_setup_clocks(hba, false);
8254 else
8255 /* If link is active, device ref_clk can't be switched off */
8256 __ufshcd_setup_clocks(hba, false, true);
8257
1ab27c9c 8258 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 8259 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
dcb6cec5 8260
57d104c1
SJ		 8261 /* Put the host controller in low power mode if possible */
8262 ufshcd_hba_vreg_set_lpm(hba);
8263 goto out;
8264
57d104c1 8265set_link_active:
401f1e44 8266 if (hba->clk_scaling.is_allowed)
8267 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 8268 ufshcd_vreg_set_hpm(hba);
8269 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8270 ufshcd_set_link_active(hba);
8271 else if (ufshcd_is_link_off(hba))
8272 ufshcd_host_reset_and_restore(hba);
8273set_dev_active:
8274 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8275 ufshcd_disable_auto_bkops(hba);
1ab27c9c 8276enable_gating:
401f1e44 8277 if (hba->clk_scaling.is_allowed)
8278 ufshcd_resume_clkscaling(hba);
1ab27c9c 8279 hba->clk_gating.is_suspended = false;
51dd905b 8280 hba->dev_info.b_rpm_dev_flush_capable = false;
1ab27c9c 8281 ufshcd_release(hba);
57d104c1 8282out:
51dd905b
SC		 8283 if (hba->dev_info.b_rpm_dev_flush_capable) {
8284 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8285 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8286 }
8287
57d104c1 8288 hba->pm_op_in_progress = 0;
51dd905b 8289
8808b4e9
SC		 8290 if (ret)
8291 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
57d104c1 8292 return ret;
7a3e97b0
SY		 8293}
8294
8295/**
57d104c1 8296 * ufshcd_resume - helper function for resume operations
3b1d0580 8297 * @hba: per adapter instance
57d104c1 8298 * @pm_op: runtime PM or system PM
7a3e97b0 8299 *
57d104c1
SJ		 8300 * This function basically brings the UFS device, UniPro link and controller
8301 * to active state.
8302 *
8303 * Returns 0 for success and non-zero for failure
7a3e97b0 8304 */
57d104c1 8305static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8306{
57d104c1
SJ		 8307 int ret;
8308 enum uic_link_state old_link_state;
8309
8310 hba->pm_op_in_progress = 1;
8311 old_link_state = hba->uic_link_state;
8312
8313 ufshcd_hba_vreg_set_hpm(hba);
8314 /* Make sure clocks are enabled before accessing controller */
8315 ret = ufshcd_setup_clocks(hba, true);
8316 if (ret)
8317 goto out;
8318
57d104c1 8319 /* enable the host irq as host controller would be active soon */
5231d38c 8320 ufshcd_enable_irq(hba);
57d104c1
SJ		 8321
8322 ret = ufshcd_vreg_set_hpm(hba);
8323 if (ret)
8324 goto disable_irq_and_vops_clks;
8325
7a3e97b0 8326 /*
57d104c1
SJ		 8327 * Call vendor specific resume callback. As these callbacks may access
8328 * vendor specific host controller register space call them when the
8329 * host clocks are ON.
7a3e97b0 8330 */
0263bcd0
YG		 8331 ret = ufshcd_vops_resume(hba, pm_op);
8332 if (ret)
8333 goto disable_vreg;
57d104c1
SJ		 8334
8335 if (ufshcd_is_link_hibern8(hba)) {
8336 ret = ufshcd_uic_hibern8_exit(hba);
8337 if (!ret)
8338 ufshcd_set_link_active(hba);
8339 else
8340 goto vendor_suspend;
8341 } else if (ufshcd_is_link_off(hba)) {
57d104c1 8342 /*
089f5b64
AD		 8343 * A full initialization of the host and the device is
8344 * required since the link was put to off during suspend.
8345 */
8346 ret = ufshcd_reset_and_restore(hba);
8347 /*
8348 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 8349 * set the link state as active
8350 */
8351 if (ret || !ufshcd_is_link_active(hba))
8352 goto vendor_suspend;
8353 }
8354
8355 if (!ufshcd_is_ufs_dev_active(hba)) {
8356 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8357 if (ret)
8358 goto set_old_link_state;
8359 }
8360
4e768e76 8361 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8362 ufshcd_enable_auto_bkops(hba);
8363 else
8364 /*
8365 * If BKOPs operations are urgently needed at this moment then
8366 * keep auto-bkops enabled or else disable it.
8367 */
8368 ufshcd_urgent_bkops(hba);
8369
1ab27c9c
ST		 8370 hba->clk_gating.is_suspended = false;
8371
fcb0c4b0
ST		 8372 if (hba->clk_scaling.is_allowed)
8373 ufshcd_resume_clkscaling(hba);
856b3483 8374
ad448378
AH		 8375 /* Enable Auto-Hibernate if configured */
8376 ufshcd_auto_hibern8_enable(hba);
8377
51dd905b
SC		 8378 if (hba->dev_info.b_rpm_dev_flush_capable) {
8379 hba->dev_info.b_rpm_dev_flush_capable = false;
8380 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
8381 }
8382
71d848b8
CG		 8383 /* Schedule clock gating in case of no access to UFS device yet */
8384 ufshcd_release(hba);
8385
57d104c1
SJ		 8386 goto out;
8387
8388set_old_link_state:
8389 ufshcd_link_state_transition(hba, old_link_state, 0);
8390vendor_suspend:
0263bcd0 8391 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 8392disable_vreg:
8393 ufshcd_vreg_set_lpm(hba);
8394disable_irq_and_vops_clks:
8395 ufshcd_disable_irq(hba);
401f1e44 8396 if (hba->clk_scaling.is_allowed)
8397 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 8398 ufshcd_setup_clocks(hba, false);
8399out:
8400 hba->pm_op_in_progress = 0;
8808b4e9
SC		 8401 if (ret)
8402 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
57d104c1
SJ		 8403 return ret;
8404}
8405
8406/**
8407 * ufshcd_system_suspend - system suspend routine
8408 * @hba: per adapter instance
57d104c1
SJ		 8409 *
8410 * Check the description of ufshcd_suspend() function for more details.
8411 *
8412 * Returns 0 for success and non-zero for failure
8413 */
8414int ufshcd_system_suspend(struct ufs_hba *hba)
8415{
8416 int ret = 0;
7ff5ab47 8417 ktime_t start = ktime_get();
57d104c1
SJ		 8418
8419 if (!hba || !hba->is_powered)
233b594b 8420 return 0;
57d104c1 8421
0b257734 8422 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8423 hba->curr_dev_pwr_mode) &&
8424 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8425 hba->uic_link_state))
8426 goto out;
57d104c1 8427
0b257734 8428 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 8429 /*
8430 * UFS device and/or UFS link low power states during runtime
8431 * suspend seems to be different than what is expected during
8432 * system suspend. Hence runtime resume the devic & link and
8433 * let the system suspend low power states to take effect.
8434 * TODO: If resume takes longer time, we might have optimize
8435 * it in future by not resuming everything if possible.
8436 */
8437 ret = ufshcd_runtime_resume(hba);
8438 if (ret)
8439 goto out;
8440 }
8441
8442 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8443out:
7ff5ab47 8444 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8445 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8446 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 8447 if (!ret)
8448 hba->is_sys_suspended = true;
57d104c1
SJ		 8449 return ret;
8450}
8451EXPORT_SYMBOL(ufshcd_system_suspend);
8452
8453/**
8454 * ufshcd_system_resume - system resume routine
8455 * @hba: per adapter instance
8456 *
8457 * Returns 0 for success and non-zero for failure
8458 */
7a3e97b0 8459
57d104c1
SJ		 8460int ufshcd_system_resume(struct ufs_hba *hba)
8461{
7ff5ab47 8462 int ret = 0;
8463 ktime_t start = ktime_get();
8464
e3ce73d6
YG		 8465 if (!hba)
8466 return -EINVAL;
8467
8468 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 8469 /*
8470 * Let the runtime resume take care of resuming
8471 * if runtime suspended.
8472 */
7ff5ab47 8473 goto out;
8474 else
8475 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8476out:
8477 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8478 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8479 hba->curr_dev_pwr_mode, hba->uic_link_state);
ce9e7bce
SC		 8480 if (!ret)
8481 hba->is_sys_suspended = false;
7ff5ab47 8482 return ret;
7a3e97b0 8483}
57d104c1 8484EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 8485
57d104c1
SJ		 8486/**
8487 * ufshcd_runtime_suspend - runtime suspend routine
8488 * @hba: per adapter instance
8489 *
8490 * Check the description of ufshcd_suspend() function for more details.
8491 *
8492 * Returns 0 for success and non-zero for failure
8493 */
66ec6d59
SRT		 8494int ufshcd_runtime_suspend(struct ufs_hba *hba)
8495{
7ff5ab47 8496 int ret = 0;
8497 ktime_t start = ktime_get();
8498
e3ce73d6
YG		 8499 if (!hba)
8500 return -EINVAL;
8501
8502 if (!hba->is_powered)
7ff5ab47 8503 goto out;
8504 else
8505 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8506out:
8507 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8508 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8509 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8510 return ret;
66ec6d59
SRT		 8511}
8512EXPORT_SYMBOL(ufshcd_runtime_suspend);
8513
57d104c1
SJ		 8514/**
8515 * ufshcd_runtime_resume - runtime resume routine
8516 * @hba: per adapter instance
8517 *
8518 * This function basically brings the UFS device, UniPro link and controller
8519 * to active state. Following operations are done in this function:
8520 *
8521 * 1. Turn on all the controller related clocks
8522 * 2. Bring the UniPro link out of Hibernate state
8523 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8524 * to active state.
8525 * 4. If auto-bkops is enabled on the device, disable it.
8526 *
8527 * So following would be the possible power state after this function return
8528 * successfully:
8529 * S1: UFS device in Active state with VCC rail ON
8530 * UniPro link in Active state
8531 * All the UFS/UniPro controller clocks are ON
8532 *
8533 * Returns 0 for success and non-zero for failure
8534 */
66ec6d59
SRT		 8535int ufshcd_runtime_resume(struct ufs_hba *hba)
8536{
7ff5ab47 8537 int ret = 0;
8538 ktime_t start = ktime_get();
8539
e3ce73d6
YG		 8540 if (!hba)
8541 return -EINVAL;
8542
8543 if (!hba->is_powered)
7ff5ab47 8544 goto out;
8545 else
8546 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8547out:
8548 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8549 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8550 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8551 return ret;
66ec6d59
SRT		 8552}
8553EXPORT_SYMBOL(ufshcd_runtime_resume);
8554
8555int ufshcd_runtime_idle(struct ufs_hba *hba)
8556{
8557 return 0;
8558}
8559EXPORT_SYMBOL(ufshcd_runtime_idle);
8560
57d104c1
SJ		 8561/**
8562 * ufshcd_shutdown - shutdown routine
8563 * @hba: per adapter instance
8564 *
8565 * This function would power off both UFS device and UFS link.
8566 *
8567 * Returns 0 always to allow force shutdown even in case of errors.
8568 */
8569int ufshcd_shutdown(struct ufs_hba *hba)
8570{
8571 int ret = 0;
8572
f51913ee
SC		 8573 if (!hba->is_powered)
8574 goto out;
8575
57d104c1
SJ		 8576 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8577 goto out;
8578
8579 if (pm_runtime_suspended(hba->dev)) {
8580 ret = ufshcd_runtime_resume(hba);
8581 if (ret)
8582 goto out;
8583 }
8584
8585 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8586out:
8587 if (ret)
8588 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8589 /* allow force shutdown even in case of errors */
8590 return 0;
8591}
8592EXPORT_SYMBOL(ufshcd_shutdown);
8593
7a3e97b0 8594/**
3b1d0580 8595 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8596 * data structure memory
8aa29f19 8597 * @hba: per adapter instance
7a3e97b0 8598 */
3b1d0580 8599void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8600{
df032bf2 8601 ufs_bsg_remove(hba);
cbb6813e 8602 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 8603 blk_cleanup_queue(hba->tmf_queue);
8604 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360 8605 blk_cleanup_queue(hba->cmd_queue);
cfdf9c91 8606 scsi_remove_host(hba->host);
7a3e97b0 8607 /* disable interrupts */
2fbd009b 8608 ufshcd_disable_intr(hba, hba->intr_mask);
5cac1095 8609 ufshcd_hba_stop(hba);
7a3e97b0 8610
eebcc196 8611 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8612 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8613 if (ufshcd_is_clkscaling_supported(hba))
8614 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8615 ufshcd_hba_exit(hba);
3b1d0580
VH		 8616}
8617EXPORT_SYMBOL_GPL(ufshcd_remove);
8618
47555a5c
YG		 8619/**
8620 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8621 * @hba: pointer to Host Bus Adapter (HBA)
8622 */
8623void ufshcd_dealloc_host(struct ufs_hba *hba)
8624{
8625 scsi_host_put(hba->host);
8626}
8627EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8628
ca3d7bf9
AM		 8629/**
8630 * ufshcd_set_dma_mask - Set dma mask based on the controller
8631 * addressing capability
8632 * @hba: per adapter instance
8633 *
8634 * Returns 0 for success, non-zero for failure
8635 */
8636static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8637{
8638 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8639 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8640 return 0;
8641 }
8642 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8643}
8644
7a3e97b0 8645/**
5c0c28a8 8646 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8647 * @dev: pointer to device handle
8648 * @hba_handle: driver private handle
7a3e97b0
SY		 8649 * Returns 0 on success, non-zero value on failure
8650 */
5c0c28a8 8651int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8652{
8653 struct Scsi_Host *host;
8654 struct ufs_hba *hba;
5c0c28a8 8655 int err = 0;
7a3e97b0 8656
3b1d0580
VH		 8657 if (!dev) {
8658 dev_err(dev,
8659 "Invalid memory reference for dev is NULL\n");
8660 err = -ENODEV;
7a3e97b0
SY		 8661 goto out_error;
8662 }
8663
7a3e97b0
SY		 8664 host = scsi_host_alloc(&ufshcd_driver_template,
8665 sizeof(struct ufs_hba));
8666 if (!host) {
3b1d0580 8667 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8668 err = -ENOMEM;
3b1d0580 8669 goto out_error;
7a3e97b0
SY		 8670 }
8671 hba = shost_priv(host);
7a3e97b0 8672 hba->host = host;
3b1d0580 8673 hba->dev = dev;
5c0c28a8 8674 *hba_handle = hba;
9e1e8a75 8675 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
5c0c28a8 8676
566ec9ad
SM		 8677 INIT_LIST_HEAD(&hba->clk_list_head);
8678
5c0c28a8
SRT		 8679out_error:
8680 return err;
8681}
8682EXPORT_SYMBOL(ufshcd_alloc_host);
8683
69a6c269
BVA		 8684/* This function exists because blk_mq_alloc_tag_set() requires this. */
8685static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
8686 const struct blk_mq_queue_data *qd)
8687{
8688 WARN_ON_ONCE(true);
8689 return BLK_STS_NOTSUPP;
8690}
8691
8692static const struct blk_mq_ops ufshcd_tmf_ops = {
8693 .queue_rq = ufshcd_queue_tmf,
8694};
8695
5c0c28a8
SRT		 8696/**
8697 * ufshcd_init - Driver initialization routine
8698 * @hba: per-adapter instance
8699 * @mmio_base: base register address
8700 * @irq: Interrupt line of device
8701 * Returns 0 on success, non-zero value on failure
8702 */
8703int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8704{
8705 int err;
8706 struct Scsi_Host *host = hba->host;
8707 struct device *dev = hba->dev;
8708
8709 if (!mmio_base) {
8710 dev_err(hba->dev,
8711 "Invalid memory reference for mmio_base is NULL\n");
8712 err = -ENODEV;
8713 goto out_error;
8714 }
8715
3b1d0580
VH		 8716 hba->mmio_base = mmio_base;
8717 hba->irq = irq;
90b8491c 8718 hba->vps = &ufs_hba_vps;
7a3e97b0 8719
aa497613 8720 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8721 if (err)
8722 goto out_error;
8723
7a3e97b0
SY		 8724 /* Read capabilities registers */
8725 ufshcd_hba_capabilities(hba);
8726
8727 /* Get UFS version supported by the controller */
8728 hba->ufs_version = ufshcd_get_ufs_version(hba);
8729
c01848c6
YG		 8730 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8731 (hba->ufs_version != UFSHCI_VERSION_11) &&
8732 (hba->ufs_version != UFSHCI_VERSION_20) &&
8733 (hba->ufs_version != UFSHCI_VERSION_21))
8734 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8735 hba->ufs_version);
8736
2fbd009b
SJ		 8737 /* Get Interrupt bit mask per version */
8738 hba->intr_mask = ufshcd_get_intr_mask(hba);
8739
ca3d7bf9
AM		 8740 err = ufshcd_set_dma_mask(hba);
8741 if (err) {
8742 dev_err(hba->dev, "set dma mask failed\n");
8743 goto out_disable;
8744 }
8745
7a3e97b0
SY		 8746 /* Allocate memory for host memory space */
8747 err = ufshcd_memory_alloc(hba);
8748 if (err) {
3b1d0580
VH		 8749 dev_err(hba->dev, "Memory allocation failed\n");
8750 goto out_disable;
7a3e97b0
SY		 8751 }
8752
8753 /* Configure LRB */
8754 ufshcd_host_memory_configure(hba);
8755
8756 host->can_queue = hba->nutrs;
8757 host->cmd_per_lun = hba->nutrs;
8758 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8759 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8760 host->max_channel = UFSHCD_MAX_CHANNEL;
8761 host->unique_id = host->host_no;
a851b2bd 8762 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8763
7eb584db
DR		 8764 hba->max_pwr_info.is_valid = false;
8765
7a3e97b0 8766 /* Initialize work queues */
e8e7f271 8767 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8768 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8769
6ccf44fe
SJ		 8770 /* Initialize UIC command mutex */
8771 mutex_init(&hba->uic_cmd_mutex);
8772
5a0b0cb9
SRT		 8773 /* Initialize mutex for device management commands */
8774 mutex_init(&hba->dev_cmd.lock);
8775
a3cd5ec5 8776 init_rwsem(&hba->clk_scaling_lock);
8777
1ab27c9c 8778 ufshcd_init_clk_gating(hba);
199ef13c 8779
eebcc196
VG		 8780 ufshcd_init_clk_scaling(hba);
8781
199ef13c
YG		 8782 /*
8783 * In order to avoid any spurious interrupt immediately after
8784 * registering UFS controller interrupt handler, clear any pending UFS
8785 * interrupt status and disable all the UFS interrupts.
8786 */
8787 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8788 REG_INTERRUPT_STATUS);
8789 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8790 /*
8791 * Make sure that UFS interrupts are disabled and any pending interrupt
8792 * status is cleared before registering UFS interrupt handler.
8793 */
8794 mb();
8795
7a3e97b0 8796 /* IRQ registration */
2953f850 8797 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8798 if (err) {
3b1d0580 8799 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8800 goto exit_gating;
57d104c1
SJ		 8801 } else {
8802 hba->is_irq_enabled = true;
7a3e97b0
SY		 8803 }
8804
3b1d0580 8805 err = scsi_add_host(host, hba->dev);
7a3e97b0 8806 if (err) {
3b1d0580 8807 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8808 goto exit_gating;
7a3e97b0
SY		 8809 }
8810
7252a360
BVA		 8811 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
8812 if (IS_ERR(hba->cmd_queue)) {
8813 err = PTR_ERR(hba->cmd_queue);
8814 goto out_remove_scsi_host;
8815 }
8816
69a6c269
BVA		 8817 hba->tmf_tag_set = (struct blk_mq_tag_set) {
8818 .nr_hw_queues = 1,
8819 .queue_depth = hba->nutmrs,
8820 .ops = &ufshcd_tmf_ops,
8821 .flags = BLK_MQ_F_NO_SCHED,
8822 };
8823 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
8824 if (err < 0)
8825 goto free_cmd_queue;
8826 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
8827 if (IS_ERR(hba->tmf_queue)) {
8828 err = PTR_ERR(hba->tmf_queue);
8829 goto free_tmf_tag_set;
8830 }
8831
d8d9f793
BA		 8832 /* Reset the attached device */
8833 ufshcd_vops_device_reset(hba);
8834
6ccf44fe
SJ		 8835 /* Host controller enable */
8836 err = ufshcd_hba_enable(hba);
7a3e97b0 8837 if (err) {
6ccf44fe 8838 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8839 ufshcd_print_host_regs(hba);
6ba65588 8840 ufshcd_print_host_state(hba);
69a6c269 8841 goto free_tmf_queue;
7a3e97b0 8842 }
6ccf44fe 8843
0c8f7586 8844 /*
8845 * Set the default power management level for runtime and system PM.
8846 * Default power saving mode is to keep UFS link in Hibern8 state
8847 * and UFS device in sleep state.
8848 */
8849 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8850 UFS_SLEEP_PWR_MODE,
8851 UIC_LINK_HIBERN8_STATE);
8852 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8853 UFS_SLEEP_PWR_MODE,
8854 UIC_LINK_HIBERN8_STATE);
8855
51dd905b
SC		 8856 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
8857 ufshcd_rpm_dev_flush_recheck_work);
8858
ad448378 8859 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 8860 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 8861 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8862 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8863 }
8864
62694735
SRT		 8865 /* Hold auto suspend until async scan completes */
8866 pm_runtime_get_sync(dev);
38135535 8867 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8868 /*
7caf489b 8869 * We are assuming that device wasn't put in sleep/power-down
8870 * state exclusively during the boot stage before kernel.
8871 * This assumption helps avoid doing link startup twice during
8872 * ufshcd_probe_hba().
57d104c1 8873 */
7caf489b 8874 ufshcd_set_ufs_dev_active(hba);
57d104c1 8875
6ccf44fe 8876 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8877 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8878
7a3e97b0
SY		 8879 return 0;
8880
69a6c269
BVA		 8881free_tmf_queue:
8882 blk_cleanup_queue(hba->tmf_queue);
8883free_tmf_tag_set:
8884 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360
BVA		 8885free_cmd_queue:
8886 blk_cleanup_queue(hba->cmd_queue);
3b1d0580
VH		 8887out_remove_scsi_host:
8888 scsi_remove_host(hba->host);
1ab27c9c 8889exit_gating:
eebcc196 8890 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8891 ufshcd_exit_clk_gating(hba);
3b1d0580 8892out_disable:
57d104c1 8893 hba->is_irq_enabled = false;
aa497613 8894 ufshcd_hba_exit(hba);
3b1d0580
VH		 8895out_error:
8896 return err;
8897}
8898EXPORT_SYMBOL_GPL(ufshcd_init);
8899
3b1d0580
VH		 8900MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8901MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8902MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8903MODULE_LICENSE("GPL");
8904MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)