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scsi: ufs: issue link starup 2 times if device isn't active
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
dcea0bfb
GB		 48#define UFSHCD_REQ_SENSE_SIZE 18
49
2fbd009b
SJ		 50#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
51 UTP_TASK_REQ_COMPL |\
52 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 53/* UIC command timeout, unit: ms */
54#define UIC_CMD_TIMEOUT 500
2fbd009b 55
5a0b0cb9
SRT		 56/* NOP OUT retries waiting for NOP IN response */
57#define NOP_OUT_RETRIES 10
58/* Timeout after 30 msecs if NOP OUT hangs without response */
59#define NOP_OUT_TIMEOUT 30 /* msecs */
60
68078d5c 61/* Query request retries */
10fe5888 62#define QUERY_REQ_RETRIES 3
68078d5c 63/* Query request timeout */
10fe5888 64#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 65
e2933132
SRT		 66/* Task management command timeout */
67#define TM_CMD_TIMEOUT 100 /* msecs */
68
64238fbd
YG		 69/* maximum number of retries for a general UIC command */
70#define UFS_UIC_COMMAND_RETRIES 3
71
1d337ec2
SRT		 72/* maximum number of link-startup retries */
73#define DME_LINKSTARTUP_RETRIES 3
74
87d0b4a6
YG		 75/* Maximum retries for Hibern8 enter */
76#define UIC_HIBERN8_ENTER_RETRIES 3
77
1d337ec2
SRT		 78/* maximum number of reset retries before giving up */
79#define MAX_HOST_RESET_RETRIES 5
80
68078d5c
DR		 81/* Expose the flag value from utp_upiu_query.value */
82#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
83
7d568652
SJ		 84/* Interrupt aggregation default timeout, unit: 40us */
85#define INT_AGGR_DEF_TO 0x02
86
aa497613
SRT		 87#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
88 ({ \
89 int _ret; \
90 if (_on) \
91 _ret = ufshcd_enable_vreg(_dev, _vreg); \
92 else \
93 _ret = ufshcd_disable_vreg(_dev, _vreg); \
94 _ret; \
95 })
96
da461cec
SJ		 97static u32 ufs_query_desc_max_size[] = {
98 QUERY_DESC_DEVICE_MAX_SIZE,
99 QUERY_DESC_CONFIGURAION_MAX_SIZE,
100 QUERY_DESC_UNIT_MAX_SIZE,
101 QUERY_DESC_RFU_MAX_SIZE,
102 QUERY_DESC_INTERCONNECT_MAX_SIZE,
103 QUERY_DESC_STRING_MAX_SIZE,
104 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 105 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 106 QUERY_DESC_POWER_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108};
109
7a3e97b0
SY		 110enum {
111 UFSHCD_MAX_CHANNEL = 0,
112 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 113 UFSHCD_CMD_PER_LUN = 32,
114 UFSHCD_CAN_QUEUE = 32,
115};
116
117/* UFSHCD states */
118enum {
7a3e97b0
SY		 119 UFSHCD_STATE_RESET,
120 UFSHCD_STATE_ERROR,
3441da7d 121 UFSHCD_STATE_OPERATIONAL,
141f8165 122 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 123};
124
125/* UFSHCD error handling flags */
126enum {
127 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 128};
129
e8e7f271
SRT		 130/* UFSHCD UIC layer error flags */
131enum {
132 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 133 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
134 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
135 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
136 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
137 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 138};
139
7a3e97b0
SY		 140/* Interrupt configuration options */
141enum {
142 UFSHCD_INT_DISABLE,
143 UFSHCD_INT_ENABLE,
144 UFSHCD_INT_CLEAR,
145};
146
3441da7d
SRT		 147#define ufshcd_set_eh_in_progress(h) \
148 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
149#define ufshcd_eh_in_progress(h) \
150 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
151#define ufshcd_clear_eh_in_progress(h) \
152 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
153
57d104c1
SJ		 154#define ufshcd_set_ufs_dev_active(h) \
155 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
156#define ufshcd_set_ufs_dev_sleep(h) \
157 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
158#define ufshcd_set_ufs_dev_poweroff(h) \
159 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
160#define ufshcd_is_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
162#define ufshcd_is_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
164#define ufshcd_is_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
166
167static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
168 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
169 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
170 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
171 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
172 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
173 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
174};
175
176static inline enum ufs_dev_pwr_mode
177ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
178{
179 return ufs_pm_lvl_states[lvl].dev_state;
180}
181
182static inline enum uic_link_state
183ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].link_state;
186}
187
3441da7d
SRT		 188static void ufshcd_tmc_handler(struct ufs_hba *hba);
189static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 190static int ufshcd_reset_and_restore(struct ufs_hba *hba);
191static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 192static void ufshcd_hba_exit(struct ufs_hba *hba);
193static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 194static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
195 bool skip_ref_clk);
196static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 197static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 198static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
199static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 200static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ		 201static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
202static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 203static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
204 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 205static int ufshcd_change_power_mode(struct ufs_hba *hba,
206 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 207static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
208{
209 return tag >= 0 && tag < hba->nutrs;
210}
57d104c1
SJ		 211
212static inline int ufshcd_enable_irq(struct ufs_hba *hba)
213{
214 int ret = 0;
215
216 if (!hba->is_irq_enabled) {
217 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
218 hba);
219 if (ret)
220 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
221 __func__, ret);
222 hba->is_irq_enabled = true;
223 }
224
225 return ret;
226}
227
228static inline void ufshcd_disable_irq(struct ufs_hba *hba)
229{
230 if (hba->is_irq_enabled) {
231 free_irq(hba->irq, hba);
232 hba->is_irq_enabled = false;
233 }
234}
3441da7d 235
b573d484
YG		 236/* replace non-printable or non-ASCII characters with spaces */
237static inline void ufshcd_remove_non_printable(char *val)
238{
239 if (!val)
240 return;
241
242 if (*val < 0x20 || *val > 0x7e)
243 *val = ' ';
244}
245
5a0b0cb9
SRT		 246/*
247 * ufshcd_wait_for_register - wait for register value to change
248 * @hba - per-adapter interface
249 * @reg - mmio register offset
250 * @mask - mask to apply to read register value
251 * @val - wait condition
252 * @interval_us - polling interval in microsecs
253 * @timeout_ms - timeout in millisecs
596585a2 254 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 255 *
256 * Returns -ETIMEDOUT on error, zero on success
257 */
596585a2
YG		 258int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
259 u32 val, unsigned long interval_us,
260 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 261{
262 int err = 0;
263 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
264
265 /* ignore bits that we don't intend to wait on */
266 val = val & mask;
267
268 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 269 if (can_sleep)
270 usleep_range(interval_us, interval_us + 50);
271 else
272 udelay(interval_us);
5a0b0cb9
SRT		 273 if (time_after(jiffies, timeout)) {
274 if ((ufshcd_readl(hba, reg) & mask) != val)
275 err = -ETIMEDOUT;
276 break;
277 }
278 }
279
280 return err;
281}
282
2fbd009b
SJ		 283/**
284 * ufshcd_get_intr_mask - Get the interrupt bit mask
285 * @hba - Pointer to adapter instance
286 *
287 * Returns interrupt bit mask per version
288 */
289static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
290{
291 if (hba->ufs_version == UFSHCI_VERSION_10)
292 return INTERRUPT_MASK_ALL_VER_10;
293 else
294 return INTERRUPT_MASK_ALL_VER_11;
295}
296
7a3e97b0
SY		 297/**
298 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
299 * @hba - Pointer to adapter instance
300 *
301 * Returns UFSHCI version supported by the controller
302 */
303static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
304{
0263bcd0
YG		 305 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
306 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 307
b873a275 308 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 309}
310
311/**
312 * ufshcd_is_device_present - Check if any device connected to
313 * the host controller
5c0c28a8 314 * @hba: pointer to adapter instance
7a3e97b0 315 *
73ec513a 316 * Returns 1 if device present, 0 if no device detected
7a3e97b0 317 */
5c0c28a8 318static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 319{
5c0c28a8
SRT		 320 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
321 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 322}
323
324/**
325 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
326 * @lrb: pointer to local command reference block
327 *
328 * This function is used to get the OCS field from UTRD
329 * Returns the OCS field in the UTRD
330 */
331static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
332{
e8c8e82a 333 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 334}
335
336/**
337 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
338 * @task_req_descp: pointer to utp_task_req_desc structure
339 *
340 * This function is used to get the OCS field from UTMRD
341 * Returns the OCS field in the UTMRD
342 */
343static inline int
344ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
345{
e8c8e82a 346 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 347}
348
349/**
350 * ufshcd_get_tm_free_slot - get a free slot for task management request
351 * @hba: per adapter instance
e2933132 352 * @free_slot: pointer to variable with available slot value
7a3e97b0 353 *
e2933132
SRT		 354 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
355 * Returns 0 if free slot is not available, else return 1 with tag value
356 * in @free_slot.
7a3e97b0 357 */
e2933132 358static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 359{
e2933132
SRT		 360 int tag;
361 bool ret = false;
362
363 if (!free_slot)
364 goto out;
365
366 do {
367 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
368 if (tag >= hba->nutmrs)
369 goto out;
370 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
371
372 *free_slot = tag;
373 ret = true;
374out:
375 return ret;
376}
377
378static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
379{
380 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 381}
382
383/**
384 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
385 * @hba: per adapter instance
386 * @pos: position of the bit to be cleared
387 */
388static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
389{
b873a275 390 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 391}
392
a48353f6
YG		 393/**
394 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
395 * @hba: per adapter instance
396 * @tag: position of the bit to be cleared
397 */
398static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
399{
400 __clear_bit(tag, &hba->outstanding_reqs);
401}
402
7a3e97b0
SY		 403/**
404 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
405 * @reg: Register value of host controller status
406 *
407 * Returns integer, 0 on Success and positive value if failed
408 */
409static inline int ufshcd_get_lists_status(u32 reg)
410{
411 /*
412 * The mask 0xFF is for the following HCS register bits
413 * Bit Description
414 * 0 Device Present
415 * 1 UTRLRDY
416 * 2 UTMRLRDY
417 * 3 UCRDY
897efe62 418 * 4-7 reserved
7a3e97b0 419 */
897efe62 420 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 421}
422
423/**
424 * ufshcd_get_uic_cmd_result - Get the UIC command result
425 * @hba: Pointer to adapter instance
426 *
427 * This function gets the result of UIC command completion
428 * Returns 0 on success, non zero value on error
429 */
430static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
431{
b873a275 432 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 433 MASK_UIC_COMMAND_RESULT;
434}
435
12b4fdb4
SJ		 436/**
437 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
438 * @hba: Pointer to adapter instance
439 *
440 * This function gets UIC command argument3
441 * Returns 0 on success, non zero value on error
442 */
443static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
444{
445 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
446}
447
7a3e97b0 448/**
5a0b0cb9 449 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 450 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 451 */
452static inline int
5a0b0cb9 453ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 454{
5a0b0cb9 455 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 456}
457
458/**
459 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
460 * @ucd_rsp_ptr: pointer to response UPIU
461 *
462 * This function gets the response status and scsi_status from response UPIU
463 * Returns the response result code.
464 */
465static inline int
466ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
467{
468 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
469}
470
1c2623c5
SJ		 471/*
472 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
473 * from response UPIU
474 * @ucd_rsp_ptr: pointer to response UPIU
475 *
476 * Return the data segment length.
477 */
478static inline unsigned int
479ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
480{
481 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
482 MASK_RSP_UPIU_DATA_SEG_LEN;
483}
484
66ec6d59
SRT		 485/**
486 * ufshcd_is_exception_event - Check if the device raised an exception event
487 * @ucd_rsp_ptr: pointer to response UPIU
488 *
489 * The function checks if the device raised an exception event indicated in
490 * the Device Information field of response UPIU.
491 *
492 * Returns true if exception is raised, false otherwise.
493 */
494static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
495{
496 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
497 MASK_RSP_EXCEPTION_EVENT ? true : false;
498}
499
7a3e97b0 500/**
7d568652 501 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 502 * @hba: per adapter instance
7a3e97b0
SY		 503 */
504static inline void
7d568652 505ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 506{
7d568652
SJ		 507 ufshcd_writel(hba, INT_AGGR_ENABLE |
508 INT_AGGR_COUNTER_AND_TIMER_RESET,
509 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
510}
511
512/**
513 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
514 * @hba: per adapter instance
515 * @cnt: Interrupt aggregation counter threshold
516 * @tmout: Interrupt aggregation timeout value
517 */
518static inline void
519ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
520{
521 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
522 INT_AGGR_COUNTER_THLD_VAL(cnt) |
523 INT_AGGR_TIMEOUT_VAL(tmout),
524 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 525}
526
b852190e
YG		 527/**
528 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
529 * @hba: per adapter instance
530 */
531static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
532{
533 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
534}
535
7a3e97b0
SY		 536/**
537 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
538 * When run-stop registers are set to 1, it indicates the
539 * host controller that it can process the requests
540 * @hba: per adapter instance
541 */
542static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
543{
b873a275
SJ		 544 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
545 REG_UTP_TASK_REQ_LIST_RUN_STOP);
546 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
547 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 548}
549
7a3e97b0
SY		 550/**
551 * ufshcd_hba_start - Start controller initialization sequence
552 * @hba: per adapter instance
553 */
554static inline void ufshcd_hba_start(struct ufs_hba *hba)
555{
b873a275 556 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 557}
558
559/**
560 * ufshcd_is_hba_active - Get controller state
561 * @hba: per adapter instance
562 *
563 * Returns zero if controller is active, 1 otherwise
564 */
565static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
566{
b873a275 567 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 568}
569
37113106
YG		 570u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
571{
572 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
573 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
574 (hba->ufs_version == UFSHCI_VERSION_11))
575 return UFS_UNIPRO_VER_1_41;
576 else
577 return UFS_UNIPRO_VER_1_6;
578}
579EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
580
581static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
582{
583 /*
584 * If both host and device support UniPro ver1.6 or later, PA layer
585 * parameters tuning happens during link startup itself.
586 *
587 * We can manually tune PA layer parameters if either host or device
588 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
589 * logic simple, we will only do manual tuning if local unipro version
590 * doesn't support ver1.6 or later.
591 */
592 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
593 return true;
594 else
595 return false;
596}
597
a508253d
GB		 598static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
599{
600 if (ufshcd_is_clkscaling_enabled(hba)) {
601 devfreq_suspend_device(hba->devfreq);
602 hba->clk_scaling.window_start_t = 0;
603 }
604}
605
606static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
607{
608 if (ufshcd_is_clkscaling_enabled(hba))
609 devfreq_resume_device(hba->devfreq);
610}
611
1ab27c9c
ST		 612static void ufshcd_ungate_work(struct work_struct *work)
613{
614 int ret;
615 unsigned long flags;
616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
617 clk_gating.ungate_work);
618
619 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
620
621 spin_lock_irqsave(hba->host->host_lock, flags);
622 if (hba->clk_gating.state == CLKS_ON) {
623 spin_unlock_irqrestore(hba->host->host_lock, flags);
624 goto unblock_reqs;
625 }
626
627 spin_unlock_irqrestore(hba->host->host_lock, flags);
628 ufshcd_setup_clocks(hba, true);
629
630 /* Exit from hibern8 */
631 if (ufshcd_can_hibern8_during_gating(hba)) {
632 /* Prevent gating in this path */
633 hba->clk_gating.is_suspended = true;
634 if (ufshcd_is_link_hibern8(hba)) {
635 ret = ufshcd_uic_hibern8_exit(hba);
636 if (ret)
637 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
638 __func__, ret);
639 else
640 ufshcd_set_link_active(hba);
641 }
642 hba->clk_gating.is_suspended = false;
643 }
644unblock_reqs:
a508253d 645 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 646 scsi_unblock_requests(hba->host);
647}
648
649/**
650 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
651 * Also, exit from hibern8 mode and set the link as active.
652 * @hba: per adapter instance
653 * @async: This indicates whether caller should ungate clocks asynchronously.
654 */
655int ufshcd_hold(struct ufs_hba *hba, bool async)
656{
657 int rc = 0;
658 unsigned long flags;
659
660 if (!ufshcd_is_clkgating_allowed(hba))
661 goto out;
1ab27c9c
ST		 662 spin_lock_irqsave(hba->host->host_lock, flags);
663 hba->clk_gating.active_reqs++;
664
53c12d0e
YG		 665 if (ufshcd_eh_in_progress(hba)) {
666 spin_unlock_irqrestore(hba->host->host_lock, flags);
667 return 0;
668 }
669
856b3483 670start:
1ab27c9c
ST		 671 switch (hba->clk_gating.state) {
672 case CLKS_ON:
f2a785ac
VG		 673 /*
674 * Wait for the ungate work to complete if in progress.
675 * Though the clocks may be in ON state, the link could
676 * still be in hibner8 state if hibern8 is allowed
677 * during clock gating.
678 * Make sure we exit hibern8 state also in addition to
679 * clocks being ON.
680 */
681 if (ufshcd_can_hibern8_during_gating(hba) &&
682 ufshcd_is_link_hibern8(hba)) {
683 spin_unlock_irqrestore(hba->host->host_lock, flags);
684 flush_work(&hba->clk_gating.ungate_work);
685 spin_lock_irqsave(hba->host->host_lock, flags);
686 goto start;
687 }
1ab27c9c
ST		 688 break;
689 case REQ_CLKS_OFF:
690 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
691 hba->clk_gating.state = CLKS_ON;
692 break;
693 }
694 /*
695 * If we here, it means gating work is either done or
696 * currently running. Hence, fall through to cancel gating
697 * work and to enable clocks.
698 */
699 case CLKS_OFF:
700 scsi_block_requests(hba->host);
701 hba->clk_gating.state = REQ_CLKS_ON;
702 schedule_work(&hba->clk_gating.ungate_work);
703 /*
704 * fall through to check if we should wait for this
705 * work to be done or not.
706 */
707 case REQ_CLKS_ON:
708 if (async) {
709 rc = -EAGAIN;
710 hba->clk_gating.active_reqs--;
711 break;
712 }
713
714 spin_unlock_irqrestore(hba->host->host_lock, flags);
715 flush_work(&hba->clk_gating.ungate_work);
716 /* Make sure state is CLKS_ON before returning */
856b3483 717 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 718 goto start;
719 default:
720 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
721 __func__, hba->clk_gating.state);
722 break;
723 }
724 spin_unlock_irqrestore(hba->host->host_lock, flags);
725out:
726 return rc;
727}
6e3fd44d 728EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 729
730static void ufshcd_gate_work(struct work_struct *work)
731{
732 struct ufs_hba *hba = container_of(work, struct ufs_hba,
733 clk_gating.gate_work.work);
734 unsigned long flags;
735
736 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 737 /*
738 * In case you are here to cancel this work the gating state
739 * would be marked as REQ_CLKS_ON. In this case save time by
740 * skipping the gating work and exit after changing the clock
741 * state to CLKS_ON.
742 */
743 if (hba->clk_gating.is_suspended ||
744 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c
ST		 745 hba->clk_gating.state = CLKS_ON;
746 goto rel_lock;
747 }
748
749 if (hba->clk_gating.active_reqs
750 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
751 || hba->lrb_in_use || hba->outstanding_tasks
752 || hba->active_uic_cmd || hba->uic_async_done)
753 goto rel_lock;
754
755 spin_unlock_irqrestore(hba->host->host_lock, flags);
756
757 /* put the link into hibern8 mode before turning off clocks */
758 if (ufshcd_can_hibern8_during_gating(hba)) {
759 if (ufshcd_uic_hibern8_enter(hba)) {
760 hba->clk_gating.state = CLKS_ON;
761 goto out;
762 }
763 ufshcd_set_link_hibern8(hba);
764 }
765
a508253d 766 ufshcd_suspend_clkscaling(hba);
856b3483 767
1ab27c9c
ST		 768 if (!ufshcd_is_link_active(hba))
769 ufshcd_setup_clocks(hba, false);
770 else
771 /* If link is active, device ref_clk can't be switched off */
772 __ufshcd_setup_clocks(hba, false, true);
773
774 /*
775 * In case you are here to cancel this work the gating state
776 * would be marked as REQ_CLKS_ON. In this case keep the state
777 * as REQ_CLKS_ON which would anyway imply that clocks are off
778 * and a request to turn them on is pending. By doing this way,
779 * we keep the state machine in tact and this would ultimately
780 * prevent from doing cancel work multiple times when there are
781 * new requests arriving before the current cancel work is done.
782 */
783 spin_lock_irqsave(hba->host->host_lock, flags);
784 if (hba->clk_gating.state == REQ_CLKS_OFF)
785 hba->clk_gating.state = CLKS_OFF;
786
787rel_lock:
788 spin_unlock_irqrestore(hba->host->host_lock, flags);
789out:
790 return;
791}
792
793/* host lock must be held before calling this variant */
794static void __ufshcd_release(struct ufs_hba *hba)
795{
796 if (!ufshcd_is_clkgating_allowed(hba))
797 return;
798
799 hba->clk_gating.active_reqs--;
800
801 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
802 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
803 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 804 || hba->active_uic_cmd || hba->uic_async_done
805 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 806 return;
807
808 hba->clk_gating.state = REQ_CLKS_OFF;
809 schedule_delayed_work(&hba->clk_gating.gate_work,
810 msecs_to_jiffies(hba->clk_gating.delay_ms));
811}
812
813void ufshcd_release(struct ufs_hba *hba)
814{
815 unsigned long flags;
816
817 spin_lock_irqsave(hba->host->host_lock, flags);
818 __ufshcd_release(hba);
819 spin_unlock_irqrestore(hba->host->host_lock, flags);
820}
6e3fd44d 821EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 822
823static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
824 struct device_attribute *attr, char *buf)
825{
826 struct ufs_hba *hba = dev_get_drvdata(dev);
827
828 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
829}
830
831static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
832 struct device_attribute *attr, const char *buf, size_t count)
833{
834 struct ufs_hba *hba = dev_get_drvdata(dev);
835 unsigned long flags, value;
836
837 if (kstrtoul(buf, 0, &value))
838 return -EINVAL;
839
840 spin_lock_irqsave(hba->host->host_lock, flags);
841 hba->clk_gating.delay_ms = value;
842 spin_unlock_irqrestore(hba->host->host_lock, flags);
843 return count;
844}
845
846static void ufshcd_init_clk_gating(struct ufs_hba *hba)
847{
848 if (!ufshcd_is_clkgating_allowed(hba))
849 return;
850
851 hba->clk_gating.delay_ms = 150;
852 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
853 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
854
855 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
856 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
857 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
858 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
859 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
860 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
861 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
862}
863
864static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
865{
866 if (!ufshcd_is_clkgating_allowed(hba))
867 return;
868 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM		 869 cancel_work_sync(&hba->clk_gating.ungate_work);
870 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 871}
872
856b3483
ST		 873/* Must be called with host lock acquired */
874static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
875{
876 if (!ufshcd_is_clkscaling_enabled(hba))
877 return;
878
879 if (!hba->clk_scaling.is_busy_started) {
880 hba->clk_scaling.busy_start_t = ktime_get();
881 hba->clk_scaling.is_busy_started = true;
882 }
883}
884
885static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
886{
887 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
888
889 if (!ufshcd_is_clkscaling_enabled(hba))
890 return;
891
892 if (!hba->outstanding_reqs && scaling->is_busy_started) {
893 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
894 scaling->busy_start_t));
895 scaling->busy_start_t = ktime_set(0, 0);
896 scaling->is_busy_started = false;
897 }
898}
7a3e97b0
SY		 899/**
900 * ufshcd_send_command - Send SCSI or device management commands
901 * @hba: per adapter instance
902 * @task_tag: Task tag of the command
903 */
904static inline
905void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
906{
856b3483 907 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 908 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 909 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 910 /* Make sure that doorbell is committed immediately */
911 wmb();
7a3e97b0
SY		 912}
913
914/**
915 * ufshcd_copy_sense_data - Copy sense data in case of check condition
916 * @lrb - pointer to local reference block
917 */
918static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
919{
920 int len;
1c2623c5
SJ		 921 if (lrbp->sense_buffer &&
922 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 923 int len_to_copy;
924
5a0b0cb9 925 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 926 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
927
7a3e97b0 928 memcpy(lrbp->sense_buffer,
5a0b0cb9 929 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 930 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 931 }
932}
933
68078d5c
DR		 934/**
935 * ufshcd_copy_query_response() - Copy the Query Response and the data
936 * descriptor
937 * @hba: per adapter instance
938 * @lrb - pointer to local reference block
939 */
940static
c6d4a831 941int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 942{
943 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
944
68078d5c 945 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 946
68078d5c
DR		 947 /* Get the descriptor */
948 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 949 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 950 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 951 u16 resp_len;
952 u16 buf_len;
68078d5c
DR		 953
954 /* data segment length */
c6d4a831 955 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 956 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 957 buf_len = be16_to_cpu(
958 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 959 if (likely(buf_len >= resp_len)) {
960 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
961 } else {
962 dev_warn(hba->dev,
963 "%s: Response size is bigger than buffer",
964 __func__);
965 return -EINVAL;
966 }
68078d5c 967 }
c6d4a831
DR		 968
969 return 0;
68078d5c
DR		 970}
971
7a3e97b0
SY		 972/**
973 * ufshcd_hba_capabilities - Read controller capabilities
974 * @hba: per adapter instance
975 */
976static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
977{
b873a275 978 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 979
980 /* nutrs and nutmrs are 0 based values */
981 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
982 hba->nutmrs =
983 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
984}
985
986/**
6ccf44fe
SJ		 987 * ufshcd_ready_for_uic_cmd - Check if controller is ready
988 * to accept UIC commands
7a3e97b0 989 * @hba: per adapter instance
6ccf44fe
SJ		 990 * Return true on success, else false
991 */
992static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
993{
994 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
995 return true;
996 else
997 return false;
998}
999
53b3d9c3
SJ		 1000/**
1001 * ufshcd_get_upmcrs - Get the power mode change request status
1002 * @hba: Pointer to adapter instance
1003 *
1004 * This function gets the UPMCRS field of HCS register
1005 * Returns value of UPMCRS field
1006 */
1007static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1008{
1009 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1010}
1011
6ccf44fe
SJ		 1012/**
1013 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1014 * @hba: per adapter instance
1015 * @uic_cmd: UIC command
1016 *
1017 * Mutex must be held.
7a3e97b0
SY		 1018 */
1019static inline void
6ccf44fe 1020ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1021{
6ccf44fe
SJ		 1022 WARN_ON(hba->active_uic_cmd);
1023
1024 hba->active_uic_cmd = uic_cmd;
1025
7a3e97b0 1026 /* Write Args */
6ccf44fe
SJ		 1027 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1028 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1029 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1030
1031 /* Write UIC Cmd */
6ccf44fe 1032 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1033 REG_UIC_COMMAND);
7a3e97b0
SY		 1034}
1035
6ccf44fe
SJ		 1036/**
1037 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1038 * @hba: per adapter instance
1039 * @uic_command: UIC command
1040 *
1041 * Must be called with mutex held.
1042 * Returns 0 only if success.
1043 */
1044static int
1045ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1046{
1047 int ret;
1048 unsigned long flags;
1049
1050 if (wait_for_completion_timeout(&uic_cmd->done,
1051 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1052 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1053 else
1054 ret = -ETIMEDOUT;
1055
1056 spin_lock_irqsave(hba->host->host_lock, flags);
1057 hba->active_uic_cmd = NULL;
1058 spin_unlock_irqrestore(hba->host->host_lock, flags);
1059
1060 return ret;
1061}
1062
1063/**
1064 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1065 * @hba: per adapter instance
1066 * @uic_cmd: UIC command
d75f7fe4 1067 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1068 *
1069 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1070 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1071 * Returns 0 only if success.
1072 */
1073static int
d75f7fe4
YG		 1074__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1075 bool completion)
6ccf44fe 1076{
6ccf44fe
SJ		 1077 if (!ufshcd_ready_for_uic_cmd(hba)) {
1078 dev_err(hba->dev,
1079 "Controller not ready to accept UIC commands\n");
1080 return -EIO;
1081 }
1082
d75f7fe4
YG		 1083 if (completion)
1084 init_completion(&uic_cmd->done);
6ccf44fe 1085
6ccf44fe 1086 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1087
57d104c1 1088 return 0;
6ccf44fe
SJ		 1089}
1090
1091/**
1092 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1093 * @hba: per adapter instance
1094 * @uic_cmd: UIC command
1095 *
1096 * Returns 0 only if success.
1097 */
1098static int
1099ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1100{
1101 int ret;
57d104c1 1102 unsigned long flags;
6ccf44fe 1103
1ab27c9c 1104 ufshcd_hold(hba, false);
6ccf44fe 1105 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1106 ufshcd_add_delay_before_dme_cmd(hba);
1107
57d104c1 1108 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1109 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1110 spin_unlock_irqrestore(hba->host->host_lock, flags);
1111 if (!ret)
1112 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1113
6ccf44fe
SJ		 1114 mutex_unlock(&hba->uic_cmd_mutex);
1115
1ab27c9c 1116 ufshcd_release(hba);
6ccf44fe
SJ		 1117 return ret;
1118}
1119
7a3e97b0
SY		 1120/**
1121 * ufshcd_map_sg - Map scatter-gather list to prdt
1122 * @lrbp - pointer to local reference block
1123 *
1124 * Returns 0 in case of success, non-zero value in case of failure
1125 */
75b1cc4a 1126static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1127{
1128 struct ufshcd_sg_entry *prd_table;
1129 struct scatterlist *sg;
1130 struct scsi_cmnd *cmd;
1131 int sg_segments;
1132 int i;
1133
1134 cmd = lrbp->cmd;
1135 sg_segments = scsi_dma_map(cmd);
1136 if (sg_segments < 0)
1137 return sg_segments;
1138
1139 if (sg_segments) {
75b1cc4a
KK		 1140 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1141 lrbp->utr_descriptor_ptr->prd_table_length =
1142 cpu_to_le16((u16)(sg_segments *
1143 sizeof(struct ufshcd_sg_entry)));
1144 else
1145 lrbp->utr_descriptor_ptr->prd_table_length =
1146 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 1147
1148 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1149
1150 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1151 prd_table[i].size =
1152 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1153 prd_table[i].base_addr =
1154 cpu_to_le32(lower_32_bits(sg->dma_address));
1155 prd_table[i].upper_addr =
1156 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1157 prd_table[i].reserved = 0;
7a3e97b0
SY		 1158 }
1159 } else {
1160 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1161 }
1162
1163 return 0;
1164}
1165
1166/**
2fbd009b 1167 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1168 * @hba: per adapter instance
2fbd009b 1169 * @intrs: interrupt bits
7a3e97b0 1170 */
2fbd009b 1171static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1172{
2fbd009b
SJ		 1173 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1174
1175 if (hba->ufs_version == UFSHCI_VERSION_10) {
1176 u32 rw;
1177 rw = set & INTERRUPT_MASK_RW_VER_10;
1178 set = rw | ((set ^ intrs) & intrs);
1179 } else {
1180 set |= intrs;
1181 }
1182
1183 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1184}
1185
1186/**
1187 * ufshcd_disable_intr - disable interrupts
1188 * @hba: per adapter instance
1189 * @intrs: interrupt bits
1190 */
1191static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1192{
1193 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1194
1195 if (hba->ufs_version == UFSHCI_VERSION_10) {
1196 u32 rw;
1197 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1198 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1199 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1200
1201 } else {
1202 set &= ~intrs;
7a3e97b0 1203 }
2fbd009b
SJ		 1204
1205 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1206}
1207
5a0b0cb9
SRT		 1208/**
1209 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1210 * descriptor according to request
1211 * @lrbp: pointer to local reference block
1212 * @upiu_flags: flags required in the header
1213 * @cmd_dir: requests data direction
1214 */
1215static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1216 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 1217{
1218 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1219 u32 data_direction;
1220 u32 dword_0;
1221
1222 if (cmd_dir == DMA_FROM_DEVICE) {
1223 data_direction = UTP_DEVICE_TO_HOST;
1224 *upiu_flags = UPIU_CMD_FLAGS_READ;
1225 } else if (cmd_dir == DMA_TO_DEVICE) {
1226 data_direction = UTP_HOST_TO_DEVICE;
1227 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1228 } else {
1229 data_direction = UTP_NO_DATA_TRANSFER;
1230 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1231 }
1232
1233 dword_0 = data_direction | (lrbp->command_type
1234 << UPIU_COMMAND_TYPE_OFFSET);
1235 if (lrbp->intr_cmd)
1236 dword_0 |= UTP_REQ_DESC_INT_CMD;
1237
1238 /* Transfer request descriptor header fields */
1239 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1240 /* dword_1 is reserved, hence it is set to 0 */
1241 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1242 /*
1243 * assigning invalid value for command status. Controller
1244 * updates OCS on command completion, with the command
1245 * status
1246 */
1247 req_desc->header.dword_2 =
1248 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1249 /* dword_3 is reserved, hence it is set to 0 */
1250 req_desc->header.dword_3 = 0;
51047266
YG		 1251
1252 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1253}
1254
1255/**
1256 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1257 * for scsi commands
1258 * @lrbp - local reference block pointer
1259 * @upiu_flags - flags
1260 */
1261static
1262void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1263{
1264 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1265 unsigned short cdb_len;
5a0b0cb9
SRT		 1266
1267 /* command descriptor fields */
1268 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1269 UPIU_TRANSACTION_COMMAND, upiu_flags,
1270 lrbp->lun, lrbp->task_tag);
1271 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1272 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1273
1274 /* Total EHS length and Data segment length will be zero */
1275 ucd_req_ptr->header.dword_2 = 0;
1276
1277 ucd_req_ptr->sc.exp_data_transfer_len =
1278 cpu_to_be32(lrbp->cmd->sdb.length);
1279
52ac95fe
YG		 1280 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1281 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1282 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1283
1284 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1285}
1286
68078d5c
DR		 1287/**
1288 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1289 * for query requsts
1290 * @hba: UFS hba
1291 * @lrbp: local reference block pointer
1292 * @upiu_flags: flags
1293 */
1294static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1295 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1296{
1297 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1298 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1299 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1300 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1301
1302 /* Query request header */
1303 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1304 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1305 lrbp->lun, lrbp->task_tag);
1306 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1307 0, query->request.query_func, 0, 0);
1308
6861285c
ZL		 1309 /* Data segment length only need for WRITE_DESC */
1310 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1311 ucd_req_ptr->header.dword_2 =
1312 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
1313 else
1314 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 1315
1316 /* Copy the Query Request buffer as is */
1317 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1318 QUERY_OSF_SIZE);
68078d5c
DR		 1319
1320 /* Copy the Descriptor */
c6d4a831
DR		 1321 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1322 memcpy(descp, query->descriptor, len);
1323
51047266 1324 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1325}
1326
5a0b0cb9
SRT		 1327static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1328{
1329 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1330
1331 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1332
1333 /* command descriptor fields */
1334 ucd_req_ptr->header.dword_0 =
1335 UPIU_HEADER_DWORD(
1336 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1337 /* clear rest of the fields of basic header */
1338 ucd_req_ptr->header.dword_1 = 0;
1339 ucd_req_ptr->header.dword_2 = 0;
1340
1341 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1342}
1343
7a3e97b0 1344/**
300bb13f
JP		 1345 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1346 * for Device Management Purposes
5a0b0cb9 1347 * @hba - per adapter instance
7a3e97b0
SY		 1348 * @lrb - pointer to local reference block
1349 */
300bb13f 1350static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1351{
7a3e97b0 1352 u32 upiu_flags;
5a0b0cb9 1353 int ret = 0;
7a3e97b0 1354
300bb13f
JP		 1355 if (hba->ufs_version == UFSHCI_VERSION_20)
1356 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1357 else
1358 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1359
1360 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1361 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1362 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1363 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1364 ufshcd_prepare_utp_nop_upiu(lrbp);
1365 else
1366 ret = -EINVAL;
1367
1368 return ret;
1369}
1370
1371/**
1372 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1373 * for SCSI Purposes
1374 * @hba - per adapter instance
1375 * @lrb - pointer to local reference block
1376 */
1377static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1378{
1379 u32 upiu_flags;
1380 int ret = 0;
1381
1382 if (hba->ufs_version == UFSHCI_VERSION_20)
1383 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1384 else
1385 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1386
1387 if (likely(lrbp->cmd)) {
1388 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1389 lrbp->cmd->sc_data_direction);
1390 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1391 } else {
1392 ret = -EINVAL;
1393 }
5a0b0cb9
SRT		 1394
1395 return ret;
7a3e97b0
SY		 1396}
1397
0ce147d4
SJ		 1398/*
1399 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1400 * @scsi_lun: scsi LUN id
1401 *
1402 * Returns UPIU LUN id
1403 */
1404static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1405{
1406 if (scsi_is_wlun(scsi_lun))
1407 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1408 | UFS_UPIU_WLUN_ID;
1409 else
1410 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1411}
1412
2a8fa600
SJ		 1413/**
1414 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1415 * @scsi_lun: UPIU W-LUN id
1416 *
1417 * Returns SCSI W-LUN id
1418 */
1419static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1420{
1421 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1422}
1423
7a3e97b0
SY		 1424/**
1425 * ufshcd_queuecommand - main entry point for SCSI requests
1426 * @cmd: command from SCSI Midlayer
1427 * @done: call back function
1428 *
1429 * Returns 0 for success, non-zero in case of failure
1430 */
1431static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1432{
1433 struct ufshcd_lrb *lrbp;
1434 struct ufs_hba *hba;
1435 unsigned long flags;
1436 int tag;
1437 int err = 0;
1438
1439 hba = shost_priv(host);
1440
1441 tag = cmd->request->tag;
14497328
YG		 1442 if (!ufshcd_valid_tag(hba, tag)) {
1443 dev_err(hba->dev,
1444 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1445 __func__, tag, cmd, cmd->request);
1446 BUG();
1447 }
7a3e97b0 1448
3441da7d
SRT		 1449 spin_lock_irqsave(hba->host->host_lock, flags);
1450 switch (hba->ufshcd_state) {
1451 case UFSHCD_STATE_OPERATIONAL:
1452 break;
141f8165 1453 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 1454 case UFSHCD_STATE_RESET:
7a3e97b0 1455 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1456 goto out_unlock;
1457 case UFSHCD_STATE_ERROR:
1458 set_host_byte(cmd, DID_ERROR);
1459 cmd->scsi_done(cmd);
1460 goto out_unlock;
1461 default:
1462 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1463 __func__, hba->ufshcd_state);
1464 set_host_byte(cmd, DID_BAD_TARGET);
1465 cmd->scsi_done(cmd);
1466 goto out_unlock;
7a3e97b0 1467 }
53c12d0e
YG		 1468
1469 /* if error handling is in progress, don't issue commands */
1470 if (ufshcd_eh_in_progress(hba)) {
1471 set_host_byte(cmd, DID_ERROR);
1472 cmd->scsi_done(cmd);
1473 goto out_unlock;
1474 }
3441da7d 1475 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1476
5a0b0cb9
SRT		 1477 /* acquire the tag to make sure device cmds don't use it */
1478 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1479 /*
1480 * Dev manage command in progress, requeue the command.
1481 * Requeuing the command helps in cases where the request *may*
1482 * find different tag instead of waiting for dev manage command
1483 * completion.
1484 */
1485 err = SCSI_MLQUEUE_HOST_BUSY;
1486 goto out;
1487 }
1488
1ab27c9c
ST		 1489 err = ufshcd_hold(hba, true);
1490 if (err) {
1491 err = SCSI_MLQUEUE_HOST_BUSY;
1492 clear_bit_unlock(tag, &hba->lrb_in_use);
1493 goto out;
1494 }
1495 WARN_ON(hba->clk_gating.state != CLKS_ON);
1496
7a3e97b0
SY		 1497 lrbp = &hba->lrb[tag];
1498
5a0b0cb9 1499 WARN_ON(lrbp->cmd);
7a3e97b0 1500 lrbp->cmd = cmd;
dcea0bfb 1501 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 1502 lrbp->sense_buffer = cmd->sense_buffer;
1503 lrbp->task_tag = tag;
0ce147d4 1504 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1505 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1506
300bb13f
JP		 1507 ufshcd_comp_scsi_upiu(hba, lrbp);
1508
75b1cc4a 1509 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 1510 if (err) {
1511 lrbp->cmd = NULL;
1512 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1513 goto out;
5a0b0cb9 1514 }
ad1a1b9c
GB		 1515 /* Make sure descriptors are ready before ringing the doorbell */
1516 wmb();
7a3e97b0
SY		 1517
1518 /* issue command to the controller */
1519 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1520 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 1521 ufshcd_send_command(hba, tag);
3441da7d 1522out_unlock:
7a3e97b0
SY		 1523 spin_unlock_irqrestore(hba->host->host_lock, flags);
1524out:
1525 return err;
1526}
1527
5a0b0cb9
SRT		 1528static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1529 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1530{
1531 lrbp->cmd = NULL;
1532 lrbp->sense_bufflen = 0;
1533 lrbp->sense_buffer = NULL;
1534 lrbp->task_tag = tag;
1535 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 1536 lrbp->intr_cmd = true; /* No interrupt aggregation */
1537 hba->dev_cmd.type = cmd_type;
1538
300bb13f 1539 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 1540}
1541
1542static int
1543ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1544{
1545 int err = 0;
1546 unsigned long flags;
1547 u32 mask = 1 << tag;
1548
1549 /* clear outstanding transaction before retry */
1550 spin_lock_irqsave(hba->host->host_lock, flags);
1551 ufshcd_utrl_clear(hba, tag);
1552 spin_unlock_irqrestore(hba->host->host_lock, flags);
1553
1554 /*
1555 * wait for for h/w to clear corresponding bit in door-bell.
1556 * max. wait is 1 sec.
1557 */
1558 err = ufshcd_wait_for_register(hba,
1559 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1560 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 1561
1562 return err;
1563}
1564
c6d4a831
DR		 1565static int
1566ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1567{
1568 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1569
1570 /* Get the UPIU response */
1571 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1572 UPIU_RSP_CODE_OFFSET;
1573 return query_res->response;
1574}
1575
5a0b0cb9
SRT		 1576/**
1577 * ufshcd_dev_cmd_completion() - handles device management command responses
1578 * @hba: per adapter instance
1579 * @lrbp: pointer to local reference block
1580 */
1581static int
1582ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1583{
1584 int resp;
1585 int err = 0;
1586
1587 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1588
1589 switch (resp) {
1590 case UPIU_TRANSACTION_NOP_IN:
1591 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1592 err = -EINVAL;
1593 dev_err(hba->dev, "%s: unexpected response %x\n",
1594 __func__, resp);
1595 }
1596 break;
68078d5c 1597 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1598 err = ufshcd_check_query_response(hba, lrbp);
1599 if (!err)
1600 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1601 break;
5a0b0cb9
SRT		 1602 case UPIU_TRANSACTION_REJECT_UPIU:
1603 /* TODO: handle Reject UPIU Response */
1604 err = -EPERM;
1605 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1606 __func__);
1607 break;
1608 default:
1609 err = -EINVAL;
1610 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1611 __func__, resp);
1612 break;
1613 }
1614
1615 return err;
1616}
1617
1618static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1619 struct ufshcd_lrb *lrbp, int max_timeout)
1620{
1621 int err = 0;
1622 unsigned long time_left;
1623 unsigned long flags;
1624
1625 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1626 msecs_to_jiffies(max_timeout));
1627
ad1a1b9c
GB		 1628 /* Make sure descriptors are ready before ringing the doorbell */
1629 wmb();
5a0b0cb9
SRT		 1630 spin_lock_irqsave(hba->host->host_lock, flags);
1631 hba->dev_cmd.complete = NULL;
1632 if (likely(time_left)) {
1633 err = ufshcd_get_tr_ocs(lrbp);
1634 if (!err)
1635 err = ufshcd_dev_cmd_completion(hba, lrbp);
1636 }
1637 spin_unlock_irqrestore(hba->host->host_lock, flags);
1638
1639 if (!time_left) {
1640 err = -ETIMEDOUT;
a48353f6
YG		 1641 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1642 __func__, lrbp->task_tag);
5a0b0cb9 1643 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1644 /* successfully cleared the command, retry if needed */
5a0b0cb9 1645 err = -EAGAIN;
a48353f6
YG		 1646 /*
1647 * in case of an error, after clearing the doorbell,
1648 * we also need to clear the outstanding_request
1649 * field in hba
1650 */
1651 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1652 }
1653
1654 return err;
1655}
1656
1657/**
1658 * ufshcd_get_dev_cmd_tag - Get device management command tag
1659 * @hba: per-adapter instance
1660 * @tag: pointer to variable with available slot value
1661 *
1662 * Get a free slot and lock it until device management command
1663 * completes.
1664 *
1665 * Returns false if free slot is unavailable for locking, else
1666 * return true with tag value in @tag.
1667 */
1668static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1669{
1670 int tag;
1671 bool ret = false;
1672 unsigned long tmp;
1673
1674 if (!tag_out)
1675 goto out;
1676
1677 do {
1678 tmp = ~hba->lrb_in_use;
1679 tag = find_last_bit(&tmp, hba->nutrs);
1680 if (tag >= hba->nutrs)
1681 goto out;
1682 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1683
1684 *tag_out = tag;
1685 ret = true;
1686out:
1687 return ret;
1688}
1689
1690static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1691{
1692 clear_bit_unlock(tag, &hba->lrb_in_use);
1693}
1694
1695/**
1696 * ufshcd_exec_dev_cmd - API for sending device management requests
1697 * @hba - UFS hba
1698 * @cmd_type - specifies the type (NOP, Query...)
1699 * @timeout - time in seconds
1700 *
68078d5c
DR		 1701 * NOTE: Since there is only one available tag for device management commands,
1702 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1703 */
1704static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1705 enum dev_cmd_type cmd_type, int timeout)
1706{
1707 struct ufshcd_lrb *lrbp;
1708 int err;
1709 int tag;
1710 struct completion wait;
1711 unsigned long flags;
1712
1713 /*
1714 * Get free slot, sleep if slots are unavailable.
1715 * Even though we use wait_event() which sleeps indefinitely,
1716 * the maximum wait time is bounded by SCSI request timeout.
1717 */
1718 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1719
1720 init_completion(&wait);
1721 lrbp = &hba->lrb[tag];
1722 WARN_ON(lrbp->cmd);
1723 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1724 if (unlikely(err))
1725 goto out_put_tag;
1726
1727 hba->dev_cmd.complete = &wait;
1728
e3dfdc53
YG		 1729 /* Make sure descriptors are ready before ringing the doorbell */
1730 wmb();
5a0b0cb9 1731 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1732 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 1733 ufshcd_send_command(hba, tag);
1734 spin_unlock_irqrestore(hba->host->host_lock, flags);
1735
1736 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1737
1738out_put_tag:
1739 ufshcd_put_dev_cmd_tag(hba, tag);
1740 wake_up(&hba->dev_cmd.tag_wq);
1741 return err;
1742}
1743
d44a5f98
DR		 1744/**
1745 * ufshcd_init_query() - init the query response and request parameters
1746 * @hba: per-adapter instance
1747 * @request: address of the request pointer to be initialized
1748 * @response: address of the response pointer to be initialized
1749 * @opcode: operation to perform
1750 * @idn: flag idn to access
1751 * @index: LU number to access
1752 * @selector: query/flag/descriptor further identification
1753 */
1754static inline void ufshcd_init_query(struct ufs_hba *hba,
1755 struct ufs_query_req **request, struct ufs_query_res **response,
1756 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1757{
1758 *request = &hba->dev_cmd.query.request;
1759 *response = &hba->dev_cmd.query.response;
1760 memset(*request, 0, sizeof(struct ufs_query_req));
1761 memset(*response, 0, sizeof(struct ufs_query_res));
1762 (*request)->upiu_req.opcode = opcode;
1763 (*request)->upiu_req.idn = idn;
1764 (*request)->upiu_req.index = index;
1765 (*request)->upiu_req.selector = selector;
1766}
1767
dc3c8d3a
YG		 1768static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1769 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
1770{
1771 int ret;
1772 int retries;
1773
1774 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1775 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1776 if (ret)
1777 dev_dbg(hba->dev,
1778 "%s: failed with error %d, retries %d\n",
1779 __func__, ret, retries);
1780 else
1781 break;
1782 }
1783
1784 if (ret)
1785 dev_err(hba->dev,
1786 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1787 __func__, opcode, idn, ret, retries);
1788 return ret;
1789}
1790
68078d5c
DR		 1791/**
1792 * ufshcd_query_flag() - API function for sending flag query requests
1793 * hba: per-adapter instance
1794 * query_opcode: flag query to perform
1795 * idn: flag idn to access
1796 * flag_res: the flag value after the query request completes
1797 *
1798 * Returns 0 for success, non-zero in case of failure
1799 */
dc3c8d3a 1800int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 1801 enum flag_idn idn, bool *flag_res)
1802{
d44a5f98
DR		 1803 struct ufs_query_req *request = NULL;
1804 struct ufs_query_res *response = NULL;
1805 int err, index = 0, selector = 0;
e5ad406c 1806 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 1807
1808 BUG_ON(!hba);
1809
1ab27c9c 1810 ufshcd_hold(hba, false);
68078d5c 1811 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1812 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1813 selector);
68078d5c
DR		 1814
1815 switch (opcode) {
1816 case UPIU_QUERY_OPCODE_SET_FLAG:
1817 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1818 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1819 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1820 break;
1821 case UPIU_QUERY_OPCODE_READ_FLAG:
1822 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1823 if (!flag_res) {
1824 /* No dummy reads */
1825 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1826 __func__);
1827 err = -EINVAL;
1828 goto out_unlock;
1829 }
1830 break;
1831 default:
1832 dev_err(hba->dev,
1833 "%s: Expected query flag opcode but got = %d\n",
1834 __func__, opcode);
1835 err = -EINVAL;
1836 goto out_unlock;
1837 }
68078d5c 1838
e5ad406c 1839 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 1840
1841 if (err) {
1842 dev_err(hba->dev,
1843 "%s: Sending flag query for idn %d failed, err = %d\n",
1844 __func__, idn, err);
1845 goto out_unlock;
1846 }
1847
1848 if (flag_res)
e8c8e82a 1849 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1850 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1851
1852out_unlock:
1853 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1854 ufshcd_release(hba);
68078d5c
DR		 1855 return err;
1856}
1857
66ec6d59
SRT		 1858/**
1859 * ufshcd_query_attr - API function for sending attribute requests
1860 * hba: per-adapter instance
1861 * opcode: attribute opcode
1862 * idn: attribute idn to access
1863 * index: index field
1864 * selector: selector field
1865 * attr_val: the attribute value after the query request completes
1866 *
1867 * Returns 0 for success, non-zero in case of failure
1868*/
bdbe5d2f 1869static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1870 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1871{
d44a5f98
DR		 1872 struct ufs_query_req *request = NULL;
1873 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1874 int err;
1875
1876 BUG_ON(!hba);
1877
1ab27c9c 1878 ufshcd_hold(hba, false);
66ec6d59
SRT		 1879 if (!attr_val) {
1880 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1881 __func__, opcode);
1882 err = -EINVAL;
1883 goto out;
1884 }
1885
1886 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1887 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1888 selector);
66ec6d59
SRT		 1889
1890 switch (opcode) {
1891 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1892 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1893 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1894 break;
1895 case UPIU_QUERY_OPCODE_READ_ATTR:
1896 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1897 break;
1898 default:
1899 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1900 __func__, opcode);
1901 err = -EINVAL;
1902 goto out_unlock;
1903 }
1904
d44a5f98 1905 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1906
1907 if (err) {
4b761b58
YG		 1908 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1909 __func__, opcode, idn, index, err);
66ec6d59
SRT		 1910 goto out_unlock;
1911 }
1912
e8c8e82a 1913 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1914
1915out_unlock:
1916 mutex_unlock(&hba->dev_cmd.lock);
1917out:
1ab27c9c 1918 ufshcd_release(hba);
66ec6d59
SRT		 1919 return err;
1920}
1921
5e86ae44
YG		 1922/**
1923 * ufshcd_query_attr_retry() - API function for sending query
1924 * attribute with retries
1925 * @hba: per-adapter instance
1926 * @opcode: attribute opcode
1927 * @idn: attribute idn to access
1928 * @index: index field
1929 * @selector: selector field
1930 * @attr_val: the attribute value after the query request
1931 * completes
1932 *
1933 * Returns 0 for success, non-zero in case of failure
1934*/
1935static int ufshcd_query_attr_retry(struct ufs_hba *hba,
1936 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1937 u32 *attr_val)
1938{
1939 int ret = 0;
1940 u32 retries;
1941
1942 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1943 ret = ufshcd_query_attr(hba, opcode, idn, index,
1944 selector, attr_val);
1945 if (ret)
1946 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
1947 __func__, ret, retries);
1948 else
1949 break;
1950 }
1951
1952 if (ret)
1953 dev_err(hba->dev,
1954 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
1955 __func__, idn, ret, QUERY_REQ_RETRIES);
1956 return ret;
1957}
1958
a70e91b8 1959static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1960 enum query_opcode opcode, enum desc_idn idn, u8 index,
1961 u8 selector, u8 *desc_buf, int *buf_len)
1962{
1963 struct ufs_query_req *request = NULL;
1964 struct ufs_query_res *response = NULL;
1965 int err;
1966
1967 BUG_ON(!hba);
1968
1ab27c9c 1969 ufshcd_hold(hba, false);
d44a5f98
DR		 1970 if (!desc_buf) {
1971 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1972 __func__, opcode);
1973 err = -EINVAL;
1974 goto out;
1975 }
1976
1977 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1978 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1979 __func__, *buf_len);
1980 err = -EINVAL;
1981 goto out;
1982 }
1983
1984 mutex_lock(&hba->dev_cmd.lock);
1985 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1986 selector);
1987 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1988 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1989
1990 switch (opcode) {
1991 case UPIU_QUERY_OPCODE_WRITE_DESC:
1992 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1993 break;
1994 case UPIU_QUERY_OPCODE_READ_DESC:
1995 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1996 break;
1997 default:
1998 dev_err(hba->dev,
1999 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2000 __func__, opcode);
2001 err = -EINVAL;
2002 goto out_unlock;
2003 }
2004
2005 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2006
2007 if (err) {
4b761b58
YG		 2008 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2009 __func__, opcode, idn, index, err);
d44a5f98
DR		 2010 goto out_unlock;
2011 }
2012
2013 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2014 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2015
2016out_unlock:
2017 mutex_unlock(&hba->dev_cmd.lock);
2018out:
1ab27c9c 2019 ufshcd_release(hba);
d44a5f98
DR		 2020 return err;
2021}
2022
a70e91b8
YG		 2023/**
2024 * ufshcd_query_descriptor_retry - API function for sending descriptor
2025 * requests
2026 * hba: per-adapter instance
2027 * opcode: attribute opcode
2028 * idn: attribute idn to access
2029 * index: index field
2030 * selector: selector field
2031 * desc_buf: the buffer that contains the descriptor
2032 * buf_len: length parameter passed to the device
2033 *
2034 * Returns 0 for success, non-zero in case of failure.
2035 * The buf_len parameter will contain, on return, the length parameter
2036 * received on the response.
2037 */
2038int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2039 enum query_opcode opcode, enum desc_idn idn, u8 index,
2040 u8 selector, u8 *desc_buf, int *buf_len)
2041{
2042 int err;
2043 int retries;
2044
2045 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2046 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2047 selector, desc_buf, buf_len);
2048 if (!err || err == -EINVAL)
2049 break;
2050 }
2051
2052 return err;
2053}
2054EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2055
da461cec
SJ		 2056/**
2057 * ufshcd_read_desc_param - read the specified descriptor parameter
2058 * @hba: Pointer to adapter instance
2059 * @desc_id: descriptor idn value
2060 * @desc_index: descriptor index
2061 * @param_offset: offset of the parameter to read
2062 * @param_read_buf: pointer to buffer where parameter would be read
2063 * @param_size: sizeof(param_read_buf)
2064 *
2065 * Return 0 in case of success, non-zero otherwise
2066 */
2067static int ufshcd_read_desc_param(struct ufs_hba *hba,
2068 enum desc_idn desc_id,
2069 int desc_index,
2070 u32 param_offset,
2071 u8 *param_read_buf,
2072 u32 param_size)
2073{
2074 int ret;
2075 u8 *desc_buf;
2076 u32 buff_len;
2077 bool is_kmalloc = true;
2078
2079 /* safety checks */
2080 if (desc_id >= QUERY_DESC_IDN_MAX)
2081 return -EINVAL;
2082
2083 buff_len = ufs_query_desc_max_size[desc_id];
2084 if ((param_offset + param_size) > buff_len)
2085 return -EINVAL;
2086
2087 if (!param_offset && (param_size == buff_len)) {
2088 /* memory space already available to hold full descriptor */
2089 desc_buf = param_read_buf;
2090 is_kmalloc = false;
2091 } else {
2092 /* allocate memory to hold full descriptor */
2093 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2094 if (!desc_buf)
2095 return -ENOMEM;
2096 }
2097
a70e91b8
YG		 2098 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2099 desc_id, desc_index, 0, desc_buf,
2100 &buff_len);
da461cec 2101
bde44bb6 2102 if (ret) {
2103 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2104 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 2105
2106 goto out;
2107 }
2108
bde44bb6 2109 /* Sanity check */
2110 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2111 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2112 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2113 ret = -EINVAL;
2114 goto out;
2115 }
2116
2117 /*
2118 * While reading variable size descriptors (like string descriptor),
2119 * some UFS devices may report the "LENGTH" (field in "Transaction
2120 * Specific fields" of Query Response UPIU) same as what was requested
2121 * in Query Request UPIU instead of reporting the actual size of the
2122 * variable size descriptor.
2123 * Although it's safe to ignore the "LENGTH" field for variable size
2124 * descriptors as we can always derive the length of the descriptor from
2125 * the descriptor header fields. Hence this change impose the length
2126 * match check only for fixed size descriptors (for which we always
2127 * request the correct size as part of Query Request UPIU).
2128 */
2129 if ((desc_id != QUERY_DESC_IDN_STRING) &&
2130 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
2131 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
2132 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
2133 ret = -EINVAL;
2134 goto out;
2135 }
2136
da461cec
SJ		 2137 if (is_kmalloc)
2138 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2139out:
2140 if (is_kmalloc)
2141 kfree(desc_buf);
2142 return ret;
2143}
2144
2145static inline int ufshcd_read_desc(struct ufs_hba *hba,
2146 enum desc_idn desc_id,
2147 int desc_index,
2148 u8 *buf,
2149 u32 size)
2150{
2151 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2152}
2153
2154static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2155 u8 *buf,
2156 u32 size)
2157{
61e07359
DR		 2158 int err = 0;
2159 int retries;
2160
2161 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2162 /* Read descriptor*/
2163 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2164 if (!err)
2165 break;
2166 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2167 }
2168
2169 return err;
da461cec
SJ		 2170}
2171
b573d484
YG		 2172int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2173{
2174 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2175}
2176EXPORT_SYMBOL(ufshcd_read_device_desc);
2177
2178/**
2179 * ufshcd_read_string_desc - read string descriptor
2180 * @hba: pointer to adapter instance
2181 * @desc_index: descriptor index
2182 * @buf: pointer to buffer where descriptor would be read
2183 * @size: size of buf
2184 * @ascii: if true convert from unicode to ascii characters
2185 *
2186 * Return 0 in case of success, non-zero otherwise
2187 */
2188int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2189 u32 size, bool ascii)
2190{
2191 int err = 0;
2192
2193 err = ufshcd_read_desc(hba,
2194 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2195
2196 if (err) {
2197 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2198 __func__, QUERY_REQ_RETRIES, err);
2199 goto out;
2200 }
2201
2202 if (ascii) {
2203 int desc_len;
2204 int ascii_len;
2205 int i;
2206 char *buff_ascii;
2207
2208 desc_len = buf[0];
2209 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2210 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2211 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2212 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2213 __func__);
2214 err = -ENOMEM;
2215 goto out;
2216 }
2217
2218 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2219 if (!buff_ascii) {
2220 err = -ENOMEM;
fcbefc3b 2221 goto out;
b573d484
YG		 2222 }
2223
2224 /*
2225 * the descriptor contains string in UTF16 format
2226 * we need to convert to utf-8 so it can be displayed
2227 */
2228 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2229 desc_len - QUERY_DESC_HDR_SIZE,
2230 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2231
2232 /* replace non-printable or non-ASCII characters with spaces */
2233 for (i = 0; i < ascii_len; i++)
2234 ufshcd_remove_non_printable(&buff_ascii[i]);
2235
2236 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2237 size - QUERY_DESC_HDR_SIZE);
2238 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2239 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 2240 kfree(buff_ascii);
2241 }
2242out:
2243 return err;
2244}
2245EXPORT_SYMBOL(ufshcd_read_string_desc);
2246
da461cec
SJ		 2247/**
2248 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2249 * @hba: Pointer to adapter instance
2250 * @lun: lun id
2251 * @param_offset: offset of the parameter to read
2252 * @param_read_buf: pointer to buffer where parameter would be read
2253 * @param_size: sizeof(param_read_buf)
2254 *
2255 * Return 0 in case of success, non-zero otherwise
2256 */
2257static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2258 int lun,
2259 enum unit_desc_param param_offset,
2260 u8 *param_read_buf,
2261 u32 param_size)
2262{
2263 /*
2264 * Unit descriptors are only available for general purpose LUs (LUN id
2265 * from 0 to 7) and RPMB Well known LU.
2266 */
0ce147d4 2267 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 2268 return -EOPNOTSUPP;
2269
2270 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2271 param_offset, param_read_buf, param_size);
2272}
2273
7a3e97b0
SY		 2274/**
2275 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2276 * @hba: per adapter instance
2277 *
2278 * 1. Allocate DMA memory for Command Descriptor array
2279 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2280 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2281 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2282 * (UTMRDL)
2283 * 4. Allocate memory for local reference block(lrb).
2284 *
2285 * Returns 0 for success, non-zero in case of failure
2286 */
2287static int ufshcd_memory_alloc(struct ufs_hba *hba)
2288{
2289 size_t utmrdl_size, utrdl_size, ucdl_size;
2290
2291 /* Allocate memory for UTP command descriptors */
2292 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 2293 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2294 ucdl_size,
2295 &hba->ucdl_dma_addr,
2296 GFP_KERNEL);
7a3e97b0
SY		 2297
2298 /*
2299 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2300 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2301 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2302 * be aligned to 128 bytes as well
2303 */
2304 if (!hba->ucdl_base_addr ||
2305 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2306 dev_err(hba->dev,
7a3e97b0
SY		 2307 "Command Descriptor Memory allocation failed\n");
2308 goto out;
2309 }
2310
2311 /*
2312 * Allocate memory for UTP Transfer descriptors
2313 * UFSHCI requires 1024 byte alignment of UTRD
2314 */
2315 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2316 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2317 utrdl_size,
2318 &hba->utrdl_dma_addr,
2319 GFP_KERNEL);
7a3e97b0
SY		 2320 if (!hba->utrdl_base_addr ||
2321 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2322 dev_err(hba->dev,
7a3e97b0
SY		 2323 "Transfer Descriptor Memory allocation failed\n");
2324 goto out;
2325 }
2326
2327 /*
2328 * Allocate memory for UTP Task Management descriptors
2329 * UFSHCI requires 1024 byte alignment of UTMRD
2330 */
2331 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2332 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2333 utmrdl_size,
2334 &hba->utmrdl_dma_addr,
2335 GFP_KERNEL);
7a3e97b0
SY		 2336 if (!hba->utmrdl_base_addr ||
2337 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2338 dev_err(hba->dev,
7a3e97b0
SY		 2339 "Task Management Descriptor Memory allocation failed\n");
2340 goto out;
2341 }
2342
2343 /* Allocate memory for local reference block */
2953f850
SJ		 2344 hba->lrb = devm_kzalloc(hba->dev,
2345 hba->nutrs * sizeof(struct ufshcd_lrb),
2346 GFP_KERNEL);
7a3e97b0 2347 if (!hba->lrb) {
3b1d0580 2348 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2349 goto out;
2350 }
2351 return 0;
2352out:
7a3e97b0
SY		 2353 return -ENOMEM;
2354}
2355
2356/**
2357 * ufshcd_host_memory_configure - configure local reference block with
2358 * memory offsets
2359 * @hba: per adapter instance
2360 *
2361 * Configure Host memory space
2362 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2363 * address.
2364 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2365 * and PRDT offset.
2366 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2367 * into local reference block.
2368 */
2369static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2370{
2371 struct utp_transfer_cmd_desc *cmd_descp;
2372 struct utp_transfer_req_desc *utrdlp;
2373 dma_addr_t cmd_desc_dma_addr;
2374 dma_addr_t cmd_desc_element_addr;
2375 u16 response_offset;
2376 u16 prdt_offset;
2377 int cmd_desc_size;
2378 int i;
2379
2380 utrdlp = hba->utrdl_base_addr;
2381 cmd_descp = hba->ucdl_base_addr;
2382
2383 response_offset =
2384 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2385 prdt_offset =
2386 offsetof(struct utp_transfer_cmd_desc, prd_table);
2387
2388 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2389 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2390
2391 for (i = 0; i < hba->nutrs; i++) {
2392 /* Configure UTRD with command descriptor base address */
2393 cmd_desc_element_addr =
2394 (cmd_desc_dma_addr + (cmd_desc_size * i));
2395 utrdlp[i].command_desc_base_addr_lo =
2396 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2397 utrdlp[i].command_desc_base_addr_hi =
2398 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2399
2400 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 2401 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
2402 utrdlp[i].response_upiu_offset =
2403 cpu_to_le16(response_offset);
2404 utrdlp[i].prd_table_offset =
2405 cpu_to_le16(prdt_offset);
2406 utrdlp[i].response_upiu_length =
2407 cpu_to_le16(ALIGNED_UPIU_SIZE);
2408 } else {
2409 utrdlp[i].response_upiu_offset =
7a3e97b0 2410 cpu_to_le16((response_offset >> 2));
75b1cc4a 2411 utrdlp[i].prd_table_offset =
7a3e97b0 2412 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 2413 utrdlp[i].response_upiu_length =
3ca316c5 2414 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 2415 }
7a3e97b0
SY		 2416
2417 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2418 hba->lrb[i].ucd_req_ptr =
2419 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2420 hba->lrb[i].ucd_rsp_ptr =
2421 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2422 hba->lrb[i].ucd_prdt_ptr =
2423 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2424 }
2425}
2426
2427/**
2428 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2429 * @hba: per adapter instance
2430 *
2431 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2432 * in order to initialize the Unipro link startup procedure.
2433 * Once the Unipro links are up, the device connected to the controller
2434 * is detected.
2435 *
2436 * Returns 0 on success, non-zero value on failure
2437 */
2438static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2439{
6ccf44fe
SJ		 2440 struct uic_command uic_cmd = {0};
2441 int ret;
7a3e97b0 2442
6ccf44fe 2443 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2444
6ccf44fe
SJ		 2445 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2446 if (ret)
2447 dev_err(hba->dev,
2448 "dme-link-startup: error code %d\n", ret);
2449 return ret;
7a3e97b0
SY		 2450}
2451
cad2e03d
YG		 2452static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2453{
2454 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2455 unsigned long min_sleep_time_us;
2456
2457 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2458 return;
2459
2460 /*
2461 * last_dme_cmd_tstamp will be 0 only for 1st call to
2462 * this function
2463 */
2464 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2465 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2466 } else {
2467 unsigned long delta =
2468 (unsigned long) ktime_to_us(
2469 ktime_sub(ktime_get(),
2470 hba->last_dme_cmd_tstamp));
2471
2472 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2473 min_sleep_time_us =
2474 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2475 else
2476 return; /* no more delay required */
2477 }
2478
2479 /* allow sleep for extra 50us if needed */
2480 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2481}
2482
12b4fdb4
SJ		 2483/**
2484 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2485 * @hba: per adapter instance
2486 * @attr_sel: uic command argument1
2487 * @attr_set: attribute set type as uic command argument2
2488 * @mib_val: setting value as uic command argument3
2489 * @peer: indicate whether peer or local
2490 *
2491 * Returns 0 on success, non-zero value on failure
2492 */
2493int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2494 u8 attr_set, u32 mib_val, u8 peer)
2495{
2496 struct uic_command uic_cmd = {0};
2497 static const char *const action[] = {
2498 "dme-set",
2499 "dme-peer-set"
2500 };
2501 const char *set = action[!!peer];
2502 int ret;
64238fbd 2503 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 2504
2505 uic_cmd.command = peer ?
2506 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2507 uic_cmd.argument1 = attr_sel;
2508 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2509 uic_cmd.argument3 = mib_val;
2510
64238fbd
YG		 2511 do {
2512 /* for peer attributes we retry upon failure */
2513 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2514 if (ret)
2515 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2516 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2517 } while (ret && peer && --retries);
2518
2519 if (!retries)
2520 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
2521 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2522 retries);
12b4fdb4
SJ		 2523
2524 return ret;
2525}
2526EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2527
2528/**
2529 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2530 * @hba: per adapter instance
2531 * @attr_sel: uic command argument1
2532 * @mib_val: the value of the attribute as returned by the UIC command
2533 * @peer: indicate whether peer or local
2534 *
2535 * Returns 0 on success, non-zero value on failure
2536 */
2537int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2538 u32 *mib_val, u8 peer)
2539{
2540 struct uic_command uic_cmd = {0};
2541 static const char *const action[] = {
2542 "dme-get",
2543 "dme-peer-get"
2544 };
2545 const char *get = action[!!peer];
2546 int ret;
64238fbd 2547 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 2548 struct ufs_pa_layer_attr orig_pwr_info;
2549 struct ufs_pa_layer_attr temp_pwr_info;
2550 bool pwr_mode_change = false;
2551
2552 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2553 orig_pwr_info = hba->pwr_info;
2554 temp_pwr_info = orig_pwr_info;
2555
2556 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2557 orig_pwr_info.pwr_rx == FAST_MODE) {
2558 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2559 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2560 pwr_mode_change = true;
2561 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2562 orig_pwr_info.pwr_rx == SLOW_MODE) {
2563 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2564 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2565 pwr_mode_change = true;
2566 }
2567 if (pwr_mode_change) {
2568 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2569 if (ret)
2570 goto out;
2571 }
2572 }
12b4fdb4
SJ		 2573
2574 uic_cmd.command = peer ?
2575 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2576 uic_cmd.argument1 = attr_sel;
2577
64238fbd
YG		 2578 do {
2579 /* for peer attributes we retry upon failure */
2580 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2581 if (ret)
2582 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2583 get, UIC_GET_ATTR_ID(attr_sel), ret);
2584 } while (ret && peer && --retries);
2585
2586 if (!retries)
2587 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
2588 get, UIC_GET_ATTR_ID(attr_sel), retries);
12b4fdb4 2589
64238fbd 2590 if (mib_val && !ret)
12b4fdb4 2591 *mib_val = uic_cmd.argument3;
874237f7
YG		 2592
2593 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2594 && pwr_mode_change)
2595 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2596out:
2597 return ret;
2598}
2599EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2600
53b3d9c3 2601/**
57d104c1
SJ		 2602 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2603 * state) and waits for it to take effect.
2604 *
53b3d9c3 2605 * @hba: per adapter instance
57d104c1
SJ		 2606 * @cmd: UIC command to execute
2607 *
2608 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2609 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2610 * and device UniPro link and hence it's final completion would be indicated by
2611 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2612 * addition to normal UIC command completion Status (UCCS). This function only
2613 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2614 *
2615 * Returns 0 on success, non-zero value on failure
2616 */
57d104c1 2617static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2618{
57d104c1 2619 struct completion uic_async_done;
53b3d9c3
SJ		 2620 unsigned long flags;
2621 u8 status;
2622 int ret;
d75f7fe4 2623 bool reenable_intr = false;
53b3d9c3 2624
53b3d9c3 2625 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2626 init_completion(&uic_async_done);
cad2e03d 2627 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2628
2629 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2630 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 2631 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2632 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2633 /*
2634 * Make sure UIC command completion interrupt is disabled before
2635 * issuing UIC command.
2636 */
2637 wmb();
2638 reenable_intr = true;
57d104c1 2639 }
d75f7fe4
YG		 2640 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2641 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 2642 if (ret) {
2643 dev_err(hba->dev,
2644 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2645 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2646 goto out;
2647 }
2648
57d104c1 2649 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2650 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2651 dev_err(hba->dev,
57d104c1
SJ		 2652 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2653 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2654 ret = -ETIMEDOUT;
2655 goto out;
2656 }
2657
2658 status = ufshcd_get_upmcrs(hba);
2659 if (status != PWR_LOCAL) {
2660 dev_err(hba->dev,
73615428 2661 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2662 cmd->command, status);
53b3d9c3
SJ		 2663 ret = (status != PWR_OK) ? status : -1;
2664 }
2665out:
2666 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2667 hba->active_uic_cmd = NULL;
57d104c1 2668 hba->uic_async_done = NULL;
d75f7fe4
YG		 2669 if (reenable_intr)
2670 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 2671 spin_unlock_irqrestore(hba->host->host_lock, flags);
2672 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2673
53b3d9c3
SJ		 2674 return ret;
2675}
2676
57d104c1
SJ		 2677/**
2678 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2679 * using DME_SET primitives.
2680 * @hba: per adapter instance
2681 * @mode: powr mode value
2682 *
2683 * Returns 0 on success, non-zero value on failure
2684 */
2685static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2686{
2687 struct uic_command uic_cmd = {0};
1ab27c9c 2688 int ret;
57d104c1 2689
c3a2f9ee
YG		 2690 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2691 ret = ufshcd_dme_set(hba,
2692 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2693 if (ret) {
2694 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2695 __func__, ret);
2696 goto out;
2697 }
2698 }
2699
57d104c1
SJ		 2700 uic_cmd.command = UIC_CMD_DME_SET;
2701 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2702 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2703 ufshcd_hold(hba, false);
2704 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2705 ufshcd_release(hba);
57d104c1 2706
c3a2f9ee 2707out:
1ab27c9c 2708 return ret;
57d104c1
SJ		 2709}
2710
53c12d0e
YG		 2711static int ufshcd_link_recovery(struct ufs_hba *hba)
2712{
2713 int ret;
2714 unsigned long flags;
2715
2716 spin_lock_irqsave(hba->host->host_lock, flags);
2717 hba->ufshcd_state = UFSHCD_STATE_RESET;
2718 ufshcd_set_eh_in_progress(hba);
2719 spin_unlock_irqrestore(hba->host->host_lock, flags);
2720
2721 ret = ufshcd_host_reset_and_restore(hba);
2722
2723 spin_lock_irqsave(hba->host->host_lock, flags);
2724 if (ret)
2725 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2726 ufshcd_clear_eh_in_progress(hba);
2727 spin_unlock_irqrestore(hba->host->host_lock, flags);
2728
2729 if (ret)
2730 dev_err(hba->dev, "%s: link recovery failed, err %d",
2731 __func__, ret);
2732
2733 return ret;
2734}
2735
87d0b4a6 2736static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 2737{
87d0b4a6 2738 int ret;
57d104c1
SJ		 2739 struct uic_command uic_cmd = {0};
2740
ee32c909
KK		 2741 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
2742
57d104c1 2743 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG		 2744 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2745
53c12d0e 2746 if (ret) {
87d0b4a6
YG		 2747 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
2748 __func__, ret);
2749
53c12d0e
YG		 2750 /*
2751 * If link recovery fails then return error so that caller
2752 * don't retry the hibern8 enter again.
2753 */
2754 if (ufshcd_link_recovery(hba))
2755 ret = -ENOLINK;
ee32c909
KK		 2756 } else
2757 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
2758 POST_CHANGE);
53c12d0e 2759
87d0b4a6
YG		 2760 return ret;
2761}
2762
2763static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2764{
2765 int ret = 0, retries;
57d104c1 2766
87d0b4a6
YG		 2767 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
2768 ret = __ufshcd_uic_hibern8_enter(hba);
2769 if (!ret || ret == -ENOLINK)
2770 goto out;
2771 }
2772out:
2773 return ret;
57d104c1
SJ		 2774}
2775
2776static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2777{
2778 struct uic_command uic_cmd = {0};
2779 int ret;
2780
ee32c909
KK		 2781 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
2782
57d104c1
SJ		 2783 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2784 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2785 if (ret) {
53c12d0e
YG		 2786 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
2787 __func__, ret);
2788 ret = ufshcd_link_recovery(hba);
ee32c909
KK		 2789 } else
2790 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
2791 POST_CHANGE);
57d104c1
SJ		 2792
2793 return ret;
2794}
2795
5064636c
YG		 2796 /**
2797 * ufshcd_init_pwr_info - setting the POR (power on reset)
2798 * values in hba power info
2799 * @hba: per-adapter instance
2800 */
2801static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2802{
2803 hba->pwr_info.gear_rx = UFS_PWM_G1;
2804 hba->pwr_info.gear_tx = UFS_PWM_G1;
2805 hba->pwr_info.lane_rx = 1;
2806 hba->pwr_info.lane_tx = 1;
2807 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2808 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2809 hba->pwr_info.hs_rate = 0;
2810}
2811
d3e89bac 2812/**
7eb584db
DR		 2813 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2814 * @hba: per-adapter instance
d3e89bac 2815 */
7eb584db 2816static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2817{
7eb584db
DR		 2818 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2819
2820 if (hba->max_pwr_info.is_valid)
2821 return 0;
2822
2823 pwr_info->pwr_tx = FASTAUTO_MODE;
2824 pwr_info->pwr_rx = FASTAUTO_MODE;
2825 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2826
2827 /* Get the connected lane count */
7eb584db
DR		 2828 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2829 &pwr_info->lane_rx);
2830 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2831 &pwr_info->lane_tx);
2832
2833 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2834 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2835 __func__,
2836 pwr_info->lane_rx,
2837 pwr_info->lane_tx);
2838 return -EINVAL;
2839 }
d3e89bac
SJ		 2840
2841 /*
2842 * First, get the maximum gears of HS speed.
2843 * If a zero value, it means there is no HSGEAR capability.
2844 * Then, get the maximum gears of PWM speed.
2845 */
7eb584db
DR		 2846 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2847 if (!pwr_info->gear_rx) {
2848 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2849 &pwr_info->gear_rx);
2850 if (!pwr_info->gear_rx) {
2851 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2852 __func__, pwr_info->gear_rx);
2853 return -EINVAL;
2854 }
2855 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2856 }
2857
7eb584db
DR		 2858 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2859 &pwr_info->gear_tx);
2860 if (!pwr_info->gear_tx) {
d3e89bac 2861 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2862 &pwr_info->gear_tx);
2863 if (!pwr_info->gear_tx) {
2864 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2865 __func__, pwr_info->gear_tx);
2866 return -EINVAL;
2867 }
2868 pwr_info->pwr_tx = SLOWAUTO_MODE;
2869 }
2870
2871 hba->max_pwr_info.is_valid = true;
2872 return 0;
2873}
2874
2875static int ufshcd_change_power_mode(struct ufs_hba *hba,
2876 struct ufs_pa_layer_attr *pwr_mode)
2877{
2878 int ret;
2879
2880 /* if already configured to the requested pwr_mode */
2881 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2882 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2883 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2884 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2885 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2886 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2887 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2888 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2889 return 0;
d3e89bac
SJ		 2890 }
2891
2892 /*
2893 * Configure attributes for power mode change with below.
2894 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2895 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2896 * - PA_HSSERIES
2897 */
7eb584db
DR		 2898 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2899 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2900 pwr_mode->lane_rx);
2901 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2902 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2903 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2904 else
2905 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2906
7eb584db
DR		 2907 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2908 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2909 pwr_mode->lane_tx);
2910 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2911 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2912 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2913 else
2914 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2915
7eb584db
DR		 2916 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2917 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2918 pwr_mode->pwr_rx == FAST_MODE ||
2919 pwr_mode->pwr_tx == FAST_MODE)
2920 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2921 pwr_mode->hs_rate);
d3e89bac 2922
7eb584db
DR		 2923 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2924 | pwr_mode->pwr_tx);
2925
2926 if (ret) {
d3e89bac 2927 dev_err(hba->dev,
7eb584db
DR		 2928 "%s: power mode change failed %d\n", __func__, ret);
2929 } else {
0263bcd0
YG		 2930 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2931 pwr_mode);
7eb584db
DR		 2932
2933 memcpy(&hba->pwr_info, pwr_mode,
2934 sizeof(struct ufs_pa_layer_attr));
2935 }
2936
2937 return ret;
2938}
2939
2940/**
2941 * ufshcd_config_pwr_mode - configure a new power mode
2942 * @hba: per-adapter instance
2943 * @desired_pwr_mode: desired power configuration
2944 */
2945static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2946 struct ufs_pa_layer_attr *desired_pwr_mode)
2947{
2948 struct ufs_pa_layer_attr final_params = { 0 };
2949 int ret;
2950
0263bcd0
YG		 2951 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2952 desired_pwr_mode, &final_params);
2953
2954 if (ret)
7eb584db
DR		 2955 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2956
2957 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2958
2959 return ret;
2960}
2961
68078d5c
DR		 2962/**
2963 * ufshcd_complete_dev_init() - checks device readiness
2964 * hba: per-adapter instance
2965 *
2966 * Set fDeviceInit flag and poll until device toggles it.
2967 */
2968static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2969{
dc3c8d3a
YG		 2970 int i;
2971 int err;
68078d5c
DR		 2972 bool flag_res = 1;
2973
dc3c8d3a
YG		 2974 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2975 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 2976 if (err) {
2977 dev_err(hba->dev,
2978 "%s setting fDeviceInit flag failed with error %d\n",
2979 __func__, err);
2980 goto out;
2981 }
2982
dc3c8d3a
YG		 2983 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
2984 for (i = 0; i < 1000 && !err && flag_res; i++)
2985 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
2986 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2987
68078d5c
DR		 2988 if (err)
2989 dev_err(hba->dev,
2990 "%s reading fDeviceInit flag failed with error %d\n",
2991 __func__, err);
2992 else if (flag_res)
2993 dev_err(hba->dev,
2994 "%s fDeviceInit was not cleared by the device\n",
2995 __func__);
2996
2997out:
2998 return err;
2999}
3000
7a3e97b0
SY		 3001/**
3002 * ufshcd_make_hba_operational - Make UFS controller operational
3003 * @hba: per adapter instance
3004 *
3005 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3006 * 1. Enable required interrupts
3007 * 2. Configure interrupt aggregation
897efe62 3008 * 3. Program UTRL and UTMRL base address
5c0c28a8 3009 * 4. Configure run-stop-registers
7a3e97b0
SY		 3010 *
3011 * Returns 0 on success, non-zero value on failure
3012 */
3013static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3014{
3015 int err = 0;
3016 u32 reg;
3017
6ccf44fe
SJ		 3018 /* Enable required interrupts */
3019 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3020
3021 /* Configure interrupt aggregation */
b852190e
YG		 3022 if (ufshcd_is_intr_aggr_allowed(hba))
3023 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3024 else
3025 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3026
3027 /* Configure UTRL and UTMRL base address registers */
3028 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3029 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3030 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3031 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3032 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3033 REG_UTP_TASK_REQ_LIST_BASE_L);
3034 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3035 REG_UTP_TASK_REQ_LIST_BASE_H);
3036
897efe62
YG		 3037 /*
3038 * Make sure base address and interrupt setup are updated before
3039 * enabling the run/stop registers below.
3040 */
3041 wmb();
3042
7a3e97b0
SY		 3043 /*
3044 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3045 */
5c0c28a8 3046 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3047 if (!(ufshcd_get_lists_status(reg))) {
3048 ufshcd_enable_run_stop_reg(hba);
3049 } else {
3b1d0580 3050 dev_err(hba->dev,
7a3e97b0
SY		 3051 "Host controller not ready to process requests");
3052 err = -EIO;
3053 goto out;
3054 }
3055
7a3e97b0
SY		 3056out:
3057 return err;
3058}
3059
596585a2
YG		 3060/**
3061 * ufshcd_hba_stop - Send controller to reset state
3062 * @hba: per adapter instance
3063 * @can_sleep: perform sleep or just spin
3064 */
3065static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3066{
3067 int err;
3068
3069 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3070 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3071 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3072 10, 1, can_sleep);
3073 if (err)
3074 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3075}
3076
7a3e97b0
SY		 3077/**
3078 * ufshcd_hba_enable - initialize the controller
3079 * @hba: per adapter instance
3080 *
3081 * The controller resets itself and controller firmware initialization
3082 * sequence kicks off. When controller is ready it will set
3083 * the Host Controller Enable bit to 1.
3084 *
3085 * Returns 0 on success, non-zero value on failure
3086 */
3087static int ufshcd_hba_enable(struct ufs_hba *hba)
3088{
3089 int retry;
3090
3091 /*
3092 * msleep of 1 and 5 used in this function might result in msleep(20),
3093 * but it was necessary to send the UFS FPGA to reset mode during
3094 * development and testing of this driver. msleep can be changed to
3095 * mdelay and retry count can be reduced based on the controller.
3096 */
596585a2 3097 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3098 /* change controller state to "reset state" */
596585a2 3099 ufshcd_hba_stop(hba, true);
7a3e97b0 3100
57d104c1
SJ		 3101 /* UniPro link is disabled at this point */
3102 ufshcd_set_link_off(hba);
3103
0263bcd0 3104 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3105
7a3e97b0
SY		 3106 /* start controller initialization sequence */
3107 ufshcd_hba_start(hba);
3108
3109 /*
3110 * To initialize a UFS host controller HCE bit must be set to 1.
3111 * During initialization the HCE bit value changes from 1->0->1.
3112 * When the host controller completes initialization sequence
3113 * it sets the value of HCE bit to 1. The same HCE bit is read back
3114 * to check if the controller has completed initialization sequence.
3115 * So without this delay the value HCE = 1, set in the previous
3116 * instruction might be read back.
3117 * This delay can be changed based on the controller.
3118 */
3119 msleep(1);
3120
3121 /* wait for the host controller to complete initialization */
3122 retry = 10;
3123 while (ufshcd_is_hba_active(hba)) {
3124 if (retry) {
3125 retry--;
3126 } else {
3b1d0580 3127 dev_err(hba->dev,
7a3e97b0
SY		 3128 "Controller enable failed\n");
3129 return -EIO;
3130 }
3131 msleep(5);
3132 }
5c0c28a8 3133
1d337ec2 3134 /* enable UIC related interrupts */
57d104c1 3135 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3136
0263bcd0 3137 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3138
7a3e97b0
SY		 3139 return 0;
3140}
3141
7ca38cf3
YG		 3142static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3143{
3144 int tx_lanes, i, err = 0;
3145
3146 if (!peer)
3147 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3148 &tx_lanes);
3149 else
3150 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3151 &tx_lanes);
3152 for (i = 0; i < tx_lanes; i++) {
3153 if (!peer)
3154 err = ufshcd_dme_set(hba,
3155 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3156 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3157 0);
3158 else
3159 err = ufshcd_dme_peer_set(hba,
3160 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3161 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3162 0);
3163 if (err) {
3164 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3165 __func__, peer, i, err);
3166 break;
3167 }
3168 }
3169
3170 return err;
3171}
3172
3173static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3174{
3175 return ufshcd_disable_tx_lcc(hba, true);
3176}
3177
7a3e97b0 3178/**
6ccf44fe 3179 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 3180 * @hba: per adapter instance
3181 *
6ccf44fe 3182 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3183 */
6ccf44fe 3184static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3185{
6ccf44fe 3186 int ret;
1d337ec2 3187 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 3188 bool link_startup_again = false;
7a3e97b0 3189
7caf489b 3190 /*
3191 * If UFS device isn't active then we will have to issue link startup
3192 * 2 times to make sure the device state move to active.
3193 */
3194 if (!ufshcd_is_ufs_dev_active(hba))
3195 link_startup_again = true;
3196
3197link_startup:
1d337ec2 3198 do {
0263bcd0 3199 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3200
1d337ec2 3201 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3202
1d337ec2
SRT		 3203 /* check if device is detected by inter-connect layer */
3204 if (!ret && !ufshcd_is_device_present(hba)) {
3205 dev_err(hba->dev, "%s: Device not present\n", __func__);
3206 ret = -ENXIO;
3207 goto out;
3208 }
6ccf44fe 3209
1d337ec2
SRT		 3210 /*
3211 * DME link lost indication is only received when link is up,
3212 * but we can't be sure if the link is up until link startup
3213 * succeeds. So reset the local Uni-Pro and try again.
3214 */
3215 if (ret && ufshcd_hba_enable(hba))
3216 goto out;
3217 } while (ret && retries--);
3218
3219 if (ret)
3220 /* failed to get the link up... retire */
5c0c28a8 3221 goto out;
5c0c28a8 3222
7caf489b 3223 if (link_startup_again) {
3224 link_startup_again = false;
3225 retries = DME_LINKSTARTUP_RETRIES;
3226 goto link_startup;
3227 }
3228
7ca38cf3
YG		 3229 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3230 ret = ufshcd_disable_device_tx_lcc(hba);
3231 if (ret)
3232 goto out;
3233 }
3234
5c0c28a8 3235 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 3236 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3237 if (ret)
3238 goto out;
7a3e97b0 3239
5c0c28a8 3240 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 3241out:
3242 if (ret)
3243 dev_err(hba->dev, "link startup failed %d\n", ret);
3244 return ret;
7a3e97b0
SY		 3245}
3246
5a0b0cb9
SRT		 3247/**
3248 * ufshcd_verify_dev_init() - Verify device initialization
3249 * @hba: per-adapter instance
3250 *
3251 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3252 * device Transport Protocol (UTP) layer is ready after a reset.
3253 * If the UTP layer at the device side is not initialized, it may
3254 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3255 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3256 */
3257static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3258{
3259 int err = 0;
3260 int retries;
3261
1ab27c9c 3262 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 3263 mutex_lock(&hba->dev_cmd.lock);
3264 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3265 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3266 NOP_OUT_TIMEOUT);
3267
3268 if (!err || err == -ETIMEDOUT)
3269 break;
3270
3271 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3272 }
3273 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3274 ufshcd_release(hba);
5a0b0cb9
SRT		 3275
3276 if (err)
3277 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3278 return err;
3279}
3280
0ce147d4
SJ		 3281/**
3282 * ufshcd_set_queue_depth - set lun queue depth
3283 * @sdev: pointer to SCSI device
3284 *
3285 * Read bLUQueueDepth value and activate scsi tagged command
3286 * queueing. For WLUN, queue depth is set to 1. For best-effort
3287 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3288 * value that host can queue.
3289 */
3290static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3291{
3292 int ret = 0;
3293 u8 lun_qdepth;
61e07359 3294 int retries;
0ce147d4
SJ		 3295 struct ufs_hba *hba;
3296
3297 hba = shost_priv(sdev->host);
3298
3299 lun_qdepth = hba->nutrs;
61e07359
DR		 3300 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3301 /* Read descriptor*/
3302 ret = ufshcd_read_unit_desc_param(hba,
3303 ufshcd_scsi_to_upiu_lun(sdev->lun),
3304 UNIT_DESC_PARAM_LU_Q_DEPTH,
3305 &lun_qdepth,
3306 sizeof(lun_qdepth));
3307 if (!ret || ret == -ENOTSUPP)
3308 break;
3309
3310 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
3311 }
0ce147d4
SJ		 3312
3313 /* Some WLUN doesn't support unit descriptor */
3314 if (ret == -EOPNOTSUPP)
3315 lun_qdepth = 1;
3316 else if (!lun_qdepth)
3317 /* eventually, we can figure out the real queue depth */
3318 lun_qdepth = hba->nutrs;
3319 else
3320 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3321
3322 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3323 __func__, lun_qdepth);
db5ed4df 3324 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 3325}
3326
57d104c1
SJ		 3327/*
3328 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3329 * @hba: per-adapter instance
3330 * @lun: UFS device lun id
3331 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3332 *
3333 * Returns 0 in case of success and b_lu_write_protect status would be returned
3334 * @b_lu_write_protect parameter.
3335 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3336 * Returns -EINVAL in case of invalid parameters passed to this function.
3337 */
3338static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3339 u8 lun,
3340 u8 *b_lu_write_protect)
3341{
3342 int ret;
3343
3344 if (!b_lu_write_protect)
3345 ret = -EINVAL;
3346 /*
3347 * According to UFS device spec, RPMB LU can't be write
3348 * protected so skip reading bLUWriteProtect parameter for
3349 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3350 */
3351 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3352 ret = -ENOTSUPP;
3353 else
3354 ret = ufshcd_read_unit_desc_param(hba,
3355 lun,
3356 UNIT_DESC_PARAM_LU_WR_PROTECT,
3357 b_lu_write_protect,
3358 sizeof(*b_lu_write_protect));
3359 return ret;
3360}
3361
3362/**
3363 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3364 * status
3365 * @hba: per-adapter instance
3366 * @sdev: pointer to SCSI device
3367 *
3368 */
3369static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3370 struct scsi_device *sdev)
3371{
3372 if (hba->dev_info.f_power_on_wp_en &&
3373 !hba->dev_info.is_lu_power_on_wp) {
3374 u8 b_lu_write_protect;
3375
3376 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3377 &b_lu_write_protect) &&
3378 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3379 hba->dev_info.is_lu_power_on_wp = true;
3380 }
3381}
3382
7a3e97b0
SY		 3383/**
3384 * ufshcd_slave_alloc - handle initial SCSI device configurations
3385 * @sdev: pointer to SCSI device
3386 *
3387 * Returns success
3388 */
3389static int ufshcd_slave_alloc(struct scsi_device *sdev)
3390{
3391 struct ufs_hba *hba;
3392
3393 hba = shost_priv(sdev->host);
7a3e97b0
SY		 3394
3395 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3396 sdev->use_10_for_ms = 1;
7a3e97b0 3397
e8e7f271
SRT		 3398 /* allow SCSI layer to restart the device in case of errors */
3399 sdev->allow_restart = 1;
4264fd61 3400
b2a6c522
SRT		 3401 /* REPORT SUPPORTED OPERATION CODES is not supported */
3402 sdev->no_report_opcodes = 1;
3403
e8e7f271 3404
0ce147d4 3405 ufshcd_set_queue_depth(sdev);
4264fd61 3406
57d104c1
SJ		 3407 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3408
7a3e97b0
SY		 3409 return 0;
3410}
3411
4264fd61
SRT		 3412/**
3413 * ufshcd_change_queue_depth - change queue depth
3414 * @sdev: pointer to SCSI device
3415 * @depth: required depth to set
4264fd61 3416 *
db5ed4df 3417 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3418 */
db5ed4df 3419static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 3420{
3421 struct ufs_hba *hba = shost_priv(sdev->host);
3422
3423 if (depth > hba->nutrs)
3424 depth = hba->nutrs;
db5ed4df 3425 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3426}
3427
eeda4749
AM		 3428/**
3429 * ufshcd_slave_configure - adjust SCSI device configurations
3430 * @sdev: pointer to SCSI device
3431 */
3432static int ufshcd_slave_configure(struct scsi_device *sdev)
3433{
3434 struct request_queue *q = sdev->request_queue;
3435
3436 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3437 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3438
3439 return 0;
3440}
3441
7a3e97b0
SY		 3442/**
3443 * ufshcd_slave_destroy - remove SCSI device configurations
3444 * @sdev: pointer to SCSI device
3445 */
3446static void ufshcd_slave_destroy(struct scsi_device *sdev)
3447{
3448 struct ufs_hba *hba;
3449
3450 hba = shost_priv(sdev->host);
0ce147d4 3451 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3452 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3453 unsigned long flags;
3454
3455 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3456 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3457 spin_unlock_irqrestore(hba->host->host_lock, flags);
3458 }
7a3e97b0
SY		 3459}
3460
3461/**
3462 * ufshcd_task_req_compl - handle task management request completion
3463 * @hba: per adapter instance
3464 * @index: index of the completed request
e2933132 3465 * @resp: task management service response
7a3e97b0 3466 *
e2933132 3467 * Returns non-zero value on error, zero on success
7a3e97b0 3468 */
e2933132 3469static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3470{
3471 struct utp_task_req_desc *task_req_descp;
3472 struct utp_upiu_task_rsp *task_rsp_upiup;
3473 unsigned long flags;
3474 int ocs_value;
3475 int task_result;
3476
3477 spin_lock_irqsave(hba->host->host_lock, flags);
3478
3479 /* Clear completed tasks from outstanding_tasks */
3480 __clear_bit(index, &hba->outstanding_tasks);
3481
3482 task_req_descp = hba->utmrdl_base_addr;
3483 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3484
3485 if (ocs_value == OCS_SUCCESS) {
3486 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3487 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 3488 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3489 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 3490 if (resp)
3491 *resp = (u8)task_result;
7a3e97b0 3492 } else {
e2933132
SRT		 3493 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3494 __func__, ocs_value);
7a3e97b0
SY		 3495 }
3496 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3497
3498 return ocs_value;
7a3e97b0
SY		 3499}
3500
7a3e97b0
SY		 3501/**
3502 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3503 * @lrb: pointer to local reference block of completed command
3504 * @scsi_status: SCSI command status
3505 *
3506 * Returns value base on SCSI command status
3507 */
3508static inline int
3509ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3510{
3511 int result = 0;
3512
3513 switch (scsi_status) {
7a3e97b0 3514 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3515 ufshcd_copy_sense_data(lrbp);
3516 case SAM_STAT_GOOD:
7a3e97b0
SY		 3517 result |= DID_OK << 16 |
3518 COMMAND_COMPLETE << 8 |
1c2623c5 3519 scsi_status;
7a3e97b0
SY		 3520 break;
3521 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3522 case SAM_STAT_BUSY:
7a3e97b0 3523 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3524 ufshcd_copy_sense_data(lrbp);
3525 result |= scsi_status;
7a3e97b0
SY		 3526 break;
3527 default:
3528 result |= DID_ERROR << 16;
3529 break;
3530 } /* end of switch */
3531
3532 return result;
3533}
3534
3535/**
3536 * ufshcd_transfer_rsp_status - Get overall status of the response
3537 * @hba: per adapter instance
3538 * @lrb: pointer to local reference block of completed command
3539 *
3540 * Returns result of the command to notify SCSI midlayer
3541 */
3542static inline int
3543ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3544{
3545 int result = 0;
3546 int scsi_status;
3547 int ocs;
3548
3549 /* overall command status of utrd */
3550 ocs = ufshcd_get_tr_ocs(lrbp);
3551
3552 switch (ocs) {
3553 case OCS_SUCCESS:
5a0b0cb9 3554 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3555
5a0b0cb9
SRT		 3556 switch (result) {
3557 case UPIU_TRANSACTION_RESPONSE:
3558 /*
3559 * get the response UPIU result to extract
3560 * the SCSI command status
3561 */
3562 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3563
3564 /*
3565 * get the result based on SCSI status response
3566 * to notify the SCSI midlayer of the command status
3567 */
3568 scsi_status = result & MASK_SCSI_STATUS;
3569 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3570
f05ac2e5
YG		 3571 /*
3572 * Currently we are only supporting BKOPs exception
3573 * events hence we can ignore BKOPs exception event
3574 * during power management callbacks. BKOPs exception
3575 * event is not expected to be raised in runtime suspend
3576 * callback as it allows the urgent bkops.
3577 * During system suspend, we are anyway forcefully
3578 * disabling the bkops and if urgent bkops is needed
3579 * it will be enabled on system resume. Long term
3580 * solution could be to abort the system suspend if
3581 * UFS device needs urgent BKOPs.
3582 */
3583 if (!hba->pm_op_in_progress &&
3584 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3585 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3586 break;
3587 case UPIU_TRANSACTION_REJECT_UPIU:
3588 /* TODO: handle Reject UPIU Response */
3589 result = DID_ERROR << 16;
3b1d0580 3590 dev_err(hba->dev,
5a0b0cb9
SRT		 3591 "Reject UPIU not fully implemented\n");
3592 break;
3593 default:
3594 result = DID_ERROR << 16;
3595 dev_err(hba->dev,
3596 "Unexpected request response code = %x\n",
3597 result);
7a3e97b0
SY		 3598 break;
3599 }
7a3e97b0
SY		 3600 break;
3601 case OCS_ABORTED:
3602 result |= DID_ABORT << 16;
3603 break;
e8e7f271
SRT		 3604 case OCS_INVALID_COMMAND_STATUS:
3605 result |= DID_REQUEUE << 16;
3606 break;
7a3e97b0
SY		 3607 case OCS_INVALID_CMD_TABLE_ATTR:
3608 case OCS_INVALID_PRDT_ATTR:
3609 case OCS_MISMATCH_DATA_BUF_SIZE:
3610 case OCS_MISMATCH_RESP_UPIU_SIZE:
3611 case OCS_PEER_COMM_FAILURE:
3612 case OCS_FATAL_ERROR:
3613 default:
3614 result |= DID_ERROR << 16;
3b1d0580 3615 dev_err(hba->dev,
7a3e97b0
SY		 3616 "OCS error from controller = %x\n", ocs);
3617 break;
3618 } /* end of switch */
3619
3620 return result;
3621}
3622
6ccf44fe
SJ		 3623/**
3624 * ufshcd_uic_cmd_compl - handle completion of uic command
3625 * @hba: per adapter instance
53b3d9c3 3626 * @intr_status: interrupt status generated by the controller
6ccf44fe 3627 */
53b3d9c3 3628static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3629{
53b3d9c3 3630 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3631 hba->active_uic_cmd->argument2 |=
3632 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3633 hba->active_uic_cmd->argument3 =
3634 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3635 complete(&hba->active_uic_cmd->done);
3636 }
53b3d9c3 3637
57d104c1
SJ		 3638 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3639 complete(hba->uic_async_done);
6ccf44fe
SJ		 3640}
3641
7a3e97b0 3642/**
9a47ec7c 3643 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3644 * @hba: per adapter instance
9a47ec7c 3645 * @completed_reqs: requests to complete
7a3e97b0 3646 */
9a47ec7c
YG		 3647static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3648 unsigned long completed_reqs)
7a3e97b0 3649{
5a0b0cb9
SRT		 3650 struct ufshcd_lrb *lrbp;
3651 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3652 int result;
3653 int index;
e9d501b1 3654
e9d501b1
DR		 3655 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3656 lrbp = &hba->lrb[index];
3657 cmd = lrbp->cmd;
3658 if (cmd) {
3659 result = ufshcd_transfer_rsp_status(hba, lrbp);
3660 scsi_dma_unmap(cmd);
3661 cmd->result = result;
3662 /* Mark completed command as NULL in LRB */
3663 lrbp->cmd = NULL;
3664 clear_bit_unlock(index, &hba->lrb_in_use);
3665 /* Do not touch lrbp after scsi done */
3666 cmd->scsi_done(cmd);
1ab27c9c 3667 __ufshcd_release(hba);
300bb13f
JP		 3668 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3669 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR		 3670 if (hba->dev_cmd.complete)
3671 complete(hba->dev_cmd.complete);
3672 }
3673 }
7a3e97b0
SY		 3674
3675 /* clear corresponding bits of completed commands */
3676 hba->outstanding_reqs ^= completed_reqs;
3677
856b3483
ST		 3678 ufshcd_clk_scaling_update_busy(hba);
3679
5a0b0cb9
SRT		 3680 /* we might have free'd some tags above */
3681 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3682}
3683
9a47ec7c
YG		 3684/**
3685 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3686 * @hba: per adapter instance
3687 */
3688static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3689{
3690 unsigned long completed_reqs;
3691 u32 tr_doorbell;
3692
3693 /* Resetting interrupt aggregation counters first and reading the
3694 * DOOR_BELL afterward allows us to handle all the completed requests.
3695 * In order to prevent other interrupts starvation the DB is read once
3696 * after reset. The down side of this solution is the possibility of
3697 * false interrupt if device completes another request after resetting
3698 * aggregation and before reading the DB.
3699 */
3700 if (ufshcd_is_intr_aggr_allowed(hba))
3701 ufshcd_reset_intr_aggr(hba);
3702
3703 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3704 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3705
3706 __ufshcd_transfer_req_compl(hba, completed_reqs);
3707}
3708
66ec6d59
SRT		 3709/**
3710 * ufshcd_disable_ee - disable exception event
3711 * @hba: per-adapter instance
3712 * @mask: exception event to disable
3713 *
3714 * Disables exception event in the device so that the EVENT_ALERT
3715 * bit is not set.
3716 *
3717 * Returns zero on success, non-zero error value on failure.
3718 */
3719static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3720{
3721 int err = 0;
3722 u32 val;
3723
3724 if (!(hba->ee_ctrl_mask & mask))
3725 goto out;
3726
3727 val = hba->ee_ctrl_mask & ~mask;
3728 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3729 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3730 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3731 if (!err)
3732 hba->ee_ctrl_mask &= ~mask;
3733out:
3734 return err;
3735}
3736
3737/**
3738 * ufshcd_enable_ee - enable exception event
3739 * @hba: per-adapter instance
3740 * @mask: exception event to enable
3741 *
3742 * Enable corresponding exception event in the device to allow
3743 * device to alert host in critical scenarios.
3744 *
3745 * Returns zero on success, non-zero error value on failure.
3746 */
3747static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3748{
3749 int err = 0;
3750 u32 val;
3751
3752 if (hba->ee_ctrl_mask & mask)
3753 goto out;
3754
3755 val = hba->ee_ctrl_mask | mask;
3756 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3757 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3758 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3759 if (!err)
3760 hba->ee_ctrl_mask |= mask;
3761out:
3762 return err;
3763}
3764
3765/**
3766 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3767 * @hba: per-adapter instance
3768 *
3769 * Allow device to manage background operations on its own. Enabling
3770 * this might lead to inconsistent latencies during normal data transfers
3771 * as the device is allowed to manage its own way of handling background
3772 * operations.
3773 *
3774 * Returns zero on success, non-zero on failure.
3775 */
3776static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3777{
3778 int err = 0;
3779
3780 if (hba->auto_bkops_enabled)
3781 goto out;
3782
dc3c8d3a 3783 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 3784 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3785 if (err) {
3786 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3787 __func__, err);
3788 goto out;
3789 }
3790
3791 hba->auto_bkops_enabled = true;
3792
3793 /* No need of URGENT_BKOPS exception from the device */
3794 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3795 if (err)
3796 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3797 __func__, err);
3798out:
3799 return err;
3800}
3801
3802/**
3803 * ufshcd_disable_auto_bkops - block device in doing background operations
3804 * @hba: per-adapter instance
3805 *
3806 * Disabling background operations improves command response latency but
3807 * has drawback of device moving into critical state where the device is
3808 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3809 * host is idle so that BKOPS are managed effectively without any negative
3810 * impacts.
3811 *
3812 * Returns zero on success, non-zero on failure.
3813 */
3814static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3815{
3816 int err = 0;
3817
3818 if (!hba->auto_bkops_enabled)
3819 goto out;
3820
3821 /*
3822 * If host assisted BKOPs is to be enabled, make sure
3823 * urgent bkops exception is allowed.
3824 */
3825 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3826 if (err) {
3827 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3828 __func__, err);
3829 goto out;
3830 }
3831
dc3c8d3a 3832 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 3833 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3834 if (err) {
3835 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3836 __func__, err);
3837 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3838 goto out;
3839 }
3840
3841 hba->auto_bkops_enabled = false;
3842out:
3843 return err;
3844}
3845
3846/**
3847 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3848 * @hba: per adapter instance
3849 *
3850 * After a device reset the device may toggle the BKOPS_EN flag
3851 * to default value. The s/w tracking variables should be updated
3852 * as well. Do this by forcing enable of auto bkops.
3853 */
3854static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3855{
3856 hba->auto_bkops_enabled = false;
3857 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3858 ufshcd_enable_auto_bkops(hba);
3859}
3860
3861static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3862{
5e86ae44 3863 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3864 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3865}
3866
3867/**
57d104c1 3868 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3869 * @hba: per-adapter instance
57d104c1 3870 * @status: bkops_status value
66ec6d59 3871 *
57d104c1
SJ		 3872 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3873 * flag in the device to permit background operations if the device
3874 * bkops_status is greater than or equal to "status" argument passed to
3875 * this function, disable otherwise.
3876 *
3877 * Returns 0 for success, non-zero in case of failure.
3878 *
3879 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3880 * to know whether auto bkops is enabled or disabled after this function
3881 * returns control to it.
66ec6d59 3882 */
57d104c1
SJ		 3883static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3884 enum bkops_status status)
66ec6d59
SRT		 3885{
3886 int err;
57d104c1 3887 u32 curr_status = 0;
66ec6d59 3888
57d104c1 3889 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3890 if (err) {
3891 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3892 __func__, err);
3893 goto out;
57d104c1
SJ		 3894 } else if (curr_status > BKOPS_STATUS_MAX) {
3895 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3896 __func__, curr_status);
3897 err = -EINVAL;
3898 goto out;
66ec6d59
SRT		 3899 }
3900
57d104c1 3901 if (curr_status >= status)
66ec6d59 3902 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3903 else
3904 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3905out:
3906 return err;
3907}
3908
57d104c1
SJ		 3909/**
3910 * ufshcd_urgent_bkops - handle urgent bkops exception event
3911 * @hba: per-adapter instance
3912 *
3913 * Enable fBackgroundOpsEn flag in the device to permit background
3914 * operations.
3915 *
3916 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3917 * and negative error value for any other failure.
3918 */
3919static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3920{
afdfff59 3921 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 3922}
3923
66ec6d59
SRT		 3924static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3925{
5e86ae44 3926 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3927 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3928}
3929
afdfff59
YG		 3930static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
3931{
3932 int err;
3933 u32 curr_status = 0;
3934
3935 if (hba->is_urgent_bkops_lvl_checked)
3936 goto enable_auto_bkops;
3937
3938 err = ufshcd_get_bkops_status(hba, &curr_status);
3939 if (err) {
3940 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3941 __func__, err);
3942 goto out;
3943 }
3944
3945 /*
3946 * We are seeing that some devices are raising the urgent bkops
3947 * exception events even when BKOPS status doesn't indicate performace
3948 * impacted or critical. Handle these device by determining their urgent
3949 * bkops status at runtime.
3950 */
3951 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
3952 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
3953 __func__, curr_status);
3954 /* update the current status as the urgent bkops level */
3955 hba->urgent_bkops_lvl = curr_status;
3956 hba->is_urgent_bkops_lvl_checked = true;
3957 }
3958
3959enable_auto_bkops:
3960 err = ufshcd_enable_auto_bkops(hba);
3961out:
3962 if (err < 0)
3963 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3964 __func__, err);
3965}
3966
66ec6d59
SRT		 3967/**
3968 * ufshcd_exception_event_handler - handle exceptions raised by device
3969 * @work: pointer to work data
3970 *
3971 * Read bExceptionEventStatus attribute from the device and handle the
3972 * exception event accordingly.
3973 */
3974static void ufshcd_exception_event_handler(struct work_struct *work)
3975{
3976 struct ufs_hba *hba;
3977 int err;
3978 u32 status = 0;
3979 hba = container_of(work, struct ufs_hba, eeh_work);
3980
62694735 3981 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3982 err = ufshcd_get_ee_status(hba, &status);
3983 if (err) {
3984 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3985 __func__, err);
3986 goto out;
3987 }
3988
3989 status &= hba->ee_ctrl_mask;
afdfff59
YG		 3990
3991 if (status & MASK_EE_URGENT_BKOPS)
3992 ufshcd_bkops_exception_event_handler(hba);
3993
66ec6d59 3994out:
62694735 3995 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3996 return;
3997}
3998
9a47ec7c
YG		 3999/* Complete requests that have door-bell cleared */
4000static void ufshcd_complete_requests(struct ufs_hba *hba)
4001{
4002 ufshcd_transfer_req_compl(hba);
4003 ufshcd_tmc_handler(hba);
4004}
4005
583fa62d
YG		 4006/**
4007 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4008 * to recover from the DL NAC errors or not.
4009 * @hba: per-adapter instance
4010 *
4011 * Returns true if error handling is required, false otherwise
4012 */
4013static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4014{
4015 unsigned long flags;
4016 bool err_handling = true;
4017
4018 spin_lock_irqsave(hba->host->host_lock, flags);
4019 /*
4020 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4021 * device fatal error and/or DL NAC & REPLAY timeout errors.
4022 */
4023 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4024 goto out;
4025
4026 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4027 ((hba->saved_err & UIC_ERROR) &&
4028 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4029 goto out;
4030
4031 if ((hba->saved_err & UIC_ERROR) &&
4032 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4033 int err;
4034 /*
4035 * wait for 50ms to see if we can get any other errors or not.
4036 */
4037 spin_unlock_irqrestore(hba->host->host_lock, flags);
4038 msleep(50);
4039 spin_lock_irqsave(hba->host->host_lock, flags);
4040
4041 /*
4042 * now check if we have got any other severe errors other than
4043 * DL NAC error?
4044 */
4045 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4046 ((hba->saved_err & UIC_ERROR) &&
4047 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4048 goto out;
4049
4050 /*
4051 * As DL NAC is the only error received so far, send out NOP
4052 * command to confirm if link is still active or not.
4053 * - If we don't get any response then do error recovery.
4054 * - If we get response then clear the DL NAC error bit.
4055 */
4056
4057 spin_unlock_irqrestore(hba->host->host_lock, flags);
4058 err = ufshcd_verify_dev_init(hba);
4059 spin_lock_irqsave(hba->host->host_lock, flags);
4060
4061 if (err)
4062 goto out;
4063
4064 /* Link seems to be alive hence ignore the DL NAC errors */
4065 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
4066 hba->saved_err &= ~UIC_ERROR;
4067 /* clear NAC error */
4068 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4069 if (!hba->saved_uic_err) {
4070 err_handling = false;
4071 goto out;
4072 }
4073 }
4074out:
4075 spin_unlock_irqrestore(hba->host->host_lock, flags);
4076 return err_handling;
4077}
4078
7a3e97b0 4079/**
e8e7f271
SRT		 4080 * ufshcd_err_handler - handle UFS errors that require s/w attention
4081 * @work: pointer to work structure
7a3e97b0 4082 */
e8e7f271 4083static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 4084{
4085 struct ufs_hba *hba;
e8e7f271
SRT		 4086 unsigned long flags;
4087 u32 err_xfer = 0;
4088 u32 err_tm = 0;
4089 int err = 0;
4090 int tag;
9a47ec7c 4091 bool needs_reset = false;
e8e7f271
SRT		 4092
4093 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 4094
62694735 4095 pm_runtime_get_sync(hba->dev);
1ab27c9c 4096 ufshcd_hold(hba, false);
e8e7f271
SRT		 4097
4098 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 4099 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 4100 goto out;
e8e7f271
SRT		 4101
4102 hba->ufshcd_state = UFSHCD_STATE_RESET;
4103 ufshcd_set_eh_in_progress(hba);
4104
4105 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 4106 ufshcd_complete_requests(hba);
583fa62d
YG		 4107
4108 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4109 bool ret;
4110
4111 spin_unlock_irqrestore(hba->host->host_lock, flags);
4112 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
4113 ret = ufshcd_quirk_dl_nac_errors(hba);
4114 spin_lock_irqsave(hba->host->host_lock, flags);
4115 if (!ret)
4116 goto skip_err_handling;
4117 }
9a47ec7c
YG		 4118 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4119 ((hba->saved_err & UIC_ERROR) &&
4120 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4121 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4122 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4123 needs_reset = true;
e8e7f271 4124
9a47ec7c
YG		 4125 /*
4126 * if host reset is required then skip clearing the pending
4127 * transfers forcefully because they will automatically get
4128 * cleared after link startup.
4129 */
4130 if (needs_reset)
4131 goto skip_pending_xfer_clear;
4132
4133 /* release lock as clear command might sleep */
4134 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4135 /* Clear pending transfer requests */
9a47ec7c
YG		 4136 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4137 if (ufshcd_clear_cmd(hba, tag)) {
4138 err_xfer = true;
4139 goto lock_skip_pending_xfer_clear;
4140 }
4141 }
e8e7f271
SRT		 4142
4143 /* Clear pending task management requests */
9a47ec7c
YG		 4144 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4145 if (ufshcd_clear_tm_cmd(hba, tag)) {
4146 err_tm = true;
4147 goto lock_skip_pending_xfer_clear;
4148 }
4149 }
e8e7f271 4150
9a47ec7c 4151lock_skip_pending_xfer_clear:
e8e7f271 4152 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4153
9a47ec7c
YG		 4154 /* Complete the requests that are cleared by s/w */
4155 ufshcd_complete_requests(hba);
4156
4157 if (err_xfer || err_tm)
4158 needs_reset = true;
4159
4160skip_pending_xfer_clear:
e8e7f271 4161 /* Fatal errors need reset */
9a47ec7c
YG		 4162 if (needs_reset) {
4163 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4164
4165 /*
4166 * ufshcd_reset_and_restore() does the link reinitialization
4167 * which will need atleast one empty doorbell slot to send the
4168 * device management commands (NOP and query commands).
4169 * If there is no slot empty at this moment then free up last
4170 * slot forcefully.
4171 */
4172 if (hba->outstanding_reqs == max_doorbells)
4173 __ufshcd_transfer_req_compl(hba,
4174 (1UL << (hba->nutrs - 1)));
4175
4176 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4177 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4178 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 4179 if (err) {
4180 dev_err(hba->dev, "%s: reset and restore failed\n",
4181 __func__);
4182 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4183 }
4184 /*
4185 * Inform scsi mid-layer that we did reset and allow to handle
4186 * Unit Attention properly.
4187 */
4188 scsi_report_bus_reset(hba->host, 0);
4189 hba->saved_err = 0;
4190 hba->saved_uic_err = 0;
4191 }
9a47ec7c 4192
583fa62d 4193skip_err_handling:
9a47ec7c
YG		 4194 if (!needs_reset) {
4195 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4196 if (hba->saved_err || hba->saved_uic_err)
4197 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4198 __func__, hba->saved_err, hba->saved_uic_err);
4199 }
4200
e8e7f271
SRT		 4201 ufshcd_clear_eh_in_progress(hba);
4202
4203out:
9a47ec7c 4204 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4205 scsi_unblock_requests(hba->host);
1ab27c9c 4206 ufshcd_release(hba);
62694735 4207 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 4208}
4209
4210/**
e8e7f271
SRT		 4211 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4212 * @hba: per-adapter instance
7a3e97b0 4213 */
e8e7f271 4214static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 4215{
4216 u32 reg;
4217
e8e7f271
SRT		 4218 /* PA_INIT_ERROR is fatal and needs UIC reset */
4219 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4220 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4221 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 4222 else if (hba->dev_quirks &
4223 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4224 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4225 hba->uic_error |=
4226 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4227 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4228 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4229 }
e8e7f271
SRT		 4230
4231 /* UIC NL/TL/DME errors needs software retry */
4232 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4233 if (reg)
4234 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4235
4236 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4237 if (reg)
4238 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4239
4240 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4241 if (reg)
4242 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4243
4244 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4245 __func__, hba->uic_error);
4246}
4247
4248/**
4249 * ufshcd_check_errors - Check for errors that need s/w attention
4250 * @hba: per-adapter instance
4251 */
4252static void ufshcd_check_errors(struct ufs_hba *hba)
4253{
4254 bool queue_eh_work = false;
4255
7a3e97b0 4256 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4257 queue_eh_work = true;
7a3e97b0
SY		 4258
4259 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 4260 hba->uic_error = 0;
4261 ufshcd_update_uic_error(hba);
4262 if (hba->uic_error)
4263 queue_eh_work = true;
7a3e97b0 4264 }
e8e7f271
SRT		 4265
4266 if (queue_eh_work) {
9a47ec7c
YG		 4267 /*
4268 * update the transfer error masks to sticky bits, let's do this
4269 * irrespective of current ufshcd_state.
4270 */
4271 hba->saved_err |= hba->errors;
4272 hba->saved_uic_err |= hba->uic_error;
4273
e8e7f271
SRT		 4274 /* handle fatal errors only when link is functional */
4275 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4276 /* block commands from scsi mid-layer */
4277 scsi_block_requests(hba->host);
4278
141f8165 4279 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
e8e7f271
SRT		 4280 schedule_work(&hba->eh_work);
4281 }
3441da7d 4282 }
e8e7f271
SRT		 4283 /*
4284 * if (!queue_eh_work) -
4285 * Other errors are either non-fatal where host recovers
4286 * itself without s/w intervention or errors that will be
4287 * handled by the SCSI core layer.
4288 */
7a3e97b0
SY		 4289}
4290
4291/**
4292 * ufshcd_tmc_handler - handle task management function completion
4293 * @hba: per adapter instance
4294 */
4295static void ufshcd_tmc_handler(struct ufs_hba *hba)
4296{
4297 u32 tm_doorbell;
4298
b873a275 4299 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4300 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4301 wake_up(&hba->tm_wq);
7a3e97b0
SY		 4302}
4303
4304/**
4305 * ufshcd_sl_intr - Interrupt service routine
4306 * @hba: per adapter instance
4307 * @intr_status: contains interrupts generated by the controller
4308 */
4309static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4310{
4311 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4312 if (hba->errors)
e8e7f271 4313 ufshcd_check_errors(hba);
7a3e97b0 4314
53b3d9c3
SJ		 4315 if (intr_status & UFSHCD_UIC_MASK)
4316 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 4317
4318 if (intr_status & UTP_TASK_REQ_COMPL)
4319 ufshcd_tmc_handler(hba);
4320
4321 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4322 ufshcd_transfer_req_compl(hba);
4323}
4324
4325/**
4326 * ufshcd_intr - Main interrupt service routine
4327 * @irq: irq number
4328 * @__hba: pointer to adapter instance
4329 *
4330 * Returns IRQ_HANDLED - If interrupt is valid
4331 * IRQ_NONE - If invalid interrupt
4332 */
4333static irqreturn_t ufshcd_intr(int irq, void *__hba)
4334{
d75f7fe4 4335 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 4336 irqreturn_t retval = IRQ_NONE;
4337 struct ufs_hba *hba = __hba;
4338
4339 spin_lock(hba->host->host_lock);
b873a275 4340 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4341 enabled_intr_status =
4342 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4343
d75f7fe4 4344 if (intr_status)
261ea452 4345 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4346
4347 if (enabled_intr_status) {
4348 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 4349 retval = IRQ_HANDLED;
4350 }
4351 spin_unlock(hba->host->host_lock);
4352 return retval;
4353}
4354
e2933132
SRT		 4355static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4356{
4357 int err = 0;
4358 u32 mask = 1 << tag;
4359 unsigned long flags;
4360
4361 if (!test_bit(tag, &hba->outstanding_tasks))
4362 goto out;
4363
4364 spin_lock_irqsave(hba->host->host_lock, flags);
4365 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4366 spin_unlock_irqrestore(hba->host->host_lock, flags);
4367
4368 /* poll for max. 1 sec to clear door bell register by h/w */
4369 err = ufshcd_wait_for_register(hba,
4370 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4371 mask, 0, 1000, 1000, true);
e2933132
SRT		 4372out:
4373 return err;
4374}
4375
7a3e97b0
SY		 4376/**
4377 * ufshcd_issue_tm_cmd - issues task management commands to controller
4378 * @hba: per adapter instance
e2933132
SRT		 4379 * @lun_id: LUN ID to which TM command is sent
4380 * @task_id: task ID to which the TM command is applicable
4381 * @tm_function: task management function opcode
4382 * @tm_response: task management service response return value
7a3e97b0 4383 *
e2933132 4384 * Returns non-zero value on error, zero on success.
7a3e97b0 4385 */
e2933132
SRT		 4386static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4387 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 4388{
4389 struct utp_task_req_desc *task_req_descp;
4390 struct utp_upiu_task_req *task_req_upiup;
4391 struct Scsi_Host *host;
4392 unsigned long flags;
e2933132 4393 int free_slot;
7a3e97b0 4394 int err;
e2933132 4395 int task_tag;
7a3e97b0
SY		 4396
4397 host = hba->host;
4398
e2933132
SRT		 4399 /*
4400 * Get free slot, sleep if slots are unavailable.
4401 * Even though we use wait_event() which sleeps indefinitely,
4402 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4403 */
4404 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4405 ufshcd_hold(hba, false);
7a3e97b0 4406
e2933132 4407 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 4408 task_req_descp = hba->utmrdl_base_addr;
4409 task_req_descp += free_slot;
4410
4411 /* Configure task request descriptor */
4412 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4413 task_req_descp->header.dword_2 =
4414 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4415
4416 /* Configure task request UPIU */
4417 task_req_upiup =
4418 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4419 task_tag = hba->nutrs + free_slot;
7a3e97b0 4420 task_req_upiup->header.dword_0 =
5a0b0cb9 4421 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4422 lun_id, task_tag);
7a3e97b0 4423 task_req_upiup->header.dword_1 =
5a0b0cb9 4424 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 4425 /*
4426 * The host shall provide the same value for LUN field in the basic
4427 * header and for Input Parameter.
4428 */
e2933132
SRT		 4429 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4430 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 4431
d2877be4
KK		 4432 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
4433
7a3e97b0
SY		 4434 /* send command to the controller */
4435 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 4436
4437 /* Make sure descriptors are ready before ringing the task doorbell */
4438 wmb();
4439
b873a275 4440 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 4441 /* Make sure that doorbell is committed immediately */
4442 wmb();
7a3e97b0
SY		 4443
4444 spin_unlock_irqrestore(host->host_lock, flags);
4445
4446 /* wait until the task management command is completed */
e2933132
SRT		 4447 err = wait_event_timeout(hba->tm_wq,
4448 test_bit(free_slot, &hba->tm_condition),
4449 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4450 if (!err) {
e2933132
SRT		 4451 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4452 __func__, tm_function);
4453 if (ufshcd_clear_tm_cmd(hba, free_slot))
4454 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4455 __func__, free_slot);
4456 err = -ETIMEDOUT;
4457 } else {
4458 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4459 }
e2933132 4460
7a3e97b0 4461 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 4462 ufshcd_put_tm_slot(hba, free_slot);
4463 wake_up(&hba->tm_tag_wq);
4464
1ab27c9c 4465 ufshcd_release(hba);
7a3e97b0
SY		 4466 return err;
4467}
4468
4469/**
3441da7d
SRT		 4470 * ufshcd_eh_device_reset_handler - device reset handler registered to
4471 * scsi layer.
7a3e97b0
SY		 4472 * @cmd: SCSI command pointer
4473 *
4474 * Returns SUCCESS/FAILED
4475 */
3441da7d 4476static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 4477{
4478 struct Scsi_Host *host;
4479 struct ufs_hba *hba;
4480 unsigned int tag;
4481 u32 pos;
4482 int err;
e2933132
SRT		 4483 u8 resp = 0xF;
4484 struct ufshcd_lrb *lrbp;
3441da7d 4485 unsigned long flags;
7a3e97b0
SY		 4486
4487 host = cmd->device->host;
4488 hba = shost_priv(host);
4489 tag = cmd->request->tag;
4490
e2933132
SRT		 4491 lrbp = &hba->lrb[tag];
4492 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4493 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 4494 if (!err)
4495 err = resp;
7a3e97b0 4496 goto out;
e2933132 4497 }
7a3e97b0 4498
3441da7d
SRT		 4499 /* clear the commands that were pending for corresponding LUN */
4500 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4501 if (hba->lrb[pos].lun == lrbp->lun) {
4502 err = ufshcd_clear_cmd(hba, pos);
4503 if (err)
4504 break;
7a3e97b0 4505 }
3441da7d
SRT		 4506 }
4507 spin_lock_irqsave(host->host_lock, flags);
4508 ufshcd_transfer_req_compl(hba);
4509 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4510out:
3441da7d
SRT		 4511 if (!err) {
4512 err = SUCCESS;
4513 } else {
4514 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4515 err = FAILED;
4516 }
7a3e97b0
SY		 4517 return err;
4518}
4519
7a3e97b0
SY		 4520/**
4521 * ufshcd_abort - abort a specific command
4522 * @cmd: SCSI command pointer
4523 *
f20810d8
SRT		 4524 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4525 * command, and in host controller by clearing the door-bell register. There can
4526 * be race between controller sending the command to the device while abort is
4527 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4528 * really issued and then try to abort it.
4529 *
7a3e97b0
SY		 4530 * Returns SUCCESS/FAILED
4531 */
4532static int ufshcd_abort(struct scsi_cmnd *cmd)
4533{
4534 struct Scsi_Host *host;
4535 struct ufs_hba *hba;
4536 unsigned long flags;
4537 unsigned int tag;
f20810d8
SRT		 4538 int err = 0;
4539 int poll_cnt;
e2933132
SRT		 4540 u8 resp = 0xF;
4541 struct ufshcd_lrb *lrbp;
e9d501b1 4542 u32 reg;
7a3e97b0
SY		 4543
4544 host = cmd->device->host;
4545 hba = shost_priv(host);
4546 tag = cmd->request->tag;
14497328
YG		 4547 if (!ufshcd_valid_tag(hba, tag)) {
4548 dev_err(hba->dev,
4549 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4550 __func__, tag, cmd, cmd->request);
4551 BUG();
4552 }
7a3e97b0 4553
1ab27c9c 4554 ufshcd_hold(hba, false);
14497328 4555 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4556 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 4557 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4558 dev_err(hba->dev,
4559 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4560 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4561 goto out;
14497328 4562 }
7a3e97b0 4563
e9d501b1
DR		 4564 if (!(reg & (1 << tag))) {
4565 dev_err(hba->dev,
4566 "%s: cmd was completed, but without a notifying intr, tag = %d",
4567 __func__, tag);
4568 }
4569
f20810d8
SRT		 4570 lrbp = &hba->lrb[tag];
4571 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4572 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4573 UFS_QUERY_TASK, &resp);
4574 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4575 /* cmd pending in the device */
4576 break;
4577 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4578 /*
4579 * cmd not pending in the device, check if it is
4580 * in transition.
4581 */
4582 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4583 if (reg & (1 << tag)) {
4584 /* sleep for max. 200us to stabilize */
4585 usleep_range(100, 200);
4586 continue;
4587 }
4588 /* command completed already */
4589 goto out;
4590 } else {
4591 if (!err)
4592 err = resp; /* service response error */
4593 goto out;
4594 }
4595 }
4596
4597 if (!poll_cnt) {
4598 err = -EBUSY;
7a3e97b0
SY		 4599 goto out;
4600 }
7a3e97b0 4601
e2933132
SRT		 4602 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4603 UFS_ABORT_TASK, &resp);
4604 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4605 if (!err)
4606 err = resp; /* service response error */
7a3e97b0 4607 goto out;
e2933132 4608 }
7a3e97b0 4609
f20810d8
SRT		 4610 err = ufshcd_clear_cmd(hba, tag);
4611 if (err)
4612 goto out;
4613
7a3e97b0
SY		 4614 scsi_dma_unmap(cmd);
4615
4616 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4617 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 4618 hba->lrb[tag].cmd = NULL;
4619 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 4620
4621 clear_bit_unlock(tag, &hba->lrb_in_use);
4622 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4623
7a3e97b0 4624out:
f20810d8
SRT		 4625 if (!err) {
4626 err = SUCCESS;
4627 } else {
4628 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4629 err = FAILED;
4630 }
4631
1ab27c9c
ST		 4632 /*
4633 * This ufshcd_release() corresponds to the original scsi cmd that got
4634 * aborted here (as we won't get any IRQ for it).
4635 */
4636 ufshcd_release(hba);
7a3e97b0
SY		 4637 return err;
4638}
4639
3441da7d
SRT		 4640/**
4641 * ufshcd_host_reset_and_restore - reset and restore host controller
4642 * @hba: per-adapter instance
4643 *
4644 * Note that host controller reset may issue DME_RESET to
4645 * local and remote (device) Uni-Pro stack and the attributes
4646 * are reset to default state.
4647 *
4648 * Returns zero on success, non-zero on failure
4649 */
4650static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4651{
4652 int err;
3441da7d
SRT		 4653 unsigned long flags;
4654
4655 /* Reset the host controller */
4656 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4657 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 4658 spin_unlock_irqrestore(hba->host->host_lock, flags);
4659
4660 err = ufshcd_hba_enable(hba);
4661 if (err)
4662 goto out;
4663
4664 /* Establish the link again and restore the device */
1d337ec2
SRT		 4665 err = ufshcd_probe_hba(hba);
4666
4667 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 4668 err = -EIO;
4669out:
4670 if (err)
4671 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4672
4673 return err;
4674}
4675
4676/**
4677 * ufshcd_reset_and_restore - reset and re-initialize host/device
4678 * @hba: per-adapter instance
4679 *
4680 * Reset and recover device, host and re-establish link. This
4681 * is helpful to recover the communication in fatal error conditions.
4682 *
4683 * Returns zero on success, non-zero on failure
4684 */
4685static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4686{
4687 int err = 0;
4688 unsigned long flags;
1d337ec2 4689 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4690
1d337ec2
SRT		 4691 do {
4692 err = ufshcd_host_reset_and_restore(hba);
4693 } while (err && --retries);
3441da7d
SRT		 4694
4695 /*
4696 * After reset the door-bell might be cleared, complete
4697 * outstanding requests in s/w here.
4698 */
4699 spin_lock_irqsave(hba->host->host_lock, flags);
4700 ufshcd_transfer_req_compl(hba);
4701 ufshcd_tmc_handler(hba);
4702 spin_unlock_irqrestore(hba->host->host_lock, flags);
4703
4704 return err;
4705}
4706
4707/**
4708 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4709 * @cmd - SCSI command pointer
4710 *
4711 * Returns SUCCESS/FAILED
4712 */
4713static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4714{
4715 int err;
4716 unsigned long flags;
4717 struct ufs_hba *hba;
4718
4719 hba = shost_priv(cmd->device->host);
4720
1ab27c9c 4721 ufshcd_hold(hba, false);
3441da7d
SRT		 4722 /*
4723 * Check if there is any race with fatal error handling.
4724 * If so, wait for it to complete. Even though fatal error
4725 * handling does reset and restore in some cases, don't assume
4726 * anything out of it. We are just avoiding race here.
4727 */
4728 do {
4729 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4730 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 4731 hba->ufshcd_state == UFSHCD_STATE_RESET))
4732 break;
4733 spin_unlock_irqrestore(hba->host->host_lock, flags);
4734 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4735 flush_work(&hba->eh_work);
3441da7d
SRT		 4736 } while (1);
4737
4738 hba->ufshcd_state = UFSHCD_STATE_RESET;
4739 ufshcd_set_eh_in_progress(hba);
4740 spin_unlock_irqrestore(hba->host->host_lock, flags);
4741
4742 err = ufshcd_reset_and_restore(hba);
4743
4744 spin_lock_irqsave(hba->host->host_lock, flags);
4745 if (!err) {
4746 err = SUCCESS;
4747 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4748 } else {
4749 err = FAILED;
4750 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4751 }
4752 ufshcd_clear_eh_in_progress(hba);
4753 spin_unlock_irqrestore(hba->host->host_lock, flags);
4754
1ab27c9c 4755 ufshcd_release(hba);
3441da7d
SRT		 4756 return err;
4757}
4758
3a4bf06d
YG		 4759/**
4760 * ufshcd_get_max_icc_level - calculate the ICC level
4761 * @sup_curr_uA: max. current supported by the regulator
4762 * @start_scan: row at the desc table to start scan from
4763 * @buff: power descriptor buffer
4764 *
4765 * Returns calculated max ICC level for specific regulator
4766 */
4767static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4768{
4769 int i;
4770 int curr_uA;
4771 u16 data;
4772 u16 unit;
4773
4774 for (i = start_scan; i >= 0; i--) {
4775 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4776 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4777 ATTR_ICC_LVL_UNIT_OFFSET;
4778 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4779 switch (unit) {
4780 case UFSHCD_NANO_AMP:
4781 curr_uA = curr_uA / 1000;
4782 break;
4783 case UFSHCD_MILI_AMP:
4784 curr_uA = curr_uA * 1000;
4785 break;
4786 case UFSHCD_AMP:
4787 curr_uA = curr_uA * 1000 * 1000;
4788 break;
4789 case UFSHCD_MICRO_AMP:
4790 default:
4791 break;
4792 }
4793 if (sup_curr_uA >= curr_uA)
4794 break;
4795 }
4796 if (i < 0) {
4797 i = 0;
4798 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4799 }
4800
4801 return (u32)i;
4802}
4803
4804/**
4805 * ufshcd_calc_icc_level - calculate the max ICC level
4806 * In case regulators are not initialized we'll return 0
4807 * @hba: per-adapter instance
4808 * @desc_buf: power descriptor buffer to extract ICC levels from.
4809 * @len: length of desc_buff
4810 *
4811 * Returns calculated ICC level
4812 */
4813static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4814 u8 *desc_buf, int len)
4815{
4816 u32 icc_level = 0;
4817
4818 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4819 !hba->vreg_info.vccq2) {
4820 dev_err(hba->dev,
4821 "%s: Regulator capability was not set, actvIccLevel=%d",
4822 __func__, icc_level);
4823 goto out;
4824 }
4825
4826 if (hba->vreg_info.vcc)
4827 icc_level = ufshcd_get_max_icc_level(
4828 hba->vreg_info.vcc->max_uA,
4829 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4830 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4831
4832 if (hba->vreg_info.vccq)
4833 icc_level = ufshcd_get_max_icc_level(
4834 hba->vreg_info.vccq->max_uA,
4835 icc_level,
4836 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4837
4838 if (hba->vreg_info.vccq2)
4839 icc_level = ufshcd_get_max_icc_level(
4840 hba->vreg_info.vccq2->max_uA,
4841 icc_level,
4842 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4843out:
4844 return icc_level;
4845}
4846
61e07359
DR		 4847static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
4848{
4849 int ret = 0;
4850 int retries;
4851
4852 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4853 /* write attribute */
4854 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4855 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
4856 if (!ret)
4857 break;
4858
4859 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
4860 }
4861
4862 return ret;
4863}
4864
3a4bf06d
YG		 4865static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4866{
4867 int ret;
4868 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4869 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4870
4871 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4872 if (ret) {
4873 dev_err(hba->dev,
4874 "%s: Failed reading power descriptor.len = %d ret = %d",
4875 __func__, buff_len, ret);
4876 return;
4877 }
4878
4879 hba->init_prefetch_data.icc_level =
4880 ufshcd_find_max_sup_active_icc_level(hba,
4881 desc_buf, buff_len);
4882 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4883 __func__, hba->init_prefetch_data.icc_level);
4884
61e07359
DR		 4885 ret = ufshcd_set_icc_levels_attr(hba,
4886 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 4887
4888 if (ret)
4889 dev_err(hba->dev,
4890 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4891 __func__, hba->init_prefetch_data.icc_level , ret);
4892
4893}
4894
2a8fa600
SJ		 4895/**
4896 * ufshcd_scsi_add_wlus - Adds required W-LUs
4897 * @hba: per-adapter instance
4898 *
4899 * UFS device specification requires the UFS devices to support 4 well known
4900 * logical units:
4901 * "REPORT_LUNS" (address: 01h)
4902 * "UFS Device" (address: 50h)
4903 * "RPMB" (address: 44h)
4904 * "BOOT" (address: 30h)
4905 * UFS device's power management needs to be controlled by "POWER CONDITION"
4906 * field of SSU (START STOP UNIT) command. But this "power condition" field
4907 * will take effect only when its sent to "UFS device" well known logical unit
4908 * hence we require the scsi_device instance to represent this logical unit in
4909 * order for the UFS host driver to send the SSU command for power management.
4910
4911 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4912 * Block) LU so user space process can control this LU. User space may also
4913 * want to have access to BOOT LU.
4914
4915 * This function adds scsi device instances for each of all well known LUs
4916 * (except "REPORT LUNS" LU).
4917 *
4918 * Returns zero on success (all required W-LUs are added successfully),
4919 * non-zero error value on failure (if failed to add any of the required W-LU).
4920 */
4921static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4922{
4923 int ret = 0;
7c48bfd0
AM		 4924 struct scsi_device *sdev_rpmb;
4925 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4926
4927 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4928 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4929 if (IS_ERR(hba->sdev_ufs_device)) {
4930 ret = PTR_ERR(hba->sdev_ufs_device);
4931 hba->sdev_ufs_device = NULL;
4932 goto out;
4933 }
7c48bfd0 4934 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4935
7c48bfd0 4936 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4937 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4938 if (IS_ERR(sdev_boot)) {
4939 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4940 goto remove_sdev_ufs_device;
4941 }
7c48bfd0 4942 scsi_device_put(sdev_boot);
2a8fa600 4943
7c48bfd0 4944 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4945 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4946 if (IS_ERR(sdev_rpmb)) {
4947 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4948 goto remove_sdev_boot;
4949 }
7c48bfd0 4950 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4951 goto out;
4952
4953remove_sdev_boot:
7c48bfd0 4954 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4955remove_sdev_ufs_device:
4956 scsi_remove_device(hba->sdev_ufs_device);
4957out:
4958 return ret;
4959}
4960
c58ab7aa
YG		 4961static int ufs_get_device_info(struct ufs_hba *hba,
4962 struct ufs_device_info *card_data)
4963{
4964 int err;
4965 u8 model_index;
4966 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
4967 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
4968
4969 err = ufshcd_read_device_desc(hba, desc_buf,
4970 QUERY_DESC_DEVICE_MAX_SIZE);
4971 if (err) {
4972 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
4973 __func__, err);
4974 goto out;
4975 }
4976
4977 /*
4978 * getting vendor (manufacturerID) and Bank Index in big endian
4979 * format
4980 */
4981 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
4982 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
4983
4984 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4985
4986 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
4987 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
4988 if (err) {
4989 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
4990 __func__, err);
4991 goto out;
4992 }
4993
4994 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
4995 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
4996 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
4997 MAX_MODEL_LEN));
4998
4999 /* Null terminate the model string */
5000 card_data->model[MAX_MODEL_LEN] = '\0';
5001
5002out:
5003 return err;
5004}
5005
5006void ufs_advertise_fixup_device(struct ufs_hba *hba)
5007{
5008 int err;
5009 struct ufs_dev_fix *f;
5010 struct ufs_device_info card_data;
5011
5012 card_data.wmanufacturerid = 0;
5013
5014 err = ufs_get_device_info(hba, &card_data);
5015 if (err) {
5016 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
5017 __func__, err);
5018 return;
5019 }
5020
5021 for (f = ufs_fixups; f->quirk; f++) {
5022 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
5023 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
5024 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
5025 !strcmp(f->card.model, UFS_ANY_MODEL)))
5026 hba->dev_quirks |= f->quirk;
5027 }
5028}
5029
37113106
YG		 5030/**
5031 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
5032 * @hba: per-adapter instance
5033 *
5034 * PA_TActivate parameter can be tuned manually if UniPro version is less than
5035 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
5036 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
5037 * the hibern8 exit latency.
5038 *
5039 * Returns zero on success, non-zero error value on failure.
5040 */
5041static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
5042{
5043 int ret = 0;
5044 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
5045
5046 ret = ufshcd_dme_peer_get(hba,
5047 UIC_ARG_MIB_SEL(
5048 RX_MIN_ACTIVATETIME_CAPABILITY,
5049 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5050 &peer_rx_min_activatetime);
5051 if (ret)
5052 goto out;
5053
5054 /* make sure proper unit conversion is applied */
5055 tuned_pa_tactivate =
5056 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
5057 / PA_TACTIVATE_TIME_UNIT_US);
5058 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5059 tuned_pa_tactivate);
5060
5061out:
5062 return ret;
5063}
5064
5065/**
5066 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
5067 * @hba: per-adapter instance
5068 *
5069 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
5070 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
5071 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
5072 * This optimal value can help reduce the hibern8 exit latency.
5073 *
5074 * Returns zero on success, non-zero error value on failure.
5075 */
5076static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
5077{
5078 int ret = 0;
5079 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
5080 u32 max_hibern8_time, tuned_pa_hibern8time;
5081
5082 ret = ufshcd_dme_get(hba,
5083 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
5084 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
5085 &local_tx_hibern8_time_cap);
5086 if (ret)
5087 goto out;
5088
5089 ret = ufshcd_dme_peer_get(hba,
5090 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
5091 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5092 &peer_rx_hibern8_time_cap);
5093 if (ret)
5094 goto out;
5095
5096 max_hibern8_time = max(local_tx_hibern8_time_cap,
5097 peer_rx_hibern8_time_cap);
5098 /* make sure proper unit conversion is applied */
5099 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
5100 / PA_HIBERN8_TIME_UNIT_US);
5101 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
5102 tuned_pa_hibern8time);
5103out:
5104 return ret;
5105}
5106
c6a6db43 5107/**
5108 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
5109 * less than device PA_TACTIVATE time.
5110 * @hba: per-adapter instance
5111 *
5112 * Some UFS devices require host PA_TACTIVATE to be lower than device
5113 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
5114 * for such devices.
5115 *
5116 * Returns zero on success, non-zero error value on failure.
5117 */
5118static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
5119{
5120 int ret = 0;
5121 u32 granularity, peer_granularity;
5122 u32 pa_tactivate, peer_pa_tactivate;
5123 u32 pa_tactivate_us, peer_pa_tactivate_us;
5124 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
5125
5126 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5127 &granularity);
5128 if (ret)
5129 goto out;
5130
5131 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5132 &peer_granularity);
5133 if (ret)
5134 goto out;
5135
5136 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
5137 (granularity > PA_GRANULARITY_MAX_VAL)) {
5138 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
5139 __func__, granularity);
5140 return -EINVAL;
5141 }
5142
5143 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
5144 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
5145 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
5146 __func__, peer_granularity);
5147 return -EINVAL;
5148 }
5149
5150 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
5151 if (ret)
5152 goto out;
5153
5154 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
5155 &peer_pa_tactivate);
5156 if (ret)
5157 goto out;
5158
5159 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
5160 peer_pa_tactivate_us = peer_pa_tactivate *
5161 gran_to_us_table[peer_granularity - 1];
5162
5163 if (pa_tactivate_us > peer_pa_tactivate_us) {
5164 u32 new_peer_pa_tactivate;
5165
5166 new_peer_pa_tactivate = pa_tactivate_us /
5167 gran_to_us_table[peer_granularity - 1];
5168 new_peer_pa_tactivate++;
5169 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5170 new_peer_pa_tactivate);
5171 }
5172
5173out:
5174 return ret;
5175}
5176
37113106
YG		 5177static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
5178{
5179 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
5180 ufshcd_tune_pa_tactivate(hba);
5181 ufshcd_tune_pa_hibern8time(hba);
5182 }
5183
5184 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
5185 /* set 1ms timeout for PA_TACTIVATE */
5186 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 5187
5188 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
5189 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 5190}
5191
6ccf44fe 5192/**
1d337ec2
SRT		 5193 * ufshcd_probe_hba - probe hba to detect device and initialize
5194 * @hba: per-adapter instance
5195 *
5196 * Execute link-startup and verify device initialization
6ccf44fe 5197 */
1d337ec2 5198static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 5199{
6ccf44fe
SJ		 5200 int ret;
5201
5202 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 5203 if (ret)
5204 goto out;
5205
5064636c
YG		 5206 ufshcd_init_pwr_info(hba);
5207
afdfff59
YG		 5208 /* set the default level for urgent bkops */
5209 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5210 hba->is_urgent_bkops_lvl_checked = false;
5211
57d104c1
SJ		 5212 /* UniPro link is active now */
5213 ufshcd_set_link_active(hba);
d3e89bac 5214
5a0b0cb9
SRT		 5215 ret = ufshcd_verify_dev_init(hba);
5216 if (ret)
5217 goto out;
68078d5c
DR		 5218
5219 ret = ufshcd_complete_dev_init(hba);
5220 if (ret)
5221 goto out;
5a0b0cb9 5222
c58ab7aa 5223 ufs_advertise_fixup_device(hba);
37113106 5224 ufshcd_tune_unipro_params(hba);
60f01870
YG		 5225
5226 ret = ufshcd_set_vccq_rail_unused(hba,
5227 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5228 if (ret)
5229 goto out;
5230
57d104c1
SJ		 5231 /* UFS device is also active now */
5232 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5233 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 5234 hba->wlun_dev_clr_ua = true;
5235
7eb584db
DR		 5236 if (ufshcd_get_max_pwr_mode(hba)) {
5237 dev_err(hba->dev,
5238 "%s: Failed getting max supported power mode\n",
5239 __func__);
5240 } else {
5241 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 5242 if (ret) {
7eb584db
DR		 5243 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5244 __func__, ret);
8643ae66
DL		 5245 goto out;
5246 }
7eb584db 5247 }
57d104c1 5248
53c12d0e
YG		 5249 /* set the state as operational after switching to desired gear */
5250 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 5251 /*
5252 * If we are in error handling context or in power management callbacks
5253 * context, no need to scan the host
5254 */
5255 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5256 bool flag;
5257
5258 /* clear any previous UFS device information */
5259 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 5260 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5261 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5262 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5263
3a4bf06d
YG		 5264 if (!hba->is_init_prefetch)
5265 ufshcd_init_icc_levels(hba);
5266
2a8fa600
SJ		 5267 /* Add required well known logical units to scsi mid layer */
5268 if (ufshcd_scsi_add_wlus(hba))
5269 goto out;
5270
3441da7d
SRT		 5271 scsi_scan_host(hba->host);
5272 pm_runtime_put_sync(hba->dev);
5273 }
3a4bf06d
YG		 5274
5275 if (!hba->is_init_prefetch)
5276 hba->is_init_prefetch = true;
5277
856b3483 5278 /* Resume devfreq after UFS device is detected */
a508253d 5279 ufshcd_resume_clkscaling(hba);
856b3483 5280
5a0b0cb9 5281out:
1d337ec2
SRT		 5282 /*
5283 * If we failed to initialize the device or the device is not
5284 * present, turn off the power/clocks etc.
5285 */
57d104c1
SJ		 5286 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5287 pm_runtime_put_sync(hba->dev);
1d337ec2 5288 ufshcd_hba_exit(hba);
57d104c1 5289 }
1d337ec2
SRT		 5290
5291 return ret;
5292}
5293
5294/**
5295 * ufshcd_async_scan - asynchronous execution for probing hba
5296 * @data: data pointer to pass to this function
5297 * @cookie: cookie data
5298 */
5299static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5300{
5301 struct ufs_hba *hba = (struct ufs_hba *)data;
5302
5303 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 5304}
5305
f550c65b
YG		 5306static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5307{
5308 unsigned long flags;
5309 struct Scsi_Host *host;
5310 struct ufs_hba *hba;
5311 int index;
5312 bool found = false;
5313
5314 if (!scmd || !scmd->device || !scmd->device->host)
5315 return BLK_EH_NOT_HANDLED;
5316
5317 host = scmd->device->host;
5318 hba = shost_priv(host);
5319 if (!hba)
5320 return BLK_EH_NOT_HANDLED;
5321
5322 spin_lock_irqsave(host->host_lock, flags);
5323
5324 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5325 if (hba->lrb[index].cmd == scmd) {
5326 found = true;
5327 break;
5328 }
5329 }
5330
5331 spin_unlock_irqrestore(host->host_lock, flags);
5332
5333 /*
5334 * Bypass SCSI error handling and reset the block layer timer if this
5335 * SCSI command was not actually dispatched to UFS driver, otherwise
5336 * let SCSI layer handle the error as usual.
5337 */
5338 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5339}
5340
7a3e97b0
SY		 5341static struct scsi_host_template ufshcd_driver_template = {
5342 .module = THIS_MODULE,
5343 .name = UFSHCD,
5344 .proc_name = UFSHCD,
5345 .queuecommand = ufshcd_queuecommand,
5346 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5347 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5348 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5349 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5350 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 5351 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5352 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5353 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 5354 .this_id = -1,
5355 .sg_tablesize = SG_ALL,
5356 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5357 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5358 .max_host_blocked = 1,
c40ecc12 5359 .track_queue_depth = 1,
7a3e97b0
SY		 5360};
5361
57d104c1
SJ		 5362static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5363 int ua)
5364{
7b16a07c 5365 int ret;
57d104c1 5366
7b16a07c
BA		 5367 if (!vreg)
5368 return 0;
57d104c1 5369
7b16a07c
BA		 5370 ret = regulator_set_load(vreg->reg, ua);
5371 if (ret < 0) {
5372 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5373 __func__, vreg->name, ua, ret);
57d104c1
SJ		 5374 }
5375
5376 return ret;
5377}
5378
5379static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5380 struct ufs_vreg *vreg)
5381{
60f01870
YG		 5382 if (!vreg)
5383 return 0;
5384 else if (vreg->unused)
5385 return 0;
5386 else
5387 return ufshcd_config_vreg_load(hba->dev, vreg,
5388 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 5389}
5390
5391static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5392 struct ufs_vreg *vreg)
5393{
60f01870
YG		 5394 if (!vreg)
5395 return 0;
5396 else if (vreg->unused)
5397 return 0;
5398 else
5399 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 5400}
5401
aa497613
SRT		 5402static int ufshcd_config_vreg(struct device *dev,
5403 struct ufs_vreg *vreg, bool on)
5404{
5405 int ret = 0;
5406 struct regulator *reg = vreg->reg;
5407 const char *name = vreg->name;
5408 int min_uV, uA_load;
5409
5410 BUG_ON(!vreg);
5411
5412 if (regulator_count_voltages(reg) > 0) {
5413 min_uV = on ? vreg->min_uV : 0;
5414 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5415 if (ret) {
5416 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5417 __func__, name, ret);
5418 goto out;
5419 }
5420
5421 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 5422 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5423 if (ret)
aa497613 5424 goto out;
aa497613
SRT		 5425 }
5426out:
5427 return ret;
5428}
5429
5430static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5431{
5432 int ret = 0;
5433
60f01870
YG		 5434 if (!vreg)
5435 goto out;
5436 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 5437 goto out;
5438
5439 ret = ufshcd_config_vreg(dev, vreg, true);
5440 if (!ret)
5441 ret = regulator_enable(vreg->reg);
5442
5443 if (!ret)
5444 vreg->enabled = true;
5445 else
5446 dev_err(dev, "%s: %s enable failed, err=%d\n",
5447 __func__, vreg->name, ret);
5448out:
5449 return ret;
5450}
5451
5452static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5453{
5454 int ret = 0;
5455
60f01870
YG		 5456 if (!vreg)
5457 goto out;
5458 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 5459 goto out;
5460
5461 ret = regulator_disable(vreg->reg);
5462
5463 if (!ret) {
5464 /* ignore errors on applying disable config */
5465 ufshcd_config_vreg(dev, vreg, false);
5466 vreg->enabled = false;
5467 } else {
5468 dev_err(dev, "%s: %s disable failed, err=%d\n",
5469 __func__, vreg->name, ret);
5470 }
5471out:
5472 return ret;
5473}
5474
5475static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5476{
5477 int ret = 0;
5478 struct device *dev = hba->dev;
5479 struct ufs_vreg_info *info = &hba->vreg_info;
5480
5481 if (!info)
5482 goto out;
5483
5484 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5485 if (ret)
5486 goto out;
5487
5488 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5489 if (ret)
5490 goto out;
5491
5492 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5493 if (ret)
5494 goto out;
5495
5496out:
5497 if (ret) {
5498 ufshcd_toggle_vreg(dev, info->vccq2, false);
5499 ufshcd_toggle_vreg(dev, info->vccq, false);
5500 ufshcd_toggle_vreg(dev, info->vcc, false);
5501 }
5502 return ret;
5503}
5504
6a771a65
RS		 5505static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5506{
5507 struct ufs_vreg_info *info = &hba->vreg_info;
5508
5509 if (info)
5510 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5511
5512 return 0;
5513}
5514
aa497613
SRT		 5515static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5516{
5517 int ret = 0;
5518
5519 if (!vreg)
5520 goto out;
5521
5522 vreg->reg = devm_regulator_get(dev, vreg->name);
5523 if (IS_ERR(vreg->reg)) {
5524 ret = PTR_ERR(vreg->reg);
5525 dev_err(dev, "%s: %s get failed, err=%d\n",
5526 __func__, vreg->name, ret);
5527 }
5528out:
5529 return ret;
5530}
5531
5532static int ufshcd_init_vreg(struct ufs_hba *hba)
5533{
5534 int ret = 0;
5535 struct device *dev = hba->dev;
5536 struct ufs_vreg_info *info = &hba->vreg_info;
5537
5538 if (!info)
5539 goto out;
5540
5541 ret = ufshcd_get_vreg(dev, info->vcc);
5542 if (ret)
5543 goto out;
5544
5545 ret = ufshcd_get_vreg(dev, info->vccq);
5546 if (ret)
5547 goto out;
5548
5549 ret = ufshcd_get_vreg(dev, info->vccq2);
5550out:
5551 return ret;
5552}
5553
6a771a65
RS		 5554static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5555{
5556 struct ufs_vreg_info *info = &hba->vreg_info;
5557
5558 if (info)
5559 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5560
5561 return 0;
5562}
5563
60f01870
YG		 5564static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5565{
5566 int ret = 0;
5567 struct ufs_vreg_info *info = &hba->vreg_info;
5568
5569 if (!info)
5570 goto out;
5571 else if (!info->vccq)
5572 goto out;
5573
5574 if (unused) {
5575 /* shut off the rail here */
5576 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5577 /*
5578 * Mark this rail as no longer used, so it doesn't get enabled
5579 * later by mistake
5580 */
5581 if (!ret)
5582 info->vccq->unused = true;
5583 } else {
5584 /*
5585 * rail should have been already enabled hence just make sure
5586 * that unused flag is cleared.
5587 */
5588 info->vccq->unused = false;
5589 }
5590out:
5591 return ret;
5592}
5593
57d104c1
SJ		 5594static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5595 bool skip_ref_clk)
c6e79dac
SRT		 5596{
5597 int ret = 0;
5598 struct ufs_clk_info *clki;
5599 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5600 unsigned long flags;
c6e79dac
SRT		 5601
5602 if (!head || list_empty(head))
5603 goto out;
5604
1e879e8f
SJ		 5605 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
5606 if (ret)
5607 return ret;
5608
c6e79dac
SRT		 5609 list_for_each_entry(clki, head, list) {
5610 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 5611 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5612 continue;
5613
c6e79dac
SRT		 5614 if (on && !clki->enabled) {
5615 ret = clk_prepare_enable(clki->clk);
5616 if (ret) {
5617 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5618 __func__, clki->name, ret);
5619 goto out;
5620 }
5621 } else if (!on && clki->enabled) {
5622 clk_disable_unprepare(clki->clk);
5623 }
5624 clki->enabled = on;
5625 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5626 clki->name, on ? "en" : "dis");
5627 }
5628 }
1ab27c9c 5629
1e879e8f
SJ		 5630 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
5631 if (ret)
5632 return ret;
5633
c6e79dac
SRT		 5634out:
5635 if (ret) {
5636 list_for_each_entry(clki, head, list) {
5637 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5638 clk_disable_unprepare(clki->clk);
5639 }
eda910e4 5640 } else if (on) {
1ab27c9c
ST		 5641 spin_lock_irqsave(hba->host->host_lock, flags);
5642 hba->clk_gating.state = CLKS_ON;
5643 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 5644 }
5645 return ret;
5646}
5647
57d104c1
SJ		 5648static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
5649{
5650 return __ufshcd_setup_clocks(hba, on, false);
5651}
5652
c6e79dac
SRT		 5653static int ufshcd_init_clocks(struct ufs_hba *hba)
5654{
5655 int ret = 0;
5656 struct ufs_clk_info *clki;
5657 struct device *dev = hba->dev;
5658 struct list_head *head = &hba->clk_list_head;
5659
5660 if (!head || list_empty(head))
5661 goto out;
5662
5663 list_for_each_entry(clki, head, list) {
5664 if (!clki->name)
5665 continue;
5666
5667 clki->clk = devm_clk_get(dev, clki->name);
5668 if (IS_ERR(clki->clk)) {
5669 ret = PTR_ERR(clki->clk);
5670 dev_err(dev, "%s: %s clk get failed, %d\n",
5671 __func__, clki->name, ret);
5672 goto out;
5673 }
5674
5675 if (clki->max_freq) {
5676 ret = clk_set_rate(clki->clk, clki->max_freq);
5677 if (ret) {
5678 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5679 __func__, clki->name,
5680 clki->max_freq, ret);
5681 goto out;
5682 }
856b3483 5683 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 5684 }
5685 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
5686 clki->name, clk_get_rate(clki->clk));
5687 }
5688out:
5689 return ret;
5690}
5691
5c0c28a8
SRT		 5692static int ufshcd_variant_hba_init(struct ufs_hba *hba)
5693{
5694 int err = 0;
5695
5696 if (!hba->vops)
5697 goto out;
5698
0263bcd0
YG		 5699 err = ufshcd_vops_init(hba);
5700 if (err)
5701 goto out;
5c0c28a8 5702
0263bcd0
YG		 5703 err = ufshcd_vops_setup_regulators(hba, true);
5704 if (err)
5705 goto out_exit;
5c0c28a8
SRT		 5706
5707 goto out;
5708
5c0c28a8 5709out_exit:
0263bcd0 5710 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5711out:
5712 if (err)
5713 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 5714 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 5715 return err;
5716}
5717
5718static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
5719{
5720 if (!hba->vops)
5721 return;
5722
0263bcd0 5723 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 5724
0263bcd0 5725 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5726}
5727
aa497613
SRT		 5728static int ufshcd_hba_init(struct ufs_hba *hba)
5729{
5730 int err;
5731
6a771a65
RS		 5732 /*
5733 * Handle host controller power separately from the UFS device power
5734 * rails as it will help controlling the UFS host controller power
5735 * collapse easily which is different than UFS device power collapse.
5736 * Also, enable the host controller power before we go ahead with rest
5737 * of the initialization here.
5738 */
5739 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 5740 if (err)
5741 goto out;
5742
6a771a65 5743 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 5744 if (err)
5745 goto out;
5746
6a771a65
RS		 5747 err = ufshcd_init_clocks(hba);
5748 if (err)
5749 goto out_disable_hba_vreg;
5750
5751 err = ufshcd_setup_clocks(hba, true);
5752 if (err)
5753 goto out_disable_hba_vreg;
5754
c6e79dac
SRT		 5755 err = ufshcd_init_vreg(hba);
5756 if (err)
5757 goto out_disable_clks;
5758
5759 err = ufshcd_setup_vreg(hba, true);
5760 if (err)
5761 goto out_disable_clks;
5762
aa497613
SRT		 5763 err = ufshcd_variant_hba_init(hba);
5764 if (err)
5765 goto out_disable_vreg;
5766
1d337ec2 5767 hba->is_powered = true;
aa497613
SRT		 5768 goto out;
5769
5770out_disable_vreg:
5771 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 5772out_disable_clks:
5773 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 5774out_disable_hba_vreg:
5775 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 5776out:
5777 return err;
5778}
5779
5780static void ufshcd_hba_exit(struct ufs_hba *hba)
5781{
1d337ec2
SRT		 5782 if (hba->is_powered) {
5783 ufshcd_variant_hba_exit(hba);
5784 ufshcd_setup_vreg(hba, false);
a508253d 5785 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 5786 ufshcd_setup_clocks(hba, false);
5787 ufshcd_setup_hba_vreg(hba, false);
5788 hba->is_powered = false;
5789 }
aa497613
SRT		 5790}
5791
57d104c1
SJ		 5792static int
5793ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
5794{
5795 unsigned char cmd[6] = {REQUEST_SENSE,
5796 0,
5797 0,
5798 0,
dcea0bfb 5799 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 5800 0};
5801 char *buffer;
5802 int ret;
5803
dcea0bfb 5804 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 5805 if (!buffer) {
5806 ret = -ENOMEM;
5807 goto out;
5808 }
5809
5810 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 5811 UFSHCD_REQ_SENSE_SIZE, NULL,
57d104c1
SJ		 5812 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
5813 if (ret)
5814 pr_err("%s: failed with err %d\n", __func__, ret);
5815
5816 kfree(buffer);
5817out:
5818 return ret;
5819}
5820
5821/**
5822 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
5823 * power mode
5824 * @hba: per adapter instance
5825 * @pwr_mode: device power mode to set
5826 *
5827 * Returns 0 if requested power mode is set successfully
5828 * Returns non-zero if failed to set the requested power mode
5829 */
5830static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
5831 enum ufs_dev_pwr_mode pwr_mode)
5832{
5833 unsigned char cmd[6] = { START_STOP };
5834 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 5835 struct scsi_device *sdp;
5836 unsigned long flags;
57d104c1
SJ		 5837 int ret;
5838
7c48bfd0
AM		 5839 spin_lock_irqsave(hba->host->host_lock, flags);
5840 sdp = hba->sdev_ufs_device;
5841 if (sdp) {
5842 ret = scsi_device_get(sdp);
5843 if (!ret && !scsi_device_online(sdp)) {
5844 ret = -ENODEV;
5845 scsi_device_put(sdp);
5846 }
5847 } else {
5848 ret = -ENODEV;
5849 }
5850 spin_unlock_irqrestore(hba->host->host_lock, flags);
5851
5852 if (ret)
5853 return ret;
57d104c1
SJ		 5854
5855 /*
5856 * If scsi commands fail, the scsi mid-layer schedules scsi error-
5857 * handling, which would wait for host to be resumed. Since we know
5858 * we are functional while we are here, skip host resume in error
5859 * handling context.
5860 */
5861 hba->host->eh_noresume = 1;
5862 if (hba->wlun_dev_clr_ua) {
5863 ret = ufshcd_send_request_sense(hba, sdp);
5864 if (ret)
5865 goto out;
5866 /* Unit attention condition is cleared now */
5867 hba->wlun_dev_clr_ua = false;
5868 }
5869
5870 cmd[4] = pwr_mode << 4;
5871
5872 /*
5873 * Current function would be generally called from the power management
5874 * callbacks hence set the REQ_PM flag so that it doesn't resume the
5875 * already suspended childs.
5876 */
5877 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
5878 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
5879 if (ret) {
5880 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 5881 "START_STOP failed for power mode: %d, result %x\n",
5882 pwr_mode, ret);
21045519
HR		 5883 if (driver_byte(ret) & DRIVER_SENSE)
5884 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 5885 }
5886
5887 if (!ret)
5888 hba->curr_dev_pwr_mode = pwr_mode;
5889out:
7c48bfd0 5890 scsi_device_put(sdp);
57d104c1
SJ		 5891 hba->host->eh_noresume = 0;
5892 return ret;
5893}
5894
5895static int ufshcd_link_state_transition(struct ufs_hba *hba,
5896 enum uic_link_state req_link_state,
5897 int check_for_bkops)
5898{
5899 int ret = 0;
5900
5901 if (req_link_state == hba->uic_link_state)
5902 return 0;
5903
5904 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5905 ret = ufshcd_uic_hibern8_enter(hba);
5906 if (!ret)
5907 ufshcd_set_link_hibern8(hba);
5908 else
5909 goto out;
5910 }
5911 /*
5912 * If autobkops is enabled, link can't be turned off because
5913 * turning off the link would also turn off the device.
5914 */
5915 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
5916 (!check_for_bkops || (check_for_bkops &&
5917 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 5918 /*
5919 * Let's make sure that link is in low power mode, we are doing
5920 * this currently by putting the link in Hibern8. Otherway to
5921 * put the link in low power mode is to send the DME end point
5922 * to device and then send the DME reset command to local
5923 * unipro. But putting the link in hibern8 is much faster.
5924 */
5925 ret = ufshcd_uic_hibern8_enter(hba);
5926 if (ret)
5927 goto out;
57d104c1
SJ		 5928 /*
5929 * Change controller state to "reset state" which
5930 * should also put the link in off/reset state
5931 */
596585a2 5932 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 5933 /*
5934 * TODO: Check if we need any delay to make sure that
5935 * controller is reset
5936 */
5937 ufshcd_set_link_off(hba);
5938 }
5939
5940out:
5941 return ret;
5942}
5943
5944static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
5945{
b799fdf7
YG		 5946 /*
5947 * It seems some UFS devices may keep drawing more than sleep current
5948 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
5949 * To avoid this situation, add 2ms delay before putting these UFS
5950 * rails in LPM mode.
5951 */
5952 if (!ufshcd_is_link_active(hba) &&
5953 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
5954 usleep_range(2000, 2100);
5955
57d104c1
SJ		 5956 /*
5957 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
5958 * power.
5959 *
5960 * If UFS device and link is in OFF state, all power supplies (VCC,
5961 * VCCQ, VCCQ2) can be turned off if power on write protect is not
5962 * required. If UFS link is inactive (Hibern8 or OFF state) and device
5963 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
5964 *
5965 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
5966 * in low power state which would save some power.
5967 */
5968 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5969 !hba->dev_info.is_lu_power_on_wp) {
5970 ufshcd_setup_vreg(hba, false);
5971 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5972 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5973 if (!ufshcd_is_link_active(hba)) {
5974 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5975 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
5976 }
5977 }
5978}
5979
5980static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
5981{
5982 int ret = 0;
5983
5984 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5985 !hba->dev_info.is_lu_power_on_wp) {
5986 ret = ufshcd_setup_vreg(hba, true);
5987 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 5988 if (!ret && !ufshcd_is_link_active(hba)) {
5989 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5990 if (ret)
5991 goto vcc_disable;
5992 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5993 if (ret)
5994 goto vccq_lpm;
5995 }
69d72ac8 5996 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 5997 }
5998 goto out;
5999
6000vccq_lpm:
6001 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
6002vcc_disable:
6003 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
6004out:
6005 return ret;
6006}
6007
6008static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
6009{
6010 if (ufshcd_is_link_off(hba))
6011 ufshcd_setup_hba_vreg(hba, false);
6012}
6013
6014static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
6015{
6016 if (ufshcd_is_link_off(hba))
6017 ufshcd_setup_hba_vreg(hba, true);
6018}
6019
7a3e97b0 6020/**
57d104c1 6021 * ufshcd_suspend - helper function for suspend operations
3b1d0580 6022 * @hba: per adapter instance
57d104c1
SJ		 6023 * @pm_op: desired low power operation type
6024 *
6025 * This function will try to put the UFS device and link into low power
6026 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
6027 * (System PM level).
6028 *
6029 * If this function is called during shutdown, it will make sure that
6030 * both UFS device and UFS link is powered off.
7a3e97b0 6031 *
57d104c1
SJ		 6032 * NOTE: UFS device & link must be active before we enter in this function.
6033 *
6034 * Returns 0 for success and non-zero for failure
7a3e97b0 6035 */
57d104c1 6036static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6037{
57d104c1
SJ		 6038 int ret = 0;
6039 enum ufs_pm_level pm_lvl;
6040 enum ufs_dev_pwr_mode req_dev_pwr_mode;
6041 enum uic_link_state req_link_state;
6042
6043 hba->pm_op_in_progress = 1;
6044 if (!ufshcd_is_shutdown_pm(pm_op)) {
6045 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
6046 hba->rpm_lvl : hba->spm_lvl;
6047 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
6048 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
6049 } else {
6050 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
6051 req_link_state = UIC_LINK_OFF_STATE;
6052 }
6053
7a3e97b0 6054 /*
57d104c1
SJ		 6055 * If we can't transition into any of the low power modes
6056 * just gate the clocks.
7a3e97b0 6057 */
1ab27c9c
ST		 6058 ufshcd_hold(hba, false);
6059 hba->clk_gating.is_suspended = true;
6060
d6fcf81a
SJ		 6061 ufshcd_suspend_clkscaling(hba);
6062
57d104c1
SJ		 6063 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
6064 req_link_state == UIC_LINK_ACTIVE_STATE) {
6065 goto disable_clks;
6066 }
7a3e97b0 6067
57d104c1
SJ		 6068 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
6069 (req_link_state == hba->uic_link_state))
d6fcf81a 6070 goto enable_gating;
57d104c1
SJ		 6071
6072 /* UFS device & link must be active before we enter in this function */
6073 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
6074 ret = -EINVAL;
d6fcf81a 6075 goto enable_gating;
57d104c1
SJ		 6076 }
6077
6078 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 6079 if (ufshcd_can_autobkops_during_suspend(hba)) {
6080 /*
6081 * The device is idle with no requests in the queue,
6082 * allow background operations if bkops status shows
6083 * that performance might be impacted.
6084 */
6085 ret = ufshcd_urgent_bkops(hba);
6086 if (ret)
6087 goto enable_gating;
6088 } else {
6089 /* make sure that auto bkops is disabled */
6090 ufshcd_disable_auto_bkops(hba);
6091 }
57d104c1
SJ		 6092 }
6093
6094 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
6095 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
6096 !ufshcd_is_runtime_pm(pm_op))) {
6097 /* ensure that bkops is disabled */
6098 ufshcd_disable_auto_bkops(hba);
6099 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
6100 if (ret)
1ab27c9c 6101 goto enable_gating;
57d104c1
SJ		 6102 }
6103
6104 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
6105 if (ret)
6106 goto set_dev_active;
6107
6108 ufshcd_vreg_set_lpm(hba);
6109
6110disable_clks:
6111 /*
6112 * Call vendor specific suspend callback. As these callbacks may access
6113 * vendor specific host controller register space call them before the
6114 * host clocks are ON.
6115 */
0263bcd0
YG		 6116 ret = ufshcd_vops_suspend(hba, pm_op);
6117 if (ret)
6118 goto set_link_active;
57d104c1 6119
57d104c1
SJ		 6120 if (!ufshcd_is_link_active(hba))
6121 ufshcd_setup_clocks(hba, false);
6122 else
6123 /* If link is active, device ref_clk can't be switched off */
6124 __ufshcd_setup_clocks(hba, false, true);
6125
1ab27c9c 6126 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 6127 /*
6128 * Disable the host irq as host controller as there won't be any
0263bcd0 6129 * host controller transaction expected till resume.
57d104c1
SJ		 6130 */
6131 ufshcd_disable_irq(hba);
6132 /* Put the host controller in low power mode if possible */
6133 ufshcd_hba_vreg_set_lpm(hba);
6134 goto out;
6135
57d104c1 6136set_link_active:
a508253d 6137 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 6138 ufshcd_vreg_set_hpm(hba);
6139 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
6140 ufshcd_set_link_active(hba);
6141 else if (ufshcd_is_link_off(hba))
6142 ufshcd_host_reset_and_restore(hba);
6143set_dev_active:
6144 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
6145 ufshcd_disable_auto_bkops(hba);
1ab27c9c 6146enable_gating:
d6fcf81a 6147 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 6148 hba->clk_gating.is_suspended = false;
6149 ufshcd_release(hba);
57d104c1
SJ		 6150out:
6151 hba->pm_op_in_progress = 0;
6152 return ret;
7a3e97b0
SY		 6153}
6154
6155/**
57d104c1 6156 * ufshcd_resume - helper function for resume operations
3b1d0580 6157 * @hba: per adapter instance
57d104c1 6158 * @pm_op: runtime PM or system PM
7a3e97b0 6159 *
57d104c1
SJ		 6160 * This function basically brings the UFS device, UniPro link and controller
6161 * to active state.
6162 *
6163 * Returns 0 for success and non-zero for failure
7a3e97b0 6164 */
57d104c1 6165static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6166{
57d104c1
SJ		 6167 int ret;
6168 enum uic_link_state old_link_state;
6169
6170 hba->pm_op_in_progress = 1;
6171 old_link_state = hba->uic_link_state;
6172
6173 ufshcd_hba_vreg_set_hpm(hba);
6174 /* Make sure clocks are enabled before accessing controller */
6175 ret = ufshcd_setup_clocks(hba, true);
6176 if (ret)
6177 goto out;
6178
57d104c1
SJ		 6179 /* enable the host irq as host controller would be active soon */
6180 ret = ufshcd_enable_irq(hba);
6181 if (ret)
6182 goto disable_irq_and_vops_clks;
6183
6184 ret = ufshcd_vreg_set_hpm(hba);
6185 if (ret)
6186 goto disable_irq_and_vops_clks;
6187
7a3e97b0 6188 /*
57d104c1
SJ		 6189 * Call vendor specific resume callback. As these callbacks may access
6190 * vendor specific host controller register space call them when the
6191 * host clocks are ON.
7a3e97b0 6192 */
0263bcd0
YG		 6193 ret = ufshcd_vops_resume(hba, pm_op);
6194 if (ret)
6195 goto disable_vreg;
57d104c1
SJ		 6196
6197 if (ufshcd_is_link_hibern8(hba)) {
6198 ret = ufshcd_uic_hibern8_exit(hba);
6199 if (!ret)
6200 ufshcd_set_link_active(hba);
6201 else
6202 goto vendor_suspend;
6203 } else if (ufshcd_is_link_off(hba)) {
6204 ret = ufshcd_host_reset_and_restore(hba);
6205 /*
6206 * ufshcd_host_reset_and_restore() should have already
6207 * set the link state as active
6208 */
6209 if (ret || !ufshcd_is_link_active(hba))
6210 goto vendor_suspend;
6211 }
6212
6213 if (!ufshcd_is_ufs_dev_active(hba)) {
6214 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6215 if (ret)
6216 goto set_old_link_state;
6217 }
6218
374a246e
SJ		 6219 /*
6220 * If BKOPs operations are urgently needed at this moment then
6221 * keep auto-bkops enabled or else disable it.
6222 */
6223 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 6224 hba->clk_gating.is_suspended = false;
6225
a508253d 6226 ufshcd_resume_clkscaling(hba);
856b3483 6227
1ab27c9c
ST		 6228 /* Schedule clock gating in case of no access to UFS device yet */
6229 ufshcd_release(hba);
57d104c1
SJ		 6230 goto out;
6231
6232set_old_link_state:
6233 ufshcd_link_state_transition(hba, old_link_state, 0);
6234vendor_suspend:
0263bcd0 6235 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 6236disable_vreg:
6237 ufshcd_vreg_set_lpm(hba);
6238disable_irq_and_vops_clks:
6239 ufshcd_disable_irq(hba);
a508253d 6240 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 6241 ufshcd_setup_clocks(hba, false);
6242out:
6243 hba->pm_op_in_progress = 0;
6244 return ret;
6245}
6246
6247/**
6248 * ufshcd_system_suspend - system suspend routine
6249 * @hba: per adapter instance
6250 * @pm_op: runtime PM or system PM
6251 *
6252 * Check the description of ufshcd_suspend() function for more details.
6253 *
6254 * Returns 0 for success and non-zero for failure
6255 */
6256int ufshcd_system_suspend(struct ufs_hba *hba)
6257{
6258 int ret = 0;
6259
6260 if (!hba || !hba->is_powered)
233b594b 6261 return 0;
57d104c1
SJ		 6262
6263 if (pm_runtime_suspended(hba->dev)) {
6264 if (hba->rpm_lvl == hba->spm_lvl)
6265 /*
6266 * There is possibility that device may still be in
6267 * active state during the runtime suspend.
6268 */
6269 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6270 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
6271 goto out;
6272
6273 /*
6274 * UFS device and/or UFS link low power states during runtime
6275 * suspend seems to be different than what is expected during
6276 * system suspend. Hence runtime resume the devic & link and
6277 * let the system suspend low power states to take effect.
6278 * TODO: If resume takes longer time, we might have optimize
6279 * it in future by not resuming everything if possible.
6280 */
6281 ret = ufshcd_runtime_resume(hba);
6282 if (ret)
6283 goto out;
6284 }
6285
6286 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6287out:
e785060e
DR		 6288 if (!ret)
6289 hba->is_sys_suspended = true;
57d104c1
SJ		 6290 return ret;
6291}
6292EXPORT_SYMBOL(ufshcd_system_suspend);
6293
6294/**
6295 * ufshcd_system_resume - system resume routine
6296 * @hba: per adapter instance
6297 *
6298 * Returns 0 for success and non-zero for failure
6299 */
7a3e97b0 6300
57d104c1
SJ		 6301int ufshcd_system_resume(struct ufs_hba *hba)
6302{
e3ce73d6
YG		 6303 if (!hba)
6304 return -EINVAL;
6305
6306 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 6307 /*
6308 * Let the runtime resume take care of resuming
6309 * if runtime suspended.
6310 */
6311 return 0;
6312
6313 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 6314}
57d104c1 6315EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6316
57d104c1
SJ		 6317/**
6318 * ufshcd_runtime_suspend - runtime suspend routine
6319 * @hba: per adapter instance
6320 *
6321 * Check the description of ufshcd_suspend() function for more details.
6322 *
6323 * Returns 0 for success and non-zero for failure
6324 */
66ec6d59
SRT		 6325int ufshcd_runtime_suspend(struct ufs_hba *hba)
6326{
e3ce73d6
YG		 6327 if (!hba)
6328 return -EINVAL;
6329
6330 if (!hba->is_powered)
66ec6d59
SRT		 6331 return 0;
6332
57d104c1 6333 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6334}
6335EXPORT_SYMBOL(ufshcd_runtime_suspend);
6336
57d104c1
SJ		 6337/**
6338 * ufshcd_runtime_resume - runtime resume routine
6339 * @hba: per adapter instance
6340 *
6341 * This function basically brings the UFS device, UniPro link and controller
6342 * to active state. Following operations are done in this function:
6343 *
6344 * 1. Turn on all the controller related clocks
6345 * 2. Bring the UniPro link out of Hibernate state
6346 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6347 * to active state.
6348 * 4. If auto-bkops is enabled on the device, disable it.
6349 *
6350 * So following would be the possible power state after this function return
6351 * successfully:
6352 * S1: UFS device in Active state with VCC rail ON
6353 * UniPro link in Active state
6354 * All the UFS/UniPro controller clocks are ON
6355 *
6356 * Returns 0 for success and non-zero for failure
6357 */
66ec6d59
SRT		 6358int ufshcd_runtime_resume(struct ufs_hba *hba)
6359{
e3ce73d6
YG		 6360 if (!hba)
6361 return -EINVAL;
6362
6363 if (!hba->is_powered)
66ec6d59 6364 return 0;
e3ce73d6
YG		 6365
6366 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6367}
6368EXPORT_SYMBOL(ufshcd_runtime_resume);
6369
6370int ufshcd_runtime_idle(struct ufs_hba *hba)
6371{
6372 return 0;
6373}
6374EXPORT_SYMBOL(ufshcd_runtime_idle);
6375
57d104c1
SJ		 6376/**
6377 * ufshcd_shutdown - shutdown routine
6378 * @hba: per adapter instance
6379 *
6380 * This function would power off both UFS device and UFS link.
6381 *
6382 * Returns 0 always to allow force shutdown even in case of errors.
6383 */
6384int ufshcd_shutdown(struct ufs_hba *hba)
6385{
6386 int ret = 0;
6387
6388 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6389 goto out;
6390
6391 if (pm_runtime_suspended(hba->dev)) {
6392 ret = ufshcd_runtime_resume(hba);
6393 if (ret)
6394 goto out;
6395 }
6396
6397 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6398out:
6399 if (ret)
6400 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6401 /* allow force shutdown even in case of errors */
6402 return 0;
6403}
6404EXPORT_SYMBOL(ufshcd_shutdown);
6405
7a3e97b0 6406/**
3b1d0580 6407 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6408 * data structure memory
3b1d0580 6409 * @hba - per adapter instance
7a3e97b0 6410 */
3b1d0580 6411void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6412{
cfdf9c91 6413 scsi_remove_host(hba->host);
7a3e97b0 6414 /* disable interrupts */
2fbd009b 6415 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6416 ufshcd_hba_stop(hba, true);
7a3e97b0 6417
1ab27c9c 6418 ufshcd_exit_clk_gating(hba);
aa497613 6419 ufshcd_hba_exit(hba);
3b1d0580
VH		 6420}
6421EXPORT_SYMBOL_GPL(ufshcd_remove);
6422
47555a5c
YG		 6423/**
6424 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6425 * @hba: pointer to Host Bus Adapter (HBA)
6426 */
6427void ufshcd_dealloc_host(struct ufs_hba *hba)
6428{
6429 scsi_host_put(hba->host);
6430}
6431EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6432
ca3d7bf9
AM		 6433/**
6434 * ufshcd_set_dma_mask - Set dma mask based on the controller
6435 * addressing capability
6436 * @hba: per adapter instance
6437 *
6438 * Returns 0 for success, non-zero for failure
6439 */
6440static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6441{
6442 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6443 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6444 return 0;
6445 }
6446 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6447}
6448
7a3e97b0 6449/**
5c0c28a8 6450 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 6451 * @dev: pointer to device handle
6452 * @hba_handle: driver private handle
7a3e97b0
SY		 6453 * Returns 0 on success, non-zero value on failure
6454 */
5c0c28a8 6455int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 6456{
6457 struct Scsi_Host *host;
6458 struct ufs_hba *hba;
5c0c28a8 6459 int err = 0;
7a3e97b0 6460
3b1d0580
VH		 6461 if (!dev) {
6462 dev_err(dev,
6463 "Invalid memory reference for dev is NULL\n");
6464 err = -ENODEV;
7a3e97b0
SY		 6465 goto out_error;
6466 }
6467
7a3e97b0
SY		 6468 host = scsi_host_alloc(&ufshcd_driver_template,
6469 sizeof(struct ufs_hba));
6470 if (!host) {
3b1d0580 6471 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6472 err = -ENOMEM;
3b1d0580 6473 goto out_error;
7a3e97b0
SY		 6474 }
6475 hba = shost_priv(host);
7a3e97b0 6476 hba->host = host;
3b1d0580 6477 hba->dev = dev;
5c0c28a8
SRT		 6478 *hba_handle = hba;
6479
6480out_error:
6481 return err;
6482}
6483EXPORT_SYMBOL(ufshcd_alloc_host);
6484
856b3483
ST		 6485static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6486{
6487 int ret = 0;
6488 struct ufs_clk_info *clki;
6489 struct list_head *head = &hba->clk_list_head;
6490
6491 if (!head || list_empty(head))
6492 goto out;
6493
f06fcc71
YG		 6494 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
6495 if (ret)
6496 return ret;
6497
856b3483
ST		 6498 list_for_each_entry(clki, head, list) {
6499 if (!IS_ERR_OR_NULL(clki->clk)) {
6500 if (scale_up && clki->max_freq) {
6501 if (clki->curr_freq == clki->max_freq)
6502 continue;
6503 ret = clk_set_rate(clki->clk, clki->max_freq);
6504 if (ret) {
6505 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6506 __func__, clki->name,
6507 clki->max_freq, ret);
6508 break;
6509 }
6510 clki->curr_freq = clki->max_freq;
6511
6512 } else if (!scale_up && clki->min_freq) {
6513 if (clki->curr_freq == clki->min_freq)
6514 continue;
6515 ret = clk_set_rate(clki->clk, clki->min_freq);
6516 if (ret) {
6517 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6518 __func__, clki->name,
6519 clki->min_freq, ret);
6520 break;
6521 }
6522 clki->curr_freq = clki->min_freq;
6523 }
6524 }
6525 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
6526 clki->name, clk_get_rate(clki->clk));
6527 }
f06fcc71
YG		 6528
6529 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
6530
856b3483
ST		 6531out:
6532 return ret;
6533}
6534
6535static int ufshcd_devfreq_target(struct device *dev,
6536 unsigned long *freq, u32 flags)
6537{
6538 int err = 0;
6539 struct ufs_hba *hba = dev_get_drvdata(dev);
30fc33f1
SJ		 6540 bool release_clk_hold = false;
6541 unsigned long irq_flags;
856b3483
ST		 6542
6543 if (!ufshcd_is_clkscaling_enabled(hba))
6544 return -EINVAL;
6545
30fc33f1
SJ		 6546 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6547 if (ufshcd_eh_in_progress(hba)) {
6548 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6549 return 0;
6550 }
6551
6552 if (ufshcd_is_clkgating_allowed(hba) &&
6553 (hba->clk_gating.state != CLKS_ON)) {
6554 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
6555 /* hold the vote until the scaling work is completed */
6556 hba->clk_gating.active_reqs++;
6557 release_clk_hold = true;
6558 hba->clk_gating.state = CLKS_ON;
6559 } else {
6560 /*
6561 * Clock gating work seems to be running in parallel
6562 * hence skip scaling work to avoid deadlock between
6563 * current scaling work and gating work.
6564 */
6565 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6566 return 0;
6567 }
6568 }
6569 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6570
856b3483
ST		 6571 if (*freq == UINT_MAX)
6572 err = ufshcd_scale_clks(hba, true);
6573 else if (*freq == 0)
6574 err = ufshcd_scale_clks(hba, false);
6575
30fc33f1
SJ		 6576 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6577 if (release_clk_hold)
6578 __ufshcd_release(hba);
6579 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6580
856b3483
ST		 6581 return err;
6582}
6583
6584static int ufshcd_devfreq_get_dev_status(struct device *dev,
6585 struct devfreq_dev_status *stat)
6586{
6587 struct ufs_hba *hba = dev_get_drvdata(dev);
6588 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
6589 unsigned long flags;
6590
6591 if (!ufshcd_is_clkscaling_enabled(hba))
6592 return -EINVAL;
6593
6594 memset(stat, 0, sizeof(*stat));
6595
6596 spin_lock_irqsave(hba->host->host_lock, flags);
6597 if (!scaling->window_start_t)
6598 goto start_window;
6599
6600 if (scaling->is_busy_started)
6601 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
6602 scaling->busy_start_t));
6603
6604 stat->total_time = jiffies_to_usecs((long)jiffies -
6605 (long)scaling->window_start_t);
6606 stat->busy_time = scaling->tot_busy_t;
6607start_window:
6608 scaling->window_start_t = jiffies;
6609 scaling->tot_busy_t = 0;
6610
6611 if (hba->outstanding_reqs) {
6612 scaling->busy_start_t = ktime_get();
6613 scaling->is_busy_started = true;
6614 } else {
6615 scaling->busy_start_t = ktime_set(0, 0);
6616 scaling->is_busy_started = false;
6617 }
6618 spin_unlock_irqrestore(hba->host->host_lock, flags);
6619 return 0;
6620}
6621
6622static struct devfreq_dev_profile ufs_devfreq_profile = {
6623 .polling_ms = 100,
6624 .target = ufshcd_devfreq_target,
6625 .get_dev_status = ufshcd_devfreq_get_dev_status,
6626};
6627
5c0c28a8
SRT		 6628/**
6629 * ufshcd_init - Driver initialization routine
6630 * @hba: per-adapter instance
6631 * @mmio_base: base register address
6632 * @irq: Interrupt line of device
6633 * Returns 0 on success, non-zero value on failure
6634 */
6635int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
6636{
6637 int err;
6638 struct Scsi_Host *host = hba->host;
6639 struct device *dev = hba->dev;
6640
6641 if (!mmio_base) {
6642 dev_err(hba->dev,
6643 "Invalid memory reference for mmio_base is NULL\n");
6644 err = -ENODEV;
6645 goto out_error;
6646 }
6647
3b1d0580
VH		 6648 hba->mmio_base = mmio_base;
6649 hba->irq = irq;
7a3e97b0 6650
aa497613 6651 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 6652 if (err)
6653 goto out_error;
6654
7a3e97b0
SY		 6655 /* Read capabilities registers */
6656 ufshcd_hba_capabilities(hba);
6657
6658 /* Get UFS version supported by the controller */
6659 hba->ufs_version = ufshcd_get_ufs_version(hba);
6660
2fbd009b
SJ		 6661 /* Get Interrupt bit mask per version */
6662 hba->intr_mask = ufshcd_get_intr_mask(hba);
6663
ca3d7bf9
AM		 6664 err = ufshcd_set_dma_mask(hba);
6665 if (err) {
6666 dev_err(hba->dev, "set dma mask failed\n");
6667 goto out_disable;
6668 }
6669
7a3e97b0
SY		 6670 /* Allocate memory for host memory space */
6671 err = ufshcd_memory_alloc(hba);
6672 if (err) {
3b1d0580
VH		 6673 dev_err(hba->dev, "Memory allocation failed\n");
6674 goto out_disable;
7a3e97b0
SY		 6675 }
6676
6677 /* Configure LRB */
6678 ufshcd_host_memory_configure(hba);
6679
6680 host->can_queue = hba->nutrs;
6681 host->cmd_per_lun = hba->nutrs;
6682 host->max_id = UFSHCD_MAX_ID;
0ce147d4 6683 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 6684 host->max_channel = UFSHCD_MAX_CHANNEL;
6685 host->unique_id = host->host_no;
6686 host->max_cmd_len = MAX_CDB_SIZE;
6687
7eb584db
DR		 6688 hba->max_pwr_info.is_valid = false;
6689
7a3e97b0 6690 /* Initailize wait queue for task management */
e2933132
SRT		 6691 init_waitqueue_head(&hba->tm_wq);
6692 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 6693
6694 /* Initialize work queues */
e8e7f271 6695 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 6696 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 6697
6ccf44fe
SJ		 6698 /* Initialize UIC command mutex */
6699 mutex_init(&hba->uic_cmd_mutex);
6700
5a0b0cb9
SRT		 6701 /* Initialize mutex for device management commands */
6702 mutex_init(&hba->dev_cmd.lock);
6703
6704 /* Initialize device management tag acquire wait queue */
6705 init_waitqueue_head(&hba->dev_cmd.tag_wq);
6706
1ab27c9c 6707 ufshcd_init_clk_gating(hba);
199ef13c
YG		 6708
6709 /*
6710 * In order to avoid any spurious interrupt immediately after
6711 * registering UFS controller interrupt handler, clear any pending UFS
6712 * interrupt status and disable all the UFS interrupts.
6713 */
6714 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
6715 REG_INTERRUPT_STATUS);
6716 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
6717 /*
6718 * Make sure that UFS interrupts are disabled and any pending interrupt
6719 * status is cleared before registering UFS interrupt handler.
6720 */
6721 mb();
6722
7a3e97b0 6723 /* IRQ registration */
2953f850 6724 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 6725 if (err) {
3b1d0580 6726 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 6727 goto exit_gating;
57d104c1
SJ		 6728 } else {
6729 hba->is_irq_enabled = true;
7a3e97b0
SY		 6730 }
6731
3b1d0580 6732 err = scsi_add_host(host, hba->dev);
7a3e97b0 6733 if (err) {
3b1d0580 6734 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 6735 goto exit_gating;
7a3e97b0
SY		 6736 }
6737
6ccf44fe
SJ		 6738 /* Host controller enable */
6739 err = ufshcd_hba_enable(hba);
7a3e97b0 6740 if (err) {
6ccf44fe 6741 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 6742 goto out_remove_scsi_host;
7a3e97b0 6743 }
6ccf44fe 6744
856b3483 6745 if (ufshcd_is_clkscaling_enabled(hba)) {
4861ee15 6746 hba->devfreq = devm_devfreq_add_device(dev, &ufs_devfreq_profile,
856b3483
ST		 6747 "simple_ondemand", NULL);
6748 if (IS_ERR(hba->devfreq)) {
6749 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
6750 PTR_ERR(hba->devfreq));
73811c94 6751 err = PTR_ERR(hba->devfreq);
856b3483
ST		 6752 goto out_remove_scsi_host;
6753 }
6754 /* Suspend devfreq until the UFS device is detected */
a508253d 6755 ufshcd_suspend_clkscaling(hba);
856b3483
ST		 6756 }
6757
62694735
SRT		 6758 /* Hold auto suspend until async scan completes */
6759 pm_runtime_get_sync(dev);
6760
57d104c1 6761 /*
7caf489b 6762 * We are assuming that device wasn't put in sleep/power-down
6763 * state exclusively during the boot stage before kernel.
6764 * This assumption helps avoid doing link startup twice during
6765 * ufshcd_probe_hba().
57d104c1 6766 */
7caf489b 6767 ufshcd_set_ufs_dev_active(hba);
57d104c1 6768
6ccf44fe
SJ		 6769 async_schedule(ufshcd_async_scan, hba);
6770
7a3e97b0
SY		 6771 return 0;
6772
3b1d0580
VH		 6773out_remove_scsi_host:
6774 scsi_remove_host(hba->host);
1ab27c9c
ST		 6775exit_gating:
6776 ufshcd_exit_clk_gating(hba);
3b1d0580 6777out_disable:
57d104c1 6778 hba->is_irq_enabled = false;
aa497613 6779 ufshcd_hba_exit(hba);
3b1d0580
VH		 6780out_error:
6781 return err;
6782}
6783EXPORT_SYMBOL_GPL(ufshcd_init);
6784
3b1d0580
VH		 6785MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
6786MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 6787MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 6788MODULE_LICENSE("GPL");
6789MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)