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ufs: fix reference counting of W-LUs
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
5c0c28a8 6 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
6ccf44fe 42
e0eca63e 43#include "ufshcd.h"
53b3d9c3 44#include "unipro.h"
7a3e97b0 45
2fbd009b
SJ		 46#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
47 UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 49/* UIC command timeout, unit: ms */
50#define UIC_CMD_TIMEOUT 500
2fbd009b 51
5a0b0cb9
SRT		 52/* NOP OUT retries waiting for NOP IN response */
53#define NOP_OUT_RETRIES 10
54/* Timeout after 30 msecs if NOP OUT hangs without response */
55#define NOP_OUT_TIMEOUT 30 /* msecs */
56
68078d5c
DR		 57/* Query request retries */
58#define QUERY_REQ_RETRIES 10
59/* Query request timeout */
60#define QUERY_REQ_TIMEOUT 30 /* msec */
61
e2933132
SRT		 62/* Task management command timeout */
63#define TM_CMD_TIMEOUT 100 /* msecs */
64
1d337ec2
SRT		 65/* maximum number of link-startup retries */
66#define DME_LINKSTARTUP_RETRIES 3
67
68/* maximum number of reset retries before giving up */
69#define MAX_HOST_RESET_RETRIES 5
70
68078d5c
DR		 71/* Expose the flag value from utp_upiu_query.value */
72#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
73
7d568652
SJ		 74/* Interrupt aggregation default timeout, unit: 40us */
75#define INT_AGGR_DEF_TO 0x02
76
aa497613
SRT		 77#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
78 ({ \
79 int _ret; \
80 if (_on) \
81 _ret = ufshcd_enable_vreg(_dev, _vreg); \
82 else \
83 _ret = ufshcd_disable_vreg(_dev, _vreg); \
84 _ret; \
85 })
86
da461cec
SJ		 87static u32 ufs_query_desc_max_size[] = {
88 QUERY_DESC_DEVICE_MAX_SIZE,
89 QUERY_DESC_CONFIGURAION_MAX_SIZE,
90 QUERY_DESC_UNIT_MAX_SIZE,
91 QUERY_DESC_RFU_MAX_SIZE,
92 QUERY_DESC_INTERCONNECT_MAX_SIZE,
93 QUERY_DESC_STRING_MAX_SIZE,
94 QUERY_DESC_RFU_MAX_SIZE,
95 QUERY_DESC_GEOMETRY_MAZ_SIZE,
96 QUERY_DESC_POWER_MAX_SIZE,
97 QUERY_DESC_RFU_MAX_SIZE,
98};
99
7a3e97b0
SY		 100enum {
101 UFSHCD_MAX_CHANNEL = 0,
102 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 103 UFSHCD_CMD_PER_LUN = 32,
104 UFSHCD_CAN_QUEUE = 32,
105};
106
107/* UFSHCD states */
108enum {
7a3e97b0
SY		 109 UFSHCD_STATE_RESET,
110 UFSHCD_STATE_ERROR,
3441da7d
SRT		 111 UFSHCD_STATE_OPERATIONAL,
112};
113
114/* UFSHCD error handling flags */
115enum {
116 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 117};
118
e8e7f271
SRT		 119/* UFSHCD UIC layer error flags */
120enum {
121 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
122 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
123 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
124 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
125};
126
7a3e97b0
SY		 127/* Interrupt configuration options */
128enum {
129 UFSHCD_INT_DISABLE,
130 UFSHCD_INT_ENABLE,
131 UFSHCD_INT_CLEAR,
132};
133
3441da7d
SRT		 134#define ufshcd_set_eh_in_progress(h) \
135 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
136#define ufshcd_eh_in_progress(h) \
137 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
138#define ufshcd_clear_eh_in_progress(h) \
139 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
140
57d104c1
SJ		 141#define ufshcd_set_ufs_dev_active(h) \
142 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
143#define ufshcd_set_ufs_dev_sleep(h) \
144 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
145#define ufshcd_set_ufs_dev_poweroff(h) \
146 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
147#define ufshcd_is_ufs_dev_active(h) \
148 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
149#define ufshcd_is_ufs_dev_sleep(h) \
150 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
151#define ufshcd_is_ufs_dev_poweroff(h) \
152 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
153
154static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
155 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
156 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
157 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
158 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
159 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
161};
162
163static inline enum ufs_dev_pwr_mode
164ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
165{
166 return ufs_pm_lvl_states[lvl].dev_state;
167}
168
169static inline enum uic_link_state
170ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].link_state;
173}
174
3441da7d
SRT		 175static void ufshcd_tmc_handler(struct ufs_hba *hba);
176static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 177static int ufshcd_reset_and_restore(struct ufs_hba *hba);
178static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 179static void ufshcd_hba_exit(struct ufs_hba *hba);
180static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 181static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
182 bool skip_ref_clk);
183static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
184static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
185static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
57d104c1
SJ		 186static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
187static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 188static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
189 struct ufs_pa_layer_attr *desired_pwr_mode);
57d104c1
SJ		 190
191static inline int ufshcd_enable_irq(struct ufs_hba *hba)
192{
193 int ret = 0;
194
195 if (!hba->is_irq_enabled) {
196 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
197 hba);
198 if (ret)
199 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
200 __func__, ret);
201 hba->is_irq_enabled = true;
202 }
203
204 return ret;
205}
206
207static inline void ufshcd_disable_irq(struct ufs_hba *hba)
208{
209 if (hba->is_irq_enabled) {
210 free_irq(hba->irq, hba);
211 hba->is_irq_enabled = false;
212 }
213}
3441da7d 214
5a0b0cb9
SRT		 215/*
216 * ufshcd_wait_for_register - wait for register value to change
217 * @hba - per-adapter interface
218 * @reg - mmio register offset
219 * @mask - mask to apply to read register value
220 * @val - wait condition
221 * @interval_us - polling interval in microsecs
222 * @timeout_ms - timeout in millisecs
223 *
224 * Returns -ETIMEDOUT on error, zero on success
225 */
226static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
227 u32 val, unsigned long interval_us, unsigned long timeout_ms)
228{
229 int err = 0;
230 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
231
232 /* ignore bits that we don't intend to wait on */
233 val = val & mask;
234
235 while ((ufshcd_readl(hba, reg) & mask) != val) {
236 /* wakeup within 50us of expiry */
237 usleep_range(interval_us, interval_us + 50);
238
239 if (time_after(jiffies, timeout)) {
240 if ((ufshcd_readl(hba, reg) & mask) != val)
241 err = -ETIMEDOUT;
242 break;
243 }
244 }
245
246 return err;
247}
248
2fbd009b
SJ		 249/**
250 * ufshcd_get_intr_mask - Get the interrupt bit mask
251 * @hba - Pointer to adapter instance
252 *
253 * Returns interrupt bit mask per version
254 */
255static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
256{
257 if (hba->ufs_version == UFSHCI_VERSION_10)
258 return INTERRUPT_MASK_ALL_VER_10;
259 else
260 return INTERRUPT_MASK_ALL_VER_11;
261}
262
7a3e97b0
SY		 263/**
264 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
265 * @hba - Pointer to adapter instance
266 *
267 * Returns UFSHCI version supported by the controller
268 */
269static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
270{
b873a275 271 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 272}
273
274/**
275 * ufshcd_is_device_present - Check if any device connected to
276 * the host controller
5c0c28a8 277 * @hba: pointer to adapter instance
7a3e97b0 278 *
73ec513a 279 * Returns 1 if device present, 0 if no device detected
7a3e97b0 280 */
5c0c28a8 281static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 282{
5c0c28a8
SRT		 283 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
284 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 285}
286
287/**
288 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
289 * @lrb: pointer to local command reference block
290 *
291 * This function is used to get the OCS field from UTRD
292 * Returns the OCS field in the UTRD
293 */
294static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
295{
e8c8e82a 296 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 297}
298
299/**
300 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
301 * @task_req_descp: pointer to utp_task_req_desc structure
302 *
303 * This function is used to get the OCS field from UTMRD
304 * Returns the OCS field in the UTMRD
305 */
306static inline int
307ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
308{
e8c8e82a 309 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 310}
311
312/**
313 * ufshcd_get_tm_free_slot - get a free slot for task management request
314 * @hba: per adapter instance
e2933132 315 * @free_slot: pointer to variable with available slot value
7a3e97b0 316 *
e2933132
SRT		 317 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
318 * Returns 0 if free slot is not available, else return 1 with tag value
319 * in @free_slot.
7a3e97b0 320 */
e2933132 321static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 322{
e2933132
SRT		 323 int tag;
324 bool ret = false;
325
326 if (!free_slot)
327 goto out;
328
329 do {
330 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
331 if (tag >= hba->nutmrs)
332 goto out;
333 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
334
335 *free_slot = tag;
336 ret = true;
337out:
338 return ret;
339}
340
341static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
342{
343 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 344}
345
346/**
347 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
348 * @hba: per adapter instance
349 * @pos: position of the bit to be cleared
350 */
351static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
352{
b873a275 353 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 354}
355
356/**
357 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
358 * @reg: Register value of host controller status
359 *
360 * Returns integer, 0 on Success and positive value if failed
361 */
362static inline int ufshcd_get_lists_status(u32 reg)
363{
364 /*
365 * The mask 0xFF is for the following HCS register bits
366 * Bit Description
367 * 0 Device Present
368 * 1 UTRLRDY
369 * 2 UTMRLRDY
370 * 3 UCRDY
371 * 4 HEI
372 * 5 DEI
373 * 6-7 reserved
374 */
375 return (((reg) & (0xFF)) >> 1) ^ (0x07);
376}
377
378/**
379 * ufshcd_get_uic_cmd_result - Get the UIC command result
380 * @hba: Pointer to adapter instance
381 *
382 * This function gets the result of UIC command completion
383 * Returns 0 on success, non zero value on error
384 */
385static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
386{
b873a275 387 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 388 MASK_UIC_COMMAND_RESULT;
389}
390
12b4fdb4
SJ		 391/**
392 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
393 * @hba: Pointer to adapter instance
394 *
395 * This function gets UIC command argument3
396 * Returns 0 on success, non zero value on error
397 */
398static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
399{
400 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
401}
402
7a3e97b0 403/**
5a0b0cb9 404 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 405 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 406 */
407static inline int
5a0b0cb9 408ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 409{
5a0b0cb9 410 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 411}
412
413/**
414 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
415 * @ucd_rsp_ptr: pointer to response UPIU
416 *
417 * This function gets the response status and scsi_status from response UPIU
418 * Returns the response result code.
419 */
420static inline int
421ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
422{
423 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
424}
425
1c2623c5
SJ		 426/*
427 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
428 * from response UPIU
429 * @ucd_rsp_ptr: pointer to response UPIU
430 *
431 * Return the data segment length.
432 */
433static inline unsigned int
434ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
435{
436 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
437 MASK_RSP_UPIU_DATA_SEG_LEN;
438}
439
66ec6d59
SRT		 440/**
441 * ufshcd_is_exception_event - Check if the device raised an exception event
442 * @ucd_rsp_ptr: pointer to response UPIU
443 *
444 * The function checks if the device raised an exception event indicated in
445 * the Device Information field of response UPIU.
446 *
447 * Returns true if exception is raised, false otherwise.
448 */
449static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
450{
451 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
452 MASK_RSP_EXCEPTION_EVENT ? true : false;
453}
454
7a3e97b0 455/**
7d568652 456 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 457 * @hba: per adapter instance
7a3e97b0
SY		 458 */
459static inline void
7d568652 460ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 461{
7d568652
SJ		 462 ufshcd_writel(hba, INT_AGGR_ENABLE |
463 INT_AGGR_COUNTER_AND_TIMER_RESET,
464 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
465}
466
467/**
468 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
469 * @hba: per adapter instance
470 * @cnt: Interrupt aggregation counter threshold
471 * @tmout: Interrupt aggregation timeout value
472 */
473static inline void
474ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
475{
476 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
477 INT_AGGR_COUNTER_THLD_VAL(cnt) |
478 INT_AGGR_TIMEOUT_VAL(tmout),
479 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 480}
481
482/**
483 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
484 * When run-stop registers are set to 1, it indicates the
485 * host controller that it can process the requests
486 * @hba: per adapter instance
487 */
488static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
489{
b873a275
SJ		 490 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
491 REG_UTP_TASK_REQ_LIST_RUN_STOP);
492 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
493 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 494}
495
7a3e97b0
SY		 496/**
497 * ufshcd_hba_start - Start controller initialization sequence
498 * @hba: per adapter instance
499 */
500static inline void ufshcd_hba_start(struct ufs_hba *hba)
501{
b873a275 502 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 503}
504
505/**
506 * ufshcd_is_hba_active - Get controller state
507 * @hba: per adapter instance
508 *
509 * Returns zero if controller is active, 1 otherwise
510 */
511static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
512{
b873a275 513 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 514}
515
1ab27c9c
ST		 516static void ufshcd_ungate_work(struct work_struct *work)
517{
518 int ret;
519 unsigned long flags;
520 struct ufs_hba *hba = container_of(work, struct ufs_hba,
521 clk_gating.ungate_work);
522
523 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
524
525 spin_lock_irqsave(hba->host->host_lock, flags);
526 if (hba->clk_gating.state == CLKS_ON) {
527 spin_unlock_irqrestore(hba->host->host_lock, flags);
528 goto unblock_reqs;
529 }
530
531 spin_unlock_irqrestore(hba->host->host_lock, flags);
532 ufshcd_setup_clocks(hba, true);
533
534 /* Exit from hibern8 */
535 if (ufshcd_can_hibern8_during_gating(hba)) {
536 /* Prevent gating in this path */
537 hba->clk_gating.is_suspended = true;
538 if (ufshcd_is_link_hibern8(hba)) {
539 ret = ufshcd_uic_hibern8_exit(hba);
540 if (ret)
541 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
542 __func__, ret);
543 else
544 ufshcd_set_link_active(hba);
545 }
546 hba->clk_gating.is_suspended = false;
547 }
548unblock_reqs:
856b3483
ST		 549 if (ufshcd_is_clkscaling_enabled(hba))
550 devfreq_resume_device(hba->devfreq);
1ab27c9c
ST		 551 scsi_unblock_requests(hba->host);
552}
553
554/**
555 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
556 * Also, exit from hibern8 mode and set the link as active.
557 * @hba: per adapter instance
558 * @async: This indicates whether caller should ungate clocks asynchronously.
559 */
560int ufshcd_hold(struct ufs_hba *hba, bool async)
561{
562 int rc = 0;
563 unsigned long flags;
564
565 if (!ufshcd_is_clkgating_allowed(hba))
566 goto out;
1ab27c9c
ST		 567 spin_lock_irqsave(hba->host->host_lock, flags);
568 hba->clk_gating.active_reqs++;
569
856b3483 570start:
1ab27c9c
ST		 571 switch (hba->clk_gating.state) {
572 case CLKS_ON:
573 break;
574 case REQ_CLKS_OFF:
575 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
576 hba->clk_gating.state = CLKS_ON;
577 break;
578 }
579 /*
580 * If we here, it means gating work is either done or
581 * currently running. Hence, fall through to cancel gating
582 * work and to enable clocks.
583 */
584 case CLKS_OFF:
585 scsi_block_requests(hba->host);
586 hba->clk_gating.state = REQ_CLKS_ON;
587 schedule_work(&hba->clk_gating.ungate_work);
588 /*
589 * fall through to check if we should wait for this
590 * work to be done or not.
591 */
592 case REQ_CLKS_ON:
593 if (async) {
594 rc = -EAGAIN;
595 hba->clk_gating.active_reqs--;
596 break;
597 }
598
599 spin_unlock_irqrestore(hba->host->host_lock, flags);
600 flush_work(&hba->clk_gating.ungate_work);
601 /* Make sure state is CLKS_ON before returning */
856b3483 602 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 603 goto start;
604 default:
605 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
606 __func__, hba->clk_gating.state);
607 break;
608 }
609 spin_unlock_irqrestore(hba->host->host_lock, flags);
610out:
611 return rc;
612}
613
614static void ufshcd_gate_work(struct work_struct *work)
615{
616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
617 clk_gating.gate_work.work);
618 unsigned long flags;
619
620 spin_lock_irqsave(hba->host->host_lock, flags);
621 if (hba->clk_gating.is_suspended) {
622 hba->clk_gating.state = CLKS_ON;
623 goto rel_lock;
624 }
625
626 if (hba->clk_gating.active_reqs
627 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
628 || hba->lrb_in_use || hba->outstanding_tasks
629 || hba->active_uic_cmd || hba->uic_async_done)
630 goto rel_lock;
631
632 spin_unlock_irqrestore(hba->host->host_lock, flags);
633
634 /* put the link into hibern8 mode before turning off clocks */
635 if (ufshcd_can_hibern8_during_gating(hba)) {
636 if (ufshcd_uic_hibern8_enter(hba)) {
637 hba->clk_gating.state = CLKS_ON;
638 goto out;
639 }
640 ufshcd_set_link_hibern8(hba);
641 }
642
856b3483
ST		 643 if (ufshcd_is_clkscaling_enabled(hba)) {
644 devfreq_suspend_device(hba->devfreq);
645 hba->clk_scaling.window_start_t = 0;
646 }
647
1ab27c9c
ST		 648 if (!ufshcd_is_link_active(hba))
649 ufshcd_setup_clocks(hba, false);
650 else
651 /* If link is active, device ref_clk can't be switched off */
652 __ufshcd_setup_clocks(hba, false, true);
653
654 /*
655 * In case you are here to cancel this work the gating state
656 * would be marked as REQ_CLKS_ON. In this case keep the state
657 * as REQ_CLKS_ON which would anyway imply that clocks are off
658 * and a request to turn them on is pending. By doing this way,
659 * we keep the state machine in tact and this would ultimately
660 * prevent from doing cancel work multiple times when there are
661 * new requests arriving before the current cancel work is done.
662 */
663 spin_lock_irqsave(hba->host->host_lock, flags);
664 if (hba->clk_gating.state == REQ_CLKS_OFF)
665 hba->clk_gating.state = CLKS_OFF;
666
667rel_lock:
668 spin_unlock_irqrestore(hba->host->host_lock, flags);
669out:
670 return;
671}
672
673/* host lock must be held before calling this variant */
674static void __ufshcd_release(struct ufs_hba *hba)
675{
676 if (!ufshcd_is_clkgating_allowed(hba))
677 return;
678
679 hba->clk_gating.active_reqs--;
680
681 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
682 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
683 || hba->lrb_in_use || hba->outstanding_tasks
684 || hba->active_uic_cmd || hba->uic_async_done)
685 return;
686
687 hba->clk_gating.state = REQ_CLKS_OFF;
688 schedule_delayed_work(&hba->clk_gating.gate_work,
689 msecs_to_jiffies(hba->clk_gating.delay_ms));
690}
691
692void ufshcd_release(struct ufs_hba *hba)
693{
694 unsigned long flags;
695
696 spin_lock_irqsave(hba->host->host_lock, flags);
697 __ufshcd_release(hba);
698 spin_unlock_irqrestore(hba->host->host_lock, flags);
699}
700
701static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
702 struct device_attribute *attr, char *buf)
703{
704 struct ufs_hba *hba = dev_get_drvdata(dev);
705
706 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
707}
708
709static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
710 struct device_attribute *attr, const char *buf, size_t count)
711{
712 struct ufs_hba *hba = dev_get_drvdata(dev);
713 unsigned long flags, value;
714
715 if (kstrtoul(buf, 0, &value))
716 return -EINVAL;
717
718 spin_lock_irqsave(hba->host->host_lock, flags);
719 hba->clk_gating.delay_ms = value;
720 spin_unlock_irqrestore(hba->host->host_lock, flags);
721 return count;
722}
723
724static void ufshcd_init_clk_gating(struct ufs_hba *hba)
725{
726 if (!ufshcd_is_clkgating_allowed(hba))
727 return;
728
729 hba->clk_gating.delay_ms = 150;
730 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
731 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
732
733 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
734 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
735 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
736 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
737 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
738 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
739 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
740}
741
742static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
743{
744 if (!ufshcd_is_clkgating_allowed(hba))
745 return;
746 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
747}
748
856b3483
ST		 749/* Must be called with host lock acquired */
750static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
751{
752 if (!ufshcd_is_clkscaling_enabled(hba))
753 return;
754
755 if (!hba->clk_scaling.is_busy_started) {
756 hba->clk_scaling.busy_start_t = ktime_get();
757 hba->clk_scaling.is_busy_started = true;
758 }
759}
760
761static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
762{
763 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
764
765 if (!ufshcd_is_clkscaling_enabled(hba))
766 return;
767
768 if (!hba->outstanding_reqs && scaling->is_busy_started) {
769 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
770 scaling->busy_start_t));
771 scaling->busy_start_t = ktime_set(0, 0);
772 scaling->is_busy_started = false;
773 }
774}
7a3e97b0
SY		 775/**
776 * ufshcd_send_command - Send SCSI or device management commands
777 * @hba: per adapter instance
778 * @task_tag: Task tag of the command
779 */
780static inline
781void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
782{
856b3483 783 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 784 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 785 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 786}
787
788/**
789 * ufshcd_copy_sense_data - Copy sense data in case of check condition
790 * @lrb - pointer to local reference block
791 */
792static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
793{
794 int len;
1c2623c5
SJ		 795 if (lrbp->sense_buffer &&
796 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 797 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 798 memcpy(lrbp->sense_buffer,
5a0b0cb9 799 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 800 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
801 }
802}
803
68078d5c
DR		 804/**
805 * ufshcd_copy_query_response() - Copy the Query Response and the data
806 * descriptor
807 * @hba: per adapter instance
808 * @lrb - pointer to local reference block
809 */
810static
c6d4a831 811int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 812{
813 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
814
68078d5c 815 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 816
68078d5c
DR		 817 /* Get the descriptor */
818 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 819 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 820 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 821 u16 resp_len;
822 u16 buf_len;
68078d5c
DR		 823
824 /* data segment length */
c6d4a831 825 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 826 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 827 buf_len = be16_to_cpu(
828 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 829 if (likely(buf_len >= resp_len)) {
830 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
831 } else {
832 dev_warn(hba->dev,
833 "%s: Response size is bigger than buffer",
834 __func__);
835 return -EINVAL;
836 }
68078d5c 837 }
c6d4a831
DR		 838
839 return 0;
68078d5c
DR		 840}
841
7a3e97b0
SY		 842/**
843 * ufshcd_hba_capabilities - Read controller capabilities
844 * @hba: per adapter instance
845 */
846static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
847{
b873a275 848 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 849
850 /* nutrs and nutmrs are 0 based values */
851 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
852 hba->nutmrs =
853 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
854}
855
856/**
6ccf44fe
SJ		 857 * ufshcd_ready_for_uic_cmd - Check if controller is ready
858 * to accept UIC commands
7a3e97b0 859 * @hba: per adapter instance
6ccf44fe
SJ		 860 * Return true on success, else false
861 */
862static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
863{
864 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
865 return true;
866 else
867 return false;
868}
869
53b3d9c3
SJ		 870/**
871 * ufshcd_get_upmcrs - Get the power mode change request status
872 * @hba: Pointer to adapter instance
873 *
874 * This function gets the UPMCRS field of HCS register
875 * Returns value of UPMCRS field
876 */
877static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
878{
879 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
880}
881
6ccf44fe
SJ		 882/**
883 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
884 * @hba: per adapter instance
885 * @uic_cmd: UIC command
886 *
887 * Mutex must be held.
7a3e97b0
SY		 888 */
889static inline void
6ccf44fe 890ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 891{
6ccf44fe
SJ		 892 WARN_ON(hba->active_uic_cmd);
893
894 hba->active_uic_cmd = uic_cmd;
895
7a3e97b0 896 /* Write Args */
6ccf44fe
SJ		 897 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
898 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
899 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 900
901 /* Write UIC Cmd */
6ccf44fe 902 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 903 REG_UIC_COMMAND);
7a3e97b0
SY		 904}
905
6ccf44fe
SJ		 906/**
907 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
908 * @hba: per adapter instance
909 * @uic_command: UIC command
910 *
911 * Must be called with mutex held.
912 * Returns 0 only if success.
913 */
914static int
915ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
916{
917 int ret;
918 unsigned long flags;
919
920 if (wait_for_completion_timeout(&uic_cmd->done,
921 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
922 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
923 else
924 ret = -ETIMEDOUT;
925
926 spin_lock_irqsave(hba->host->host_lock, flags);
927 hba->active_uic_cmd = NULL;
928 spin_unlock_irqrestore(hba->host->host_lock, flags);
929
930 return ret;
931}
932
933/**
934 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
935 * @hba: per adapter instance
936 * @uic_cmd: UIC command
937 *
938 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 939 * with mutex held and host_lock locked.
6ccf44fe
SJ		 940 * Returns 0 only if success.
941 */
942static int
943__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
944{
6ccf44fe
SJ		 945 if (!ufshcd_ready_for_uic_cmd(hba)) {
946 dev_err(hba->dev,
947 "Controller not ready to accept UIC commands\n");
948 return -EIO;
949 }
950
951 init_completion(&uic_cmd->done);
952
6ccf44fe 953 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 954
57d104c1 955 return 0;
6ccf44fe
SJ		 956}
957
958/**
959 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
960 * @hba: per adapter instance
961 * @uic_cmd: UIC command
962 *
963 * Returns 0 only if success.
964 */
965static int
966ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
967{
968 int ret;
57d104c1 969 unsigned long flags;
6ccf44fe 970
1ab27c9c 971 ufshcd_hold(hba, false);
6ccf44fe 972 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 973 spin_lock_irqsave(hba->host->host_lock, flags);
6ccf44fe 974 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
57d104c1
SJ		 975 spin_unlock_irqrestore(hba->host->host_lock, flags);
976 if (!ret)
977 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
978
6ccf44fe
SJ		 979 mutex_unlock(&hba->uic_cmd_mutex);
980
1ab27c9c 981 ufshcd_release(hba);
6ccf44fe
SJ		 982 return ret;
983}
984
7a3e97b0
SY		 985/**
986 * ufshcd_map_sg - Map scatter-gather list to prdt
987 * @lrbp - pointer to local reference block
988 *
989 * Returns 0 in case of success, non-zero value in case of failure
990 */
991static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
992{
993 struct ufshcd_sg_entry *prd_table;
994 struct scatterlist *sg;
995 struct scsi_cmnd *cmd;
996 int sg_segments;
997 int i;
998
999 cmd = lrbp->cmd;
1000 sg_segments = scsi_dma_map(cmd);
1001 if (sg_segments < 0)
1002 return sg_segments;
1003
1004 if (sg_segments) {
1005 lrbp->utr_descriptor_ptr->prd_table_length =
1006 cpu_to_le16((u16) (sg_segments));
1007
1008 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1009
1010 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1011 prd_table[i].size =
1012 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1013 prd_table[i].base_addr =
1014 cpu_to_le32(lower_32_bits(sg->dma_address));
1015 prd_table[i].upper_addr =
1016 cpu_to_le32(upper_32_bits(sg->dma_address));
1017 }
1018 } else {
1019 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1020 }
1021
1022 return 0;
1023}
1024
1025/**
2fbd009b 1026 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1027 * @hba: per adapter instance
2fbd009b 1028 * @intrs: interrupt bits
7a3e97b0 1029 */
2fbd009b 1030static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1031{
2fbd009b
SJ		 1032 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1033
1034 if (hba->ufs_version == UFSHCI_VERSION_10) {
1035 u32 rw;
1036 rw = set & INTERRUPT_MASK_RW_VER_10;
1037 set = rw | ((set ^ intrs) & intrs);
1038 } else {
1039 set |= intrs;
1040 }
1041
1042 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1043}
1044
1045/**
1046 * ufshcd_disable_intr - disable interrupts
1047 * @hba: per adapter instance
1048 * @intrs: interrupt bits
1049 */
1050static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1051{
1052 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1053
1054 if (hba->ufs_version == UFSHCI_VERSION_10) {
1055 u32 rw;
1056 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1057 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1058 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1059
1060 } else {
1061 set &= ~intrs;
7a3e97b0 1062 }
2fbd009b
SJ		 1063
1064 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1065}
1066
5a0b0cb9
SRT		 1067/**
1068 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1069 * descriptor according to request
1070 * @lrbp: pointer to local reference block
1071 * @upiu_flags: flags required in the header
1072 * @cmd_dir: requests data direction
1073 */
1074static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
1075 u32 *upiu_flags, enum dma_data_direction cmd_dir)
1076{
1077 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1078 u32 data_direction;
1079 u32 dword_0;
1080
1081 if (cmd_dir == DMA_FROM_DEVICE) {
1082 data_direction = UTP_DEVICE_TO_HOST;
1083 *upiu_flags = UPIU_CMD_FLAGS_READ;
1084 } else if (cmd_dir == DMA_TO_DEVICE) {
1085 data_direction = UTP_HOST_TO_DEVICE;
1086 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1087 } else {
1088 data_direction = UTP_NO_DATA_TRANSFER;
1089 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1090 }
1091
1092 dword_0 = data_direction | (lrbp->command_type
1093 << UPIU_COMMAND_TYPE_OFFSET);
1094 if (lrbp->intr_cmd)
1095 dword_0 |= UTP_REQ_DESC_INT_CMD;
1096
1097 /* Transfer request descriptor header fields */
1098 req_desc->header.dword_0 = cpu_to_le32(dword_0);
1099
1100 /*
1101 * assigning invalid value for command status. Controller
1102 * updates OCS on command completion, with the command
1103 * status
1104 */
1105 req_desc->header.dword_2 =
1106 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1107}
1108
1109/**
1110 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1111 * for scsi commands
1112 * @lrbp - local reference block pointer
1113 * @upiu_flags - flags
1114 */
1115static
1116void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1117{
1118 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1119
1120 /* command descriptor fields */
1121 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1122 UPIU_TRANSACTION_COMMAND, upiu_flags,
1123 lrbp->lun, lrbp->task_tag);
1124 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1125 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1126
1127 /* Total EHS length and Data segment length will be zero */
1128 ucd_req_ptr->header.dword_2 = 0;
1129
1130 ucd_req_ptr->sc.exp_data_transfer_len =
1131 cpu_to_be32(lrbp->cmd->sdb.length);
1132
1133 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
1134 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
1135}
1136
68078d5c
DR		 1137/**
1138 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1139 * for query requsts
1140 * @hba: UFS hba
1141 * @lrbp: local reference block pointer
1142 * @upiu_flags: flags
1143 */
1144static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1145 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1146{
1147 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1148 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1149 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1150 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1151
1152 /* Query request header */
1153 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1154 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1155 lrbp->lun, lrbp->task_tag);
1156 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1157 0, query->request.query_func, 0, 0);
1158
1159 /* Data segment length */
1160 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1161 0, 0, len >> 8, (u8)len);
1162
1163 /* Copy the Query Request buffer as is */
1164 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1165 QUERY_OSF_SIZE);
68078d5c
DR		 1166
1167 /* Copy the Descriptor */
c6d4a831
DR		 1168 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1169 memcpy(descp, query->descriptor, len);
1170
68078d5c
DR		 1171}
1172
5a0b0cb9
SRT		 1173static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1174{
1175 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1176
1177 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1178
1179 /* command descriptor fields */
1180 ucd_req_ptr->header.dword_0 =
1181 UPIU_HEADER_DWORD(
1182 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
1183}
1184
7a3e97b0
SY		 1185/**
1186 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 1187 * @hba - per adapter instance
7a3e97b0
SY		 1188 * @lrb - pointer to local reference block
1189 */
5a0b0cb9 1190static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1191{
7a3e97b0 1192 u32 upiu_flags;
5a0b0cb9 1193 int ret = 0;
7a3e97b0
SY		 1194
1195 switch (lrbp->command_type) {
1196 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 1197 if (likely(lrbp->cmd)) {
1198 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1199 lrbp->cmd->sc_data_direction);
1200 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 1201 } else {
5a0b0cb9 1202 ret = -EINVAL;
7a3e97b0 1203 }
7a3e97b0
SY		 1204 break;
1205 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 1206 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 1207 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1208 ufshcd_prepare_utp_query_req_upiu(
1209 hba, lrbp, upiu_flags);
1210 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 1211 ufshcd_prepare_utp_nop_upiu(lrbp);
1212 else
1213 ret = -EINVAL;
7a3e97b0
SY		 1214 break;
1215 case UTP_CMD_TYPE_UFS:
1216 /* For UFS native command implementation */
5a0b0cb9
SRT		 1217 ret = -ENOTSUPP;
1218 dev_err(hba->dev, "%s: UFS native command are not supported\n",
1219 __func__);
1220 break;
1221 default:
1222 ret = -ENOTSUPP;
1223 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
1224 __func__, lrbp->command_type);
7a3e97b0
SY		 1225 break;
1226 } /* end of switch */
5a0b0cb9
SRT		 1227
1228 return ret;
7a3e97b0
SY		 1229}
1230
0ce147d4
SJ		 1231/*
1232 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1233 * @scsi_lun: scsi LUN id
1234 *
1235 * Returns UPIU LUN id
1236 */
1237static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1238{
1239 if (scsi_is_wlun(scsi_lun))
1240 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1241 | UFS_UPIU_WLUN_ID;
1242 else
1243 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1244}
1245
2a8fa600
SJ		 1246/**
1247 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1248 * @scsi_lun: UPIU W-LUN id
1249 *
1250 * Returns SCSI W-LUN id
1251 */
1252static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1253{
1254 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1255}
1256
7a3e97b0
SY		 1257/**
1258 * ufshcd_queuecommand - main entry point for SCSI requests
1259 * @cmd: command from SCSI Midlayer
1260 * @done: call back function
1261 *
1262 * Returns 0 for success, non-zero in case of failure
1263 */
1264static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1265{
1266 struct ufshcd_lrb *lrbp;
1267 struct ufs_hba *hba;
1268 unsigned long flags;
1269 int tag;
1270 int err = 0;
1271
1272 hba = shost_priv(host);
1273
1274 tag = cmd->request->tag;
1275
3441da7d
SRT		 1276 spin_lock_irqsave(hba->host->host_lock, flags);
1277 switch (hba->ufshcd_state) {
1278 case UFSHCD_STATE_OPERATIONAL:
1279 break;
1280 case UFSHCD_STATE_RESET:
7a3e97b0 1281 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1282 goto out_unlock;
1283 case UFSHCD_STATE_ERROR:
1284 set_host_byte(cmd, DID_ERROR);
1285 cmd->scsi_done(cmd);
1286 goto out_unlock;
1287 default:
1288 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1289 __func__, hba->ufshcd_state);
1290 set_host_byte(cmd, DID_BAD_TARGET);
1291 cmd->scsi_done(cmd);
1292 goto out_unlock;
7a3e97b0 1293 }
3441da7d 1294 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1295
5a0b0cb9
SRT		 1296 /* acquire the tag to make sure device cmds don't use it */
1297 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1298 /*
1299 * Dev manage command in progress, requeue the command.
1300 * Requeuing the command helps in cases where the request *may*
1301 * find different tag instead of waiting for dev manage command
1302 * completion.
1303 */
1304 err = SCSI_MLQUEUE_HOST_BUSY;
1305 goto out;
1306 }
1307
1ab27c9c
ST		 1308 err = ufshcd_hold(hba, true);
1309 if (err) {
1310 err = SCSI_MLQUEUE_HOST_BUSY;
1311 clear_bit_unlock(tag, &hba->lrb_in_use);
1312 goto out;
1313 }
1314 WARN_ON(hba->clk_gating.state != CLKS_ON);
1315
7a3e97b0
SY		 1316 lrbp = &hba->lrb[tag];
1317
5a0b0cb9 1318 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 1319 lrbp->cmd = cmd;
1320 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1321 lrbp->sense_buffer = cmd->sense_buffer;
1322 lrbp->task_tag = tag;
0ce147d4 1323 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
5a0b0cb9 1324 lrbp->intr_cmd = false;
7a3e97b0
SY		 1325 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1326
1327 /* form UPIU before issuing the command */
5a0b0cb9 1328 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 1329 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 1330 if (err) {
1331 lrbp->cmd = NULL;
1332 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1333 goto out;
5a0b0cb9 1334 }
7a3e97b0
SY		 1335
1336 /* issue command to the controller */
1337 spin_lock_irqsave(hba->host->host_lock, flags);
1338 ufshcd_send_command(hba, tag);
3441da7d 1339out_unlock:
7a3e97b0
SY		 1340 spin_unlock_irqrestore(hba->host->host_lock, flags);
1341out:
1342 return err;
1343}
1344
5a0b0cb9
SRT		 1345static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1346 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1347{
1348 lrbp->cmd = NULL;
1349 lrbp->sense_bufflen = 0;
1350 lrbp->sense_buffer = NULL;
1351 lrbp->task_tag = tag;
1352 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
1353 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1354 lrbp->intr_cmd = true; /* No interrupt aggregation */
1355 hba->dev_cmd.type = cmd_type;
1356
1357 return ufshcd_compose_upiu(hba, lrbp);
1358}
1359
1360static int
1361ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1362{
1363 int err = 0;
1364 unsigned long flags;
1365 u32 mask = 1 << tag;
1366
1367 /* clear outstanding transaction before retry */
1368 spin_lock_irqsave(hba->host->host_lock, flags);
1369 ufshcd_utrl_clear(hba, tag);
1370 spin_unlock_irqrestore(hba->host->host_lock, flags);
1371
1372 /*
1373 * wait for for h/w to clear corresponding bit in door-bell.
1374 * max. wait is 1 sec.
1375 */
1376 err = ufshcd_wait_for_register(hba,
1377 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1378 mask, ~mask, 1000, 1000);
1379
1380 return err;
1381}
1382
c6d4a831
DR		 1383static int
1384ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1385{
1386 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1387
1388 /* Get the UPIU response */
1389 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1390 UPIU_RSP_CODE_OFFSET;
1391 return query_res->response;
1392}
1393
5a0b0cb9
SRT		 1394/**
1395 * ufshcd_dev_cmd_completion() - handles device management command responses
1396 * @hba: per adapter instance
1397 * @lrbp: pointer to local reference block
1398 */
1399static int
1400ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1401{
1402 int resp;
1403 int err = 0;
1404
1405 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1406
1407 switch (resp) {
1408 case UPIU_TRANSACTION_NOP_IN:
1409 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1410 err = -EINVAL;
1411 dev_err(hba->dev, "%s: unexpected response %x\n",
1412 __func__, resp);
1413 }
1414 break;
68078d5c 1415 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1416 err = ufshcd_check_query_response(hba, lrbp);
1417 if (!err)
1418 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1419 break;
5a0b0cb9
SRT		 1420 case UPIU_TRANSACTION_REJECT_UPIU:
1421 /* TODO: handle Reject UPIU Response */
1422 err = -EPERM;
1423 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1424 __func__);
1425 break;
1426 default:
1427 err = -EINVAL;
1428 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1429 __func__, resp);
1430 break;
1431 }
1432
1433 return err;
1434}
1435
1436static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1437 struct ufshcd_lrb *lrbp, int max_timeout)
1438{
1439 int err = 0;
1440 unsigned long time_left;
1441 unsigned long flags;
1442
1443 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1444 msecs_to_jiffies(max_timeout));
1445
1446 spin_lock_irqsave(hba->host->host_lock, flags);
1447 hba->dev_cmd.complete = NULL;
1448 if (likely(time_left)) {
1449 err = ufshcd_get_tr_ocs(lrbp);
1450 if (!err)
1451 err = ufshcd_dev_cmd_completion(hba, lrbp);
1452 }
1453 spin_unlock_irqrestore(hba->host->host_lock, flags);
1454
1455 if (!time_left) {
1456 err = -ETIMEDOUT;
1457 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1458 /* sucessfully cleared the command, retry if needed */
1459 err = -EAGAIN;
1460 }
1461
1462 return err;
1463}
1464
1465/**
1466 * ufshcd_get_dev_cmd_tag - Get device management command tag
1467 * @hba: per-adapter instance
1468 * @tag: pointer to variable with available slot value
1469 *
1470 * Get a free slot and lock it until device management command
1471 * completes.
1472 *
1473 * Returns false if free slot is unavailable for locking, else
1474 * return true with tag value in @tag.
1475 */
1476static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1477{
1478 int tag;
1479 bool ret = false;
1480 unsigned long tmp;
1481
1482 if (!tag_out)
1483 goto out;
1484
1485 do {
1486 tmp = ~hba->lrb_in_use;
1487 tag = find_last_bit(&tmp, hba->nutrs);
1488 if (tag >= hba->nutrs)
1489 goto out;
1490 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1491
1492 *tag_out = tag;
1493 ret = true;
1494out:
1495 return ret;
1496}
1497
1498static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1499{
1500 clear_bit_unlock(tag, &hba->lrb_in_use);
1501}
1502
1503/**
1504 * ufshcd_exec_dev_cmd - API for sending device management requests
1505 * @hba - UFS hba
1506 * @cmd_type - specifies the type (NOP, Query...)
1507 * @timeout - time in seconds
1508 *
68078d5c
DR		 1509 * NOTE: Since there is only one available tag for device management commands,
1510 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1511 */
1512static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1513 enum dev_cmd_type cmd_type, int timeout)
1514{
1515 struct ufshcd_lrb *lrbp;
1516 int err;
1517 int tag;
1518 struct completion wait;
1519 unsigned long flags;
1520
1521 /*
1522 * Get free slot, sleep if slots are unavailable.
1523 * Even though we use wait_event() which sleeps indefinitely,
1524 * the maximum wait time is bounded by SCSI request timeout.
1525 */
1526 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1527
1528 init_completion(&wait);
1529 lrbp = &hba->lrb[tag];
1530 WARN_ON(lrbp->cmd);
1531 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1532 if (unlikely(err))
1533 goto out_put_tag;
1534
1535 hba->dev_cmd.complete = &wait;
1536
1537 spin_lock_irqsave(hba->host->host_lock, flags);
1538 ufshcd_send_command(hba, tag);
1539 spin_unlock_irqrestore(hba->host->host_lock, flags);
1540
1541 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1542
1543out_put_tag:
1544 ufshcd_put_dev_cmd_tag(hba, tag);
1545 wake_up(&hba->dev_cmd.tag_wq);
1546 return err;
1547}
1548
d44a5f98
DR		 1549/**
1550 * ufshcd_init_query() - init the query response and request parameters
1551 * @hba: per-adapter instance
1552 * @request: address of the request pointer to be initialized
1553 * @response: address of the response pointer to be initialized
1554 * @opcode: operation to perform
1555 * @idn: flag idn to access
1556 * @index: LU number to access
1557 * @selector: query/flag/descriptor further identification
1558 */
1559static inline void ufshcd_init_query(struct ufs_hba *hba,
1560 struct ufs_query_req **request, struct ufs_query_res **response,
1561 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1562{
1563 *request = &hba->dev_cmd.query.request;
1564 *response = &hba->dev_cmd.query.response;
1565 memset(*request, 0, sizeof(struct ufs_query_req));
1566 memset(*response, 0, sizeof(struct ufs_query_res));
1567 (*request)->upiu_req.opcode = opcode;
1568 (*request)->upiu_req.idn = idn;
1569 (*request)->upiu_req.index = index;
1570 (*request)->upiu_req.selector = selector;
1571}
1572
68078d5c
DR		 1573/**
1574 * ufshcd_query_flag() - API function for sending flag query requests
1575 * hba: per-adapter instance
1576 * query_opcode: flag query to perform
1577 * idn: flag idn to access
1578 * flag_res: the flag value after the query request completes
1579 *
1580 * Returns 0 for success, non-zero in case of failure
1581 */
1582static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1583 enum flag_idn idn, bool *flag_res)
1584{
d44a5f98
DR		 1585 struct ufs_query_req *request = NULL;
1586 struct ufs_query_res *response = NULL;
1587 int err, index = 0, selector = 0;
68078d5c
DR		 1588
1589 BUG_ON(!hba);
1590
1ab27c9c 1591 ufshcd_hold(hba, false);
68078d5c 1592 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1593 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1594 selector);
68078d5c
DR		 1595
1596 switch (opcode) {
1597 case UPIU_QUERY_OPCODE_SET_FLAG:
1598 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1599 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1600 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1601 break;
1602 case UPIU_QUERY_OPCODE_READ_FLAG:
1603 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1604 if (!flag_res) {
1605 /* No dummy reads */
1606 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1607 __func__);
1608 err = -EINVAL;
1609 goto out_unlock;
1610 }
1611 break;
1612 default:
1613 dev_err(hba->dev,
1614 "%s: Expected query flag opcode but got = %d\n",
1615 __func__, opcode);
1616 err = -EINVAL;
1617 goto out_unlock;
1618 }
68078d5c 1619
d44a5f98 1620 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
68078d5c
DR		 1621
1622 if (err) {
1623 dev_err(hba->dev,
1624 "%s: Sending flag query for idn %d failed, err = %d\n",
1625 __func__, idn, err);
1626 goto out_unlock;
1627 }
1628
1629 if (flag_res)
e8c8e82a 1630 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1631 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1632
1633out_unlock:
1634 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1635 ufshcd_release(hba);
68078d5c
DR		 1636 return err;
1637}
1638
66ec6d59
SRT		 1639/**
1640 * ufshcd_query_attr - API function for sending attribute requests
1641 * hba: per-adapter instance
1642 * opcode: attribute opcode
1643 * idn: attribute idn to access
1644 * index: index field
1645 * selector: selector field
1646 * attr_val: the attribute value after the query request completes
1647 *
1648 * Returns 0 for success, non-zero in case of failure
1649*/
bdbe5d2f 1650static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1651 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1652{
d44a5f98
DR		 1653 struct ufs_query_req *request = NULL;
1654 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1655 int err;
1656
1657 BUG_ON(!hba);
1658
1ab27c9c 1659 ufshcd_hold(hba, false);
66ec6d59
SRT		 1660 if (!attr_val) {
1661 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1662 __func__, opcode);
1663 err = -EINVAL;
1664 goto out;
1665 }
1666
1667 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1668 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1669 selector);
66ec6d59
SRT		 1670
1671 switch (opcode) {
1672 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1673 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1674 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1675 break;
1676 case UPIU_QUERY_OPCODE_READ_ATTR:
1677 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1678 break;
1679 default:
1680 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1681 __func__, opcode);
1682 err = -EINVAL;
1683 goto out_unlock;
1684 }
1685
d44a5f98 1686 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1687
1688 if (err) {
1689 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1690 __func__, opcode, idn, err);
1691 goto out_unlock;
1692 }
1693
e8c8e82a 1694 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1695
1696out_unlock:
1697 mutex_unlock(&hba->dev_cmd.lock);
1698out:
1ab27c9c 1699 ufshcd_release(hba);
66ec6d59
SRT		 1700 return err;
1701}
1702
d44a5f98
DR		 1703/**
1704 * ufshcd_query_descriptor - API function for sending descriptor requests
1705 * hba: per-adapter instance
1706 * opcode: attribute opcode
1707 * idn: attribute idn to access
1708 * index: index field
1709 * selector: selector field
1710 * desc_buf: the buffer that contains the descriptor
1711 * buf_len: length parameter passed to the device
1712 *
1713 * Returns 0 for success, non-zero in case of failure.
1714 * The buf_len parameter will contain, on return, the length parameter
1715 * received on the response.
1716 */
7289f983 1717static int ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1718 enum query_opcode opcode, enum desc_idn idn, u8 index,
1719 u8 selector, u8 *desc_buf, int *buf_len)
1720{
1721 struct ufs_query_req *request = NULL;
1722 struct ufs_query_res *response = NULL;
1723 int err;
1724
1725 BUG_ON(!hba);
1726
1ab27c9c 1727 ufshcd_hold(hba, false);
d44a5f98
DR		 1728 if (!desc_buf) {
1729 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1730 __func__, opcode);
1731 err = -EINVAL;
1732 goto out;
1733 }
1734
1735 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1736 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1737 __func__, *buf_len);
1738 err = -EINVAL;
1739 goto out;
1740 }
1741
1742 mutex_lock(&hba->dev_cmd.lock);
1743 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1744 selector);
1745 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1746 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1747
1748 switch (opcode) {
1749 case UPIU_QUERY_OPCODE_WRITE_DESC:
1750 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1751 break;
1752 case UPIU_QUERY_OPCODE_READ_DESC:
1753 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1754 break;
1755 default:
1756 dev_err(hba->dev,
1757 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1758 __func__, opcode);
1759 err = -EINVAL;
1760 goto out_unlock;
1761 }
1762
1763 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1764
1765 if (err) {
1766 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1767 __func__, opcode, idn, err);
1768 goto out_unlock;
1769 }
1770
1771 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1772 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1773
1774out_unlock:
1775 mutex_unlock(&hba->dev_cmd.lock);
1776out:
1ab27c9c 1777 ufshcd_release(hba);
d44a5f98
DR		 1778 return err;
1779}
1780
da461cec
SJ		 1781/**
1782 * ufshcd_read_desc_param - read the specified descriptor parameter
1783 * @hba: Pointer to adapter instance
1784 * @desc_id: descriptor idn value
1785 * @desc_index: descriptor index
1786 * @param_offset: offset of the parameter to read
1787 * @param_read_buf: pointer to buffer where parameter would be read
1788 * @param_size: sizeof(param_read_buf)
1789 *
1790 * Return 0 in case of success, non-zero otherwise
1791 */
1792static int ufshcd_read_desc_param(struct ufs_hba *hba,
1793 enum desc_idn desc_id,
1794 int desc_index,
1795 u32 param_offset,
1796 u8 *param_read_buf,
1797 u32 param_size)
1798{
1799 int ret;
1800 u8 *desc_buf;
1801 u32 buff_len;
1802 bool is_kmalloc = true;
1803
1804 /* safety checks */
1805 if (desc_id >= QUERY_DESC_IDN_MAX)
1806 return -EINVAL;
1807
1808 buff_len = ufs_query_desc_max_size[desc_id];
1809 if ((param_offset + param_size) > buff_len)
1810 return -EINVAL;
1811
1812 if (!param_offset && (param_size == buff_len)) {
1813 /* memory space already available to hold full descriptor */
1814 desc_buf = param_read_buf;
1815 is_kmalloc = false;
1816 } else {
1817 /* allocate memory to hold full descriptor */
1818 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1819 if (!desc_buf)
1820 return -ENOMEM;
1821 }
1822
1823 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1824 desc_id, desc_index, 0, desc_buf,
1825 &buff_len);
1826
1827 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1828 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1829 ufs_query_desc_max_size[desc_id])
1830 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1831 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1832 __func__, desc_id, param_offset, buff_len, ret);
1833 if (!ret)
1834 ret = -EINVAL;
1835
1836 goto out;
1837 }
1838
1839 if (is_kmalloc)
1840 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1841out:
1842 if (is_kmalloc)
1843 kfree(desc_buf);
1844 return ret;
1845}
1846
1847static inline int ufshcd_read_desc(struct ufs_hba *hba,
1848 enum desc_idn desc_id,
1849 int desc_index,
1850 u8 *buf,
1851 u32 size)
1852{
1853 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1854}
1855
1856static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1857 u8 *buf,
1858 u32 size)
1859{
1860 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1861}
1862
1863/**
1864 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1865 * @hba: Pointer to adapter instance
1866 * @lun: lun id
1867 * @param_offset: offset of the parameter to read
1868 * @param_read_buf: pointer to buffer where parameter would be read
1869 * @param_size: sizeof(param_read_buf)
1870 *
1871 * Return 0 in case of success, non-zero otherwise
1872 */
1873static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1874 int lun,
1875 enum unit_desc_param param_offset,
1876 u8 *param_read_buf,
1877 u32 param_size)
1878{
1879 /*
1880 * Unit descriptors are only available for general purpose LUs (LUN id
1881 * from 0 to 7) and RPMB Well known LU.
1882 */
0ce147d4 1883 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 1884 return -EOPNOTSUPP;
1885
1886 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1887 param_offset, param_read_buf, param_size);
1888}
1889
7a3e97b0
SY		 1890/**
1891 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1892 * @hba: per adapter instance
1893 *
1894 * 1. Allocate DMA memory for Command Descriptor array
1895 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1896 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1897 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1898 * (UTMRDL)
1899 * 4. Allocate memory for local reference block(lrb).
1900 *
1901 * Returns 0 for success, non-zero in case of failure
1902 */
1903static int ufshcd_memory_alloc(struct ufs_hba *hba)
1904{
1905 size_t utmrdl_size, utrdl_size, ucdl_size;
1906
1907 /* Allocate memory for UTP command descriptors */
1908 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1909 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1910 ucdl_size,
1911 &hba->ucdl_dma_addr,
1912 GFP_KERNEL);
7a3e97b0
SY		 1913
1914 /*
1915 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1916 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1917 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1918 * be aligned to 128 bytes as well
1919 */
1920 if (!hba->ucdl_base_addr ||
1921 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1922 dev_err(hba->dev,
7a3e97b0
SY		 1923 "Command Descriptor Memory allocation failed\n");
1924 goto out;
1925 }
1926
1927 /*
1928 * Allocate memory for UTP Transfer descriptors
1929 * UFSHCI requires 1024 byte alignment of UTRD
1930 */
1931 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 1932 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1933 utrdl_size,
1934 &hba->utrdl_dma_addr,
1935 GFP_KERNEL);
7a3e97b0
SY		 1936 if (!hba->utrdl_base_addr ||
1937 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1938 dev_err(hba->dev,
7a3e97b0
SY		 1939 "Transfer Descriptor Memory allocation failed\n");
1940 goto out;
1941 }
1942
1943 /*
1944 * Allocate memory for UTP Task Management descriptors
1945 * UFSHCI requires 1024 byte alignment of UTMRD
1946 */
1947 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 1948 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1949 utmrdl_size,
1950 &hba->utmrdl_dma_addr,
1951 GFP_KERNEL);
7a3e97b0
SY		 1952 if (!hba->utmrdl_base_addr ||
1953 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1954 dev_err(hba->dev,
7a3e97b0
SY		 1955 "Task Management Descriptor Memory allocation failed\n");
1956 goto out;
1957 }
1958
1959 /* Allocate memory for local reference block */
2953f850
SJ		 1960 hba->lrb = devm_kzalloc(hba->dev,
1961 hba->nutrs * sizeof(struct ufshcd_lrb),
1962 GFP_KERNEL);
7a3e97b0 1963 if (!hba->lrb) {
3b1d0580 1964 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 1965 goto out;
1966 }
1967 return 0;
1968out:
7a3e97b0
SY		 1969 return -ENOMEM;
1970}
1971
1972/**
1973 * ufshcd_host_memory_configure - configure local reference block with
1974 * memory offsets
1975 * @hba: per adapter instance
1976 *
1977 * Configure Host memory space
1978 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
1979 * address.
1980 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
1981 * and PRDT offset.
1982 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
1983 * into local reference block.
1984 */
1985static void ufshcd_host_memory_configure(struct ufs_hba *hba)
1986{
1987 struct utp_transfer_cmd_desc *cmd_descp;
1988 struct utp_transfer_req_desc *utrdlp;
1989 dma_addr_t cmd_desc_dma_addr;
1990 dma_addr_t cmd_desc_element_addr;
1991 u16 response_offset;
1992 u16 prdt_offset;
1993 int cmd_desc_size;
1994 int i;
1995
1996 utrdlp = hba->utrdl_base_addr;
1997 cmd_descp = hba->ucdl_base_addr;
1998
1999 response_offset =
2000 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2001 prdt_offset =
2002 offsetof(struct utp_transfer_cmd_desc, prd_table);
2003
2004 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2005 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2006
2007 for (i = 0; i < hba->nutrs; i++) {
2008 /* Configure UTRD with command descriptor base address */
2009 cmd_desc_element_addr =
2010 (cmd_desc_dma_addr + (cmd_desc_size * i));
2011 utrdlp[i].command_desc_base_addr_lo =
2012 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2013 utrdlp[i].command_desc_base_addr_hi =
2014 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2015
2016 /* Response upiu and prdt offset should be in double words */
2017 utrdlp[i].response_upiu_offset =
2018 cpu_to_le16((response_offset >> 2));
2019 utrdlp[i].prd_table_offset =
2020 cpu_to_le16((prdt_offset >> 2));
2021 utrdlp[i].response_upiu_length =
3ca316c5 2022 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 2023
2024 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2025 hba->lrb[i].ucd_req_ptr =
2026 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2027 hba->lrb[i].ucd_rsp_ptr =
2028 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2029 hba->lrb[i].ucd_prdt_ptr =
2030 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2031 }
2032}
2033
2034/**
2035 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2036 * @hba: per adapter instance
2037 *
2038 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2039 * in order to initialize the Unipro link startup procedure.
2040 * Once the Unipro links are up, the device connected to the controller
2041 * is detected.
2042 *
2043 * Returns 0 on success, non-zero value on failure
2044 */
2045static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2046{
6ccf44fe
SJ		 2047 struct uic_command uic_cmd = {0};
2048 int ret;
7a3e97b0 2049
6ccf44fe 2050 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2051
6ccf44fe
SJ		 2052 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2053 if (ret)
2054 dev_err(hba->dev,
2055 "dme-link-startup: error code %d\n", ret);
2056 return ret;
7a3e97b0
SY		 2057}
2058
12b4fdb4
SJ		 2059/**
2060 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2061 * @hba: per adapter instance
2062 * @attr_sel: uic command argument1
2063 * @attr_set: attribute set type as uic command argument2
2064 * @mib_val: setting value as uic command argument3
2065 * @peer: indicate whether peer or local
2066 *
2067 * Returns 0 on success, non-zero value on failure
2068 */
2069int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2070 u8 attr_set, u32 mib_val, u8 peer)
2071{
2072 struct uic_command uic_cmd = {0};
2073 static const char *const action[] = {
2074 "dme-set",
2075 "dme-peer-set"
2076 };
2077 const char *set = action[!!peer];
2078 int ret;
2079
2080 uic_cmd.command = peer ?
2081 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2082 uic_cmd.argument1 = attr_sel;
2083 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2084 uic_cmd.argument3 = mib_val;
2085
2086 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2087 if (ret)
2088 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2089 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2090
2091 return ret;
2092}
2093EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2094
2095/**
2096 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2097 * @hba: per adapter instance
2098 * @attr_sel: uic command argument1
2099 * @mib_val: the value of the attribute as returned by the UIC command
2100 * @peer: indicate whether peer or local
2101 *
2102 * Returns 0 on success, non-zero value on failure
2103 */
2104int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2105 u32 *mib_val, u8 peer)
2106{
2107 struct uic_command uic_cmd = {0};
2108 static const char *const action[] = {
2109 "dme-get",
2110 "dme-peer-get"
2111 };
2112 const char *get = action[!!peer];
2113 int ret;
2114
2115 uic_cmd.command = peer ?
2116 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2117 uic_cmd.argument1 = attr_sel;
2118
2119 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2120 if (ret) {
2121 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
2122 get, UIC_GET_ATTR_ID(attr_sel), ret);
2123 goto out;
2124 }
2125
2126 if (mib_val)
2127 *mib_val = uic_cmd.argument3;
2128out:
2129 return ret;
2130}
2131EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2132
53b3d9c3 2133/**
57d104c1
SJ		 2134 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2135 * state) and waits for it to take effect.
2136 *
53b3d9c3 2137 * @hba: per adapter instance
57d104c1
SJ		 2138 * @cmd: UIC command to execute
2139 *
2140 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2141 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2142 * and device UniPro link and hence it's final completion would be indicated by
2143 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2144 * addition to normal UIC command completion Status (UCCS). This function only
2145 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2146 *
2147 * Returns 0 on success, non-zero value on failure
2148 */
57d104c1 2149static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2150{
57d104c1 2151 struct completion uic_async_done;
53b3d9c3
SJ		 2152 unsigned long flags;
2153 u8 status;
2154 int ret;
2155
53b3d9c3 2156 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2157 init_completion(&uic_async_done);
53b3d9c3
SJ		 2158
2159 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1
SJ		 2160 hba->uic_async_done = &uic_async_done;
2161 ret = __ufshcd_send_uic_cmd(hba, cmd);
53b3d9c3 2162 spin_unlock_irqrestore(hba->host->host_lock, flags);
53b3d9c3
SJ		 2163 if (ret) {
2164 dev_err(hba->dev,
57d104c1
SJ		 2165 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2166 cmd->command, cmd->argument3, ret);
2167 goto out;
2168 }
2169 ret = ufshcd_wait_for_uic_cmd(hba, cmd);
2170 if (ret) {
2171 dev_err(hba->dev,
2172 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2173 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2174 goto out;
2175 }
2176
57d104c1 2177 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2178 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2179 dev_err(hba->dev,
57d104c1
SJ		 2180 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2181 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2182 ret = -ETIMEDOUT;
2183 goto out;
2184 }
2185
2186 status = ufshcd_get_upmcrs(hba);
2187 if (status != PWR_LOCAL) {
2188 dev_err(hba->dev,
57d104c1
SJ		 2189 "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
2190 cmd->command, status);
53b3d9c3
SJ		 2191 ret = (status != PWR_OK) ? status : -1;
2192 }
2193out:
2194 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2195 hba->uic_async_done = NULL;
53b3d9c3
SJ		 2196 spin_unlock_irqrestore(hba->host->host_lock, flags);
2197 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2198
53b3d9c3
SJ		 2199 return ret;
2200}
2201
57d104c1
SJ		 2202/**
2203 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2204 * using DME_SET primitives.
2205 * @hba: per adapter instance
2206 * @mode: powr mode value
2207 *
2208 * Returns 0 on success, non-zero value on failure
2209 */
2210static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2211{
2212 struct uic_command uic_cmd = {0};
1ab27c9c 2213 int ret;
57d104c1
SJ		 2214
2215 uic_cmd.command = UIC_CMD_DME_SET;
2216 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2217 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2218 ufshcd_hold(hba, false);
2219 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2220 ufshcd_release(hba);
57d104c1 2221
1ab27c9c 2222 return ret;
57d104c1
SJ		 2223}
2224
2225static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2226{
2227 struct uic_command uic_cmd = {0};
2228
2229 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
2230
2231 return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2232}
2233
2234static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2235{
2236 struct uic_command uic_cmd = {0};
2237 int ret;
2238
2239 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2240 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2241 if (ret) {
2242 ufshcd_set_link_off(hba);
2243 ret = ufshcd_host_reset_and_restore(hba);
2244 }
2245
2246 return ret;
2247}
2248
d3e89bac 2249/**
7eb584db
DR		 2250 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2251 * @hba: per-adapter instance
d3e89bac 2252 */
7eb584db 2253static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2254{
7eb584db
DR		 2255 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2256
2257 if (hba->max_pwr_info.is_valid)
2258 return 0;
2259
2260 pwr_info->pwr_tx = FASTAUTO_MODE;
2261 pwr_info->pwr_rx = FASTAUTO_MODE;
2262 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2263
2264 /* Get the connected lane count */
7eb584db
DR		 2265 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2266 &pwr_info->lane_rx);
2267 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2268 &pwr_info->lane_tx);
2269
2270 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2271 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2272 __func__,
2273 pwr_info->lane_rx,
2274 pwr_info->lane_tx);
2275 return -EINVAL;
2276 }
d3e89bac
SJ		 2277
2278 /*
2279 * First, get the maximum gears of HS speed.
2280 * If a zero value, it means there is no HSGEAR capability.
2281 * Then, get the maximum gears of PWM speed.
2282 */
7eb584db
DR		 2283 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2284 if (!pwr_info->gear_rx) {
2285 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2286 &pwr_info->gear_rx);
2287 if (!pwr_info->gear_rx) {
2288 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2289 __func__, pwr_info->gear_rx);
2290 return -EINVAL;
2291 }
2292 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2293 }
2294
7eb584db
DR		 2295 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2296 &pwr_info->gear_tx);
2297 if (!pwr_info->gear_tx) {
d3e89bac 2298 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2299 &pwr_info->gear_tx);
2300 if (!pwr_info->gear_tx) {
2301 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2302 __func__, pwr_info->gear_tx);
2303 return -EINVAL;
2304 }
2305 pwr_info->pwr_tx = SLOWAUTO_MODE;
2306 }
2307
2308 hba->max_pwr_info.is_valid = true;
2309 return 0;
2310}
2311
2312static int ufshcd_change_power_mode(struct ufs_hba *hba,
2313 struct ufs_pa_layer_attr *pwr_mode)
2314{
2315 int ret;
2316
2317 /* if already configured to the requested pwr_mode */
2318 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2319 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2320 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2321 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2322 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2323 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2324 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2325 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2326 return 0;
d3e89bac
SJ		 2327 }
2328
2329 /*
2330 * Configure attributes for power mode change with below.
2331 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2332 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2333 * - PA_HSSERIES
2334 */
7eb584db
DR		 2335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2337 pwr_mode->lane_rx);
2338 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2339 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2340 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2341 else
2342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2343
7eb584db
DR		 2344 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2345 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2346 pwr_mode->lane_tx);
2347 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2348 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2349 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2350 else
2351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2352
7eb584db
DR		 2353 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2354 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2355 pwr_mode->pwr_rx == FAST_MODE ||
2356 pwr_mode->pwr_tx == FAST_MODE)
2357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2358 pwr_mode->hs_rate);
d3e89bac 2359
7eb584db
DR		 2360 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2361 | pwr_mode->pwr_tx);
2362
2363 if (ret) {
d3e89bac 2364 dev_err(hba->dev,
7eb584db
DR		 2365 "%s: power mode change failed %d\n", __func__, ret);
2366 } else {
2367 if (hba->vops && hba->vops->pwr_change_notify)
2368 hba->vops->pwr_change_notify(hba,
2369 POST_CHANGE, NULL, pwr_mode);
2370
2371 memcpy(&hba->pwr_info, pwr_mode,
2372 sizeof(struct ufs_pa_layer_attr));
2373 }
2374
2375 return ret;
2376}
2377
2378/**
2379 * ufshcd_config_pwr_mode - configure a new power mode
2380 * @hba: per-adapter instance
2381 * @desired_pwr_mode: desired power configuration
2382 */
2383static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2384 struct ufs_pa_layer_attr *desired_pwr_mode)
2385{
2386 struct ufs_pa_layer_attr final_params = { 0 };
2387 int ret;
2388
2389 if (hba->vops && hba->vops->pwr_change_notify)
2390 hba->vops->pwr_change_notify(hba,
2391 PRE_CHANGE, desired_pwr_mode, &final_params);
2392 else
2393 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2394
2395 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2396
2397 return ret;
2398}
2399
68078d5c
DR		 2400/**
2401 * ufshcd_complete_dev_init() - checks device readiness
2402 * hba: per-adapter instance
2403 *
2404 * Set fDeviceInit flag and poll until device toggles it.
2405 */
2406static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2407{
2408 int i, retries, err = 0;
2409 bool flag_res = 1;
2410
2411 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2412 /* Set the fDeviceInit flag */
2413 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2414 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
2415 if (!err || err == -ETIMEDOUT)
2416 break;
2417 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2418 }
2419 if (err) {
2420 dev_err(hba->dev,
2421 "%s setting fDeviceInit flag failed with error %d\n",
2422 __func__, err);
2423 goto out;
2424 }
2425
2426 /* poll for max. 100 iterations for fDeviceInit flag to clear */
2427 for (i = 0; i < 100 && !err && flag_res; i++) {
2428 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2429 err = ufshcd_query_flag(hba,
2430 UPIU_QUERY_OPCODE_READ_FLAG,
2431 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2432 if (!err || err == -ETIMEDOUT)
2433 break;
2434 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
2435 err);
2436 }
2437 }
2438 if (err)
2439 dev_err(hba->dev,
2440 "%s reading fDeviceInit flag failed with error %d\n",
2441 __func__, err);
2442 else if (flag_res)
2443 dev_err(hba->dev,
2444 "%s fDeviceInit was not cleared by the device\n",
2445 __func__);
2446
2447out:
2448 return err;
2449}
2450
7a3e97b0
SY		 2451/**
2452 * ufshcd_make_hba_operational - Make UFS controller operational
2453 * @hba: per adapter instance
2454 *
2455 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2456 * 1. Enable required interrupts
2457 * 2. Configure interrupt aggregation
2458 * 3. Program UTRL and UTMRL base addres
2459 * 4. Configure run-stop-registers
7a3e97b0
SY		 2460 *
2461 * Returns 0 on success, non-zero value on failure
2462 */
2463static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2464{
2465 int err = 0;
2466 u32 reg;
2467
6ccf44fe
SJ		 2468 /* Enable required interrupts */
2469 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2470
2471 /* Configure interrupt aggregation */
7d568652 2472 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
6ccf44fe
SJ		 2473
2474 /* Configure UTRL and UTMRL base address registers */
2475 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2476 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2477 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2478 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2479 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2480 REG_UTP_TASK_REQ_LIST_BASE_L);
2481 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2482 REG_UTP_TASK_REQ_LIST_BASE_H);
2483
7a3e97b0
SY		 2484 /*
2485 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
2486 * DEI, HEI bits must be 0
2487 */
5c0c28a8 2488 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 2489 if (!(ufshcd_get_lists_status(reg))) {
2490 ufshcd_enable_run_stop_reg(hba);
2491 } else {
3b1d0580 2492 dev_err(hba->dev,
7a3e97b0
SY		 2493 "Host controller not ready to process requests");
2494 err = -EIO;
2495 goto out;
2496 }
2497
7a3e97b0
SY		 2498out:
2499 return err;
2500}
2501
2502/**
2503 * ufshcd_hba_enable - initialize the controller
2504 * @hba: per adapter instance
2505 *
2506 * The controller resets itself and controller firmware initialization
2507 * sequence kicks off. When controller is ready it will set
2508 * the Host Controller Enable bit to 1.
2509 *
2510 * Returns 0 on success, non-zero value on failure
2511 */
2512static int ufshcd_hba_enable(struct ufs_hba *hba)
2513{
2514 int retry;
2515
2516 /*
2517 * msleep of 1 and 5 used in this function might result in msleep(20),
2518 * but it was necessary to send the UFS FPGA to reset mode during
2519 * development and testing of this driver. msleep can be changed to
2520 * mdelay and retry count can be reduced based on the controller.
2521 */
2522 if (!ufshcd_is_hba_active(hba)) {
2523
2524 /* change controller state to "reset state" */
2525 ufshcd_hba_stop(hba);
2526
2527 /*
2528 * This delay is based on the testing done with UFS host
2529 * controller FPGA. The delay can be changed based on the
2530 * host controller used.
2531 */
2532 msleep(5);
2533 }
2534
57d104c1
SJ		 2535 /* UniPro link is disabled at this point */
2536 ufshcd_set_link_off(hba);
2537
5c0c28a8
SRT		 2538 if (hba->vops && hba->vops->hce_enable_notify)
2539 hba->vops->hce_enable_notify(hba, PRE_CHANGE);
2540
7a3e97b0
SY		 2541 /* start controller initialization sequence */
2542 ufshcd_hba_start(hba);
2543
2544 /*
2545 * To initialize a UFS host controller HCE bit must be set to 1.
2546 * During initialization the HCE bit value changes from 1->0->1.
2547 * When the host controller completes initialization sequence
2548 * it sets the value of HCE bit to 1. The same HCE bit is read back
2549 * to check if the controller has completed initialization sequence.
2550 * So without this delay the value HCE = 1, set in the previous
2551 * instruction might be read back.
2552 * This delay can be changed based on the controller.
2553 */
2554 msleep(1);
2555
2556 /* wait for the host controller to complete initialization */
2557 retry = 10;
2558 while (ufshcd_is_hba_active(hba)) {
2559 if (retry) {
2560 retry--;
2561 } else {
3b1d0580 2562 dev_err(hba->dev,
7a3e97b0
SY		 2563 "Controller enable failed\n");
2564 return -EIO;
2565 }
2566 msleep(5);
2567 }
5c0c28a8 2568
1d337ec2 2569 /* enable UIC related interrupts */
57d104c1 2570 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 2571
5c0c28a8
SRT		 2572 if (hba->vops && hba->vops->hce_enable_notify)
2573 hba->vops->hce_enable_notify(hba, POST_CHANGE);
2574
7a3e97b0
SY		 2575 return 0;
2576}
2577
2578/**
6ccf44fe 2579 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 2580 * @hba: per adapter instance
2581 *
6ccf44fe 2582 * Returns 0 for success, non-zero in case of failure
7a3e97b0 2583 */
6ccf44fe 2584static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 2585{
6ccf44fe 2586 int ret;
1d337ec2 2587 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 2588
1d337ec2
SRT		 2589 do {
2590 if (hba->vops && hba->vops->link_startup_notify)
2591 hba->vops->link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 2592
1d337ec2 2593 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 2594
1d337ec2
SRT		 2595 /* check if device is detected by inter-connect layer */
2596 if (!ret && !ufshcd_is_device_present(hba)) {
2597 dev_err(hba->dev, "%s: Device not present\n", __func__);
2598 ret = -ENXIO;
2599 goto out;
2600 }
6ccf44fe 2601
1d337ec2
SRT		 2602 /*
2603 * DME link lost indication is only received when link is up,
2604 * but we can't be sure if the link is up until link startup
2605 * succeeds. So reset the local Uni-Pro and try again.
2606 */
2607 if (ret && ufshcd_hba_enable(hba))
2608 goto out;
2609 } while (ret && retries--);
2610
2611 if (ret)
2612 /* failed to get the link up... retire */
5c0c28a8 2613 goto out;
5c0c28a8
SRT		 2614
2615 /* Include any host controller configuration via UIC commands */
2616 if (hba->vops && hba->vops->link_startup_notify) {
2617 ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
2618 if (ret)
2619 goto out;
2620 }
7a3e97b0 2621
5c0c28a8 2622 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 2623out:
2624 if (ret)
2625 dev_err(hba->dev, "link startup failed %d\n", ret);
2626 return ret;
7a3e97b0
SY		 2627}
2628
5a0b0cb9
SRT		 2629/**
2630 * ufshcd_verify_dev_init() - Verify device initialization
2631 * @hba: per-adapter instance
2632 *
2633 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2634 * device Transport Protocol (UTP) layer is ready after a reset.
2635 * If the UTP layer at the device side is not initialized, it may
2636 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2637 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2638 */
2639static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2640{
2641 int err = 0;
2642 int retries;
2643
1ab27c9c 2644 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 2645 mutex_lock(&hba->dev_cmd.lock);
2646 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2647 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2648 NOP_OUT_TIMEOUT);
2649
2650 if (!err || err == -ETIMEDOUT)
2651 break;
2652
2653 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2654 }
2655 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2656 ufshcd_release(hba);
5a0b0cb9
SRT		 2657
2658 if (err)
2659 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2660 return err;
2661}
2662
0ce147d4
SJ		 2663/**
2664 * ufshcd_set_queue_depth - set lun queue depth
2665 * @sdev: pointer to SCSI device
2666 *
2667 * Read bLUQueueDepth value and activate scsi tagged command
2668 * queueing. For WLUN, queue depth is set to 1. For best-effort
2669 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
2670 * value that host can queue.
2671 */
2672static void ufshcd_set_queue_depth(struct scsi_device *sdev)
2673{
2674 int ret = 0;
2675 u8 lun_qdepth;
2676 struct ufs_hba *hba;
2677
2678 hba = shost_priv(sdev->host);
2679
2680 lun_qdepth = hba->nutrs;
2681 ret = ufshcd_read_unit_desc_param(hba,
2682 ufshcd_scsi_to_upiu_lun(sdev->lun),
2683 UNIT_DESC_PARAM_LU_Q_DEPTH,
2684 &lun_qdepth,
2685 sizeof(lun_qdepth));
2686
2687 /* Some WLUN doesn't support unit descriptor */
2688 if (ret == -EOPNOTSUPP)
2689 lun_qdepth = 1;
2690 else if (!lun_qdepth)
2691 /* eventually, we can figure out the real queue depth */
2692 lun_qdepth = hba->nutrs;
2693 else
2694 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
2695
2696 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2697 __func__, lun_qdepth);
2698 scsi_activate_tcq(sdev, lun_qdepth);
2699}
2700
57d104c1
SJ		 2701/*
2702 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
2703 * @hba: per-adapter instance
2704 * @lun: UFS device lun id
2705 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
2706 *
2707 * Returns 0 in case of success and b_lu_write_protect status would be returned
2708 * @b_lu_write_protect parameter.
2709 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
2710 * Returns -EINVAL in case of invalid parameters passed to this function.
2711 */
2712static int ufshcd_get_lu_wp(struct ufs_hba *hba,
2713 u8 lun,
2714 u8 *b_lu_write_protect)
2715{
2716 int ret;
2717
2718 if (!b_lu_write_protect)
2719 ret = -EINVAL;
2720 /*
2721 * According to UFS device spec, RPMB LU can't be write
2722 * protected so skip reading bLUWriteProtect parameter for
2723 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
2724 */
2725 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
2726 ret = -ENOTSUPP;
2727 else
2728 ret = ufshcd_read_unit_desc_param(hba,
2729 lun,
2730 UNIT_DESC_PARAM_LU_WR_PROTECT,
2731 b_lu_write_protect,
2732 sizeof(*b_lu_write_protect));
2733 return ret;
2734}
2735
2736/**
2737 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
2738 * status
2739 * @hba: per-adapter instance
2740 * @sdev: pointer to SCSI device
2741 *
2742 */
2743static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
2744 struct scsi_device *sdev)
2745{
2746 if (hba->dev_info.f_power_on_wp_en &&
2747 !hba->dev_info.is_lu_power_on_wp) {
2748 u8 b_lu_write_protect;
2749
2750 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
2751 &b_lu_write_protect) &&
2752 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
2753 hba->dev_info.is_lu_power_on_wp = true;
2754 }
2755}
2756
7a3e97b0
SY		 2757/**
2758 * ufshcd_slave_alloc - handle initial SCSI device configurations
2759 * @sdev: pointer to SCSI device
2760 *
2761 * Returns success
2762 */
2763static int ufshcd_slave_alloc(struct scsi_device *sdev)
2764{
2765 struct ufs_hba *hba;
2766
2767 hba = shost_priv(sdev->host);
2768 sdev->tagged_supported = 1;
2769
2770 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2771 sdev->use_10_for_ms = 1;
2772 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
2773
e8e7f271
SRT		 2774 /* allow SCSI layer to restart the device in case of errors */
2775 sdev->allow_restart = 1;
4264fd61 2776
b2a6c522
SRT		 2777 /* REPORT SUPPORTED OPERATION CODES is not supported */
2778 sdev->no_report_opcodes = 1;
2779
e8e7f271 2780
0ce147d4 2781 ufshcd_set_queue_depth(sdev);
4264fd61 2782
57d104c1
SJ		 2783 ufshcd_get_lu_power_on_wp_status(hba, sdev);
2784
7a3e97b0
SY		 2785 return 0;
2786}
2787
4264fd61
SRT		 2788/**
2789 * ufshcd_change_queue_depth - change queue depth
2790 * @sdev: pointer to SCSI device
2791 * @depth: required depth to set
2792 * @reason: reason for changing the depth
2793 *
2794 * Change queue depth according to the reason and make sure
2795 * the max. limits are not crossed.
2796 */
7289f983
SRT		 2797static int ufshcd_change_queue_depth(struct scsi_device *sdev,
2798 int depth, int reason)
4264fd61
SRT		 2799{
2800 struct ufs_hba *hba = shost_priv(sdev->host);
2801
2802 if (depth > hba->nutrs)
2803 depth = hba->nutrs;
2804
2805 switch (reason) {
2806 case SCSI_QDEPTH_DEFAULT:
2807 case SCSI_QDEPTH_RAMP_UP:
2808 if (!sdev->tagged_supported)
2809 depth = 1;
2810 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth);
2811 break;
2812 case SCSI_QDEPTH_QFULL:
2813 scsi_track_queue_full(sdev, depth);
2814 break;
2815 default:
2816 return -EOPNOTSUPP;
2817 }
2818
2819 return depth;
2820}
2821
eeda4749
AM		 2822/**
2823 * ufshcd_slave_configure - adjust SCSI device configurations
2824 * @sdev: pointer to SCSI device
2825 */
2826static int ufshcd_slave_configure(struct scsi_device *sdev)
2827{
2828 struct request_queue *q = sdev->request_queue;
2829
2830 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2831 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
2832
2833 return 0;
2834}
2835
7a3e97b0
SY		 2836/**
2837 * ufshcd_slave_destroy - remove SCSI device configurations
2838 * @sdev: pointer to SCSI device
2839 */
2840static void ufshcd_slave_destroy(struct scsi_device *sdev)
2841{
2842 struct ufs_hba *hba;
2843
2844 hba = shost_priv(sdev->host);
2845 scsi_deactivate_tcq(sdev, hba->nutrs);
0ce147d4 2846 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 2847 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
2848 unsigned long flags;
2849
2850 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 2851 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 2852 spin_unlock_irqrestore(hba->host->host_lock, flags);
2853 }
7a3e97b0
SY		 2854}
2855
2856/**
2857 * ufshcd_task_req_compl - handle task management request completion
2858 * @hba: per adapter instance
2859 * @index: index of the completed request
e2933132 2860 * @resp: task management service response
7a3e97b0 2861 *
e2933132 2862 * Returns non-zero value on error, zero on success
7a3e97b0 2863 */
e2933132 2864static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 2865{
2866 struct utp_task_req_desc *task_req_descp;
2867 struct utp_upiu_task_rsp *task_rsp_upiup;
2868 unsigned long flags;
2869 int ocs_value;
2870 int task_result;
2871
2872 spin_lock_irqsave(hba->host->host_lock, flags);
2873
2874 /* Clear completed tasks from outstanding_tasks */
2875 __clear_bit(index, &hba->outstanding_tasks);
2876
2877 task_req_descp = hba->utmrdl_base_addr;
2878 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
2879
2880 if (ocs_value == OCS_SUCCESS) {
2881 task_rsp_upiup = (struct utp_upiu_task_rsp *)
2882 task_req_descp[index].task_rsp_upiu;
2883 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
2884 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 2885 if (resp)
2886 *resp = (u8)task_result;
7a3e97b0 2887 } else {
e2933132
SRT		 2888 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
2889 __func__, ocs_value);
7a3e97b0
SY		 2890 }
2891 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 2892
2893 return ocs_value;
7a3e97b0
SY		 2894}
2895
7a3e97b0
SY		 2896/**
2897 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
2898 * @lrb: pointer to local reference block of completed command
2899 * @scsi_status: SCSI command status
2900 *
2901 * Returns value base on SCSI command status
2902 */
2903static inline int
2904ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
2905{
2906 int result = 0;
2907
2908 switch (scsi_status) {
7a3e97b0 2909 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 2910 ufshcd_copy_sense_data(lrbp);
2911 case SAM_STAT_GOOD:
7a3e97b0
SY		 2912 result |= DID_OK << 16 |
2913 COMMAND_COMPLETE << 8 |
1c2623c5 2914 scsi_status;
7a3e97b0
SY		 2915 break;
2916 case SAM_STAT_TASK_SET_FULL:
1c2623c5 2917 case SAM_STAT_BUSY:
7a3e97b0 2918 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 2919 ufshcd_copy_sense_data(lrbp);
2920 result |= scsi_status;
7a3e97b0
SY		 2921 break;
2922 default:
2923 result |= DID_ERROR << 16;
2924 break;
2925 } /* end of switch */
2926
2927 return result;
2928}
2929
2930/**
2931 * ufshcd_transfer_rsp_status - Get overall status of the response
2932 * @hba: per adapter instance
2933 * @lrb: pointer to local reference block of completed command
2934 *
2935 * Returns result of the command to notify SCSI midlayer
2936 */
2937static inline int
2938ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2939{
2940 int result = 0;
2941 int scsi_status;
2942 int ocs;
2943
2944 /* overall command status of utrd */
2945 ocs = ufshcd_get_tr_ocs(lrbp);
2946
2947 switch (ocs) {
2948 case OCS_SUCCESS:
5a0b0cb9 2949 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 2950
5a0b0cb9
SRT		 2951 switch (result) {
2952 case UPIU_TRANSACTION_RESPONSE:
2953 /*
2954 * get the response UPIU result to extract
2955 * the SCSI command status
2956 */
2957 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
2958
2959 /*
2960 * get the result based on SCSI status response
2961 * to notify the SCSI midlayer of the command status
2962 */
2963 scsi_status = result & MASK_SCSI_STATUS;
2964 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59
SRT		 2965
2966 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
2967 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 2968 break;
2969 case UPIU_TRANSACTION_REJECT_UPIU:
2970 /* TODO: handle Reject UPIU Response */
2971 result = DID_ERROR << 16;
3b1d0580 2972 dev_err(hba->dev,
5a0b0cb9
SRT		 2973 "Reject UPIU not fully implemented\n");
2974 break;
2975 default:
2976 result = DID_ERROR << 16;
2977 dev_err(hba->dev,
2978 "Unexpected request response code = %x\n",
2979 result);
7a3e97b0
SY		 2980 break;
2981 }
7a3e97b0
SY		 2982 break;
2983 case OCS_ABORTED:
2984 result |= DID_ABORT << 16;
2985 break;
e8e7f271
SRT		 2986 case OCS_INVALID_COMMAND_STATUS:
2987 result |= DID_REQUEUE << 16;
2988 break;
7a3e97b0
SY		 2989 case OCS_INVALID_CMD_TABLE_ATTR:
2990 case OCS_INVALID_PRDT_ATTR:
2991 case OCS_MISMATCH_DATA_BUF_SIZE:
2992 case OCS_MISMATCH_RESP_UPIU_SIZE:
2993 case OCS_PEER_COMM_FAILURE:
2994 case OCS_FATAL_ERROR:
2995 default:
2996 result |= DID_ERROR << 16;
3b1d0580 2997 dev_err(hba->dev,
7a3e97b0
SY		 2998 "OCS error from controller = %x\n", ocs);
2999 break;
3000 } /* end of switch */
3001
3002 return result;
3003}
3004
6ccf44fe
SJ		 3005/**
3006 * ufshcd_uic_cmd_compl - handle completion of uic command
3007 * @hba: per adapter instance
53b3d9c3 3008 * @intr_status: interrupt status generated by the controller
6ccf44fe 3009 */
53b3d9c3 3010static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3011{
53b3d9c3 3012 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3013 hba->active_uic_cmd->argument2 |=
3014 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3015 hba->active_uic_cmd->argument3 =
3016 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3017 complete(&hba->active_uic_cmd->done);
3018 }
53b3d9c3 3019
57d104c1
SJ		 3020 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3021 complete(hba->uic_async_done);
6ccf44fe
SJ		 3022}
3023
7a3e97b0
SY		 3024/**
3025 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3026 * @hba: per adapter instance
3027 */
3028static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3029{
5a0b0cb9
SRT		 3030 struct ufshcd_lrb *lrbp;
3031 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3032 unsigned long completed_reqs;
3033 u32 tr_doorbell;
3034 int result;
3035 int index;
e9d501b1
DR		 3036
3037 /* Resetting interrupt aggregation counters first and reading the
3038 * DOOR_BELL afterward allows us to handle all the completed requests.
3039 * In order to prevent other interrupts starvation the DB is read once
3040 * after reset. The down side of this solution is the possibility of
3041 * false interrupt if device completes another request after resetting
3042 * aggregation and before reading the DB.
3043 */
3044 ufshcd_reset_intr_aggr(hba);
7a3e97b0 3045
b873a275 3046 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 3047 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3048
e9d501b1
DR		 3049 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3050 lrbp = &hba->lrb[index];
3051 cmd = lrbp->cmd;
3052 if (cmd) {
3053 result = ufshcd_transfer_rsp_status(hba, lrbp);
3054 scsi_dma_unmap(cmd);
3055 cmd->result = result;
3056 /* Mark completed command as NULL in LRB */
3057 lrbp->cmd = NULL;
3058 clear_bit_unlock(index, &hba->lrb_in_use);
3059 /* Do not touch lrbp after scsi done */
3060 cmd->scsi_done(cmd);
1ab27c9c 3061 __ufshcd_release(hba);
e9d501b1
DR		 3062 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
3063 if (hba->dev_cmd.complete)
3064 complete(hba->dev_cmd.complete);
3065 }
3066 }
7a3e97b0
SY		 3067
3068 /* clear corresponding bits of completed commands */
3069 hba->outstanding_reqs ^= completed_reqs;
3070
856b3483
ST		 3071 ufshcd_clk_scaling_update_busy(hba);
3072
5a0b0cb9
SRT		 3073 /* we might have free'd some tags above */
3074 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3075}
3076
66ec6d59
SRT		 3077/**
3078 * ufshcd_disable_ee - disable exception event
3079 * @hba: per-adapter instance
3080 * @mask: exception event to disable
3081 *
3082 * Disables exception event in the device so that the EVENT_ALERT
3083 * bit is not set.
3084 *
3085 * Returns zero on success, non-zero error value on failure.
3086 */
3087static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3088{
3089 int err = 0;
3090 u32 val;
3091
3092 if (!(hba->ee_ctrl_mask & mask))
3093 goto out;
3094
3095 val = hba->ee_ctrl_mask & ~mask;
3096 val &= 0xFFFF; /* 2 bytes */
3097 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3098 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3099 if (!err)
3100 hba->ee_ctrl_mask &= ~mask;
3101out:
3102 return err;
3103}
3104
3105/**
3106 * ufshcd_enable_ee - enable exception event
3107 * @hba: per-adapter instance
3108 * @mask: exception event to enable
3109 *
3110 * Enable corresponding exception event in the device to allow
3111 * device to alert host in critical scenarios.
3112 *
3113 * Returns zero on success, non-zero error value on failure.
3114 */
3115static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3116{
3117 int err = 0;
3118 u32 val;
3119
3120 if (hba->ee_ctrl_mask & mask)
3121 goto out;
3122
3123 val = hba->ee_ctrl_mask | mask;
3124 val &= 0xFFFF; /* 2 bytes */
3125 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3126 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3127 if (!err)
3128 hba->ee_ctrl_mask |= mask;
3129out:
3130 return err;
3131}
3132
3133/**
3134 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3135 * @hba: per-adapter instance
3136 *
3137 * Allow device to manage background operations on its own. Enabling
3138 * this might lead to inconsistent latencies during normal data transfers
3139 * as the device is allowed to manage its own way of handling background
3140 * operations.
3141 *
3142 * Returns zero on success, non-zero on failure.
3143 */
3144static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3145{
3146 int err = 0;
3147
3148 if (hba->auto_bkops_enabled)
3149 goto out;
3150
3151 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3152 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3153 if (err) {
3154 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3155 __func__, err);
3156 goto out;
3157 }
3158
3159 hba->auto_bkops_enabled = true;
3160
3161 /* No need of URGENT_BKOPS exception from the device */
3162 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3163 if (err)
3164 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3165 __func__, err);
3166out:
3167 return err;
3168}
3169
3170/**
3171 * ufshcd_disable_auto_bkops - block device in doing background operations
3172 * @hba: per-adapter instance
3173 *
3174 * Disabling background operations improves command response latency but
3175 * has drawback of device moving into critical state where the device is
3176 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3177 * host is idle so that BKOPS are managed effectively without any negative
3178 * impacts.
3179 *
3180 * Returns zero on success, non-zero on failure.
3181 */
3182static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3183{
3184 int err = 0;
3185
3186 if (!hba->auto_bkops_enabled)
3187 goto out;
3188
3189 /*
3190 * If host assisted BKOPs is to be enabled, make sure
3191 * urgent bkops exception is allowed.
3192 */
3193 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3194 if (err) {
3195 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3196 __func__, err);
3197 goto out;
3198 }
3199
3200 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
3201 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3202 if (err) {
3203 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3204 __func__, err);
3205 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3206 goto out;
3207 }
3208
3209 hba->auto_bkops_enabled = false;
3210out:
3211 return err;
3212}
3213
3214/**
3215 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3216 * @hba: per adapter instance
3217 *
3218 * After a device reset the device may toggle the BKOPS_EN flag
3219 * to default value. The s/w tracking variables should be updated
3220 * as well. Do this by forcing enable of auto bkops.
3221 */
3222static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3223{
3224 hba->auto_bkops_enabled = false;
3225 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3226 ufshcd_enable_auto_bkops(hba);
3227}
3228
3229static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3230{
3231 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3232 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3233}
3234
3235/**
57d104c1 3236 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3237 * @hba: per-adapter instance
57d104c1 3238 * @status: bkops_status value
66ec6d59 3239 *
57d104c1
SJ		 3240 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3241 * flag in the device to permit background operations if the device
3242 * bkops_status is greater than or equal to "status" argument passed to
3243 * this function, disable otherwise.
3244 *
3245 * Returns 0 for success, non-zero in case of failure.
3246 *
3247 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3248 * to know whether auto bkops is enabled or disabled after this function
3249 * returns control to it.
66ec6d59 3250 */
57d104c1
SJ		 3251static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3252 enum bkops_status status)
66ec6d59
SRT		 3253{
3254 int err;
57d104c1 3255 u32 curr_status = 0;
66ec6d59 3256
57d104c1 3257 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3258 if (err) {
3259 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3260 __func__, err);
3261 goto out;
57d104c1
SJ		 3262 } else if (curr_status > BKOPS_STATUS_MAX) {
3263 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3264 __func__, curr_status);
3265 err = -EINVAL;
3266 goto out;
66ec6d59
SRT		 3267 }
3268
57d104c1 3269 if (curr_status >= status)
66ec6d59 3270 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3271 else
3272 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3273out:
3274 return err;
3275}
3276
57d104c1
SJ		 3277/**
3278 * ufshcd_urgent_bkops - handle urgent bkops exception event
3279 * @hba: per-adapter instance
3280 *
3281 * Enable fBackgroundOpsEn flag in the device to permit background
3282 * operations.
3283 *
3284 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3285 * and negative error value for any other failure.
3286 */
3287static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3288{
3289 return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
3290}
3291
66ec6d59
SRT		 3292static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3293{
3294 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3295 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3296}
3297
3298/**
3299 * ufshcd_exception_event_handler - handle exceptions raised by device
3300 * @work: pointer to work data
3301 *
3302 * Read bExceptionEventStatus attribute from the device and handle the
3303 * exception event accordingly.
3304 */
3305static void ufshcd_exception_event_handler(struct work_struct *work)
3306{
3307 struct ufs_hba *hba;
3308 int err;
3309 u32 status = 0;
3310 hba = container_of(work, struct ufs_hba, eeh_work);
3311
62694735 3312 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3313 err = ufshcd_get_ee_status(hba, &status);
3314 if (err) {
3315 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3316 __func__, err);
3317 goto out;
3318 }
3319
3320 status &= hba->ee_ctrl_mask;
3321 if (status & MASK_EE_URGENT_BKOPS) {
3322 err = ufshcd_urgent_bkops(hba);
57d104c1 3323 if (err < 0)
66ec6d59
SRT		 3324 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3325 __func__, err);
3326 }
3327out:
62694735 3328 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3329 return;
3330}
3331
7a3e97b0 3332/**
e8e7f271
SRT		 3333 * ufshcd_err_handler - handle UFS errors that require s/w attention
3334 * @work: pointer to work structure
7a3e97b0 3335 */
e8e7f271 3336static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 3337{
3338 struct ufs_hba *hba;
e8e7f271
SRT		 3339 unsigned long flags;
3340 u32 err_xfer = 0;
3341 u32 err_tm = 0;
3342 int err = 0;
3343 int tag;
3344
3345 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 3346
62694735 3347 pm_runtime_get_sync(hba->dev);
1ab27c9c 3348 ufshcd_hold(hba, false);
e8e7f271
SRT		 3349
3350 spin_lock_irqsave(hba->host->host_lock, flags);
3351 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
3352 spin_unlock_irqrestore(hba->host->host_lock, flags);
3353 goto out;
3354 }
3355
3356 hba->ufshcd_state = UFSHCD_STATE_RESET;
3357 ufshcd_set_eh_in_progress(hba);
3358
3359 /* Complete requests that have door-bell cleared by h/w */
3360 ufshcd_transfer_req_compl(hba);
3361 ufshcd_tmc_handler(hba);
3362 spin_unlock_irqrestore(hba->host->host_lock, flags);
3363
3364 /* Clear pending transfer requests */
3365 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
3366 if (ufshcd_clear_cmd(hba, tag))
3367 err_xfer |= 1 << tag;
3368
3369 /* Clear pending task management requests */
3370 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
3371 if (ufshcd_clear_tm_cmd(hba, tag))
3372 err_tm |= 1 << tag;
3373
3374 /* Complete the requests that are cleared by s/w */
3375 spin_lock_irqsave(hba->host->host_lock, flags);
3376 ufshcd_transfer_req_compl(hba);
3377 ufshcd_tmc_handler(hba);
3378 spin_unlock_irqrestore(hba->host->host_lock, flags);
3379
3380 /* Fatal errors need reset */
3381 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
3382 ((hba->saved_err & UIC_ERROR) &&
3383 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
3384 err = ufshcd_reset_and_restore(hba);
3385 if (err) {
3386 dev_err(hba->dev, "%s: reset and restore failed\n",
3387 __func__);
3388 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3389 }
3390 /*
3391 * Inform scsi mid-layer that we did reset and allow to handle
3392 * Unit Attention properly.
3393 */
3394 scsi_report_bus_reset(hba->host, 0);
3395 hba->saved_err = 0;
3396 hba->saved_uic_err = 0;
3397 }
3398 ufshcd_clear_eh_in_progress(hba);
3399
3400out:
3401 scsi_unblock_requests(hba->host);
1ab27c9c 3402 ufshcd_release(hba);
62694735 3403 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 3404}
3405
3406/**
e8e7f271
SRT		 3407 * ufshcd_update_uic_error - check and set fatal UIC error flags.
3408 * @hba: per-adapter instance
7a3e97b0 3409 */
e8e7f271 3410static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 3411{
3412 u32 reg;
3413
e8e7f271
SRT		 3414 /* PA_INIT_ERROR is fatal and needs UIC reset */
3415 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
3416 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
3417 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
3418
3419 /* UIC NL/TL/DME errors needs software retry */
3420 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
3421 if (reg)
3422 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
3423
3424 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
3425 if (reg)
3426 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
3427
3428 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
3429 if (reg)
3430 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
3431
3432 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
3433 __func__, hba->uic_error);
3434}
3435
3436/**
3437 * ufshcd_check_errors - Check for errors that need s/w attention
3438 * @hba: per-adapter instance
3439 */
3440static void ufshcd_check_errors(struct ufs_hba *hba)
3441{
3442 bool queue_eh_work = false;
3443
7a3e97b0 3444 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 3445 queue_eh_work = true;
7a3e97b0
SY		 3446
3447 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 3448 hba->uic_error = 0;
3449 ufshcd_update_uic_error(hba);
3450 if (hba->uic_error)
3451 queue_eh_work = true;
7a3e97b0 3452 }
e8e7f271
SRT		 3453
3454 if (queue_eh_work) {
3455 /* handle fatal errors only when link is functional */
3456 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
3457 /* block commands from scsi mid-layer */
3458 scsi_block_requests(hba->host);
3459
3460 /* transfer error masks to sticky bits */
3461 hba->saved_err |= hba->errors;
3462 hba->saved_uic_err |= hba->uic_error;
3463
3464 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3465 schedule_work(&hba->eh_work);
3466 }
3441da7d 3467 }
e8e7f271
SRT		 3468 /*
3469 * if (!queue_eh_work) -
3470 * Other errors are either non-fatal where host recovers
3471 * itself without s/w intervention or errors that will be
3472 * handled by the SCSI core layer.
3473 */
7a3e97b0
SY		 3474}
3475
3476/**
3477 * ufshcd_tmc_handler - handle task management function completion
3478 * @hba: per adapter instance
3479 */
3480static void ufshcd_tmc_handler(struct ufs_hba *hba)
3481{
3482 u32 tm_doorbell;
3483
b873a275 3484 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 3485 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 3486 wake_up(&hba->tm_wq);
7a3e97b0
SY		 3487}
3488
3489/**
3490 * ufshcd_sl_intr - Interrupt service routine
3491 * @hba: per adapter instance
3492 * @intr_status: contains interrupts generated by the controller
3493 */
3494static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
3495{
3496 hba->errors = UFSHCD_ERROR_MASK & intr_status;
3497 if (hba->errors)
e8e7f271 3498 ufshcd_check_errors(hba);
7a3e97b0 3499
53b3d9c3
SJ		 3500 if (intr_status & UFSHCD_UIC_MASK)
3501 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 3502
3503 if (intr_status & UTP_TASK_REQ_COMPL)
3504 ufshcd_tmc_handler(hba);
3505
3506 if (intr_status & UTP_TRANSFER_REQ_COMPL)
3507 ufshcd_transfer_req_compl(hba);
3508}
3509
3510/**
3511 * ufshcd_intr - Main interrupt service routine
3512 * @irq: irq number
3513 * @__hba: pointer to adapter instance
3514 *
3515 * Returns IRQ_HANDLED - If interrupt is valid
3516 * IRQ_NONE - If invalid interrupt
3517 */
3518static irqreturn_t ufshcd_intr(int irq, void *__hba)
3519{
3520 u32 intr_status;
3521 irqreturn_t retval = IRQ_NONE;
3522 struct ufs_hba *hba = __hba;
3523
3524 spin_lock(hba->host->host_lock);
b873a275 3525 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 3526
3527 if (intr_status) {
261ea452 3528 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 3529 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 3530 retval = IRQ_HANDLED;
3531 }
3532 spin_unlock(hba->host->host_lock);
3533 return retval;
3534}
3535
e2933132
SRT		 3536static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
3537{
3538 int err = 0;
3539 u32 mask = 1 << tag;
3540 unsigned long flags;
3541
3542 if (!test_bit(tag, &hba->outstanding_tasks))
3543 goto out;
3544
3545 spin_lock_irqsave(hba->host->host_lock, flags);
3546 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
3547 spin_unlock_irqrestore(hba->host->host_lock, flags);
3548
3549 /* poll for max. 1 sec to clear door bell register by h/w */
3550 err = ufshcd_wait_for_register(hba,
3551 REG_UTP_TASK_REQ_DOOR_BELL,
3552 mask, 0, 1000, 1000);
3553out:
3554 return err;
3555}
3556
7a3e97b0
SY		 3557/**
3558 * ufshcd_issue_tm_cmd - issues task management commands to controller
3559 * @hba: per adapter instance
e2933132
SRT		 3560 * @lun_id: LUN ID to which TM command is sent
3561 * @task_id: task ID to which the TM command is applicable
3562 * @tm_function: task management function opcode
3563 * @tm_response: task management service response return value
7a3e97b0 3564 *
e2933132 3565 * Returns non-zero value on error, zero on success.
7a3e97b0 3566 */
e2933132
SRT		 3567static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
3568 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 3569{
3570 struct utp_task_req_desc *task_req_descp;
3571 struct utp_upiu_task_req *task_req_upiup;
3572 struct Scsi_Host *host;
3573 unsigned long flags;
e2933132 3574 int free_slot;
7a3e97b0 3575 int err;
e2933132 3576 int task_tag;
7a3e97b0
SY		 3577
3578 host = hba->host;
3579
e2933132
SRT		 3580 /*
3581 * Get free slot, sleep if slots are unavailable.
3582 * Even though we use wait_event() which sleeps indefinitely,
3583 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
3584 */
3585 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 3586 ufshcd_hold(hba, false);
7a3e97b0 3587
e2933132 3588 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3589 task_req_descp = hba->utmrdl_base_addr;
3590 task_req_descp += free_slot;
3591
3592 /* Configure task request descriptor */
3593 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
3594 task_req_descp->header.dword_2 =
3595 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
3596
3597 /* Configure task request UPIU */
3598 task_req_upiup =
3599 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 3600 task_tag = hba->nutrs + free_slot;
7a3e97b0 3601 task_req_upiup->header.dword_0 =
5a0b0cb9 3602 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 3603 lun_id, task_tag);
7a3e97b0 3604 task_req_upiup->header.dword_1 =
5a0b0cb9 3605 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 3606 /*
3607 * The host shall provide the same value for LUN field in the basic
3608 * header and for Input Parameter.
3609 */
e2933132
SRT		 3610 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
3611 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 3612
3613 /* send command to the controller */
3614 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 3615 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 3616
3617 spin_unlock_irqrestore(host->host_lock, flags);
3618
3619 /* wait until the task management command is completed */
e2933132
SRT		 3620 err = wait_event_timeout(hba->tm_wq,
3621 test_bit(free_slot, &hba->tm_condition),
3622 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 3623 if (!err) {
e2933132
SRT		 3624 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
3625 __func__, tm_function);
3626 if (ufshcd_clear_tm_cmd(hba, free_slot))
3627 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
3628 __func__, free_slot);
3629 err = -ETIMEDOUT;
3630 } else {
3631 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 3632 }
e2933132 3633
7a3e97b0 3634 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 3635 ufshcd_put_tm_slot(hba, free_slot);
3636 wake_up(&hba->tm_tag_wq);
3637
1ab27c9c 3638 ufshcd_release(hba);
7a3e97b0
SY		 3639 return err;
3640}
3641
3642/**
3441da7d
SRT		 3643 * ufshcd_eh_device_reset_handler - device reset handler registered to
3644 * scsi layer.
7a3e97b0
SY		 3645 * @cmd: SCSI command pointer
3646 *
3647 * Returns SUCCESS/FAILED
3648 */
3441da7d 3649static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 3650{
3651 struct Scsi_Host *host;
3652 struct ufs_hba *hba;
3653 unsigned int tag;
3654 u32 pos;
3655 int err;
e2933132
SRT		 3656 u8 resp = 0xF;
3657 struct ufshcd_lrb *lrbp;
3441da7d 3658 unsigned long flags;
7a3e97b0
SY		 3659
3660 host = cmd->device->host;
3661 hba = shost_priv(host);
3662 tag = cmd->request->tag;
3663
e2933132
SRT		 3664 lrbp = &hba->lrb[tag];
3665 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
3666 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 3667 if (!err)
3668 err = resp;
7a3e97b0 3669 goto out;
e2933132 3670 }
7a3e97b0 3671
3441da7d
SRT		 3672 /* clear the commands that were pending for corresponding LUN */
3673 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3674 if (hba->lrb[pos].lun == lrbp->lun) {
3675 err = ufshcd_clear_cmd(hba, pos);
3676 if (err)
3677 break;
7a3e97b0 3678 }
3441da7d
SRT		 3679 }
3680 spin_lock_irqsave(host->host_lock, flags);
3681 ufshcd_transfer_req_compl(hba);
3682 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 3683out:
3441da7d
SRT		 3684 if (!err) {
3685 err = SUCCESS;
3686 } else {
3687 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3688 err = FAILED;
3689 }
7a3e97b0
SY		 3690 return err;
3691}
3692
7a3e97b0
SY		 3693/**
3694 * ufshcd_abort - abort a specific command
3695 * @cmd: SCSI command pointer
3696 *
f20810d8
SRT		 3697 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3698 * command, and in host controller by clearing the door-bell register. There can
3699 * be race between controller sending the command to the device while abort is
3700 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3701 * really issued and then try to abort it.
3702 *
7a3e97b0
SY		 3703 * Returns SUCCESS/FAILED
3704 */
3705static int ufshcd_abort(struct scsi_cmnd *cmd)
3706{
3707 struct Scsi_Host *host;
3708 struct ufs_hba *hba;
3709 unsigned long flags;
3710 unsigned int tag;
f20810d8
SRT		 3711 int err = 0;
3712 int poll_cnt;
e2933132
SRT		 3713 u8 resp = 0xF;
3714 struct ufshcd_lrb *lrbp;
e9d501b1 3715 u32 reg;
7a3e97b0
SY		 3716
3717 host = cmd->device->host;
3718 hba = shost_priv(host);
3719 tag = cmd->request->tag;
3720
1ab27c9c 3721 ufshcd_hold(hba, false);
f20810d8
SRT		 3722 /* If command is already aborted/completed, return SUCCESS */
3723 if (!(test_bit(tag, &hba->outstanding_reqs)))
3724 goto out;
7a3e97b0 3725
e9d501b1
DR		 3726 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3727 if (!(reg & (1 << tag))) {
3728 dev_err(hba->dev,
3729 "%s: cmd was completed, but without a notifying intr, tag = %d",
3730 __func__, tag);
3731 }
3732
f20810d8
SRT		 3733 lrbp = &hba->lrb[tag];
3734 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3735 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3736 UFS_QUERY_TASK, &resp);
3737 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3738 /* cmd pending in the device */
3739 break;
3740 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3741 /*
3742 * cmd not pending in the device, check if it is
3743 * in transition.
3744 */
3745 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3746 if (reg & (1 << tag)) {
3747 /* sleep for max. 200us to stabilize */
3748 usleep_range(100, 200);
3749 continue;
3750 }
3751 /* command completed already */
3752 goto out;
3753 } else {
3754 if (!err)
3755 err = resp; /* service response error */
3756 goto out;
3757 }
3758 }
3759
3760 if (!poll_cnt) {
3761 err = -EBUSY;
7a3e97b0
SY		 3762 goto out;
3763 }
7a3e97b0 3764
e2933132
SRT		 3765 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3766 UFS_ABORT_TASK, &resp);
3767 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3768 if (!err)
3769 err = resp; /* service response error */
7a3e97b0 3770 goto out;
e2933132 3771 }
7a3e97b0 3772
f20810d8
SRT		 3773 err = ufshcd_clear_cmd(hba, tag);
3774 if (err)
3775 goto out;
3776
7a3e97b0
SY		 3777 scsi_dma_unmap(cmd);
3778
3779 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3780 __clear_bit(tag, &hba->outstanding_reqs);
3781 hba->lrb[tag].cmd = NULL;
3782 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 3783
3784 clear_bit_unlock(tag, &hba->lrb_in_use);
3785 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 3786
7a3e97b0 3787out:
f20810d8
SRT		 3788 if (!err) {
3789 err = SUCCESS;
3790 } else {
3791 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3792 err = FAILED;
3793 }
3794
1ab27c9c
ST		 3795 /*
3796 * This ufshcd_release() corresponds to the original scsi cmd that got
3797 * aborted here (as we won't get any IRQ for it).
3798 */
3799 ufshcd_release(hba);
7a3e97b0
SY		 3800 return err;
3801}
3802
3441da7d
SRT		 3803/**
3804 * ufshcd_host_reset_and_restore - reset and restore host controller
3805 * @hba: per-adapter instance
3806 *
3807 * Note that host controller reset may issue DME_RESET to
3808 * local and remote (device) Uni-Pro stack and the attributes
3809 * are reset to default state.
3810 *
3811 * Returns zero on success, non-zero on failure
3812 */
3813static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
3814{
3815 int err;
3441da7d
SRT		 3816 unsigned long flags;
3817
3818 /* Reset the host controller */
3819 spin_lock_irqsave(hba->host->host_lock, flags);
3820 ufshcd_hba_stop(hba);
3821 spin_unlock_irqrestore(hba->host->host_lock, flags);
3822
3823 err = ufshcd_hba_enable(hba);
3824 if (err)
3825 goto out;
3826
3827 /* Establish the link again and restore the device */
1d337ec2
SRT		 3828 err = ufshcd_probe_hba(hba);
3829
3830 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 3831 err = -EIO;
3832out:
3833 if (err)
3834 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
3835
3836 return err;
3837}
3838
3839/**
3840 * ufshcd_reset_and_restore - reset and re-initialize host/device
3841 * @hba: per-adapter instance
3842 *
3843 * Reset and recover device, host and re-establish link. This
3844 * is helpful to recover the communication in fatal error conditions.
3845 *
3846 * Returns zero on success, non-zero on failure
3847 */
3848static int ufshcd_reset_and_restore(struct ufs_hba *hba)
3849{
3850 int err = 0;
3851 unsigned long flags;
1d337ec2 3852 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 3853
1d337ec2
SRT		 3854 do {
3855 err = ufshcd_host_reset_and_restore(hba);
3856 } while (err && --retries);
3441da7d
SRT		 3857
3858 /*
3859 * After reset the door-bell might be cleared, complete
3860 * outstanding requests in s/w here.
3861 */
3862 spin_lock_irqsave(hba->host->host_lock, flags);
3863 ufshcd_transfer_req_compl(hba);
3864 ufshcd_tmc_handler(hba);
3865 spin_unlock_irqrestore(hba->host->host_lock, flags);
3866
3867 return err;
3868}
3869
3870/**
3871 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
3872 * @cmd - SCSI command pointer
3873 *
3874 * Returns SUCCESS/FAILED
3875 */
3876static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
3877{
3878 int err;
3879 unsigned long flags;
3880 struct ufs_hba *hba;
3881
3882 hba = shost_priv(cmd->device->host);
3883
1ab27c9c 3884 ufshcd_hold(hba, false);
3441da7d
SRT		 3885 /*
3886 * Check if there is any race with fatal error handling.
3887 * If so, wait for it to complete. Even though fatal error
3888 * handling does reset and restore in some cases, don't assume
3889 * anything out of it. We are just avoiding race here.
3890 */
3891 do {
3892 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 3893 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 3894 hba->ufshcd_state == UFSHCD_STATE_RESET))
3895 break;
3896 spin_unlock_irqrestore(hba->host->host_lock, flags);
3897 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 3898 flush_work(&hba->eh_work);
3441da7d
SRT		 3899 } while (1);
3900
3901 hba->ufshcd_state = UFSHCD_STATE_RESET;
3902 ufshcd_set_eh_in_progress(hba);
3903 spin_unlock_irqrestore(hba->host->host_lock, flags);
3904
3905 err = ufshcd_reset_and_restore(hba);
3906
3907 spin_lock_irqsave(hba->host->host_lock, flags);
3908 if (!err) {
3909 err = SUCCESS;
3910 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
3911 } else {
3912 err = FAILED;
3913 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3914 }
3915 ufshcd_clear_eh_in_progress(hba);
3916 spin_unlock_irqrestore(hba->host->host_lock, flags);
3917
1ab27c9c 3918 ufshcd_release(hba);
3441da7d
SRT		 3919 return err;
3920}
3921
3a4bf06d
YG		 3922/**
3923 * ufshcd_get_max_icc_level - calculate the ICC level
3924 * @sup_curr_uA: max. current supported by the regulator
3925 * @start_scan: row at the desc table to start scan from
3926 * @buff: power descriptor buffer
3927 *
3928 * Returns calculated max ICC level for specific regulator
3929 */
3930static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
3931{
3932 int i;
3933 int curr_uA;
3934 u16 data;
3935 u16 unit;
3936
3937 for (i = start_scan; i >= 0; i--) {
3938 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
3939 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
3940 ATTR_ICC_LVL_UNIT_OFFSET;
3941 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
3942 switch (unit) {
3943 case UFSHCD_NANO_AMP:
3944 curr_uA = curr_uA / 1000;
3945 break;
3946 case UFSHCD_MILI_AMP:
3947 curr_uA = curr_uA * 1000;
3948 break;
3949 case UFSHCD_AMP:
3950 curr_uA = curr_uA * 1000 * 1000;
3951 break;
3952 case UFSHCD_MICRO_AMP:
3953 default:
3954 break;
3955 }
3956 if (sup_curr_uA >= curr_uA)
3957 break;
3958 }
3959 if (i < 0) {
3960 i = 0;
3961 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
3962 }
3963
3964 return (u32)i;
3965}
3966
3967/**
3968 * ufshcd_calc_icc_level - calculate the max ICC level
3969 * In case regulators are not initialized we'll return 0
3970 * @hba: per-adapter instance
3971 * @desc_buf: power descriptor buffer to extract ICC levels from.
3972 * @len: length of desc_buff
3973 *
3974 * Returns calculated ICC level
3975 */
3976static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
3977 u8 *desc_buf, int len)
3978{
3979 u32 icc_level = 0;
3980
3981 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
3982 !hba->vreg_info.vccq2) {
3983 dev_err(hba->dev,
3984 "%s: Regulator capability was not set, actvIccLevel=%d",
3985 __func__, icc_level);
3986 goto out;
3987 }
3988
3989 if (hba->vreg_info.vcc)
3990 icc_level = ufshcd_get_max_icc_level(
3991 hba->vreg_info.vcc->max_uA,
3992 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
3993 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
3994
3995 if (hba->vreg_info.vccq)
3996 icc_level = ufshcd_get_max_icc_level(
3997 hba->vreg_info.vccq->max_uA,
3998 icc_level,
3999 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4000
4001 if (hba->vreg_info.vccq2)
4002 icc_level = ufshcd_get_max_icc_level(
4003 hba->vreg_info.vccq2->max_uA,
4004 icc_level,
4005 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4006out:
4007 return icc_level;
4008}
4009
4010static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4011{
4012 int ret;
4013 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4014 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4015
4016 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4017 if (ret) {
4018 dev_err(hba->dev,
4019 "%s: Failed reading power descriptor.len = %d ret = %d",
4020 __func__, buff_len, ret);
4021 return;
4022 }
4023
4024 hba->init_prefetch_data.icc_level =
4025 ufshcd_find_max_sup_active_icc_level(hba,
4026 desc_buf, buff_len);
4027 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4028 __func__, hba->init_prefetch_data.icc_level);
4029
4030 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4031 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4032 &hba->init_prefetch_data.icc_level);
4033
4034 if (ret)
4035 dev_err(hba->dev,
4036 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4037 __func__, hba->init_prefetch_data.icc_level , ret);
4038
4039}
4040
2a8fa600
SJ		 4041/**
4042 * ufshcd_scsi_add_wlus - Adds required W-LUs
4043 * @hba: per-adapter instance
4044 *
4045 * UFS device specification requires the UFS devices to support 4 well known
4046 * logical units:
4047 * "REPORT_LUNS" (address: 01h)
4048 * "UFS Device" (address: 50h)
4049 * "RPMB" (address: 44h)
4050 * "BOOT" (address: 30h)
4051 * UFS device's power management needs to be controlled by "POWER CONDITION"
4052 * field of SSU (START STOP UNIT) command. But this "power condition" field
4053 * will take effect only when its sent to "UFS device" well known logical unit
4054 * hence we require the scsi_device instance to represent this logical unit in
4055 * order for the UFS host driver to send the SSU command for power management.
4056
4057 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4058 * Block) LU so user space process can control this LU. User space may also
4059 * want to have access to BOOT LU.
4060
4061 * This function adds scsi device instances for each of all well known LUs
4062 * (except "REPORT LUNS" LU).
4063 *
4064 * Returns zero on success (all required W-LUs are added successfully),
4065 * non-zero error value on failure (if failed to add any of the required W-LU).
4066 */
4067static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4068{
4069 int ret = 0;
7c48bfd0
AM		 4070 struct scsi_device *sdev_rpmb;
4071 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4072
4073 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4074 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4075 if (IS_ERR(hba->sdev_ufs_device)) {
4076 ret = PTR_ERR(hba->sdev_ufs_device);
4077 hba->sdev_ufs_device = NULL;
4078 goto out;
4079 }
7c48bfd0 4080 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4081
7c48bfd0 4082 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4083 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4084 if (IS_ERR(sdev_boot)) {
4085 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4086 goto remove_sdev_ufs_device;
4087 }
7c48bfd0 4088 scsi_device_put(sdev_boot);
2a8fa600 4089
7c48bfd0 4090 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4091 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4092 if (IS_ERR(sdev_rpmb)) {
4093 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4094 goto remove_sdev_boot;
4095 }
7c48bfd0 4096 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4097 goto out;
4098
4099remove_sdev_boot:
7c48bfd0 4100 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4101remove_sdev_ufs_device:
4102 scsi_remove_device(hba->sdev_ufs_device);
4103out:
4104 return ret;
4105}
4106
6ccf44fe 4107/**
1d337ec2
SRT		 4108 * ufshcd_probe_hba - probe hba to detect device and initialize
4109 * @hba: per-adapter instance
4110 *
4111 * Execute link-startup and verify device initialization
6ccf44fe 4112 */
1d337ec2 4113static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 4114{
6ccf44fe
SJ		 4115 int ret;
4116
4117 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 4118 if (ret)
4119 goto out;
4120
57d104c1
SJ		 4121 /* UniPro link is active now */
4122 ufshcd_set_link_active(hba);
d3e89bac 4123
5a0b0cb9
SRT		 4124 ret = ufshcd_verify_dev_init(hba);
4125 if (ret)
4126 goto out;
68078d5c
DR		 4127
4128 ret = ufshcd_complete_dev_init(hba);
4129 if (ret)
4130 goto out;
5a0b0cb9 4131
57d104c1
SJ		 4132 /* UFS device is also active now */
4133 ufshcd_set_ufs_dev_active(hba);
66ec6d59 4134 ufshcd_force_reset_auto_bkops(hba);
3441da7d 4135 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 4136 hba->wlun_dev_clr_ua = true;
4137
7eb584db
DR		 4138 if (ufshcd_get_max_pwr_mode(hba)) {
4139 dev_err(hba->dev,
4140 "%s: Failed getting max supported power mode\n",
4141 __func__);
4142 } else {
4143 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
4144 if (ret)
4145 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
4146 __func__, ret);
4147 }
57d104c1
SJ		 4148
4149 /*
4150 * If we are in error handling context or in power management callbacks
4151 * context, no need to scan the host
4152 */
4153 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4154 bool flag;
4155
4156 /* clear any previous UFS device information */
4157 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
4158 if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4159 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
4160 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 4161
3a4bf06d
YG		 4162 if (!hba->is_init_prefetch)
4163 ufshcd_init_icc_levels(hba);
4164
2a8fa600
SJ		 4165 /* Add required well known logical units to scsi mid layer */
4166 if (ufshcd_scsi_add_wlus(hba))
4167 goto out;
4168
3441da7d
SRT		 4169 scsi_scan_host(hba->host);
4170 pm_runtime_put_sync(hba->dev);
4171 }
3a4bf06d
YG		 4172
4173 if (!hba->is_init_prefetch)
4174 hba->is_init_prefetch = true;
4175
856b3483
ST		 4176 /* Resume devfreq after UFS device is detected */
4177 if (ufshcd_is_clkscaling_enabled(hba))
4178 devfreq_resume_device(hba->devfreq);
4179
5a0b0cb9 4180out:
1d337ec2
SRT		 4181 /*
4182 * If we failed to initialize the device or the device is not
4183 * present, turn off the power/clocks etc.
4184 */
57d104c1
SJ		 4185 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4186 pm_runtime_put_sync(hba->dev);
1d337ec2 4187 ufshcd_hba_exit(hba);
57d104c1 4188 }
1d337ec2
SRT		 4189
4190 return ret;
4191}
4192
4193/**
4194 * ufshcd_async_scan - asynchronous execution for probing hba
4195 * @data: data pointer to pass to this function
4196 * @cookie: cookie data
4197 */
4198static void ufshcd_async_scan(void *data, async_cookie_t cookie)
4199{
4200 struct ufs_hba *hba = (struct ufs_hba *)data;
4201
4202 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 4203}
4204
7a3e97b0
SY		 4205static struct scsi_host_template ufshcd_driver_template = {
4206 .module = THIS_MODULE,
4207 .name = UFSHCD,
4208 .proc_name = UFSHCD,
4209 .queuecommand = ufshcd_queuecommand,
4210 .slave_alloc = ufshcd_slave_alloc,
eeda4749 4211 .slave_configure = ufshcd_slave_configure,
7a3e97b0 4212 .slave_destroy = ufshcd_slave_destroy,
4264fd61 4213 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 4214 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 4215 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
4216 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 4217 .this_id = -1,
4218 .sg_tablesize = SG_ALL,
4219 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
4220 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 4221 .max_host_blocked = 1,
7a3e97b0
SY		 4222};
4223
57d104c1
SJ		 4224static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
4225 int ua)
4226{
4227 int ret = 0;
4228 struct regulator *reg = vreg->reg;
4229 const char *name = vreg->name;
4230
4231 BUG_ON(!vreg);
4232
4233 ret = regulator_set_optimum_mode(reg, ua);
4234 if (ret >= 0) {
4235 /*
4236 * regulator_set_optimum_mode() returns new regulator
4237 * mode upon success.
4238 */
4239 ret = 0;
4240 } else {
4241 dev_err(dev, "%s: %s set optimum mode(ua=%d) failed, err=%d\n",
4242 __func__, name, ua, ret);
4243 }
4244
4245 return ret;
4246}
4247
4248static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
4249 struct ufs_vreg *vreg)
4250{
4251 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
4252}
4253
4254static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
4255 struct ufs_vreg *vreg)
4256{
4257 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
4258}
4259
aa497613
SRT		 4260static int ufshcd_config_vreg(struct device *dev,
4261 struct ufs_vreg *vreg, bool on)
4262{
4263 int ret = 0;
4264 struct regulator *reg = vreg->reg;
4265 const char *name = vreg->name;
4266 int min_uV, uA_load;
4267
4268 BUG_ON(!vreg);
4269
4270 if (regulator_count_voltages(reg) > 0) {
4271 min_uV = on ? vreg->min_uV : 0;
4272 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
4273 if (ret) {
4274 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
4275 __func__, name, ret);
4276 goto out;
4277 }
4278
4279 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 4280 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
4281 if (ret)
aa497613 4282 goto out;
aa497613
SRT		 4283 }
4284out:
4285 return ret;
4286}
4287
4288static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
4289{
4290 int ret = 0;
4291
4292 if (!vreg || vreg->enabled)
4293 goto out;
4294
4295 ret = ufshcd_config_vreg(dev, vreg, true);
4296 if (!ret)
4297 ret = regulator_enable(vreg->reg);
4298
4299 if (!ret)
4300 vreg->enabled = true;
4301 else
4302 dev_err(dev, "%s: %s enable failed, err=%d\n",
4303 __func__, vreg->name, ret);
4304out:
4305 return ret;
4306}
4307
4308static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
4309{
4310 int ret = 0;
4311
4312 if (!vreg || !vreg->enabled)
4313 goto out;
4314
4315 ret = regulator_disable(vreg->reg);
4316
4317 if (!ret) {
4318 /* ignore errors on applying disable config */
4319 ufshcd_config_vreg(dev, vreg, false);
4320 vreg->enabled = false;
4321 } else {
4322 dev_err(dev, "%s: %s disable failed, err=%d\n",
4323 __func__, vreg->name, ret);
4324 }
4325out:
4326 return ret;
4327}
4328
4329static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
4330{
4331 int ret = 0;
4332 struct device *dev = hba->dev;
4333 struct ufs_vreg_info *info = &hba->vreg_info;
4334
4335 if (!info)
4336 goto out;
4337
4338 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
4339 if (ret)
4340 goto out;
4341
4342 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
4343 if (ret)
4344 goto out;
4345
4346 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
4347 if (ret)
4348 goto out;
4349
4350out:
4351 if (ret) {
4352 ufshcd_toggle_vreg(dev, info->vccq2, false);
4353 ufshcd_toggle_vreg(dev, info->vccq, false);
4354 ufshcd_toggle_vreg(dev, info->vcc, false);
4355 }
4356 return ret;
4357}
4358
6a771a65
RS		 4359static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
4360{
4361 struct ufs_vreg_info *info = &hba->vreg_info;
4362
4363 if (info)
4364 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
4365
4366 return 0;
4367}
4368
aa497613
SRT		 4369static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
4370{
4371 int ret = 0;
4372
4373 if (!vreg)
4374 goto out;
4375
4376 vreg->reg = devm_regulator_get(dev, vreg->name);
4377 if (IS_ERR(vreg->reg)) {
4378 ret = PTR_ERR(vreg->reg);
4379 dev_err(dev, "%s: %s get failed, err=%d\n",
4380 __func__, vreg->name, ret);
4381 }
4382out:
4383 return ret;
4384}
4385
4386static int ufshcd_init_vreg(struct ufs_hba *hba)
4387{
4388 int ret = 0;
4389 struct device *dev = hba->dev;
4390 struct ufs_vreg_info *info = &hba->vreg_info;
4391
4392 if (!info)
4393 goto out;
4394
4395 ret = ufshcd_get_vreg(dev, info->vcc);
4396 if (ret)
4397 goto out;
4398
4399 ret = ufshcd_get_vreg(dev, info->vccq);
4400 if (ret)
4401 goto out;
4402
4403 ret = ufshcd_get_vreg(dev, info->vccq2);
4404out:
4405 return ret;
4406}
4407
6a771a65
RS		 4408static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
4409{
4410 struct ufs_vreg_info *info = &hba->vreg_info;
4411
4412 if (info)
4413 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
4414
4415 return 0;
4416}
4417
57d104c1
SJ		 4418static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
4419 bool skip_ref_clk)
c6e79dac
SRT		 4420{
4421 int ret = 0;
4422 struct ufs_clk_info *clki;
4423 struct list_head *head = &hba->clk_list_head;
1ab27c9c 4424 unsigned long flags;
c6e79dac
SRT		 4425
4426 if (!head || list_empty(head))
4427 goto out;
4428
4429 list_for_each_entry(clki, head, list) {
4430 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 4431 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
4432 continue;
4433
c6e79dac
SRT		 4434 if (on && !clki->enabled) {
4435 ret = clk_prepare_enable(clki->clk);
4436 if (ret) {
4437 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
4438 __func__, clki->name, ret);
4439 goto out;
4440 }
4441 } else if (!on && clki->enabled) {
4442 clk_disable_unprepare(clki->clk);
4443 }
4444 clki->enabled = on;
4445 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
4446 clki->name, on ? "en" : "dis");
4447 }
4448 }
1ab27c9c
ST		 4449
4450 if (hba->vops && hba->vops->setup_clocks)
4451 ret = hba->vops->setup_clocks(hba, on);
c6e79dac
SRT		 4452out:
4453 if (ret) {
4454 list_for_each_entry(clki, head, list) {
4455 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
4456 clk_disable_unprepare(clki->clk);
4457 }
1ab27c9c
ST		 4458 } else if (!ret && on) {
4459 spin_lock_irqsave(hba->host->host_lock, flags);
4460 hba->clk_gating.state = CLKS_ON;
4461 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 4462 }
4463 return ret;
4464}
4465
57d104c1
SJ		 4466static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
4467{
4468 return __ufshcd_setup_clocks(hba, on, false);
4469}
4470
c6e79dac
SRT		 4471static int ufshcd_init_clocks(struct ufs_hba *hba)
4472{
4473 int ret = 0;
4474 struct ufs_clk_info *clki;
4475 struct device *dev = hba->dev;
4476 struct list_head *head = &hba->clk_list_head;
4477
4478 if (!head || list_empty(head))
4479 goto out;
4480
4481 list_for_each_entry(clki, head, list) {
4482 if (!clki->name)
4483 continue;
4484
4485 clki->clk = devm_clk_get(dev, clki->name);
4486 if (IS_ERR(clki->clk)) {
4487 ret = PTR_ERR(clki->clk);
4488 dev_err(dev, "%s: %s clk get failed, %d\n",
4489 __func__, clki->name, ret);
4490 goto out;
4491 }
4492
4493 if (clki->max_freq) {
4494 ret = clk_set_rate(clki->clk, clki->max_freq);
4495 if (ret) {
4496 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
4497 __func__, clki->name,
4498 clki->max_freq, ret);
4499 goto out;
4500 }
856b3483 4501 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 4502 }
4503 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
4504 clki->name, clk_get_rate(clki->clk));
4505 }
4506out:
4507 return ret;
4508}
4509
5c0c28a8
SRT		 4510static int ufshcd_variant_hba_init(struct ufs_hba *hba)
4511{
4512 int err = 0;
4513
4514 if (!hba->vops)
4515 goto out;
4516
4517 if (hba->vops->init) {
4518 err = hba->vops->init(hba);
4519 if (err)
4520 goto out;
4521 }
4522
5c0c28a8
SRT		 4523 if (hba->vops->setup_regulators) {
4524 err = hba->vops->setup_regulators(hba, true);
4525 if (err)
1ab27c9c 4526 goto out_exit;
5c0c28a8
SRT		 4527 }
4528
4529 goto out;
4530
5c0c28a8
SRT		 4531out_exit:
4532 if (hba->vops->exit)
4533 hba->vops->exit(hba);
4534out:
4535 if (err)
4536 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
4537 __func__, hba->vops ? hba->vops->name : "", err);
4538 return err;
4539}
4540
4541static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
4542{
4543 if (!hba->vops)
4544 return;
4545
4546 if (hba->vops->setup_clocks)
4547 hba->vops->setup_clocks(hba, false);
4548
4549 if (hba->vops->setup_regulators)
4550 hba->vops->setup_regulators(hba, false);
4551
4552 if (hba->vops->exit)
4553 hba->vops->exit(hba);
4554}
4555
aa497613
SRT		 4556static int ufshcd_hba_init(struct ufs_hba *hba)
4557{
4558 int err;
4559
6a771a65
RS		 4560 /*
4561 * Handle host controller power separately from the UFS device power
4562 * rails as it will help controlling the UFS host controller power
4563 * collapse easily which is different than UFS device power collapse.
4564 * Also, enable the host controller power before we go ahead with rest
4565 * of the initialization here.
4566 */
4567 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 4568 if (err)
4569 goto out;
4570
6a771a65 4571 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 4572 if (err)
4573 goto out;
4574
6a771a65
RS		 4575 err = ufshcd_init_clocks(hba);
4576 if (err)
4577 goto out_disable_hba_vreg;
4578
4579 err = ufshcd_setup_clocks(hba, true);
4580 if (err)
4581 goto out_disable_hba_vreg;
4582
c6e79dac
SRT		 4583 err = ufshcd_init_vreg(hba);
4584 if (err)
4585 goto out_disable_clks;
4586
4587 err = ufshcd_setup_vreg(hba, true);
4588 if (err)
4589 goto out_disable_clks;
4590
aa497613
SRT		 4591 err = ufshcd_variant_hba_init(hba);
4592 if (err)
4593 goto out_disable_vreg;
4594
1d337ec2 4595 hba->is_powered = true;
aa497613
SRT		 4596 goto out;
4597
4598out_disable_vreg:
4599 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 4600out_disable_clks:
4601 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 4602out_disable_hba_vreg:
4603 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 4604out:
4605 return err;
4606}
4607
4608static void ufshcd_hba_exit(struct ufs_hba *hba)
4609{
1d337ec2
SRT		 4610 if (hba->is_powered) {
4611 ufshcd_variant_hba_exit(hba);
4612 ufshcd_setup_vreg(hba, false);
4613 ufshcd_setup_clocks(hba, false);
4614 ufshcd_setup_hba_vreg(hba, false);
4615 hba->is_powered = false;
4616 }
aa497613
SRT		 4617}
4618
57d104c1
SJ		 4619static int
4620ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
4621{
4622 unsigned char cmd[6] = {REQUEST_SENSE,
4623 0,
4624 0,
4625 0,
4626 SCSI_SENSE_BUFFERSIZE,
4627 0};
4628 char *buffer;
4629 int ret;
4630
4631 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4632 if (!buffer) {
4633 ret = -ENOMEM;
4634 goto out;
4635 }
4636
4637 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
4638 SCSI_SENSE_BUFFERSIZE, NULL,
4639 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
4640 if (ret)
4641 pr_err("%s: failed with err %d\n", __func__, ret);
4642
4643 kfree(buffer);
4644out:
4645 return ret;
4646}
4647
4648/**
4649 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
4650 * power mode
4651 * @hba: per adapter instance
4652 * @pwr_mode: device power mode to set
4653 *
4654 * Returns 0 if requested power mode is set successfully
4655 * Returns non-zero if failed to set the requested power mode
4656 */
4657static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
4658 enum ufs_dev_pwr_mode pwr_mode)
4659{
4660 unsigned char cmd[6] = { START_STOP };
4661 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 4662 struct scsi_device *sdp;
4663 unsigned long flags;
57d104c1
SJ		 4664 int ret;
4665
7c48bfd0
AM		 4666 spin_lock_irqsave(hba->host->host_lock, flags);
4667 sdp = hba->sdev_ufs_device;
4668 if (sdp) {
4669 ret = scsi_device_get(sdp);
4670 if (!ret && !scsi_device_online(sdp)) {
4671 ret = -ENODEV;
4672 scsi_device_put(sdp);
4673 }
4674 } else {
4675 ret = -ENODEV;
4676 }
4677 spin_unlock_irqrestore(hba->host->host_lock, flags);
4678
4679 if (ret)
4680 return ret;
57d104c1
SJ		 4681
4682 /*
4683 * If scsi commands fail, the scsi mid-layer schedules scsi error-
4684 * handling, which would wait for host to be resumed. Since we know
4685 * we are functional while we are here, skip host resume in error
4686 * handling context.
4687 */
4688 hba->host->eh_noresume = 1;
4689 if (hba->wlun_dev_clr_ua) {
4690 ret = ufshcd_send_request_sense(hba, sdp);
4691 if (ret)
4692 goto out;
4693 /* Unit attention condition is cleared now */
4694 hba->wlun_dev_clr_ua = false;
4695 }
4696
4697 cmd[4] = pwr_mode << 4;
4698
4699 /*
4700 * Current function would be generally called from the power management
4701 * callbacks hence set the REQ_PM flag so that it doesn't resume the
4702 * already suspended childs.
4703 */
4704 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
4705 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
4706 if (ret) {
4707 sdev_printk(KERN_WARNING, sdp,
4708 "START_STOP failed for power mode: %d\n", pwr_mode);
4709 scsi_show_result(ret);
4710 if (driver_byte(ret) & DRIVER_SENSE) {
4711 scsi_show_sense_hdr(&sshdr);
4712 scsi_show_extd_sense(sshdr.asc, sshdr.ascq);
4713 }
4714 }
4715
4716 if (!ret)
4717 hba->curr_dev_pwr_mode = pwr_mode;
4718out:
7c48bfd0 4719 scsi_device_put(sdp);
57d104c1
SJ		 4720 hba->host->eh_noresume = 0;
4721 return ret;
4722}
4723
4724static int ufshcd_link_state_transition(struct ufs_hba *hba,
4725 enum uic_link_state req_link_state,
4726 int check_for_bkops)
4727{
4728 int ret = 0;
4729
4730 if (req_link_state == hba->uic_link_state)
4731 return 0;
4732
4733 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
4734 ret = ufshcd_uic_hibern8_enter(hba);
4735 if (!ret)
4736 ufshcd_set_link_hibern8(hba);
4737 else
4738 goto out;
4739 }
4740 /*
4741 * If autobkops is enabled, link can't be turned off because
4742 * turning off the link would also turn off the device.
4743 */
4744 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
4745 (!check_for_bkops || (check_for_bkops &&
4746 !hba->auto_bkops_enabled))) {
4747 /*
4748 * Change controller state to "reset state" which
4749 * should also put the link in off/reset state
4750 */
4751 ufshcd_hba_stop(hba);
4752 /*
4753 * TODO: Check if we need any delay to make sure that
4754 * controller is reset
4755 */
4756 ufshcd_set_link_off(hba);
4757 }
4758
4759out:
4760 return ret;
4761}
4762
4763static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
4764{
4765 /*
4766 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
4767 * power.
4768 *
4769 * If UFS device and link is in OFF state, all power supplies (VCC,
4770 * VCCQ, VCCQ2) can be turned off if power on write protect is not
4771 * required. If UFS link is inactive (Hibern8 or OFF state) and device
4772 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
4773 *
4774 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
4775 * in low power state which would save some power.
4776 */
4777 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4778 !hba->dev_info.is_lu_power_on_wp) {
4779 ufshcd_setup_vreg(hba, false);
4780 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4781 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4782 if (!ufshcd_is_link_active(hba)) {
4783 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4784 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
4785 }
4786 }
4787}
4788
4789static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
4790{
4791 int ret = 0;
4792
4793 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4794 !hba->dev_info.is_lu_power_on_wp) {
4795 ret = ufshcd_setup_vreg(hba, true);
4796 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4797 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
4798 if (!ret && !ufshcd_is_link_active(hba)) {
4799 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
4800 if (ret)
4801 goto vcc_disable;
4802 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
4803 if (ret)
4804 goto vccq_lpm;
4805 }
4806 }
4807 goto out;
4808
4809vccq_lpm:
4810 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4811vcc_disable:
4812 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4813out:
4814 return ret;
4815}
4816
4817static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
4818{
4819 if (ufshcd_is_link_off(hba))
4820 ufshcd_setup_hba_vreg(hba, false);
4821}
4822
4823static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
4824{
4825 if (ufshcd_is_link_off(hba))
4826 ufshcd_setup_hba_vreg(hba, true);
4827}
4828
7a3e97b0 4829/**
57d104c1 4830 * ufshcd_suspend - helper function for suspend operations
3b1d0580 4831 * @hba: per adapter instance
57d104c1
SJ		 4832 * @pm_op: desired low power operation type
4833 *
4834 * This function will try to put the UFS device and link into low power
4835 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
4836 * (System PM level).
4837 *
4838 * If this function is called during shutdown, it will make sure that
4839 * both UFS device and UFS link is powered off.
7a3e97b0 4840 *
57d104c1
SJ		 4841 * NOTE: UFS device & link must be active before we enter in this function.
4842 *
4843 * Returns 0 for success and non-zero for failure
7a3e97b0 4844 */
57d104c1 4845static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4846{
57d104c1
SJ		 4847 int ret = 0;
4848 enum ufs_pm_level pm_lvl;
4849 enum ufs_dev_pwr_mode req_dev_pwr_mode;
4850 enum uic_link_state req_link_state;
4851
4852 hba->pm_op_in_progress = 1;
4853 if (!ufshcd_is_shutdown_pm(pm_op)) {
4854 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
4855 hba->rpm_lvl : hba->spm_lvl;
4856 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
4857 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
4858 } else {
4859 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
4860 req_link_state = UIC_LINK_OFF_STATE;
4861 }
4862
7a3e97b0 4863 /*
57d104c1
SJ		 4864 * If we can't transition into any of the low power modes
4865 * just gate the clocks.
7a3e97b0 4866 */
1ab27c9c
ST		 4867 ufshcd_hold(hba, false);
4868 hba->clk_gating.is_suspended = true;
4869
57d104c1
SJ		 4870 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
4871 req_link_state == UIC_LINK_ACTIVE_STATE) {
4872 goto disable_clks;
4873 }
7a3e97b0 4874
57d104c1
SJ		 4875 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
4876 (req_link_state == hba->uic_link_state))
4877 goto out;
4878
4879 /* UFS device & link must be active before we enter in this function */
4880 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
4881 ret = -EINVAL;
4882 goto out;
4883 }
4884
4885 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 4886 if (ufshcd_can_autobkops_during_suspend(hba)) {
4887 /*
4888 * The device is idle with no requests in the queue,
4889 * allow background operations if bkops status shows
4890 * that performance might be impacted.
4891 */
4892 ret = ufshcd_urgent_bkops(hba);
4893 if (ret)
4894 goto enable_gating;
4895 } else {
4896 /* make sure that auto bkops is disabled */
4897 ufshcd_disable_auto_bkops(hba);
4898 }
57d104c1
SJ		 4899 }
4900
4901 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
4902 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
4903 !ufshcd_is_runtime_pm(pm_op))) {
4904 /* ensure that bkops is disabled */
4905 ufshcd_disable_auto_bkops(hba);
4906 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
4907 if (ret)
1ab27c9c 4908 goto enable_gating;
57d104c1
SJ		 4909 }
4910
4911 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
4912 if (ret)
4913 goto set_dev_active;
4914
4915 ufshcd_vreg_set_lpm(hba);
4916
4917disable_clks:
856b3483
ST		 4918 /*
4919 * The clock scaling needs access to controller registers. Hence, Wait
4920 * for pending clock scaling work to be done before clocks are
4921 * turned off.
4922 */
4923 if (ufshcd_is_clkscaling_enabled(hba)) {
4924 devfreq_suspend_device(hba->devfreq);
4925 hba->clk_scaling.window_start_t = 0;
4926 }
57d104c1
SJ		 4927 /*
4928 * Call vendor specific suspend callback. As these callbacks may access
4929 * vendor specific host controller register space call them before the
4930 * host clocks are ON.
4931 */
4932 if (hba->vops && hba->vops->suspend) {
4933 ret = hba->vops->suspend(hba, pm_op);
4934 if (ret)
4935 goto set_link_active;
4936 }
4937
4938 if (hba->vops && hba->vops->setup_clocks) {
4939 ret = hba->vops->setup_clocks(hba, false);
4940 if (ret)
4941 goto vops_resume;
4942 }
4943
4944 if (!ufshcd_is_link_active(hba))
4945 ufshcd_setup_clocks(hba, false);
4946 else
4947 /* If link is active, device ref_clk can't be switched off */
4948 __ufshcd_setup_clocks(hba, false, true);
4949
1ab27c9c 4950 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 4951 /*
4952 * Disable the host irq as host controller as there won't be any
4953 * host controller trasanction expected till resume.
4954 */
4955 ufshcd_disable_irq(hba);
4956 /* Put the host controller in low power mode if possible */
4957 ufshcd_hba_vreg_set_lpm(hba);
4958 goto out;
4959
4960vops_resume:
4961 if (hba->vops && hba->vops->resume)
4962 hba->vops->resume(hba, pm_op);
4963set_link_active:
4964 ufshcd_vreg_set_hpm(hba);
4965 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
4966 ufshcd_set_link_active(hba);
4967 else if (ufshcd_is_link_off(hba))
4968 ufshcd_host_reset_and_restore(hba);
4969set_dev_active:
4970 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
4971 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST		 4972enable_gating:
4973 hba->clk_gating.is_suspended = false;
4974 ufshcd_release(hba);
57d104c1
SJ		 4975out:
4976 hba->pm_op_in_progress = 0;
4977 return ret;
7a3e97b0
SY		 4978}
4979
4980/**
57d104c1 4981 * ufshcd_resume - helper function for resume operations
3b1d0580 4982 * @hba: per adapter instance
57d104c1 4983 * @pm_op: runtime PM or system PM
7a3e97b0 4984 *
57d104c1
SJ		 4985 * This function basically brings the UFS device, UniPro link and controller
4986 * to active state.
4987 *
4988 * Returns 0 for success and non-zero for failure
7a3e97b0 4989 */
57d104c1 4990static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4991{
57d104c1
SJ		 4992 int ret;
4993 enum uic_link_state old_link_state;
4994
4995 hba->pm_op_in_progress = 1;
4996 old_link_state = hba->uic_link_state;
4997
4998 ufshcd_hba_vreg_set_hpm(hba);
4999 /* Make sure clocks are enabled before accessing controller */
5000 ret = ufshcd_setup_clocks(hba, true);
5001 if (ret)
5002 goto out;
5003
57d104c1
SJ		 5004 /* enable the host irq as host controller would be active soon */
5005 ret = ufshcd_enable_irq(hba);
5006 if (ret)
5007 goto disable_irq_and_vops_clks;
5008
5009 ret = ufshcd_vreg_set_hpm(hba);
5010 if (ret)
5011 goto disable_irq_and_vops_clks;
5012
7a3e97b0 5013 /*
57d104c1
SJ		 5014 * Call vendor specific resume callback. As these callbacks may access
5015 * vendor specific host controller register space call them when the
5016 * host clocks are ON.
7a3e97b0 5017 */
57d104c1
SJ		 5018 if (hba->vops && hba->vops->resume) {
5019 ret = hba->vops->resume(hba, pm_op);
5020 if (ret)
5021 goto disable_vreg;
5022 }
5023
5024 if (ufshcd_is_link_hibern8(hba)) {
5025 ret = ufshcd_uic_hibern8_exit(hba);
5026 if (!ret)
5027 ufshcd_set_link_active(hba);
5028 else
5029 goto vendor_suspend;
5030 } else if (ufshcd_is_link_off(hba)) {
5031 ret = ufshcd_host_reset_and_restore(hba);
5032 /*
5033 * ufshcd_host_reset_and_restore() should have already
5034 * set the link state as active
5035 */
5036 if (ret || !ufshcd_is_link_active(hba))
5037 goto vendor_suspend;
5038 }
5039
5040 if (!ufshcd_is_ufs_dev_active(hba)) {
5041 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
5042 if (ret)
5043 goto set_old_link_state;
5044 }
5045
374a246e
SJ		 5046 /*
5047 * If BKOPs operations are urgently needed at this moment then
5048 * keep auto-bkops enabled or else disable it.
5049 */
5050 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 5051 hba->clk_gating.is_suspended = false;
5052
856b3483
ST		 5053 if (ufshcd_is_clkscaling_enabled(hba))
5054 devfreq_resume_device(hba->devfreq);
5055
1ab27c9c
ST		 5056 /* Schedule clock gating in case of no access to UFS device yet */
5057 ufshcd_release(hba);
57d104c1
SJ		 5058 goto out;
5059
5060set_old_link_state:
5061 ufshcd_link_state_transition(hba, old_link_state, 0);
5062vendor_suspend:
5063 if (hba->vops && hba->vops->suspend)
5064 hba->vops->suspend(hba, pm_op);
5065disable_vreg:
5066 ufshcd_vreg_set_lpm(hba);
5067disable_irq_and_vops_clks:
5068 ufshcd_disable_irq(hba);
57d104c1
SJ		 5069 ufshcd_setup_clocks(hba, false);
5070out:
5071 hba->pm_op_in_progress = 0;
5072 return ret;
5073}
5074
5075/**
5076 * ufshcd_system_suspend - system suspend routine
5077 * @hba: per adapter instance
5078 * @pm_op: runtime PM or system PM
5079 *
5080 * Check the description of ufshcd_suspend() function for more details.
5081 *
5082 * Returns 0 for success and non-zero for failure
5083 */
5084int ufshcd_system_suspend(struct ufs_hba *hba)
5085{
5086 int ret = 0;
5087
5088 if (!hba || !hba->is_powered)
5089 goto out;
5090
5091 if (pm_runtime_suspended(hba->dev)) {
5092 if (hba->rpm_lvl == hba->spm_lvl)
5093 /*
5094 * There is possibility that device may still be in
5095 * active state during the runtime suspend.
5096 */
5097 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
5098 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
5099 goto out;
5100
5101 /*
5102 * UFS device and/or UFS link low power states during runtime
5103 * suspend seems to be different than what is expected during
5104 * system suspend. Hence runtime resume the devic & link and
5105 * let the system suspend low power states to take effect.
5106 * TODO: If resume takes longer time, we might have optimize
5107 * it in future by not resuming everything if possible.
5108 */
5109 ret = ufshcd_runtime_resume(hba);
5110 if (ret)
5111 goto out;
5112 }
5113
5114 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
5115out:
e785060e
DR		 5116 if (!ret)
5117 hba->is_sys_suspended = true;
57d104c1
SJ		 5118 return ret;
5119}
5120EXPORT_SYMBOL(ufshcd_system_suspend);
5121
5122/**
5123 * ufshcd_system_resume - system resume routine
5124 * @hba: per adapter instance
5125 *
5126 * Returns 0 for success and non-zero for failure
5127 */
7a3e97b0 5128
57d104c1
SJ		 5129int ufshcd_system_resume(struct ufs_hba *hba)
5130{
5131 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
5132 /*
5133 * Let the runtime resume take care of resuming
5134 * if runtime suspended.
5135 */
5136 return 0;
5137
5138 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 5139}
57d104c1 5140EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 5141
57d104c1
SJ		 5142/**
5143 * ufshcd_runtime_suspend - runtime suspend routine
5144 * @hba: per adapter instance
5145 *
5146 * Check the description of ufshcd_suspend() function for more details.
5147 *
5148 * Returns 0 for success and non-zero for failure
5149 */
66ec6d59
SRT		 5150int ufshcd_runtime_suspend(struct ufs_hba *hba)
5151{
57d104c1 5152 if (!hba || !hba->is_powered)
66ec6d59
SRT		 5153 return 0;
5154
57d104c1 5155 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5156}
5157EXPORT_SYMBOL(ufshcd_runtime_suspend);
5158
57d104c1
SJ		 5159/**
5160 * ufshcd_runtime_resume - runtime resume routine
5161 * @hba: per adapter instance
5162 *
5163 * This function basically brings the UFS device, UniPro link and controller
5164 * to active state. Following operations are done in this function:
5165 *
5166 * 1. Turn on all the controller related clocks
5167 * 2. Bring the UniPro link out of Hibernate state
5168 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
5169 * to active state.
5170 * 4. If auto-bkops is enabled on the device, disable it.
5171 *
5172 * So following would be the possible power state after this function return
5173 * successfully:
5174 * S1: UFS device in Active state with VCC rail ON
5175 * UniPro link in Active state
5176 * All the UFS/UniPro controller clocks are ON
5177 *
5178 * Returns 0 for success and non-zero for failure
5179 */
66ec6d59
SRT		 5180int ufshcd_runtime_resume(struct ufs_hba *hba)
5181{
57d104c1 5182 if (!hba || !hba->is_powered)
66ec6d59 5183 return 0;
57d104c1
SJ		 5184 else
5185 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5186}
5187EXPORT_SYMBOL(ufshcd_runtime_resume);
5188
5189int ufshcd_runtime_idle(struct ufs_hba *hba)
5190{
5191 return 0;
5192}
5193EXPORT_SYMBOL(ufshcd_runtime_idle);
5194
57d104c1
SJ		 5195/**
5196 * ufshcd_shutdown - shutdown routine
5197 * @hba: per adapter instance
5198 *
5199 * This function would power off both UFS device and UFS link.
5200 *
5201 * Returns 0 always to allow force shutdown even in case of errors.
5202 */
5203int ufshcd_shutdown(struct ufs_hba *hba)
5204{
5205 int ret = 0;
5206
5207 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
5208 goto out;
5209
5210 if (pm_runtime_suspended(hba->dev)) {
5211 ret = ufshcd_runtime_resume(hba);
5212 if (ret)
5213 goto out;
5214 }
5215
5216 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
5217out:
5218 if (ret)
5219 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
5220 /* allow force shutdown even in case of errors */
5221 return 0;
5222}
5223EXPORT_SYMBOL(ufshcd_shutdown);
5224
7a3e97b0 5225/**
3b1d0580 5226 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 5227 * data structure memory
3b1d0580 5228 * @hba - per adapter instance
7a3e97b0 5229 */
3b1d0580 5230void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 5231{
cfdf9c91 5232 scsi_remove_host(hba->host);
7a3e97b0 5233 /* disable interrupts */
2fbd009b 5234 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 5235 ufshcd_hba_stop(hba);
7a3e97b0 5236
7a3e97b0 5237 scsi_host_put(hba->host);
5c0c28a8 5238
1ab27c9c 5239 ufshcd_exit_clk_gating(hba);
856b3483
ST		 5240 if (ufshcd_is_clkscaling_enabled(hba))
5241 devfreq_remove_device(hba->devfreq);
aa497613 5242 ufshcd_hba_exit(hba);
3b1d0580
VH		 5243}
5244EXPORT_SYMBOL_GPL(ufshcd_remove);
5245
ca3d7bf9
AM		 5246/**
5247 * ufshcd_set_dma_mask - Set dma mask based on the controller
5248 * addressing capability
5249 * @hba: per adapter instance
5250 *
5251 * Returns 0 for success, non-zero for failure
5252 */
5253static int ufshcd_set_dma_mask(struct ufs_hba *hba)
5254{
5255 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
5256 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
5257 return 0;
5258 }
5259 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
5260}
5261
7a3e97b0 5262/**
5c0c28a8 5263 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 5264 * @dev: pointer to device handle
5265 * @hba_handle: driver private handle
7a3e97b0
SY		 5266 * Returns 0 on success, non-zero value on failure
5267 */
5c0c28a8 5268int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 5269{
5270 struct Scsi_Host *host;
5271 struct ufs_hba *hba;
5c0c28a8 5272 int err = 0;
7a3e97b0 5273
3b1d0580
VH		 5274 if (!dev) {
5275 dev_err(dev,
5276 "Invalid memory reference for dev is NULL\n");
5277 err = -ENODEV;
7a3e97b0
SY		 5278 goto out_error;
5279 }
5280
7a3e97b0
SY		 5281 host = scsi_host_alloc(&ufshcd_driver_template,
5282 sizeof(struct ufs_hba));
5283 if (!host) {
3b1d0580 5284 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 5285 err = -ENOMEM;
3b1d0580 5286 goto out_error;
7a3e97b0
SY		 5287 }
5288 hba = shost_priv(host);
7a3e97b0 5289 hba->host = host;
3b1d0580 5290 hba->dev = dev;
5c0c28a8
SRT		 5291 *hba_handle = hba;
5292
5293out_error:
5294 return err;
5295}
5296EXPORT_SYMBOL(ufshcd_alloc_host);
5297
856b3483
ST		 5298static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
5299{
5300 int ret = 0;
5301 struct ufs_clk_info *clki;
5302 struct list_head *head = &hba->clk_list_head;
5303
5304 if (!head || list_empty(head))
5305 goto out;
5306
5307 list_for_each_entry(clki, head, list) {
5308 if (!IS_ERR_OR_NULL(clki->clk)) {
5309 if (scale_up && clki->max_freq) {
5310 if (clki->curr_freq == clki->max_freq)
5311 continue;
5312 ret = clk_set_rate(clki->clk, clki->max_freq);
5313 if (ret) {
5314 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5315 __func__, clki->name,
5316 clki->max_freq, ret);
5317 break;
5318 }
5319 clki->curr_freq = clki->max_freq;
5320
5321 } else if (!scale_up && clki->min_freq) {
5322 if (clki->curr_freq == clki->min_freq)
5323 continue;
5324 ret = clk_set_rate(clki->clk, clki->min_freq);
5325 if (ret) {
5326 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5327 __func__, clki->name,
5328 clki->min_freq, ret);
5329 break;
5330 }
5331 clki->curr_freq = clki->min_freq;
5332 }
5333 }
5334 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
5335 clki->name, clk_get_rate(clki->clk));
5336 }
5337 if (hba->vops->clk_scale_notify)
5338 hba->vops->clk_scale_notify(hba);
5339out:
5340 return ret;
5341}
5342
5343static int ufshcd_devfreq_target(struct device *dev,
5344 unsigned long *freq, u32 flags)
5345{
5346 int err = 0;
5347 struct ufs_hba *hba = dev_get_drvdata(dev);
5348
5349 if (!ufshcd_is_clkscaling_enabled(hba))
5350 return -EINVAL;
5351
5352 if (*freq == UINT_MAX)
5353 err = ufshcd_scale_clks(hba, true);
5354 else if (*freq == 0)
5355 err = ufshcd_scale_clks(hba, false);
5356
5357 return err;
5358}
5359
5360static int ufshcd_devfreq_get_dev_status(struct device *dev,
5361 struct devfreq_dev_status *stat)
5362{
5363 struct ufs_hba *hba = dev_get_drvdata(dev);
5364 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
5365 unsigned long flags;
5366
5367 if (!ufshcd_is_clkscaling_enabled(hba))
5368 return -EINVAL;
5369
5370 memset(stat, 0, sizeof(*stat));
5371
5372 spin_lock_irqsave(hba->host->host_lock, flags);
5373 if (!scaling->window_start_t)
5374 goto start_window;
5375
5376 if (scaling->is_busy_started)
5377 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
5378 scaling->busy_start_t));
5379
5380 stat->total_time = jiffies_to_usecs((long)jiffies -
5381 (long)scaling->window_start_t);
5382 stat->busy_time = scaling->tot_busy_t;
5383start_window:
5384 scaling->window_start_t = jiffies;
5385 scaling->tot_busy_t = 0;
5386
5387 if (hba->outstanding_reqs) {
5388 scaling->busy_start_t = ktime_get();
5389 scaling->is_busy_started = true;
5390 } else {
5391 scaling->busy_start_t = ktime_set(0, 0);
5392 scaling->is_busy_started = false;
5393 }
5394 spin_unlock_irqrestore(hba->host->host_lock, flags);
5395 return 0;
5396}
5397
5398static struct devfreq_dev_profile ufs_devfreq_profile = {
5399 .polling_ms = 100,
5400 .target = ufshcd_devfreq_target,
5401 .get_dev_status = ufshcd_devfreq_get_dev_status,
5402};
5403
5c0c28a8
SRT		 5404/**
5405 * ufshcd_init - Driver initialization routine
5406 * @hba: per-adapter instance
5407 * @mmio_base: base register address
5408 * @irq: Interrupt line of device
5409 * Returns 0 on success, non-zero value on failure
5410 */
5411int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
5412{
5413 int err;
5414 struct Scsi_Host *host = hba->host;
5415 struct device *dev = hba->dev;
5416
5417 if (!mmio_base) {
5418 dev_err(hba->dev,
5419 "Invalid memory reference for mmio_base is NULL\n");
5420 err = -ENODEV;
5421 goto out_error;
5422 }
5423
3b1d0580
VH		 5424 hba->mmio_base = mmio_base;
5425 hba->irq = irq;
7a3e97b0 5426
aa497613 5427 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 5428 if (err)
5429 goto out_error;
5430
7a3e97b0
SY		 5431 /* Read capabilities registers */
5432 ufshcd_hba_capabilities(hba);
5433
5434 /* Get UFS version supported by the controller */
5435 hba->ufs_version = ufshcd_get_ufs_version(hba);
5436
2fbd009b
SJ		 5437 /* Get Interrupt bit mask per version */
5438 hba->intr_mask = ufshcd_get_intr_mask(hba);
5439
ca3d7bf9
AM		 5440 err = ufshcd_set_dma_mask(hba);
5441 if (err) {
5442 dev_err(hba->dev, "set dma mask failed\n");
5443 goto out_disable;
5444 }
5445
7a3e97b0
SY		 5446 /* Allocate memory for host memory space */
5447 err = ufshcd_memory_alloc(hba);
5448 if (err) {
3b1d0580
VH		 5449 dev_err(hba->dev, "Memory allocation failed\n");
5450 goto out_disable;
7a3e97b0
SY		 5451 }
5452
5453 /* Configure LRB */
5454 ufshcd_host_memory_configure(hba);
5455
5456 host->can_queue = hba->nutrs;
5457 host->cmd_per_lun = hba->nutrs;
5458 host->max_id = UFSHCD_MAX_ID;
0ce147d4 5459 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 5460 host->max_channel = UFSHCD_MAX_CHANNEL;
5461 host->unique_id = host->host_no;
5462 host->max_cmd_len = MAX_CDB_SIZE;
5463
7eb584db
DR		 5464 hba->max_pwr_info.is_valid = false;
5465
7a3e97b0 5466 /* Initailize wait queue for task management */
e2933132
SRT		 5467 init_waitqueue_head(&hba->tm_wq);
5468 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 5469
5470 /* Initialize work queues */
e8e7f271 5471 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 5472 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 5473
6ccf44fe
SJ		 5474 /* Initialize UIC command mutex */
5475 mutex_init(&hba->uic_cmd_mutex);
5476
5a0b0cb9
SRT		 5477 /* Initialize mutex for device management commands */
5478 mutex_init(&hba->dev_cmd.lock);
5479
5480 /* Initialize device management tag acquire wait queue */
5481 init_waitqueue_head(&hba->dev_cmd.tag_wq);
5482
1ab27c9c 5483 ufshcd_init_clk_gating(hba);
7a3e97b0 5484 /* IRQ registration */
2953f850 5485 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 5486 if (err) {
3b1d0580 5487 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 5488 goto exit_gating;
57d104c1
SJ		 5489 } else {
5490 hba->is_irq_enabled = true;
7a3e97b0
SY		 5491 }
5492
5493 /* Enable SCSI tag mapping */
5494 err = scsi_init_shared_tag_map(host, host->can_queue);
5495 if (err) {
3b1d0580 5496 dev_err(hba->dev, "init shared queue failed\n");
1ab27c9c 5497 goto exit_gating;
7a3e97b0
SY		 5498 }
5499
3b1d0580 5500 err = scsi_add_host(host, hba->dev);
7a3e97b0 5501 if (err) {
3b1d0580 5502 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 5503 goto exit_gating;
7a3e97b0
SY		 5504 }
5505
6ccf44fe
SJ		 5506 /* Host controller enable */
5507 err = ufshcd_hba_enable(hba);
7a3e97b0 5508 if (err) {
6ccf44fe 5509 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 5510 goto out_remove_scsi_host;
7a3e97b0 5511 }
6ccf44fe 5512
856b3483
ST		 5513 if (ufshcd_is_clkscaling_enabled(hba)) {
5514 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
5515 "simple_ondemand", NULL);
5516 if (IS_ERR(hba->devfreq)) {
5517 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
5518 PTR_ERR(hba->devfreq));
5519 goto out_remove_scsi_host;
5520 }
5521 /* Suspend devfreq until the UFS device is detected */
5522 devfreq_suspend_device(hba->devfreq);
5523 hba->clk_scaling.window_start_t = 0;
5524 }
5525
62694735
SRT		 5526 /* Hold auto suspend until async scan completes */
5527 pm_runtime_get_sync(dev);
5528
57d104c1
SJ		 5529 /*
5530 * The device-initialize-sequence hasn't been invoked yet.
5531 * Set the device to power-off state
5532 */
5533 ufshcd_set_ufs_dev_poweroff(hba);
5534
6ccf44fe
SJ		 5535 async_schedule(ufshcd_async_scan, hba);
5536
7a3e97b0
SY		 5537 return 0;
5538
3b1d0580
VH		 5539out_remove_scsi_host:
5540 scsi_remove_host(hba->host);
1ab27c9c
ST		 5541exit_gating:
5542 ufshcd_exit_clk_gating(hba);
3b1d0580 5543out_disable:
57d104c1 5544 hba->is_irq_enabled = false;
3b1d0580 5545 scsi_host_put(host);
aa497613 5546 ufshcd_hba_exit(hba);
3b1d0580
VH		 5547out_error:
5548 return err;
5549}
5550EXPORT_SYMBOL_GPL(ufshcd_init);
5551
3b1d0580
VH		 5552MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
5553MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 5554MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 5555MODULE_LICENSE("GPL");
5556MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)