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scsi: ufs: qcom: Enable RPM_AUTOSUSPEND for runtime PM
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
67351119 1// SPDX-License-Identifier: GPL-2.0-or-later
7a3e97b0 2/*
e0eca63e 3 * Universal Flash Storage Host controller driver Core
3b1d0580 4 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 */
11
6ccf44fe 12#include <linux/async.h>
856b3483 13#include <linux/devfreq.h>
b573d484 14#include <linux/nls.h>
54b879b7 15#include <linux/of.h>
ad448378 16#include <linux/bitfield.h>
fb276f77 17#include <linux/blk-pm.h>
c72e79c0 18#include <linux/blkdev.h>
3f06f780
BVA		 19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
3f06f780
BVA		 23#include <linux/regulator/consumer.h>
24#include <scsi/scsi_cmnd.h>
25#include <scsi/scsi_dbg.h>
b294ff3e 26#include <scsi/scsi_driver.h>
3f06f780 27#include <scsi/scsi_eh.h>
4bc26113 28#include "ufshcd-priv.h"
c58ab7aa 29#include "ufs_quirks.h"
53b3d9c3 30#include "unipro.h"
cbb6813e 31#include "ufs-sysfs.h"
b6cacaf2 32#include "ufs-debugfs.h"
c11a1ae9 33#include "ufs-fault-injection.h"
df032bf2 34#include "ufs_bsg.h"
df043c74 35#include "ufshcd-crypto.h"
f02bc975 36#include "ufshpb.h"
3d17b9b5 37#include <asm/unaligned.h>
7a3e97b0 38
7ff5ab47 39#define CREATE_TRACE_POINTS
40#include <trace/events/ufs.h>
41
2fbd009b
SJ		 42#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
43 UTP_TASK_REQ_COMPL |\
44 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 45/* UIC command timeout, unit: ms */
46#define UIC_CMD_TIMEOUT 500
2fbd009b 47
5a0b0cb9
SRT		 48/* NOP OUT retries waiting for NOP IN response */
49#define NOP_OUT_RETRIES 10
782e2efb
DP		 50/* Timeout after 50 msecs if NOP OUT hangs without response */
51#define NOP_OUT_TIMEOUT 50 /* msecs */
5a0b0cb9 52
68078d5c 53/* Query request retries */
10fe5888 54#define QUERY_REQ_RETRIES 3
68078d5c 55/* Query request timeout */
10fe5888 56#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 57
e2933132
SRT		 58/* Task management command timeout */
59#define TM_CMD_TIMEOUT 100 /* msecs */
60
64238fbd
YG		 61/* maximum number of retries for a general UIC command */
62#define UFS_UIC_COMMAND_RETRIES 3
63
1d337ec2
SRT		 64/* maximum number of link-startup retries */
65#define DME_LINKSTARTUP_RETRIES 3
66
87d0b4a6
YG		 67/* Maximum retries for Hibern8 enter */
68#define UIC_HIBERN8_ENTER_RETRIES 3
69
1d337ec2
SRT		 70/* maximum number of reset retries before giving up */
71#define MAX_HOST_RESET_RETRIES 5
72
87bf6a6b
AH		 73/* Maximum number of error handler retries before giving up */
74#define MAX_ERR_HANDLER_RETRIES 5
75
68078d5c
DR		 76/* Expose the flag value from utp_upiu_query.value */
77#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
78
7d568652
SJ		 79/* Interrupt aggregation default timeout, unit: 40us */
80#define INT_AGGR_DEF_TO 0x02
81
49615ba1
SC		 82/* default delay of autosuspend: 2000 ms */
83#define RPM_AUTOSUSPEND_DELAY_MS 2000
84
51dd905b
SC		 85/* Default delay of RPM device flush delayed work */
86#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
87
09f17791
CG		 88/* Default value of wait time before gating device ref clock */
89#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
90
29707fab
KK		 91/* Polling time to wait for fDeviceInit */
92#define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
93
aa497613
SRT		 94#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
95 ({ \
96 int _ret; \
97 if (_on) \
98 _ret = ufshcd_enable_vreg(_dev, _vreg); \
99 else \
100 _ret = ufshcd_disable_vreg(_dev, _vreg); \
101 _ret; \
102 })
103
ba80917d
TW		 104#define ufshcd_hex_dump(prefix_str, buf, len) do { \
105 size_t __len = (len); \
106 print_hex_dump(KERN_ERR, prefix_str, \
107 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
108 16, 4, buf, __len, false); \
109} while (0)
110
111int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
112 const char *prefix)
113{
d6724756
MG		 114 u32 *regs;
115 size_t pos;
116
117 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
118 return -EINVAL;
ba80917d 119
cddaebaf 120 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 121 if (!regs)
122 return -ENOMEM;
123
ef600310
KK		 124 for (pos = 0; pos < len; pos += 4) {
125 if (offset == 0 &&
126 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
127 pos <= REG_UIC_ERROR_CODE_DME)
128 continue;
d6724756 129 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
ef600310 130 }
d6724756 131
ba80917d
TW		 132 ufshcd_hex_dump(prefix, regs, len);
133 kfree(regs);
134
135 return 0;
136}
137EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 138
7a3e97b0
SY		 139enum {
140 UFSHCD_MAX_CHANNEL = 0,
141 UFSHCD_MAX_ID = 1,
945c3cca
BVA		 142 UFSHCD_NUM_RESERVED = 1,
143 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
144 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
7a3e97b0
SY		 145};
146
4693fad7
BVA		 147static const char *const ufshcd_state_name[] = {
148 [UFSHCD_STATE_RESET] = "reset",
149 [UFSHCD_STATE_OPERATIONAL] = "operational",
150 [UFSHCD_STATE_ERROR] = "error",
151 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
152 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
153};
154
3441da7d
SRT		 155/* UFSHCD error handling flags */
156enum {
157 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 158};
159
e8e7f271
SRT		 160/* UFSHCD UIC layer error flags */
161enum {
162 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 163 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
164 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
165 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
166 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
167 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
2355b66e 168 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
e8e7f271
SRT		 169};
170
3441da7d 171#define ufshcd_set_eh_in_progress(h) \
9c490d2d 172 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 173#define ufshcd_eh_in_progress(h) \
9c490d2d 174 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 175#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 176 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 177
cbb6813e 178struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
e2ac7ab2
BVA		 179 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
180 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
181 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
182 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
183 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
184 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
fe1d4c2e
AH		 185 /*
186 * For DeepSleep, the link is first put in hibern8 and then off.
187 * Leaving the link in hibern8 is not supported.
188 */
e2ac7ab2 189 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
57d104c1
SJ		 190};
191
192static inline enum ufs_dev_pwr_mode
193ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
194{
195 return ufs_pm_lvl_states[lvl].dev_state;
196}
197
198static inline enum uic_link_state
199ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
200{
201 return ufs_pm_lvl_states[lvl].link_state;
202}
203
0c8f7586 204static inline enum ufs_pm_level
205ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
206 enum uic_link_state link_state)
207{
208 enum ufs_pm_level lvl;
209
210 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
211 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
212 (ufs_pm_lvl_states[lvl].link_state == link_state))
213 return lvl;
214 }
215
216 /* if no match found, return the level 0 */
217 return UFS_PM_LVL_0;
218}
219
aead21f3 220static const struct ufs_dev_quirk ufs_fixups[] = {
56d4a186 221 /* UFS cards deviations table */
dd2cf44f
BVA		 222 { .wmanufacturerid = UFS_VENDOR_MICRON,
223 .model = UFS_ANY_MODEL,
224 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
225 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ },
226 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
227 .model = UFS_ANY_MODEL,
228 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
229 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
230 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
231 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
232 .model = UFS_ANY_MODEL,
233 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
234 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
235 .model = "hB8aL1" /*H28U62301AMR*/,
236 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
237 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
238 .model = UFS_ANY_MODEL,
239 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
240 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
241 .model = "THGLF2G9C8KBADG",
242 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
243 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
244 .model = "THGLF2G9D8KBADG",
245 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
246 {}
56d4a186
SJ		 247};
248
9333d775 249static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 250static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 251static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 252static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 253static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 254static void ufshcd_hba_exit(struct ufs_hba *hba);
68444d73 255static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
1ab27c9c 256static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
cad2e03d 257static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 258static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 259static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
260static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 261static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 262static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 263static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 264static int ufshcd_change_power_mode(struct ufs_hba *hba,
265 struct ufs_pa_layer_attr *pwr_mode);
c72e79c0
CG		 266static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
267static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
268static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
269 struct ufs_vreg *vreg);
307348f6 270static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
3b5f3c0d
YH		 271static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
272static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
dd7143e2
CG		 273static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
274static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
3d17b9b5 275
5231d38c 276static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 277{
57d104c1 278 if (!hba->is_irq_enabled) {
5231d38c 279 enable_irq(hba->irq);
57d104c1
SJ		 280 hba->is_irq_enabled = true;
281 }
57d104c1
SJ		 282}
283
284static inline void ufshcd_disable_irq(struct ufs_hba *hba)
285{
286 if (hba->is_irq_enabled) {
5231d38c 287 disable_irq(hba->irq);
57d104c1
SJ		 288 hba->is_irq_enabled = false;
289 }
290}
3441da7d 291
3d17b9b5
AD		 292static inline void ufshcd_wb_config(struct ufs_hba *hba)
293{
79e3520f 294 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 295 return;
296
3b5f3c0d
YH		 297 ufshcd_wb_toggle(hba, true);
298
299 ufshcd_wb_toggle_flush_during_h8(hba, true);
21acf460
SC		 300 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
301 ufshcd_wb_toggle_flush(hba, true);
3d17b9b5
AD		 302}
303
38135535
SJ		 304static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
305{
306 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
307 scsi_unblock_requests(hba->host);
308}
309
310static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
311{
312 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
313 scsi_block_requests(hba->host);
314}
315
6667e6d9 316static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 317 enum ufs_trace_str_t str_t)
6667e6d9
OS		 318{
319 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
89ac2c3b 320 struct utp_upiu_header *header;
6667e6d9 321
9d5095e7
BH		 322 if (!trace_ufshcd_upiu_enabled())
323 return;
324
89ac2c3b
BH		 325 if (str_t == UFS_CMD_SEND)
326 header = &rq->header;
327 else
328 header = &hba->lrb[tag].ucd_rsp_ptr->header;
329
330 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
867fdc2d 331 UFS_TSF_CDB);
6667e6d9
OS		 332}
333
fb475b74
AA		 334static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
335 enum ufs_trace_str_t str_t,
336 struct utp_upiu_req *rq_rsp)
6667e6d9 337{
9d5095e7
BH		 338 if (!trace_ufshcd_upiu_enabled())
339 return;
6667e6d9 340
be20b51c 341 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
867fdc2d 342 &rq_rsp->qr, UFS_TSF_OSF);
6667e6d9
OS		 343}
344
345static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 346 enum ufs_trace_str_t str_t)
6667e6d9 347{
e8c2da7e 348 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
6667e6d9 349
9d5095e7
BH		 350 if (!trace_ufshcd_upiu_enabled())
351 return;
352
0ed083e9 353 if (str_t == UFS_TM_SEND)
1352eec8
GS		 354 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
355 &descp->upiu_req.req_header,
356 &descp->upiu_req.input_param1,
357 UFS_TSF_TM_INPUT);
0ed083e9 358 else
1352eec8
GS		 359 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
360 &descp->upiu_rsp.rsp_header,
361 &descp->upiu_rsp.output_param1,
362 UFS_TSF_TM_OUTPUT);
6667e6d9
OS		 363}
364
aa5c6979
SC		 365static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
366 struct uic_command *ucmd,
28fa68fc 367 enum ufs_trace_str_t str_t)
aa5c6979
SC		 368{
369 u32 cmd;
370
371 if (!trace_ufshcd_uic_command_enabled())
372 return;
373
28fa68fc 374 if (str_t == UFS_CMD_SEND)
aa5c6979
SC		 375 cmd = ucmd->command;
376 else
377 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
378
28fa68fc 379 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
aa5c6979
SC		 380 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
381 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
382 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
383}
384
28fa68fc
BH		 385static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
386 enum ufs_trace_str_t str_t)
1a07f2d9 387{
2bd3b6b7 388 u64 lba = 0;
69a314d6 389 u8 opcode = 0, group_id = 0;
1a07f2d9 390 u32 intr, doorbell;
e7c3b379 391 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 392 struct scsi_cmnd *cmd = lrbp->cmd;
3f2c1002 393 struct request *rq = scsi_cmd_to_rq(cmd);
1a07f2d9
LS		 394 int transfer_len = -1;
395
44b5de36
BH		 396 if (!cmd)
397 return;
398
44b5de36
BH		 399 /* trace UPIU also */
400 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
f0101af4
BH		 401 if (!trace_ufshcd_command_enabled())
402 return;
403
44b5de36 404 opcode = cmd->cmnd[0];
44b5de36
BH		 405
406 if (opcode == READ_10 || opcode == WRITE_10) {
407 /*
408 * Currently we only fully trace read(10) and write(10) commands
409 */
410 transfer_len =
411 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
2bd3b6b7 412 lba = scsi_get_lba(cmd);
44b5de36
BH		 413 if (opcode == WRITE_10)
414 group_id = lrbp->cmd->cmnd[6];
415 } else if (opcode == UNMAP) {
416 /*
417 * The number of Bytes to be unmapped beginning with the lba.
418 */
3f2c1002 419 transfer_len = blk_rq_bytes(rq);
2bd3b6b7 420 lba = scsi_get_lba(cmd);
1a07f2d9
LS		 421 }
422
423 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
424 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
28fa68fc 425 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
69a314d6 426 doorbell, transfer_len, intr, lba, opcode, group_id);
1a07f2d9
LS		 427}
428
ff8e20c6
DR		 429static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
430{
431 struct ufs_clk_info *clki;
432 struct list_head *head = &hba->clk_list_head;
433
566ec9ad 434 if (list_empty(head))
ff8e20c6
DR		 435 return;
436
437 list_for_each_entry(clki, head, list) {
438 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
439 clki->max_freq)
440 dev_err(hba->dev, "clk: %s, rate: %u\n",
441 clki->name, clki->curr_freq);
442 }
443}
444
e965e5e0
SC		 445static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
446 char *err_name)
ff8e20c6
DR		 447{
448 int i;
27752647 449 bool found = false;
e965e5e0 450 struct ufs_event_hist *e;
ff8e20c6 451
e965e5e0
SC		 452 if (id >= UFS_EVT_CNT)
453 return;
ff8e20c6 454
e965e5e0 455 e = &hba->ufs_stats.event[id];
ff8e20c6 456
e965e5e0
SC		 457 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
458 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
459
460 if (e->tstamp[p] == 0)
ff8e20c6 461 continue;
c5397f13 462 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
e965e5e0 463 e->val[p], ktime_to_us(e->tstamp[p]));
27752647 464 found = true;
ff8e20c6 465 }
27752647
SC		 466
467 if (!found)
fd1fb4d5 468 dev_err(hba->dev, "No record of %s\n", err_name);
bafd09f8
DH		 469 else
470 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
ff8e20c6
DR		 471}
472
e965e5e0 473static void ufshcd_print_evt_hist(struct ufs_hba *hba)
66cc820f 474{
ba80917d 475 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
ff8e20c6 476
e965e5e0
SC		 477 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
478 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
479 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
480 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
481 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
482 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
483 "auto_hibern8_err");
484 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
485 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
486 "link_startup_fail");
487 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
488 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
489 "suspend_fail");
490 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
491 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
492 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
ff8e20c6 493
7c486d91 494 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 495}
496
497static
498void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
499{
500 struct ufshcd_lrb *lrbp;
7fabb77b 501 int prdt_length;
66cc820f
DR		 502 int tag;
503
504 for_each_set_bit(tag, &bitmap, hba->nutrs) {
505 lrbp = &hba->lrb[tag];
506
ff8e20c6
DR		 507 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
508 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 509 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
510 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 511 dev_err(hba->dev,
512 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
513 tag, (u64)lrbp->utrd_dma_addr);
514
66cc820f
DR		 515 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
516 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 517 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
518 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 519 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
520 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 521 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
522 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 523 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
524 sizeof(struct utp_upiu_rsp));
66cc820f 525
7fabb77b
GB		 526 prdt_length = le16_to_cpu(
527 lrbp->utr_descriptor_ptr->prd_table_length);
cc770ce3
EB		 528 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
529 prdt_length /= sizeof(struct ufshcd_sg_entry);
530
7fabb77b
GB		 531 dev_err(hba->dev,
532 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
533 tag, prdt_length,
534 (u64)lrbp->ucd_prdt_dma_addr);
535
536 if (pr_prdt)
66cc820f 537 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 538 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 539 }
540}
541
542static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
543{
66cc820f
DR		 544 int tag;
545
546 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 547 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
548
66cc820f 549 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 550 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 551 }
552}
553
6ba65588
GB		 554static void ufshcd_print_host_state(struct ufs_hba *hba)
555{
e2106584 556 struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
3f8af604 557
6ba65588 558 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 559 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
560 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 561 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
562 hba->saved_err, hba->saved_uic_err);
563 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
564 hba->curr_dev_pwr_mode, hba->uic_link_state);
565 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
566 hba->pm_op_in_progress, hba->is_sys_suspended);
567 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
568 hba->auto_bkops_enabled, hba->host->host_self_blocked);
569 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
3f8af604
CG		 570 dev_err(hba->dev,
571 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
572 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
573 hba->ufs_stats.hibern8_exit_cnt);
574 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
575 ktime_to_us(hba->ufs_stats.last_intr_ts),
576 hba->ufs_stats.last_intr_status);
6ba65588
GB		 577 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
578 hba->eh_flags, hba->req_abort_count);
3f8af604
CG		 579 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
580 hba->ufs_version, hba->capabilities, hba->caps);
6ba65588
GB		 581 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
582 hba->dev_quirks);
3f8af604
CG		 583 if (sdev_ufs)
584 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
585 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
586
587 ufshcd_print_clk_freqs(hba);
6ba65588
GB		 588}
589
ff8e20c6
DR		 590/**
591 * ufshcd_print_pwr_info - print power params as saved in hba
592 * power info
593 * @hba: per-adapter instance
594 */
595static void ufshcd_print_pwr_info(struct ufs_hba *hba)
596{
597 static const char * const names[] = {
598 "INVALID MODE",
599 "FAST MODE",
600 "SLOW_MODE",
601 "INVALID MODE",
602 "FASTAUTO_MODE",
603 "SLOWAUTO_MODE",
604 "INVALID MODE",
605 };
606
71bb9ab6
AH		 607 /*
608 * Using dev_dbg to avoid messages during runtime PM to avoid
609 * never-ending cycles of messages written back to storage by user space
610 * causing runtime resume, causing more messages and so on.
611 */
612 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
ff8e20c6
DR		 613 __func__,
614 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
615 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
616 names[hba->pwr_info.pwr_rx],
617 names[hba->pwr_info.pwr_tx],
618 hba->pwr_info.hs_rate);
619}
620
31a5d9ca
SC		 621static void ufshcd_device_reset(struct ufs_hba *hba)
622{
623 int err;
624
625 err = ufshcd_vops_device_reset(hba);
626
627 if (!err) {
628 ufshcd_set_ufs_dev_active(hba);
629 if (ufshcd_is_wb_allowed(hba)) {
4cd48995
BH		 630 hba->dev_info.wb_enabled = false;
631 hba->dev_info.wb_buf_flush_enabled = false;
31a5d9ca
SC		 632 }
633 }
634 if (err != -EOPNOTSUPP)
635 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
636}
637
5c955c10
SC		 638void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
639{
640 if (!us)
641 return;
642
643 if (us < 10)
644 udelay(us);
645 else
646 usleep_range(us, us + tolerance);
647}
648EXPORT_SYMBOL_GPL(ufshcd_delay_us);
649
5cac1095 650/**
5a0b0cb9 651 * ufshcd_wait_for_register - wait for register value to change
5cac1095
BVA		 652 * @hba: per-adapter interface
653 * @reg: mmio register offset
654 * @mask: mask to apply to the read register value
655 * @val: value to wait for
656 * @interval_us: polling interval in microseconds
657 * @timeout_ms: timeout in milliseconds
5a0b0cb9 658 *
5cac1095
BVA		 659 * Return:
660 * -ETIMEDOUT on error, zero on success.
5a0b0cb9 661 */
59a57bb7 662static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
596585a2 663 u32 val, unsigned long interval_us,
5cac1095 664 unsigned long timeout_ms)
5a0b0cb9
SRT		 665{
666 int err = 0;
667 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
668
669 /* ignore bits that we don't intend to wait on */
670 val = val & mask;
671
672 while ((ufshcd_readl(hba, reg) & mask) != val) {
5cac1095 673 usleep_range(interval_us, interval_us + 50);
5a0b0cb9
SRT		 674 if (time_after(jiffies, timeout)) {
675 if ((ufshcd_readl(hba, reg) & mask) != val)
676 err = -ETIMEDOUT;
677 break;
678 }
679 }
680
681 return err;
682}
683
2fbd009b
SJ		 684/**
685 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 686 * @hba: Pointer to adapter instance
2fbd009b
SJ		 687 *
688 * Returns interrupt bit mask per version
689 */
690static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
691{
51428818
CC		 692 if (hba->ufs_version == ufshci_version(1, 0))
693 return INTERRUPT_MASK_ALL_VER_10;
694 if (hba->ufs_version <= ufshci_version(2, 0))
695 return INTERRUPT_MASK_ALL_VER_11;
c01848c6 696
51428818 697 return INTERRUPT_MASK_ALL_VER_21;
2fbd009b
SJ		 698}
699
7a3e97b0
SY		 700/**
701 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 702 * @hba: Pointer to adapter instance
7a3e97b0
SY		 703 *
704 * Returns UFSHCI version supported by the controller
705 */
706static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
707{
51428818
CC		 708 u32 ufshci_ver;
709
0263bcd0 710 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
51428818
CC		 711 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
712 else
713 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
9949e702 714
51428818
CC		 715 /*
716 * UFSHCI v1.x uses a different version scheme, in order
717 * to allow the use of comparisons with the ufshci_version
718 * function, we convert it to the same scheme as ufs 2.0+.
719 */
720 if (ufshci_ver & 0x00010000)
721 return ufshci_version(1, ufshci_ver & 0x00000100);
722
723 return ufshci_ver;
7a3e97b0
SY		 724}
725
726/**
727 * ufshcd_is_device_present - Check if any device connected to
728 * the host controller
5c0c28a8 729 * @hba: pointer to adapter instance
7a3e97b0 730 *
c9e6010b 731 * Returns true if device present, false if no device detected
7a3e97b0 732 */
c9e6010b 733static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 734{
51d1628f 735 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
7a3e97b0
SY		 736}
737
738/**
739 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 740 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 741 *
742 * This function is used to get the OCS field from UTRD
743 * Returns the OCS field in the UTRD
744 */
957d63e7 745static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
7a3e97b0 746{
e8c8e82a 747 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 748}
749
7a3e97b0
SY		 750/**
751 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
752 * @hba: per adapter instance
753 * @pos: position of the bit to be cleared
754 */
755static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
756{
87183841
AA		 757 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
758 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
759 else
760 ufshcd_writel(hba, ~(1 << pos),
761 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 762}
763
764/**
765 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
766 * @hba: per adapter instance
767 * @pos: position of the bit to be cleared
768 */
769static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
770{
87183841
AA		 771 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
772 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
773 else
774 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 775}
776
777/**
778 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
779 * @reg: Register value of host controller status
780 *
781 * Returns integer, 0 on Success and positive value if failed
782 */
783static inline int ufshcd_get_lists_status(u32 reg)
784{
6cf16115 785 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 786}
787
788/**
789 * ufshcd_get_uic_cmd_result - Get the UIC command result
790 * @hba: Pointer to adapter instance
791 *
792 * This function gets the result of UIC command completion
793 * Returns 0 on success, non zero value on error
794 */
795static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
796{
b873a275 797 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 798 MASK_UIC_COMMAND_RESULT;
799}
800
12b4fdb4
SJ		 801/**
802 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
803 * @hba: Pointer to adapter instance
804 *
805 * This function gets UIC command argument3
806 * Returns 0 on success, non zero value on error
807 */
808static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
809{
810 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
811}
812
7a3e97b0 813/**
5a0b0cb9 814 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 815 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 816 */
817static inline int
5a0b0cb9 818ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 819{
5a0b0cb9 820 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 821}
822
823/**
824 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
825 * @ucd_rsp_ptr: pointer to response UPIU
826 *
827 * This function gets the response status and scsi_status from response UPIU
828 * Returns the response result code.
829 */
830static inline int
831ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
832{
833 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
834}
835
1c2623c5
SJ		 836/*
837 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
838 * from response UPIU
839 * @ucd_rsp_ptr: pointer to response UPIU
840 *
841 * Return the data segment length.
842 */
843static inline unsigned int
844ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
845{
846 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
847 MASK_RSP_UPIU_DATA_SEG_LEN;
848}
849
66ec6d59
SRT		 850/**
851 * ufshcd_is_exception_event - Check if the device raised an exception event
852 * @ucd_rsp_ptr: pointer to response UPIU
853 *
854 * The function checks if the device raised an exception event indicated in
855 * the Device Information field of response UPIU.
856 *
857 * Returns true if exception is raised, false otherwise.
858 */
859static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
860{
861 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
51d1628f 862 MASK_RSP_EXCEPTION_EVENT;
66ec6d59
SRT		 863}
864
7a3e97b0 865/**
7d568652 866 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 867 * @hba: per adapter instance
7a3e97b0
SY		 868 */
869static inline void
7d568652 870ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 871{
7d568652
SJ		 872 ufshcd_writel(hba, INT_AGGR_ENABLE |
873 INT_AGGR_COUNTER_AND_TIMER_RESET,
874 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
875}
876
877/**
878 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
879 * @hba: per adapter instance
880 * @cnt: Interrupt aggregation counter threshold
881 * @tmout: Interrupt aggregation timeout value
882 */
883static inline void
884ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
885{
886 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
887 INT_AGGR_COUNTER_THLD_VAL(cnt) |
888 INT_AGGR_TIMEOUT_VAL(tmout),
889 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 890}
891
b852190e
YG		 892/**
893 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
894 * @hba: per adapter instance
895 */
896static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
897{
898 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
899}
900
7a3e97b0
SY		 901/**
902 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
903 * When run-stop registers are set to 1, it indicates the
904 * host controller that it can process the requests
905 * @hba: per adapter instance
906 */
907static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
908{
b873a275
SJ		 909 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
910 REG_UTP_TASK_REQ_LIST_RUN_STOP);
911 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
912 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 913}
914
7a3e97b0
SY		 915/**
916 * ufshcd_hba_start - Start controller initialization sequence
917 * @hba: per adapter instance
918 */
919static inline void ufshcd_hba_start(struct ufs_hba *hba)
920{
df043c74
ST		 921 u32 val = CONTROLLER_ENABLE;
922
923 if (ufshcd_crypto_enable(hba))
924 val |= CRYPTO_GENERAL_ENABLE;
925
926 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 927}
928
929/**
930 * ufshcd_is_hba_active - Get controller state
931 * @hba: per adapter instance
932 *
acbbfe48 933 * Returns true if and only if the controller is active.
7a3e97b0 934 */
c9e6010b 935static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 936{
acbbfe48 937 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
7a3e97b0
SY		 938}
939
37113106
YG		 940u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
941{
942 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
51428818 943 if (hba->ufs_version <= ufshci_version(1, 1))
37113106
YG		 944 return UFS_UNIPRO_VER_1_41;
945 else
946 return UFS_UNIPRO_VER_1_6;
947}
948EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
949
950static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
951{
952 /*
953 * If both host and device support UniPro ver1.6 or later, PA layer
954 * parameters tuning happens during link startup itself.
955 *
956 * We can manually tune PA layer parameters if either host or device
957 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
958 * logic simple, we will only do manual tuning if local unipro version
959 * doesn't support ver1.6 or later.
960 */
a858af9a 961 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
37113106
YG		 962}
963
394b949f
SJ		 964/**
965 * ufshcd_set_clk_freq - set UFS controller clock frequencies
966 * @hba: per adapter instance
967 * @scale_up: If True, set max possible frequency othewise set low frequency
968 *
969 * Returns 0 if successful
970 * Returns < 0 for any other errors
971 */
972static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 973{
974 int ret = 0;
975 struct ufs_clk_info *clki;
976 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 977
566ec9ad 978 if (list_empty(head))
a3cd5ec5 979 goto out;
980
a3cd5ec5 981 list_for_each_entry(clki, head, list) {
982 if (!IS_ERR_OR_NULL(clki->clk)) {
983 if (scale_up && clki->max_freq) {
984 if (clki->curr_freq == clki->max_freq)
985 continue;
986
a3cd5ec5 987 ret = clk_set_rate(clki->clk, clki->max_freq);
988 if (ret) {
989 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
990 __func__, clki->name,
991 clki->max_freq, ret);
992 break;
993 }
994 trace_ufshcd_clk_scaling(dev_name(hba->dev),
995 "scaled up", clki->name,
996 clki->curr_freq,
997 clki->max_freq);
998
999 clki->curr_freq = clki->max_freq;
1000
1001 } else if (!scale_up && clki->min_freq) {
1002 if (clki->curr_freq == clki->min_freq)
1003 continue;
1004
a3cd5ec5 1005 ret = clk_set_rate(clki->clk, clki->min_freq);
1006 if (ret) {
1007 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1008 __func__, clki->name,
1009 clki->min_freq, ret);
1010 break;
1011 }
1012 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1013 "scaled down", clki->name,
1014 clki->curr_freq,
1015 clki->min_freq);
1016 clki->curr_freq = clki->min_freq;
1017 }
1018 }
1019 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1020 clki->name, clk_get_rate(clki->clk));
1021 }
1022
394b949f
SJ		 1023out:
1024 return ret;
1025}
1026
1027/**
1028 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1029 * @hba: per adapter instance
1030 * @scale_up: True if scaling up and false if scaling down
1031 *
1032 * Returns 0 if successful
1033 * Returns < 0 for any other errors
1034 */
1035static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1036{
1037 int ret = 0;
1038 ktime_t start = ktime_get();
1039
1040 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1041 if (ret)
1042 goto out;
1043
1044 ret = ufshcd_set_clk_freq(hba, scale_up);
1045 if (ret)
1046 goto out;
1047
a3cd5ec5 1048 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 1049 if (ret)
1050 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 1051
1052out:
394b949f 1053 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 1054 (scale_up ? "up" : "down"),
1055 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1056 return ret;
1057}
1058
1059/**
1060 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1061 * @hba: per adapter instance
1062 * @scale_up: True if scaling up and false if scaling down
1063 *
1064 * Returns true if scaling is required, false otherwise.
1065 */
1066static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1067 bool scale_up)
1068{
1069 struct ufs_clk_info *clki;
1070 struct list_head *head = &hba->clk_list_head;
1071
566ec9ad 1072 if (list_empty(head))
a3cd5ec5 1073 return false;
1074
1075 list_for_each_entry(clki, head, list) {
1076 if (!IS_ERR_OR_NULL(clki->clk)) {
1077 if (scale_up && clki->max_freq) {
1078 if (clki->curr_freq == clki->max_freq)
1079 continue;
1080 return true;
1081 } else if (!scale_up && clki->min_freq) {
1082 if (clki->curr_freq == clki->min_freq)
1083 continue;
1084 return true;
1085 }
1086 }
1087 }
1088
1089 return false;
1090}
1091
8d077ede
BVA		 1092/*
1093 * Determine the number of pending commands by counting the bits in the SCSI
1094 * device budget maps. This approach has been selected because a bit is set in
1095 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1096 * flag. The host_self_blocked flag can be modified by calling
1097 * scsi_block_requests() or scsi_unblock_requests().
1098 */
1099static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1100{
1101 struct scsi_device *sdev;
1102 u32 pending = 0;
1103
99c66a88
BH		 1104 lockdep_assert_held(hba->host->host_lock);
1105 __shost_for_each_device(sdev, hba->host)
8d077ede
BVA		 1106 pending += sbitmap_weight(&sdev->budget_map);
1107
1108 return pending;
1109}
1110
a3cd5ec5 1111static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1112 u64 wait_timeout_us)
1113{
1114 unsigned long flags;
1115 int ret = 0;
1116 u32 tm_doorbell;
8d077ede 1117 u32 tr_pending;
a3cd5ec5 1118 bool timeout = false, do_last_check = false;
1119 ktime_t start;
1120
1121 ufshcd_hold(hba, false);
1122 spin_lock_irqsave(hba->host->host_lock, flags);
1123 /*
1124 * Wait for all the outstanding tasks/transfer requests.
1125 * Verify by checking the doorbell registers are clear.
1126 */
1127 start = ktime_get();
1128 do {
1129 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1130 ret = -EBUSY;
1131 goto out;
1132 }
1133
1134 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
8d077ede
BVA		 1135 tr_pending = ufshcd_pending_cmds(hba);
1136 if (!tm_doorbell && !tr_pending) {
a3cd5ec5 1137 timeout = false;
1138 break;
1139 } else if (do_last_check) {
1140 break;
1141 }
1142
1143 spin_unlock_irqrestore(hba->host->host_lock, flags);
1144 schedule();
1145 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1146 wait_timeout_us) {
1147 timeout = true;
1148 /*
1149 * We might have scheduled out for long time so make
1150 * sure to check if doorbells are cleared by this time
1151 * or not.
1152 */
1153 do_last_check = true;
1154 }
1155 spin_lock_irqsave(hba->host->host_lock, flags);
8d077ede 1156 } while (tm_doorbell || tr_pending);
a3cd5ec5 1157
1158 if (timeout) {
1159 dev_err(hba->dev,
1160 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
8d077ede 1161 __func__, tm_doorbell, tr_pending);
a3cd5ec5 1162 ret = -EBUSY;
1163 }
1164out:
1165 spin_unlock_irqrestore(hba->host->host_lock, flags);
1166 ufshcd_release(hba);
1167 return ret;
1168}
1169
1170/**
1171 * ufshcd_scale_gear - scale up/down UFS gear
1172 * @hba: per adapter instance
1173 * @scale_up: True for scaling up gear and false for scaling down
1174 *
1175 * Returns 0 for success,
1176 * Returns -EBUSY if scaling can't happen at this time
1177 * Returns non-zero for any other errors
1178 */
1179static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1180{
a3cd5ec5 1181 int ret = 0;
1182 struct ufs_pa_layer_attr new_pwr_info;
1183
1184 if (scale_up) {
1185 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1186 sizeof(struct ufs_pa_layer_attr));
1187 } else {
1188 memcpy(&new_pwr_info, &hba->pwr_info,
1189 sizeof(struct ufs_pa_layer_attr));
1190
29b87e92
CG		 1191 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1192 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
a3cd5ec5 1193 /* save the current power mode */
1194 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1195 &hba->pwr_info,
1196 sizeof(struct ufs_pa_layer_attr));
1197
1198 /* scale down gear */
29b87e92
CG		 1199 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1200 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
a3cd5ec5 1201 }
1202 }
1203
1204 /* check if the power mode needs to be changed or not? */
6a9df818 1205 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1206 if (ret)
1207 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1208 __func__, ret,
1209 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1210 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1211
1212 return ret;
1213}
1214
1215static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1216{
1217 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1218 int ret = 0;
1219 /*
1220 * make sure that there are no outstanding requests when
1221 * clock scaling is in progress
1222 */
38135535 1223 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1224 down_write(&hba->clk_scaling_lock);
0e9d4ca4
CG		 1225
1226 if (!hba->clk_scaling.is_allowed ||
1227 ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
a3cd5ec5 1228 ret = -EBUSY;
1229 up_write(&hba->clk_scaling_lock);
38135535 1230 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1231 goto out;
a3cd5ec5 1232 }
1233
0e9d4ca4
CG		 1234 /* let's not get into low power until clock scaling is completed */
1235 ufshcd_hold(hba, false);
1236
1237out:
a3cd5ec5 1238 return ret;
1239}
1240
0e9d4ca4 1241static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
a3cd5ec5 1242{
0e9d4ca4
CG		 1243 if (writelock)
1244 up_write(&hba->clk_scaling_lock);
1245 else
1246 up_read(&hba->clk_scaling_lock);
38135535 1247 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1248 ufshcd_release(hba);
a3cd5ec5 1249}
1250
1251/**
1252 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1253 * @hba: per adapter instance
1254 * @scale_up: True for scaling up and false for scalin down
1255 *
1256 * Returns 0 for success,
1257 * Returns -EBUSY if scaling can't happen at this time
1258 * Returns non-zero for any other errors
1259 */
1260static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1261{
1262 int ret = 0;
0e9d4ca4 1263 bool is_writelock = true;
401f1e44 1264
a3cd5ec5 1265 ret = ufshcd_clock_scaling_prepare(hba);
1266 if (ret)
0e9d4ca4 1267 return ret;
a3cd5ec5 1268
1269 /* scale down the gear before scaling down clocks */
1270 if (!scale_up) {
1271 ret = ufshcd_scale_gear(hba, false);
1272 if (ret)
394b949f 1273 goto out_unprepare;
a3cd5ec5 1274 }
1275
1276 ret = ufshcd_scale_clks(hba, scale_up);
1277 if (ret) {
1278 if (!scale_up)
1279 ufshcd_scale_gear(hba, true);
394b949f 1280 goto out_unprepare;
a3cd5ec5 1281 }
1282
1283 /* scale up the gear after scaling up clocks */
1284 if (scale_up) {
1285 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1286 if (ret) {
a3cd5ec5 1287 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1288 goto out_unprepare;
1289 }
a3cd5ec5 1290 }
1291
3d17b9b5 1292 /* Enable Write Booster if we have scaled up else disable it */
0e9d4ca4
CG		 1293 downgrade_write(&hba->clk_scaling_lock);
1294 is_writelock = false;
3b5f3c0d 1295 ufshcd_wb_toggle(hba, scale_up);
3d17b9b5 1296
394b949f 1297out_unprepare:
0e9d4ca4 1298 ufshcd_clock_scaling_unprepare(hba, is_writelock);
a3cd5ec5 1299 return ret;
1300}
1301
401f1e44 1302static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1303{
1304 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1305 clk_scaling.suspend_work);
1306 unsigned long irq_flags;
1307
1308 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1309 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1310 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1311 return;
1312 }
1313 hba->clk_scaling.is_suspended = true;
1314 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1315
1316 __ufshcd_suspend_clkscaling(hba);
1317}
1318
1319static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1320{
1321 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1322 clk_scaling.resume_work);
1323 unsigned long irq_flags;
1324
1325 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1326 if (!hba->clk_scaling.is_suspended) {
1327 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1328 return;
1329 }
1330 hba->clk_scaling.is_suspended = false;
1331 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1332
1333 devfreq_resume_device(hba->devfreq);
1334}
1335
a3cd5ec5 1336static int ufshcd_devfreq_target(struct device *dev,
1337 unsigned long *freq, u32 flags)
1338{
1339 int ret = 0;
1340 struct ufs_hba *hba = dev_get_drvdata(dev);
1341 ktime_t start;
401f1e44 1342 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1343 struct list_head *clk_list = &hba->clk_list_head;
1344 struct ufs_clk_info *clki;
a3cd5ec5 1345 unsigned long irq_flags;
1346
1347 if (!ufshcd_is_clkscaling_supported(hba))
1348 return -EINVAL;
1349
91831d33
AD		 1350 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1351 /* Override with the closest supported frequency */
1352 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1353 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1354 if (ufshcd_eh_in_progress(hba)) {
1355 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1356 return 0;
1357 }
1358
401f1e44 1359 if (!hba->clk_scaling.active_reqs)
1360 sched_clk_scaling_suspend_work = true;
1361
092b4558
BA		 1362 if (list_empty(clk_list)) {
1363 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1364 goto out;
1365 }
1366
91831d33 1367 /* Decide based on the rounded-off frequency and update */
51d1628f 1368 scale_up = *freq == clki->max_freq;
91831d33
AD		 1369 if (!scale_up)
1370 *freq = clki->min_freq;
1371 /* Update the frequency */
401f1e44 1372 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1373 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1374 ret = 0;
1375 goto out; /* no state change required */
a3cd5ec5 1376 }
1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1378
1379 start = ktime_get();
a3cd5ec5 1380 ret = ufshcd_devfreq_scale(hba, scale_up);
1381
a3cd5ec5 1382 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1383 (scale_up ? "up" : "down"),
1384 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1385
401f1e44 1386out:
1387 if (sched_clk_scaling_suspend_work)
1388 queue_work(hba->clk_scaling.workq,
1389 &hba->clk_scaling.suspend_work);
1390
a3cd5ec5 1391 return ret;
1392}
1393
a3cd5ec5 1394static int ufshcd_devfreq_get_dev_status(struct device *dev,
1395 struct devfreq_dev_status *stat)
1396{
1397 struct ufs_hba *hba = dev_get_drvdata(dev);
1398 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1399 unsigned long flags;
91831d33
AD		 1400 struct list_head *clk_list = &hba->clk_list_head;
1401 struct ufs_clk_info *clki;
b1bf66d1 1402 ktime_t curr_t;
a3cd5ec5 1403
1404 if (!ufshcd_is_clkscaling_supported(hba))
1405 return -EINVAL;
1406
1407 memset(stat, 0, sizeof(*stat));
1408
1409 spin_lock_irqsave(hba->host->host_lock, flags);
b1bf66d1 1410 curr_t = ktime_get();
a3cd5ec5 1411 if (!scaling->window_start_t)
1412 goto start_window;
1413
91831d33
AD		 1414 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1415 /*
1416 * If current frequency is 0, then the ondemand governor considers
1417 * there's no initial frequency set. And it always requests to set
1418 * to max. frequency.
1419 */
1420 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1421 if (scaling->is_busy_started)
b1bf66d1
SC		 1422 scaling->tot_busy_t += ktime_us_delta(curr_t,
1423 scaling->busy_start_t);
a3cd5ec5 1424
b1bf66d1 1425 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
a3cd5ec5 1426 stat->busy_time = scaling->tot_busy_t;
1427start_window:
b1bf66d1 1428 scaling->window_start_t = curr_t;
a3cd5ec5 1429 scaling->tot_busy_t = 0;
1430
1431 if (hba->outstanding_reqs) {
b1bf66d1 1432 scaling->busy_start_t = curr_t;
a3cd5ec5 1433 scaling->is_busy_started = true;
1434 } else {
1435 scaling->busy_start_t = 0;
1436 scaling->is_busy_started = false;
1437 }
1438 spin_unlock_irqrestore(hba->host->host_lock, flags);
1439 return 0;
1440}
1441
deac444f
BA		 1442static int ufshcd_devfreq_init(struct ufs_hba *hba)
1443{
092b4558
BA		 1444 struct list_head *clk_list = &hba->clk_list_head;
1445 struct ufs_clk_info *clki;
deac444f
BA		 1446 struct devfreq *devfreq;
1447 int ret;
1448
092b4558
BA		 1449 /* Skip devfreq if we don't have any clocks in the list */
1450 if (list_empty(clk_list))
1451 return 0;
1452
1453 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1454 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1455 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1456
90b8491c
SC		 1457 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1458 &hba->vps->ondemand_data);
092b4558 1459 devfreq = devfreq_add_device(hba->dev,
90b8491c 1460 &hba->vps->devfreq_profile,
deac444f 1461 DEVFREQ_GOV_SIMPLE_ONDEMAND,
90b8491c 1462 &hba->vps->ondemand_data);
deac444f
BA		 1463 if (IS_ERR(devfreq)) {
1464 ret = PTR_ERR(devfreq);
1465 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1466
1467 dev_pm_opp_remove(hba->dev, clki->min_freq);
1468 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1469 return ret;
1470 }
1471
1472 hba->devfreq = devfreq;
1473
1474 return 0;
1475}
1476
092b4558
BA		 1477static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1478{
1479 struct list_head *clk_list = &hba->clk_list_head;
1480 struct ufs_clk_info *clki;
1481
1482 if (!hba->devfreq)
1483 return;
1484
1485 devfreq_remove_device(hba->devfreq);
1486 hba->devfreq = NULL;
1487
1488 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1489 dev_pm_opp_remove(hba->dev, clki->min_freq);
1490 dev_pm_opp_remove(hba->dev, clki->max_freq);
1491}
1492
401f1e44 1493static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1494{
1495 unsigned long flags;
1496
1497 devfreq_suspend_device(hba->devfreq);
1498 spin_lock_irqsave(hba->host->host_lock, flags);
1499 hba->clk_scaling.window_start_t = 0;
1500 spin_unlock_irqrestore(hba->host->host_lock, flags);
1501}
a3cd5ec5 1502
a508253d
GB		 1503static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1504{
401f1e44 1505 unsigned long flags;
1506 bool suspend = false;
1507
f9a7fa34
SC		 1508 cancel_work_sync(&hba->clk_scaling.suspend_work);
1509 cancel_work_sync(&hba->clk_scaling.resume_work);
fcb0c4b0 1510
401f1e44 1511 spin_lock_irqsave(hba->host->host_lock, flags);
1512 if (!hba->clk_scaling.is_suspended) {
1513 suspend = true;
1514 hba->clk_scaling.is_suspended = true;
1515 }
1516 spin_unlock_irqrestore(hba->host->host_lock, flags);
1517
1518 if (suspend)
1519 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1520}
1521
1522static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1523{
401f1e44 1524 unsigned long flags;
1525 bool resume = false;
1526
401f1e44 1527 spin_lock_irqsave(hba->host->host_lock, flags);
1528 if (hba->clk_scaling.is_suspended) {
1529 resume = true;
1530 hba->clk_scaling.is_suspended = false;
1531 }
1532 spin_unlock_irqrestore(hba->host->host_lock, flags);
1533
1534 if (resume)
1535 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1536}
1537
1538static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1539 struct device_attribute *attr, char *buf)
1540{
1541 struct ufs_hba *hba = dev_get_drvdata(dev);
1542
1481b7fe 1543 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
fcb0c4b0
ST		 1544}
1545
1546static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1547 struct device_attribute *attr, const char *buf, size_t count)
1548{
1549 struct ufs_hba *hba = dev_get_drvdata(dev);
1550 u32 value;
9cd20d3f 1551 int err = 0;
fcb0c4b0
ST		 1552
1553 if (kstrtou32(buf, 0, &value))
1554 return -EINVAL;
1555
9cd20d3f
CG		 1556 down(&hba->host_sem);
1557 if (!ufshcd_is_user_access_allowed(hba)) {
1558 err = -EBUSY;
1559 goto out;
1560 }
1561
fcb0c4b0 1562 value = !!value;
0e9d4ca4 1563 if (value == hba->clk_scaling.is_enabled)
fcb0c4b0
ST		 1564 goto out;
1565
b294ff3e 1566 ufshcd_rpm_get_sync(hba);
fcb0c4b0
ST		 1567 ufshcd_hold(hba, false);
1568
0e9d4ca4 1569 hba->clk_scaling.is_enabled = value;
401f1e44 1570
fcb0c4b0
ST		 1571 if (value) {
1572 ufshcd_resume_clkscaling(hba);
1573 } else {
1574 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1575 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1576 if (err)
1577 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1578 __func__, err);
1579 }
fcb0c4b0
ST		 1580
1581 ufshcd_release(hba);
b294ff3e 1582 ufshcd_rpm_put_sync(hba);
fcb0c4b0 1583out:
9cd20d3f
CG		 1584 up(&hba->host_sem);
1585 return err ? err : count;
a508253d
GB		 1586}
1587
4543d9d7 1588static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
a3cd5ec5 1589{
1590 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1591 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1592 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1593 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1594 hba->clk_scaling.enable_attr.attr.mode = 0644;
1595 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1596 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1597}
1598
4543d9d7
CG		 1599static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1600{
1601 if (hba->clk_scaling.enable_attr.attr.name)
1602 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1603}
1604
1605static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1606{
1607 char wq_name[sizeof("ufs_clkscaling_00")];
1608
1609 if (!ufshcd_is_clkscaling_supported(hba))
1610 return;
1611
80d892f4
CG		 1612 if (!hba->clk_scaling.min_gear)
1613 hba->clk_scaling.min_gear = UFS_HS_G1;
1614
4543d9d7
CG		 1615 INIT_WORK(&hba->clk_scaling.suspend_work,
1616 ufshcd_clk_scaling_suspend_work);
1617 INIT_WORK(&hba->clk_scaling.resume_work,
1618 ufshcd_clk_scaling_resume_work);
1619
1620 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1621 hba->host->host_no);
1622 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1623
1624 hba->clk_scaling.is_initialized = true;
1625}
1626
1627static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1628{
1629 if (!hba->clk_scaling.is_initialized)
1630 return;
1631
1632 ufshcd_remove_clk_scaling_sysfs(hba);
1633 destroy_workqueue(hba->clk_scaling.workq);
1634 ufshcd_devfreq_remove(hba);
1635 hba->clk_scaling.is_initialized = false;
1636}
1637
1ab27c9c
ST		 1638static void ufshcd_ungate_work(struct work_struct *work)
1639{
1640 int ret;
1641 unsigned long flags;
1642 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1643 clk_gating.ungate_work);
1644
1645 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1646
1647 spin_lock_irqsave(hba->host->host_lock, flags);
1648 if (hba->clk_gating.state == CLKS_ON) {
1649 spin_unlock_irqrestore(hba->host->host_lock, flags);
1650 goto unblock_reqs;
1651 }
1652
1653 spin_unlock_irqrestore(hba->host->host_lock, flags);
dd7143e2 1654 ufshcd_hba_vreg_set_hpm(hba);
1ab27c9c
ST		 1655 ufshcd_setup_clocks(hba, true);
1656
8b0bbf00
SC		 1657 ufshcd_enable_irq(hba);
1658
1ab27c9c
ST		 1659 /* Exit from hibern8 */
1660 if (ufshcd_can_hibern8_during_gating(hba)) {
1661 /* Prevent gating in this path */
1662 hba->clk_gating.is_suspended = true;
1663 if (ufshcd_is_link_hibern8(hba)) {
1664 ret = ufshcd_uic_hibern8_exit(hba);
1665 if (ret)
1666 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1667 __func__, ret);
1668 else
1669 ufshcd_set_link_active(hba);
1670 }
1671 hba->clk_gating.is_suspended = false;
1672 }
1673unblock_reqs:
38135535 1674 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1675}
1676
1677/**
1678 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1679 * Also, exit from hibern8 mode and set the link as active.
1680 * @hba: per adapter instance
1681 * @async: This indicates whether caller should ungate clocks asynchronously.
1682 */
1683int ufshcd_hold(struct ufs_hba *hba, bool async)
1684{
1685 int rc = 0;
93b6c5db 1686 bool flush_result;
1ab27c9c
ST		 1687 unsigned long flags;
1688
3489c34b
BVA		 1689 if (!ufshcd_is_clkgating_allowed(hba) ||
1690 !hba->clk_gating.is_initialized)
1ab27c9c 1691 goto out;
1ab27c9c
ST		 1692 spin_lock_irqsave(hba->host->host_lock, flags);
1693 hba->clk_gating.active_reqs++;
1694
856b3483 1695start:
1ab27c9c
ST		 1696 switch (hba->clk_gating.state) {
1697 case CLKS_ON:
f2a785ac
VG		 1698 /*
1699 * Wait for the ungate work to complete if in progress.
1700 * Though the clocks may be in ON state, the link could
1701 * still be in hibner8 state if hibern8 is allowed
1702 * during clock gating.
1703 * Make sure we exit hibern8 state also in addition to
1704 * clocks being ON.
1705 */
1706 if (ufshcd_can_hibern8_during_gating(hba) &&
1707 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1708 if (async) {
1709 rc = -EAGAIN;
1710 hba->clk_gating.active_reqs--;
1711 break;
1712 }
f2a785ac 1713 spin_unlock_irqrestore(hba->host->host_lock, flags);
93b6c5db
SC		 1714 flush_result = flush_work(&hba->clk_gating.ungate_work);
1715 if (hba->clk_gating.is_suspended && !flush_result)
1716 goto out;
f2a785ac
VG		 1717 spin_lock_irqsave(hba->host->host_lock, flags);
1718 goto start;
1719 }
1ab27c9c
ST		 1720 break;
1721 case REQ_CLKS_OFF:
1722 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1723 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1724 trace_ufshcd_clk_gating(dev_name(hba->dev),
1725 hba->clk_gating.state);
1ab27c9c
ST		 1726 break;
1727 }
1728 /*
9c490d2d 1729 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1730 * currently running. Hence, fall through to cancel gating
1731 * work and to enable clocks.
1732 */
df561f66 1733 fallthrough;
1ab27c9c 1734 case CLKS_OFF:
1ab27c9c 1735 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1736 trace_ufshcd_clk_gating(dev_name(hba->dev),
1737 hba->clk_gating.state);
da3fecb0
CG		 1738 if (queue_work(hba->clk_gating.clk_gating_workq,
1739 &hba->clk_gating.ungate_work))
1740 ufshcd_scsi_block_requests(hba);
1ab27c9c
ST		 1741 /*
1742 * fall through to check if we should wait for this
1743 * work to be done or not.
1744 */
df561f66 1745 fallthrough;
1ab27c9c
ST		 1746 case REQ_CLKS_ON:
1747 if (async) {
1748 rc = -EAGAIN;
1749 hba->clk_gating.active_reqs--;
1750 break;
1751 }
1752
1753 spin_unlock_irqrestore(hba->host->host_lock, flags);
1754 flush_work(&hba->clk_gating.ungate_work);
1755 /* Make sure state is CLKS_ON before returning */
856b3483 1756 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1757 goto start;
1758 default:
1759 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1760 __func__, hba->clk_gating.state);
1761 break;
1762 }
1763 spin_unlock_irqrestore(hba->host->host_lock, flags);
1764out:
1765 return rc;
1766}
6e3fd44d 1767EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1768
1769static void ufshcd_gate_work(struct work_struct *work)
1770{
1771 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1772 clk_gating.gate_work.work);
1773 unsigned long flags;
4db7a236 1774 int ret;
1ab27c9c
ST		 1775
1776 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1777 /*
1778 * In case you are here to cancel this work the gating state
1779 * would be marked as REQ_CLKS_ON. In this case save time by
1780 * skipping the gating work and exit after changing the clock
1781 * state to CLKS_ON.
1782 */
1783 if (hba->clk_gating.is_suspended ||
18f01374 1784 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1785 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1786 trace_ufshcd_clk_gating(dev_name(hba->dev),
1787 hba->clk_gating.state);
1ab27c9c
ST		 1788 goto rel_lock;
1789 }
1790
1791 if (hba->clk_gating.active_reqs
1792 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
bd0b3538 1793 || hba->outstanding_reqs || hba->outstanding_tasks
1ab27c9c
ST		 1794 || hba->active_uic_cmd || hba->uic_async_done)
1795 goto rel_lock;
1796
1797 spin_unlock_irqrestore(hba->host->host_lock, flags);
1798
1799 /* put the link into hibern8 mode before turning off clocks */
1800 if (ufshcd_can_hibern8_during_gating(hba)) {
4db7a236
CG		 1801 ret = ufshcd_uic_hibern8_enter(hba);
1802 if (ret) {
1ab27c9c 1803 hba->clk_gating.state = CLKS_ON;
4db7a236
CG		 1804 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1805 __func__, ret);
7ff5ab47 1806 trace_ufshcd_clk_gating(dev_name(hba->dev),
1807 hba->clk_gating.state);
1ab27c9c
ST		 1808 goto out;
1809 }
1810 ufshcd_set_link_hibern8(hba);
1811 }
1812
8b0bbf00
SC		 1813 ufshcd_disable_irq(hba);
1814
81309c24 1815 ufshcd_setup_clocks(hba, false);
1ab27c9c 1816
dd7143e2
CG		 1817 /* Put the host controller in low power mode if possible */
1818 ufshcd_hba_vreg_set_lpm(hba);
1ab27c9c
ST		 1819 /*
1820 * In case you are here to cancel this work the gating state
1821 * would be marked as REQ_CLKS_ON. In this case keep the state
1822 * as REQ_CLKS_ON which would anyway imply that clocks are off
1823 * and a request to turn them on is pending. By doing this way,
1824 * we keep the state machine in tact and this would ultimately
1825 * prevent from doing cancel work multiple times when there are
1826 * new requests arriving before the current cancel work is done.
1827 */
1828 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1829 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1830 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1831 trace_ufshcd_clk_gating(dev_name(hba->dev),
1832 hba->clk_gating.state);
1833 }
1ab27c9c
ST		 1834rel_lock:
1835 spin_unlock_irqrestore(hba->host->host_lock, flags);
1836out:
1837 return;
1838}
1839
1840/* host lock must be held before calling this variant */
1841static void __ufshcd_release(struct ufs_hba *hba)
1842{
1843 if (!ufshcd_is_clkgating_allowed(hba))
1844 return;
1845
1846 hba->clk_gating.active_reqs--;
1847
4db7a236
CG		 1848 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1849 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
3489c34b 1850 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
fd62de11
JK		 1851 hba->active_uic_cmd || hba->uic_async_done ||
1852 hba->clk_gating.state == CLKS_OFF)
1ab27c9c
ST		 1853 return;
1854
1855 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1856 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1857 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1858 &hba->clk_gating.gate_work,
1859 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1860}
1861
1862void ufshcd_release(struct ufs_hba *hba)
1863{
1864 unsigned long flags;
1865
1866 spin_lock_irqsave(hba->host->host_lock, flags);
1867 __ufshcd_release(hba);
1868 spin_unlock_irqrestore(hba->host->host_lock, flags);
1869}
6e3fd44d 1870EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1871
1872static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1873 struct device_attribute *attr, char *buf)
1874{
1875 struct ufs_hba *hba = dev_get_drvdata(dev);
1876
bafd09f8 1877 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1ab27c9c
ST		 1878}
1879
ad8a647e
BVA		 1880void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1881{
1882 struct ufs_hba *hba = dev_get_drvdata(dev);
1883 unsigned long flags;
1884
1885 spin_lock_irqsave(hba->host->host_lock, flags);
1886 hba->clk_gating.delay_ms = value;
1887 spin_unlock_irqrestore(hba->host->host_lock, flags);
1888}
1889EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1890
1ab27c9c
ST		 1891static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1892 struct device_attribute *attr, const char *buf, size_t count)
1893{
ad8a647e 1894 unsigned long value;
1ab27c9c
ST		 1895
1896 if (kstrtoul(buf, 0, &value))
1897 return -EINVAL;
1898
ad8a647e 1899 ufshcd_clkgate_delay_set(dev, value);
1ab27c9c
ST		 1900 return count;
1901}
1902
b427411a
ST		 1903static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1904 struct device_attribute *attr, char *buf)
1905{
1906 struct ufs_hba *hba = dev_get_drvdata(dev);
1907
bafd09f8 1908 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
b427411a
ST		 1909}
1910
1911static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1912 struct device_attribute *attr, const char *buf, size_t count)
1913{
1914 struct ufs_hba *hba = dev_get_drvdata(dev);
1915 unsigned long flags;
1916 u32 value;
1917
1918 if (kstrtou32(buf, 0, &value))
1919 return -EINVAL;
1920
1921 value = !!value;
b6645112
JK		 1922
1923 spin_lock_irqsave(hba->host->host_lock, flags);
b427411a
ST		 1924 if (value == hba->clk_gating.is_enabled)
1925 goto out;
1926
b6645112
JK		 1927 if (value)
1928 __ufshcd_release(hba);
1929 else
b427411a 1930 hba->clk_gating.active_reqs++;
b427411a
ST		 1931
1932 hba->clk_gating.is_enabled = value;
1933out:
b6645112 1934 spin_unlock_irqrestore(hba->host->host_lock, flags);
b427411a
ST		 1935 return count;
1936}
1937
4543d9d7 1938static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1939{
4543d9d7
CG		 1940 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1941 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1942 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1943 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1944 hba->clk_gating.delay_attr.attr.mode = 0644;
1945 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1946 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
eebcc196 1947
4543d9d7
CG		 1948 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1949 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1950 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1951 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1952 hba->clk_gating.enable_attr.attr.mode = 0644;
1953 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1954 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
eebcc196
VG		 1955}
1956
4543d9d7 1957static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1958{
4543d9d7
CG		 1959 if (hba->clk_gating.delay_attr.attr.name)
1960 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1961 if (hba->clk_gating.enable_attr.attr.name)
1962 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
eebcc196
VG		 1963}
1964
1ab27c9c
ST		 1965static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1966{
10e5e375
VV		 1967 char wq_name[sizeof("ufs_clk_gating_00")];
1968
1ab27c9c
ST		 1969 if (!ufshcd_is_clkgating_allowed(hba))
1970 return;
1971
2dec9475
CG		 1972 hba->clk_gating.state = CLKS_ON;
1973
1ab27c9c
ST		 1974 hba->clk_gating.delay_ms = 150;
1975 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1976 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1977
10e5e375
VV		 1978 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1979 hba->host->host_no);
1980 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
e93e6e49 1981 WQ_MEM_RECLAIM | WQ_HIGHPRI);
10e5e375 1982
4543d9d7 1983 ufshcd_init_clk_gating_sysfs(hba);
b427411a 1984
4543d9d7
CG		 1985 hba->clk_gating.is_enabled = true;
1986 hba->clk_gating.is_initialized = true;
1ab27c9c
ST		 1987}
1988
1989static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1990{
4543d9d7 1991 if (!hba->clk_gating.is_initialized)
1ab27c9c 1992 return;
3489c34b 1993
4543d9d7 1994 ufshcd_remove_clk_gating_sysfs(hba);
3489c34b
BVA		 1995
1996 /* Ungate the clock if necessary. */
1997 ufshcd_hold(hba, false);
4543d9d7 1998 hba->clk_gating.is_initialized = false;
3489c34b
BVA		 1999 ufshcd_release(hba);
2000
2001 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 2002}
2003
856b3483
ST		 2004/* Must be called with host lock acquired */
2005static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2006{
401f1e44 2007 bool queue_resume_work = false;
b1bf66d1 2008 ktime_t curr_t = ktime_get();
a45f9371 2009 unsigned long flags;
401f1e44 2010
fcb0c4b0 2011 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2012 return;
2013
a45f9371 2014 spin_lock_irqsave(hba->host->host_lock, flags);
401f1e44 2015 if (!hba->clk_scaling.active_reqs++)
2016 queue_resume_work = true;
2017
a45f9371
CG		 2018 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2019 spin_unlock_irqrestore(hba->host->host_lock, flags);
401f1e44 2020 return;
a45f9371 2021 }
401f1e44 2022
2023 if (queue_resume_work)
2024 queue_work(hba->clk_scaling.workq,
2025 &hba->clk_scaling.resume_work);
2026
2027 if (!hba->clk_scaling.window_start_t) {
b1bf66d1 2028 hba->clk_scaling.window_start_t = curr_t;
401f1e44 2029 hba->clk_scaling.tot_busy_t = 0;
2030 hba->clk_scaling.is_busy_started = false;
2031 }
2032
856b3483 2033 if (!hba->clk_scaling.is_busy_started) {
b1bf66d1 2034 hba->clk_scaling.busy_start_t = curr_t;
856b3483
ST		 2035 hba->clk_scaling.is_busy_started = true;
2036 }
a45f9371 2037 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483
ST		 2038}
2039
2040static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2041{
2042 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
a45f9371 2043 unsigned long flags;
856b3483 2044
fcb0c4b0 2045 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2046 return;
2047
a45f9371
CG		 2048 spin_lock_irqsave(hba->host->host_lock, flags);
2049 hba->clk_scaling.active_reqs--;
856b3483
ST		 2050 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2051 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2052 scaling->busy_start_t));
8b0e1953 2053 scaling->busy_start_t = 0;
856b3483
ST		 2054 scaling->is_busy_started = false;
2055 }
a45f9371 2056 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2057}
1d8613a2
CG		 2058
2059static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2060{
2061 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2062 return READ;
2063 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2064 return WRITE;
2065 else
2066 return -EINVAL;
2067}
2068
2069static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2070 struct ufshcd_lrb *lrbp)
2071{
2072 struct ufs_hba_monitor *m = &hba->monitor;
2073
2074 return (m->enabled && lrbp && lrbp->cmd &&
2075 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2076 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2077}
2078
2079static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2080{
2081 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2082 unsigned long flags;
1d8613a2 2083
a45f9371 2084 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2
CG		 2085 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2086 hba->monitor.busy_start_ts[dir] = ktime_get();
a45f9371 2087 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d8613a2
CG		 2088}
2089
2090static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2091{
2092 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2093 unsigned long flags;
1d8613a2 2094
a45f9371 2095 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2 2096 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
3f2c1002 2097 struct request *req = scsi_cmd_to_rq(lrbp->cmd);
1d8613a2
CG		 2098 struct ufs_hba_monitor *m = &hba->monitor;
2099 ktime_t now, inc, lat;
2100
2101 now = lrbp->compl_time_stamp;
2102 inc = ktime_sub(now, m->busy_start_ts[dir]);
2103 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2104 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2105
2106 /* Update latencies */
2107 m->nr_req[dir]++;
2108 lat = ktime_sub(now, lrbp->issue_time_stamp);
2109 m->lat_sum[dir] += lat;
2110 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2111 m->lat_max[dir] = lat;
2112 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2113 m->lat_min[dir] = lat;
2114
2115 m->nr_queued[dir]--;
2116 /* Push forward the busy start of monitor */
2117 m->busy_start_ts[dir] = now;
2118 }
a45f9371 2119 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2120}
1d8613a2 2121
7a3e97b0
SY		 2122/**
2123 * ufshcd_send_command - Send SCSI or device management commands
2124 * @hba: per adapter instance
2125 * @task_tag: Task tag of the command
2126 */
2127static inline
2128void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2129{
6edfdcfe 2130 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
1f522c50 2131 unsigned long flags;
6edfdcfe
SC		 2132
2133 lrbp->issue_time_stamp = ktime_get();
2134 lrbp->compl_time_stamp = ktime_set(0, 0);
28fa68fc 2135 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
856b3483 2136 ufshcd_clk_scaling_start_busy(hba);
1d8613a2
CG		 2137 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2138 ufshcd_start_monitor(hba, lrbp);
169f5eb2
BVA		 2139
2140 spin_lock_irqsave(&hba->outstanding_lock, flags);
a024ad0d
BVA		 2141 if (hba->vops && hba->vops->setup_xfer_req)
2142 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
169f5eb2 2143 __set_bit(task_tag, &hba->outstanding_reqs);
1f522c50 2144 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
169f5eb2 2145 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7a3e97b0
SY		 2146}
2147
2148/**
2149 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 2150 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2151 */
2152static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2153{
1de4378f 2154 u8 *const sense_buffer = lrbp->cmd->sense_buffer;
7a3e97b0 2155 int len;
1de4378f
BVA		 2156
2157 if (sense_buffer &&
1c2623c5 2158 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 2159 int len_to_copy;
2160
5a0b0cb9 2161 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 2162 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 2163
1de4378f 2164 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
09a5a24f 2165 len_to_copy);
7a3e97b0
SY		 2166 }
2167}
2168
68078d5c
DR		 2169/**
2170 * ufshcd_copy_query_response() - Copy the Query Response and the data
2171 * descriptor
2172 * @hba: per adapter instance
8aa29f19 2173 * @lrbp: pointer to local reference block
68078d5c
DR		 2174 */
2175static
c6d4a831 2176int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 2177{
2178 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2179
68078d5c 2180 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 2181
68078d5c 2182 /* Get the descriptor */
1c90836f
AA		 2183 if (hba->dev_cmd.query.descriptor &&
2184 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 2185 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 2186 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 2187 u16 resp_len;
2188 u16 buf_len;
68078d5c
DR		 2189
2190 /* data segment length */
c6d4a831 2191 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 2192 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 2193 buf_len = be16_to_cpu(
2194 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 2195 if (likely(buf_len >= resp_len)) {
2196 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2197 } else {
2198 dev_warn(hba->dev,
3d4881d1
BH		 2199 "%s: rsp size %d is bigger than buffer size %d",
2200 __func__, resp_len, buf_len);
c6d4a831
DR		 2201 return -EINVAL;
2202 }
68078d5c 2203 }
c6d4a831
DR		 2204
2205 return 0;
68078d5c
DR		 2206}
2207
7a3e97b0
SY		 2208/**
2209 * ufshcd_hba_capabilities - Read controller capabilities
2210 * @hba: per adapter instance
df043c74
ST		 2211 *
2212 * Return: 0 on success, negative on error.
7a3e97b0 2213 */
df043c74 2214static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
7a3e97b0 2215{
df043c74
ST		 2216 int err;
2217
b873a275 2218 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 2219
2220 /* nutrs and nutmrs are 0 based values */
2221 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2222 hba->nutmrs =
2223 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
945c3cca 2224 hba->reserved_slot = hba->nutrs - 1;
df043c74
ST		 2225
2226 /* Read crypto capabilities */
2227 err = ufshcd_hba_init_crypto_capabilities(hba);
2228 if (err)
2229 dev_err(hba->dev, "crypto setup failed\n");
2230
2231 return err;
7a3e97b0
SY		 2232}
2233
2234/**
6ccf44fe
SJ		 2235 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2236 * to accept UIC commands
7a3e97b0 2237 * @hba: per adapter instance
6ccf44fe
SJ		 2238 * Return true on success, else false
2239 */
2240static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2241{
a858af9a 2242 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
6ccf44fe
SJ		 2243}
2244
53b3d9c3
SJ		 2245/**
2246 * ufshcd_get_upmcrs - Get the power mode change request status
2247 * @hba: Pointer to adapter instance
2248 *
2249 * This function gets the UPMCRS field of HCS register
2250 * Returns value of UPMCRS field
2251 */
2252static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2253{
2254 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2255}
2256
6ccf44fe 2257/**
35c7d874 2258 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
6ccf44fe
SJ		 2259 * @hba: per adapter instance
2260 * @uic_cmd: UIC command
7a3e97b0
SY		 2261 */
2262static inline void
6ccf44fe 2263ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2264{
35c7d874
BVA		 2265 lockdep_assert_held(&hba->uic_cmd_mutex);
2266
6ccf44fe
SJ		 2267 WARN_ON(hba->active_uic_cmd);
2268
2269 hba->active_uic_cmd = uic_cmd;
2270
7a3e97b0 2271 /* Write Args */
6ccf44fe
SJ		 2272 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2273 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2274 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0 2275
28fa68fc 2276 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
aa5c6979 2277
7a3e97b0 2278 /* Write UIC Cmd */
6ccf44fe 2279 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2280 REG_UIC_COMMAND);
7a3e97b0
SY		 2281}
2282
6ccf44fe 2283/**
35c7d874 2284 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
6ccf44fe 2285 * @hba: per adapter instance
8aa29f19 2286 * @uic_cmd: UIC command
6ccf44fe 2287 *
6ccf44fe
SJ		 2288 * Returns 0 only if success.
2289 */
2290static int
2291ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2292{
2293 int ret;
2294 unsigned long flags;
2295
35c7d874
BVA		 2296 lockdep_assert_held(&hba->uic_cmd_mutex);
2297
6ccf44fe 2298 if (wait_for_completion_timeout(&uic_cmd->done,
0f52fcb9 2299 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
6ccf44fe 2300 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
0f52fcb9 2301 } else {
6ccf44fe 2302 ret = -ETIMEDOUT;
0f52fcb9
CG		 2303 dev_err(hba->dev,
2304 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2305 uic_cmd->command, uic_cmd->argument3);
2306
2307 if (!uic_cmd->cmd_active) {
2308 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2309 __func__);
2310 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2311 }
2312 }
6ccf44fe
SJ		 2313
2314 spin_lock_irqsave(hba->host->host_lock, flags);
2315 hba->active_uic_cmd = NULL;
2316 spin_unlock_irqrestore(hba->host->host_lock, flags);
2317
2318 return ret;
2319}
2320
2321/**
2322 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2323 * @hba: per adapter instance
2324 * @uic_cmd: UIC command
d75f7fe4 2325 * @completion: initialize the completion only if this is set to true
6ccf44fe 2326 *
6ccf44fe
SJ		 2327 * Returns 0 only if success.
2328 */
2329static int
d75f7fe4
YG		 2330__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2331 bool completion)
6ccf44fe 2332{
35c7d874
BVA		 2333 lockdep_assert_held(&hba->uic_cmd_mutex);
2334 lockdep_assert_held(hba->host->host_lock);
2335
6ccf44fe
SJ		 2336 if (!ufshcd_ready_for_uic_cmd(hba)) {
2337 dev_err(hba->dev,
2338 "Controller not ready to accept UIC commands\n");
2339 return -EIO;
2340 }
2341
d75f7fe4
YG		 2342 if (completion)
2343 init_completion(&uic_cmd->done);
6ccf44fe 2344
0f52fcb9 2345 uic_cmd->cmd_active = 1;
6ccf44fe 2346 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2347
57d104c1 2348 return 0;
6ccf44fe
SJ		 2349}
2350
2351/**
2352 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2353 * @hba: per adapter instance
2354 * @uic_cmd: UIC command
2355 *
2356 * Returns 0 only if success.
2357 */
e77044c5 2358int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2359{
2360 int ret;
57d104c1 2361 unsigned long flags;
6ccf44fe 2362
a22bcfdb 2363 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2364 return 0;
2365
1ab27c9c 2366 ufshcd_hold(hba, false);
6ccf44fe 2367 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2368 ufshcd_add_delay_before_dme_cmd(hba);
2369
57d104c1 2370 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2371 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2372 spin_unlock_irqrestore(hba->host->host_lock, flags);
2373 if (!ret)
2374 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2375
6ccf44fe
SJ		 2376 mutex_unlock(&hba->uic_cmd_mutex);
2377
1ab27c9c 2378 ufshcd_release(hba);
6ccf44fe
SJ		 2379 return ret;
2380}
2381
7a3e97b0
SY		 2382/**
2383 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2384 * @hba: per adapter instance
2385 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2386 *
2387 * Returns 0 in case of success, non-zero value in case of failure
2388 */
75b1cc4a 2389static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2390{
2391 struct ufshcd_sg_entry *prd_table;
2392 struct scatterlist *sg;
2393 struct scsi_cmnd *cmd;
2394 int sg_segments;
2395 int i;
2396
2397 cmd = lrbp->cmd;
2398 sg_segments = scsi_dma_map(cmd);
2399 if (sg_segments < 0)
2400 return sg_segments;
2401
2402 if (sg_segments) {
26f968d7
AA		 2403
2404 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2405 lrbp->utr_descriptor_ptr->prd_table_length =
2406 cpu_to_le16((sg_segments *
2407 sizeof(struct ufshcd_sg_entry)));
2408 else
2409 lrbp->utr_descriptor_ptr->prd_table_length =
3ad317a1 2410 cpu_to_le16(sg_segments);
7a3e97b0 2411
3ad317a1 2412 prd_table = lrbp->ucd_prdt_ptr;
7a3e97b0
SY		 2413
2414 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1ea7d802
BVA		 2415 const unsigned int len = sg_dma_len(sg);
2416
2417 /*
2418 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2419 * based value that indicates the length, in bytes, of
2420 * the data block. A maximum of length of 256KB may
2421 * exist for any entry. Bits 1:0 of this field shall be
2422 * 11b to indicate Dword granularity. A value of '3'
2423 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2424 */
2425 WARN_ONCE(len > 256 * 1024, "len = %#x\n", len);
2426 prd_table[i].size = cpu_to_le32(len - 1);
2427 prd_table[i].addr = cpu_to_le64(sg->dma_address);
52ac95fe 2428 prd_table[i].reserved = 0;
7a3e97b0
SY		 2429 }
2430 } else {
2431 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2432 }
2433
2434 return 0;
2435}
2436
2437/**
2fbd009b 2438 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2439 * @hba: per adapter instance
2fbd009b 2440 * @intrs: interrupt bits
7a3e97b0 2441 */
2fbd009b 2442static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2443{
2fbd009b
SJ		 2444 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2445
51428818 2446 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2447 u32 rw;
2448 rw = set & INTERRUPT_MASK_RW_VER_10;
2449 set = rw | ((set ^ intrs) & intrs);
2450 } else {
2451 set |= intrs;
2452 }
2453
2454 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2455}
2456
2457/**
2458 * ufshcd_disable_intr - disable interrupts
2459 * @hba: per adapter instance
2460 * @intrs: interrupt bits
2461 */
2462static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2463{
2464 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2465
51428818 2466 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2467 u32 rw;
2468 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2469 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2470 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2471
2472 } else {
2473 set &= ~intrs;
7a3e97b0 2474 }
2fbd009b
SJ		 2475
2476 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2477}
2478
5a0b0cb9
SRT		 2479/**
2480 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2481 * descriptor according to request
2482 * @lrbp: pointer to local reference block
2483 * @upiu_flags: flags required in the header
2484 * @cmd_dir: requests data direction
2485 */
2486static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
a23064c4 2487 u8 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2488{
2489 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2490 u32 data_direction;
2491 u32 dword_0;
df043c74
ST		 2492 u32 dword_1 = 0;
2493 u32 dword_3 = 0;
5a0b0cb9
SRT		 2494
2495 if (cmd_dir == DMA_FROM_DEVICE) {
2496 data_direction = UTP_DEVICE_TO_HOST;
2497 *upiu_flags = UPIU_CMD_FLAGS_READ;
2498 } else if (cmd_dir == DMA_TO_DEVICE) {
2499 data_direction = UTP_HOST_TO_DEVICE;
2500 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2501 } else {
2502 data_direction = UTP_NO_DATA_TRANSFER;
2503 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2504 }
2505
2506 dword_0 = data_direction | (lrbp->command_type
2507 << UPIU_COMMAND_TYPE_OFFSET);
2508 if (lrbp->intr_cmd)
2509 dword_0 |= UTP_REQ_DESC_INT_CMD;
2510
df043c74
ST		 2511 /* Prepare crypto related dwords */
2512 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2513
5a0b0cb9
SRT		 2514 /* Transfer request descriptor header fields */
2515 req_desc->header.dword_0 = cpu_to_le32(dword_0);
df043c74 2516 req_desc->header.dword_1 = cpu_to_le32(dword_1);
5a0b0cb9
SRT		 2517 /*
2518 * assigning invalid value for command status. Controller
2519 * updates OCS on command completion, with the command
2520 * status
2521 */
2522 req_desc->header.dword_2 =
2523 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
df043c74 2524 req_desc->header.dword_3 = cpu_to_le32(dword_3);
51047266
YG		 2525
2526 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2527}
2528
2529/**
2530 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2531 * for scsi commands
8aa29f19
BVA		 2532 * @lrbp: local reference block pointer
2533 * @upiu_flags: flags
5a0b0cb9
SRT		 2534 */
2535static
a23064c4 2536void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
5a0b0cb9 2537{
1b21b8f0 2538 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2539 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2540 unsigned short cdb_len;
5a0b0cb9
SRT		 2541
2542 /* command descriptor fields */
2543 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2544 UPIU_TRANSACTION_COMMAND, upiu_flags,
2545 lrbp->lun, lrbp->task_tag);
2546 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2547 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2548
2549 /* Total EHS length and Data segment length will be zero */
2550 ucd_req_ptr->header.dword_2 = 0;
2551
1b21b8f0 2552 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2553
1b21b8f0 2554 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2555 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2556 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2557
2558 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2559}
2560
68078d5c
DR		 2561/**
2562 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2563 * for query requsts
2564 * @hba: UFS hba
2565 * @lrbp: local reference block pointer
2566 * @upiu_flags: flags
2567 */
2568static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
a23064c4 2569 struct ufshcd_lrb *lrbp, u8 upiu_flags)
68078d5c
DR		 2570{
2571 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2572 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2573 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2574
2575 /* Query request header */
2576 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2577 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2578 lrbp->lun, lrbp->task_tag);
2579 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2580 0, query->request.query_func, 0, 0);
2581
6861285c
ZL		 2582 /* Data segment length only need for WRITE_DESC */
2583 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2584 ucd_req_ptr->header.dword_2 =
2585 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2586 else
2587 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2588
2589 /* Copy the Query Request buffer as is */
2590 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2591 QUERY_OSF_SIZE);
68078d5c
DR		 2592
2593 /* Copy the Descriptor */
c6d4a831 2594 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2595 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2596
51047266 2597 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2598}
2599
5a0b0cb9
SRT		 2600static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2601{
2602 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2603
2604 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2605
2606 /* command descriptor fields */
2607 ucd_req_ptr->header.dword_0 =
2608 UPIU_HEADER_DWORD(
2609 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2610 /* clear rest of the fields of basic header */
2611 ucd_req_ptr->header.dword_1 = 0;
2612 ucd_req_ptr->header.dword_2 = 0;
2613
2614 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2615}
2616
7a3e97b0 2617/**
f273c54b 2618 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
300bb13f 2619 * for Device Management Purposes
8aa29f19
BVA		 2620 * @hba: per adapter instance
2621 * @lrbp: pointer to local reference block
7a3e97b0 2622 */
f273c54b
BH		 2623static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2624 struct ufshcd_lrb *lrbp)
7a3e97b0 2625{
a23064c4 2626 u8 upiu_flags;
5a0b0cb9 2627 int ret = 0;
7a3e97b0 2628
51428818 2629 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2630 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2631 else
2632 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2633
2634 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2635 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2636 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2637 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2638 ufshcd_prepare_utp_nop_upiu(lrbp);
2639 else
2640 ret = -EINVAL;
2641
2642 return ret;
2643}
2644
2645/**
2646 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2647 * for SCSI Purposes
8aa29f19
BVA		 2648 * @hba: per adapter instance
2649 * @lrbp: pointer to local reference block
300bb13f
JP		 2650 */
2651static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2652{
a23064c4 2653 u8 upiu_flags;
300bb13f
JP		 2654 int ret = 0;
2655
51428818 2656 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2657 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2658 else
2659 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2660
2661 if (likely(lrbp->cmd)) {
2662 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2663 lrbp->cmd->sc_data_direction);
2664 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2665 } else {
2666 ret = -EINVAL;
2667 }
5a0b0cb9
SRT		 2668
2669 return ret;
7a3e97b0
SY		 2670}
2671
2a8fa600
SJ		 2672/**
2673 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2674 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2675 *
2676 * Returns SCSI W-LUN id
2677 */
2678static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2679{
2680 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2681}
2682
b294ff3e
AD		 2683static inline bool is_device_wlun(struct scsi_device *sdev)
2684{
2685 return sdev->lun ==
2686 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2687}
2688
eaab9b57
BVA		 2689/*
2690 * Associate the UFS controller queue with the default and poll HCTX types.
2691 * Initialize the mq_map[] arrays.
2692 */
2693static int ufshcd_map_queues(struct Scsi_Host *shost)
2694{
2695 int i, ret;
2696
2697 for (i = 0; i < shost->nr_maps; i++) {
2698 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2699
2700 switch (i) {
2701 case HCTX_TYPE_DEFAULT:
2702 case HCTX_TYPE_POLL:
2703 map->nr_queues = 1;
2704 break;
2705 case HCTX_TYPE_READ:
2706 map->nr_queues = 0;
10af1156 2707 continue;
eaab9b57
BVA		 2708 default:
2709 WARN_ON_ONCE(true);
2710 }
2711 map->queue_offset = 0;
2712 ret = blk_mq_map_queues(map);
2713 WARN_ON_ONCE(ret);
2714 }
2715
2716 return 0;
2717}
2718
4d2b8d40
BVA		 2719static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2720{
2721 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2722 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2723 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2724 i * sizeof(struct utp_transfer_cmd_desc);
2725 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2726 response_upiu);
2727 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2728
2729 lrb->utr_descriptor_ptr = utrdlp + i;
2730 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2731 i * sizeof(struct utp_transfer_req_desc);
2732 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2733 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2734 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2735 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
3ad317a1 2736 lrb->ucd_prdt_ptr = cmd_descp[i].prd_table;
4d2b8d40
BVA		 2737 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2738}
2739
7a3e97b0
SY		 2740/**
2741 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2742 * @host: SCSI host pointer
7a3e97b0 2743 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2744 *
2745 * Returns 0 for success, non-zero in case of failure
2746 */
2747static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2748{
4728ab4a 2749 struct ufs_hba *hba = shost_priv(host);
3f2c1002 2750 int tag = scsi_cmd_to_rq(cmd)->tag;
7a3e97b0 2751 struct ufshcd_lrb *lrbp;
7a3e97b0
SY		 2752 int err = 0;
2753
eaab9b57 2754 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
7a3e97b0 2755
5675c381
BVA		 2756 /*
2757 * Allows the UFS error handler to wait for prior ufshcd_queuecommand()
2758 * calls.
2759 */
2760 rcu_read_lock();
2761
a45f9371
CG		 2762 switch (hba->ufshcd_state) {
2763 case UFSHCD_STATE_OPERATIONAL:
d489f18a 2764 break;
a45f9371 2765 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
d489f18a
AH		 2766 /*
2767 * SCSI error handler can call ->queuecommand() while UFS error
2768 * handler is in progress. Error interrupts could change the
2769 * state from UFSHCD_STATE_RESET to
2770 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2771 * being issued in that case.
2772 */
2773 if (ufshcd_eh_in_progress(hba)) {
2774 err = SCSI_MLQUEUE_HOST_BUSY;
2775 goto out;
2776 }
a45f9371
CG		 2777 break;
2778 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2779 /*
2780 * pm_runtime_get_sync() is used at error handling preparation
2781 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2782 * PM ops, it can never be finished if we let SCSI layer keep
2783 * retrying it, which gets err handler stuck forever. Neither
2784 * can we let the scsi cmd pass through, because UFS is in bad
2785 * state, the scsi cmd may eventually time out, which will get
2786 * err handler blocked for too long. So, just fail the scsi cmd
2787 * sent from PM ops, err handler can recover PM error anyways.
2788 */
2789 if (hba->pm_op_in_progress) {
2790 hba->force_reset = true;
2791 set_host_byte(cmd, DID_BAD_TARGET);
35c3730a 2792 scsi_done(cmd);
a45f9371
CG		 2793 goto out;
2794 }
2795 fallthrough;
2796 case UFSHCD_STATE_RESET:
2797 err = SCSI_MLQUEUE_HOST_BUSY;
2798 goto out;
2799 case UFSHCD_STATE_ERROR:
2800 set_host_byte(cmd, DID_ERROR);
35c3730a 2801 scsi_done(cmd);
a45f9371 2802 goto out;
a45f9371
CG		 2803 }
2804
7fabb77b
GB		 2805 hba->req_abort_count = 0;
2806
1ab27c9c
ST		 2807 err = ufshcd_hold(hba, true);
2808 if (err) {
2809 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2810 goto out;
2811 }
2dec9475
CG		 2812 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2813 (hba->clk_gating.state != CLKS_ON));
1ab27c9c 2814
a45f9371 2815 lrbp = &hba->lrb[tag];
5a0b0cb9 2816 WARN_ON(lrbp->cmd);
7a3e97b0 2817 lrbp->cmd = cmd;
7a3e97b0 2818 lrbp->task_tag = tag;
0ce147d4 2819 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
51d1628f 2820 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
df043c74 2821
3f2c1002 2822 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
df043c74 2823
e0b299e3 2824 lrbp->req_abort_skip = false;
7a3e97b0 2825
09d9e4d0 2826 ufshpb_prep(hba, lrbp);
2fff76f8 2827
300bb13f
JP		 2828 ufshcd_comp_scsi_upiu(hba, lrbp);
2829
75b1cc4a 2830 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2831 if (err) {
2832 lrbp->cmd = NULL;
17c7d35f 2833 ufshcd_release(hba);
7a3e97b0 2834 goto out;
5a0b0cb9 2835 }
7a3e97b0 2836
7a3e97b0 2837 ufshcd_send_command(hba, tag);
5675c381 2838
7a3e97b0 2839out:
5675c381
BVA		 2840 rcu_read_unlock();
2841
88b09900
AH		 2842 if (ufs_trigger_eh()) {
2843 unsigned long flags;
2844
2845 spin_lock_irqsave(hba->host->host_lock, flags);
2846 ufshcd_schedule_eh_work(hba);
2847 spin_unlock_irqrestore(hba->host->host_lock, flags);
2848 }
c11a1ae9 2849
7a3e97b0
SY		 2850 return err;
2851}
2852
5a0b0cb9
SRT		 2853static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2854 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2855{
2856 lrbp->cmd = NULL;
5a0b0cb9
SRT		 2857 lrbp->task_tag = tag;
2858 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9 2859 lrbp->intr_cmd = true; /* No interrupt aggregation */
df043c74 2860 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5a0b0cb9
SRT		 2861 hba->dev_cmd.type = cmd_type;
2862
f273c54b 2863 return ufshcd_compose_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2864}
2865
2866static int
2867ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2868{
2869 int err = 0;
2870 unsigned long flags;
2871 u32 mask = 1 << tag;
2872
2873 /* clear outstanding transaction before retry */
2874 spin_lock_irqsave(hba->host->host_lock, flags);
2875 ufshcd_utrl_clear(hba, tag);
2876 spin_unlock_irqrestore(hba->host->host_lock, flags);
2877
2878 /*
32424902 2879 * wait for h/w to clear corresponding bit in door-bell.
5a0b0cb9
SRT		 2880 * max. wait is 1 sec.
2881 */
2882 err = ufshcd_wait_for_register(hba,
2883 REG_UTP_TRANSFER_REQ_DOOR_BELL,
5cac1095 2884 mask, ~mask, 1000, 1000);
5a0b0cb9
SRT		 2885
2886 return err;
2887}
2888
c6d4a831
DR		 2889static int
2890ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2891{
2892 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2893
2894 /* Get the UPIU response */
2895 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2896 UPIU_RSP_CODE_OFFSET;
2897 return query_res->response;
2898}
2899
5a0b0cb9
SRT		 2900/**
2901 * ufshcd_dev_cmd_completion() - handles device management command responses
2902 * @hba: per adapter instance
2903 * @lrbp: pointer to local reference block
2904 */
2905static int
2906ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2907{
2908 int resp;
2909 int err = 0;
2910
ff8e20c6 2911 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2912 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2913
2914 switch (resp) {
2915 case UPIU_TRANSACTION_NOP_IN:
2916 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2917 err = -EINVAL;
2918 dev_err(hba->dev, "%s: unexpected response %x\n",
2919 __func__, resp);
2920 }
2921 break;
68078d5c 2922 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2923 err = ufshcd_check_query_response(hba, lrbp);
2924 if (!err)
2925 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2926 break;
5a0b0cb9
SRT		 2927 case UPIU_TRANSACTION_REJECT_UPIU:
2928 /* TODO: handle Reject UPIU Response */
2929 err = -EPERM;
2930 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2931 __func__);
2932 break;
2933 default:
2934 err = -EINVAL;
2935 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2936 __func__, resp);
2937 break;
2938 }
2939
2940 return err;
2941}
2942
2943static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2944 struct ufshcd_lrb *lrbp, int max_timeout)
2945{
2946 int err = 0;
2947 unsigned long time_left;
2948 unsigned long flags;
2949
2950 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2951 msecs_to_jiffies(max_timeout));
2952
2953 spin_lock_irqsave(hba->host->host_lock, flags);
2954 hba->dev_cmd.complete = NULL;
2955 if (likely(time_left)) {
2956 err = ufshcd_get_tr_ocs(lrbp);
2957 if (!err)
2958 err = ufshcd_dev_cmd_completion(hba, lrbp);
2959 }
2960 spin_unlock_irqrestore(hba->host->host_lock, flags);
2961
2962 if (!time_left) {
2963 err = -ETIMEDOUT;
a48353f6
YG		 2964 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2965 __func__, lrbp->task_tag);
5a0b0cb9 2966 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2967 /* successfully cleared the command, retry if needed */
5a0b0cb9 2968 err = -EAGAIN;
a48353f6
YG		 2969 /*
2970 * in case of an error, after clearing the doorbell,
2971 * we also need to clear the outstanding_request
2972 * field in hba
2973 */
169f5eb2
BVA		 2974 spin_lock_irqsave(&hba->outstanding_lock, flags);
2975 __clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2976 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5a0b0cb9
SRT		 2977 }
2978
2979 return err;
2980}
2981
5a0b0cb9
SRT		 2982/**
2983 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2984 * @hba: UFS hba
2985 * @cmd_type: specifies the type (NOP, Query...)
d0b2b70e 2986 * @timeout: timeout in milliseconds
5a0b0cb9 2987 *
68078d5c
DR		 2988 * NOTE: Since there is only one available tag for device management commands,
2989 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2990 */
2991static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2992 enum dev_cmd_type cmd_type, int timeout)
2993{
8a686f26 2994 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 2995 const u32 tag = hba->reserved_slot;
5a0b0cb9
SRT		 2996 struct ufshcd_lrb *lrbp;
2997 int err;
5a0b0cb9 2998
945c3cca
BVA		 2999 /* Protects use of hba->reserved_slot. */
3000 lockdep_assert_held(&hba->dev_cmd.lock);
a3cd5ec5 3001
945c3cca 3002 down_read(&hba->clk_scaling_lock);
5a0b0cb9 3003
a45f9371 3004 lrbp = &hba->lrb[tag];
5a0b0cb9
SRT		 3005 WARN_ON(lrbp->cmd);
3006 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3007 if (unlikely(err))
eb783bb8 3008 goto out;
5a0b0cb9
SRT		 3009
3010 hba->dev_cmd.complete = &wait;
3011
fb475b74 3012 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5a0b0cb9 3013
a45f9371 3014 ufshcd_send_command(hba, tag);
5a0b0cb9 3015 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
fb475b74
AA		 3016 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3017 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6667e6d9 3018
eb783bb8 3019out:
a3cd5ec5 3020 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 3021 return err;
3022}
3023
d44a5f98
DR		 3024/**
3025 * ufshcd_init_query() - init the query response and request parameters
3026 * @hba: per-adapter instance
3027 * @request: address of the request pointer to be initialized
3028 * @response: address of the response pointer to be initialized
3029 * @opcode: operation to perform
3030 * @idn: flag idn to access
3031 * @index: LU number to access
3032 * @selector: query/flag/descriptor further identification
3033 */
3034static inline void ufshcd_init_query(struct ufs_hba *hba,
3035 struct ufs_query_req **request, struct ufs_query_res **response,
3036 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3037{
3038 *request = &hba->dev_cmd.query.request;
3039 *response = &hba->dev_cmd.query.response;
3040 memset(*request, 0, sizeof(struct ufs_query_req));
3041 memset(*response, 0, sizeof(struct ufs_query_res));
3042 (*request)->upiu_req.opcode = opcode;
3043 (*request)->upiu_req.idn = idn;
3044 (*request)->upiu_req.index = index;
3045 (*request)->upiu_req.selector = selector;
3046}
3047
dc3c8d3a 3048static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1f34eedf 3049 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
dc3c8d3a
YG		 3050{
3051 int ret;
3052 int retries;
3053
3054 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1f34eedf 3055 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
dc3c8d3a
YG		 3056 if (ret)
3057 dev_dbg(hba->dev,
3058 "%s: failed with error %d, retries %d\n",
3059 __func__, ret, retries);
3060 else
3061 break;
3062 }
3063
3064 if (ret)
3065 dev_err(hba->dev,
3066 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3067 __func__, opcode, idn, ret, retries);
3068 return ret;
3069}
3070
68078d5c
DR		 3071/**
3072 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 3073 * @hba: per-adapter instance
3074 * @opcode: flag query to perform
3075 * @idn: flag idn to access
1f34eedf 3076 * @index: flag index to access
8aa29f19 3077 * @flag_res: the flag value after the query request completes
68078d5c
DR		 3078 *
3079 * Returns 0 for success, non-zero in case of failure
3080 */
dc3c8d3a 3081int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 3082 enum flag_idn idn, u8 index, bool *flag_res)
68078d5c 3083{
d44a5f98
DR		 3084 struct ufs_query_req *request = NULL;
3085 struct ufs_query_res *response = NULL;
1f34eedf 3086 int err, selector = 0;
e5ad406c 3087 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 3088
3089 BUG_ON(!hba);
3090
1ab27c9c 3091 ufshcd_hold(hba, false);
68078d5c 3092 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3093 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3094 selector);
68078d5c
DR		 3095
3096 switch (opcode) {
3097 case UPIU_QUERY_OPCODE_SET_FLAG:
3098 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3099 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3100 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3101 break;
3102 case UPIU_QUERY_OPCODE_READ_FLAG:
3103 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3104 if (!flag_res) {
3105 /* No dummy reads */
3106 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3107 __func__);
3108 err = -EINVAL;
3109 goto out_unlock;
3110 }
3111 break;
3112 default:
3113 dev_err(hba->dev,
3114 "%s: Expected query flag opcode but got = %d\n",
3115 __func__, opcode);
3116 err = -EINVAL;
3117 goto out_unlock;
3118 }
68078d5c 3119
e5ad406c 3120 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 3121
3122 if (err) {
3123 dev_err(hba->dev,
3124 "%s: Sending flag query for idn %d failed, err = %d\n",
3125 __func__, idn, err);
3126 goto out_unlock;
3127 }
3128
3129 if (flag_res)
e8c8e82a 3130 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 3131 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3132
3133out_unlock:
3134 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3135 ufshcd_release(hba);
68078d5c
DR		 3136 return err;
3137}
3138
66ec6d59
SRT		 3139/**
3140 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 3141 * @hba: per-adapter instance
3142 * @opcode: attribute opcode
3143 * @idn: attribute idn to access
3144 * @index: index field
3145 * @selector: selector field
3146 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 3147 *
3148 * Returns 0 for success, non-zero in case of failure
3149*/
ec92b59c
SN		 3150int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3151 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 3152{
d44a5f98
DR		 3153 struct ufs_query_req *request = NULL;
3154 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 3155 int err;
3156
3157 BUG_ON(!hba);
3158
3159 if (!attr_val) {
3160 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3161 __func__, opcode);
8ca1a40b 3162 return -EINVAL;
66ec6d59
SRT		 3163 }
3164
8ca1a40b 3165 ufshcd_hold(hba, false);
3166
66ec6d59 3167 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3168 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3169 selector);
66ec6d59
SRT		 3170
3171 switch (opcode) {
3172 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3173 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 3174 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 3175 break;
3176 case UPIU_QUERY_OPCODE_READ_ATTR:
3177 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3178 break;
3179 default:
3180 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3181 __func__, opcode);
3182 err = -EINVAL;
3183 goto out_unlock;
3184 }
3185
d44a5f98 3186 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 3187
3188 if (err) {
4b761b58
YG		 3189 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3190 __func__, opcode, idn, index, err);
66ec6d59
SRT		 3191 goto out_unlock;
3192 }
3193
e8c8e82a 3194 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 3195
3196out_unlock:
3197 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3198 ufshcd_release(hba);
66ec6d59
SRT		 3199 return err;
3200}
3201
5e86ae44
YG		 3202/**
3203 * ufshcd_query_attr_retry() - API function for sending query
3204 * attribute with retries
3205 * @hba: per-adapter instance
3206 * @opcode: attribute opcode
3207 * @idn: attribute idn to access
3208 * @index: index field
3209 * @selector: selector field
3210 * @attr_val: the attribute value after the query request
3211 * completes
3212 *
3213 * Returns 0 for success, non-zero in case of failure
3214*/
41d8a933 3215int ufshcd_query_attr_retry(struct ufs_hba *hba,
5e86ae44
YG		 3216 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3217 u32 *attr_val)
3218{
3219 int ret = 0;
3220 u32 retries;
3221
68c9fcfd 3222 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 3223 ret = ufshcd_query_attr(hba, opcode, idn, index,
3224 selector, attr_val);
3225 if (ret)
3226 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3227 __func__, ret, retries);
3228 else
3229 break;
3230 }
3231
3232 if (ret)
3233 dev_err(hba->dev,
3234 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3235 __func__, idn, ret, QUERY_REQ_RETRIES);
3236 return ret;
3237}
3238
a70e91b8 3239static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 3240 enum query_opcode opcode, enum desc_idn idn, u8 index,
3241 u8 selector, u8 *desc_buf, int *buf_len)
3242{
3243 struct ufs_query_req *request = NULL;
3244 struct ufs_query_res *response = NULL;
3245 int err;
3246
3247 BUG_ON(!hba);
3248
3249 if (!desc_buf) {
3250 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3251 __func__, opcode);
8ca1a40b 3252 return -EINVAL;
d44a5f98
DR		 3253 }
3254
a4b0e8a4 3255 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 3256 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3257 __func__, *buf_len);
8ca1a40b 3258 return -EINVAL;
d44a5f98
DR		 3259 }
3260
8ca1a40b 3261 ufshcd_hold(hba, false);
3262
d44a5f98
DR		 3263 mutex_lock(&hba->dev_cmd.lock);
3264 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3265 selector);
3266 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3267 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3268
3269 switch (opcode) {
3270 case UPIU_QUERY_OPCODE_WRITE_DESC:
3271 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3272 break;
3273 case UPIU_QUERY_OPCODE_READ_DESC:
3274 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3275 break;
3276 default:
3277 dev_err(hba->dev,
3278 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3279 __func__, opcode);
3280 err = -EINVAL;
3281 goto out_unlock;
3282 }
3283
3284 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3285
3286 if (err) {
4b761b58
YG		 3287 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3288 __func__, opcode, idn, index, err);
d44a5f98
DR		 3289 goto out_unlock;
3290 }
3291
ea2aab24 3292 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3293
3294out_unlock:
cfcbae38 3295 hba->dev_cmd.query.descriptor = NULL;
d44a5f98 3296 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3297 ufshcd_release(hba);
d44a5f98
DR		 3298 return err;
3299}
3300
a70e91b8 3301/**
8aa29f19
BVA		 3302 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3303 * @hba: per-adapter instance
3304 * @opcode: attribute opcode
3305 * @idn: attribute idn to access
3306 * @index: index field
3307 * @selector: selector field
3308 * @desc_buf: the buffer that contains the descriptor
3309 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3310 *
3311 * Returns 0 for success, non-zero in case of failure.
3312 * The buf_len parameter will contain, on return, the length parameter
3313 * received on the response.
3314 */
2238d31c
SN		 3315int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3316 enum query_opcode opcode,
3317 enum desc_idn idn, u8 index,
3318 u8 selector,
3319 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3320{
3321 int err;
3322 int retries;
3323
3324 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3325 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3326 selector, desc_buf, buf_len);
3327 if (!err || err == -EINVAL)
3328 break;
3329 }
3330
3331 return err;
3332}
a70e91b8 3333
a4b0e8a4
PM		 3334/**
3335 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3336 * @hba: Pointer to adapter instance
3337 * @desc_id: descriptor idn value
3338 * @desc_len: mapped desc length (out)
a4b0e8a4 3339 */
7a0bf85b
BH		 3340void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3341 int *desc_len)
a4b0e8a4 3342{
7a0bf85b
BH		 3343 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3344 desc_id == QUERY_DESC_IDN_RFU_1)
a4b0e8a4 3345 *desc_len = 0;
7a0bf85b
BH		 3346 else
3347 *desc_len = hba->desc_size[desc_id];
a4b0e8a4
PM		 3348}
3349EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3350
7a0bf85b 3351static void ufshcd_update_desc_length(struct ufs_hba *hba,
72fb690e 3352 enum desc_idn desc_id, int desc_index,
7a0bf85b
BH		 3353 unsigned char desc_len)
3354{
3355 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
72fb690e
BH		 3356 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3357 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3358 * than the RPMB unit, however, both descriptors share the same
3359 * desc_idn, to cover both unit descriptors with one length, we
3360 * choose the normal unit descriptor length by desc_index.
3361 */
7a0bf85b
BH		 3362 hba->desc_size[desc_id] = desc_len;
3363}
3364
da461cec
SJ		 3365/**
3366 * ufshcd_read_desc_param - read the specified descriptor parameter
3367 * @hba: Pointer to adapter instance
3368 * @desc_id: descriptor idn value
3369 * @desc_index: descriptor index
3370 * @param_offset: offset of the parameter to read
3371 * @param_read_buf: pointer to buffer where parameter would be read
3372 * @param_size: sizeof(param_read_buf)
3373 *
3374 * Return 0 in case of success, non-zero otherwise
3375 */
45bced87
SN		 3376int ufshcd_read_desc_param(struct ufs_hba *hba,
3377 enum desc_idn desc_id,
3378 int desc_index,
3379 u8 param_offset,
3380 u8 *param_read_buf,
3381 u8 param_size)
da461cec
SJ		 3382{
3383 int ret;
3384 u8 *desc_buf;
a4b0e8a4 3385 int buff_len;
da461cec
SJ		 3386 bool is_kmalloc = true;
3387
a4b0e8a4
PM		 3388 /* Safety check */
3389 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3390 return -EINVAL;
3391
7a0bf85b
BH		 3392 /* Get the length of descriptor */
3393 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3394 if (!buff_len) {
1699f980
CG		 3395 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3396 return -EINVAL;
3397 }
3398
3399 if (param_offset >= buff_len) {
3400 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3401 __func__, param_offset, desc_id, buff_len);
7a0bf85b 3402 return -EINVAL;
a4b0e8a4
PM		 3403 }
3404
3405 /* Check whether we need temp memory */
3406 if (param_offset != 0 || param_size < buff_len) {
1699f980 3407 desc_buf = kzalloc(buff_len, GFP_KERNEL);
da461cec
SJ		 3408 if (!desc_buf)
3409 return -ENOMEM;
a4b0e8a4
PM		 3410 } else {
3411 desc_buf = param_read_buf;
3412 is_kmalloc = false;
da461cec
SJ		 3413 }
3414
a4b0e8a4 3415 /* Request for full descriptor */
a70e91b8 3416 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3417 desc_id, desc_index, 0,
3418 desc_buf, &buff_len);
da461cec 3419
bde44bb6 3420 if (ret) {
1699f980 3421 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
bde44bb6 3422 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3423 goto out;
3424 }
3425
bde44bb6 3426 /* Sanity check */
3427 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1699f980 3428 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
bde44bb6 3429 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3430 ret = -EINVAL;
3431 goto out;
3432 }
3433
7a0bf85b
BH		 3434 /* Update descriptor length */
3435 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
72fb690e 3436 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
7a0bf85b 3437
1699f980
CG		 3438 if (is_kmalloc) {
3439 /* Make sure we don't copy more data than available */
d3d9c457
BVA		 3440 if (param_offset >= buff_len)
3441 ret = -EINVAL;
3442 else
3443 memcpy(param_read_buf, &desc_buf[param_offset],
3444 min_t(u32, param_size, buff_len - param_offset));
1699f980 3445 }
da461cec
SJ		 3446out:
3447 if (is_kmalloc)
3448 kfree(desc_buf);
3449 return ret;
3450}
3451
4b828fe1
TW		 3452/**
3453 * struct uc_string_id - unicode string
3454 *
3455 * @len: size of this descriptor inclusive
3456 * @type: descriptor type
3457 * @uc: unicode string character
3458 */
3459struct uc_string_id {
3460 u8 len;
3461 u8 type;
ec38c0ad 3462 wchar_t uc[];
4b828fe1
TW		 3463} __packed;
3464
3465/* replace non-printable or non-ASCII characters with spaces */
3466static inline char ufshcd_remove_non_printable(u8 ch)
3467{
3468 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3469}
3470
b573d484
YG		 3471/**
3472 * ufshcd_read_string_desc - read string descriptor
3473 * @hba: pointer to adapter instance
3474 * @desc_index: descriptor index
4b828fe1
TW		 3475 * @buf: pointer to buffer where descriptor would be read,
3476 * the caller should free the memory.
b573d484 3477 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3478 * null terminated string.
b573d484 3479 *
4b828fe1
TW		 3480 * Return:
3481 * * string size on success.
3482 * * -ENOMEM: on allocation failure
3483 * * -EINVAL: on a wrong parameter
b573d484 3484 */
4b828fe1
TW		 3485int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3486 u8 **buf, bool ascii)
b573d484 3487{
4b828fe1
TW		 3488 struct uc_string_id *uc_str;
3489 u8 *str;
3490 int ret;
b573d484 3491
4b828fe1
TW		 3492 if (!buf)
3493 return -EINVAL;
b573d484 3494
4b828fe1
TW		 3495 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3496 if (!uc_str)
3497 return -ENOMEM;
b573d484 3498
c4607a09
BH		 3499 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3500 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
4b828fe1
TW		 3501 if (ret < 0) {
3502 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3503 QUERY_REQ_RETRIES, ret);
3504 str = NULL;
3505 goto out;
3506 }
3507
3508 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3509 dev_dbg(hba->dev, "String Desc is of zero length\n");
3510 str = NULL;
3511 ret = 0;
b573d484
YG		 3512 goto out;
3513 }
3514
3515 if (ascii) {
4b828fe1 3516 ssize_t ascii_len;
b573d484 3517 int i;
b573d484 3518 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3519 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3520 str = kzalloc(ascii_len, GFP_KERNEL);
3521 if (!str) {
3522 ret = -ENOMEM;
fcbefc3b 3523 goto out;
b573d484
YG		 3524 }
3525
3526 /*
3527 * the descriptor contains string in UTF16 format
3528 * we need to convert to utf-8 so it can be displayed
3529 */
4b828fe1
TW		 3530 ret = utf16s_to_utf8s(uc_str->uc,
3531 uc_str->len - QUERY_DESC_HDR_SIZE,
3532 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3533
3534 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3535 for (i = 0; i < ret; i++)
3536 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3537
4b828fe1
TW		 3538 str[ret++] = '\0';
3539
3540 } else {
5f57704d 3541 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3542 if (!str) {
3543 ret = -ENOMEM;
3544 goto out;
3545 }
4b828fe1 3546 ret = uc_str->len;
b573d484
YG		 3547 }
3548out:
4b828fe1
TW		 3549 *buf = str;
3550 kfree(uc_str);
3551 return ret;
b573d484 3552}
b573d484 3553
da461cec
SJ		 3554/**
3555 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3556 * @hba: Pointer to adapter instance
3557 * @lun: lun id
3558 * @param_offset: offset of the parameter to read
3559 * @param_read_buf: pointer to buffer where parameter would be read
3560 * @param_size: sizeof(param_read_buf)
3561 *
3562 * Return 0 in case of success, non-zero otherwise
3563 */
3564static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3565 int lun,
3566 enum unit_desc_param param_offset,
3567 u8 *param_read_buf,
3568 u32 param_size)
3569{
3570 /*
3571 * Unit descriptors are only available for general purpose LUs (LUN id
3572 * from 0 to 7) and RPMB Well known LU.
3573 */
a2fca52e 3574 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
da461cec
SJ		 3575 return -EOPNOTSUPP;
3576
3577 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3578 param_offset, param_read_buf, param_size);
3579}
3580
09f17791
CG		 3581static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3582{
3583 int err = 0;
3584 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3585
3586 if (hba->dev_info.wspecversion >= 0x300) {
3587 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3588 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3589 &gating_wait);
3590 if (err)
3591 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3592 err, gating_wait);
3593
3594 if (gating_wait == 0) {
3595 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3596 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3597 gating_wait);
3598 }
3599
3600 hba->dev_info.clk_gating_wait_us = gating_wait;
3601 }
3602
3603 return err;
3604}
3605
7a3e97b0
SY		 3606/**
3607 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3608 * @hba: per adapter instance
3609 *
3610 * 1. Allocate DMA memory for Command Descriptor array
3611 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3612 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3613 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3614 * (UTMRDL)
3615 * 4. Allocate memory for local reference block(lrb).
3616 *
3617 * Returns 0 for success, non-zero in case of failure
3618 */
3619static int ufshcd_memory_alloc(struct ufs_hba *hba)
3620{
3621 size_t utmrdl_size, utrdl_size, ucdl_size;
3622
3623 /* Allocate memory for UTP command descriptors */
3624 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3625 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3626 ucdl_size,
3627 &hba->ucdl_dma_addr,
3628 GFP_KERNEL);
7a3e97b0
SY		 3629
3630 /*
3631 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3632 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3633 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3634 * be aligned to 128 bytes as well
3635 */
3636 if (!hba->ucdl_base_addr ||
3637 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3638 dev_err(hba->dev,
7a3e97b0
SY		 3639 "Command Descriptor Memory allocation failed\n");
3640 goto out;
3641 }
3642
3643 /*
3644 * Allocate memory for UTP Transfer descriptors
3645 * UFSHCI requires 1024 byte alignment of UTRD
3646 */
3647 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3648 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3649 utrdl_size,
3650 &hba->utrdl_dma_addr,
3651 GFP_KERNEL);
7a3e97b0
SY		 3652 if (!hba->utrdl_base_addr ||
3653 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3654 dev_err(hba->dev,
7a3e97b0
SY		 3655 "Transfer Descriptor Memory allocation failed\n");
3656 goto out;
3657 }
3658
3659 /*
3660 * Allocate memory for UTP Task Management descriptors
3661 * UFSHCI requires 1024 byte alignment of UTMRD
3662 */
3663 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3664 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3665 utmrdl_size,
3666 &hba->utmrdl_dma_addr,
3667 GFP_KERNEL);
7a3e97b0
SY		 3668 if (!hba->utmrdl_base_addr ||
3669 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3670 dev_err(hba->dev,
7a3e97b0
SY		 3671 "Task Management Descriptor Memory allocation failed\n");
3672 goto out;
3673 }
3674
3675 /* Allocate memory for local reference block */
a86854d0
KC		 3676 hba->lrb = devm_kcalloc(hba->dev,
3677 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3678 GFP_KERNEL);
7a3e97b0 3679 if (!hba->lrb) {
3b1d0580 3680 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3681 goto out;
3682 }
3683 return 0;
3684out:
7a3e97b0
SY		 3685 return -ENOMEM;
3686}
3687
3688/**
3689 * ufshcd_host_memory_configure - configure local reference block with
3690 * memory offsets
3691 * @hba: per adapter instance
3692 *
3693 * Configure Host memory space
3694 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3695 * address.
3696 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3697 * and PRDT offset.
3698 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3699 * into local reference block.
3700 */
3701static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3702{
7a3e97b0
SY		 3703 struct utp_transfer_req_desc *utrdlp;
3704 dma_addr_t cmd_desc_dma_addr;
3705 dma_addr_t cmd_desc_element_addr;
3706 u16 response_offset;
3707 u16 prdt_offset;
3708 int cmd_desc_size;
3709 int i;
3710
3711 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3712
3713 response_offset =
3714 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3715 prdt_offset =
3716 offsetof(struct utp_transfer_cmd_desc, prd_table);
3717
3718 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3719 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3720
3721 for (i = 0; i < hba->nutrs; i++) {
3722 /* Configure UTRD with command descriptor base address */
3723 cmd_desc_element_addr =
3724 (cmd_desc_dma_addr + (cmd_desc_size * i));
3725 utrdlp[i].command_desc_base_addr_lo =
3726 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3727 utrdlp[i].command_desc_base_addr_hi =
3728 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3729
3730 /* Response upiu and prdt offset should be in double words */
26f968d7
AA		 3731 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3732 utrdlp[i].response_upiu_offset =
3733 cpu_to_le16(response_offset);
3734 utrdlp[i].prd_table_offset =
3735 cpu_to_le16(prdt_offset);
3736 utrdlp[i].response_upiu_length =
3737 cpu_to_le16(ALIGNED_UPIU_SIZE);
3738 } else {
3739 utrdlp[i].response_upiu_offset =
3740 cpu_to_le16(response_offset >> 2);
3741 utrdlp[i].prd_table_offset =
3742 cpu_to_le16(prdt_offset >> 2);
3743 utrdlp[i].response_upiu_length =
3744 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3745 }
7a3e97b0 3746
4d2b8d40 3747 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3748 }
3749}
3750
3751/**
3752 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3753 * @hba: per adapter instance
3754 *
3755 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3756 * in order to initialize the Unipro link startup procedure.
3757 * Once the Unipro links are up, the device connected to the controller
3758 * is detected.
3759 *
3760 * Returns 0 on success, non-zero value on failure
3761 */
3762static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3763{
6ccf44fe
SJ		 3764 struct uic_command uic_cmd = {0};
3765 int ret;
7a3e97b0 3766
6ccf44fe 3767 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3768
6ccf44fe
SJ		 3769 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3770 if (ret)
ff8e20c6 3771 dev_dbg(hba->dev,
6ccf44fe
SJ		 3772 "dme-link-startup: error code %d\n", ret);
3773 return ret;
7a3e97b0 3774}
39bf2d83
AA		 3775/**
3776 * ufshcd_dme_reset - UIC command for DME_RESET
3777 * @hba: per adapter instance
3778 *
3779 * DME_RESET command is issued in order to reset UniPro stack.
3780 * This function now deals with cold reset.
3781 *
3782 * Returns 0 on success, non-zero value on failure
3783 */
3784static int ufshcd_dme_reset(struct ufs_hba *hba)
3785{
3786 struct uic_command uic_cmd = {0};
3787 int ret;
3788
3789 uic_cmd.command = UIC_CMD_DME_RESET;
3790
3791 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3792 if (ret)
3793 dev_err(hba->dev,
3794 "dme-reset: error code %d\n", ret);
3795
3796 return ret;
3797}
3798
fc85a74e
SC		 3799int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3800 int agreed_gear,
3801 int adapt_val)
3802{
3803 int ret;
3804
3805 if (agreed_gear != UFS_HS_G4)
66df79cc 3806 adapt_val = PA_NO_ADAPT;
fc85a74e
SC		 3807
3808 ret = ufshcd_dme_set(hba,
3809 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3810 adapt_val);
3811 return ret;
3812}
3813EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3814
39bf2d83
AA		 3815/**
3816 * ufshcd_dme_enable - UIC command for DME_ENABLE
3817 * @hba: per adapter instance
3818 *
3819 * DME_ENABLE command is issued in order to enable UniPro stack.
3820 *
3821 * Returns 0 on success, non-zero value on failure
3822 */
3823static int ufshcd_dme_enable(struct ufs_hba *hba)
3824{
3825 struct uic_command uic_cmd = {0};
3826 int ret;
3827
3828 uic_cmd.command = UIC_CMD_DME_ENABLE;
3829
3830 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3831 if (ret)
3832 dev_err(hba->dev,
1fa05700 3833 "dme-enable: error code %d\n", ret);
39bf2d83
AA		 3834
3835 return ret;
3836}
7a3e97b0 3837
cad2e03d
YG		 3838static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3839{
3840 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3841 unsigned long min_sleep_time_us;
3842
3843 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3844 return;
3845
3846 /*
3847 * last_dme_cmd_tstamp will be 0 only for 1st call to
3848 * this function
3849 */
3850 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3851 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3852 } else {
3853 unsigned long delta =
3854 (unsigned long) ktime_to_us(
3855 ktime_sub(ktime_get(),
3856 hba->last_dme_cmd_tstamp));
3857
3858 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3859 min_sleep_time_us =
3860 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3861 else
3862 return; /* no more delay required */
3863 }
3864
3865 /* allow sleep for extra 50us if needed */
3866 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3867}
3868
12b4fdb4
SJ		 3869/**
3870 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3871 * @hba: per adapter instance
3872 * @attr_sel: uic command argument1
3873 * @attr_set: attribute set type as uic command argument2
3874 * @mib_val: setting value as uic command argument3
3875 * @peer: indicate whether peer or local
3876 *
3877 * Returns 0 on success, non-zero value on failure
3878 */
3879int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3880 u8 attr_set, u32 mib_val, u8 peer)
3881{
3882 struct uic_command uic_cmd = {0};
3883 static const char *const action[] = {
3884 "dme-set",
3885 "dme-peer-set"
3886 };
3887 const char *set = action[!!peer];
3888 int ret;
64238fbd 3889 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3890
3891 uic_cmd.command = peer ?
3892 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3893 uic_cmd.argument1 = attr_sel;
3894 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3895 uic_cmd.argument3 = mib_val;
3896
64238fbd
YG		 3897 do {
3898 /* for peer attributes we retry upon failure */
3899 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3900 if (ret)
3901 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3902 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3903 } while (ret && peer && --retries);
3904
f37e9f8c 3905 if (ret)
64238fbd 3906 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3907 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3908 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3909
3910 return ret;
3911}
3912EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3913
3914/**
3915 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3916 * @hba: per adapter instance
3917 * @attr_sel: uic command argument1
3918 * @mib_val: the value of the attribute as returned by the UIC command
3919 * @peer: indicate whether peer or local
3920 *
3921 * Returns 0 on success, non-zero value on failure
3922 */
3923int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3924 u32 *mib_val, u8 peer)
3925{
3926 struct uic_command uic_cmd = {0};
3927 static const char *const action[] = {
3928 "dme-get",
3929 "dme-peer-get"
3930 };
3931 const char *get = action[!!peer];
3932 int ret;
64238fbd 3933 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3934 struct ufs_pa_layer_attr orig_pwr_info;
3935 struct ufs_pa_layer_attr temp_pwr_info;
3936 bool pwr_mode_change = false;
3937
3938 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3939 orig_pwr_info = hba->pwr_info;
3940 temp_pwr_info = orig_pwr_info;
3941
3942 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3943 orig_pwr_info.pwr_rx == FAST_MODE) {
3944 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3945 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3946 pwr_mode_change = true;
3947 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3948 orig_pwr_info.pwr_rx == SLOW_MODE) {
3949 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3950 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3951 pwr_mode_change = true;
3952 }
3953 if (pwr_mode_change) {
3954 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3955 if (ret)
3956 goto out;
3957 }
3958 }
12b4fdb4
SJ		 3959
3960 uic_cmd.command = peer ?
3961 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3962 uic_cmd.argument1 = attr_sel;
3963
64238fbd
YG		 3964 do {
3965 /* for peer attributes we retry upon failure */
3966 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3967 if (ret)
3968 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3969 get, UIC_GET_ATTR_ID(attr_sel), ret);
3970 } while (ret && peer && --retries);
3971
f37e9f8c 3972 if (ret)
64238fbd 3973 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3974 get, UIC_GET_ATTR_ID(attr_sel),
3975 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3976
64238fbd 3977 if (mib_val && !ret)
12b4fdb4 3978 *mib_val = uic_cmd.argument3;
874237f7
YG		 3979
3980 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3981 && pwr_mode_change)
3982 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3983out:
3984 return ret;
3985}
3986EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3987
53b3d9c3 3988/**
57d104c1
SJ		 3989 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3990 * state) and waits for it to take effect.
3991 *
53b3d9c3 3992 * @hba: per adapter instance
57d104c1
SJ		 3993 * @cmd: UIC command to execute
3994 *
3995 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3996 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3997 * and device UniPro link and hence it's final completion would be indicated by
3998 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3999 * addition to normal UIC command completion Status (UCCS). This function only
4000 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 4001 *
4002 * Returns 0 on success, non-zero value on failure
4003 */
57d104c1 4004static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 4005{
8a686f26 4006 DECLARE_COMPLETION_ONSTACK(uic_async_done);
53b3d9c3
SJ		 4007 unsigned long flags;
4008 u8 status;
4009 int ret;
d75f7fe4 4010 bool reenable_intr = false;
53b3d9c3 4011
53b3d9c3 4012 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d 4013 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 4014
4015 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236
CG		 4016 if (ufshcd_is_link_broken(hba)) {
4017 ret = -ENOLINK;
4018 goto out_unlock;
4019 }
57d104c1 4020 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 4021 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4022 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4023 /*
4024 * Make sure UIC command completion interrupt is disabled before
4025 * issuing UIC command.
4026 */
4027 wmb();
4028 reenable_intr = true;
57d104c1 4029 }
d75f7fe4
YG		 4030 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4031 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 4032 if (ret) {
4033 dev_err(hba->dev,
4034 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4035 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 4036 goto out;
4037 }
4038
57d104c1 4039 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 4040 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4041 dev_err(hba->dev,
57d104c1
SJ		 4042 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4043 cmd->command, cmd->argument3);
0f52fcb9
CG		 4044
4045 if (!cmd->cmd_active) {
4046 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4047 __func__);
4048 goto check_upmcrs;
4049 }
4050
53b3d9c3
SJ		 4051 ret = -ETIMEDOUT;
4052 goto out;
4053 }
4054
0f52fcb9 4055check_upmcrs:
53b3d9c3
SJ		 4056 status = ufshcd_get_upmcrs(hba);
4057 if (status != PWR_LOCAL) {
4058 dev_err(hba->dev,
479da360 4059 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 4060 cmd->command, status);
53b3d9c3
SJ		 4061 ret = (status != PWR_OK) ? status : -1;
4062 }
4063out:
7942f7b5
VG		 4064 if (ret) {
4065 ufshcd_print_host_state(hba);
4066 ufshcd_print_pwr_info(hba);
e965e5e0 4067 ufshcd_print_evt_hist(hba);
7942f7b5
VG		 4068 }
4069
53b3d9c3 4070 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 4071 hba->active_uic_cmd = NULL;
57d104c1 4072 hba->uic_async_done = NULL;
d75f7fe4
YG		 4073 if (reenable_intr)
4074 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4db7a236
CG		 4075 if (ret) {
4076 ufshcd_set_link_broken(hba);
88b09900 4077 ufshcd_schedule_eh_work(hba);
4db7a236
CG		 4078 }
4079out_unlock:
53b3d9c3
SJ		 4080 spin_unlock_irqrestore(hba->host->host_lock, flags);
4081 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 4082
53b3d9c3
SJ		 4083 return ret;
4084}
4085
57d104c1
SJ		 4086/**
4087 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4088 * using DME_SET primitives.
4089 * @hba: per adapter instance
4090 * @mode: powr mode value
4091 *
4092 * Returns 0 on success, non-zero value on failure
4093 */
4094static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4095{
4096 struct uic_command uic_cmd = {0};
1ab27c9c 4097 int ret;
57d104c1 4098
c3a2f9ee
YG		 4099 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4100 ret = ufshcd_dme_set(hba,
4101 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4102 if (ret) {
4103 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4104 __func__, ret);
4105 goto out;
4106 }
4107 }
4108
57d104c1
SJ		 4109 uic_cmd.command = UIC_CMD_DME_SET;
4110 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4111 uic_cmd.argument3 = mode;
1ab27c9c
ST		 4112 ufshcd_hold(hba, false);
4113 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4114 ufshcd_release(hba);
57d104c1 4115
c3a2f9ee 4116out:
1ab27c9c 4117 return ret;
57d104c1
SJ		 4118}
4119
087c5efa 4120int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 4121{
4122 int ret;
4123 unsigned long flags;
4124
4125 spin_lock_irqsave(hba->host->host_lock, flags);
4126 hba->ufshcd_state = UFSHCD_STATE_RESET;
4127 ufshcd_set_eh_in_progress(hba);
4128 spin_unlock_irqrestore(hba->host->host_lock, flags);
4129
ebdd1dfd 4130 /* Reset the attached device */
31a5d9ca 4131 ufshcd_device_reset(hba);
ebdd1dfd 4132
53c12d0e
YG		 4133 ret = ufshcd_host_reset_and_restore(hba);
4134
4135 spin_lock_irqsave(hba->host->host_lock, flags);
4136 if (ret)
4137 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4138 ufshcd_clear_eh_in_progress(hba);
4139 spin_unlock_irqrestore(hba->host->host_lock, flags);
4140
4141 if (ret)
4142 dev_err(hba->dev, "%s: link recovery failed, err %d",
4143 __func__, ret);
4144
4145 return ret;
4146}
087c5efa 4147EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 4148
525943a5 4149int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 4150{
87d0b4a6 4151 int ret;
57d104c1 4152 struct uic_command uic_cmd = {0};
911a0771 4153 ktime_t start = ktime_get();
57d104c1 4154
ee32c909
KK		 4155 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4156
57d104c1 4157 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 4158 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4159 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4160 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 4161
4db7a236 4162 if (ret)
87d0b4a6
YG		 4163 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4164 __func__, ret);
4db7a236 4165 else
ee32c909
KK		 4166 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4167 POST_CHANGE);
53c12d0e 4168
87d0b4a6
YG		 4169 return ret;
4170}
525943a5 4171EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
87d0b4a6 4172
9d19bf7a 4173int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 4174{
4175 struct uic_command uic_cmd = {0};
4176 int ret;
911a0771 4177 ktime_t start = ktime_get();
57d104c1 4178
ee32c909
KK		 4179 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4180
57d104c1
SJ		 4181 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4182 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4183 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4184 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4185
57d104c1 4186 if (ret) {
53c12d0e
YG		 4187 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4188 __func__, ret);
ff8e20c6 4189 } else {
ee32c909
KK		 4190 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4191 POST_CHANGE);
ff8e20c6
DR		 4192 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4193 hba->ufs_stats.hibern8_exit_cnt++;
4194 }
57d104c1
SJ		 4195
4196 return ret;
4197}
9d19bf7a 4198EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 4199
ba7af5ec
SC		 4200void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4201{
4202 unsigned long flags;
be7594a4 4203 bool update = false;
ba7af5ec 4204
be7594a4 4205 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 4206 return;
4207
4208 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 4209 if (hba->ahit != ahit) {
4210 hba->ahit = ahit;
4211 update = true;
4212 }
ba7af5ec 4213 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4 4214
b294ff3e 4215 if (update &&
e2106584 4216 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
b294ff3e 4217 ufshcd_rpm_get_sync(hba);
be7594a4
CG		 4218 ufshcd_hold(hba, false);
4219 ufshcd_auto_hibern8_enable(hba);
4220 ufshcd_release(hba);
b294ff3e 4221 ufshcd_rpm_put_sync(hba);
be7594a4 4222 }
ba7af5ec
SC		 4223}
4224EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4225
71d848b8 4226void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378 4227{
499f7a96 4228 if (!ufshcd_is_auto_hibern8_supported(hba))
ad448378
AH		 4229 return;
4230
ad448378 4231 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
ad448378
AH		 4232}
4233
5064636c
YG		 4234 /**
4235 * ufshcd_init_pwr_info - setting the POR (power on reset)
4236 * values in hba power info
4237 * @hba: per-adapter instance
4238 */
4239static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4240{
4241 hba->pwr_info.gear_rx = UFS_PWM_G1;
4242 hba->pwr_info.gear_tx = UFS_PWM_G1;
4243 hba->pwr_info.lane_rx = 1;
4244 hba->pwr_info.lane_tx = 1;
4245 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4246 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4247 hba->pwr_info.hs_rate = 0;
4248}
4249
d3e89bac 4250/**
7eb584db
DR		 4251 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4252 * @hba: per-adapter instance
d3e89bac 4253 */
7eb584db 4254static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 4255{
7eb584db
DR		 4256 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4257
4258 if (hba->max_pwr_info.is_valid)
4259 return 0;
4260
2349b533 4261 pwr_info->pwr_tx = FAST_MODE;
4262 pwr_info->pwr_rx = FAST_MODE;
7eb584db 4263 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4264
4265 /* Get the connected lane count */
7eb584db
DR		 4266 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4267 &pwr_info->lane_rx);
4268 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4269 &pwr_info->lane_tx);
4270
4271 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4272 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4273 __func__,
4274 pwr_info->lane_rx,
4275 pwr_info->lane_tx);
4276 return -EINVAL;
4277 }
d3e89bac
SJ		 4278
4279 /*
4280 * First, get the maximum gears of HS speed.
4281 * If a zero value, it means there is no HSGEAR capability.
4282 * Then, get the maximum gears of PWM speed.
4283 */
7eb584db
DR		 4284 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4285 if (!pwr_info->gear_rx) {
4286 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4287 &pwr_info->gear_rx);
4288 if (!pwr_info->gear_rx) {
4289 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4290 __func__, pwr_info->gear_rx);
4291 return -EINVAL;
4292 }
2349b533 4293 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4294 }
4295
7eb584db
DR		 4296 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4297 &pwr_info->gear_tx);
4298 if (!pwr_info->gear_tx) {
d3e89bac 4299 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4300 &pwr_info->gear_tx);
4301 if (!pwr_info->gear_tx) {
4302 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4303 __func__, pwr_info->gear_tx);
4304 return -EINVAL;
4305 }
2349b533 4306 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4307 }
4308
4309 hba->max_pwr_info.is_valid = true;
4310 return 0;
4311}
4312
4313static int ufshcd_change_power_mode(struct ufs_hba *hba,
4314 struct ufs_pa_layer_attr *pwr_mode)
4315{
4316 int ret;
4317
4318 /* if already configured to the requested pwr_mode */
2355b66e
CG		 4319 if (!hba->force_pmc &&
4320 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
7eb584db
DR		 4321 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4322 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4323 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4324 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4325 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4326 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4327 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4328 return 0;
d3e89bac
SJ		 4329 }
4330
4331 /*
4332 * Configure attributes for power mode change with below.
4333 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4334 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4335 * - PA_HSSERIES
4336 */
7eb584db
DR		 4337 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4339 pwr_mode->lane_rx);
4340 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4341 pwr_mode->pwr_rx == FAST_MODE)
21c2e341 4342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
7eb584db 4343 else
21c2e341 4344 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
d3e89bac 4345
7eb584db
DR		 4346 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4347 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4348 pwr_mode->lane_tx);
4349 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4350 pwr_mode->pwr_tx == FAST_MODE)
21c2e341 4351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
7eb584db 4352 else
21c2e341 4353 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
d3e89bac 4354
7eb584db
DR		 4355 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4356 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4357 pwr_mode->pwr_rx == FAST_MODE ||
4358 pwr_mode->pwr_tx == FAST_MODE)
4359 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4360 pwr_mode->hs_rate);
d3e89bac 4361
b1d0d2eb
KK		 4362 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4363 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4364 DL_FC0ProtectionTimeOutVal_Default);
4365 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4366 DL_TC0ReplayTimeOutVal_Default);
4367 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4368 DL_AFC0ReqTimeOutVal_Default);
4369 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4370 DL_FC1ProtectionTimeOutVal_Default);
4371 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4372 DL_TC1ReplayTimeOutVal_Default);
4373 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4374 DL_AFC1ReqTimeOutVal_Default);
4375
4376 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4377 DL_FC0ProtectionTimeOutVal_Default);
4378 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4379 DL_TC0ReplayTimeOutVal_Default);
4380 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4381 DL_AFC0ReqTimeOutVal_Default);
4382 }
08342537 4383
7eb584db
DR		 4384 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4385 | pwr_mode->pwr_tx);
4386
4387 if (ret) {
d3e89bac 4388 dev_err(hba->dev,
7eb584db
DR		 4389 "%s: power mode change failed %d\n", __func__, ret);
4390 } else {
0263bcd0
YG		 4391 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4392 pwr_mode);
7eb584db
DR		 4393
4394 memcpy(&hba->pwr_info, pwr_mode,
4395 sizeof(struct ufs_pa_layer_attr));
4396 }
4397
4398 return ret;
4399}
4400
4401/**
4402 * ufshcd_config_pwr_mode - configure a new power mode
4403 * @hba: per-adapter instance
4404 * @desired_pwr_mode: desired power configuration
4405 */
0d846e70 4406int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4407 struct ufs_pa_layer_attr *desired_pwr_mode)
4408{
4409 struct ufs_pa_layer_attr final_params = { 0 };
4410 int ret;
4411
0263bcd0
YG		 4412 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4413 desired_pwr_mode, &final_params);
4414
4415 if (ret)
7eb584db
DR		 4416 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4417
4418 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4419
4420 return ret;
4421}
0d846e70 4422EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4423
68078d5c
DR		 4424/**
4425 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4426 * @hba: per-adapter instance
68078d5c
DR		 4427 *
4428 * Set fDeviceInit flag and poll until device toggles it.
4429 */
4430static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4431{
dc3c8d3a 4432 int err;
7dfdcc39 4433 bool flag_res = true;
29707fab 4434 ktime_t timeout;
68078d5c 4435
dc3c8d3a 4436 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4437 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
68078d5c
DR		 4438 if (err) {
4439 dev_err(hba->dev,
4440 "%s setting fDeviceInit flag failed with error %d\n",
4441 __func__, err);
4442 goto out;
4443 }
4444
29707fab
KK		 4445 /* Poll fDeviceInit flag to be cleared */
4446 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4447 do {
4448 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4449 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4450 if (!flag_res)
4451 break;
a4e6496f 4452 usleep_range(500, 1000);
29707fab 4453 } while (ktime_before(ktime_get(), timeout));
dc3c8d3a 4454
29707fab 4455 if (err) {
68078d5c 4456 dev_err(hba->dev,
29707fab
KK		 4457 "%s reading fDeviceInit flag failed with error %d\n",
4458 __func__, err);
4459 } else if (flag_res) {
68078d5c 4460 dev_err(hba->dev,
29707fab
KK		 4461 "%s fDeviceInit was not cleared by the device\n",
4462 __func__);
4463 err = -EBUSY;
4464 }
68078d5c
DR		 4465out:
4466 return err;
4467}
4468
7a3e97b0
SY		 4469/**
4470 * ufshcd_make_hba_operational - Make UFS controller operational
4471 * @hba: per adapter instance
4472 *
4473 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4474 * 1. Enable required interrupts
4475 * 2. Configure interrupt aggregation
897efe62 4476 * 3. Program UTRL and UTMRL base address
5c0c28a8 4477 * 4. Configure run-stop-registers
7a3e97b0
SY		 4478 *
4479 * Returns 0 on success, non-zero value on failure
4480 */
9d19bf7a 4481int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4482{
4483 int err = 0;
4484 u32 reg;
4485
6ccf44fe
SJ		 4486 /* Enable required interrupts */
4487 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4488
4489 /* Configure interrupt aggregation */
b852190e
YG		 4490 if (ufshcd_is_intr_aggr_allowed(hba))
4491 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4492 else
4493 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4494
4495 /* Configure UTRL and UTMRL base address registers */
4496 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4497 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4498 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4499 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4500 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4501 REG_UTP_TASK_REQ_LIST_BASE_L);
4502 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4503 REG_UTP_TASK_REQ_LIST_BASE_H);
4504
897efe62
YG		 4505 /*
4506 * Make sure base address and interrupt setup are updated before
4507 * enabling the run/stop registers below.
4508 */
4509 wmb();
4510
7a3e97b0
SY		 4511 /*
4512 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4513 */
5c0c28a8 4514 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4515 if (!(ufshcd_get_lists_status(reg))) {
4516 ufshcd_enable_run_stop_reg(hba);
4517 } else {
3b1d0580 4518 dev_err(hba->dev,
7a3e97b0
SY		 4519 "Host controller not ready to process requests");
4520 err = -EIO;
7a3e97b0
SY		 4521 }
4522
7a3e97b0
SY		 4523 return err;
4524}
9d19bf7a 4525EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4526
596585a2
YG		 4527/**
4528 * ufshcd_hba_stop - Send controller to reset state
4529 * @hba: per adapter instance
596585a2 4530 */
3a95f5b3 4531void ufshcd_hba_stop(struct ufs_hba *hba)
596585a2 4532{
5cac1095 4533 unsigned long flags;
596585a2
YG		 4534 int err;
4535
5cac1095
BVA		 4536 /*
4537 * Obtain the host lock to prevent that the controller is disabled
4538 * while the UFS interrupt handler is active on another CPU.
4539 */
4540 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4541 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
5cac1095
BVA		 4542 spin_unlock_irqrestore(hba->host->host_lock, flags);
4543
596585a2
YG		 4544 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4545 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
5cac1095 4546 10, 1);
596585a2
YG		 4547 if (err)
4548 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4549}
3a95f5b3 4550EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
596585a2 4551
7a3e97b0 4552/**
39bf2d83 4553 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4554 * @hba: per adapter instance
4555 *
4556 * The controller resets itself and controller firmware initialization
4557 * sequence kicks off. When controller is ready it will set
4558 * the Host Controller Enable bit to 1.
4559 *
4560 * Returns 0 on success, non-zero value on failure
4561 */
39bf2d83 4562static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0 4563{
6081b12c
SC		 4564 int retry_outer = 3;
4565 int retry_inner;
7a3e97b0 4566
6081b12c 4567start:
acbbfe48 4568 if (ufshcd_is_hba_active(hba))
7a3e97b0 4569 /* change controller state to "reset state" */
5cac1095 4570 ufshcd_hba_stop(hba);
7a3e97b0 4571
57d104c1
SJ		 4572 /* UniPro link is disabled at this point */
4573 ufshcd_set_link_off(hba);
4574
0263bcd0 4575 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4576
7a3e97b0
SY		 4577 /* start controller initialization sequence */
4578 ufshcd_hba_start(hba);
4579
4580 /*
4581 * To initialize a UFS host controller HCE bit must be set to 1.
4582 * During initialization the HCE bit value changes from 1->0->1.
4583 * When the host controller completes initialization sequence
4584 * it sets the value of HCE bit to 1. The same HCE bit is read back
4585 * to check if the controller has completed initialization sequence.
4586 * So without this delay the value HCE = 1, set in the previous
4587 * instruction might be read back.
4588 * This delay can be changed based on the controller.
4589 */
90b8491c 4590 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
7a3e97b0
SY		 4591
4592 /* wait for the host controller to complete initialization */
6081b12c 4593 retry_inner = 50;
acbbfe48 4594 while (!ufshcd_is_hba_active(hba)) {
6081b12c
SC		 4595 if (retry_inner) {
4596 retry_inner--;
7a3e97b0 4597 } else {
3b1d0580 4598 dev_err(hba->dev,
7a3e97b0 4599 "Controller enable failed\n");
6081b12c
SC		 4600 if (retry_outer) {
4601 retry_outer--;
4602 goto start;
4603 }
7a3e97b0
SY		 4604 return -EIO;
4605 }
9fc305ef 4606 usleep_range(1000, 1100);
7a3e97b0 4607 }
5c0c28a8 4608
1d337ec2 4609 /* enable UIC related interrupts */
57d104c1 4610 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4611
0263bcd0 4612 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4613
7a3e97b0
SY		 4614 return 0;
4615}
39bf2d83
AA		 4616
4617int ufshcd_hba_enable(struct ufs_hba *hba)
4618{
4619 int ret;
4620
4621 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4622 ufshcd_set_link_off(hba);
4623 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4624
4625 /* enable UIC related interrupts */
4626 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4627 ret = ufshcd_dme_reset(hba);
4628 if (!ret) {
4629 ret = ufshcd_dme_enable(hba);
4630 if (!ret)
4631 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4632 if (ret)
4633 dev_err(hba->dev,
4634 "Host controller enable failed with non-hce\n");
4635 }
4636 } else {
4637 ret = ufshcd_hba_execute_hce(hba);
4638 }
4639
4640 return ret;
4641}
9d19bf7a
SC		 4642EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4643
7ca38cf3
YG		 4644static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4645{
ba0320fb 4646 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4647
4648 if (!peer)
4649 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4650 &tx_lanes);
4651 else
4652 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4653 &tx_lanes);
4654 for (i = 0; i < tx_lanes; i++) {
4655 if (!peer)
4656 err = ufshcd_dme_set(hba,
4657 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4658 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4659 0);
4660 else
4661 err = ufshcd_dme_peer_set(hba,
4662 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4663 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4664 0);
4665 if (err) {
4666 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4667 __func__, peer, i, err);
4668 break;
4669 }
4670 }
4671
4672 return err;
4673}
4674
4675static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4676{
4677 return ufshcd_disable_tx_lcc(hba, true);
4678}
4679
e965e5e0 4680void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
8808b4e9 4681{
e965e5e0
SC		 4682 struct ufs_event_hist *e;
4683
4684 if (id >= UFS_EVT_CNT)
4685 return;
4686
4687 e = &hba->ufs_stats.event[id];
4688 e->val[e->pos] = val;
4689 e->tstamp[e->pos] = ktime_get();
b6cacaf2 4690 e->cnt += 1;
e965e5e0 4691 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
172614a9
SC		 4692
4693 ufshcd_vops_event_notify(hba, id, &val);
8808b4e9 4694}
e965e5e0 4695EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
8808b4e9 4696
7a3e97b0 4697/**
6ccf44fe 4698 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4699 * @hba: per adapter instance
4700 *
6ccf44fe 4701 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4702 */
6ccf44fe 4703static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4704{
6ccf44fe 4705 int ret;
1d337ec2 4706 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4707 bool link_startup_again = false;
7a3e97b0 4708
7caf489b 4709 /*
4710 * If UFS device isn't active then we will have to issue link startup
4711 * 2 times to make sure the device state move to active.
4712 */
4713 if (!ufshcd_is_ufs_dev_active(hba))
4714 link_startup_again = true;
7a3e97b0 4715
7caf489b 4716link_startup:
1d337ec2 4717 do {
0263bcd0 4718 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4719
1d337ec2 4720 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4721
1d337ec2
SRT		 4722 /* check if device is detected by inter-connect layer */
4723 if (!ret && !ufshcd_is_device_present(hba)) {
e965e5e0
SC		 4724 ufshcd_update_evt_hist(hba,
4725 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4726 0);
1d337ec2
SRT		 4727 dev_err(hba->dev, "%s: Device not present\n", __func__);
4728 ret = -ENXIO;
4729 goto out;
4730 }
6ccf44fe 4731
1d337ec2
SRT		 4732 /*
4733 * DME link lost indication is only received when link is up,
4734 * but we can't be sure if the link is up until link startup
4735 * succeeds. So reset the local Uni-Pro and try again.
4736 */
8808b4e9 4737 if (ret && ufshcd_hba_enable(hba)) {
e965e5e0
SC		 4738 ufshcd_update_evt_hist(hba,
4739 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4740 (u32)ret);
1d337ec2 4741 goto out;
8808b4e9 4742 }
1d337ec2
SRT		 4743 } while (ret && retries--);
4744
8808b4e9 4745 if (ret) {
1d337ec2 4746 /* failed to get the link up... retire */
e965e5e0
SC		 4747 ufshcd_update_evt_hist(hba,
4748 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4749 (u32)ret);
5c0c28a8 4750 goto out;
8808b4e9 4751 }
5c0c28a8 4752
7caf489b 4753 if (link_startup_again) {
4754 link_startup_again = false;
4755 retries = DME_LINKSTARTUP_RETRIES;
4756 goto link_startup;
4757 }
4758
d2aebb9b 4759 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4760 ufshcd_init_pwr_info(hba);
4761 ufshcd_print_pwr_info(hba);
4762
7ca38cf3
YG		 4763 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4764 ret = ufshcd_disable_device_tx_lcc(hba);
4765 if (ret)
4766 goto out;
4767 }
4768
5c0c28a8 4769 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4770 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4771 if (ret)
4772 goto out;
7a3e97b0 4773
2355b66e
CG		 4774 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4775 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5c0c28a8 4776 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4777out:
7942f7b5 4778 if (ret) {
6ccf44fe 4779 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4780 ufshcd_print_host_state(hba);
4781 ufshcd_print_pwr_info(hba);
e965e5e0 4782 ufshcd_print_evt_hist(hba);
7942f7b5 4783 }
6ccf44fe 4784 return ret;
7a3e97b0
SY		 4785}
4786
5a0b0cb9
SRT		 4787/**
4788 * ufshcd_verify_dev_init() - Verify device initialization
4789 * @hba: per-adapter instance
4790 *
4791 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4792 * device Transport Protocol (UTP) layer is ready after a reset.
4793 * If the UTP layer at the device side is not initialized, it may
4794 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4795 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4796 */
4797static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4798{
4799 int err = 0;
4800 int retries;
4801
1ab27c9c 4802 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4803 mutex_lock(&hba->dev_cmd.lock);
4804 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4805 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1cbc9ad3 4806 hba->nop_out_timeout);
5a0b0cb9
SRT		 4807
4808 if (!err || err == -ETIMEDOUT)
4809 break;
4810
4811 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4812 }
4813 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4814 ufshcd_release(hba);
5a0b0cb9
SRT		 4815
4816 if (err)
4817 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4818 return err;
4819}
4820
0ce147d4
SJ		 4821/**
4822 * ufshcd_set_queue_depth - set lun queue depth
4823 * @sdev: pointer to SCSI device
4824 *
4825 * Read bLUQueueDepth value and activate scsi tagged command
4826 * queueing. For WLUN, queue depth is set to 1. For best-effort
4827 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4828 * value that host can queue.
4829 */
4830static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4831{
4832 int ret = 0;
4833 u8 lun_qdepth;
4834 struct ufs_hba *hba;
4835
4836 hba = shost_priv(sdev->host);
4837
4838 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4839 ret = ufshcd_read_unit_desc_param(hba,
4840 ufshcd_scsi_to_upiu_lun(sdev->lun),
4841 UNIT_DESC_PARAM_LU_Q_DEPTH,
4842 &lun_qdepth,
4843 sizeof(lun_qdepth));
0ce147d4
SJ		 4844
4845 /* Some WLUN doesn't support unit descriptor */
4846 if (ret == -EOPNOTSUPP)
4847 lun_qdepth = 1;
4848 else if (!lun_qdepth)
4849 /* eventually, we can figure out the real queue depth */
4850 lun_qdepth = hba->nutrs;
4851 else
4852 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4853
4854 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4855 __func__, lun_qdepth);
db5ed4df 4856 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4857}
4858
57d104c1
SJ		 4859/*
4860 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4861 * @hba: per-adapter instance
4862 * @lun: UFS device lun id
4863 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4864 *
4865 * Returns 0 in case of success and b_lu_write_protect status would be returned
4866 * @b_lu_write_protect parameter.
4867 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4868 * Returns -EINVAL in case of invalid parameters passed to this function.
4869 */
4870static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4871 u8 lun,
4872 u8 *b_lu_write_protect)
4873{
4874 int ret;
4875
4876 if (!b_lu_write_protect)
4877 ret = -EINVAL;
4878 /*
4879 * According to UFS device spec, RPMB LU can't be write
4880 * protected so skip reading bLUWriteProtect parameter for
4881 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4882 */
1baa8011 4883 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4884 ret = -ENOTSUPP;
4885 else
4886 ret = ufshcd_read_unit_desc_param(hba,
4887 lun,
4888 UNIT_DESC_PARAM_LU_WR_PROTECT,
4889 b_lu_write_protect,
4890 sizeof(*b_lu_write_protect));
4891 return ret;
4892}
4893
4894/**
4895 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4896 * status
4897 * @hba: per-adapter instance
4898 * @sdev: pointer to SCSI device
4899 *
4900 */
4901static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4902 struct scsi_device *sdev)
4903{
4904 if (hba->dev_info.f_power_on_wp_en &&
4905 !hba->dev_info.is_lu_power_on_wp) {
4906 u8 b_lu_write_protect;
4907
4908 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4909 &b_lu_write_protect) &&
4910 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4911 hba->dev_info.is_lu_power_on_wp = true;
4912 }
4913}
4914
b294ff3e
AD		 4915/**
4916 * ufshcd_setup_links - associate link b/w device wlun and other luns
4917 * @sdev: pointer to SCSI device
4918 * @hba: pointer to ufs hba
4919 */
4920static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4921{
4922 struct device_link *link;
4923
4924 /*
4925 * Device wlun is the supplier & rest of the luns are consumers.
4926 * This ensures that device wlun suspends after all other luns.
4927 */
e2106584 4928 if (hba->ufs_device_wlun) {
b294ff3e 4929 link = device_link_add(&sdev->sdev_gendev,
e2106584 4930 &hba->ufs_device_wlun->sdev_gendev,
b294ff3e
AD		 4931 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4932 if (!link) {
4933 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
e2106584 4934 dev_name(&hba->ufs_device_wlun->sdev_gendev));
b294ff3e
AD		 4935 return;
4936 }
4937 hba->luns_avail--;
4938 /* Ignore REPORT_LUN wlun probing */
4939 if (hba->luns_avail == 1) {
4940 ufshcd_rpm_put(hba);
4941 return;
4942 }
4943 } else {
4944 /*
4945 * Device wlun is probed. The assumption is that WLUNs are
4946 * scanned before other LUNs.
4947 */
4948 hba->luns_avail--;
4949 }
4950}
4951
7a3e97b0
SY		 4952/**
4953 * ufshcd_slave_alloc - handle initial SCSI device configurations
4954 * @sdev: pointer to SCSI device
4955 *
4956 * Returns success
4957 */
4958static int ufshcd_slave_alloc(struct scsi_device *sdev)
4959{
4960 struct ufs_hba *hba;
4961
4962 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4963
4964 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4965 sdev->use_10_for_ms = 1;
a3a76391
CG		 4966
4967 /* DBD field should be set to 1 in mode sense(10) */
4968 sdev->set_dbd_for_ms = 1;
7a3e97b0 4969
e8e7f271
SRT		 4970 /* allow SCSI layer to restart the device in case of errors */
4971 sdev->allow_restart = 1;
4264fd61 4972
b2a6c522
SRT		 4973 /* REPORT SUPPORTED OPERATION CODES is not supported */
4974 sdev->no_report_opcodes = 1;
4975
84af7e8b
SRT		 4976 /* WRITE_SAME command is not supported */
4977 sdev->no_write_same = 1;
e8e7f271 4978
0ce147d4 4979 ufshcd_set_queue_depth(sdev);
4264fd61 4980
57d104c1
SJ		 4981 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4982
b294ff3e
AD		 4983 ufshcd_setup_links(hba, sdev);
4984
7a3e97b0
SY		 4985 return 0;
4986}
4987
4264fd61
SRT		 4988/**
4989 * ufshcd_change_queue_depth - change queue depth
4990 * @sdev: pointer to SCSI device
4991 * @depth: required depth to set
4264fd61 4992 *
db5ed4df 4993 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4994 */
db5ed4df 4995static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61 4996{
fc21da8a 4997 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
4264fd61
SRT		 4998}
4999
f02bc975
DP		 5000static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
5001{
5002 /* skip well-known LU */
41d8a933
DP		 5003 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5004 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
f02bc975
DP		 5005 return;
5006
5007 ufshpb_destroy_lu(hba, sdev);
5008}
5009
5010static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
5011{
5012 /* skip well-known LU */
5013 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5014 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5015 return;
5016
5017 ufshpb_init_hpb_lu(hba, sdev);
5018}
5019
eeda4749
AM		 5020/**
5021 * ufshcd_slave_configure - adjust SCSI device configurations
5022 * @sdev: pointer to SCSI device
5023 */
5024static int ufshcd_slave_configure(struct scsi_device *sdev)
5025{
49615ba1 5026 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 5027 struct request_queue *q = sdev->request_queue;
5028
f02bc975
DP		 5029 ufshcd_hpb_configure(hba, sdev);
5030
eeda4749 5031 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2b2bfc8a
KK		 5032 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5033 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
b294ff3e
AD		 5034 /*
5035 * Block runtime-pm until all consumers are added.
5036 * Refer ufshcd_setup_links().
5037 */
5038 if (is_device_wlun(sdev))
5039 pm_runtime_get_noresume(&sdev->sdev_gendev);
5040 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
49615ba1 5041 sdev->rpm_autosuspend = 1;
71bb9ab6
AH		 5042 /*
5043 * Do not print messages during runtime PM to avoid never-ending cycles
5044 * of messages written back to storage by user space causing runtime
5045 * resume, causing more messages and so on.
5046 */
5047 sdev->silence_suspend = 1;
49615ba1 5048
cb77cb5a 5049 ufshcd_crypto_register(hba, q);
df043c74 5050
eeda4749
AM		 5051 return 0;
5052}
5053
7a3e97b0
SY		 5054/**
5055 * ufshcd_slave_destroy - remove SCSI device configurations
5056 * @sdev: pointer to SCSI device
5057 */
5058static void ufshcd_slave_destroy(struct scsi_device *sdev)
5059{
5060 struct ufs_hba *hba;
bf25967a 5061 unsigned long flags;
7a3e97b0
SY		 5062
5063 hba = shost_priv(sdev->host);
f02bc975
DP		 5064
5065 ufshcd_hpb_destroy(hba, sdev);
5066
0ce147d4 5067 /* Drop the reference as it won't be needed anymore */
7c48bfd0 5068 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
7c48bfd0 5069 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584 5070 hba->ufs_device_wlun = NULL;
7c48bfd0 5071 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2106584 5072 } else if (hba->ufs_device_wlun) {
bf25967a
AH		 5073 struct device *supplier = NULL;
5074
5075 /* Ensure UFS Device WLUN exists and does not disappear */
5076 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584
BVA		 5077 if (hba->ufs_device_wlun) {
5078 supplier = &hba->ufs_device_wlun->sdev_gendev;
bf25967a
AH		 5079 get_device(supplier);
5080 }
5081 spin_unlock_irqrestore(hba->host->host_lock, flags);
5082
5083 if (supplier) {
5084 /*
5085 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5086 * device will not have been registered but can still
5087 * have a device link holding a reference to the device.
5088 */
5089 device_link_remove(&sdev->sdev_gendev, supplier);
5090 put_device(supplier);
5091 }
7c48bfd0 5092 }
7a3e97b0
SY		 5093}
5094
7a3e97b0
SY		 5095/**
5096 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 5097 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5098 * @scsi_status: SCSI command status
5099 *
5100 * Returns value base on SCSI command status
5101 */
5102static inline int
5103ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5104{
5105 int result = 0;
5106
5107 switch (scsi_status) {
7a3e97b0 5108 case SAM_STAT_CHECK_CONDITION:
1c2623c5 5109 ufshcd_copy_sense_data(lrbp);
df561f66 5110 fallthrough;
1c2623c5 5111 case SAM_STAT_GOOD:
db83d8a5 5112 result |= DID_OK << 16 | scsi_status;
7a3e97b0
SY		 5113 break;
5114 case SAM_STAT_TASK_SET_FULL:
1c2623c5 5115 case SAM_STAT_BUSY:
7a3e97b0 5116 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 5117 ufshcd_copy_sense_data(lrbp);
5118 result |= scsi_status;
7a3e97b0
SY		 5119 break;
5120 default:
5121 result |= DID_ERROR << 16;
5122 break;
5123 } /* end of switch */
5124
5125 return result;
5126}
5127
5128/**
5129 * ufshcd_transfer_rsp_status - Get overall status of the response
5130 * @hba: per adapter instance
8aa29f19 5131 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5132 *
5133 * Returns result of the command to notify SCSI midlayer
5134 */
5135static inline int
5136ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5137{
5138 int result = 0;
5139 int scsi_status;
957d63e7 5140 enum utp_ocs ocs;
7a3e97b0
SY		 5141
5142 /* overall command status of utrd */
5143 ocs = ufshcd_get_tr_ocs(lrbp);
5144
d779a6e9
KK		 5145 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5146 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5147 MASK_RSP_UPIU_RESULT)
5148 ocs = OCS_SUCCESS;
5149 }
5150
7a3e97b0
SY		 5151 switch (ocs) {
5152 case OCS_SUCCESS:
5a0b0cb9 5153 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 5154 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 5155 switch (result) {
5156 case UPIU_TRANSACTION_RESPONSE:
5157 /*
5158 * get the response UPIU result to extract
5159 * the SCSI command status
5160 */
5161 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5162
5163 /*
5164 * get the result based on SCSI status response
5165 * to notify the SCSI midlayer of the command status
5166 */
5167 scsi_status = result & MASK_SCSI_STATUS;
5168 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 5169
f05ac2e5
YG		 5170 /*
5171 * Currently we are only supporting BKOPs exception
5172 * events hence we can ignore BKOPs exception event
5173 * during power management callbacks. BKOPs exception
5174 * event is not expected to be raised in runtime suspend
5175 * callback as it allows the urgent bkops.
5176 * During system suspend, we are anyway forcefully
5177 * disabling the bkops and if urgent bkops is needed
5178 * it will be enabled on system resume. Long term
5179 * solution could be to abort the system suspend if
5180 * UFS device needs urgent BKOPs.
5181 */
5182 if (!hba->pm_op_in_progress &&
aa53f580 5183 !ufshcd_eh_in_progress(hba) &&
b294ff3e
AD		 5184 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5185 /* Flushed in suspend */
5186 schedule_work(&hba->eeh_work);
4b5f4907
DP		 5187
5188 if (scsi_status == SAM_STAT_GOOD)
5189 ufshpb_rsp_upiu(hba, lrbp);
5a0b0cb9
SRT		 5190 break;
5191 case UPIU_TRANSACTION_REJECT_UPIU:
5192 /* TODO: handle Reject UPIU Response */
5193 result = DID_ERROR << 16;
3b1d0580 5194 dev_err(hba->dev,
5a0b0cb9
SRT		 5195 "Reject UPIU not fully implemented\n");
5196 break;
5197 default:
5a0b0cb9
SRT		 5198 dev_err(hba->dev,
5199 "Unexpected request response code = %x\n",
5200 result);
e0347d89 5201 result = DID_ERROR << 16;
7a3e97b0
SY		 5202 break;
5203 }
7a3e97b0
SY		 5204 break;
5205 case OCS_ABORTED:
5206 result |= DID_ABORT << 16;
5207 break;
e8e7f271
SRT		 5208 case OCS_INVALID_COMMAND_STATUS:
5209 result |= DID_REQUEUE << 16;
5210 break;
7a3e97b0
SY		 5211 case OCS_INVALID_CMD_TABLE_ATTR:
5212 case OCS_INVALID_PRDT_ATTR:
5213 case OCS_MISMATCH_DATA_BUF_SIZE:
5214 case OCS_MISMATCH_RESP_UPIU_SIZE:
5215 case OCS_PEER_COMM_FAILURE:
5216 case OCS_FATAL_ERROR:
5e7341e1
ST		 5217 case OCS_DEVICE_FATAL_ERROR:
5218 case OCS_INVALID_CRYPTO_CONFIG:
5219 case OCS_GENERAL_CRYPTO_ERROR:
7a3e97b0
SY		 5220 default:
5221 result |= DID_ERROR << 16;
3b1d0580 5222 dev_err(hba->dev,
ff8e20c6
DR		 5223 "OCS error from controller = %x for tag %d\n",
5224 ocs, lrbp->task_tag);
e965e5e0 5225 ufshcd_print_evt_hist(hba);
6ba65588 5226 ufshcd_print_host_state(hba);
7a3e97b0
SY		 5227 break;
5228 } /* end of switch */
5229
eeb1b55b
JK		 5230 if ((host_byte(result) != DID_OK) &&
5231 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
66cc820f 5232 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 5233 return result;
5234}
5235
a45f9371
CG		 5236static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5237 u32 intr_mask)
5238{
5239 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5240 !ufshcd_is_auto_hibern8_enabled(hba))
5241 return false;
5242
5243 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5244 return false;
5245
5246 if (hba->active_uic_cmd &&
5247 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5248 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5249 return false;
5250
5251 return true;
5252}
5253
6ccf44fe
SJ		 5254/**
5255 * ufshcd_uic_cmd_compl - handle completion of uic command
5256 * @hba: per adapter instance
53b3d9c3 5257 * @intr_status: interrupt status generated by the controller
9333d775
VG		 5258 *
5259 * Returns
5260 * IRQ_HANDLED - If interrupt is valid
5261 * IRQ_NONE - If invalid interrupt
6ccf44fe 5262 */
9333d775 5263static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 5264{
9333d775
VG		 5265 irqreturn_t retval = IRQ_NONE;
5266
a45f9371
CG		 5267 spin_lock(hba->host->host_lock);
5268 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5269 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5270
53b3d9c3 5271 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 5272 hba->active_uic_cmd->argument2 |=
5273 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 5274 hba->active_uic_cmd->argument3 =
5275 ufshcd_get_dme_attr_val(hba);
0f52fcb9
CG		 5276 if (!hba->uic_async_done)
5277 hba->active_uic_cmd->cmd_active = 0;
6ccf44fe 5278 complete(&hba->active_uic_cmd->done);
9333d775 5279 retval = IRQ_HANDLED;
6ccf44fe 5280 }
53b3d9c3 5281
9333d775 5282 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
0f52fcb9 5283 hba->active_uic_cmd->cmd_active = 0;
57d104c1 5284 complete(hba->uic_async_done);
9333d775
VG		 5285 retval = IRQ_HANDLED;
5286 }
aa5c6979
SC		 5287
5288 if (retval == IRQ_HANDLED)
5289 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
28fa68fc 5290 UFS_CMD_COMP);
a45f9371 5291 spin_unlock(hba->host->host_lock);
9333d775 5292 return retval;
6ccf44fe
SJ		 5293}
5294
6f8dafde
BVA		 5295/* Release the resources allocated for processing a SCSI command. */
5296static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5297 struct ufshcd_lrb *lrbp)
5298{
5299 struct scsi_cmnd *cmd = lrbp->cmd;
5300
5301 scsi_dma_unmap(cmd);
5302 lrbp->cmd = NULL; /* Mark the command as completed. */
5303 ufshcd_release(hba);
5304 ufshcd_clk_scaling_update_busy(hba);
5305}
5306
7a3e97b0 5307/**
9a47ec7c 5308 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 5309 * @hba: per adapter instance
73dc3c4a 5310 * @completed_reqs: bitmask that indicates which requests to complete
7a3e97b0 5311 */
9a47ec7c 5312static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
11682523 5313 unsigned long completed_reqs)
7a3e97b0 5314{
5a0b0cb9
SRT		 5315 struct ufshcd_lrb *lrbp;
5316 struct scsi_cmnd *cmd;
7a3e97b0 5317 int index;
e9d501b1 5318
e9d501b1
DR		 5319 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5320 lrbp = &hba->lrb[index];
a3170376 5321 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 5322 cmd = lrbp->cmd;
5323 if (cmd) {
1d8613a2
CG		 5324 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5325 ufshcd_update_monitor(hba, lrbp);
28fa68fc 5326 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
6f8dafde
BVA		 5327 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
5328 ufshcd_release_scsi_cmd(hba, lrbp);
e9d501b1 5329 /* Do not touch lrbp after scsi done */
35c3730a 5330 scsi_done(cmd);
300bb13f
JP		 5331 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5332 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 5333 if (hba->dev_cmd.complete) {
5334 ufshcd_add_command_trace(hba, index,
28fa68fc 5335 UFS_DEV_COMP);
e9d501b1 5336 complete(hba->dev_cmd.complete);
3eb9dcc0 5337 ufshcd_clk_scaling_update_busy(hba);
1a07f2d9 5338 }
e9d501b1
DR		 5339 }
5340 }
7a3e97b0
SY		 5341}
5342
eaab9b57
BVA		 5343/*
5344 * Returns > 0 if one or more commands have been completed or 0 if no
5345 * requests have been completed.
5346 */
5347static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5348{
5349 struct ufs_hba *hba = shost_priv(shost);
5350 unsigned long completed_reqs, flags;
5351 u32 tr_doorbell;
5352
5353 spin_lock_irqsave(&hba->outstanding_lock, flags);
5354 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5355 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5356 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5357 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5358 hba->outstanding_reqs);
5359 hba->outstanding_reqs &= ~completed_reqs;
5360 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5361
5362 if (completed_reqs)
5363 __ufshcd_transfer_req_compl(hba, completed_reqs);
5364
5365 return completed_reqs;
5366}
5367
9a47ec7c 5368/**
1f522c50 5369 * ufshcd_transfer_req_compl - handle SCSI and query command completion
9a47ec7c 5370 * @hba: per adapter instance
9333d775
VG		 5371 *
5372 * Returns
5373 * IRQ_HANDLED - If interrupt is valid
5374 * IRQ_NONE - If invalid interrupt
9a47ec7c 5375 */
11682523 5376static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c 5377{
9a47ec7c
YG		 5378 /* Resetting interrupt aggregation counters first and reading the
5379 * DOOR_BELL afterward allows us to handle all the completed requests.
5380 * In order to prevent other interrupts starvation the DB is read once
5381 * after reset. The down side of this solution is the possibility of
5382 * false interrupt if device completes another request after resetting
5383 * aggregation and before reading the DB.
5384 */
b638b5eb
AA		 5385 if (ufshcd_is_intr_aggr_allowed(hba) &&
5386 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 5387 ufshcd_reset_intr_aggr(hba);
5388
c11a1ae9
BVA		 5389 if (ufs_fail_completion())
5390 return IRQ_HANDLED;
5391
eaab9b57
BVA		 5392 /*
5393 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5394 * do not want polling to trigger spurious interrupt complaints.
5395 */
5396 ufshcd_poll(hba->host, 0);
9a47ec7c 5397
eaab9b57 5398 return IRQ_HANDLED;
9a47ec7c
YG		 5399}
5400
7deedfda 5401int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
cd469475
AH		 5402{
5403 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5404 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5405 &ee_ctrl_mask);
5406}
5407
7deedfda 5408int ufshcd_write_ee_control(struct ufs_hba *hba)
cd469475
AH		 5409{
5410 int err;
5411
5412 mutex_lock(&hba->ee_ctrl_mutex);
5413 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5414 mutex_unlock(&hba->ee_ctrl_mutex);
5415 if (err)
5416 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5417 __func__, err);
5418 return err;
5419}
5420
5421int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5422 u16 set, u16 clr)
5423{
5424 u16 new_mask, ee_ctrl_mask;
5425 int err = 0;
5426
5427 mutex_lock(&hba->ee_ctrl_mutex);
5428 new_mask = (*mask & ~clr) | set;
5429 ee_ctrl_mask = new_mask | *other_mask;
5430 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5431 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5432 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5433 if (!err) {
5434 hba->ee_ctrl_mask = ee_ctrl_mask;
5435 *mask = new_mask;
5436 }
5437 mutex_unlock(&hba->ee_ctrl_mutex);
5438 return err;
5439}
5440
66ec6d59
SRT		 5441/**
5442 * ufshcd_disable_ee - disable exception event
5443 * @hba: per-adapter instance
5444 * @mask: exception event to disable
5445 *
5446 * Disables exception event in the device so that the EVENT_ALERT
5447 * bit is not set.
5448 *
5449 * Returns zero on success, non-zero error value on failure.
5450 */
cd469475 5451static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5452{
cd469475 5453 return ufshcd_update_ee_drv_mask(hba, 0, mask);
66ec6d59
SRT		 5454}
5455
5456/**
5457 * ufshcd_enable_ee - enable exception event
5458 * @hba: per-adapter instance
5459 * @mask: exception event to enable
5460 *
5461 * Enable corresponding exception event in the device to allow
5462 * device to alert host in critical scenarios.
5463 *
5464 * Returns zero on success, non-zero error value on failure.
5465 */
cd469475 5466static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5467{
cd469475 5468 return ufshcd_update_ee_drv_mask(hba, mask, 0);
66ec6d59
SRT		 5469}
5470
5471/**
5472 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5473 * @hba: per-adapter instance
5474 *
5475 * Allow device to manage background operations on its own. Enabling
5476 * this might lead to inconsistent latencies during normal data transfers
5477 * as the device is allowed to manage its own way of handling background
5478 * operations.
5479 *
5480 * Returns zero on success, non-zero on failure.
5481 */
5482static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5483{
5484 int err = 0;
5485
5486 if (hba->auto_bkops_enabled)
5487 goto out;
5488
dc3c8d3a 5489 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 5490 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5491 if (err) {
5492 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5493 __func__, err);
5494 goto out;
5495 }
5496
5497 hba->auto_bkops_enabled = true;
7ff5ab47 5498 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5499
5500 /* No need of URGENT_BKOPS exception from the device */
5501 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5502 if (err)
5503 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5504 __func__, err);
5505out:
5506 return err;
5507}
5508
5509/**
5510 * ufshcd_disable_auto_bkops - block device in doing background operations
5511 * @hba: per-adapter instance
5512 *
5513 * Disabling background operations improves command response latency but
5514 * has drawback of device moving into critical state where the device is
5515 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5516 * host is idle so that BKOPS are managed effectively without any negative
5517 * impacts.
5518 *
5519 * Returns zero on success, non-zero on failure.
5520 */
5521static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5522{
5523 int err = 0;
5524
5525 if (!hba->auto_bkops_enabled)
5526 goto out;
5527
5528 /*
5529 * If host assisted BKOPs is to be enabled, make sure
5530 * urgent bkops exception is allowed.
5531 */
5532 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5533 if (err) {
5534 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5535 __func__, err);
5536 goto out;
5537 }
5538
dc3c8d3a 5539 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
1f34eedf 5540 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5541 if (err) {
5542 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5543 __func__, err);
5544 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5545 goto out;
5546 }
5547
5548 hba->auto_bkops_enabled = false;
7ff5ab47 5549 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5550 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5551out:
5552 return err;
5553}
5554
5555/**
4e768e76 5556 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5557 * @hba: per adapter instance
5558 *
5559 * After a device reset the device may toggle the BKOPS_EN flag
5560 * to default value. The s/w tracking variables should be updated
4e768e76 5561 * as well. This function would change the auto-bkops state based on
5562 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5563 */
4e768e76 5564static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5565{
4e768e76 5566 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5567 hba->auto_bkops_enabled = false;
5568 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5569 ufshcd_enable_auto_bkops(hba);
5570 } else {
5571 hba->auto_bkops_enabled = true;
5572 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5573 ufshcd_disable_auto_bkops(hba);
5574 }
7b6668d8 5575 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
24366c2a 5576 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5577}
5578
5579static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5580{
5e86ae44 5581 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5582 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5583}
5584
5585/**
57d104c1 5586 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5587 * @hba: per-adapter instance
57d104c1 5588 * @status: bkops_status value
66ec6d59 5589 *
57d104c1
SJ		 5590 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5591 * flag in the device to permit background operations if the device
5592 * bkops_status is greater than or equal to "status" argument passed to
5593 * this function, disable otherwise.
5594 *
5595 * Returns 0 for success, non-zero in case of failure.
5596 *
5597 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5598 * to know whether auto bkops is enabled or disabled after this function
5599 * returns control to it.
66ec6d59 5600 */
57d104c1
SJ		 5601static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5602 enum bkops_status status)
66ec6d59
SRT		 5603{
5604 int err;
57d104c1 5605 u32 curr_status = 0;
66ec6d59 5606
57d104c1 5607 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5608 if (err) {
5609 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5610 __func__, err);
5611 goto out;
57d104c1
SJ		 5612 } else if (curr_status > BKOPS_STATUS_MAX) {
5613 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5614 __func__, curr_status);
5615 err = -EINVAL;
5616 goto out;
66ec6d59
SRT		 5617 }
5618
57d104c1 5619 if (curr_status >= status)
66ec6d59 5620 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5621 else
5622 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5623out:
5624 return err;
5625}
5626
57d104c1
SJ		 5627/**
5628 * ufshcd_urgent_bkops - handle urgent bkops exception event
5629 * @hba: per-adapter instance
5630 *
5631 * Enable fBackgroundOpsEn flag in the device to permit background
5632 * operations.
5633 *
5634 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5635 * and negative error value for any other failure.
5636 */
5637static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5638{
afdfff59 5639 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5640}
5641
66ec6d59
SRT		 5642static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5643{
5e86ae44 5644 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5645 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5646}
5647
afdfff59
YG		 5648static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5649{
5650 int err;
5651 u32 curr_status = 0;
5652
5653 if (hba->is_urgent_bkops_lvl_checked)
5654 goto enable_auto_bkops;
5655
5656 err = ufshcd_get_bkops_status(hba, &curr_status);
5657 if (err) {
5658 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5659 __func__, err);
5660 goto out;
5661 }
5662
5663 /*
5664 * We are seeing that some devices are raising the urgent bkops
5665 * exception events even when BKOPS status doesn't indicate performace
5666 * impacted or critical. Handle these device by determining their urgent
5667 * bkops status at runtime.
5668 */
5669 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5670 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5671 __func__, curr_status);
5672 /* update the current status as the urgent bkops level */
5673 hba->urgent_bkops_lvl = curr_status;
5674 hba->is_urgent_bkops_lvl_checked = true;
5675 }
5676
5677enable_auto_bkops:
5678 err = ufshcd_enable_auto_bkops(hba);
5679out:
5680 if (err < 0)
5681 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5682 __func__, err);
5683}
5684
322c4b29
AA		 5685static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5686{
5687 u32 value;
5688
5689 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5690 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5691 return;
5692
5693 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5694
5695 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5696
5697 /*
5698 * A placeholder for the platform vendors to add whatever additional
5699 * steps required
5700 */
5701}
5702
3b5f3c0d 5703static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
3d17b9b5 5704{
6f8d5a6a 5705 u8 index;
3b5f3c0d
YH		 5706 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5707 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5708
5709 index = ufshcd_wb_get_query_index(hba);
5710 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5711}
5712
5713int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5714{
5715 int ret;
3d17b9b5 5716
79e3520f 5717 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5718 return 0;
5719
4cd48995 5720 if (!(enable ^ hba->dev_info.wb_enabled))
3d17b9b5 5721 return 0;
3d17b9b5 5722
3b5f3c0d 5723 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
3d17b9b5 5724 if (ret) {
3b5f3c0d 5725 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
3d17b9b5
AD		 5726 __func__, enable ? "enable" : "disable", ret);
5727 return ret;
5728 }
5729
4cd48995 5730 hba->dev_info.wb_enabled = enable;
3b5f3c0d
YH		 5731 dev_info(hba->dev, "%s Write Booster %s\n",
5732 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5733
5734 return ret;
5735}
5736
3b5f3c0d 5737static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
3d17b9b5 5738{
3b5f3c0d 5739 int ret;
3d17b9b5 5740
3b5f3c0d
YH		 5741 ret = __ufshcd_wb_toggle(hba, set,
5742 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5743 if (ret) {
5744 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5745 __func__, set ? "enable" : "disable", ret);
5746 return;
5747 }
5748 dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5749 __func__, set ? "enabled" : "disabled");
3d17b9b5
AD		 5750}
5751
3b5f3c0d 5752static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
3d17b9b5
AD		 5753{
5754 int ret;
5755
d3ba622d
BH		 5756 if (!ufshcd_is_wb_allowed(hba) ||
5757 hba->dev_info.wb_buf_flush_enabled == enable)
3b5f3c0d 5758 return;
3d17b9b5 5759
3b5f3c0d 5760 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
3d17b9b5 5761 if (ret) {
d3ba622d
BH		 5762 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5763 enable ? "enable" : "disable", ret);
3b5f3c0d 5764 return;
3d17b9b5
AD		 5765 }
5766
d3ba622d
BH		 5767 hba->dev_info.wb_buf_flush_enabled = enable;
5768
3b5f3c0d
YH		 5769 dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5770 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5771}
5772
5773static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5774 u32 avail_buf)
5775{
5776 u32 cur_buf;
5777 int ret;
e31011ab 5778 u8 index;
3d17b9b5 5779
e31011ab 5780 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5781 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5782 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
e31011ab 5783 index, 0, &cur_buf);
3d17b9b5
AD		 5784 if (ret) {
5785 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5786 __func__, ret);
5787 return false;
5788 }
5789
5790 if (!cur_buf) {
5791 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5792 cur_buf);
5793 return false;
5794 }
d14734ae 5795 /* Let it continue to flush when available buffer exceeds threshold */
a858af9a 5796 return avail_buf < hba->vps->wb_flush_threshold;
3d17b9b5
AD		 5797}
5798
f681d107
JC		 5799static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5800{
5801 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
5802 ufshcd_wb_toggle_flush(hba, false);
5803
5804 ufshcd_wb_toggle_flush_during_h8(hba, false);
5805 ufshcd_wb_toggle(hba, false);
5806 hba->caps &= ~UFSHCD_CAP_WB_EN;
5807
5808 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5809}
5810
5811static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5812{
5813 u32 lifetime;
5814 int ret;
5815 u8 index;
5816
5817 index = ufshcd_wb_get_query_index(hba);
5818 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5819 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5820 index, 0, &lifetime);
5821 if (ret) {
5822 dev_err(hba->dev,
5823 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
5824 __func__, ret);
5825 return false;
5826 }
5827
5828 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
5829 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
5830 __func__, lifetime);
5831 return false;
5832 }
5833
5834 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
5835 __func__, lifetime);
5836
5837 return true;
5838}
5839
51dd905b 5840static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
3d17b9b5
AD		 5841{
5842 int ret;
5843 u32 avail_buf;
e31011ab 5844 u8 index;
3d17b9b5 5845
79e3520f 5846 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5 5847 return false;
f681d107
JC		 5848
5849 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
5850 ufshcd_wb_force_disable(hba);
5851 return false;
5852 }
5853
3d17b9b5
AD		 5854 /*
5855 * The ufs device needs the vcc to be ON to flush.
5856 * With user-space reduction enabled, it's enough to enable flush
5857 * by checking only the available buffer. The threshold
5858 * defined here is > 90% full.
5859 * With user-space preserved enabled, the current-buffer
5860 * should be checked too because the wb buffer size can reduce
5861 * when disk tends to be full. This info is provided by current
5862 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5863 * keeping vcc on when current buffer is empty.
5864 */
e31011ab 5865 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5866 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5867 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
e31011ab 5868 index, 0, &avail_buf);
3d17b9b5
AD		 5869 if (ret) {
5870 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5871 __func__, ret);
5872 return false;
5873 }
5874
a858af9a
BVA		 5875 if (!hba->dev_info.b_presrv_uspc_en)
5876 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
3d17b9b5
AD		 5877
5878 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5879}
5880
51dd905b
SC		 5881static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5882{
5883 struct ufs_hba *hba = container_of(to_delayed_work(work),
5884 struct ufs_hba,
5885 rpm_dev_flush_recheck_work);
5886 /*
5887 * To prevent unnecessary VCC power drain after device finishes
5888 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5889 * after a certain delay to recheck the threshold by next runtime
5890 * suspend.
5891 */
b294ff3e
AD		 5892 ufshcd_rpm_get_sync(hba);
5893 ufshcd_rpm_put_sync(hba);
51dd905b
SC		 5894}
5895
66ec6d59
SRT		 5896/**
5897 * ufshcd_exception_event_handler - handle exceptions raised by device
5898 * @work: pointer to work data
5899 *
5900 * Read bExceptionEventStatus attribute from the device and handle the
5901 * exception event accordingly.
5902 */
5903static void ufshcd_exception_event_handler(struct work_struct *work)
5904{
5905 struct ufs_hba *hba;
5906 int err;
5907 u32 status = 0;
5908 hba = container_of(work, struct ufs_hba, eeh_work);
5909
03e1d28e 5910 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5911 err = ufshcd_get_ee_status(hba, &status);
5912 if (err) {
5913 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5914 __func__, err);
5915 goto out;
5916 }
5917
f7733625
AH		 5918 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5919
cd469475 5920 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
afdfff59
YG		 5921 ufshcd_bkops_exception_event_handler(hba);
5922
322c4b29
AA		 5923 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
5924 ufshcd_temp_exception_event_handler(hba, status);
5925
7deedfda 5926 ufs_debugfs_exception_event(hba, status);
66ec6d59 5927out:
03e1d28e 5928 ufshcd_scsi_unblock_requests(hba);
66ec6d59
SRT		 5929}
5930
9a47ec7c
YG		 5931/* Complete requests that have door-bell cleared */
5932static void ufshcd_complete_requests(struct ufs_hba *hba)
5933{
11682523 5934 ufshcd_transfer_req_compl(hba);
9a47ec7c
YG		 5935 ufshcd_tmc_handler(hba);
5936}
5937
583fa62d
YG		 5938/**
5939 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5940 * to recover from the DL NAC errors or not.
5941 * @hba: per-adapter instance
5942 *
5943 * Returns true if error handling is required, false otherwise
5944 */
5945static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5946{
5947 unsigned long flags;
5948 bool err_handling = true;
5949
5950 spin_lock_irqsave(hba->host->host_lock, flags);
5951 /*
5952 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5953 * device fatal error and/or DL NAC & REPLAY timeout errors.
5954 */
5955 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5956 goto out;
5957
5958 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5959 ((hba->saved_err & UIC_ERROR) &&
5960 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5961 goto out;
5962
5963 if ((hba->saved_err & UIC_ERROR) &&
5964 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5965 int err;
5966 /*
5967 * wait for 50ms to see if we can get any other errors or not.
5968 */
5969 spin_unlock_irqrestore(hba->host->host_lock, flags);
5970 msleep(50);
5971 spin_lock_irqsave(hba->host->host_lock, flags);
5972
5973 /*
5974 * now check if we have got any other severe errors other than
5975 * DL NAC error?
5976 */
5977 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5978 ((hba->saved_err & UIC_ERROR) &&
5979 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5980 goto out;
5981
5982 /*
5983 * As DL NAC is the only error received so far, send out NOP
5984 * command to confirm if link is still active or not.
5985 * - If we don't get any response then do error recovery.
5986 * - If we get response then clear the DL NAC error bit.
5987 */
5988
5989 spin_unlock_irqrestore(hba->host->host_lock, flags);
5990 err = ufshcd_verify_dev_init(hba);
5991 spin_lock_irqsave(hba->host->host_lock, flags);
5992
5993 if (err)
5994 goto out;
5995
5996 /* Link seems to be alive hence ignore the DL NAC errors */
5997 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5998 hba->saved_err &= ~UIC_ERROR;
5999 /* clear NAC error */
6000 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
b0008625 6001 if (!hba->saved_uic_err)
583fa62d 6002 err_handling = false;
583fa62d
YG		 6003 }
6004out:
6005 spin_unlock_irqrestore(hba->host->host_lock, flags);
6006 return err_handling;
6007}
6008
88b09900
AH		 6009/* host lock must be held before calling this func */
6010static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6011{
6012 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6013 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6014}
6015
267a59f6 6016void ufshcd_schedule_eh_work(struct ufs_hba *hba)
88b09900 6017{
267a59f6
BVA		 6018 lockdep_assert_held(hba->host->host_lock);
6019
88b09900
AH		 6020 /* handle fatal errors only when link is not in error state */
6021 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6022 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6023 ufshcd_is_saved_err_fatal(hba))
6024 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6025 else
6026 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6027 queue_work(hba->eh_wq, &hba->eh_work);
6028 }
6029}
6030
348e1bc5
SC		 6031static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6032{
6033 down_write(&hba->clk_scaling_lock);
6034 hba->clk_scaling.is_allowed = allow;
6035 up_write(&hba->clk_scaling_lock);
6036}
6037
6038static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6039{
6040 if (suspend) {
6041 if (hba->clk_scaling.is_enabled)
6042 ufshcd_suspend_clkscaling(hba);
6043 ufshcd_clk_scaling_allow(hba, false);
6044 } else {
6045 ufshcd_clk_scaling_allow(hba, true);
6046 if (hba->clk_scaling.is_enabled)
6047 ufshcd_resume_clkscaling(hba);
6048 }
6049}
6050
c72e79c0
CG		 6051static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6052{
b294ff3e 6053 ufshcd_rpm_get_sync(hba);
e2106584 6054 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
b294ff3e 6055 hba->is_sys_suspended) {
88a92d6a
CG		 6056 enum ufs_pm_op pm_op;
6057
c72e79c0 6058 /*
b294ff3e 6059 * Don't assume anything of resume, if
c72e79c0
CG		 6060 * resume fails, irq and clocks can be OFF, and powers
6061 * can be OFF or in LPM.
6062 */
6063 ufshcd_setup_hba_vreg(hba, true);
6064 ufshcd_enable_irq(hba);
6065 ufshcd_setup_vreg(hba, true);
6066 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6067 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6068 ufshcd_hold(hba, false);
6069 if (!ufshcd_is_clkgating_allowed(hba))
6070 ufshcd_setup_clocks(hba, true);
6071 ufshcd_release(hba);
88a92d6a
CG		 6072 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6073 ufshcd_vops_resume(hba, pm_op);
c72e79c0
CG		 6074 } else {
6075 ufshcd_hold(hba, false);
348e1bc5
SC		 6076 if (ufshcd_is_clkscaling_supported(hba) &&
6077 hba->clk_scaling.is_enabled)
c72e79c0 6078 ufshcd_suspend_clkscaling(hba);
348e1bc5 6079 ufshcd_clk_scaling_allow(hba, false);
c72e79c0 6080 }
aa53f580
CG		 6081 ufshcd_scsi_block_requests(hba);
6082 /* Drain ufshcd_queuecommand() */
5675c381 6083 synchronize_rcu();
aa53f580 6084 cancel_work_sync(&hba->eeh_work);
c72e79c0
CG		 6085}
6086
6087static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6088{
aa53f580 6089 ufshcd_scsi_unblock_requests(hba);
c72e79c0 6090 ufshcd_release(hba);
348e1bc5
SC		 6091 if (ufshcd_is_clkscaling_supported(hba))
6092 ufshcd_clk_scaling_suspend(hba, false);
b294ff3e 6093 ufshcd_rpm_put(hba);
c72e79c0
CG		 6094}
6095
6096static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6097{
9cd20d3f 6098 return (!hba->is_powered || hba->shutting_down ||
e2106584 6099 !hba->ufs_device_wlun ||
9cd20d3f 6100 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
c72e79c0 6101 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
9cd20d3f 6102 ufshcd_is_link_broken(hba))));
c72e79c0
CG		 6103}
6104
6105#ifdef CONFIG_PM
6106static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6107{
6108 struct Scsi_Host *shost = hba->host;
6109 struct scsi_device *sdev;
6110 struct request_queue *q;
6111 int ret;
6112
88a92d6a 6113 hba->is_sys_suspended = false;
c72e79c0 6114 /*
b294ff3e 6115 * Set RPM status of wlun device to RPM_ACTIVE,
c72e79c0
CG		 6116 * this also clears its runtime error.
6117 */
e2106584 6118 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
b294ff3e
AD		 6119
6120 /* hba device might have a runtime error otherwise */
6121 if (ret)
6122 ret = pm_runtime_set_active(hba->dev);
c72e79c0 6123 /*
b294ff3e
AD		 6124 * If wlun device had runtime error, we also need to resume those
6125 * consumer scsi devices in case any of them has failed to be
6126 * resumed due to supplier runtime resume failure. This is to unblock
c72e79c0
CG		 6127 * blk_queue_enter in case there are bios waiting inside it.
6128 */
6129 if (!ret) {
6130 shost_for_each_device(sdev, shost) {
6131 q = sdev->request_queue;
6132 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6133 q->rpm_status == RPM_SUSPENDING))
6134 pm_request_resume(q->dev);
6135 }
6136 }
6137}
6138#else
6139static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6140{
6141}
6142#endif
6143
2355b66e
CG		 6144static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6145{
6146 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6147 u32 mode;
6148
6149 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6150
6151 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6152 return true;
6153
6154 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6155 return true;
6156
6157 return false;
6158}
6159
7a3e97b0 6160/**
e8e7f271 6161 * ufshcd_err_handler - handle UFS errors that require s/w attention
88b09900 6162 * @work: pointer to work structure
7a3e97b0 6163 */
88b09900 6164static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0 6165{
87bf6a6b 6166 int retries = MAX_ERR_HANDLER_RETRIES;
88b09900 6167 struct ufs_hba *hba;
e8e7f271 6168 unsigned long flags;
87bf6a6b
AH		 6169 bool needs_restore;
6170 bool needs_reset;
6171 bool err_xfer;
6172 bool err_tm;
6173 int pmc_err;
e8e7f271
SRT		 6174 int tag;
6175
88b09900
AH		 6176 hba = container_of(work, struct ufs_hba, eh_work);
6177
4693fad7
BVA		 6178 dev_info(hba->dev,
6179 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6180 __func__, ufshcd_state_name[hba->ufshcd_state],
6181 hba->is_powered, hba->shutting_down, hba->saved_err,
6182 hba->saved_uic_err, hba->force_reset,
6183 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6184
9cd20d3f 6185 down(&hba->host_sem);
e8e7f271 6186 spin_lock_irqsave(hba->host->host_lock, flags);
c72e79c0 6187 if (ufshcd_err_handling_should_stop(hba)) {
4db7a236
CG		 6188 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6189 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6190 spin_unlock_irqrestore(hba->host->host_lock, flags);
9cd20d3f 6191 up(&hba->host_sem);
4db7a236
CG		 6192 return;
6193 }
6194 ufshcd_set_eh_in_progress(hba);
6195 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6196 ufshcd_err_handling_prepare(hba);
a45f9371
CG		 6197 /* Complete requests that have door-bell cleared by h/w */
6198 ufshcd_complete_requests(hba);
e8e7f271 6199 spin_lock_irqsave(hba->host->host_lock, flags);
87bf6a6b
AH		 6200again:
6201 needs_restore = false;
6202 needs_reset = false;
6203 err_xfer = false;
6204 err_tm = false;
6205
aa53f580
CG		 6206 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6207 hba->ufshcd_state = UFSHCD_STATE_RESET;
88a92d6a
CG		 6208 /*
6209 * A full reset and restore might have happened after preparation
6210 * is finished, double check whether we should stop.
6211 */
6212 if (ufshcd_err_handling_should_stop(hba))
6213 goto skip_err_handling;
6214
583fa62d
YG		 6215 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6216 bool ret;
6217
6218 spin_unlock_irqrestore(hba->host->host_lock, flags);
6219 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6220 ret = ufshcd_quirk_dl_nac_errors(hba);
6221 spin_lock_irqsave(hba->host->host_lock, flags);
88a92d6a 6222 if (!ret && ufshcd_err_handling_should_stop(hba))
583fa62d
YG		 6223 goto skip_err_handling;
6224 }
4db7a236 6225
2355b66e
CG		 6226 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6227 (hba->saved_uic_err &&
6228 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
c3be8d1e
CG		 6229 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6230
6231 spin_unlock_irqrestore(hba->host->host_lock, flags);
6232 ufshcd_print_host_state(hba);
6233 ufshcd_print_pwr_info(hba);
e965e5e0 6234 ufshcd_print_evt_hist(hba);
c3be8d1e
CG		 6235 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6236 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6237 spin_lock_irqsave(hba->host->host_lock, flags);
6238 }
6239
9a47ec7c
YG		 6240 /*
6241 * if host reset is required then skip clearing the pending
2df74b69
CG		 6242 * transfers forcefully because they will get cleared during
6243 * host reset and restore
9a47ec7c 6244 */
88a92d6a
CG		 6245 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6246 ufshcd_is_saved_err_fatal(hba) ||
6247 ((hba->saved_err & UIC_ERROR) &&
6248 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6249 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6250 needs_reset = true;
2355b66e 6251 goto do_reset;
88a92d6a 6252 }
9a47ec7c 6253
2355b66e
CG		 6254 /*
6255 * If LINERESET was caught, UFS might have been put to PWM mode,
6256 * check if power mode restore is needed.
6257 */
6258 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6259 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6260 if (!hba->saved_uic_err)
6261 hba->saved_err &= ~UIC_ERROR;
6262 spin_unlock_irqrestore(hba->host->host_lock, flags);
6263 if (ufshcd_is_pwr_mode_restore_needed(hba))
6264 needs_restore = true;
6265 spin_lock_irqsave(hba->host->host_lock, flags);
6266 if (!hba->saved_err && !needs_restore)
6267 goto skip_err_handling;
6268 }
9a47ec7c 6269
2355b66e 6270 hba->silence_err_logs = true;
9a47ec7c
YG		 6271 /* release lock as clear command might sleep */
6272 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6273 /* Clear pending transfer requests */
9a47ec7c 6274 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
307348f6 6275 if (ufshcd_try_to_abort_task(hba, tag)) {
9a47ec7c
YG		 6276 err_xfer = true;
6277 goto lock_skip_pending_xfer_clear;
6278 }
4693fad7
BVA		 6279 dev_err(hba->dev, "Aborted tag %d / CDB %#02x\n", tag,
6280 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1);
9a47ec7c 6281 }
e8e7f271
SRT		 6282
6283 /* Clear pending task management requests */
9a47ec7c
YG		 6284 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6285 if (ufshcd_clear_tm_cmd(hba, tag)) {
6286 err_tm = true;
6287 goto lock_skip_pending_xfer_clear;
6288 }
6289 }
e8e7f271 6290
9a47ec7c 6291lock_skip_pending_xfer_clear:
11682523
BVA		 6292 /* Complete the requests that are cleared by s/w */
6293 ufshcd_complete_requests(hba);
9a47ec7c 6294
a45f9371
CG		 6295 spin_lock_irqsave(hba->host->host_lock, flags);
6296 hba->silence_err_logs = false;
2355b66e 6297 if (err_xfer || err_tm) {
9a47ec7c 6298 needs_reset = true;
2355b66e
CG		 6299 goto do_reset;
6300 }
9a47ec7c 6301
2355b66e
CG		 6302 /*
6303 * After all reqs and tasks are cleared from doorbell,
6304 * now it is safe to retore power mode.
6305 */
6306 if (needs_restore) {
6307 spin_unlock_irqrestore(hba->host->host_lock, flags);
6308 /*
6309 * Hold the scaling lock just in case dev cmds
6310 * are sent via bsg and/or sysfs.
6311 */
6312 down_write(&hba->clk_scaling_lock);
6313 hba->force_pmc = true;
6314 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6315 if (pmc_err) {
6316 needs_reset = true;
6317 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6318 __func__, pmc_err);
6319 }
6320 hba->force_pmc = false;
6321 ufshcd_print_pwr_info(hba);
6322 up_write(&hba->clk_scaling_lock);
6323 spin_lock_irqsave(hba->host->host_lock, flags);
6324 }
9a47ec7c 6325
2355b66e 6326do_reset:
e8e7f271 6327 /* Fatal errors need reset */
9a47ec7c 6328 if (needs_reset) {
87bf6a6b
AH		 6329 int err;
6330
4db7a236 6331 hba->force_reset = false;
9a47ec7c 6332 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6333 err = ufshcd_reset_and_restore(hba);
4db7a236
CG		 6334 if (err)
6335 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6336 __func__, err);
c72e79c0
CG		 6337 else
6338 ufshcd_recover_pm_error(hba);
9a47ec7c 6339 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6340 }
9a47ec7c 6341
583fa62d 6342skip_err_handling:
9a47ec7c 6343 if (!needs_reset) {
4db7a236
CG		 6344 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6345 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
9a47ec7c
YG		 6346 if (hba->saved_err || hba->saved_uic_err)
6347 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6348 __func__, hba->saved_err, hba->saved_uic_err);
6349 }
87bf6a6b
AH		 6350 /* Exit in an operational state or dead */
6351 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6352 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6353 if (--retries)
6354 goto again;
6355 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6356 }
e8e7f271 6357 ufshcd_clear_eh_in_progress(hba);
9a47ec7c 6358 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6359 ufshcd_err_handling_unprepare(hba);
9cd20d3f 6360 up(&hba->host_sem);
4693fad7
BVA		 6361
6362 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6363 ufshcd_state_name[hba->ufshcd_state]);
7a3e97b0
SY		 6364}
6365
6366/**
e8e7f271
SRT		 6367 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6368 * @hba: per-adapter instance
9333d775
VG		 6369 *
6370 * Returns
6371 * IRQ_HANDLED - If interrupt is valid
6372 * IRQ_NONE - If invalid interrupt
7a3e97b0 6373 */
9333d775 6374static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 6375{
6376 u32 reg;
9333d775 6377 irqreturn_t retval = IRQ_NONE;
7a3e97b0 6378
2355b66e 6379 /* PHY layer error */
fb7b45f0 6380 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
fb7b45f0 6381 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
2355b66e 6382 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6383 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
fb7b45f0
DR		 6384 /*
6385 * To know whether this error is fatal or not, DB timeout
6386 * must be checked but this error is handled separately.
6387 */
2355b66e
CG		 6388 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6389 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6390 __func__);
6391
6392 /* Got a LINERESET indication. */
6393 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6394 struct uic_command *cmd = NULL;
6395
6396 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6397 if (hba->uic_async_done && hba->active_uic_cmd)
6398 cmd = hba->active_uic_cmd;
6399 /*
6400 * Ignore the LINERESET during power mode change
6401 * operation via DME_SET command.
6402 */
6403 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6404 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6405 }
9333d775 6406 retval |= IRQ_HANDLED;
ff8e20c6 6407 }
fb7b45f0 6408
e8e7f271
SRT		 6409 /* PA_INIT_ERROR is fatal and needs UIC reset */
6410 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 6411 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6412 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6413 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
ff8e20c6 6414
9333d775
VG		 6415 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6416 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6417 else if (hba->dev_quirks &
6418 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6419 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6420 hba->uic_error |=
6421 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6422 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6423 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6424 }
6425 retval |= IRQ_HANDLED;
583fa62d 6426 }
e8e7f271
SRT		 6427
6428 /* UIC NL/TL/DME errors needs software retry */
6429 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 6430 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6431 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6432 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
e8e7f271 6433 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 6434 retval |= IRQ_HANDLED;
ff8e20c6 6435 }
e8e7f271
SRT		 6436
6437 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 6438 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6439 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6440 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
e8e7f271 6441 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 6442 retval |= IRQ_HANDLED;
ff8e20c6 6443 }
e8e7f271
SRT		 6444
6445 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 6446 if ((reg & UIC_DME_ERROR) &&
6447 (reg & UIC_DME_ERROR_CODE_MASK)) {
e965e5e0 6448 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
e8e7f271 6449 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 6450 retval |= IRQ_HANDLED;
ff8e20c6 6451 }
e8e7f271
SRT		 6452
6453 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6454 __func__, hba->uic_error);
9333d775 6455 return retval;
e8e7f271
SRT		 6456}
6457
6458/**
6459 * ufshcd_check_errors - Check for errors that need s/w attention
6460 * @hba: per-adapter instance
a45f9371 6461 * @intr_status: interrupt status generated by the controller
9333d775
VG		 6462 *
6463 * Returns
6464 * IRQ_HANDLED - If interrupt is valid
6465 * IRQ_NONE - If invalid interrupt
e8e7f271 6466 */
a45f9371 6467static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
e8e7f271
SRT		 6468{
6469 bool queue_eh_work = false;
9333d775 6470 irqreturn_t retval = IRQ_NONE;
e8e7f271 6471
a45f9371
CG		 6472 spin_lock(hba->host->host_lock);
6473 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6474
d3c615bf 6475 if (hba->errors & INT_FATAL_ERRORS) {
e965e5e0
SC		 6476 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6477 hba->errors);
e8e7f271 6478 queue_eh_work = true;
d3c615bf 6479 }
7a3e97b0
SY		 6480
6481 if (hba->errors & UIC_ERROR) {
e8e7f271 6482 hba->uic_error = 0;
9333d775 6483 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 6484 if (hba->uic_error)
6485 queue_eh_work = true;
7a3e97b0 6486 }
e8e7f271 6487
82174440
SC		 6488 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6489 dev_err(hba->dev,
6490 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6491 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6492 "Enter" : "Exit",
6493 hba->errors, ufshcd_get_upmcrs(hba));
e965e5e0 6494 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
d3c615bf 6495 hba->errors);
4db7a236 6496 ufshcd_set_link_broken(hba);
82174440
SC		 6497 queue_eh_work = true;
6498 }
6499
e8e7f271 6500 if (queue_eh_work) {
9a47ec7c
YG		 6501 /*
6502 * update the transfer error masks to sticky bits, let's do this
6503 * irrespective of current ufshcd_state.
6504 */
6505 hba->saved_err |= hba->errors;
6506 hba->saved_uic_err |= hba->uic_error;
6507
4db7a236 6508 /* dump controller state before resetting */
ace3804b
CG		 6509 if ((hba->saved_err &
6510 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
2355b66e
CG		 6511 (hba->saved_uic_err &&
6512 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
4db7a236 6513 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
66cc820f
DR		 6514 __func__, hba->saved_err,
6515 hba->saved_uic_err);
c3be8d1e
CG		 6516 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6517 "host_regs: ");
4db7a236 6518 ufshcd_print_pwr_info(hba);
e8e7f271 6519 }
88b09900 6520 ufshcd_schedule_eh_work(hba);
9333d775 6521 retval |= IRQ_HANDLED;
3441da7d 6522 }
e8e7f271
SRT		 6523 /*
6524 * if (!queue_eh_work) -
6525 * Other errors are either non-fatal where host recovers
6526 * itself without s/w intervention or errors that will be
6527 * handled by the SCSI core layer.
6528 */
a45f9371
CG		 6529 hba->errors = 0;
6530 hba->uic_error = 0;
6531 spin_unlock(hba->host->host_lock);
9333d775 6532 return retval;
7a3e97b0
SY		 6533}
6534
6535/**
6536 * ufshcd_tmc_handler - handle task management function completion
6537 * @hba: per adapter instance
9333d775
VG		 6538 *
6539 * Returns
6540 * IRQ_HANDLED - If interrupt is valid
6541 * IRQ_NONE - If invalid interrupt
7a3e97b0 6542 */
9333d775 6543static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 6544{
f5ef336f
AH		 6545 unsigned long flags, pending, issued;
6546 irqreturn_t ret = IRQ_NONE;
6547 int tag;
6548
a45f9371 6549 spin_lock_irqsave(hba->host->host_lock, flags);
5cb37a26 6550 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
f5ef336f
AH		 6551 issued = hba->outstanding_tasks & ~pending;
6552 for_each_set_bit(tag, &issued, hba->nutmrs) {
6553 struct request *req = hba->tmf_rqs[tag];
6554 struct completion *c = req->end_io_data;
6555
6556 complete(c);
6557 ret = IRQ_HANDLED;
6558 }
a45f9371
CG		 6559 spin_unlock_irqrestore(hba->host->host_lock, flags);
6560
f5ef336f 6561 return ret;
7a3e97b0
SY		 6562}
6563
6564/**
6565 * ufshcd_sl_intr - Interrupt service routine
6566 * @hba: per adapter instance
6567 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 6568 *
6569 * Returns
6570 * IRQ_HANDLED - If interrupt is valid
6571 * IRQ_NONE - If invalid interrupt
7a3e97b0 6572 */
9333d775 6573static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 6574{
9333d775
VG		 6575 irqreturn_t retval = IRQ_NONE;
6576
53b3d9c3 6577 if (intr_status & UFSHCD_UIC_MASK)
9333d775 6578 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0 6579
a45f9371
CG		 6580 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6581 retval |= ufshcd_check_errors(hba, intr_status);
6582
7a3e97b0 6583 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 6584 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 6585
6586 if (intr_status & UTP_TRANSFER_REQ_COMPL)
11682523 6587 retval |= ufshcd_transfer_req_compl(hba);
9333d775
VG		 6588
6589 return retval;
7a3e97b0
SY		 6590}
6591
6592/**
6593 * ufshcd_intr - Main interrupt service routine
6594 * @irq: irq number
6595 * @__hba: pointer to adapter instance
6596 *
9333d775
VG		 6597 * Returns
6598 * IRQ_HANDLED - If interrupt is valid
6599 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 6600 */
6601static irqreturn_t ufshcd_intr(int irq, void *__hba)
6602{
127d5f7c 6603 u32 intr_status, enabled_intr_status = 0;
7a3e97b0
SY		 6604 irqreturn_t retval = IRQ_NONE;
6605 struct ufs_hba *hba = __hba;
7f6ba4f1 6606 int retries = hba->nutrs;
7a3e97b0 6607
b873a275 6608 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
3f8af604
CG		 6609 hba->ufs_stats.last_intr_status = intr_status;
6610 hba->ufs_stats.last_intr_ts = ktime_get();
7a3e97b0 6611
7f6ba4f1
VG		 6612 /*
6613 * There could be max of hba->nutrs reqs in flight and in worst case
6614 * if the reqs get finished 1 by 1 after the interrupt status is
6615 * read, make sure we handle them by checking the interrupt status
6616 * again in a loop until we process all of the reqs before returning.
6617 */
127d5f7c 6618 while (intr_status && retries--) {
7f6ba4f1
VG		 6619 enabled_intr_status =
6620 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
60ec3755 6621 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 6622 if (enabled_intr_status)
6623 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 6624
6625 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
127d5f7c 6626 }
d75f7fe4 6627
eeb1b55b 6628 if (enabled_intr_status && retval == IRQ_NONE &&
40d2fd05
BVA		 6629 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6630 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
eeb1b55b
JK		 6631 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6632 __func__,
6633 intr_status,
6634 hba->ufs_stats.last_intr_status,
6635 enabled_intr_status);
9333d775
VG		 6636 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6637 }
6638
7a3e97b0
SY		 6639 return retval;
6640}
6641
e2933132
SRT		 6642static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6643{
6644 int err = 0;
6645 u32 mask = 1 << tag;
6646 unsigned long flags;
6647
6648 if (!test_bit(tag, &hba->outstanding_tasks))
6649 goto out;
6650
6651 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 6652 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 6653 spin_unlock_irqrestore(hba->host->host_lock, flags);
6654
6655 /* poll for max. 1 sec to clear door bell register by h/w */
6656 err = ufshcd_wait_for_register(hba,
6657 REG_UTP_TASK_REQ_DOOR_BELL,
5cac1095 6658 mask, 0, 1000, 1000);
4693fad7
BVA		 6659
6660 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6661 tag, err ? "succeeded" : "failed");
6662
e2933132
SRT		 6663out:
6664 return err;
6665}
6666
c6049cd9
CH		 6667static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6668 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 6669{
69a6c269 6670 struct request_queue *q = hba->tmf_queue;
c6049cd9 6671 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 6672 DECLARE_COMPLETION_ONSTACK(wait);
6673 struct request *req;
7a3e97b0 6674 unsigned long flags;
4b42d557 6675 int task_tag, err;
7a3e97b0 6676
e2933132 6677 /*
0bf6d96c 6678 * blk_mq_alloc_request() is used here only to get a free tag.
e2933132 6679 */
0bf6d96c 6680 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
eeb1b55b
JK		 6681 if (IS_ERR(req))
6682 return PTR_ERR(req);
6683
69a6c269 6684 req->end_io_data = &wait;
1ab27c9c 6685 ufshcd_hold(hba, false);
7a3e97b0 6686
e2933132 6687 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0 6688
4b42d557 6689 task_tag = req->tag;
eaab9b57
BVA		 6690 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6691 task_tag);
f5ef336f 6692 hba->tmf_rqs[req->tag] = req;
1352eec8 6693 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
c6049cd9 6694
4b42d557
CG		 6695 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6696 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
d2877be4 6697
7a3e97b0 6698 /* send command to the controller */
4b42d557 6699 __set_bit(task_tag, &hba->outstanding_tasks);
897efe62 6700
4b42d557 6701 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 6702 /* Make sure that doorbell is committed immediately */
6703 wmb();
7a3e97b0
SY		 6704
6705 spin_unlock_irqrestore(host->host_lock, flags);
6706
28fa68fc 6707 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6667e6d9 6708
7a3e97b0 6709 /* wait until the task management command is completed */
69a6c269 6710 err = wait_for_completion_io_timeout(&wait,
e2933132 6711 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 6712 if (!err) {
28fa68fc 6713 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
e2933132
SRT		 6714 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6715 __func__, tm_function);
4b42d557
CG		 6716 if (ufshcd_clear_tm_cmd(hba, task_tag))
6717 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6718 __func__, task_tag);
e2933132
SRT		 6719 err = -ETIMEDOUT;
6720 } else {
c6049cd9 6721 err = 0;
4b42d557 6722 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
c6049cd9 6723
28fa68fc 6724 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7a3e97b0 6725 }
e2933132 6726
b557217c 6727 spin_lock_irqsave(hba->host->host_lock, flags);
f5ef336f 6728 hba->tmf_rqs[req->tag] = NULL;
4b42d557 6729 __clear_bit(task_tag, &hba->outstanding_tasks);
b557217c
SC		 6730 spin_unlock_irqrestore(hba->host->host_lock, flags);
6731
4b42d557 6732 ufshcd_release(hba);
0bf6d96c 6733 blk_mq_free_request(req);
e2933132 6734
7a3e97b0
SY		 6735 return err;
6736}
6737
c6049cd9
CH		 6738/**
6739 * ufshcd_issue_tm_cmd - issues task management commands to controller
6740 * @hba: per adapter instance
6741 * @lun_id: LUN ID to which TM command is sent
6742 * @task_id: task ID to which the TM command is applicable
6743 * @tm_function: task management function opcode
6744 * @tm_response: task management service response return value
6745 *
6746 * Returns non-zero value on error, zero on success.
6747 */
6748static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6749 u8 tm_function, u8 *tm_response)
6750{
6751 struct utp_task_req_desc treq = { { 0 }, };
957d63e7
BVA		 6752 enum utp_ocs ocs_value;
6753 int err;
c6049cd9
CH		 6754
6755 /* Configure task request descriptor */
6756 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6757 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6758
6759 /* Configure task request UPIU */
1352eec8 6760 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
c6049cd9 6761 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
1352eec8 6762 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
c6049cd9
CH		 6763
6764 /*
6765 * The host shall provide the same value for LUN field in the basic
6766 * header and for Input Parameter.
6767 */
1352eec8
GS		 6768 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6769 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
c6049cd9
CH		 6770
6771 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6772 if (err == -ETIMEDOUT)
6773 return err;
6774
6775 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6776 if (ocs_value != OCS_SUCCESS)
6777 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6778 __func__, ocs_value);
6779 else if (tm_response)
1352eec8 6780 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
c6049cd9
CH		 6781 MASK_TM_SERVICE_RESP;
6782 return err;
6783}
6784
5e0a86ee
AA		 6785/**
6786 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6787 * @hba: per-adapter instance
6788 * @req_upiu: upiu request
6789 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6790 * @desc_buff: pointer to descriptor buffer, NULL if NA
6791 * @buff_len: descriptor size, 0 if NA
d0e9760d 6792 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6793 * @desc_op: descriptor operation
6794 *
6795 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6796 * Therefore, it "rides" the device management infrastructure: uses its tag and
6797 * tasks work queues.
6798 *
6799 * Since there is only one available tag for device management commands,
6800 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6801 */
6802static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6803 struct utp_upiu_req *req_upiu,
6804 struct utp_upiu_req *rsp_upiu,
6805 u8 *desc_buff, int *buff_len,
7f674c38 6806 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6807 enum query_opcode desc_op)
6808{
8a686f26 6809 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 6810 const u32 tag = hba->reserved_slot;
5e0a86ee
AA		 6811 struct ufshcd_lrb *lrbp;
6812 int err = 0;
a23064c4 6813 u8 upiu_flags;
5e0a86ee 6814
945c3cca
BVA		 6815 /* Protects use of hba->reserved_slot. */
6816 lockdep_assert_held(&hba->dev_cmd.lock);
5e0a86ee 6817
945c3cca 6818 down_read(&hba->clk_scaling_lock);
5e0a86ee 6819
a45f9371 6820 lrbp = &hba->lrb[tag];
7a7e66c6 6821 WARN_ON(lrbp->cmd);
5e0a86ee 6822 lrbp->cmd = NULL;
5e0a86ee
AA		 6823 lrbp->task_tag = tag;
6824 lrbp->lun = 0;
6825 lrbp->intr_cmd = true;
df043c74 6826 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5e0a86ee
AA		 6827 hba->dev_cmd.type = cmd_type;
6828
51428818 6829 if (hba->ufs_version <= ufshci_version(1, 1))
5e0a86ee 6830 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
51428818 6831 else
5e0a86ee 6832 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5e0a86ee
AA		 6833
6834 /* update the task tag in the request upiu */
6835 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6836
6837 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6838
6839 /* just copy the upiu request as it is */
6840 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6841 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6842 /* The Data Segment Area is optional depending upon the query
6843 * function value. for WRITE DESCRIPTOR, the data segment
6844 * follows right after the tsf.
6845 */
6846 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6847 *buff_len = 0;
6848 }
6849
6850 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6851
6852 hba->dev_cmd.complete = &wait;
6853
10542489 6854 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5e0a86ee 6855
a45f9371 6856 ufshcd_send_command(hba, tag);
5e0a86ee
AA		 6857 /*
6858 * ignore the returning value here - ufshcd_check_query_response is
6859 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6860 * read the response directly ignoring all errors.
6861 */
6862 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6863
6864 /* just copy the upiu response as it is */
6865 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6866 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6867 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6868 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6869 MASK_QUERY_DATA_SEG_LEN;
6870
6871 if (*buff_len >= resp_len) {
6872 memcpy(desc_buff, descp, resp_len);
6873 *buff_len = resp_len;
6874 } else {
3d4881d1
BH		 6875 dev_warn(hba->dev,
6876 "%s: rsp size %d is bigger than buffer size %d",
6877 __func__, resp_len, *buff_len);
4bbbe242
AA		 6878 *buff_len = 0;
6879 err = -EINVAL;
6880 }
6881 }
10542489
BH		 6882 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6883 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
5e0a86ee 6884
5e0a86ee
AA		 6885 up_read(&hba->clk_scaling_lock);
6886 return err;
6887}
6888
6889/**
6890 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6891 * @hba: per-adapter instance
6892 * @req_upiu: upiu request
6893 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6894 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6895 * @desc_buff: pointer to descriptor buffer, NULL if NA
6896 * @buff_len: descriptor size, 0 if NA
6897 * @desc_op: descriptor operation
6898 *
6899 * Supports UTP Transfer requests (nop and query), and UTP Task
6900 * Management requests.
6901 * It is up to the caller to fill the upiu conent properly, as it will
6902 * be copied without any further input validations.
6903 */
6904int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6905 struct utp_upiu_req *req_upiu,
6906 struct utp_upiu_req *rsp_upiu,
6907 int msgcode,
6908 u8 *desc_buff, int *buff_len,
6909 enum query_opcode desc_op)
6910{
6911 int err;
7f674c38 6912 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee 6913 struct utp_task_req_desc treq = { { 0 }, };
957d63e7 6914 enum utp_ocs ocs_value;
5e0a86ee
AA		 6915 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6916
5e0a86ee
AA		 6917 switch (msgcode) {
6918 case UPIU_TRANSACTION_NOP_OUT:
6919 cmd_type = DEV_CMD_TYPE_NOP;
df561f66 6920 fallthrough;
5e0a86ee
AA		 6921 case UPIU_TRANSACTION_QUERY_REQ:
6922 ufshcd_hold(hba, false);
6923 mutex_lock(&hba->dev_cmd.lock);
6924 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6925 desc_buff, buff_len,
6926 cmd_type, desc_op);
6927 mutex_unlock(&hba->dev_cmd.lock);
6928 ufshcd_release(hba);
6929
6930 break;
6931 case UPIU_TRANSACTION_TASK_REQ:
6932 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6933 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6934
1352eec8 6935 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
5e0a86ee
AA		 6936
6937 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6938 if (err == -ETIMEDOUT)
6939 break;
6940
6941 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6942 if (ocs_value != OCS_SUCCESS) {
6943 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6944 ocs_value);
6945 break;
6946 }
6947
1352eec8 6948 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
5e0a86ee
AA		 6949
6950 break;
6951 default:
6952 err = -EINVAL;
6953
6954 break;
6955 }
6956
5e0a86ee
AA		 6957 return err;
6958}
6959
7a3e97b0 6960/**
3441da7d
SRT		 6961 * ufshcd_eh_device_reset_handler - device reset handler registered to
6962 * scsi layer.
7a3e97b0
SY		 6963 * @cmd: SCSI command pointer
6964 *
6965 * Returns SUCCESS/FAILED
6966 */
3441da7d 6967static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6968{
6969 struct Scsi_Host *host;
6970 struct ufs_hba *hba;
7a3e97b0
SY		 6971 u32 pos;
6972 int err;
35fc4cd3 6973 u8 resp = 0xF, lun;
7a3e97b0
SY		 6974
6975 host = cmd->device->host;
6976 hba = shost_priv(host);
7a3e97b0 6977
35fc4cd3
CG		 6978 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6979 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
e2933132 6980 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6981 if (!err)
6982 err = resp;
7a3e97b0 6983 goto out;
e2933132 6984 }
7a3e97b0 6985
3441da7d
SRT		 6986 /* clear the commands that were pending for corresponding LUN */
6987 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
35fc4cd3 6988 if (hba->lrb[pos].lun == lun) {
3441da7d
SRT		 6989 err = ufshcd_clear_cmd(hba, pos);
6990 if (err)
6991 break;
11682523 6992 __ufshcd_transfer_req_compl(hba, 1U << pos);
7a3e97b0 6993 }
3441da7d 6994 }
7fabb77b 6995
7a3e97b0 6996out:
7fabb77b 6997 hba->req_abort_count = 0;
e965e5e0 6998 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
3441da7d
SRT		 6999 if (!err) {
7000 err = SUCCESS;
7001 } else {
7002 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7003 err = FAILED;
7004 }
7a3e97b0
SY		 7005 return err;
7006}
7007
e0b299e3
GB		 7008static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7009{
7010 struct ufshcd_lrb *lrbp;
7011 int tag;
7012
7013 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7014 lrbp = &hba->lrb[tag];
7015 lrbp->req_abort_skip = true;
7016 }
7017}
7018
7a3e97b0 7019/**
307348f6 7020 * ufshcd_try_to_abort_task - abort a specific task
d23ec0b6
LJ		 7021 * @hba: Pointer to adapter instance
7022 * @tag: Task tag/index to be aborted
7a3e97b0 7023 *
f20810d8
SRT		 7024 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7025 * command, and in host controller by clearing the door-bell register. There can
7026 * be race between controller sending the command to the device while abort is
7027 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7028 * really issued and then try to abort it.
7029 *
307348f6
CG		 7030 * Returns zero on success, non-zero on failure
7031 */
7032static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7033{
7034 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7035 int err = 0;
7036 int poll_cnt;
7037 u8 resp = 0xF;
7038 u32 reg;
7039
7040 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7041 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7042 UFS_QUERY_TASK, &resp);
7043 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7044 /* cmd pending in the device */
7045 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7046 __func__, tag);
7047 break;
7048 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7049 /*
7050 * cmd not pending in the device, check if it is
7051 * in transition.
7052 */
7053 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7054 __func__, tag);
7055 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7056 if (reg & (1 << tag)) {
7057 /* sleep for max. 200us to stabilize */
7058 usleep_range(100, 200);
7059 continue;
7060 }
7061 /* command completed already */
7062 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7063 __func__, tag);
7064 goto out;
7065 } else {
7066 dev_err(hba->dev,
7067 "%s: no response from device. tag = %d, err %d\n",
7068 __func__, tag, err);
7069 if (!err)
7070 err = resp; /* service response error */
7071 goto out;
7072 }
7073 }
7074
7075 if (!poll_cnt) {
7076 err = -EBUSY;
7077 goto out;
7078 }
7079
7080 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7081 UFS_ABORT_TASK, &resp);
7082 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7083 if (!err) {
7084 err = resp; /* service response error */
7085 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7086 __func__, tag, err);
7087 }
7088 goto out;
7089 }
7090
7091 err = ufshcd_clear_cmd(hba, tag);
7092 if (err)
7093 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7094 __func__, tag, err);
7095
7096out:
7097 return err;
7098}
7099
7100/**
7101 * ufshcd_abort - scsi host template eh_abort_handler callback
7102 * @cmd: SCSI command pointer
7103 *
7a3e97b0
SY		 7104 * Returns SUCCESS/FAILED
7105 */
7106static int ufshcd_abort(struct scsi_cmnd *cmd)
7107{
4728ab4a
BVA		 7108 struct Scsi_Host *host = cmd->device->host;
7109 struct ufs_hba *hba = shost_priv(host);
3f2c1002 7110 int tag = scsi_cmd_to_rq(cmd)->tag;
4728ab4a 7111 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7a3e97b0 7112 unsigned long flags;
64180742 7113 int err = FAILED;
1fbaa02d 7114 bool outstanding;
e9d501b1 7115 u32 reg;
7a3e97b0 7116
4728ab4a 7117 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7a3e97b0 7118
1ab27c9c 7119 ufshcd_hold(hba, false);
14497328 7120 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
64180742 7121 /* If command is already aborted/completed, return FAILED. */
14497328
YG		 7122 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7123 dev_err(hba->dev,
7124 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7125 __func__, tag, hba->outstanding_reqs, reg);
64180742 7126 goto release;
14497328 7127 }
7a3e97b0 7128
66cc820f 7129 /* Print Transfer Request of aborted task */
d87a1f6d 7130 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 7131
7fabb77b
GB		 7132 /*
7133 * Print detailed info about aborted request.
7134 * As more than one request might get aborted at the same time,
7135 * print full information only for the first aborted request in order
7136 * to reduce repeated printouts. For other aborted requests only print
7137 * basic details.
7138 */
7a7e66c6 7139 scsi_print_command(cmd);
7fabb77b 7140 if (!hba->req_abort_count) {
e965e5e0
SC		 7141 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7142 ufshcd_print_evt_hist(hba);
6ba65588 7143 ufshcd_print_host_state(hba);
7fabb77b
GB		 7144 ufshcd_print_pwr_info(hba);
7145 ufshcd_print_trs(hba, 1 << tag, true);
7146 } else {
7147 ufshcd_print_trs(hba, 1 << tag, false);
7148 }
7149 hba->req_abort_count++;
e0b299e3 7150
d87a1f6d
BH		 7151 if (!(reg & (1 << tag))) {
7152 dev_err(hba->dev,
7153 "%s: cmd was completed, but without a notifying intr, tag = %d",
7154 __func__, tag);
11682523 7155 __ufshcd_transfer_req_compl(hba, 1UL << tag);
64180742 7156 goto release;
d87a1f6d
BH		 7157 }
7158
7a7e66c6
CG		 7159 /*
7160 * Task abort to the device W-LUN is illegal. When this command
7161 * will fail, due to spec violation, scsi err handling next step
7162 * will be to send LU reset which, again, is a spec violation.
7163 * To avoid these unnecessary/illegal steps, first we clean up
a45f9371 7164 * the lrb taken by this cmd and re-set it in outstanding_reqs,
88b09900 7165 * then queue the eh_work and bail.
7a7e66c6
CG		 7166 */
7167 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7168 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
64180742 7169
7a7e66c6 7170 spin_lock_irqsave(host->host_lock, flags);
a45f9371 7171 hba->force_reset = true;
88b09900 7172 ufshcd_schedule_eh_work(hba);
7a7e66c6 7173 spin_unlock_irqrestore(host->host_lock, flags);
64180742 7174 goto release;
7a7e66c6
CG		 7175 }
7176
e0b299e3 7177 /* Skip task abort in case previous aborts failed and report failure */
64180742
BVA		 7178 if (lrbp->req_abort_skip) {
7179 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7180 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7181 goto release;
7182 }
f20810d8 7183
64180742
BVA		 7184 err = ufshcd_try_to_abort_task(hba, tag);
7185 if (err) {
f20810d8 7186 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 7187 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8 7188 err = FAILED;
64180742 7189 goto release;
f20810d8
SRT		 7190 }
7191
1fbaa02d
BVA		 7192 /*
7193 * Clear the corresponding bit from outstanding_reqs since the command
7194 * has been aborted successfully.
7195 */
7196 spin_lock_irqsave(&hba->outstanding_lock, flags);
7197 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7198 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7199
7200 if (outstanding)
7201 ufshcd_release_scsi_cmd(hba, lrbp);
7202
64180742
BVA		 7203 err = SUCCESS;
7204
7205release:
7206 /* Matches the ufshcd_hold() call at the start of this function. */
1ab27c9c 7207 ufshcd_release(hba);
7a3e97b0
SY		 7208 return err;
7209}
7210
3441da7d
SRT		 7211/**
7212 * ufshcd_host_reset_and_restore - reset and restore host controller
7213 * @hba: per-adapter instance
7214 *
7215 * Note that host controller reset may issue DME_RESET to
7216 * local and remote (device) Uni-Pro stack and the attributes
7217 * are reset to default state.
7218 *
7219 * Returns zero on success, non-zero on failure
7220 */
7221static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7222{
7223 int err;
3441da7d 7224
2df74b69
CG		 7225 /*
7226 * Stop the host controller and complete the requests
7227 * cleared by h/w
7228 */
f02bc975 7229 ufshpb_reset_host(hba);
5cac1095 7230 ufshcd_hba_stop(hba);
2df74b69 7231 hba->silence_err_logs = true;
11682523 7232 ufshcd_complete_requests(hba);
2df74b69 7233 hba->silence_err_logs = false;
3441da7d 7234
a3cd5ec5 7235 /* scale up clocks to max frequency before full reinitialization */
394b949f 7236 ufshcd_set_clk_freq(hba, true);
a3cd5ec5 7237
3441da7d 7238 err = ufshcd_hba_enable(hba);
3441da7d
SRT		 7239
7240 /* Establish the link again and restore the device */
1918651f 7241 if (!err)
4ee7ee53
JK		 7242 err = ufshcd_probe_hba(hba, false);
7243
3441da7d
SRT		 7244 if (err)
7245 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
e965e5e0 7246 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
3441da7d
SRT		 7247 return err;
7248}
7249
7250/**
7251 * ufshcd_reset_and_restore - reset and re-initialize host/device
7252 * @hba: per-adapter instance
7253 *
7254 * Reset and recover device, host and re-establish link. This
7255 * is helpful to recover the communication in fatal error conditions.
7256 *
7257 * Returns zero on success, non-zero on failure
7258 */
7259static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7260{
54a40453
AH		 7261 u32 saved_err = 0;
7262 u32 saved_uic_err = 0;
3441da7d 7263 int err = 0;
4db7a236 7264 unsigned long flags;
1d337ec2 7265 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 7266
4db7a236 7267 spin_lock_irqsave(hba->host->host_lock, flags);
1d337ec2 7268 do {
54a40453
AH		 7269 /*
7270 * This is a fresh start, cache and clear saved error first,
7271 * in case new error generated during reset and restore.
7272 */
7273 saved_err |= hba->saved_err;
7274 saved_uic_err |= hba->saved_uic_err;
7275 hba->saved_err = 0;
7276 hba->saved_uic_err = 0;
7277 hba->force_reset = false;
7278 hba->ufshcd_state = UFSHCD_STATE_RESET;
7279 spin_unlock_irqrestore(hba->host->host_lock, flags);
7280
d8d9f793 7281 /* Reset the attached device */
31a5d9ca 7282 ufshcd_device_reset(hba);
d8d9f793 7283
1d337ec2 7284 err = ufshcd_host_reset_and_restore(hba);
54a40453
AH		 7285
7286 spin_lock_irqsave(hba->host->host_lock, flags);
7287 if (err)
7288 continue;
7289 /* Do not exit unless operational or dead */
7290 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7291 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7292 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7293 err = -EAGAIN;
1d337ec2 7294 } while (err && --retries);
3441da7d 7295
4db7a236
CG		 7296 /*
7297 * Inform scsi mid-layer that we did reset and allow to handle
7298 * Unit Attention properly.
7299 */
7300 scsi_report_bus_reset(hba->host, 0);
7301 if (err) {
88a92d6a 7302 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4db7a236
CG		 7303 hba->saved_err |= saved_err;
7304 hba->saved_uic_err |= saved_uic_err;
7305 }
7306 spin_unlock_irqrestore(hba->host->host_lock, flags);
7307
3441da7d
SRT		 7308 return err;
7309}
7310
7311/**
7312 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 7313 * @cmd: SCSI command pointer
3441da7d
SRT		 7314 *
7315 * Returns SUCCESS/FAILED
7316 */
7317static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7318{
4db7a236 7319 int err = SUCCESS;
3441da7d
SRT		 7320 unsigned long flags;
7321 struct ufs_hba *hba;
7322
7323 hba = shost_priv(cmd->device->host);
7324
4db7a236
CG		 7325 spin_lock_irqsave(hba->host->host_lock, flags);
7326 hba->force_reset = true;
88b09900 7327 ufshcd_schedule_eh_work(hba);
4db7a236 7328 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
3441da7d
SRT		 7329 spin_unlock_irqrestore(hba->host->host_lock, flags);
7330
88b09900 7331 flush_work(&hba->eh_work);
3441da7d
SRT		 7332
7333 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236 7334 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
3441da7d 7335 err = FAILED;
3441da7d
SRT		 7336 spin_unlock_irqrestore(hba->host->host_lock, flags);
7337
7338 return err;
7339}
7340
3a4bf06d
YG		 7341/**
7342 * ufshcd_get_max_icc_level - calculate the ICC level
7343 * @sup_curr_uA: max. current supported by the regulator
7344 * @start_scan: row at the desc table to start scan from
7345 * @buff: power descriptor buffer
7346 *
7347 * Returns calculated max ICC level for specific regulator
7348 */
7349static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7350{
7351 int i;
7352 int curr_uA;
7353 u16 data;
7354 u16 unit;
7355
7356 for (i = start_scan; i >= 0; i--) {
9d3ab17e 7357 data = get_unaligned_be16(&buff[2 * i]);
3a4bf06d
YG		 7358 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7359 ATTR_ICC_LVL_UNIT_OFFSET;
7360 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7361 switch (unit) {
7362 case UFSHCD_NANO_AMP:
7363 curr_uA = curr_uA / 1000;
7364 break;
7365 case UFSHCD_MILI_AMP:
7366 curr_uA = curr_uA * 1000;
7367 break;
7368 case UFSHCD_AMP:
7369 curr_uA = curr_uA * 1000 * 1000;
7370 break;
7371 case UFSHCD_MICRO_AMP:
7372 default:
7373 break;
7374 }
7375 if (sup_curr_uA >= curr_uA)
7376 break;
7377 }
7378 if (i < 0) {
7379 i = 0;
7380 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7381 }
7382
7383 return (u32)i;
7384}
7385
7386/**
11eea9b3 7387 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
3a4bf06d
YG		 7388 * In case regulators are not initialized we'll return 0
7389 * @hba: per-adapter instance
7390 * @desc_buf: power descriptor buffer to extract ICC levels from.
7391 * @len: length of desc_buff
7392 *
7393 * Returns calculated ICC level
7394 */
7395static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7396 u8 *desc_buf, int len)
7397{
7398 u32 icc_level = 0;
7399
7400 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7401 !hba->vreg_info.vccq2) {
71bb9ab6
AH		 7402 /*
7403 * Using dev_dbg to avoid messages during runtime PM to avoid
7404 * never-ending cycles of messages written back to storage by
7405 * user space causing runtime resume, causing more messages and
7406 * so on.
7407 */
7408 dev_dbg(hba->dev,
3a4bf06d
YG		 7409 "%s: Regulator capability was not set, actvIccLevel=%d",
7410 __func__, icc_level);
7411 goto out;
7412 }
7413
0873045f 7414 if (hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 7415 icc_level = ufshcd_get_max_icc_level(
7416 hba->vreg_info.vcc->max_uA,
7417 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7418 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7419
0873045f 7420 if (hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 7421 icc_level = ufshcd_get_max_icc_level(
7422 hba->vreg_info.vccq->max_uA,
7423 icc_level,
7424 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7425
0873045f 7426 if (hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 7427 icc_level = ufshcd_get_max_icc_level(
7428 hba->vreg_info.vccq2->max_uA,
7429 icc_level,
7430 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7431out:
7432 return icc_level;
7433}
7434
e89860f1 7435static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 7436{
7437 int ret;
7a0bf85b 7438 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
bbe21d7a 7439 u8 *desc_buf;
e89860f1 7440 u32 icc_level;
bbe21d7a
KC		 7441
7442 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7443 if (!desc_buf)
7444 return;
3a4bf06d 7445
c4607a09
BH		 7446 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7447 desc_buf, buff_len);
3a4bf06d
YG		 7448 if (ret) {
7449 dev_err(hba->dev,
7450 "%s: Failed reading power descriptor.len = %d ret = %d",
7451 __func__, buff_len, ret);
bbe21d7a 7452 goto out;
3a4bf06d
YG		 7453 }
7454
e89860f1
CG		 7455 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7456 buff_len);
7457 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 7458
dbd34a61 7459 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 7460 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 7461
7462 if (ret)
7463 dev_err(hba->dev,
7464 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 7465 __func__, icc_level, ret);
3a4bf06d 7466
bbe21d7a
KC		 7467out:
7468 kfree(desc_buf);
3a4bf06d
YG		 7469}
7470
fb276f77
CG		 7471static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7472{
7473 scsi_autopm_get_device(sdev);
7474 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7475 if (sdev->rpm_autosuspend)
7476 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7477 RPM_AUTOSUSPEND_DELAY_MS);
7478 scsi_autopm_put_device(sdev);
7479}
7480
2a8fa600
SJ		 7481/**
7482 * ufshcd_scsi_add_wlus - Adds required W-LUs
7483 * @hba: per-adapter instance
7484 *
7485 * UFS device specification requires the UFS devices to support 4 well known
7486 * logical units:
7487 * "REPORT_LUNS" (address: 01h)
7488 * "UFS Device" (address: 50h)
7489 * "RPMB" (address: 44h)
7490 * "BOOT" (address: 30h)
7491 * UFS device's power management needs to be controlled by "POWER CONDITION"
7492 * field of SSU (START STOP UNIT) command. But this "power condition" field
7493 * will take effect only when its sent to "UFS device" well known logical unit
7494 * hence we require the scsi_device instance to represent this logical unit in
7495 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 7496 *
2a8fa600
SJ		 7497 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7498 * Block) LU so user space process can control this LU. User space may also
7499 * want to have access to BOOT LU.
8aa29f19 7500 *
2a8fa600
SJ		 7501 * This function adds scsi device instances for each of all well known LUs
7502 * (except "REPORT LUNS" LU).
7503 *
7504 * Returns zero on success (all required W-LUs are added successfully),
7505 * non-zero error value on failure (if failed to add any of the required W-LU).
7506 */
7507static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7508{
7509 int ret = 0;
59830c09 7510 struct scsi_device *sdev_boot, *sdev_rpmb;
2a8fa600 7511
e2106584 7512 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7513 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
e2106584
BVA		 7514 if (IS_ERR(hba->ufs_device_wlun)) {
7515 ret = PTR_ERR(hba->ufs_device_wlun);
7516 hba->ufs_device_wlun = NULL;
2a8fa600
SJ		 7517 goto out;
7518 }
e2106584 7519 scsi_device_put(hba->ufs_device_wlun);
2a8fa600 7520
59830c09 7521 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7522 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
59830c09
BVA		 7523 if (IS_ERR(sdev_rpmb)) {
7524 ret = PTR_ERR(sdev_rpmb);
e2106584 7525 goto remove_ufs_device_wlun;
2a8fa600 7526 }
59830c09
BVA		 7527 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7528 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 7529
7530 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7531 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 7532 if (IS_ERR(sdev_boot)) {
3d21fbde 7533 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 7534 } else {
7535 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 7536 scsi_device_put(sdev_boot);
fb276f77 7537 }
2a8fa600
SJ		 7538 goto out;
7539
e2106584
BVA		 7540remove_ufs_device_wlun:
7541 scsi_remove_device(hba->ufs_device_wlun);
2a8fa600
SJ		 7542out:
7543 return ret;
7544}
7545
3d17b9b5
AD		 7546static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7547{
a7f1e69d 7548 struct ufs_dev_info *dev_info = &hba->dev_info;
6f8d5a6a
SC		 7549 u8 lun;
7550 u32 d_lu_wb_buf_alloc;
e8d03813 7551 u32 ext_ufs_feature;
6f8d5a6a 7552
817d7e14
SC		 7553 if (!ufshcd_is_wb_allowed(hba))
7554 return;
f681d107 7555
a7f1e69d
SC		 7556 /*
7557 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7558 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7559 * enabled
7560 */
7561 if (!(dev_info->wspecversion >= 0x310 ||
7562 dev_info->wspecversion == 0x220 ||
7563 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7564 goto wb_disabled;
817d7e14 7565
7a0bf85b
BH		 7566 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7567 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
817d7e14
SC		 7568 goto wb_disabled;
7569
e8d03813
BH		 7570 ext_ufs_feature = get_unaligned_be32(desc_buf +
7571 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
817d7e14 7572
e8d03813 7573 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
817d7e14
SC		 7574 goto wb_disabled;
7575
3d17b9b5 7576 /*
ae1ce1fc
BH		 7577 * WB may be supported but not configured while provisioning. The spec
7578 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7579 * buffer configured.
3d17b9b5 7580 */
4cd48995 7581 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
3d17b9b5 7582
a7f1e69d 7583 dev_info->b_presrv_uspc_en =
3d17b9b5
AD		 7584 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7585
4cd48995 7586 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
e8d03813
BH		 7587 if (!get_unaligned_be32(desc_buf +
7588 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
6f8d5a6a
SC		 7589 goto wb_disabled;
7590 } else {
7591 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7592 d_lu_wb_buf_alloc = 0;
7593 ufshcd_read_unit_desc_param(hba,
7594 lun,
7595 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7596 (u8 *)&d_lu_wb_buf_alloc,
7597 sizeof(d_lu_wb_buf_alloc));
7598 if (d_lu_wb_buf_alloc) {
a7f1e69d 7599 dev_info->wb_dedicated_lu = lun;
6f8d5a6a
SC		 7600 break;
7601 }
7602 }
817d7e14 7603
6f8d5a6a
SC		 7604 if (!d_lu_wb_buf_alloc)
7605 goto wb_disabled;
7606 }
f681d107
JC		 7607
7608 if (!ufshcd_is_wb_buf_lifetime_available(hba))
7609 goto wb_disabled;
7610
817d7e14
SC		 7611 return;
7612
7613wb_disabled:
7614 hba->caps &= ~UFSHCD_CAP_WB_EN;
7615}
7616
e88e2d32
AA		 7617static void ufshcd_temp_notif_probe(struct ufs_hba *hba, u8 *desc_buf)
7618{
7619 struct ufs_dev_info *dev_info = &hba->dev_info;
7620 u32 ext_ufs_feature;
7621 u8 mask = 0;
7622
7623 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7624 return;
7625
7626 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7627
7628 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7629 mask |= MASK_EE_TOO_LOW_TEMP;
7630
7631 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7632 mask |= MASK_EE_TOO_HIGH_TEMP;
7633
7634 if (mask) {
7635 ufshcd_enable_ee(hba, mask);
7636 ufs_hwmon_probe(hba, mask);
7637 }
7638}
7639
aead21f3
BVA		 7640void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
7641 const struct ufs_dev_quirk *fixups)
817d7e14 7642{
aead21f3 7643 const struct ufs_dev_quirk *f;
817d7e14
SC		 7644 struct ufs_dev_info *dev_info = &hba->dev_info;
7645
8db269a5
SC		 7646 if (!fixups)
7647 return;
7648
7649 for (f = fixups; f->quirk; f++) {
817d7e14
SC		 7650 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7651 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7652 ((dev_info->model &&
7653 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7654 !strcmp(f->model, UFS_ANY_MODEL)))
7655 hba->dev_quirks |= f->quirk;
7656 }
3d17b9b5 7657}
8db269a5 7658EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
3d17b9b5 7659
c28c00ba
SC		 7660static void ufs_fixup_device_setup(struct ufs_hba *hba)
7661{
7662 /* fix by general quirk table */
8db269a5 7663 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
c28c00ba
SC		 7664
7665 /* allow vendors to fix quirks */
7666 ufshcd_vops_fixup_dev_quirks(hba);
7667}
7668
09750066 7669static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 7670{
7671 int err;
7672 u8 model_index;
f02bc975 7673 u8 b_ufs_feature_sup;
bbe21d7a 7674 u8 *desc_buf;
09750066 7675 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 7676
458a45f5 7677 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 7678 if (!desc_buf) {
7679 err = -ENOMEM;
7680 goto out;
7681 }
c58ab7aa 7682
c4607a09 7683 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7a0bf85b 7684 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
c58ab7aa
YG		 7685 if (err) {
7686 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7687 __func__, err);
7688 goto out;
7689 }
7690
7691 /*
7692 * getting vendor (manufacturerID) and Bank Index in big endian
7693 * format
7694 */
09750066 7695 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 7696 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7697
09f17791
CG		 7698 /* getting Specification Version in big endian format */
7699 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7700 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
f02bc975 7701 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
09f17791 7702
c58ab7aa 7703 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5 7704
f02bc975
DP		 7705 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7706 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
41d8a933
DP		 7707 bool hpb_en = false;
7708
f02bc975 7709 ufshpb_get_dev_info(hba, desc_buf);
41d8a933
DP		 7710
7711 if (!ufshpb_is_legacy(hba))
7712 err = ufshcd_query_flag_retry(hba,
7713 UPIU_QUERY_OPCODE_READ_FLAG,
7714 QUERY_FLAG_IDN_HPB_EN, 0,
7715 &hpb_en);
7716
7717 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7718 dev_info->hpb_enabled = true;
f02bc975
DP		 7719 }
7720
4b828fe1 7721 err = ufshcd_read_string_desc(hba, model_index,
09750066 7722 &dev_info->model, SD_ASCII_STD);
4b828fe1 7723 if (err < 0) {
c58ab7aa
YG		 7724 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7725 __func__, err);
7726 goto out;
7727 }
7728
b294ff3e
AD		 7729 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7730 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7731
817d7e14
SC		 7732 ufs_fixup_device_setup(hba);
7733
a7f1e69d 7734 ufshcd_wb_probe(hba, desc_buf);
817d7e14 7735
e88e2d32
AA		 7736 ufshcd_temp_notif_probe(hba, desc_buf);
7737
4b828fe1
TW		 7738 /*
7739 * ufshcd_read_string_desc returns size of the string
7740 * reset the error value
7741 */
7742 err = 0;
c58ab7aa
YG		 7743
7744out:
bbe21d7a 7745 kfree(desc_buf);
c58ab7aa
YG		 7746 return err;
7747}
7748
09750066 7749static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 7750{
09750066
BH		 7751 struct ufs_dev_info *dev_info = &hba->dev_info;
7752
7753 kfree(dev_info->model);
7754 dev_info->model = NULL;
4b828fe1
TW		 7755}
7756
37113106
YG		 7757/**
7758 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7759 * @hba: per-adapter instance
7760 *
7761 * PA_TActivate parameter can be tuned manually if UniPro version is less than
7762 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7763 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7764 * the hibern8 exit latency.
7765 *
7766 * Returns zero on success, non-zero error value on failure.
7767 */
7768static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7769{
7770 int ret = 0;
7771 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7772
7773 ret = ufshcd_dme_peer_get(hba,
7774 UIC_ARG_MIB_SEL(
7775 RX_MIN_ACTIVATETIME_CAPABILITY,
7776 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7777 &peer_rx_min_activatetime);
7778 if (ret)
7779 goto out;
7780
7781 /* make sure proper unit conversion is applied */
7782 tuned_pa_tactivate =
7783 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7784 / PA_TACTIVATE_TIME_UNIT_US);
7785 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7786 tuned_pa_tactivate);
7787
7788out:
7789 return ret;
7790}
7791
7792/**
7793 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7794 * @hba: per-adapter instance
7795 *
7796 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7797 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7798 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7799 * This optimal value can help reduce the hibern8 exit latency.
7800 *
7801 * Returns zero on success, non-zero error value on failure.
7802 */
7803static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7804{
7805 int ret = 0;
7806 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7807 u32 max_hibern8_time, tuned_pa_hibern8time;
7808
7809 ret = ufshcd_dme_get(hba,
7810 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7811 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7812 &local_tx_hibern8_time_cap);
7813 if (ret)
7814 goto out;
7815
7816 ret = ufshcd_dme_peer_get(hba,
7817 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7818 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7819 &peer_rx_hibern8_time_cap);
7820 if (ret)
7821 goto out;
7822
7823 max_hibern8_time = max(local_tx_hibern8_time_cap,
7824 peer_rx_hibern8_time_cap);
7825 /* make sure proper unit conversion is applied */
7826 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7827 / PA_HIBERN8_TIME_UNIT_US);
7828 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7829 tuned_pa_hibern8time);
7830out:
7831 return ret;
7832}
7833
c6a6db43 7834/**
7835 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7836 * less than device PA_TACTIVATE time.
7837 * @hba: per-adapter instance
7838 *
7839 * Some UFS devices require host PA_TACTIVATE to be lower than device
7840 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7841 * for such devices.
7842 *
7843 * Returns zero on success, non-zero error value on failure.
7844 */
7845static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7846{
7847 int ret = 0;
7848 u32 granularity, peer_granularity;
7849 u32 pa_tactivate, peer_pa_tactivate;
7850 u32 pa_tactivate_us, peer_pa_tactivate_us;
7851 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7852
7853 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7854 &granularity);
7855 if (ret)
7856 goto out;
7857
7858 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7859 &peer_granularity);
7860 if (ret)
7861 goto out;
7862
7863 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7864 (granularity > PA_GRANULARITY_MAX_VAL)) {
7865 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7866 __func__, granularity);
7867 return -EINVAL;
7868 }
7869
7870 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7871 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7872 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7873 __func__, peer_granularity);
7874 return -EINVAL;
7875 }
7876
7877 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7878 if (ret)
7879 goto out;
7880
7881 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7882 &peer_pa_tactivate);
7883 if (ret)
7884 goto out;
7885
7886 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7887 peer_pa_tactivate_us = peer_pa_tactivate *
7888 gran_to_us_table[peer_granularity - 1];
7889
9008661e 7890 if (pa_tactivate_us >= peer_pa_tactivate_us) {
c6a6db43 7891 u32 new_peer_pa_tactivate;
7892
7893 new_peer_pa_tactivate = pa_tactivate_us /
7894 gran_to_us_table[peer_granularity - 1];
7895 new_peer_pa_tactivate++;
7896 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7897 new_peer_pa_tactivate);
7898 }
7899
7900out:
7901 return ret;
7902}
7903
09750066 7904static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 7905{
7906 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7907 ufshcd_tune_pa_tactivate(hba);
7908 ufshcd_tune_pa_hibern8time(hba);
7909 }
7910
e91ed9e0
CG		 7911 ufshcd_vops_apply_dev_quirks(hba);
7912
37113106
YG		 7913 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7914 /* set 1ms timeout for PA_TACTIVATE */
7915 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 7916
7917 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7918 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 7919}
7920
ff8e20c6
DR		 7921static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7922{
ff8e20c6
DR		 7923 hba->ufs_stats.hibern8_exit_cnt = 0;
7924 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 7925 hba->req_abort_count = 0;
ff8e20c6
DR		 7926}
7927
731f0621
BH		 7928static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7929{
7930 int err;
7931 size_t buff_len;
7932 u8 *desc_buf;
7933
7a0bf85b 7934 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
731f0621
BH		 7935 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7936 if (!desc_buf) {
7937 err = -ENOMEM;
7938 goto out;
7939 }
7940
c4607a09
BH		 7941 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7942 desc_buf, buff_len);
731f0621
BH		 7943 if (err) {
7944 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7945 __func__, err);
7946 goto out;
7947 }
7948
7949 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7950 hba->dev_info.max_lu_supported = 32;
7951 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7952 hba->dev_info.max_lu_supported = 8;
7953
f02bc975
DP		 7954 if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7955 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7956 ufshpb_get_geo_info(hba, desc_buf);
7957
731f0621
BH		 7958out:
7959 kfree(desc_buf);
7960 return err;
7961}
7962
743b09d8
BVA		 7963struct ufs_ref_clk {
7964 unsigned long freq_hz;
7965 enum ufs_ref_clk_freq val;
7966};
7967
9e1e8a75
SJ		 7968static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7969 {19200000, REF_CLK_FREQ_19_2_MHZ},
7970 {26000000, REF_CLK_FREQ_26_MHZ},
7971 {38400000, REF_CLK_FREQ_38_4_MHZ},
7972 {52000000, REF_CLK_FREQ_52_MHZ},
7973 {0, REF_CLK_FREQ_INVAL},
7974};
7975
7976static enum ufs_ref_clk_freq
7977ufs_get_bref_clk_from_hz(unsigned long freq)
7978{
7979 int i;
7980
7981 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7982 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7983 return ufs_ref_clk_freqs[i].val;
7984
7985 return REF_CLK_FREQ_INVAL;
7986}
7987
7988void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7989{
7990 unsigned long freq;
7991
7992 freq = clk_get_rate(refclk);
7993
7994 hba->dev_ref_clk_freq =
7995 ufs_get_bref_clk_from_hz(freq);
7996
7997 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7998 dev_err(hba->dev,
7999 "invalid ref_clk setting = %ld\n", freq);
8000}
8001
8002static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8003{
8004 int err;
8005 u32 ref_clk;
8006 u32 freq = hba->dev_ref_clk_freq;
8007
8008 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8009 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8010
8011 if (err) {
8012 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8013 err);
8014 goto out;
8015 }
8016
8017 if (ref_clk == freq)
8018 goto out; /* nothing to update */
8019
8020 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8021 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8022
8023 if (err) {
8024 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8025 ufs_ref_clk_freqs[freq].freq_hz);
8026 goto out;
8027 }
8028
8029 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8030 ufs_ref_clk_freqs[freq].freq_hz);
8031
8032out:
8033 return err;
8034}
8035
1b9e2141
BH		 8036static int ufshcd_device_params_init(struct ufs_hba *hba)
8037{
8038 bool flag;
7a0bf85b 8039 int ret, i;
1b9e2141 8040
7a0bf85b
BH		 8041 /* Init device descriptor sizes */
8042 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
8043 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
1b9e2141 8044
731f0621
BH		 8045 /* Init UFS geometry descriptor related parameters */
8046 ret = ufshcd_device_geo_params_init(hba);
8047 if (ret)
8048 goto out;
8049
1b9e2141
BH		 8050 /* Check and apply UFS device quirks */
8051 ret = ufs_get_device_desc(hba);
8052 if (ret) {
8053 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8054 __func__, ret);
8055 goto out;
8056 }
8057
09f17791
CG		 8058 ufshcd_get_ref_clk_gating_wait(hba);
8059
1b9e2141 8060 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 8061 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
1b9e2141
BH		 8062 hba->dev_info.f_power_on_wp_en = flag;
8063
2b35b2ad
BH		 8064 /* Probe maximum power mode co-supported by both UFS host and device */
8065 if (ufshcd_get_max_pwr_mode(hba))
8066 dev_err(hba->dev,
8067 "%s: Failed getting max supported power mode\n",
8068 __func__);
1b9e2141
BH		 8069out:
8070 return ret;
8071}
8072
8073/**
8074 * ufshcd_add_lus - probe and add UFS logical units
8075 * @hba: per-adapter instance
8076 */
8077static int ufshcd_add_lus(struct ufs_hba *hba)
8078{
8079 int ret;
8080
1b9e2141
BH		 8081 /* Add required well known logical units to scsi mid layer */
8082 ret = ufshcd_scsi_add_wlus(hba);
8083 if (ret)
8084 goto out;
8085
8086 /* Initialize devfreq after UFS device is detected */
8087 if (ufshcd_is_clkscaling_supported(hba)) {
8088 memcpy(&hba->clk_scaling.saved_pwr_info.info,
8089 &hba->pwr_info,
8090 sizeof(struct ufs_pa_layer_attr));
8091 hba->clk_scaling.saved_pwr_info.is_valid = true;
1b9e2141 8092 hba->clk_scaling.is_allowed = true;
1b9e2141 8093
b058fa86
SC		 8094 ret = ufshcd_devfreq_init(hba);
8095 if (ret)
8096 goto out;
8097
8098 hba->clk_scaling.is_enabled = true;
8099 ufshcd_init_clk_scaling_sysfs(hba);
1b9e2141
BH		 8100 }
8101
8102 ufs_bsg_probe(hba);
f02bc975 8103 ufshpb_init(hba);
1b9e2141
BH		 8104 scsi_scan_host(hba->host);
8105 pm_runtime_put_sync(hba->dev);
8106
1b9e2141
BH		 8107out:
8108 return ret;
8109}
8110
6ccf44fe 8111/**
568dd995 8112 * ufshcd_probe_hba - probe hba to detect device and initialize it
1d337ec2 8113 * @hba: per-adapter instance
568dd995 8114 * @init_dev_params: whether or not to call ufshcd_device_params_init().
1d337ec2
SRT		 8115 *
8116 * Execute link-startup and verify device initialization
6ccf44fe 8117 */
568dd995 8118static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
6ccf44fe 8119{
6ccf44fe 8120 int ret;
4db7a236 8121 unsigned long flags;
7ff5ab47 8122 ktime_t start = ktime_get();
6ccf44fe 8123
aa53f580
CG		 8124 hba->ufshcd_state = UFSHCD_STATE_RESET;
8125
6ccf44fe 8126 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 8127 if (ret)
8128 goto out;
8129
10fb4f87 8130 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8131 goto out;
8132
ff8e20c6
DR		 8133 /* Debug counters initialization */
8134 ufshcd_clear_dbg_ufs_stats(hba);
8135
57d104c1
SJ		 8136 /* UniPro link is active now */
8137 ufshcd_set_link_active(hba);
d3e89bac 8138
1b9e2141 8139 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 8140 ret = ufshcd_verify_dev_init(hba);
8141 if (ret)
8142 goto out;
68078d5c 8143
1b9e2141 8144 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 8145 ret = ufshcd_complete_dev_init(hba);
8146 if (ret)
8147 goto out;
5a0b0cb9 8148
1b9e2141
BH		 8149 /*
8150 * Initialize UFS device parameters used by driver, these
8151 * parameters are associated with UFS descriptors.
8152 */
568dd995 8153 if (init_dev_params) {
1b9e2141
BH		 8154 ret = ufshcd_device_params_init(hba);
8155 if (ret)
8156 goto out;
93fdd5ac
TW		 8157 }
8158
09750066 8159 ufshcd_tune_unipro_params(hba);
4b828fe1 8160
57d104c1
SJ		 8161 /* UFS device is also active now */
8162 ufshcd_set_ufs_dev_active(hba);
66ec6d59 8163 ufshcd_force_reset_auto_bkops(hba);
57d104c1 8164
2b35b2ad
BH		 8165 /* Gear up to HS gear if supported */
8166 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 8167 /*
8168 * Set the right value to bRefClkFreq before attempting to
8169 * switch to HS gears.
8170 */
8171 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8172 ufshcd_set_dev_ref_clk(hba);
7eb584db 8173 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 8174 if (ret) {
7eb584db
DR		 8175 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8176 __func__, ret);
8643ae66
DL		 8177 goto out;
8178 }
6a9df818 8179 ufshcd_print_pwr_info(hba);
7eb584db 8180 }
57d104c1 8181
e89860f1
CG		 8182 /*
8183 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8184 * and for removable UFS card as well, hence always set the parameter.
8185 * Note: Error handler may issue the device reset hence resetting
8186 * bActiveICCLevel as well so it is always safe to set this here.
8187 */
8188 ufshcd_set_active_icc_lvl(hba);
8189
3d17b9b5 8190 ufshcd_wb_config(hba);
cd469475
AH		 8191 if (hba->ee_usr_mask)
8192 ufshcd_write_ee_control(hba);
71d848b8
CG		 8193 /* Enable Auto-Hibernate if configured */
8194 ufshcd_auto_hibern8_enable(hba);
8195
f02bc975 8196 ufshpb_reset(hba);
5a0b0cb9 8197out:
4db7a236
CG		 8198 spin_lock_irqsave(hba->host->host_lock, flags);
8199 if (ret)
8200 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8201 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8202 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8203 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d337ec2 8204
7ff5ab47 8205 trace_ufshcd_init(dev_name(hba->dev), ret,
8206 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8207 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 8208 return ret;
8209}
8210
8211/**
8212 * ufshcd_async_scan - asynchronous execution for probing hba
8213 * @data: data pointer to pass to this function
8214 * @cookie: cookie data
8215 */
8216static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8217{
8218 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 8219 int ret;
1d337ec2 8220
9cd20d3f 8221 down(&hba->host_sem);
1b9e2141
BH		 8222 /* Initialize hba, detect and initialize UFS device */
8223 ret = ufshcd_probe_hba(hba, true);
9cd20d3f 8224 up(&hba->host_sem);
1b9e2141
BH		 8225 if (ret)
8226 goto out;
8227
8228 /* Probe and add UFS logical units */
8229 ret = ufshcd_add_lus(hba);
8230out:
8231 /*
8232 * If we failed to initialize the device or the device is not
8233 * present, turn off the power/clocks etc.
8234 */
8235 if (ret) {
8236 pm_runtime_put_sync(hba->dev);
1b9e2141
BH		 8237 ufshcd_hba_exit(hba);
8238 }
6ccf44fe
SJ		 8239}
8240
d829fc8a
SN		 8241static const struct attribute_group *ufshcd_driver_groups[] = {
8242 &ufs_sysfs_unit_descriptor_group,
ec92b59c 8243 &ufs_sysfs_lun_attributes_group,
f02bc975
DP		 8244#ifdef CONFIG_SCSI_UFS_HPB
8245 &ufs_sysfs_hpb_stat_group,
41d8a933 8246 &ufs_sysfs_hpb_param_group,
f02bc975 8247#endif
d829fc8a
SN		 8248 NULL,
8249};
8250
90b8491c
SC		 8251static struct ufs_hba_variant_params ufs_hba_vps = {
8252 .hba_enable_delay_us = 1000,
d14734ae 8253 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
90b8491c
SC		 8254 .devfreq_profile.polling_ms = 100,
8255 .devfreq_profile.target = ufshcd_devfreq_target,
8256 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8257 .ondemand_data.upthreshold = 70,
8258 .ondemand_data.downdifferential = 5,
8259};
8260
7a3e97b0
SY		 8261static struct scsi_host_template ufshcd_driver_template = {
8262 .module = THIS_MODULE,
8263 .name = UFSHCD,
8264 .proc_name = UFSHCD,
eaab9b57 8265 .map_queues = ufshcd_map_queues,
7a3e97b0 8266 .queuecommand = ufshcd_queuecommand,
eaab9b57 8267 .mq_poll = ufshcd_poll,
7a3e97b0 8268 .slave_alloc = ufshcd_slave_alloc,
eeda4749 8269 .slave_configure = ufshcd_slave_configure,
7a3e97b0 8270 .slave_destroy = ufshcd_slave_destroy,
4264fd61 8271 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 8272 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 8273 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8274 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 8275 .this_id = -1,
8276 .sg_tablesize = SG_ALL,
8277 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8278 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 8279 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 8280 .max_host_blocked = 1,
c40ecc12 8281 .track_queue_depth = 1,
d829fc8a 8282 .sdev_groups = ufshcd_driver_groups,
4af14d11 8283 .dma_boundary = PAGE_SIZE - 1,
49615ba1 8284 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 8285};
8286
57d104c1
SJ		 8287static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8288 int ua)
8289{
7b16a07c 8290 int ret;
57d104c1 8291
7b16a07c
BA		 8292 if (!vreg)
8293 return 0;
57d104c1 8294
0487fff7
SC		 8295 /*
8296 * "set_load" operation shall be required on those regulators
8297 * which specifically configured current limitation. Otherwise
8298 * zero max_uA may cause unexpected behavior when regulator is
8299 * enabled or set as high power mode.
8300 */
8301 if (!vreg->max_uA)
8302 return 0;
8303
7b16a07c
BA		 8304 ret = regulator_set_load(vreg->reg, ua);
8305 if (ret < 0) {
8306 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8307 __func__, vreg->name, ua, ret);
57d104c1
SJ		 8308 }
8309
8310 return ret;
8311}
8312
8313static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8314 struct ufs_vreg *vreg)
8315{
73067981 8316 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 8317}
8318
8319static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8320 struct ufs_vreg *vreg)
8321{
7c7cfdcf
AH		 8322 if (!vreg)
8323 return 0;
8324
73067981 8325 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 8326}
8327
aa497613
SRT		 8328static int ufshcd_config_vreg(struct device *dev,
8329 struct ufs_vreg *vreg, bool on)
8330{
9474c64e
BVA		 8331 if (regulator_count_voltages(vreg->reg) <= 0)
8332 return 0;
90d88f47 8333
9474c64e 8334 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
aa497613
SRT		 8335}
8336
8337static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8338{
8339 int ret = 0;
8340
73067981 8341 if (!vreg || vreg->enabled)
aa497613
SRT		 8342 goto out;
8343
8344 ret = ufshcd_config_vreg(dev, vreg, true);
8345 if (!ret)
8346 ret = regulator_enable(vreg->reg);
8347
8348 if (!ret)
8349 vreg->enabled = true;
8350 else
8351 dev_err(dev, "%s: %s enable failed, err=%d\n",
8352 __func__, vreg->name, ret);
8353out:
8354 return ret;
8355}
8356
8357static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8358{
8359 int ret = 0;
8360
f8162ac7 8361 if (!vreg || !vreg->enabled || vreg->always_on)
aa497613
SRT		 8362 goto out;
8363
8364 ret = regulator_disable(vreg->reg);
8365
8366 if (!ret) {
8367 /* ignore errors on applying disable config */
8368 ufshcd_config_vreg(dev, vreg, false);
8369 vreg->enabled = false;
8370 } else {
8371 dev_err(dev, "%s: %s disable failed, err=%d\n",
8372 __func__, vreg->name, ret);
8373 }
8374out:
8375 return ret;
8376}
8377
8378static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8379{
8380 int ret = 0;
8381 struct device *dev = hba->dev;
8382 struct ufs_vreg_info *info = &hba->vreg_info;
8383
aa497613
SRT		 8384 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8385 if (ret)
8386 goto out;
8387
8388 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8389 if (ret)
8390 goto out;
8391
8392 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
aa497613
SRT		 8393
8394out:
8395 if (ret) {
8396 ufshcd_toggle_vreg(dev, info->vccq2, false);
8397 ufshcd_toggle_vreg(dev, info->vccq, false);
8398 ufshcd_toggle_vreg(dev, info->vcc, false);
8399 }
8400 return ret;
8401}
8402
6a771a65
RS		 8403static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8404{
8405 struct ufs_vreg_info *info = &hba->vreg_info;
8406
60b7b823 8407 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 8408}
8409
aa497613
SRT		 8410static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8411{
8412 int ret = 0;
8413
8414 if (!vreg)
8415 goto out;
8416
8417 vreg->reg = devm_regulator_get(dev, vreg->name);
8418 if (IS_ERR(vreg->reg)) {
8419 ret = PTR_ERR(vreg->reg);
8420 dev_err(dev, "%s: %s get failed, err=%d\n",
8421 __func__, vreg->name, ret);
8422 }
8423out:
8424 return ret;
8425}
8426
8427static int ufshcd_init_vreg(struct ufs_hba *hba)
8428{
8429 int ret = 0;
8430 struct device *dev = hba->dev;
8431 struct ufs_vreg_info *info = &hba->vreg_info;
8432
aa497613
SRT		 8433 ret = ufshcd_get_vreg(dev, info->vcc);
8434 if (ret)
8435 goto out;
8436
8437 ret = ufshcd_get_vreg(dev, info->vccq);
b0008625
BH		 8438 if (!ret)
8439 ret = ufshcd_get_vreg(dev, info->vccq2);
aa497613
SRT		 8440out:
8441 return ret;
8442}
8443
6a771a65
RS		 8444static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8445{
8446 struct ufs_vreg_info *info = &hba->vreg_info;
8447
8448 if (info)
8449 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8450
8451 return 0;
8452}
8453
81309c24 8454static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
c6e79dac
SRT		 8455{
8456 int ret = 0;
8457 struct ufs_clk_info *clki;
8458 struct list_head *head = &hba->clk_list_head;
1ab27c9c 8459 unsigned long flags;
911a0771 8460 ktime_t start = ktime_get();
8461 bool clk_state_changed = false;
c6e79dac 8462
566ec9ad 8463 if (list_empty(head))
c6e79dac
SRT		 8464 goto out;
8465
38f3242e
CG		 8466 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8467 if (ret)
8468 return ret;
1e879e8f 8469
c6e79dac
SRT		 8470 list_for_each_entry(clki, head, list) {
8471 if (!IS_ERR_OR_NULL(clki->clk)) {
81309c24
CG		 8472 /*
8473 * Don't disable clocks which are needed
8474 * to keep the link active.
8475 */
8476 if (ufshcd_is_link_active(hba) &&
8477 clki->keep_link_active)
57d104c1
SJ		 8478 continue;
8479
911a0771 8480 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 8481 if (on && !clki->enabled) {
8482 ret = clk_prepare_enable(clki->clk);
8483 if (ret) {
8484 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8485 __func__, clki->name, ret);
8486 goto out;
8487 }
8488 } else if (!on && clki->enabled) {
8489 clk_disable_unprepare(clki->clk);
8490 }
8491 clki->enabled = on;
8492 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8493 clki->name, on ? "en" : "dis");
8494 }
8495 }
1ab27c9c 8496
38f3242e
CG		 8497 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8498 if (ret)
8499 return ret;
1e879e8f 8500
c6e79dac
SRT		 8501out:
8502 if (ret) {
8503 list_for_each_entry(clki, head, list) {
8504 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8505 clk_disable_unprepare(clki->clk);
8506 }
7ff5ab47 8507 } else if (!ret && on) {
1ab27c9c
ST		 8508 spin_lock_irqsave(hba->host->host_lock, flags);
8509 hba->clk_gating.state = CLKS_ON;
7ff5ab47 8510 trace_ufshcd_clk_gating(dev_name(hba->dev),
8511 hba->clk_gating.state);
1ab27c9c 8512 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 8513 }
7ff5ab47 8514
911a0771 8515 if (clk_state_changed)
8516 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8517 (on ? "on" : "off"),
8518 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 8519 return ret;
8520}
8521
8522static int ufshcd_init_clocks(struct ufs_hba *hba)
8523{
8524 int ret = 0;
8525 struct ufs_clk_info *clki;
8526 struct device *dev = hba->dev;
8527 struct list_head *head = &hba->clk_list_head;
8528
566ec9ad 8529 if (list_empty(head))
c6e79dac
SRT		 8530 goto out;
8531
8532 list_for_each_entry(clki, head, list) {
8533 if (!clki->name)
8534 continue;
8535
8536 clki->clk = devm_clk_get(dev, clki->name);
8537 if (IS_ERR(clki->clk)) {
8538 ret = PTR_ERR(clki->clk);
8539 dev_err(dev, "%s: %s clk get failed, %d\n",
8540 __func__, clki->name, ret);
8541 goto out;
8542 }
8543
9e1e8a75
SJ		 8544 /*
8545 * Parse device ref clk freq as per device tree "ref_clk".
8546 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8547 * in ufshcd_alloc_host().
8548 */
8549 if (!strcmp(clki->name, "ref_clk"))
8550 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8551
c6e79dac
SRT		 8552 if (clki->max_freq) {
8553 ret = clk_set_rate(clki->clk, clki->max_freq);
8554 if (ret) {
8555 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8556 __func__, clki->name,
8557 clki->max_freq, ret);
8558 goto out;
8559 }
856b3483 8560 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 8561 }
8562 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8563 clki->name, clk_get_rate(clki->clk));
8564 }
8565out:
8566 return ret;
8567}
8568
5c0c28a8
SRT		 8569static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8570{
8571 int err = 0;
8572
8573 if (!hba->vops)
8574 goto out;
8575
0263bcd0 8576 err = ufshcd_vops_init(hba);
5c0c28a8
SRT		 8577 if (err)
8578 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 8579 __func__, ufshcd_get_var_name(hba), err);
ade921a8 8580out:
5c0c28a8
SRT		 8581 return err;
8582}
8583
8584static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8585{
8586 if (!hba->vops)
8587 return;
8588
0263bcd0 8589 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 8590}
8591
aa497613
SRT		 8592static int ufshcd_hba_init(struct ufs_hba *hba)
8593{
8594 int err;
8595
6a771a65
RS		 8596 /*
8597 * Handle host controller power separately from the UFS device power
8598 * rails as it will help controlling the UFS host controller power
8599 * collapse easily which is different than UFS device power collapse.
8600 * Also, enable the host controller power before we go ahead with rest
8601 * of the initialization here.
8602 */
8603 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 8604 if (err)
8605 goto out;
8606
6a771a65 8607 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 8608 if (err)
8609 goto out;
8610
6a771a65
RS		 8611 err = ufshcd_init_clocks(hba);
8612 if (err)
8613 goto out_disable_hba_vreg;
8614
8615 err = ufshcd_setup_clocks(hba, true);
8616 if (err)
8617 goto out_disable_hba_vreg;
8618
c6e79dac
SRT		 8619 err = ufshcd_init_vreg(hba);
8620 if (err)
8621 goto out_disable_clks;
8622
8623 err = ufshcd_setup_vreg(hba, true);
8624 if (err)
8625 goto out_disable_clks;
8626
aa497613
SRT		 8627 err = ufshcd_variant_hba_init(hba);
8628 if (err)
8629 goto out_disable_vreg;
8630
b6cacaf2
AH		 8631 ufs_debugfs_hba_init(hba);
8632
1d337ec2 8633 hba->is_powered = true;
aa497613
SRT		 8634 goto out;
8635
8636out_disable_vreg:
8637 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 8638out_disable_clks:
8639 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 8640out_disable_hba_vreg:
8641 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 8642out:
8643 return err;
8644}
8645
8646static void ufshcd_hba_exit(struct ufs_hba *hba)
8647{
1d337ec2 8648 if (hba->is_powered) {
4543d9d7
CG		 8649 ufshcd_exit_clk_scaling(hba);
8650 ufshcd_exit_clk_gating(hba);
88b09900
AH		 8651 if (hba->eh_wq)
8652 destroy_workqueue(hba->eh_wq);
b6cacaf2 8653 ufs_debugfs_hba_exit(hba);
1d337ec2
SRT		 8654 ufshcd_variant_hba_exit(hba);
8655 ufshcd_setup_vreg(hba, false);
8656 ufshcd_setup_clocks(hba, false);
8657 ufshcd_setup_hba_vreg(hba, false);
8658 hba->is_powered = false;
09750066 8659 ufs_put_device_desc(hba);
1d337ec2 8660 }
aa497613
SRT		 8661}
8662
57d104c1
SJ		 8663/**
8664 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8665 * power mode
8666 * @hba: per adapter instance
8667 * @pwr_mode: device power mode to set
8668 *
8669 * Returns 0 if requested power mode is set successfully
ad6c8a42 8670 * Returns < 0 if failed to set the requested power mode
57d104c1
SJ		 8671 */
8672static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8673 enum ufs_dev_pwr_mode pwr_mode)
8674{
8675 unsigned char cmd[6] = { START_STOP };
8676 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 8677 struct scsi_device *sdp;
8678 unsigned long flags;
af21c3fd 8679 int ret, retries;
57d104c1 8680
7c48bfd0 8681 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584 8682 sdp = hba->ufs_device_wlun;
7c48bfd0
AM		 8683 if (sdp) {
8684 ret = scsi_device_get(sdp);
8685 if (!ret && !scsi_device_online(sdp)) {
8686 ret = -ENODEV;
8687 scsi_device_put(sdp);
8688 }
8689 } else {
8690 ret = -ENODEV;
8691 }
8692 spin_unlock_irqrestore(hba->host->host_lock, flags);
8693
8694 if (ret)
8695 return ret;
57d104c1
SJ		 8696
8697 /*
8698 * If scsi commands fail, the scsi mid-layer schedules scsi error-
8699 * handling, which would wait for host to be resumed. Since we know
8700 * we are functional while we are here, skip host resume in error
8701 * handling context.
8702 */
8703 hba->host->eh_noresume = 1;
57d104c1
SJ		 8704
8705 cmd[4] = pwr_mode << 4;
8706
8707 /*
8708 * Current function would be generally called from the power management
e8064021 8709 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 8710 * already suspended childs.
8711 */
af21c3fd
JK		 8712 for (retries = 3; retries > 0; --retries) {
8713 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8714 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8715 if (!scsi_status_is_check_condition(ret) ||
8716 !scsi_sense_valid(&sshdr) ||
8717 sshdr.sense_key != UNIT_ATTENTION)
8718 break;
8719 }
57d104c1
SJ		 8720 if (ret) {
8721 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 8722 "START_STOP failed for power mode: %d, result %x\n",
8723 pwr_mode, ret);
ad6c8a42
KK		 8724 if (ret > 0) {
8725 if (scsi_sense_valid(&sshdr))
8726 scsi_print_sense_hdr(sdp, NULL, &sshdr);
8727 ret = -EIO;
8728 }
57d104c1
SJ		 8729 }
8730
8731 if (!ret)
8732 hba->curr_dev_pwr_mode = pwr_mode;
1918651f 8733
7c48bfd0 8734 scsi_device_put(sdp);
57d104c1
SJ		 8735 hba->host->eh_noresume = 0;
8736 return ret;
8737}
8738
8739static int ufshcd_link_state_transition(struct ufs_hba *hba,
8740 enum uic_link_state req_link_state,
8741 int check_for_bkops)
8742{
8743 int ret = 0;
8744
8745 if (req_link_state == hba->uic_link_state)
8746 return 0;
8747
8748 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8749 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236 8750 if (!ret) {
57d104c1 8751 ufshcd_set_link_hibern8(hba);
4db7a236
CG		 8752 } else {
8753 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8754 __func__, ret);
57d104c1 8755 goto out;
4db7a236 8756 }
57d104c1
SJ		 8757 }
8758 /*
8759 * If autobkops is enabled, link can't be turned off because
fe1d4c2e
AH		 8760 * turning off the link would also turn off the device, except in the
8761 * case of DeepSleep where the device is expected to remain powered.
57d104c1
SJ		 8762 */
8763 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 8764 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 8765 /*
8766 * Let's make sure that link is in low power mode, we are doing
8767 * this currently by putting the link in Hibern8. Otherway to
8768 * put the link in low power mode is to send the DME end point
8769 * to device and then send the DME reset command to local
8770 * unipro. But putting the link in hibern8 is much faster.
fe1d4c2e
AH		 8771 *
8772 * Note also that putting the link in Hibern8 is a requirement
8773 * for entering DeepSleep.
f3099fbd
YG		 8774 */
8775 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236
CG		 8776 if (ret) {
8777 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8778 __func__, ret);
f3099fbd 8779 goto out;
4db7a236 8780 }
57d104c1
SJ		 8781 /*
8782 * Change controller state to "reset state" which
8783 * should also put the link in off/reset state
8784 */
5cac1095 8785 ufshcd_hba_stop(hba);
57d104c1
SJ		 8786 /*
8787 * TODO: Check if we need any delay to make sure that
8788 * controller is reset
8789 */
8790 ufshcd_set_link_off(hba);
8791 }
8792
8793out:
8794 return ret;
8795}
8796
8797static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8798{
c4df6eed
SC		 8799 bool vcc_off = false;
8800
b799fdf7
YG		 8801 /*
8802 * It seems some UFS devices may keep drawing more than sleep current
8803 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8804 * To avoid this situation, add 2ms delay before putting these UFS
8805 * rails in LPM mode.
8806 */
8807 if (!ufshcd_is_link_active(hba) &&
8808 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8809 usleep_range(2000, 2100);
8810
57d104c1
SJ		 8811 /*
8812 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8813 * power.
8814 *
8815 * If UFS device and link is in OFF state, all power supplies (VCC,
8816 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8817 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8818 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8819 *
8820 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8821 * in low power state which would save some power.
3d17b9b5
AD		 8822 *
8823 * If Write Booster is enabled and the device needs to flush the WB
8824 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 8825 */
8826 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8827 !hba->dev_info.is_lu_power_on_wp) {
8828 ufshcd_setup_vreg(hba, false);
c4df6eed 8829 vcc_off = true;
57d104c1 8830 } else if (!ufshcd_is_ufs_dev_active(hba)) {
51dd905b 8831 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
c4df6eed 8832 vcc_off = true;
23043dd8 8833 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
57d104c1
SJ		 8834 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8835 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8836 }
8837 }
c4df6eed
SC		 8838
8839 /*
8840 * Some UFS devices require delay after VCC power rail is turned-off.
8841 */
8842 if (vcc_off && hba->vreg_info.vcc &&
8843 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8844 usleep_range(5000, 5100);
57d104c1
SJ		 8845}
8846
9bb25e5d 8847#ifdef CONFIG_PM
57d104c1
SJ		 8848static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8849{
8850 int ret = 0;
8851
8852 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8853 !hba->dev_info.is_lu_power_on_wp) {
8854 ret = ufshcd_setup_vreg(hba, true);
8855 } else if (!ufshcd_is_ufs_dev_active(hba)) {
23043dd8 8856 if (!ufshcd_is_link_active(hba)) {
57d104c1
SJ		 8857 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8858 if (ret)
8859 goto vcc_disable;
8860 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8861 if (ret)
8862 goto vccq_lpm;
8863 }
69d72ac8 8864 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 8865 }
8866 goto out;
8867
8868vccq_lpm:
8869 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8870vcc_disable:
8871 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8872out:
8873 return ret;
8874}
9bb25e5d 8875#endif /* CONFIG_PM */
57d104c1
SJ		 8876
8877static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8878{
dd7143e2 8879 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8880 ufshcd_setup_hba_vreg(hba, false);
8881}
8882
8883static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8884{
dd7143e2 8885 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8886 ufshcd_setup_hba_vreg(hba, true);
8887}
8888
b294ff3e 8889static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8890{
57d104c1 8891 int ret = 0;
fe1d4c2e 8892 int check_for_bkops;
57d104c1
SJ		 8893 enum ufs_pm_level pm_lvl;
8894 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8895 enum uic_link_state req_link_state;
8896
b294ff3e 8897 hba->pm_op_in_progress = true;
4c6cb9ed
BVA		 8898 if (pm_op != UFS_SHUTDOWN_PM) {
8899 pm_lvl = pm_op == UFS_RUNTIME_PM ?
57d104c1
SJ		 8900 hba->rpm_lvl : hba->spm_lvl;
8901 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8902 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8903 } else {
8904 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8905 req_link_state = UIC_LINK_OFF_STATE;
8906 }
8907
f02bc975
DP		 8908 ufshpb_suspend(hba);
8909
7a3e97b0 8910 /*
57d104c1
SJ		 8911 * If we can't transition into any of the low power modes
8912 * just gate the clocks.
7a3e97b0 8913 */
1ab27c9c
ST		 8914 ufshcd_hold(hba, false);
8915 hba->clk_gating.is_suspended = true;
8916
348e1bc5
SC		 8917 if (ufshcd_is_clkscaling_supported(hba))
8918 ufshcd_clk_scaling_suspend(hba, true);
d6fcf81a 8919
57d104c1
SJ		 8920 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8921 req_link_state == UIC_LINK_ACTIVE_STATE) {
b294ff3e 8922 goto vops_suspend;
57d104c1 8923 }
7a3e97b0 8924
57d104c1
SJ		 8925 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8926 (req_link_state == hba->uic_link_state))
b294ff3e 8927 goto enable_scaling;
57d104c1
SJ		 8928
8929 /* UFS device & link must be active before we enter in this function */
8930 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8931 ret = -EINVAL;
b294ff3e 8932 goto enable_scaling;
57d104c1
SJ		 8933 }
8934
4c6cb9ed 8935 if (pm_op == UFS_RUNTIME_PM) {
374a246e
SJ		 8936 if (ufshcd_can_autobkops_during_suspend(hba)) {
8937 /*
8938 * The device is idle with no requests in the queue,
8939 * allow background operations if bkops status shows
8940 * that performance might be impacted.
8941 */
8942 ret = ufshcd_urgent_bkops(hba);
8943 if (ret)
b294ff3e 8944 goto enable_scaling;
374a246e
SJ		 8945 } else {
8946 /* make sure that auto bkops is disabled */
8947 ufshcd_disable_auto_bkops(hba);
8948 }
3d17b9b5 8949 /*
51dd905b
SC		 8950 * If device needs to do BKOP or WB buffer flush during
8951 * Hibern8, keep device power mode as "active power mode"
8952 * and VCC supply.
3d17b9b5 8953 */
51dd905b
SC		 8954 hba->dev_info.b_rpm_dev_flush_capable =
8955 hba->auto_bkops_enabled ||
8956 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8957 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8958 ufshcd_is_auto_hibern8_enabled(hba))) &&
8959 ufshcd_wb_need_flush(hba));
8960 }
8961
6948a96a
KK		 8962 flush_work(&hba->eeh_work);
8963
9561f584
PW		 8964 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
8965 if (ret)
8966 goto enable_scaling;
8967
51dd905b 8968 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
4c6cb9ed 8969 if (pm_op != UFS_RUNTIME_PM)
51dd905b
SC		 8970 /* ensure that bkops is disabled */
8971 ufshcd_disable_auto_bkops(hba);
57d104c1 8972
51dd905b
SC		 8973 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8974 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8975 if (ret)
b294ff3e 8976 goto enable_scaling;
51dd905b 8977 }
57d104c1
SJ		 8978 }
8979
fe1d4c2e
AH		 8980 /*
8981 * In the case of DeepSleep, the device is expected to remain powered
8982 * with the link off, so do not check for bkops.
8983 */
8984 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8985 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
57d104c1
SJ		 8986 if (ret)
8987 goto set_dev_active;
8988
b294ff3e 8989vops_suspend:
57d104c1
SJ		 8990 /*
8991 * Call vendor specific suspend callback. As these callbacks may access
8992 * vendor specific host controller register space call them before the
8993 * host clocks are ON.
8994 */
9561f584 8995 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
0263bcd0
YG		 8996 if (ret)
8997 goto set_link_active;
57d104c1
SJ		 8998 goto out;
8999
57d104c1 9000set_link_active:
fe1d4c2e
AH		 9001 /*
9002 * Device hardware reset is required to exit DeepSleep. Also, for
9003 * DeepSleep, the link is off so host reset and restore will be done
9004 * further below.
9005 */
9006 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9007 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9008 WARN_ON(!ufshcd_is_link_off(hba));
9009 }
57d104c1
SJ		 9010 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9011 ufshcd_set_link_active(hba);
9012 else if (ufshcd_is_link_off(hba))
9013 ufshcd_host_reset_and_restore(hba);
9014set_dev_active:
fe1d4c2e
AH		 9015 /* Can also get here needing to exit DeepSleep */
9016 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9017 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9018 ufshcd_host_reset_and_restore(hba);
9019 }
57d104c1
SJ		 9020 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9021 ufshcd_disable_auto_bkops(hba);
b294ff3e 9022enable_scaling:
348e1bc5
SC		 9023 if (ufshcd_is_clkscaling_supported(hba))
9024 ufshcd_clk_scaling_suspend(hba, false);
9025
51dd905b 9026 hba->dev_info.b_rpm_dev_flush_capable = false;
57d104c1 9027out:
51dd905b
SC		 9028 if (hba->dev_info.b_rpm_dev_flush_capable) {
9029 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9030 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9031 }
9032
b294ff3e
AD		 9033 if (ret) {
9034 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9035 hba->clk_gating.is_suspended = false;
9036 ufshcd_release(hba);
f02bc975 9037 ufshpb_resume(hba);
b294ff3e
AD		 9038 }
9039 hba->pm_op_in_progress = false;
57d104c1 9040 return ret;
7a3e97b0
SY		 9041}
9042
75d645a6 9043#ifdef CONFIG_PM
b294ff3e 9044static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 9045{
57d104c1 9046 int ret;
b294ff3e 9047 enum uic_link_state old_link_state = hba->uic_link_state;
57d104c1 9048
b294ff3e 9049 hba->pm_op_in_progress = true;
57d104c1 9050
7a3e97b0 9051 /*
57d104c1
SJ		 9052 * Call vendor specific resume callback. As these callbacks may access
9053 * vendor specific host controller register space call them when the
9054 * host clocks are ON.
7a3e97b0 9055 */
0263bcd0
YG		 9056 ret = ufshcd_vops_resume(hba, pm_op);
9057 if (ret)
b294ff3e 9058 goto out;
57d104c1 9059
fe1d4c2e
AH		 9060 /* For DeepSleep, the only supported option is to have the link off */
9061 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9062
57d104c1
SJ		 9063 if (ufshcd_is_link_hibern8(hba)) {
9064 ret = ufshcd_uic_hibern8_exit(hba);
4db7a236 9065 if (!ret) {
57d104c1 9066 ufshcd_set_link_active(hba);
4db7a236
CG		 9067 } else {
9068 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9069 __func__, ret);
57d104c1 9070 goto vendor_suspend;
4db7a236 9071 }
57d104c1 9072 } else if (ufshcd_is_link_off(hba)) {
57d104c1 9073 /*
089f5b64
AD		 9074 * A full initialization of the host and the device is
9075 * required since the link was put to off during suspend.
fe1d4c2e
AH		 9076 * Note, in the case of DeepSleep, the device will exit
9077 * DeepSleep due to device reset.
089f5b64
AD		 9078 */
9079 ret = ufshcd_reset_and_restore(hba);
9080 /*
9081 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 9082 * set the link state as active
9083 */
9084 if (ret || !ufshcd_is_link_active(hba))
9085 goto vendor_suspend;
9086 }
9087
9088 if (!ufshcd_is_ufs_dev_active(hba)) {
9089 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9090 if (ret)
9091 goto set_old_link_state;
9092 }
9093
4e768e76 9094 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9095 ufshcd_enable_auto_bkops(hba);
9096 else
9097 /*
9098 * If BKOPs operations are urgently needed at this moment then
9099 * keep auto-bkops enabled or else disable it.
9100 */
9101 ufshcd_urgent_bkops(hba);
9102
cd469475
AH		 9103 if (hba->ee_usr_mask)
9104 ufshcd_write_ee_control(hba);
9105
348e1bc5
SC		 9106 if (ufshcd_is_clkscaling_supported(hba))
9107 ufshcd_clk_scaling_suspend(hba, false);
856b3483 9108
51dd905b
SC		 9109 if (hba->dev_info.b_rpm_dev_flush_capable) {
9110 hba->dev_info.b_rpm_dev_flush_capable = false;
9111 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9112 }
9113
b294ff3e
AD		 9114 /* Enable Auto-Hibernate if configured */
9115 ufshcd_auto_hibern8_enable(hba);
f02bc975
DP		 9116
9117 ufshpb_resume(hba);
57d104c1
SJ		 9118 goto out;
9119
9120set_old_link_state:
9121 ufshcd_link_state_transition(hba, old_link_state, 0);
9122vendor_suspend:
9561f584
PW		 9123 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9124 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
b294ff3e
AD		 9125out:
9126 if (ret)
9127 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9128 hba->clk_gating.is_suspended = false;
9129 ufshcd_release(hba);
9130 hba->pm_op_in_progress = false;
9131 return ret;
9132}
9133
9134static int ufshcd_wl_runtime_suspend(struct device *dev)
9135{
9136 struct scsi_device *sdev = to_scsi_device(dev);
9137 struct ufs_hba *hba;
9138 int ret;
9139 ktime_t start = ktime_get();
9140
9141 hba = shost_priv(sdev->host);
9142
9143 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9144 if (ret)
9145 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9146
9147 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9148 ktime_to_us(ktime_sub(ktime_get(), start)),
9149 hba->curr_dev_pwr_mode, hba->uic_link_state);
9150
9151 return ret;
9152}
9153
9154static int ufshcd_wl_runtime_resume(struct device *dev)
9155{
9156 struct scsi_device *sdev = to_scsi_device(dev);
9157 struct ufs_hba *hba;
9158 int ret = 0;
9159 ktime_t start = ktime_get();
9160
9161 hba = shost_priv(sdev->host);
9162
9163 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9164 if (ret)
9165 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9166
9167 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9168 ktime_to_us(ktime_sub(ktime_get(), start)),
9169 hba->curr_dev_pwr_mode, hba->uic_link_state);
9170
9171 return ret;
9172}
75d645a6 9173#endif
b294ff3e
AD		 9174
9175#ifdef CONFIG_PM_SLEEP
9176static int ufshcd_wl_suspend(struct device *dev)
9177{
9178 struct scsi_device *sdev = to_scsi_device(dev);
9179 struct ufs_hba *hba;
9180 int ret = 0;
9181 ktime_t start = ktime_get();
9182
9183 hba = shost_priv(sdev->host);
9184 down(&hba->host_sem);
9185
9186 if (pm_runtime_suspended(dev))
9187 goto out;
9188
9189 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9190 if (ret) {
9191 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9192 up(&hba->host_sem);
9193 }
9194
9195out:
9196 if (!ret)
9197 hba->is_sys_suspended = true;
9198 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9199 ktime_to_us(ktime_sub(ktime_get(), start)),
9200 hba->curr_dev_pwr_mode, hba->uic_link_state);
9201
9202 return ret;
9203}
9204
9205static int ufshcd_wl_resume(struct device *dev)
9206{
9207 struct scsi_device *sdev = to_scsi_device(dev);
9208 struct ufs_hba *hba;
9209 int ret = 0;
9210 ktime_t start = ktime_get();
9211
9212 hba = shost_priv(sdev->host);
9213
9214 if (pm_runtime_suspended(dev))
9215 goto out;
9216
9217 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9218 if (ret)
9219 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9220out:
9221 trace_ufshcd_wl_resume(dev_name(dev), ret,
9222 ktime_to_us(ktime_sub(ktime_get(), start)),
9223 hba->curr_dev_pwr_mode, hba->uic_link_state);
9224 if (!ret)
9225 hba->is_sys_suspended = false;
9226 up(&hba->host_sem);
9227 return ret;
9228}
9229#endif
9230
9231static void ufshcd_wl_shutdown(struct device *dev)
9232{
9233 struct scsi_device *sdev = to_scsi_device(dev);
9234 struct ufs_hba *hba;
9235
9236 hba = shost_priv(sdev->host);
9237
9238 down(&hba->host_sem);
9239 hba->shutting_down = true;
9240 up(&hba->host_sem);
9241
9242 /* Turn on everything while shutting down */
9243 ufshcd_rpm_get_sync(hba);
9244 scsi_device_quiesce(sdev);
9245 shost_for_each_device(sdev, hba->host) {
e2106584 9246 if (sdev == hba->ufs_device_wlun)
b294ff3e
AD		 9247 continue;
9248 scsi_device_quiesce(sdev);
9249 }
9250 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9251}
9252
9253/**
9254 * ufshcd_suspend - helper function for suspend operations
9255 * @hba: per adapter instance
9256 *
9257 * This function will put disable irqs, turn off clocks
9258 * and set vreg and hba-vreg in lpm mode.
b294ff3e
AD		 9259 */
9260static int ufshcd_suspend(struct ufs_hba *hba)
9261{
9262 int ret;
9263
9264 if (!hba->is_powered)
9265 return 0;
9266 /*
9267 * Disable the host irq as host controller as there won't be any
9268 * host controller transaction expected till resume.
9269 */
57d104c1 9270 ufshcd_disable_irq(hba);
b294ff3e
AD		 9271 ret = ufshcd_setup_clocks(hba, false);
9272 if (ret) {
9273 ufshcd_enable_irq(hba);
9274 return ret;
9275 }
2dec9475
CG		 9276 if (ufshcd_is_clkgating_allowed(hba)) {
9277 hba->clk_gating.state = CLKS_OFF;
9278 trace_ufshcd_clk_gating(dev_name(hba->dev),
9279 hba->clk_gating.state);
9280 }
b294ff3e
AD		 9281
9282 ufshcd_vreg_set_lpm(hba);
9283 /* Put the host controller in low power mode if possible */
9284 ufshcd_hba_vreg_set_lpm(hba);
9285 return ret;
9286}
9287
9bb25e5d 9288#ifdef CONFIG_PM
b294ff3e
AD		 9289/**
9290 * ufshcd_resume - helper function for resume operations
9291 * @hba: per adapter instance
9292 *
9293 * This function basically turns on the regulators, clocks and
9294 * irqs of the hba.
b294ff3e
AD		 9295 *
9296 * Returns 0 for success and non-zero for failure
9297 */
9298static int ufshcd_resume(struct ufs_hba *hba)
9299{
9300 int ret;
9301
9302 if (!hba->is_powered)
9303 return 0;
9304
9305 ufshcd_hba_vreg_set_hpm(hba);
9306 ret = ufshcd_vreg_set_hpm(hba);
9307 if (ret)
9308 goto out;
9309
9310 /* Make sure clocks are enabled before accessing controller */
9311 ret = ufshcd_setup_clocks(hba, true);
9312 if (ret)
9313 goto disable_vreg;
9314
9315 /* enable the host irq as host controller would be active soon */
9316 ufshcd_enable_irq(hba);
9317 goto out;
9318
528db9e5
ZC		 9319disable_vreg:
9320 ufshcd_vreg_set_lpm(hba);
57d104c1 9321out:
8808b4e9 9322 if (ret)
e965e5e0 9323 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
57d104c1
SJ		 9324 return ret;
9325}
9bb25e5d 9326#endif /* CONFIG_PM */
57d104c1 9327
9bb25e5d 9328#ifdef CONFIG_PM_SLEEP
57d104c1 9329/**
f1ecbe1e
BVA		 9330 * ufshcd_system_suspend - system suspend callback
9331 * @dev: Device associated with the UFS controller.
57d104c1 9332 *
f1ecbe1e
BVA		 9333 * Executed before putting the system into a sleep state in which the contents
9334 * of main memory are preserved.
57d104c1
SJ		 9335 *
9336 * Returns 0 for success and non-zero for failure
9337 */
f1ecbe1e 9338int ufshcd_system_suspend(struct device *dev)
57d104c1 9339{
f1ecbe1e 9340 struct ufs_hba *hba = dev_get_drvdata(dev);
57d104c1 9341 int ret = 0;
7ff5ab47 9342 ktime_t start = ktime_get();
57d104c1 9343
b294ff3e 9344 if (pm_runtime_suspended(hba->dev))
0b257734 9345 goto out;
57d104c1 9346
b294ff3e 9347 ret = ufshcd_suspend(hba);
57d104c1 9348out:
7ff5ab47 9349 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9350 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9351 hba->curr_dev_pwr_mode, hba->uic_link_state);
57d104c1
SJ		 9352 return ret;
9353}
9354EXPORT_SYMBOL(ufshcd_system_suspend);
9355
9356/**
f1ecbe1e
BVA		 9357 * ufshcd_system_resume - system resume callback
9358 * @dev: Device associated with the UFS controller.
9359 *
9360 * Executed after waking the system up from a sleep state in which the contents
9361 * of main memory were preserved.
57d104c1
SJ		 9362 *
9363 * Returns 0 for success and non-zero for failure
9364 */
f1ecbe1e 9365int ufshcd_system_resume(struct device *dev)
57d104c1 9366{
f1ecbe1e 9367 struct ufs_hba *hba = dev_get_drvdata(dev);
7ff5ab47 9368 ktime_t start = ktime_get();
f1ecbe1e 9369 int ret = 0;
7ff5ab47 9370
b294ff3e 9371 if (pm_runtime_suspended(hba->dev))
7ff5ab47 9372 goto out;
b294ff3e
AD		 9373
9374 ret = ufshcd_resume(hba);
9375
7ff5ab47 9376out:
9377 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9378 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9379 hba->curr_dev_pwr_mode, hba->uic_link_state);
b294ff3e 9380
7ff5ab47 9381 return ret;
7a3e97b0 9382}
57d104c1 9383EXPORT_SYMBOL(ufshcd_system_resume);
9bb25e5d 9384#endif /* CONFIG_PM_SLEEP */
3b1d0580 9385
9bb25e5d 9386#ifdef CONFIG_PM
57d104c1 9387/**
f1ecbe1e
BVA		 9388 * ufshcd_runtime_suspend - runtime suspend callback
9389 * @dev: Device associated with the UFS controller.
57d104c1
SJ		 9390 *
9391 * Check the description of ufshcd_suspend() function for more details.
9392 *
9393 * Returns 0 for success and non-zero for failure
9394 */
f1ecbe1e 9395int ufshcd_runtime_suspend(struct device *dev)
66ec6d59 9396{
f1ecbe1e 9397 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9398 int ret;
7ff5ab47 9399 ktime_t start = ktime_get();
9400
b294ff3e
AD		 9401 ret = ufshcd_suspend(hba);
9402
7ff5ab47 9403 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9404 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9405 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9406 return ret;
66ec6d59
SRT		 9407}
9408EXPORT_SYMBOL(ufshcd_runtime_suspend);
9409
57d104c1
SJ		 9410/**
9411 * ufshcd_runtime_resume - runtime resume routine
f1ecbe1e 9412 * @dev: Device associated with the UFS controller.
57d104c1 9413 *
b294ff3e 9414 * This function basically brings controller
57d104c1
SJ		 9415 * to active state. Following operations are done in this function:
9416 *
9417 * 1. Turn on all the controller related clocks
b294ff3e 9418 * 2. Turn ON VCC rail
57d104c1 9419 */
f1ecbe1e 9420int ufshcd_runtime_resume(struct device *dev)
66ec6d59 9421{
f1ecbe1e 9422 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9423 int ret;
7ff5ab47 9424 ktime_t start = ktime_get();
9425
b294ff3e
AD		 9426 ret = ufshcd_resume(hba);
9427
7ff5ab47 9428 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9429 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9430 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9431 return ret;
66ec6d59
SRT		 9432}
9433EXPORT_SYMBOL(ufshcd_runtime_resume);
9bb25e5d 9434#endif /* CONFIG_PM */
66ec6d59 9435
57d104c1
SJ		 9436/**
9437 * ufshcd_shutdown - shutdown routine
9438 * @hba: per adapter instance
9439 *
b294ff3e
AD		 9440 * This function would turn off both UFS device and UFS hba
9441 * regulators. It would also disable clocks.
57d104c1
SJ		 9442 *
9443 * Returns 0 always to allow force shutdown even in case of errors.
9444 */
9445int ufshcd_shutdown(struct ufs_hba *hba)
9446{
57d104c1
SJ		 9447 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9448 goto out;
9449
e92643db 9450 pm_runtime_get_sync(hba->dev);
57d104c1 9451
b294ff3e 9452 ufshcd_suspend(hba);
57d104c1 9453out:
88a92d6a 9454 hba->is_powered = false;
57d104c1
SJ		 9455 /* allow force shutdown even in case of errors */
9456 return 0;
9457}
9458EXPORT_SYMBOL(ufshcd_shutdown);
9459
7a3e97b0 9460/**
3b1d0580 9461 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 9462 * data structure memory
8aa29f19 9463 * @hba: per adapter instance
7a3e97b0 9464 */
3b1d0580 9465void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 9466{
e2106584 9467 if (hba->ufs_device_wlun)
b294ff3e 9468 ufshcd_rpm_get_sync(hba);
e88e2d32 9469 ufs_hwmon_remove(hba);
df032bf2 9470 ufs_bsg_remove(hba);
4b5f4907 9471 ufshpb_remove(hba);
cbb6813e 9472 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 9473 blk_cleanup_queue(hba->tmf_queue);
9474 blk_mq_free_tag_set(&hba->tmf_tag_set);
cfdf9c91 9475 scsi_remove_host(hba->host);
7a3e97b0 9476 /* disable interrupts */
2fbd009b 9477 ufshcd_disable_intr(hba, hba->intr_mask);
5cac1095 9478 ufshcd_hba_stop(hba);
aa497613 9479 ufshcd_hba_exit(hba);
3b1d0580
VH		 9480}
9481EXPORT_SYMBOL_GPL(ufshcd_remove);
9482
47555a5c
YG		 9483/**
9484 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9485 * @hba: pointer to Host Bus Adapter (HBA)
9486 */
9487void ufshcd_dealloc_host(struct ufs_hba *hba)
9488{
9489 scsi_host_put(hba->host);
9490}
9491EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9492
ca3d7bf9
AM		 9493/**
9494 * ufshcd_set_dma_mask - Set dma mask based on the controller
9495 * addressing capability
9496 * @hba: per adapter instance
9497 *
9498 * Returns 0 for success, non-zero for failure
9499 */
9500static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9501{
9502 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9503 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9504 return 0;
9505 }
9506 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9507}
9508
7a3e97b0 9509/**
5c0c28a8 9510 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 9511 * @dev: pointer to device handle
9512 * @hba_handle: driver private handle
7a3e97b0
SY		 9513 * Returns 0 on success, non-zero value on failure
9514 */
5c0c28a8 9515int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 9516{
9517 struct Scsi_Host *host;
9518 struct ufs_hba *hba;
5c0c28a8 9519 int err = 0;
7a3e97b0 9520
3b1d0580
VH		 9521 if (!dev) {
9522 dev_err(dev,
9523 "Invalid memory reference for dev is NULL\n");
9524 err = -ENODEV;
7a3e97b0
SY		 9525 goto out_error;
9526 }
9527
7a3e97b0
SY		 9528 host = scsi_host_alloc(&ufshcd_driver_template,
9529 sizeof(struct ufs_hba));
9530 if (!host) {
3b1d0580 9531 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 9532 err = -ENOMEM;
3b1d0580 9533 goto out_error;
7a3e97b0 9534 }
eaab9b57 9535 host->nr_maps = HCTX_TYPE_POLL + 1;
7a3e97b0 9536 hba = shost_priv(host);
7a3e97b0 9537 hba->host = host;
3b1d0580 9538 hba->dev = dev;
9e1e8a75 9539 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
1cbc9ad3 9540 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
566ec9ad 9541 INIT_LIST_HEAD(&hba->clk_list_head);
169f5eb2
BVA		 9542 spin_lock_init(&hba->outstanding_lock);
9543
9544 *hba_handle = hba;
566ec9ad 9545
5c0c28a8
SRT		 9546out_error:
9547 return err;
9548}
9549EXPORT_SYMBOL(ufshcd_alloc_host);
9550
69a6c269
BVA		 9551/* This function exists because blk_mq_alloc_tag_set() requires this. */
9552static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9553 const struct blk_mq_queue_data *qd)
9554{
9555 WARN_ON_ONCE(true);
9556 return BLK_STS_NOTSUPP;
9557}
9558
9559static const struct blk_mq_ops ufshcd_tmf_ops = {
9560 .queue_rq = ufshcd_queue_tmf,
9561};
9562
5c0c28a8
SRT		 9563/**
9564 * ufshcd_init - Driver initialization routine
9565 * @hba: per-adapter instance
9566 * @mmio_base: base register address
9567 * @irq: Interrupt line of device
9568 * Returns 0 on success, non-zero value on failure
9569 */
9570int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9571{
9572 int err;
9573 struct Scsi_Host *host = hba->host;
9574 struct device *dev = hba->dev;
88b09900 9575 char eh_wq_name[sizeof("ufs_eh_wq_00")];
5c0c28a8 9576
21ad0e49
BVA		 9577 /*
9578 * dev_set_drvdata() must be called before any callbacks are registered
9579 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
9580 * sysfs).
9581 */
9582 dev_set_drvdata(dev, hba);
9583
5c0c28a8
SRT		 9584 if (!mmio_base) {
9585 dev_err(hba->dev,
9586 "Invalid memory reference for mmio_base is NULL\n");
9587 err = -ENODEV;
9588 goto out_error;
9589 }
9590
3b1d0580
VH		 9591 hba->mmio_base = mmio_base;
9592 hba->irq = irq;
90b8491c 9593 hba->vps = &ufs_hba_vps;
7a3e97b0 9594
aa497613 9595 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 9596 if (err)
9597 goto out_error;
9598
7a3e97b0 9599 /* Read capabilities registers */
df043c74
ST		 9600 err = ufshcd_hba_capabilities(hba);
9601 if (err)
9602 goto out_disable;
7a3e97b0
SY		 9603
9604 /* Get UFS version supported by the controller */
9605 hba->ufs_version = ufshcd_get_ufs_version(hba);
9606
2fbd009b
SJ		 9607 /* Get Interrupt bit mask per version */
9608 hba->intr_mask = ufshcd_get_intr_mask(hba);
9609
ca3d7bf9
AM		 9610 err = ufshcd_set_dma_mask(hba);
9611 if (err) {
9612 dev_err(hba->dev, "set dma mask failed\n");
9613 goto out_disable;
9614 }
9615
7a3e97b0
SY		 9616 /* Allocate memory for host memory space */
9617 err = ufshcd_memory_alloc(hba);
9618 if (err) {
3b1d0580
VH		 9619 dev_err(hba->dev, "Memory allocation failed\n");
9620 goto out_disable;
7a3e97b0
SY		 9621 }
9622
9623 /* Configure LRB */
9624 ufshcd_host_memory_configure(hba);
9625
945c3cca
BVA		 9626 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9627 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
7a3e97b0 9628 host->max_id = UFSHCD_MAX_ID;
0ce147d4 9629 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 9630 host->max_channel = UFSHCD_MAX_CHANNEL;
9631 host->unique_id = host->host_no;
a851b2bd 9632 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 9633
7eb584db
DR		 9634 hba->max_pwr_info.is_valid = false;
9635
88b09900
AH		 9636 /* Initialize work queues */
9637 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9638 hba->host->host_no);
9639 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9640 if (!hba->eh_wq) {
9641 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9642 __func__);
9643 err = -ENOMEM;
9644 goto out_disable;
9645 }
9646 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 9647 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 9648
9cd20d3f 9649 sema_init(&hba->host_sem, 1);
88a92d6a 9650
6ccf44fe
SJ		 9651 /* Initialize UIC command mutex */
9652 mutex_init(&hba->uic_cmd_mutex);
9653
5a0b0cb9
SRT		 9654 /* Initialize mutex for device management commands */
9655 mutex_init(&hba->dev_cmd.lock);
9656
cd469475
AH		 9657 /* Initialize mutex for exception event control */
9658 mutex_init(&hba->ee_ctrl_mutex);
9659
a3cd5ec5 9660 init_rwsem(&hba->clk_scaling_lock);
9661
1ab27c9c 9662 ufshcd_init_clk_gating(hba);
199ef13c 9663
eebcc196
VG		 9664 ufshcd_init_clk_scaling(hba);
9665
199ef13c
YG		 9666 /*
9667 * In order to avoid any spurious interrupt immediately after
9668 * registering UFS controller interrupt handler, clear any pending UFS
9669 * interrupt status and disable all the UFS interrupts.
9670 */
9671 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9672 REG_INTERRUPT_STATUS);
9673 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9674 /*
9675 * Make sure that UFS interrupts are disabled and any pending interrupt
9676 * status is cleared before registering UFS interrupt handler.
9677 */
9678 mb();
9679
7a3e97b0 9680 /* IRQ registration */
2953f850 9681 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 9682 if (err) {
3b1d0580 9683 dev_err(hba->dev, "request irq failed\n");
4543d9d7 9684 goto out_disable;
57d104c1
SJ		 9685 } else {
9686 hba->is_irq_enabled = true;
7a3e97b0
SY		 9687 }
9688
3b1d0580 9689 err = scsi_add_host(host, hba->dev);
7a3e97b0 9690 if (err) {
3b1d0580 9691 dev_err(hba->dev, "scsi_add_host failed\n");
4543d9d7 9692 goto out_disable;
7a3e97b0
SY		 9693 }
9694
69a6c269
BVA		 9695 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9696 .nr_hw_queues = 1,
9697 .queue_depth = hba->nutmrs,
9698 .ops = &ufshcd_tmf_ops,
9699 .flags = BLK_MQ_F_NO_SCHED,
9700 };
9701 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9702 if (err < 0)
511a083b 9703 goto out_remove_scsi_host;
69a6c269
BVA		 9704 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9705 if (IS_ERR(hba->tmf_queue)) {
9706 err = PTR_ERR(hba->tmf_queue);
9707 goto free_tmf_tag_set;
9708 }
f5ef336f
AH		 9709 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
9710 sizeof(*hba->tmf_rqs), GFP_KERNEL);
9711 if (!hba->tmf_rqs) {
9712 err = -ENOMEM;
9713 goto free_tmf_queue;
9714 }
69a6c269 9715
d8d9f793 9716 /* Reset the attached device */
31a5d9ca 9717 ufshcd_device_reset(hba);
d8d9f793 9718
df043c74
ST		 9719 ufshcd_init_crypto(hba);
9720
6ccf44fe
SJ		 9721 /* Host controller enable */
9722 err = ufshcd_hba_enable(hba);
7a3e97b0 9723 if (err) {
6ccf44fe 9724 dev_err(hba->dev, "Host controller enable failed\n");
e965e5e0 9725 ufshcd_print_evt_hist(hba);
6ba65588 9726 ufshcd_print_host_state(hba);
69a6c269 9727 goto free_tmf_queue;
7a3e97b0 9728 }
6ccf44fe 9729
0c8f7586 9730 /*
9731 * Set the default power management level for runtime and system PM.
9732 * Default power saving mode is to keep UFS link in Hibern8 state
9733 * and UFS device in sleep state.
9734 */
9735 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9736 UFS_SLEEP_PWR_MODE,
9737 UIC_LINK_HIBERN8_STATE);
9738 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9739 UFS_SLEEP_PWR_MODE,
9740 UIC_LINK_HIBERN8_STATE);
9741
51dd905b
SC		 9742 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9743 ufshcd_rpm_dev_flush_recheck_work);
9744
ad448378 9745 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 9746 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 9747 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9748 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9749 }
9750
62694735
SRT		 9751 /* Hold auto suspend until async scan completes */
9752 pm_runtime_get_sync(dev);
38135535 9753 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 9754 /*
7caf489b 9755 * We are assuming that device wasn't put in sleep/power-down
9756 * state exclusively during the boot stage before kernel.
9757 * This assumption helps avoid doing link startup twice during
9758 * ufshcd_probe_hba().
57d104c1 9759 */
7caf489b 9760 ufshcd_set_ufs_dev_active(hba);
57d104c1 9761
6ccf44fe 9762 async_schedule(ufshcd_async_scan, hba);
cbb6813e 9763 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 9764
1084514c 9765 device_enable_async_suspend(dev);
7a3e97b0
SY		 9766 return 0;
9767
69a6c269
BVA		 9768free_tmf_queue:
9769 blk_cleanup_queue(hba->tmf_queue);
9770free_tmf_tag_set:
9771 blk_mq_free_tag_set(&hba->tmf_tag_set);
3b1d0580
VH		 9772out_remove_scsi_host:
9773 scsi_remove_host(hba->host);
3b1d0580 9774out_disable:
57d104c1 9775 hba->is_irq_enabled = false;
aa497613 9776 ufshcd_hba_exit(hba);
3b1d0580
VH		 9777out_error:
9778 return err;
9779}
9780EXPORT_SYMBOL_GPL(ufshcd_init);
9781
b294ff3e
AD		 9782void ufshcd_resume_complete(struct device *dev)
9783{
9784 struct ufs_hba *hba = dev_get_drvdata(dev);
9785
9786 if (hba->complete_put) {
9787 ufshcd_rpm_put(hba);
9788 hba->complete_put = false;
9789 }
b294ff3e
AD		 9790}
9791EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9792
ddba1cf7
AH		 9793static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
9794{
e2106584 9795 struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
ddba1cf7
AH		 9796 enum ufs_dev_pwr_mode dev_pwr_mode;
9797 enum uic_link_state link_state;
9798 unsigned long flags;
9799 bool res;
9800
9801 spin_lock_irqsave(&dev->power.lock, flags);
9802 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
9803 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
9804 res = pm_runtime_suspended(dev) &&
9805 hba->curr_dev_pwr_mode == dev_pwr_mode &&
9806 hba->uic_link_state == link_state &&
9807 !hba->dev_info.b_rpm_dev_flush_capable;
9808 spin_unlock_irqrestore(&dev->power.lock, flags);
9809
9810 return res;
9811}
9812
9813int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
b294ff3e
AD		 9814{
9815 struct ufs_hba *hba = dev_get_drvdata(dev);
9816 int ret;
9817
9818 /*
9819 * SCSI assumes that runtime-pm and system-pm for scsi drivers
9820 * are same. And it doesn't wake up the device for system-suspend
9821 * if it's runtime suspended. But ufs doesn't follow that.
9822 * Refer ufshcd_resume_complete()
9823 */
e2106584 9824 if (hba->ufs_device_wlun) {
ddba1cf7
AH		 9825 /* Prevent runtime suspend */
9826 ufshcd_rpm_get_noresume(hba);
9827 /*
9828 * Check if already runtime suspended in same state as system
9829 * suspend would be.
9830 */
9831 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
9832 /* RPM state is not ok for SPM, so runtime resume */
9833 ret = ufshcd_rpm_resume(hba);
9834 if (ret < 0 && ret != -EACCES) {
9835 ufshcd_rpm_put(hba);
9836 return ret;
9837 }
b294ff3e
AD		 9838 }
9839 hba->complete_put = true;
9840 }
b294ff3e
AD		 9841 return 0;
9842}
ddba1cf7
AH		 9843EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
9844
9845int ufshcd_suspend_prepare(struct device *dev)
9846{
9847 return __ufshcd_suspend_prepare(dev, true);
9848}
b294ff3e
AD		 9849EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9850
9851#ifdef CONFIG_PM_SLEEP
9852static int ufshcd_wl_poweroff(struct device *dev)
9853{
9854 struct scsi_device *sdev = to_scsi_device(dev);
9855 struct ufs_hba *hba = shost_priv(sdev->host);
9856
9857 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9858 return 0;
9859}
9860#endif
9861
9862static int ufshcd_wl_probe(struct device *dev)
9863{
9864 struct scsi_device *sdev = to_scsi_device(dev);
9865
9866 if (!is_device_wlun(sdev))
9867 return -ENODEV;
9868
9869 blk_pm_runtime_init(sdev->request_queue, dev);
9870 pm_runtime_set_autosuspend_delay(dev, 0);
9871 pm_runtime_allow(dev);
9872
9873 return 0;
9874}
9875
9876static int ufshcd_wl_remove(struct device *dev)
9877{
9878 pm_runtime_forbid(dev);
9879 return 0;
9880}
9881
9882static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9883#ifdef CONFIG_PM_SLEEP
9884 .suspend = ufshcd_wl_suspend,
9885 .resume = ufshcd_wl_resume,
9886 .freeze = ufshcd_wl_suspend,
9887 .thaw = ufshcd_wl_resume,
9888 .poweroff = ufshcd_wl_poweroff,
9889 .restore = ufshcd_wl_resume,
9890#endif
9891 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9892};
9893
9894/*
9895 * ufs_dev_wlun_template - describes ufs device wlun
9896 * ufs-device wlun - used to send pm commands
9897 * All luns are consumers of ufs-device wlun.
9898 *
9899 * Currently, no sd driver is present for wluns.
9900 * Hence the no specific pm operations are performed.
9901 * With ufs design, SSU should be sent to ufs-device wlun.
9902 * Hence register a scsi driver for ufs wluns only.
9903 */
9904static struct scsi_driver ufs_dev_wlun_template = {
9905 .gendrv = {
9906 .name = "ufs_device_wlun",
9907 .owner = THIS_MODULE,
9908 .probe = ufshcd_wl_probe,
9909 .remove = ufshcd_wl_remove,
9910 .pm = &ufshcd_wl_pm_ops,
9911 .shutdown = ufshcd_wl_shutdown,
9912 },
9913};
9914
b6cacaf2
AH		 9915static int __init ufshcd_core_init(void)
9916{
b294ff3e
AD		 9917 int ret;
9918
9a868c8a
BVA		 9919 /* Verify that there are no gaps in struct utp_transfer_cmd_desc. */
9920 static_assert(sizeof(struct utp_transfer_cmd_desc) ==
9921 2 * ALIGNED_UPIU_SIZE +
9922 SG_ALL * sizeof(struct ufshcd_sg_entry));
9923
b6cacaf2 9924 ufs_debugfs_init();
b294ff3e
AD		 9925
9926 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9927 if (ret)
edc0596c 9928 ufs_debugfs_exit();
b294ff3e 9929 return ret;
b6cacaf2
AH		 9930}
9931
9932static void __exit ufshcd_core_exit(void)
9933{
9934 ufs_debugfs_exit();
b294ff3e 9935 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
b6cacaf2
AH		 9936}
9937
9938module_init(ufshcd_core_init);
9939module_exit(ufshcd_core_exit);
9940
3b1d0580
VH		 9941MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9942MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 9943MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0 9944MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)