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scsi: ufs: add queries retry mechanism
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
dcea0bfb
GB		 48#define UFSHCD_REQ_SENSE_SIZE 18
49
2fbd009b
SJ		 50#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
51 UTP_TASK_REQ_COMPL |\
52 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 53/* UIC command timeout, unit: ms */
54#define UIC_CMD_TIMEOUT 500
2fbd009b 55
5a0b0cb9
SRT		 56/* NOP OUT retries waiting for NOP IN response */
57#define NOP_OUT_RETRIES 10
58/* Timeout after 30 msecs if NOP OUT hangs without response */
59#define NOP_OUT_TIMEOUT 30 /* msecs */
60
68078d5c
DR		 61/* Query request retries */
62#define QUERY_REQ_RETRIES 10
63/* Query request timeout */
64#define QUERY_REQ_TIMEOUT 30 /* msec */
e5ad406c
YG		 65/*
66 * Query request timeout for fDeviceInit flag
67 * fDeviceInit query response time for some devices is too large that default
68 * QUERY_REQ_TIMEOUT may not be enough for such devices.
69 */
70#define QUERY_FDEVICEINIT_REQ_TIMEOUT 600 /* msec */
68078d5c 71
e2933132
SRT		 72/* Task management command timeout */
73#define TM_CMD_TIMEOUT 100 /* msecs */
74
64238fbd
YG		 75/* maximum number of retries for a general UIC command */
76#define UFS_UIC_COMMAND_RETRIES 3
77
1d337ec2
SRT		 78/* maximum number of link-startup retries */
79#define DME_LINKSTARTUP_RETRIES 3
80
87d0b4a6
YG		 81/* Maximum retries for Hibern8 enter */
82#define UIC_HIBERN8_ENTER_RETRIES 3
83
1d337ec2
SRT		 84/* maximum number of reset retries before giving up */
85#define MAX_HOST_RESET_RETRIES 5
86
68078d5c
DR		 87/* Expose the flag value from utp_upiu_query.value */
88#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
89
7d568652
SJ		 90/* Interrupt aggregation default timeout, unit: 40us */
91#define INT_AGGR_DEF_TO 0x02
92
aa497613
SRT		 93#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
94 ({ \
95 int _ret; \
96 if (_on) \
97 _ret = ufshcd_enable_vreg(_dev, _vreg); \
98 else \
99 _ret = ufshcd_disable_vreg(_dev, _vreg); \
100 _ret; \
101 })
102
da461cec
SJ		 103static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 111 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114};
115
7a3e97b0
SY		 116enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121};
122
123/* UFSHCD states */
124enum {
7a3e97b0
SY		 125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
3441da7d 127 UFSHCD_STATE_OPERATIONAL,
141f8165 128 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 129};
130
131/* UFSHCD error handling flags */
132enum {
133 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 134};
135
e8e7f271
SRT		 136/* UFSHCD UIC layer error flags */
137enum {
138 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 139 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
140 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
141 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
142 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
143 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 144};
145
7a3e97b0
SY		 146/* Interrupt configuration options */
147enum {
148 UFSHCD_INT_DISABLE,
149 UFSHCD_INT_ENABLE,
150 UFSHCD_INT_CLEAR,
151};
152
3441da7d
SRT		 153#define ufshcd_set_eh_in_progress(h) \
154 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
155#define ufshcd_eh_in_progress(h) \
156 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
157#define ufshcd_clear_eh_in_progress(h) \
158 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
159
57d104c1
SJ		 160#define ufshcd_set_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
162#define ufshcd_set_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
164#define ufshcd_set_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
166#define ufshcd_is_ufs_dev_active(h) \
167 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
168#define ufshcd_is_ufs_dev_sleep(h) \
169 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
170#define ufshcd_is_ufs_dev_poweroff(h) \
171 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
172
173static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
175 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
177 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
180};
181
182static inline enum ufs_dev_pwr_mode
183ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].dev_state;
186}
187
188static inline enum uic_link_state
189ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
190{
191 return ufs_pm_lvl_states[lvl].link_state;
192}
193
3441da7d
SRT		 194static void ufshcd_tmc_handler(struct ufs_hba *hba);
195static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 196static int ufshcd_reset_and_restore(struct ufs_hba *hba);
197static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 198static void ufshcd_hba_exit(struct ufs_hba *hba);
199static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 200static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
201 bool skip_ref_clk);
202static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 203static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 204static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
205static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 206static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ		 207static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
208static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 209static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
210 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 211static int ufshcd_change_power_mode(struct ufs_hba *hba,
212 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 213static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
214{
215 return tag >= 0 && tag < hba->nutrs;
216}
57d104c1
SJ		 217
218static inline int ufshcd_enable_irq(struct ufs_hba *hba)
219{
220 int ret = 0;
221
222 if (!hba->is_irq_enabled) {
223 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
224 hba);
225 if (ret)
226 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
227 __func__, ret);
228 hba->is_irq_enabled = true;
229 }
230
231 return ret;
232}
233
234static inline void ufshcd_disable_irq(struct ufs_hba *hba)
235{
236 if (hba->is_irq_enabled) {
237 free_irq(hba->irq, hba);
238 hba->is_irq_enabled = false;
239 }
240}
3441da7d 241
b573d484
YG		 242/* replace non-printable or non-ASCII characters with spaces */
243static inline void ufshcd_remove_non_printable(char *val)
244{
245 if (!val)
246 return;
247
248 if (*val < 0x20 || *val > 0x7e)
249 *val = ' ';
250}
251
5a0b0cb9
SRT		 252/*
253 * ufshcd_wait_for_register - wait for register value to change
254 * @hba - per-adapter interface
255 * @reg - mmio register offset
256 * @mask - mask to apply to read register value
257 * @val - wait condition
258 * @interval_us - polling interval in microsecs
259 * @timeout_ms - timeout in millisecs
596585a2 260 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 261 *
262 * Returns -ETIMEDOUT on error, zero on success
263 */
596585a2
YG		 264int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
265 u32 val, unsigned long interval_us,
266 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 267{
268 int err = 0;
269 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
270
271 /* ignore bits that we don't intend to wait on */
272 val = val & mask;
273
274 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 275 if (can_sleep)
276 usleep_range(interval_us, interval_us + 50);
277 else
278 udelay(interval_us);
5a0b0cb9
SRT		 279 if (time_after(jiffies, timeout)) {
280 if ((ufshcd_readl(hba, reg) & mask) != val)
281 err = -ETIMEDOUT;
282 break;
283 }
284 }
285
286 return err;
287}
288
2fbd009b
SJ		 289/**
290 * ufshcd_get_intr_mask - Get the interrupt bit mask
291 * @hba - Pointer to adapter instance
292 *
293 * Returns interrupt bit mask per version
294 */
295static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
296{
297 if (hba->ufs_version == UFSHCI_VERSION_10)
298 return INTERRUPT_MASK_ALL_VER_10;
299 else
300 return INTERRUPT_MASK_ALL_VER_11;
301}
302
7a3e97b0
SY		 303/**
304 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
305 * @hba - Pointer to adapter instance
306 *
307 * Returns UFSHCI version supported by the controller
308 */
309static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
310{
0263bcd0
YG		 311 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
312 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 313
b873a275 314 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 315}
316
317/**
318 * ufshcd_is_device_present - Check if any device connected to
319 * the host controller
5c0c28a8 320 * @hba: pointer to adapter instance
7a3e97b0 321 *
73ec513a 322 * Returns 1 if device present, 0 if no device detected
7a3e97b0 323 */
5c0c28a8 324static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 325{
5c0c28a8
SRT		 326 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
327 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 328}
329
330/**
331 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
332 * @lrb: pointer to local command reference block
333 *
334 * This function is used to get the OCS field from UTRD
335 * Returns the OCS field in the UTRD
336 */
337static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
338{
e8c8e82a 339 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 340}
341
342/**
343 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
344 * @task_req_descp: pointer to utp_task_req_desc structure
345 *
346 * This function is used to get the OCS field from UTMRD
347 * Returns the OCS field in the UTMRD
348 */
349static inline int
350ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
351{
e8c8e82a 352 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 353}
354
355/**
356 * ufshcd_get_tm_free_slot - get a free slot for task management request
357 * @hba: per adapter instance
e2933132 358 * @free_slot: pointer to variable with available slot value
7a3e97b0 359 *
e2933132
SRT		 360 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
361 * Returns 0 if free slot is not available, else return 1 with tag value
362 * in @free_slot.
7a3e97b0 363 */
e2933132 364static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 365{
e2933132
SRT		 366 int tag;
367 bool ret = false;
368
369 if (!free_slot)
370 goto out;
371
372 do {
373 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
374 if (tag >= hba->nutmrs)
375 goto out;
376 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
377
378 *free_slot = tag;
379 ret = true;
380out:
381 return ret;
382}
383
384static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
385{
386 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 387}
388
389/**
390 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
391 * @hba: per adapter instance
392 * @pos: position of the bit to be cleared
393 */
394static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
395{
b873a275 396 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 397}
398
a48353f6
YG		 399/**
400 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
401 * @hba: per adapter instance
402 * @tag: position of the bit to be cleared
403 */
404static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
405{
406 __clear_bit(tag, &hba->outstanding_reqs);
407}
408
7a3e97b0
SY		 409/**
410 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
411 * @reg: Register value of host controller status
412 *
413 * Returns integer, 0 on Success and positive value if failed
414 */
415static inline int ufshcd_get_lists_status(u32 reg)
416{
417 /*
418 * The mask 0xFF is for the following HCS register bits
419 * Bit Description
420 * 0 Device Present
421 * 1 UTRLRDY
422 * 2 UTMRLRDY
423 * 3 UCRDY
897efe62 424 * 4-7 reserved
7a3e97b0 425 */
897efe62 426 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 427}
428
429/**
430 * ufshcd_get_uic_cmd_result - Get the UIC command result
431 * @hba: Pointer to adapter instance
432 *
433 * This function gets the result of UIC command completion
434 * Returns 0 on success, non zero value on error
435 */
436static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
437{
b873a275 438 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 439 MASK_UIC_COMMAND_RESULT;
440}
441
12b4fdb4
SJ		 442/**
443 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
444 * @hba: Pointer to adapter instance
445 *
446 * This function gets UIC command argument3
447 * Returns 0 on success, non zero value on error
448 */
449static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
450{
451 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
452}
453
7a3e97b0 454/**
5a0b0cb9 455 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 456 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 457 */
458static inline int
5a0b0cb9 459ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 460{
5a0b0cb9 461 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 462}
463
464/**
465 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
466 * @ucd_rsp_ptr: pointer to response UPIU
467 *
468 * This function gets the response status and scsi_status from response UPIU
469 * Returns the response result code.
470 */
471static inline int
472ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
473{
474 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
475}
476
1c2623c5
SJ		 477/*
478 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
479 * from response UPIU
480 * @ucd_rsp_ptr: pointer to response UPIU
481 *
482 * Return the data segment length.
483 */
484static inline unsigned int
485ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
486{
487 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
488 MASK_RSP_UPIU_DATA_SEG_LEN;
489}
490
66ec6d59
SRT		 491/**
492 * ufshcd_is_exception_event - Check if the device raised an exception event
493 * @ucd_rsp_ptr: pointer to response UPIU
494 *
495 * The function checks if the device raised an exception event indicated in
496 * the Device Information field of response UPIU.
497 *
498 * Returns true if exception is raised, false otherwise.
499 */
500static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
501{
502 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
503 MASK_RSP_EXCEPTION_EVENT ? true : false;
504}
505
7a3e97b0 506/**
7d568652 507 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 508 * @hba: per adapter instance
7a3e97b0
SY		 509 */
510static inline void
7d568652 511ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 512{
7d568652
SJ		 513 ufshcd_writel(hba, INT_AGGR_ENABLE |
514 INT_AGGR_COUNTER_AND_TIMER_RESET,
515 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
516}
517
518/**
519 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
520 * @hba: per adapter instance
521 * @cnt: Interrupt aggregation counter threshold
522 * @tmout: Interrupt aggregation timeout value
523 */
524static inline void
525ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
526{
527 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
528 INT_AGGR_COUNTER_THLD_VAL(cnt) |
529 INT_AGGR_TIMEOUT_VAL(tmout),
530 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 531}
532
b852190e
YG		 533/**
534 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
535 * @hba: per adapter instance
536 */
537static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
538{
539 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
540}
541
7a3e97b0
SY		 542/**
543 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
544 * When run-stop registers are set to 1, it indicates the
545 * host controller that it can process the requests
546 * @hba: per adapter instance
547 */
548static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
549{
b873a275
SJ		 550 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
551 REG_UTP_TASK_REQ_LIST_RUN_STOP);
552 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
553 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 554}
555
7a3e97b0
SY		 556/**
557 * ufshcd_hba_start - Start controller initialization sequence
558 * @hba: per adapter instance
559 */
560static inline void ufshcd_hba_start(struct ufs_hba *hba)
561{
b873a275 562 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 563}
564
565/**
566 * ufshcd_is_hba_active - Get controller state
567 * @hba: per adapter instance
568 *
569 * Returns zero if controller is active, 1 otherwise
570 */
571static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
572{
b873a275 573 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 574}
575
37113106
YG		 576u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
577{
578 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
579 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
580 (hba->ufs_version == UFSHCI_VERSION_11))
581 return UFS_UNIPRO_VER_1_41;
582 else
583 return UFS_UNIPRO_VER_1_6;
584}
585EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
586
587static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
588{
589 /*
590 * If both host and device support UniPro ver1.6 or later, PA layer
591 * parameters tuning happens during link startup itself.
592 *
593 * We can manually tune PA layer parameters if either host or device
594 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
595 * logic simple, we will only do manual tuning if local unipro version
596 * doesn't support ver1.6 or later.
597 */
598 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
599 return true;
600 else
601 return false;
602}
603
a508253d
GB		 604static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
605{
606 if (ufshcd_is_clkscaling_enabled(hba)) {
607 devfreq_suspend_device(hba->devfreq);
608 hba->clk_scaling.window_start_t = 0;
609 }
610}
611
612static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
613{
614 if (ufshcd_is_clkscaling_enabled(hba))
615 devfreq_resume_device(hba->devfreq);
616}
617
1ab27c9c
ST		 618static void ufshcd_ungate_work(struct work_struct *work)
619{
620 int ret;
621 unsigned long flags;
622 struct ufs_hba *hba = container_of(work, struct ufs_hba,
623 clk_gating.ungate_work);
624
625 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
626
627 spin_lock_irqsave(hba->host->host_lock, flags);
628 if (hba->clk_gating.state == CLKS_ON) {
629 spin_unlock_irqrestore(hba->host->host_lock, flags);
630 goto unblock_reqs;
631 }
632
633 spin_unlock_irqrestore(hba->host->host_lock, flags);
634 ufshcd_setup_clocks(hba, true);
635
636 /* Exit from hibern8 */
637 if (ufshcd_can_hibern8_during_gating(hba)) {
638 /* Prevent gating in this path */
639 hba->clk_gating.is_suspended = true;
640 if (ufshcd_is_link_hibern8(hba)) {
641 ret = ufshcd_uic_hibern8_exit(hba);
642 if (ret)
643 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
644 __func__, ret);
645 else
646 ufshcd_set_link_active(hba);
647 }
648 hba->clk_gating.is_suspended = false;
649 }
650unblock_reqs:
a508253d 651 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 652 scsi_unblock_requests(hba->host);
653}
654
655/**
656 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
657 * Also, exit from hibern8 mode and set the link as active.
658 * @hba: per adapter instance
659 * @async: This indicates whether caller should ungate clocks asynchronously.
660 */
661int ufshcd_hold(struct ufs_hba *hba, bool async)
662{
663 int rc = 0;
664 unsigned long flags;
665
666 if (!ufshcd_is_clkgating_allowed(hba))
667 goto out;
1ab27c9c
ST		 668 spin_lock_irqsave(hba->host->host_lock, flags);
669 hba->clk_gating.active_reqs++;
670
53c12d0e
YG		 671 if (ufshcd_eh_in_progress(hba)) {
672 spin_unlock_irqrestore(hba->host->host_lock, flags);
673 return 0;
674 }
675
856b3483 676start:
1ab27c9c
ST		 677 switch (hba->clk_gating.state) {
678 case CLKS_ON:
f2a785ac
VG		 679 /*
680 * Wait for the ungate work to complete if in progress.
681 * Though the clocks may be in ON state, the link could
682 * still be in hibner8 state if hibern8 is allowed
683 * during clock gating.
684 * Make sure we exit hibern8 state also in addition to
685 * clocks being ON.
686 */
687 if (ufshcd_can_hibern8_during_gating(hba) &&
688 ufshcd_is_link_hibern8(hba)) {
689 spin_unlock_irqrestore(hba->host->host_lock, flags);
690 flush_work(&hba->clk_gating.ungate_work);
691 spin_lock_irqsave(hba->host->host_lock, flags);
692 goto start;
693 }
1ab27c9c
ST		 694 break;
695 case REQ_CLKS_OFF:
696 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
697 hba->clk_gating.state = CLKS_ON;
698 break;
699 }
700 /*
701 * If we here, it means gating work is either done or
702 * currently running. Hence, fall through to cancel gating
703 * work and to enable clocks.
704 */
705 case CLKS_OFF:
706 scsi_block_requests(hba->host);
707 hba->clk_gating.state = REQ_CLKS_ON;
708 schedule_work(&hba->clk_gating.ungate_work);
709 /*
710 * fall through to check if we should wait for this
711 * work to be done or not.
712 */
713 case REQ_CLKS_ON:
714 if (async) {
715 rc = -EAGAIN;
716 hba->clk_gating.active_reqs--;
717 break;
718 }
719
720 spin_unlock_irqrestore(hba->host->host_lock, flags);
721 flush_work(&hba->clk_gating.ungate_work);
722 /* Make sure state is CLKS_ON before returning */
856b3483 723 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 724 goto start;
725 default:
726 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
727 __func__, hba->clk_gating.state);
728 break;
729 }
730 spin_unlock_irqrestore(hba->host->host_lock, flags);
731out:
732 return rc;
733}
6e3fd44d 734EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 735
736static void ufshcd_gate_work(struct work_struct *work)
737{
738 struct ufs_hba *hba = container_of(work, struct ufs_hba,
739 clk_gating.gate_work.work);
740 unsigned long flags;
741
742 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 743 /*
744 * In case you are here to cancel this work the gating state
745 * would be marked as REQ_CLKS_ON. In this case save time by
746 * skipping the gating work and exit after changing the clock
747 * state to CLKS_ON.
748 */
749 if (hba->clk_gating.is_suspended ||
750 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c
ST		 751 hba->clk_gating.state = CLKS_ON;
752 goto rel_lock;
753 }
754
755 if (hba->clk_gating.active_reqs
756 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
757 || hba->lrb_in_use || hba->outstanding_tasks
758 || hba->active_uic_cmd || hba->uic_async_done)
759 goto rel_lock;
760
761 spin_unlock_irqrestore(hba->host->host_lock, flags);
762
763 /* put the link into hibern8 mode before turning off clocks */
764 if (ufshcd_can_hibern8_during_gating(hba)) {
765 if (ufshcd_uic_hibern8_enter(hba)) {
766 hba->clk_gating.state = CLKS_ON;
767 goto out;
768 }
769 ufshcd_set_link_hibern8(hba);
770 }
771
a508253d 772 ufshcd_suspend_clkscaling(hba);
856b3483 773
1ab27c9c
ST		 774 if (!ufshcd_is_link_active(hba))
775 ufshcd_setup_clocks(hba, false);
776 else
777 /* If link is active, device ref_clk can't be switched off */
778 __ufshcd_setup_clocks(hba, false, true);
779
780 /*
781 * In case you are here to cancel this work the gating state
782 * would be marked as REQ_CLKS_ON. In this case keep the state
783 * as REQ_CLKS_ON which would anyway imply that clocks are off
784 * and a request to turn them on is pending. By doing this way,
785 * we keep the state machine in tact and this would ultimately
786 * prevent from doing cancel work multiple times when there are
787 * new requests arriving before the current cancel work is done.
788 */
789 spin_lock_irqsave(hba->host->host_lock, flags);
790 if (hba->clk_gating.state == REQ_CLKS_OFF)
791 hba->clk_gating.state = CLKS_OFF;
792
793rel_lock:
794 spin_unlock_irqrestore(hba->host->host_lock, flags);
795out:
796 return;
797}
798
799/* host lock must be held before calling this variant */
800static void __ufshcd_release(struct ufs_hba *hba)
801{
802 if (!ufshcd_is_clkgating_allowed(hba))
803 return;
804
805 hba->clk_gating.active_reqs--;
806
807 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
808 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
809 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 810 || hba->active_uic_cmd || hba->uic_async_done
811 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 812 return;
813
814 hba->clk_gating.state = REQ_CLKS_OFF;
815 schedule_delayed_work(&hba->clk_gating.gate_work,
816 msecs_to_jiffies(hba->clk_gating.delay_ms));
817}
818
819void ufshcd_release(struct ufs_hba *hba)
820{
821 unsigned long flags;
822
823 spin_lock_irqsave(hba->host->host_lock, flags);
824 __ufshcd_release(hba);
825 spin_unlock_irqrestore(hba->host->host_lock, flags);
826}
6e3fd44d 827EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 828
829static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
830 struct device_attribute *attr, char *buf)
831{
832 struct ufs_hba *hba = dev_get_drvdata(dev);
833
834 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
835}
836
837static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
838 struct device_attribute *attr, const char *buf, size_t count)
839{
840 struct ufs_hba *hba = dev_get_drvdata(dev);
841 unsigned long flags, value;
842
843 if (kstrtoul(buf, 0, &value))
844 return -EINVAL;
845
846 spin_lock_irqsave(hba->host->host_lock, flags);
847 hba->clk_gating.delay_ms = value;
848 spin_unlock_irqrestore(hba->host->host_lock, flags);
849 return count;
850}
851
852static void ufshcd_init_clk_gating(struct ufs_hba *hba)
853{
854 if (!ufshcd_is_clkgating_allowed(hba))
855 return;
856
857 hba->clk_gating.delay_ms = 150;
858 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
859 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
860
861 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
862 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
863 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
864 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
865 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
866 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
867 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
868}
869
870static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
871{
872 if (!ufshcd_is_clkgating_allowed(hba))
873 return;
874 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM		 875 cancel_work_sync(&hba->clk_gating.ungate_work);
876 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 877}
878
856b3483
ST		 879/* Must be called with host lock acquired */
880static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
881{
882 if (!ufshcd_is_clkscaling_enabled(hba))
883 return;
884
885 if (!hba->clk_scaling.is_busy_started) {
886 hba->clk_scaling.busy_start_t = ktime_get();
887 hba->clk_scaling.is_busy_started = true;
888 }
889}
890
891static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
892{
893 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
894
895 if (!ufshcd_is_clkscaling_enabled(hba))
896 return;
897
898 if (!hba->outstanding_reqs && scaling->is_busy_started) {
899 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
900 scaling->busy_start_t));
901 scaling->busy_start_t = ktime_set(0, 0);
902 scaling->is_busy_started = false;
903 }
904}
7a3e97b0
SY		 905/**
906 * ufshcd_send_command - Send SCSI or device management commands
907 * @hba: per adapter instance
908 * @task_tag: Task tag of the command
909 */
910static inline
911void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
912{
856b3483 913 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 914 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 915 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 916 /* Make sure that doorbell is committed immediately */
917 wmb();
7a3e97b0
SY		 918}
919
920/**
921 * ufshcd_copy_sense_data - Copy sense data in case of check condition
922 * @lrb - pointer to local reference block
923 */
924static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
925{
926 int len;
1c2623c5
SJ		 927 if (lrbp->sense_buffer &&
928 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 929 int len_to_copy;
930
5a0b0cb9 931 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 932 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
933
7a3e97b0 934 memcpy(lrbp->sense_buffer,
5a0b0cb9 935 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 936 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 937 }
938}
939
68078d5c
DR		 940/**
941 * ufshcd_copy_query_response() - Copy the Query Response and the data
942 * descriptor
943 * @hba: per adapter instance
944 * @lrb - pointer to local reference block
945 */
946static
c6d4a831 947int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 948{
949 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
950
68078d5c 951 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 952
68078d5c
DR		 953 /* Get the descriptor */
954 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 955 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 956 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 957 u16 resp_len;
958 u16 buf_len;
68078d5c
DR		 959
960 /* data segment length */
c6d4a831 961 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 962 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 963 buf_len = be16_to_cpu(
964 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 965 if (likely(buf_len >= resp_len)) {
966 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
967 } else {
968 dev_warn(hba->dev,
969 "%s: Response size is bigger than buffer",
970 __func__);
971 return -EINVAL;
972 }
68078d5c 973 }
c6d4a831
DR		 974
975 return 0;
68078d5c
DR		 976}
977
7a3e97b0
SY		 978/**
979 * ufshcd_hba_capabilities - Read controller capabilities
980 * @hba: per adapter instance
981 */
982static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
983{
b873a275 984 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 985
986 /* nutrs and nutmrs are 0 based values */
987 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
988 hba->nutmrs =
989 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
990}
991
992/**
6ccf44fe
SJ		 993 * ufshcd_ready_for_uic_cmd - Check if controller is ready
994 * to accept UIC commands
7a3e97b0 995 * @hba: per adapter instance
6ccf44fe
SJ		 996 * Return true on success, else false
997 */
998static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
999{
1000 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1001 return true;
1002 else
1003 return false;
1004}
1005
53b3d9c3
SJ		 1006/**
1007 * ufshcd_get_upmcrs - Get the power mode change request status
1008 * @hba: Pointer to adapter instance
1009 *
1010 * This function gets the UPMCRS field of HCS register
1011 * Returns value of UPMCRS field
1012 */
1013static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1014{
1015 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1016}
1017
6ccf44fe
SJ		 1018/**
1019 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1020 * @hba: per adapter instance
1021 * @uic_cmd: UIC command
1022 *
1023 * Mutex must be held.
7a3e97b0
SY		 1024 */
1025static inline void
6ccf44fe 1026ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1027{
6ccf44fe
SJ		 1028 WARN_ON(hba->active_uic_cmd);
1029
1030 hba->active_uic_cmd = uic_cmd;
1031
7a3e97b0 1032 /* Write Args */
6ccf44fe
SJ		 1033 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1034 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1035 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1036
1037 /* Write UIC Cmd */
6ccf44fe 1038 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1039 REG_UIC_COMMAND);
7a3e97b0
SY		 1040}
1041
6ccf44fe
SJ		 1042/**
1043 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1044 * @hba: per adapter instance
1045 * @uic_command: UIC command
1046 *
1047 * Must be called with mutex held.
1048 * Returns 0 only if success.
1049 */
1050static int
1051ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1052{
1053 int ret;
1054 unsigned long flags;
1055
1056 if (wait_for_completion_timeout(&uic_cmd->done,
1057 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1058 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1059 else
1060 ret = -ETIMEDOUT;
1061
1062 spin_lock_irqsave(hba->host->host_lock, flags);
1063 hba->active_uic_cmd = NULL;
1064 spin_unlock_irqrestore(hba->host->host_lock, flags);
1065
1066 return ret;
1067}
1068
1069/**
1070 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1071 * @hba: per adapter instance
1072 * @uic_cmd: UIC command
d75f7fe4 1073 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1074 *
1075 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1076 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1077 * Returns 0 only if success.
1078 */
1079static int
d75f7fe4
YG		 1080__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1081 bool completion)
6ccf44fe 1082{
6ccf44fe
SJ		 1083 if (!ufshcd_ready_for_uic_cmd(hba)) {
1084 dev_err(hba->dev,
1085 "Controller not ready to accept UIC commands\n");
1086 return -EIO;
1087 }
1088
d75f7fe4
YG		 1089 if (completion)
1090 init_completion(&uic_cmd->done);
6ccf44fe 1091
6ccf44fe 1092 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1093
57d104c1 1094 return 0;
6ccf44fe
SJ		 1095}
1096
1097/**
1098 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1099 * @hba: per adapter instance
1100 * @uic_cmd: UIC command
1101 *
1102 * Returns 0 only if success.
1103 */
1104static int
1105ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1106{
1107 int ret;
57d104c1 1108 unsigned long flags;
6ccf44fe 1109
1ab27c9c 1110 ufshcd_hold(hba, false);
6ccf44fe 1111 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1112 ufshcd_add_delay_before_dme_cmd(hba);
1113
57d104c1 1114 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1115 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1116 spin_unlock_irqrestore(hba->host->host_lock, flags);
1117 if (!ret)
1118 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1119
6ccf44fe
SJ		 1120 mutex_unlock(&hba->uic_cmd_mutex);
1121
1ab27c9c 1122 ufshcd_release(hba);
6ccf44fe
SJ		 1123 return ret;
1124}
1125
7a3e97b0
SY		 1126/**
1127 * ufshcd_map_sg - Map scatter-gather list to prdt
1128 * @lrbp - pointer to local reference block
1129 *
1130 * Returns 0 in case of success, non-zero value in case of failure
1131 */
75b1cc4a 1132static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1133{
1134 struct ufshcd_sg_entry *prd_table;
1135 struct scatterlist *sg;
1136 struct scsi_cmnd *cmd;
1137 int sg_segments;
1138 int i;
1139
1140 cmd = lrbp->cmd;
1141 sg_segments = scsi_dma_map(cmd);
1142 if (sg_segments < 0)
1143 return sg_segments;
1144
1145 if (sg_segments) {
75b1cc4a
KK		 1146 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1147 lrbp->utr_descriptor_ptr->prd_table_length =
1148 cpu_to_le16((u16)(sg_segments *
1149 sizeof(struct ufshcd_sg_entry)));
1150 else
1151 lrbp->utr_descriptor_ptr->prd_table_length =
1152 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 1153
1154 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1155
1156 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1157 prd_table[i].size =
1158 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1159 prd_table[i].base_addr =
1160 cpu_to_le32(lower_32_bits(sg->dma_address));
1161 prd_table[i].upper_addr =
1162 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1163 prd_table[i].reserved = 0;
7a3e97b0
SY		 1164 }
1165 } else {
1166 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1167 }
1168
1169 return 0;
1170}
1171
1172/**
2fbd009b 1173 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1174 * @hba: per adapter instance
2fbd009b 1175 * @intrs: interrupt bits
7a3e97b0 1176 */
2fbd009b 1177static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1178{
2fbd009b
SJ		 1179 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1180
1181 if (hba->ufs_version == UFSHCI_VERSION_10) {
1182 u32 rw;
1183 rw = set & INTERRUPT_MASK_RW_VER_10;
1184 set = rw | ((set ^ intrs) & intrs);
1185 } else {
1186 set |= intrs;
1187 }
1188
1189 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1190}
1191
1192/**
1193 * ufshcd_disable_intr - disable interrupts
1194 * @hba: per adapter instance
1195 * @intrs: interrupt bits
1196 */
1197static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1198{
1199 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1200
1201 if (hba->ufs_version == UFSHCI_VERSION_10) {
1202 u32 rw;
1203 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1204 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1205 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1206
1207 } else {
1208 set &= ~intrs;
7a3e97b0 1209 }
2fbd009b
SJ		 1210
1211 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1212}
1213
5a0b0cb9
SRT		 1214/**
1215 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1216 * descriptor according to request
1217 * @lrbp: pointer to local reference block
1218 * @upiu_flags: flags required in the header
1219 * @cmd_dir: requests data direction
1220 */
1221static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1222 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 1223{
1224 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1225 u32 data_direction;
1226 u32 dword_0;
1227
1228 if (cmd_dir == DMA_FROM_DEVICE) {
1229 data_direction = UTP_DEVICE_TO_HOST;
1230 *upiu_flags = UPIU_CMD_FLAGS_READ;
1231 } else if (cmd_dir == DMA_TO_DEVICE) {
1232 data_direction = UTP_HOST_TO_DEVICE;
1233 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1234 } else {
1235 data_direction = UTP_NO_DATA_TRANSFER;
1236 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1237 }
1238
1239 dword_0 = data_direction | (lrbp->command_type
1240 << UPIU_COMMAND_TYPE_OFFSET);
1241 if (lrbp->intr_cmd)
1242 dword_0 |= UTP_REQ_DESC_INT_CMD;
1243
1244 /* Transfer request descriptor header fields */
1245 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1246 /* dword_1 is reserved, hence it is set to 0 */
1247 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1248 /*
1249 * assigning invalid value for command status. Controller
1250 * updates OCS on command completion, with the command
1251 * status
1252 */
1253 req_desc->header.dword_2 =
1254 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1255 /* dword_3 is reserved, hence it is set to 0 */
1256 req_desc->header.dword_3 = 0;
51047266
YG		 1257
1258 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1259}
1260
1261/**
1262 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1263 * for scsi commands
1264 * @lrbp - local reference block pointer
1265 * @upiu_flags - flags
1266 */
1267static
1268void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1269{
1270 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1271 unsigned short cdb_len;
5a0b0cb9
SRT		 1272
1273 /* command descriptor fields */
1274 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1275 UPIU_TRANSACTION_COMMAND, upiu_flags,
1276 lrbp->lun, lrbp->task_tag);
1277 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1278 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1279
1280 /* Total EHS length and Data segment length will be zero */
1281 ucd_req_ptr->header.dword_2 = 0;
1282
1283 ucd_req_ptr->sc.exp_data_transfer_len =
1284 cpu_to_be32(lrbp->cmd->sdb.length);
1285
52ac95fe
YG		 1286 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1287 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1288 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1289
1290 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1291}
1292
68078d5c
DR		 1293/**
1294 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1295 * for query requsts
1296 * @hba: UFS hba
1297 * @lrbp: local reference block pointer
1298 * @upiu_flags: flags
1299 */
1300static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1301 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1302{
1303 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1304 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1305 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1306 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1307
1308 /* Query request header */
1309 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1310 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1311 lrbp->lun, lrbp->task_tag);
1312 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1313 0, query->request.query_func, 0, 0);
1314
6861285c
ZL		 1315 /* Data segment length only need for WRITE_DESC */
1316 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1317 ucd_req_ptr->header.dword_2 =
1318 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
1319 else
1320 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 1321
1322 /* Copy the Query Request buffer as is */
1323 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1324 QUERY_OSF_SIZE);
68078d5c
DR		 1325
1326 /* Copy the Descriptor */
c6d4a831
DR		 1327 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1328 memcpy(descp, query->descriptor, len);
1329
51047266 1330 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1331}
1332
5a0b0cb9
SRT		 1333static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1334{
1335 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1336
1337 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1338
1339 /* command descriptor fields */
1340 ucd_req_ptr->header.dword_0 =
1341 UPIU_HEADER_DWORD(
1342 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1343 /* clear rest of the fields of basic header */
1344 ucd_req_ptr->header.dword_1 = 0;
1345 ucd_req_ptr->header.dword_2 = 0;
1346
1347 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1348}
1349
7a3e97b0 1350/**
300bb13f
JP		 1351 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1352 * for Device Management Purposes
5a0b0cb9 1353 * @hba - per adapter instance
7a3e97b0
SY		 1354 * @lrb - pointer to local reference block
1355 */
300bb13f 1356static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1357{
7a3e97b0 1358 u32 upiu_flags;
5a0b0cb9 1359 int ret = 0;
7a3e97b0 1360
300bb13f
JP		 1361 if (hba->ufs_version == UFSHCI_VERSION_20)
1362 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1363 else
1364 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1365
1366 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1367 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1368 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1369 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1370 ufshcd_prepare_utp_nop_upiu(lrbp);
1371 else
1372 ret = -EINVAL;
1373
1374 return ret;
1375}
1376
1377/**
1378 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1379 * for SCSI Purposes
1380 * @hba - per adapter instance
1381 * @lrb - pointer to local reference block
1382 */
1383static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1384{
1385 u32 upiu_flags;
1386 int ret = 0;
1387
1388 if (hba->ufs_version == UFSHCI_VERSION_20)
1389 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1390 else
1391 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1392
1393 if (likely(lrbp->cmd)) {
1394 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1395 lrbp->cmd->sc_data_direction);
1396 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1397 } else {
1398 ret = -EINVAL;
1399 }
5a0b0cb9
SRT		 1400
1401 return ret;
7a3e97b0
SY		 1402}
1403
0ce147d4
SJ		 1404/*
1405 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1406 * @scsi_lun: scsi LUN id
1407 *
1408 * Returns UPIU LUN id
1409 */
1410static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1411{
1412 if (scsi_is_wlun(scsi_lun))
1413 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1414 | UFS_UPIU_WLUN_ID;
1415 else
1416 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1417}
1418
2a8fa600
SJ		 1419/**
1420 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1421 * @scsi_lun: UPIU W-LUN id
1422 *
1423 * Returns SCSI W-LUN id
1424 */
1425static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1426{
1427 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1428}
1429
7a3e97b0
SY		 1430/**
1431 * ufshcd_queuecommand - main entry point for SCSI requests
1432 * @cmd: command from SCSI Midlayer
1433 * @done: call back function
1434 *
1435 * Returns 0 for success, non-zero in case of failure
1436 */
1437static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1438{
1439 struct ufshcd_lrb *lrbp;
1440 struct ufs_hba *hba;
1441 unsigned long flags;
1442 int tag;
1443 int err = 0;
1444
1445 hba = shost_priv(host);
1446
1447 tag = cmd->request->tag;
14497328
YG		 1448 if (!ufshcd_valid_tag(hba, tag)) {
1449 dev_err(hba->dev,
1450 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1451 __func__, tag, cmd, cmd->request);
1452 BUG();
1453 }
7a3e97b0 1454
3441da7d
SRT		 1455 spin_lock_irqsave(hba->host->host_lock, flags);
1456 switch (hba->ufshcd_state) {
1457 case UFSHCD_STATE_OPERATIONAL:
1458 break;
141f8165 1459 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 1460 case UFSHCD_STATE_RESET:
7a3e97b0 1461 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1462 goto out_unlock;
1463 case UFSHCD_STATE_ERROR:
1464 set_host_byte(cmd, DID_ERROR);
1465 cmd->scsi_done(cmd);
1466 goto out_unlock;
1467 default:
1468 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1469 __func__, hba->ufshcd_state);
1470 set_host_byte(cmd, DID_BAD_TARGET);
1471 cmd->scsi_done(cmd);
1472 goto out_unlock;
7a3e97b0 1473 }
53c12d0e
YG		 1474
1475 /* if error handling is in progress, don't issue commands */
1476 if (ufshcd_eh_in_progress(hba)) {
1477 set_host_byte(cmd, DID_ERROR);
1478 cmd->scsi_done(cmd);
1479 goto out_unlock;
1480 }
3441da7d 1481 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1482
5a0b0cb9
SRT		 1483 /* acquire the tag to make sure device cmds don't use it */
1484 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1485 /*
1486 * Dev manage command in progress, requeue the command.
1487 * Requeuing the command helps in cases where the request *may*
1488 * find different tag instead of waiting for dev manage command
1489 * completion.
1490 */
1491 err = SCSI_MLQUEUE_HOST_BUSY;
1492 goto out;
1493 }
1494
1ab27c9c
ST		 1495 err = ufshcd_hold(hba, true);
1496 if (err) {
1497 err = SCSI_MLQUEUE_HOST_BUSY;
1498 clear_bit_unlock(tag, &hba->lrb_in_use);
1499 goto out;
1500 }
1501 WARN_ON(hba->clk_gating.state != CLKS_ON);
1502
7a3e97b0
SY		 1503 lrbp = &hba->lrb[tag];
1504
5a0b0cb9 1505 WARN_ON(lrbp->cmd);
7a3e97b0 1506 lrbp->cmd = cmd;
dcea0bfb 1507 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 1508 lrbp->sense_buffer = cmd->sense_buffer;
1509 lrbp->task_tag = tag;
0ce147d4 1510 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1511 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1512
300bb13f
JP		 1513 ufshcd_comp_scsi_upiu(hba, lrbp);
1514
75b1cc4a 1515 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 1516 if (err) {
1517 lrbp->cmd = NULL;
1518 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1519 goto out;
5a0b0cb9 1520 }
ad1a1b9c
GB		 1521 /* Make sure descriptors are ready before ringing the doorbell */
1522 wmb();
7a3e97b0
SY		 1523
1524 /* issue command to the controller */
1525 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1526 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 1527 ufshcd_send_command(hba, tag);
3441da7d 1528out_unlock:
7a3e97b0
SY		 1529 spin_unlock_irqrestore(hba->host->host_lock, flags);
1530out:
1531 return err;
1532}
1533
5a0b0cb9
SRT		 1534static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1535 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1536{
1537 lrbp->cmd = NULL;
1538 lrbp->sense_bufflen = 0;
1539 lrbp->sense_buffer = NULL;
1540 lrbp->task_tag = tag;
1541 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 1542 lrbp->intr_cmd = true; /* No interrupt aggregation */
1543 hba->dev_cmd.type = cmd_type;
1544
300bb13f 1545 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 1546}
1547
1548static int
1549ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1550{
1551 int err = 0;
1552 unsigned long flags;
1553 u32 mask = 1 << tag;
1554
1555 /* clear outstanding transaction before retry */
1556 spin_lock_irqsave(hba->host->host_lock, flags);
1557 ufshcd_utrl_clear(hba, tag);
1558 spin_unlock_irqrestore(hba->host->host_lock, flags);
1559
1560 /*
1561 * wait for for h/w to clear corresponding bit in door-bell.
1562 * max. wait is 1 sec.
1563 */
1564 err = ufshcd_wait_for_register(hba,
1565 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1566 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 1567
1568 return err;
1569}
1570
c6d4a831
DR		 1571static int
1572ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1573{
1574 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1575
1576 /* Get the UPIU response */
1577 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1578 UPIU_RSP_CODE_OFFSET;
1579 return query_res->response;
1580}
1581
5a0b0cb9
SRT		 1582/**
1583 * ufshcd_dev_cmd_completion() - handles device management command responses
1584 * @hba: per adapter instance
1585 * @lrbp: pointer to local reference block
1586 */
1587static int
1588ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1589{
1590 int resp;
1591 int err = 0;
1592
1593 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1594
1595 switch (resp) {
1596 case UPIU_TRANSACTION_NOP_IN:
1597 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1598 err = -EINVAL;
1599 dev_err(hba->dev, "%s: unexpected response %x\n",
1600 __func__, resp);
1601 }
1602 break;
68078d5c 1603 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1604 err = ufshcd_check_query_response(hba, lrbp);
1605 if (!err)
1606 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1607 break;
5a0b0cb9
SRT		 1608 case UPIU_TRANSACTION_REJECT_UPIU:
1609 /* TODO: handle Reject UPIU Response */
1610 err = -EPERM;
1611 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1612 __func__);
1613 break;
1614 default:
1615 err = -EINVAL;
1616 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1617 __func__, resp);
1618 break;
1619 }
1620
1621 return err;
1622}
1623
1624static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1625 struct ufshcd_lrb *lrbp, int max_timeout)
1626{
1627 int err = 0;
1628 unsigned long time_left;
1629 unsigned long flags;
1630
1631 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1632 msecs_to_jiffies(max_timeout));
1633
ad1a1b9c
GB		 1634 /* Make sure descriptors are ready before ringing the doorbell */
1635 wmb();
5a0b0cb9
SRT		 1636 spin_lock_irqsave(hba->host->host_lock, flags);
1637 hba->dev_cmd.complete = NULL;
1638 if (likely(time_left)) {
1639 err = ufshcd_get_tr_ocs(lrbp);
1640 if (!err)
1641 err = ufshcd_dev_cmd_completion(hba, lrbp);
1642 }
1643 spin_unlock_irqrestore(hba->host->host_lock, flags);
1644
1645 if (!time_left) {
1646 err = -ETIMEDOUT;
a48353f6
YG		 1647 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1648 __func__, lrbp->task_tag);
5a0b0cb9 1649 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1650 /* successfully cleared the command, retry if needed */
5a0b0cb9 1651 err = -EAGAIN;
a48353f6
YG		 1652 /*
1653 * in case of an error, after clearing the doorbell,
1654 * we also need to clear the outstanding_request
1655 * field in hba
1656 */
1657 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1658 }
1659
1660 return err;
1661}
1662
1663/**
1664 * ufshcd_get_dev_cmd_tag - Get device management command tag
1665 * @hba: per-adapter instance
1666 * @tag: pointer to variable with available slot value
1667 *
1668 * Get a free slot and lock it until device management command
1669 * completes.
1670 *
1671 * Returns false if free slot is unavailable for locking, else
1672 * return true with tag value in @tag.
1673 */
1674static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1675{
1676 int tag;
1677 bool ret = false;
1678 unsigned long tmp;
1679
1680 if (!tag_out)
1681 goto out;
1682
1683 do {
1684 tmp = ~hba->lrb_in_use;
1685 tag = find_last_bit(&tmp, hba->nutrs);
1686 if (tag >= hba->nutrs)
1687 goto out;
1688 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1689
1690 *tag_out = tag;
1691 ret = true;
1692out:
1693 return ret;
1694}
1695
1696static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1697{
1698 clear_bit_unlock(tag, &hba->lrb_in_use);
1699}
1700
1701/**
1702 * ufshcd_exec_dev_cmd - API for sending device management requests
1703 * @hba - UFS hba
1704 * @cmd_type - specifies the type (NOP, Query...)
1705 * @timeout - time in seconds
1706 *
68078d5c
DR		 1707 * NOTE: Since there is only one available tag for device management commands,
1708 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1709 */
1710static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1711 enum dev_cmd_type cmd_type, int timeout)
1712{
1713 struct ufshcd_lrb *lrbp;
1714 int err;
1715 int tag;
1716 struct completion wait;
1717 unsigned long flags;
1718
1719 /*
1720 * Get free slot, sleep if slots are unavailable.
1721 * Even though we use wait_event() which sleeps indefinitely,
1722 * the maximum wait time is bounded by SCSI request timeout.
1723 */
1724 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1725
1726 init_completion(&wait);
1727 lrbp = &hba->lrb[tag];
1728 WARN_ON(lrbp->cmd);
1729 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1730 if (unlikely(err))
1731 goto out_put_tag;
1732
1733 hba->dev_cmd.complete = &wait;
1734
e3dfdc53
YG		 1735 /* Make sure descriptors are ready before ringing the doorbell */
1736 wmb();
5a0b0cb9 1737 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1738 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 1739 ufshcd_send_command(hba, tag);
1740 spin_unlock_irqrestore(hba->host->host_lock, flags);
1741
1742 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1743
1744out_put_tag:
1745 ufshcd_put_dev_cmd_tag(hba, tag);
1746 wake_up(&hba->dev_cmd.tag_wq);
1747 return err;
1748}
1749
d44a5f98
DR		 1750/**
1751 * ufshcd_init_query() - init the query response and request parameters
1752 * @hba: per-adapter instance
1753 * @request: address of the request pointer to be initialized
1754 * @response: address of the response pointer to be initialized
1755 * @opcode: operation to perform
1756 * @idn: flag idn to access
1757 * @index: LU number to access
1758 * @selector: query/flag/descriptor further identification
1759 */
1760static inline void ufshcd_init_query(struct ufs_hba *hba,
1761 struct ufs_query_req **request, struct ufs_query_res **response,
1762 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1763{
1764 *request = &hba->dev_cmd.query.request;
1765 *response = &hba->dev_cmd.query.response;
1766 memset(*request, 0, sizeof(struct ufs_query_req));
1767 memset(*response, 0, sizeof(struct ufs_query_res));
1768 (*request)->upiu_req.opcode = opcode;
1769 (*request)->upiu_req.idn = idn;
1770 (*request)->upiu_req.index = index;
1771 (*request)->upiu_req.selector = selector;
1772}
1773
dc3c8d3a
YG		 1774static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1775 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
1776{
1777 int ret;
1778 int retries;
1779
1780 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1781 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1782 if (ret)
1783 dev_dbg(hba->dev,
1784 "%s: failed with error %d, retries %d\n",
1785 __func__, ret, retries);
1786 else
1787 break;
1788 }
1789
1790 if (ret)
1791 dev_err(hba->dev,
1792 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1793 __func__, opcode, idn, ret, retries);
1794 return ret;
1795}
1796
68078d5c
DR		 1797/**
1798 * ufshcd_query_flag() - API function for sending flag query requests
1799 * hba: per-adapter instance
1800 * query_opcode: flag query to perform
1801 * idn: flag idn to access
1802 * flag_res: the flag value after the query request completes
1803 *
1804 * Returns 0 for success, non-zero in case of failure
1805 */
dc3c8d3a 1806int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 1807 enum flag_idn idn, bool *flag_res)
1808{
d44a5f98
DR		 1809 struct ufs_query_req *request = NULL;
1810 struct ufs_query_res *response = NULL;
1811 int err, index = 0, selector = 0;
e5ad406c 1812 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 1813
1814 BUG_ON(!hba);
1815
1ab27c9c 1816 ufshcd_hold(hba, false);
68078d5c 1817 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1818 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1819 selector);
68078d5c
DR		 1820
1821 switch (opcode) {
1822 case UPIU_QUERY_OPCODE_SET_FLAG:
1823 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1824 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1825 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1826 break;
1827 case UPIU_QUERY_OPCODE_READ_FLAG:
1828 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1829 if (!flag_res) {
1830 /* No dummy reads */
1831 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1832 __func__);
1833 err = -EINVAL;
1834 goto out_unlock;
1835 }
1836 break;
1837 default:
1838 dev_err(hba->dev,
1839 "%s: Expected query flag opcode but got = %d\n",
1840 __func__, opcode);
1841 err = -EINVAL;
1842 goto out_unlock;
1843 }
68078d5c 1844
e5ad406c
YG		 1845 if (idn == QUERY_FLAG_IDN_FDEVICEINIT)
1846 timeout = QUERY_FDEVICEINIT_REQ_TIMEOUT;
1847
1848 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 1849
1850 if (err) {
1851 dev_err(hba->dev,
1852 "%s: Sending flag query for idn %d failed, err = %d\n",
1853 __func__, idn, err);
1854 goto out_unlock;
1855 }
1856
1857 if (flag_res)
e8c8e82a 1858 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1859 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1860
1861out_unlock:
1862 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1863 ufshcd_release(hba);
68078d5c
DR		 1864 return err;
1865}
1866
66ec6d59
SRT		 1867/**
1868 * ufshcd_query_attr - API function for sending attribute requests
1869 * hba: per-adapter instance
1870 * opcode: attribute opcode
1871 * idn: attribute idn to access
1872 * index: index field
1873 * selector: selector field
1874 * attr_val: the attribute value after the query request completes
1875 *
1876 * Returns 0 for success, non-zero in case of failure
1877*/
bdbe5d2f 1878static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1879 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1880{
d44a5f98
DR		 1881 struct ufs_query_req *request = NULL;
1882 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1883 int err;
1884
1885 BUG_ON(!hba);
1886
1ab27c9c 1887 ufshcd_hold(hba, false);
66ec6d59
SRT		 1888 if (!attr_val) {
1889 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1890 __func__, opcode);
1891 err = -EINVAL;
1892 goto out;
1893 }
1894
1895 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1896 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1897 selector);
66ec6d59
SRT		 1898
1899 switch (opcode) {
1900 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1901 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1902 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1903 break;
1904 case UPIU_QUERY_OPCODE_READ_ATTR:
1905 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1906 break;
1907 default:
1908 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1909 __func__, opcode);
1910 err = -EINVAL;
1911 goto out_unlock;
1912 }
1913
d44a5f98 1914 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1915
1916 if (err) {
1917 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1918 __func__, opcode, idn, err);
1919 goto out_unlock;
1920 }
1921
e8c8e82a 1922 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1923
1924out_unlock:
1925 mutex_unlock(&hba->dev_cmd.lock);
1926out:
1ab27c9c 1927 ufshcd_release(hba);
66ec6d59
SRT		 1928 return err;
1929}
1930
5e86ae44
YG		 1931/**
1932 * ufshcd_query_attr_retry() - API function for sending query
1933 * attribute with retries
1934 * @hba: per-adapter instance
1935 * @opcode: attribute opcode
1936 * @idn: attribute idn to access
1937 * @index: index field
1938 * @selector: selector field
1939 * @attr_val: the attribute value after the query request
1940 * completes
1941 *
1942 * Returns 0 for success, non-zero in case of failure
1943*/
1944static int ufshcd_query_attr_retry(struct ufs_hba *hba,
1945 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1946 u32 *attr_val)
1947{
1948 int ret = 0;
1949 u32 retries;
1950
1951 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1952 ret = ufshcd_query_attr(hba, opcode, idn, index,
1953 selector, attr_val);
1954 if (ret)
1955 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
1956 __func__, ret, retries);
1957 else
1958 break;
1959 }
1960
1961 if (ret)
1962 dev_err(hba->dev,
1963 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
1964 __func__, idn, ret, QUERY_REQ_RETRIES);
1965 return ret;
1966}
1967
a70e91b8 1968static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1969 enum query_opcode opcode, enum desc_idn idn, u8 index,
1970 u8 selector, u8 *desc_buf, int *buf_len)
1971{
1972 struct ufs_query_req *request = NULL;
1973 struct ufs_query_res *response = NULL;
1974 int err;
1975
1976 BUG_ON(!hba);
1977
1ab27c9c 1978 ufshcd_hold(hba, false);
d44a5f98
DR		 1979 if (!desc_buf) {
1980 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1981 __func__, opcode);
1982 err = -EINVAL;
1983 goto out;
1984 }
1985
1986 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1987 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1988 __func__, *buf_len);
1989 err = -EINVAL;
1990 goto out;
1991 }
1992
1993 mutex_lock(&hba->dev_cmd.lock);
1994 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1995 selector);
1996 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1997 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1998
1999 switch (opcode) {
2000 case UPIU_QUERY_OPCODE_WRITE_DESC:
2001 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2002 break;
2003 case UPIU_QUERY_OPCODE_READ_DESC:
2004 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2005 break;
2006 default:
2007 dev_err(hba->dev,
2008 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2009 __func__, opcode);
2010 err = -EINVAL;
2011 goto out_unlock;
2012 }
2013
2014 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2015
2016 if (err) {
2017 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
2018 __func__, opcode, idn, err);
2019 goto out_unlock;
2020 }
2021
2022 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2023 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2024
2025out_unlock:
2026 mutex_unlock(&hba->dev_cmd.lock);
2027out:
1ab27c9c 2028 ufshcd_release(hba);
d44a5f98
DR		 2029 return err;
2030}
2031
a70e91b8
YG		 2032/**
2033 * ufshcd_query_descriptor_retry - API function for sending descriptor
2034 * requests
2035 * hba: per-adapter instance
2036 * opcode: attribute opcode
2037 * idn: attribute idn to access
2038 * index: index field
2039 * selector: selector field
2040 * desc_buf: the buffer that contains the descriptor
2041 * buf_len: length parameter passed to the device
2042 *
2043 * Returns 0 for success, non-zero in case of failure.
2044 * The buf_len parameter will contain, on return, the length parameter
2045 * received on the response.
2046 */
2047int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2048 enum query_opcode opcode, enum desc_idn idn, u8 index,
2049 u8 selector, u8 *desc_buf, int *buf_len)
2050{
2051 int err;
2052 int retries;
2053
2054 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2055 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2056 selector, desc_buf, buf_len);
2057 if (!err || err == -EINVAL)
2058 break;
2059 }
2060
2061 return err;
2062}
2063EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2064
da461cec
SJ		 2065/**
2066 * ufshcd_read_desc_param - read the specified descriptor parameter
2067 * @hba: Pointer to adapter instance
2068 * @desc_id: descriptor idn value
2069 * @desc_index: descriptor index
2070 * @param_offset: offset of the parameter to read
2071 * @param_read_buf: pointer to buffer where parameter would be read
2072 * @param_size: sizeof(param_read_buf)
2073 *
2074 * Return 0 in case of success, non-zero otherwise
2075 */
2076static int ufshcd_read_desc_param(struct ufs_hba *hba,
2077 enum desc_idn desc_id,
2078 int desc_index,
2079 u32 param_offset,
2080 u8 *param_read_buf,
2081 u32 param_size)
2082{
2083 int ret;
2084 u8 *desc_buf;
2085 u32 buff_len;
2086 bool is_kmalloc = true;
2087
2088 /* safety checks */
2089 if (desc_id >= QUERY_DESC_IDN_MAX)
2090 return -EINVAL;
2091
2092 buff_len = ufs_query_desc_max_size[desc_id];
2093 if ((param_offset + param_size) > buff_len)
2094 return -EINVAL;
2095
2096 if (!param_offset && (param_size == buff_len)) {
2097 /* memory space already available to hold full descriptor */
2098 desc_buf = param_read_buf;
2099 is_kmalloc = false;
2100 } else {
2101 /* allocate memory to hold full descriptor */
2102 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2103 if (!desc_buf)
2104 return -ENOMEM;
2105 }
2106
a70e91b8
YG		 2107 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2108 desc_id, desc_index, 0, desc_buf,
2109 &buff_len);
da461cec
SJ		 2110
2111 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
2112 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
2113 ufs_query_desc_max_size[desc_id])
2114 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
2115 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
2116 __func__, desc_id, param_offset, buff_len, ret);
2117 if (!ret)
2118 ret = -EINVAL;
2119
2120 goto out;
2121 }
2122
2123 if (is_kmalloc)
2124 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2125out:
2126 if (is_kmalloc)
2127 kfree(desc_buf);
2128 return ret;
2129}
2130
2131static inline int ufshcd_read_desc(struct ufs_hba *hba,
2132 enum desc_idn desc_id,
2133 int desc_index,
2134 u8 *buf,
2135 u32 size)
2136{
2137 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2138}
2139
2140static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2141 u8 *buf,
2142 u32 size)
2143{
61e07359
DR		 2144 int err = 0;
2145 int retries;
2146
2147 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2148 /* Read descriptor*/
2149 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2150 if (!err)
2151 break;
2152 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2153 }
2154
2155 return err;
da461cec
SJ		 2156}
2157
b573d484
YG		 2158int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2159{
2160 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2161}
2162EXPORT_SYMBOL(ufshcd_read_device_desc);
2163
2164/**
2165 * ufshcd_read_string_desc - read string descriptor
2166 * @hba: pointer to adapter instance
2167 * @desc_index: descriptor index
2168 * @buf: pointer to buffer where descriptor would be read
2169 * @size: size of buf
2170 * @ascii: if true convert from unicode to ascii characters
2171 *
2172 * Return 0 in case of success, non-zero otherwise
2173 */
2174int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2175 u32 size, bool ascii)
2176{
2177 int err = 0;
2178
2179 err = ufshcd_read_desc(hba,
2180 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2181
2182 if (err) {
2183 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2184 __func__, QUERY_REQ_RETRIES, err);
2185 goto out;
2186 }
2187
2188 if (ascii) {
2189 int desc_len;
2190 int ascii_len;
2191 int i;
2192 char *buff_ascii;
2193
2194 desc_len = buf[0];
2195 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2196 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2197 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2198 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2199 __func__);
2200 err = -ENOMEM;
2201 goto out;
2202 }
2203
2204 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2205 if (!buff_ascii) {
2206 err = -ENOMEM;
fcbefc3b 2207 goto out;
b573d484
YG		 2208 }
2209
2210 /*
2211 * the descriptor contains string in UTF16 format
2212 * we need to convert to utf-8 so it can be displayed
2213 */
2214 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2215 desc_len - QUERY_DESC_HDR_SIZE,
2216 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2217
2218 /* replace non-printable or non-ASCII characters with spaces */
2219 for (i = 0; i < ascii_len; i++)
2220 ufshcd_remove_non_printable(&buff_ascii[i]);
2221
2222 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2223 size - QUERY_DESC_HDR_SIZE);
2224 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2225 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 2226 kfree(buff_ascii);
2227 }
2228out:
2229 return err;
2230}
2231EXPORT_SYMBOL(ufshcd_read_string_desc);
2232
da461cec
SJ		 2233/**
2234 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2235 * @hba: Pointer to adapter instance
2236 * @lun: lun id
2237 * @param_offset: offset of the parameter to read
2238 * @param_read_buf: pointer to buffer where parameter would be read
2239 * @param_size: sizeof(param_read_buf)
2240 *
2241 * Return 0 in case of success, non-zero otherwise
2242 */
2243static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2244 int lun,
2245 enum unit_desc_param param_offset,
2246 u8 *param_read_buf,
2247 u32 param_size)
2248{
2249 /*
2250 * Unit descriptors are only available for general purpose LUs (LUN id
2251 * from 0 to 7) and RPMB Well known LU.
2252 */
0ce147d4 2253 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 2254 return -EOPNOTSUPP;
2255
2256 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2257 param_offset, param_read_buf, param_size);
2258}
2259
7a3e97b0
SY		 2260/**
2261 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2262 * @hba: per adapter instance
2263 *
2264 * 1. Allocate DMA memory for Command Descriptor array
2265 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2266 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2267 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2268 * (UTMRDL)
2269 * 4. Allocate memory for local reference block(lrb).
2270 *
2271 * Returns 0 for success, non-zero in case of failure
2272 */
2273static int ufshcd_memory_alloc(struct ufs_hba *hba)
2274{
2275 size_t utmrdl_size, utrdl_size, ucdl_size;
2276
2277 /* Allocate memory for UTP command descriptors */
2278 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 2279 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2280 ucdl_size,
2281 &hba->ucdl_dma_addr,
2282 GFP_KERNEL);
7a3e97b0
SY		 2283
2284 /*
2285 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2286 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2287 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2288 * be aligned to 128 bytes as well
2289 */
2290 if (!hba->ucdl_base_addr ||
2291 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2292 dev_err(hba->dev,
7a3e97b0
SY		 2293 "Command Descriptor Memory allocation failed\n");
2294 goto out;
2295 }
2296
2297 /*
2298 * Allocate memory for UTP Transfer descriptors
2299 * UFSHCI requires 1024 byte alignment of UTRD
2300 */
2301 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2302 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2303 utrdl_size,
2304 &hba->utrdl_dma_addr,
2305 GFP_KERNEL);
7a3e97b0
SY		 2306 if (!hba->utrdl_base_addr ||
2307 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2308 dev_err(hba->dev,
7a3e97b0
SY		 2309 "Transfer Descriptor Memory allocation failed\n");
2310 goto out;
2311 }
2312
2313 /*
2314 * Allocate memory for UTP Task Management descriptors
2315 * UFSHCI requires 1024 byte alignment of UTMRD
2316 */
2317 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2318 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2319 utmrdl_size,
2320 &hba->utmrdl_dma_addr,
2321 GFP_KERNEL);
7a3e97b0
SY		 2322 if (!hba->utmrdl_base_addr ||
2323 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2324 dev_err(hba->dev,
7a3e97b0
SY		 2325 "Task Management Descriptor Memory allocation failed\n");
2326 goto out;
2327 }
2328
2329 /* Allocate memory for local reference block */
2953f850
SJ		 2330 hba->lrb = devm_kzalloc(hba->dev,
2331 hba->nutrs * sizeof(struct ufshcd_lrb),
2332 GFP_KERNEL);
7a3e97b0 2333 if (!hba->lrb) {
3b1d0580 2334 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2335 goto out;
2336 }
2337 return 0;
2338out:
7a3e97b0
SY		 2339 return -ENOMEM;
2340}
2341
2342/**
2343 * ufshcd_host_memory_configure - configure local reference block with
2344 * memory offsets
2345 * @hba: per adapter instance
2346 *
2347 * Configure Host memory space
2348 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2349 * address.
2350 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2351 * and PRDT offset.
2352 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2353 * into local reference block.
2354 */
2355static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2356{
2357 struct utp_transfer_cmd_desc *cmd_descp;
2358 struct utp_transfer_req_desc *utrdlp;
2359 dma_addr_t cmd_desc_dma_addr;
2360 dma_addr_t cmd_desc_element_addr;
2361 u16 response_offset;
2362 u16 prdt_offset;
2363 int cmd_desc_size;
2364 int i;
2365
2366 utrdlp = hba->utrdl_base_addr;
2367 cmd_descp = hba->ucdl_base_addr;
2368
2369 response_offset =
2370 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2371 prdt_offset =
2372 offsetof(struct utp_transfer_cmd_desc, prd_table);
2373
2374 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2375 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2376
2377 for (i = 0; i < hba->nutrs; i++) {
2378 /* Configure UTRD with command descriptor base address */
2379 cmd_desc_element_addr =
2380 (cmd_desc_dma_addr + (cmd_desc_size * i));
2381 utrdlp[i].command_desc_base_addr_lo =
2382 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2383 utrdlp[i].command_desc_base_addr_hi =
2384 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2385
2386 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 2387 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
2388 utrdlp[i].response_upiu_offset =
2389 cpu_to_le16(response_offset);
2390 utrdlp[i].prd_table_offset =
2391 cpu_to_le16(prdt_offset);
2392 utrdlp[i].response_upiu_length =
2393 cpu_to_le16(ALIGNED_UPIU_SIZE);
2394 } else {
2395 utrdlp[i].response_upiu_offset =
7a3e97b0 2396 cpu_to_le16((response_offset >> 2));
75b1cc4a 2397 utrdlp[i].prd_table_offset =
7a3e97b0 2398 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 2399 utrdlp[i].response_upiu_length =
3ca316c5 2400 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 2401 }
7a3e97b0
SY		 2402
2403 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2404 hba->lrb[i].ucd_req_ptr =
2405 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2406 hba->lrb[i].ucd_rsp_ptr =
2407 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2408 hba->lrb[i].ucd_prdt_ptr =
2409 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2410 }
2411}
2412
2413/**
2414 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2415 * @hba: per adapter instance
2416 *
2417 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2418 * in order to initialize the Unipro link startup procedure.
2419 * Once the Unipro links are up, the device connected to the controller
2420 * is detected.
2421 *
2422 * Returns 0 on success, non-zero value on failure
2423 */
2424static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2425{
6ccf44fe
SJ		 2426 struct uic_command uic_cmd = {0};
2427 int ret;
7a3e97b0 2428
6ccf44fe 2429 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2430
6ccf44fe
SJ		 2431 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2432 if (ret)
2433 dev_err(hba->dev,
2434 "dme-link-startup: error code %d\n", ret);
2435 return ret;
7a3e97b0
SY		 2436}
2437
cad2e03d
YG		 2438static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2439{
2440 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2441 unsigned long min_sleep_time_us;
2442
2443 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2444 return;
2445
2446 /*
2447 * last_dme_cmd_tstamp will be 0 only for 1st call to
2448 * this function
2449 */
2450 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2451 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2452 } else {
2453 unsigned long delta =
2454 (unsigned long) ktime_to_us(
2455 ktime_sub(ktime_get(),
2456 hba->last_dme_cmd_tstamp));
2457
2458 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2459 min_sleep_time_us =
2460 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2461 else
2462 return; /* no more delay required */
2463 }
2464
2465 /* allow sleep for extra 50us if needed */
2466 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2467}
2468
12b4fdb4
SJ		 2469/**
2470 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2471 * @hba: per adapter instance
2472 * @attr_sel: uic command argument1
2473 * @attr_set: attribute set type as uic command argument2
2474 * @mib_val: setting value as uic command argument3
2475 * @peer: indicate whether peer or local
2476 *
2477 * Returns 0 on success, non-zero value on failure
2478 */
2479int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2480 u8 attr_set, u32 mib_val, u8 peer)
2481{
2482 struct uic_command uic_cmd = {0};
2483 static const char *const action[] = {
2484 "dme-set",
2485 "dme-peer-set"
2486 };
2487 const char *set = action[!!peer];
2488 int ret;
64238fbd 2489 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 2490
2491 uic_cmd.command = peer ?
2492 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2493 uic_cmd.argument1 = attr_sel;
2494 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2495 uic_cmd.argument3 = mib_val;
2496
64238fbd
YG		 2497 do {
2498 /* for peer attributes we retry upon failure */
2499 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2500 if (ret)
2501 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2502 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2503 } while (ret && peer && --retries);
2504
2505 if (!retries)
2506 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
2507 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2508 retries);
12b4fdb4
SJ		 2509
2510 return ret;
2511}
2512EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2513
2514/**
2515 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2516 * @hba: per adapter instance
2517 * @attr_sel: uic command argument1
2518 * @mib_val: the value of the attribute as returned by the UIC command
2519 * @peer: indicate whether peer or local
2520 *
2521 * Returns 0 on success, non-zero value on failure
2522 */
2523int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2524 u32 *mib_val, u8 peer)
2525{
2526 struct uic_command uic_cmd = {0};
2527 static const char *const action[] = {
2528 "dme-get",
2529 "dme-peer-get"
2530 };
2531 const char *get = action[!!peer];
2532 int ret;
64238fbd 2533 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 2534 struct ufs_pa_layer_attr orig_pwr_info;
2535 struct ufs_pa_layer_attr temp_pwr_info;
2536 bool pwr_mode_change = false;
2537
2538 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2539 orig_pwr_info = hba->pwr_info;
2540 temp_pwr_info = orig_pwr_info;
2541
2542 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2543 orig_pwr_info.pwr_rx == FAST_MODE) {
2544 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2545 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2546 pwr_mode_change = true;
2547 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2548 orig_pwr_info.pwr_rx == SLOW_MODE) {
2549 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2550 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2551 pwr_mode_change = true;
2552 }
2553 if (pwr_mode_change) {
2554 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2555 if (ret)
2556 goto out;
2557 }
2558 }
12b4fdb4
SJ		 2559
2560 uic_cmd.command = peer ?
2561 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2562 uic_cmd.argument1 = attr_sel;
2563
64238fbd
YG		 2564 do {
2565 /* for peer attributes we retry upon failure */
2566 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2567 if (ret)
2568 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2569 get, UIC_GET_ATTR_ID(attr_sel), ret);
2570 } while (ret && peer && --retries);
2571
2572 if (!retries)
2573 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
2574 get, UIC_GET_ATTR_ID(attr_sel), retries);
12b4fdb4 2575
64238fbd 2576 if (mib_val && !ret)
12b4fdb4 2577 *mib_val = uic_cmd.argument3;
874237f7
YG		 2578
2579 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2580 && pwr_mode_change)
2581 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2582out:
2583 return ret;
2584}
2585EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2586
53b3d9c3 2587/**
57d104c1
SJ		 2588 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2589 * state) and waits for it to take effect.
2590 *
53b3d9c3 2591 * @hba: per adapter instance
57d104c1
SJ		 2592 * @cmd: UIC command to execute
2593 *
2594 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2595 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2596 * and device UniPro link and hence it's final completion would be indicated by
2597 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2598 * addition to normal UIC command completion Status (UCCS). This function only
2599 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2600 *
2601 * Returns 0 on success, non-zero value on failure
2602 */
57d104c1 2603static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2604{
57d104c1 2605 struct completion uic_async_done;
53b3d9c3
SJ		 2606 unsigned long flags;
2607 u8 status;
2608 int ret;
d75f7fe4 2609 bool reenable_intr = false;
53b3d9c3 2610
53b3d9c3 2611 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2612 init_completion(&uic_async_done);
cad2e03d 2613 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2614
2615 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2616 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 2617 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2618 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2619 /*
2620 * Make sure UIC command completion interrupt is disabled before
2621 * issuing UIC command.
2622 */
2623 wmb();
2624 reenable_intr = true;
57d104c1 2625 }
d75f7fe4
YG		 2626 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2627 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 2628 if (ret) {
2629 dev_err(hba->dev,
2630 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2631 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2632 goto out;
2633 }
2634
57d104c1 2635 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2636 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2637 dev_err(hba->dev,
57d104c1
SJ		 2638 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2639 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2640 ret = -ETIMEDOUT;
2641 goto out;
2642 }
2643
2644 status = ufshcd_get_upmcrs(hba);
2645 if (status != PWR_LOCAL) {
2646 dev_err(hba->dev,
73615428 2647 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2648 cmd->command, status);
53b3d9c3
SJ		 2649 ret = (status != PWR_OK) ? status : -1;
2650 }
2651out:
2652 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2653 hba->active_uic_cmd = NULL;
57d104c1 2654 hba->uic_async_done = NULL;
d75f7fe4
YG		 2655 if (reenable_intr)
2656 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 2657 spin_unlock_irqrestore(hba->host->host_lock, flags);
2658 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2659
53b3d9c3
SJ		 2660 return ret;
2661}
2662
57d104c1
SJ		 2663/**
2664 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2665 * using DME_SET primitives.
2666 * @hba: per adapter instance
2667 * @mode: powr mode value
2668 *
2669 * Returns 0 on success, non-zero value on failure
2670 */
2671static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2672{
2673 struct uic_command uic_cmd = {0};
1ab27c9c 2674 int ret;
57d104c1 2675
c3a2f9ee
YG		 2676 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2677 ret = ufshcd_dme_set(hba,
2678 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2679 if (ret) {
2680 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2681 __func__, ret);
2682 goto out;
2683 }
2684 }
2685
57d104c1
SJ		 2686 uic_cmd.command = UIC_CMD_DME_SET;
2687 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2688 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2689 ufshcd_hold(hba, false);
2690 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2691 ufshcd_release(hba);
57d104c1 2692
c3a2f9ee 2693out:
1ab27c9c 2694 return ret;
57d104c1
SJ		 2695}
2696
53c12d0e
YG		 2697static int ufshcd_link_recovery(struct ufs_hba *hba)
2698{
2699 int ret;
2700 unsigned long flags;
2701
2702 spin_lock_irqsave(hba->host->host_lock, flags);
2703 hba->ufshcd_state = UFSHCD_STATE_RESET;
2704 ufshcd_set_eh_in_progress(hba);
2705 spin_unlock_irqrestore(hba->host->host_lock, flags);
2706
2707 ret = ufshcd_host_reset_and_restore(hba);
2708
2709 spin_lock_irqsave(hba->host->host_lock, flags);
2710 if (ret)
2711 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2712 ufshcd_clear_eh_in_progress(hba);
2713 spin_unlock_irqrestore(hba->host->host_lock, flags);
2714
2715 if (ret)
2716 dev_err(hba->dev, "%s: link recovery failed, err %d",
2717 __func__, ret);
2718
2719 return ret;
2720}
2721
87d0b4a6 2722static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 2723{
87d0b4a6 2724 int ret;
57d104c1
SJ		 2725 struct uic_command uic_cmd = {0};
2726
ee32c909
KK		 2727 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
2728
57d104c1 2729 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG		 2730 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2731
53c12d0e 2732 if (ret) {
87d0b4a6
YG		 2733 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
2734 __func__, ret);
2735
53c12d0e
YG		 2736 /*
2737 * If link recovery fails then return error so that caller
2738 * don't retry the hibern8 enter again.
2739 */
2740 if (ufshcd_link_recovery(hba))
2741 ret = -ENOLINK;
ee32c909
KK		 2742 } else
2743 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
2744 POST_CHANGE);
53c12d0e 2745
87d0b4a6
YG		 2746 return ret;
2747}
2748
2749static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2750{
2751 int ret = 0, retries;
57d104c1 2752
87d0b4a6
YG		 2753 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
2754 ret = __ufshcd_uic_hibern8_enter(hba);
2755 if (!ret || ret == -ENOLINK)
2756 goto out;
2757 }
2758out:
2759 return ret;
57d104c1
SJ		 2760}
2761
2762static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2763{
2764 struct uic_command uic_cmd = {0};
2765 int ret;
2766
ee32c909
KK		 2767 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
2768
57d104c1
SJ		 2769 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2770 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2771 if (ret) {
53c12d0e
YG		 2772 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
2773 __func__, ret);
2774 ret = ufshcd_link_recovery(hba);
ee32c909
KK		 2775 } else
2776 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
2777 POST_CHANGE);
57d104c1
SJ		 2778
2779 return ret;
2780}
2781
5064636c
YG		 2782 /**
2783 * ufshcd_init_pwr_info - setting the POR (power on reset)
2784 * values in hba power info
2785 * @hba: per-adapter instance
2786 */
2787static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2788{
2789 hba->pwr_info.gear_rx = UFS_PWM_G1;
2790 hba->pwr_info.gear_tx = UFS_PWM_G1;
2791 hba->pwr_info.lane_rx = 1;
2792 hba->pwr_info.lane_tx = 1;
2793 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2794 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2795 hba->pwr_info.hs_rate = 0;
2796}
2797
d3e89bac 2798/**
7eb584db
DR		 2799 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2800 * @hba: per-adapter instance
d3e89bac 2801 */
7eb584db 2802static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2803{
7eb584db
DR		 2804 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2805
2806 if (hba->max_pwr_info.is_valid)
2807 return 0;
2808
2809 pwr_info->pwr_tx = FASTAUTO_MODE;
2810 pwr_info->pwr_rx = FASTAUTO_MODE;
2811 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2812
2813 /* Get the connected lane count */
7eb584db
DR		 2814 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2815 &pwr_info->lane_rx);
2816 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2817 &pwr_info->lane_tx);
2818
2819 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2820 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2821 __func__,
2822 pwr_info->lane_rx,
2823 pwr_info->lane_tx);
2824 return -EINVAL;
2825 }
d3e89bac
SJ		 2826
2827 /*
2828 * First, get the maximum gears of HS speed.
2829 * If a zero value, it means there is no HSGEAR capability.
2830 * Then, get the maximum gears of PWM speed.
2831 */
7eb584db
DR		 2832 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2833 if (!pwr_info->gear_rx) {
2834 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2835 &pwr_info->gear_rx);
2836 if (!pwr_info->gear_rx) {
2837 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2838 __func__, pwr_info->gear_rx);
2839 return -EINVAL;
2840 }
2841 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2842 }
2843
7eb584db
DR		 2844 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2845 &pwr_info->gear_tx);
2846 if (!pwr_info->gear_tx) {
d3e89bac 2847 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2848 &pwr_info->gear_tx);
2849 if (!pwr_info->gear_tx) {
2850 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2851 __func__, pwr_info->gear_tx);
2852 return -EINVAL;
2853 }
2854 pwr_info->pwr_tx = SLOWAUTO_MODE;
2855 }
2856
2857 hba->max_pwr_info.is_valid = true;
2858 return 0;
2859}
2860
2861static int ufshcd_change_power_mode(struct ufs_hba *hba,
2862 struct ufs_pa_layer_attr *pwr_mode)
2863{
2864 int ret;
2865
2866 /* if already configured to the requested pwr_mode */
2867 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2868 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2869 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2870 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2871 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2872 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2873 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2874 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2875 return 0;
d3e89bac
SJ		 2876 }
2877
2878 /*
2879 * Configure attributes for power mode change with below.
2880 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2881 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2882 * - PA_HSSERIES
2883 */
7eb584db
DR		 2884 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2885 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2886 pwr_mode->lane_rx);
2887 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2888 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2889 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2890 else
2891 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2892
7eb584db
DR		 2893 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2894 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2895 pwr_mode->lane_tx);
2896 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2897 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2898 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2899 else
2900 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2901
7eb584db
DR		 2902 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2903 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2904 pwr_mode->pwr_rx == FAST_MODE ||
2905 pwr_mode->pwr_tx == FAST_MODE)
2906 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2907 pwr_mode->hs_rate);
d3e89bac 2908
7eb584db
DR		 2909 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2910 | pwr_mode->pwr_tx);
2911
2912 if (ret) {
d3e89bac 2913 dev_err(hba->dev,
7eb584db
DR		 2914 "%s: power mode change failed %d\n", __func__, ret);
2915 } else {
0263bcd0
YG		 2916 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2917 pwr_mode);
7eb584db
DR		 2918
2919 memcpy(&hba->pwr_info, pwr_mode,
2920 sizeof(struct ufs_pa_layer_attr));
2921 }
2922
2923 return ret;
2924}
2925
2926/**
2927 * ufshcd_config_pwr_mode - configure a new power mode
2928 * @hba: per-adapter instance
2929 * @desired_pwr_mode: desired power configuration
2930 */
2931static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2932 struct ufs_pa_layer_attr *desired_pwr_mode)
2933{
2934 struct ufs_pa_layer_attr final_params = { 0 };
2935 int ret;
2936
0263bcd0
YG		 2937 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2938 desired_pwr_mode, &final_params);
2939
2940 if (ret)
7eb584db
DR		 2941 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2942
2943 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2944
2945 return ret;
2946}
2947
68078d5c
DR		 2948/**
2949 * ufshcd_complete_dev_init() - checks device readiness
2950 * hba: per-adapter instance
2951 *
2952 * Set fDeviceInit flag and poll until device toggles it.
2953 */
2954static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2955{
dc3c8d3a
YG		 2956 int i;
2957 int err;
68078d5c
DR		 2958 bool flag_res = 1;
2959
dc3c8d3a
YG		 2960 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2961 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 2962 if (err) {
2963 dev_err(hba->dev,
2964 "%s setting fDeviceInit flag failed with error %d\n",
2965 __func__, err);
2966 goto out;
2967 }
2968
dc3c8d3a
YG		 2969 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
2970 for (i = 0; i < 1000 && !err && flag_res; i++)
2971 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
2972 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2973
68078d5c
DR		 2974 if (err)
2975 dev_err(hba->dev,
2976 "%s reading fDeviceInit flag failed with error %d\n",
2977 __func__, err);
2978 else if (flag_res)
2979 dev_err(hba->dev,
2980 "%s fDeviceInit was not cleared by the device\n",
2981 __func__);
2982
2983out:
2984 return err;
2985}
2986
7a3e97b0
SY		 2987/**
2988 * ufshcd_make_hba_operational - Make UFS controller operational
2989 * @hba: per adapter instance
2990 *
2991 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2992 * 1. Enable required interrupts
2993 * 2. Configure interrupt aggregation
897efe62 2994 * 3. Program UTRL and UTMRL base address
5c0c28a8 2995 * 4. Configure run-stop-registers
7a3e97b0
SY		 2996 *
2997 * Returns 0 on success, non-zero value on failure
2998 */
2999static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3000{
3001 int err = 0;
3002 u32 reg;
3003
6ccf44fe
SJ		 3004 /* Enable required interrupts */
3005 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3006
3007 /* Configure interrupt aggregation */
b852190e
YG		 3008 if (ufshcd_is_intr_aggr_allowed(hba))
3009 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3010 else
3011 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3012
3013 /* Configure UTRL and UTMRL base address registers */
3014 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3015 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3016 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3017 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3018 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3019 REG_UTP_TASK_REQ_LIST_BASE_L);
3020 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3021 REG_UTP_TASK_REQ_LIST_BASE_H);
3022
897efe62
YG		 3023 /*
3024 * Make sure base address and interrupt setup are updated before
3025 * enabling the run/stop registers below.
3026 */
3027 wmb();
3028
7a3e97b0
SY		 3029 /*
3030 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3031 */
5c0c28a8 3032 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3033 if (!(ufshcd_get_lists_status(reg))) {
3034 ufshcd_enable_run_stop_reg(hba);
3035 } else {
3b1d0580 3036 dev_err(hba->dev,
7a3e97b0
SY		 3037 "Host controller not ready to process requests");
3038 err = -EIO;
3039 goto out;
3040 }
3041
7a3e97b0
SY		 3042out:
3043 return err;
3044}
3045
596585a2
YG		 3046/**
3047 * ufshcd_hba_stop - Send controller to reset state
3048 * @hba: per adapter instance
3049 * @can_sleep: perform sleep or just spin
3050 */
3051static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3052{
3053 int err;
3054
3055 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3056 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3057 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3058 10, 1, can_sleep);
3059 if (err)
3060 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3061}
3062
7a3e97b0
SY		 3063/**
3064 * ufshcd_hba_enable - initialize the controller
3065 * @hba: per adapter instance
3066 *
3067 * The controller resets itself and controller firmware initialization
3068 * sequence kicks off. When controller is ready it will set
3069 * the Host Controller Enable bit to 1.
3070 *
3071 * Returns 0 on success, non-zero value on failure
3072 */
3073static int ufshcd_hba_enable(struct ufs_hba *hba)
3074{
3075 int retry;
3076
3077 /*
3078 * msleep of 1 and 5 used in this function might result in msleep(20),
3079 * but it was necessary to send the UFS FPGA to reset mode during
3080 * development and testing of this driver. msleep can be changed to
3081 * mdelay and retry count can be reduced based on the controller.
3082 */
596585a2 3083 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3084 /* change controller state to "reset state" */
596585a2 3085 ufshcd_hba_stop(hba, true);
7a3e97b0 3086
57d104c1
SJ		 3087 /* UniPro link is disabled at this point */
3088 ufshcd_set_link_off(hba);
3089
0263bcd0 3090 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3091
7a3e97b0
SY		 3092 /* start controller initialization sequence */
3093 ufshcd_hba_start(hba);
3094
3095 /*
3096 * To initialize a UFS host controller HCE bit must be set to 1.
3097 * During initialization the HCE bit value changes from 1->0->1.
3098 * When the host controller completes initialization sequence
3099 * it sets the value of HCE bit to 1. The same HCE bit is read back
3100 * to check if the controller has completed initialization sequence.
3101 * So without this delay the value HCE = 1, set in the previous
3102 * instruction might be read back.
3103 * This delay can be changed based on the controller.
3104 */
3105 msleep(1);
3106
3107 /* wait for the host controller to complete initialization */
3108 retry = 10;
3109 while (ufshcd_is_hba_active(hba)) {
3110 if (retry) {
3111 retry--;
3112 } else {
3b1d0580 3113 dev_err(hba->dev,
7a3e97b0
SY		 3114 "Controller enable failed\n");
3115 return -EIO;
3116 }
3117 msleep(5);
3118 }
5c0c28a8 3119
1d337ec2 3120 /* enable UIC related interrupts */
57d104c1 3121 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3122
0263bcd0 3123 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3124
7a3e97b0
SY		 3125 return 0;
3126}
3127
7ca38cf3
YG		 3128static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3129{
3130 int tx_lanes, i, err = 0;
3131
3132 if (!peer)
3133 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3134 &tx_lanes);
3135 else
3136 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3137 &tx_lanes);
3138 for (i = 0; i < tx_lanes; i++) {
3139 if (!peer)
3140 err = ufshcd_dme_set(hba,
3141 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3142 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3143 0);
3144 else
3145 err = ufshcd_dme_peer_set(hba,
3146 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3147 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3148 0);
3149 if (err) {
3150 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3151 __func__, peer, i, err);
3152 break;
3153 }
3154 }
3155
3156 return err;
3157}
3158
3159static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3160{
3161 return ufshcd_disable_tx_lcc(hba, true);
3162}
3163
7a3e97b0 3164/**
6ccf44fe 3165 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 3166 * @hba: per adapter instance
3167 *
6ccf44fe 3168 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3169 */
6ccf44fe 3170static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3171{
6ccf44fe 3172 int ret;
1d337ec2 3173 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 3174
1d337ec2 3175 do {
0263bcd0 3176 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3177
1d337ec2 3178 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3179
1d337ec2
SRT		 3180 /* check if device is detected by inter-connect layer */
3181 if (!ret && !ufshcd_is_device_present(hba)) {
3182 dev_err(hba->dev, "%s: Device not present\n", __func__);
3183 ret = -ENXIO;
3184 goto out;
3185 }
6ccf44fe 3186
1d337ec2
SRT		 3187 /*
3188 * DME link lost indication is only received when link is up,
3189 * but we can't be sure if the link is up until link startup
3190 * succeeds. So reset the local Uni-Pro and try again.
3191 */
3192 if (ret && ufshcd_hba_enable(hba))
3193 goto out;
3194 } while (ret && retries--);
3195
3196 if (ret)
3197 /* failed to get the link up... retire */
5c0c28a8 3198 goto out;
5c0c28a8 3199
7ca38cf3
YG		 3200 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3201 ret = ufshcd_disable_device_tx_lcc(hba);
3202 if (ret)
3203 goto out;
3204 }
3205
5c0c28a8 3206 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 3207 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3208 if (ret)
3209 goto out;
7a3e97b0 3210
5c0c28a8 3211 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 3212out:
3213 if (ret)
3214 dev_err(hba->dev, "link startup failed %d\n", ret);
3215 return ret;
7a3e97b0
SY		 3216}
3217
5a0b0cb9
SRT		 3218/**
3219 * ufshcd_verify_dev_init() - Verify device initialization
3220 * @hba: per-adapter instance
3221 *
3222 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3223 * device Transport Protocol (UTP) layer is ready after a reset.
3224 * If the UTP layer at the device side is not initialized, it may
3225 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3226 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3227 */
3228static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3229{
3230 int err = 0;
3231 int retries;
3232
1ab27c9c 3233 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 3234 mutex_lock(&hba->dev_cmd.lock);
3235 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3236 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3237 NOP_OUT_TIMEOUT);
3238
3239 if (!err || err == -ETIMEDOUT)
3240 break;
3241
3242 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3243 }
3244 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3245 ufshcd_release(hba);
5a0b0cb9
SRT		 3246
3247 if (err)
3248 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3249 return err;
3250}
3251
0ce147d4
SJ		 3252/**
3253 * ufshcd_set_queue_depth - set lun queue depth
3254 * @sdev: pointer to SCSI device
3255 *
3256 * Read bLUQueueDepth value and activate scsi tagged command
3257 * queueing. For WLUN, queue depth is set to 1. For best-effort
3258 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3259 * value that host can queue.
3260 */
3261static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3262{
3263 int ret = 0;
3264 u8 lun_qdepth;
61e07359 3265 int retries;
0ce147d4
SJ		 3266 struct ufs_hba *hba;
3267
3268 hba = shost_priv(sdev->host);
3269
3270 lun_qdepth = hba->nutrs;
61e07359
DR		 3271 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3272 /* Read descriptor*/
3273 ret = ufshcd_read_unit_desc_param(hba,
3274 ufshcd_scsi_to_upiu_lun(sdev->lun),
3275 UNIT_DESC_PARAM_LU_Q_DEPTH,
3276 &lun_qdepth,
3277 sizeof(lun_qdepth));
3278 if (!ret || ret == -ENOTSUPP)
3279 break;
3280
3281 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
3282 }
0ce147d4
SJ		 3283
3284 /* Some WLUN doesn't support unit descriptor */
3285 if (ret == -EOPNOTSUPP)
3286 lun_qdepth = 1;
3287 else if (!lun_qdepth)
3288 /* eventually, we can figure out the real queue depth */
3289 lun_qdepth = hba->nutrs;
3290 else
3291 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3292
3293 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3294 __func__, lun_qdepth);
db5ed4df 3295 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 3296}
3297
57d104c1
SJ		 3298/*
3299 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3300 * @hba: per-adapter instance
3301 * @lun: UFS device lun id
3302 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3303 *
3304 * Returns 0 in case of success and b_lu_write_protect status would be returned
3305 * @b_lu_write_protect parameter.
3306 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3307 * Returns -EINVAL in case of invalid parameters passed to this function.
3308 */
3309static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3310 u8 lun,
3311 u8 *b_lu_write_protect)
3312{
3313 int ret;
3314
3315 if (!b_lu_write_protect)
3316 ret = -EINVAL;
3317 /*
3318 * According to UFS device spec, RPMB LU can't be write
3319 * protected so skip reading bLUWriteProtect parameter for
3320 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3321 */
3322 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3323 ret = -ENOTSUPP;
3324 else
3325 ret = ufshcd_read_unit_desc_param(hba,
3326 lun,
3327 UNIT_DESC_PARAM_LU_WR_PROTECT,
3328 b_lu_write_protect,
3329 sizeof(*b_lu_write_protect));
3330 return ret;
3331}
3332
3333/**
3334 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3335 * status
3336 * @hba: per-adapter instance
3337 * @sdev: pointer to SCSI device
3338 *
3339 */
3340static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3341 struct scsi_device *sdev)
3342{
3343 if (hba->dev_info.f_power_on_wp_en &&
3344 !hba->dev_info.is_lu_power_on_wp) {
3345 u8 b_lu_write_protect;
3346
3347 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3348 &b_lu_write_protect) &&
3349 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3350 hba->dev_info.is_lu_power_on_wp = true;
3351 }
3352}
3353
7a3e97b0
SY		 3354/**
3355 * ufshcd_slave_alloc - handle initial SCSI device configurations
3356 * @sdev: pointer to SCSI device
3357 *
3358 * Returns success
3359 */
3360static int ufshcd_slave_alloc(struct scsi_device *sdev)
3361{
3362 struct ufs_hba *hba;
3363
3364 hba = shost_priv(sdev->host);
7a3e97b0
SY		 3365
3366 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3367 sdev->use_10_for_ms = 1;
7a3e97b0 3368
e8e7f271
SRT		 3369 /* allow SCSI layer to restart the device in case of errors */
3370 sdev->allow_restart = 1;
4264fd61 3371
b2a6c522
SRT		 3372 /* REPORT SUPPORTED OPERATION CODES is not supported */
3373 sdev->no_report_opcodes = 1;
3374
e8e7f271 3375
0ce147d4 3376 ufshcd_set_queue_depth(sdev);
4264fd61 3377
57d104c1
SJ		 3378 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3379
7a3e97b0
SY		 3380 return 0;
3381}
3382
4264fd61
SRT		 3383/**
3384 * ufshcd_change_queue_depth - change queue depth
3385 * @sdev: pointer to SCSI device
3386 * @depth: required depth to set
4264fd61 3387 *
db5ed4df 3388 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3389 */
db5ed4df 3390static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 3391{
3392 struct ufs_hba *hba = shost_priv(sdev->host);
3393
3394 if (depth > hba->nutrs)
3395 depth = hba->nutrs;
db5ed4df 3396 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3397}
3398
eeda4749
AM		 3399/**
3400 * ufshcd_slave_configure - adjust SCSI device configurations
3401 * @sdev: pointer to SCSI device
3402 */
3403static int ufshcd_slave_configure(struct scsi_device *sdev)
3404{
3405 struct request_queue *q = sdev->request_queue;
3406
3407 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3408 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3409
3410 return 0;
3411}
3412
7a3e97b0
SY		 3413/**
3414 * ufshcd_slave_destroy - remove SCSI device configurations
3415 * @sdev: pointer to SCSI device
3416 */
3417static void ufshcd_slave_destroy(struct scsi_device *sdev)
3418{
3419 struct ufs_hba *hba;
3420
3421 hba = shost_priv(sdev->host);
0ce147d4 3422 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3423 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3424 unsigned long flags;
3425
3426 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3427 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3428 spin_unlock_irqrestore(hba->host->host_lock, flags);
3429 }
7a3e97b0
SY		 3430}
3431
3432/**
3433 * ufshcd_task_req_compl - handle task management request completion
3434 * @hba: per adapter instance
3435 * @index: index of the completed request
e2933132 3436 * @resp: task management service response
7a3e97b0 3437 *
e2933132 3438 * Returns non-zero value on error, zero on success
7a3e97b0 3439 */
e2933132 3440static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3441{
3442 struct utp_task_req_desc *task_req_descp;
3443 struct utp_upiu_task_rsp *task_rsp_upiup;
3444 unsigned long flags;
3445 int ocs_value;
3446 int task_result;
3447
3448 spin_lock_irqsave(hba->host->host_lock, flags);
3449
3450 /* Clear completed tasks from outstanding_tasks */
3451 __clear_bit(index, &hba->outstanding_tasks);
3452
3453 task_req_descp = hba->utmrdl_base_addr;
3454 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3455
3456 if (ocs_value == OCS_SUCCESS) {
3457 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3458 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 3459 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3460 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 3461 if (resp)
3462 *resp = (u8)task_result;
7a3e97b0 3463 } else {
e2933132
SRT		 3464 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3465 __func__, ocs_value);
7a3e97b0
SY		 3466 }
3467 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3468
3469 return ocs_value;
7a3e97b0
SY		 3470}
3471
7a3e97b0
SY		 3472/**
3473 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3474 * @lrb: pointer to local reference block of completed command
3475 * @scsi_status: SCSI command status
3476 *
3477 * Returns value base on SCSI command status
3478 */
3479static inline int
3480ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3481{
3482 int result = 0;
3483
3484 switch (scsi_status) {
7a3e97b0 3485 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3486 ufshcd_copy_sense_data(lrbp);
3487 case SAM_STAT_GOOD:
7a3e97b0
SY		 3488 result |= DID_OK << 16 |
3489 COMMAND_COMPLETE << 8 |
1c2623c5 3490 scsi_status;
7a3e97b0
SY		 3491 break;
3492 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3493 case SAM_STAT_BUSY:
7a3e97b0 3494 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3495 ufshcd_copy_sense_data(lrbp);
3496 result |= scsi_status;
7a3e97b0
SY		 3497 break;
3498 default:
3499 result |= DID_ERROR << 16;
3500 break;
3501 } /* end of switch */
3502
3503 return result;
3504}
3505
3506/**
3507 * ufshcd_transfer_rsp_status - Get overall status of the response
3508 * @hba: per adapter instance
3509 * @lrb: pointer to local reference block of completed command
3510 *
3511 * Returns result of the command to notify SCSI midlayer
3512 */
3513static inline int
3514ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3515{
3516 int result = 0;
3517 int scsi_status;
3518 int ocs;
3519
3520 /* overall command status of utrd */
3521 ocs = ufshcd_get_tr_ocs(lrbp);
3522
3523 switch (ocs) {
3524 case OCS_SUCCESS:
5a0b0cb9 3525 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3526
5a0b0cb9
SRT		 3527 switch (result) {
3528 case UPIU_TRANSACTION_RESPONSE:
3529 /*
3530 * get the response UPIU result to extract
3531 * the SCSI command status
3532 */
3533 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3534
3535 /*
3536 * get the result based on SCSI status response
3537 * to notify the SCSI midlayer of the command status
3538 */
3539 scsi_status = result & MASK_SCSI_STATUS;
3540 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3541
f05ac2e5
YG		 3542 /*
3543 * Currently we are only supporting BKOPs exception
3544 * events hence we can ignore BKOPs exception event
3545 * during power management callbacks. BKOPs exception
3546 * event is not expected to be raised in runtime suspend
3547 * callback as it allows the urgent bkops.
3548 * During system suspend, we are anyway forcefully
3549 * disabling the bkops and if urgent bkops is needed
3550 * it will be enabled on system resume. Long term
3551 * solution could be to abort the system suspend if
3552 * UFS device needs urgent BKOPs.
3553 */
3554 if (!hba->pm_op_in_progress &&
3555 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3556 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3557 break;
3558 case UPIU_TRANSACTION_REJECT_UPIU:
3559 /* TODO: handle Reject UPIU Response */
3560 result = DID_ERROR << 16;
3b1d0580 3561 dev_err(hba->dev,
5a0b0cb9
SRT		 3562 "Reject UPIU not fully implemented\n");
3563 break;
3564 default:
3565 result = DID_ERROR << 16;
3566 dev_err(hba->dev,
3567 "Unexpected request response code = %x\n",
3568 result);
7a3e97b0
SY		 3569 break;
3570 }
7a3e97b0
SY		 3571 break;
3572 case OCS_ABORTED:
3573 result |= DID_ABORT << 16;
3574 break;
e8e7f271
SRT		 3575 case OCS_INVALID_COMMAND_STATUS:
3576 result |= DID_REQUEUE << 16;
3577 break;
7a3e97b0
SY		 3578 case OCS_INVALID_CMD_TABLE_ATTR:
3579 case OCS_INVALID_PRDT_ATTR:
3580 case OCS_MISMATCH_DATA_BUF_SIZE:
3581 case OCS_MISMATCH_RESP_UPIU_SIZE:
3582 case OCS_PEER_COMM_FAILURE:
3583 case OCS_FATAL_ERROR:
3584 default:
3585 result |= DID_ERROR << 16;
3b1d0580 3586 dev_err(hba->dev,
7a3e97b0
SY		 3587 "OCS error from controller = %x\n", ocs);
3588 break;
3589 } /* end of switch */
3590
3591 return result;
3592}
3593
6ccf44fe
SJ		 3594/**
3595 * ufshcd_uic_cmd_compl - handle completion of uic command
3596 * @hba: per adapter instance
53b3d9c3 3597 * @intr_status: interrupt status generated by the controller
6ccf44fe 3598 */
53b3d9c3 3599static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3600{
53b3d9c3 3601 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3602 hba->active_uic_cmd->argument2 |=
3603 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3604 hba->active_uic_cmd->argument3 =
3605 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3606 complete(&hba->active_uic_cmd->done);
3607 }
53b3d9c3 3608
57d104c1
SJ		 3609 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3610 complete(hba->uic_async_done);
6ccf44fe
SJ		 3611}
3612
7a3e97b0 3613/**
9a47ec7c 3614 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3615 * @hba: per adapter instance
9a47ec7c 3616 * @completed_reqs: requests to complete
7a3e97b0 3617 */
9a47ec7c
YG		 3618static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3619 unsigned long completed_reqs)
7a3e97b0 3620{
5a0b0cb9
SRT		 3621 struct ufshcd_lrb *lrbp;
3622 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3623 int result;
3624 int index;
e9d501b1 3625
e9d501b1
DR		 3626 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3627 lrbp = &hba->lrb[index];
3628 cmd = lrbp->cmd;
3629 if (cmd) {
3630 result = ufshcd_transfer_rsp_status(hba, lrbp);
3631 scsi_dma_unmap(cmd);
3632 cmd->result = result;
3633 /* Mark completed command as NULL in LRB */
3634 lrbp->cmd = NULL;
3635 clear_bit_unlock(index, &hba->lrb_in_use);
3636 /* Do not touch lrbp after scsi done */
3637 cmd->scsi_done(cmd);
1ab27c9c 3638 __ufshcd_release(hba);
300bb13f
JP		 3639 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3640 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR		 3641 if (hba->dev_cmd.complete)
3642 complete(hba->dev_cmd.complete);
3643 }
3644 }
7a3e97b0
SY		 3645
3646 /* clear corresponding bits of completed commands */
3647 hba->outstanding_reqs ^= completed_reqs;
3648
856b3483
ST		 3649 ufshcd_clk_scaling_update_busy(hba);
3650
5a0b0cb9
SRT		 3651 /* we might have free'd some tags above */
3652 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3653}
3654
9a47ec7c
YG		 3655/**
3656 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3657 * @hba: per adapter instance
3658 */
3659static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3660{
3661 unsigned long completed_reqs;
3662 u32 tr_doorbell;
3663
3664 /* Resetting interrupt aggregation counters first and reading the
3665 * DOOR_BELL afterward allows us to handle all the completed requests.
3666 * In order to prevent other interrupts starvation the DB is read once
3667 * after reset. The down side of this solution is the possibility of
3668 * false interrupt if device completes another request after resetting
3669 * aggregation and before reading the DB.
3670 */
3671 if (ufshcd_is_intr_aggr_allowed(hba))
3672 ufshcd_reset_intr_aggr(hba);
3673
3674 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3675 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3676
3677 __ufshcd_transfer_req_compl(hba, completed_reqs);
3678}
3679
66ec6d59
SRT		 3680/**
3681 * ufshcd_disable_ee - disable exception event
3682 * @hba: per-adapter instance
3683 * @mask: exception event to disable
3684 *
3685 * Disables exception event in the device so that the EVENT_ALERT
3686 * bit is not set.
3687 *
3688 * Returns zero on success, non-zero error value on failure.
3689 */
3690static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3691{
3692 int err = 0;
3693 u32 val;
3694
3695 if (!(hba->ee_ctrl_mask & mask))
3696 goto out;
3697
3698 val = hba->ee_ctrl_mask & ~mask;
3699 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3700 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3701 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3702 if (!err)
3703 hba->ee_ctrl_mask &= ~mask;
3704out:
3705 return err;
3706}
3707
3708/**
3709 * ufshcd_enable_ee - enable exception event
3710 * @hba: per-adapter instance
3711 * @mask: exception event to enable
3712 *
3713 * Enable corresponding exception event in the device to allow
3714 * device to alert host in critical scenarios.
3715 *
3716 * Returns zero on success, non-zero error value on failure.
3717 */
3718static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3719{
3720 int err = 0;
3721 u32 val;
3722
3723 if (hba->ee_ctrl_mask & mask)
3724 goto out;
3725
3726 val = hba->ee_ctrl_mask | mask;
3727 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3728 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3729 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3730 if (!err)
3731 hba->ee_ctrl_mask |= mask;
3732out:
3733 return err;
3734}
3735
3736/**
3737 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3738 * @hba: per-adapter instance
3739 *
3740 * Allow device to manage background operations on its own. Enabling
3741 * this might lead to inconsistent latencies during normal data transfers
3742 * as the device is allowed to manage its own way of handling background
3743 * operations.
3744 *
3745 * Returns zero on success, non-zero on failure.
3746 */
3747static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3748{
3749 int err = 0;
3750
3751 if (hba->auto_bkops_enabled)
3752 goto out;
3753
dc3c8d3a 3754 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 3755 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3756 if (err) {
3757 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3758 __func__, err);
3759 goto out;
3760 }
3761
3762 hba->auto_bkops_enabled = true;
3763
3764 /* No need of URGENT_BKOPS exception from the device */
3765 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3766 if (err)
3767 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3768 __func__, err);
3769out:
3770 return err;
3771}
3772
3773/**
3774 * ufshcd_disable_auto_bkops - block device in doing background operations
3775 * @hba: per-adapter instance
3776 *
3777 * Disabling background operations improves command response latency but
3778 * has drawback of device moving into critical state where the device is
3779 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3780 * host is idle so that BKOPS are managed effectively without any negative
3781 * impacts.
3782 *
3783 * Returns zero on success, non-zero on failure.
3784 */
3785static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3786{
3787 int err = 0;
3788
3789 if (!hba->auto_bkops_enabled)
3790 goto out;
3791
3792 /*
3793 * If host assisted BKOPs is to be enabled, make sure
3794 * urgent bkops exception is allowed.
3795 */
3796 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3797 if (err) {
3798 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3799 __func__, err);
3800 goto out;
3801 }
3802
dc3c8d3a 3803 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 3804 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3805 if (err) {
3806 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3807 __func__, err);
3808 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3809 goto out;
3810 }
3811
3812 hba->auto_bkops_enabled = false;
3813out:
3814 return err;
3815}
3816
3817/**
3818 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3819 * @hba: per adapter instance
3820 *
3821 * After a device reset the device may toggle the BKOPS_EN flag
3822 * to default value. The s/w tracking variables should be updated
3823 * as well. Do this by forcing enable of auto bkops.
3824 */
3825static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3826{
3827 hba->auto_bkops_enabled = false;
3828 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3829 ufshcd_enable_auto_bkops(hba);
3830}
3831
3832static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3833{
5e86ae44 3834 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3835 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3836}
3837
3838/**
57d104c1 3839 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3840 * @hba: per-adapter instance
57d104c1 3841 * @status: bkops_status value
66ec6d59 3842 *
57d104c1
SJ		 3843 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3844 * flag in the device to permit background operations if the device
3845 * bkops_status is greater than or equal to "status" argument passed to
3846 * this function, disable otherwise.
3847 *
3848 * Returns 0 for success, non-zero in case of failure.
3849 *
3850 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3851 * to know whether auto bkops is enabled or disabled after this function
3852 * returns control to it.
66ec6d59 3853 */
57d104c1
SJ		 3854static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3855 enum bkops_status status)
66ec6d59
SRT		 3856{
3857 int err;
57d104c1 3858 u32 curr_status = 0;
66ec6d59 3859
57d104c1 3860 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3861 if (err) {
3862 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3863 __func__, err);
3864 goto out;
57d104c1
SJ		 3865 } else if (curr_status > BKOPS_STATUS_MAX) {
3866 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3867 __func__, curr_status);
3868 err = -EINVAL;
3869 goto out;
66ec6d59
SRT		 3870 }
3871
57d104c1 3872 if (curr_status >= status)
66ec6d59 3873 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3874 else
3875 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3876out:
3877 return err;
3878}
3879
57d104c1
SJ		 3880/**
3881 * ufshcd_urgent_bkops - handle urgent bkops exception event
3882 * @hba: per-adapter instance
3883 *
3884 * Enable fBackgroundOpsEn flag in the device to permit background
3885 * operations.
3886 *
3887 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3888 * and negative error value for any other failure.
3889 */
3890static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3891{
afdfff59 3892 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 3893}
3894
66ec6d59
SRT		 3895static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3896{
5e86ae44 3897 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3898 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3899}
3900
afdfff59
YG		 3901static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
3902{
3903 int err;
3904 u32 curr_status = 0;
3905
3906 if (hba->is_urgent_bkops_lvl_checked)
3907 goto enable_auto_bkops;
3908
3909 err = ufshcd_get_bkops_status(hba, &curr_status);
3910 if (err) {
3911 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3912 __func__, err);
3913 goto out;
3914 }
3915
3916 /*
3917 * We are seeing that some devices are raising the urgent bkops
3918 * exception events even when BKOPS status doesn't indicate performace
3919 * impacted or critical. Handle these device by determining their urgent
3920 * bkops status at runtime.
3921 */
3922 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
3923 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
3924 __func__, curr_status);
3925 /* update the current status as the urgent bkops level */
3926 hba->urgent_bkops_lvl = curr_status;
3927 hba->is_urgent_bkops_lvl_checked = true;
3928 }
3929
3930enable_auto_bkops:
3931 err = ufshcd_enable_auto_bkops(hba);
3932out:
3933 if (err < 0)
3934 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3935 __func__, err);
3936}
3937
66ec6d59
SRT		 3938/**
3939 * ufshcd_exception_event_handler - handle exceptions raised by device
3940 * @work: pointer to work data
3941 *
3942 * Read bExceptionEventStatus attribute from the device and handle the
3943 * exception event accordingly.
3944 */
3945static void ufshcd_exception_event_handler(struct work_struct *work)
3946{
3947 struct ufs_hba *hba;
3948 int err;
3949 u32 status = 0;
3950 hba = container_of(work, struct ufs_hba, eeh_work);
3951
62694735 3952 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3953 err = ufshcd_get_ee_status(hba, &status);
3954 if (err) {
3955 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3956 __func__, err);
3957 goto out;
3958 }
3959
3960 status &= hba->ee_ctrl_mask;
afdfff59
YG		 3961
3962 if (status & MASK_EE_URGENT_BKOPS)
3963 ufshcd_bkops_exception_event_handler(hba);
3964
66ec6d59 3965out:
62694735 3966 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3967 return;
3968}
3969
9a47ec7c
YG		 3970/* Complete requests that have door-bell cleared */
3971static void ufshcd_complete_requests(struct ufs_hba *hba)
3972{
3973 ufshcd_transfer_req_compl(hba);
3974 ufshcd_tmc_handler(hba);
3975}
3976
583fa62d
YG		 3977/**
3978 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
3979 * to recover from the DL NAC errors or not.
3980 * @hba: per-adapter instance
3981 *
3982 * Returns true if error handling is required, false otherwise
3983 */
3984static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
3985{
3986 unsigned long flags;
3987 bool err_handling = true;
3988
3989 spin_lock_irqsave(hba->host->host_lock, flags);
3990 /*
3991 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
3992 * device fatal error and/or DL NAC & REPLAY timeout errors.
3993 */
3994 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
3995 goto out;
3996
3997 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
3998 ((hba->saved_err & UIC_ERROR) &&
3999 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4000 goto out;
4001
4002 if ((hba->saved_err & UIC_ERROR) &&
4003 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4004 int err;
4005 /*
4006 * wait for 50ms to see if we can get any other errors or not.
4007 */
4008 spin_unlock_irqrestore(hba->host->host_lock, flags);
4009 msleep(50);
4010 spin_lock_irqsave(hba->host->host_lock, flags);
4011
4012 /*
4013 * now check if we have got any other severe errors other than
4014 * DL NAC error?
4015 */
4016 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4017 ((hba->saved_err & UIC_ERROR) &&
4018 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4019 goto out;
4020
4021 /*
4022 * As DL NAC is the only error received so far, send out NOP
4023 * command to confirm if link is still active or not.
4024 * - If we don't get any response then do error recovery.
4025 * - If we get response then clear the DL NAC error bit.
4026 */
4027
4028 spin_unlock_irqrestore(hba->host->host_lock, flags);
4029 err = ufshcd_verify_dev_init(hba);
4030 spin_lock_irqsave(hba->host->host_lock, flags);
4031
4032 if (err)
4033 goto out;
4034
4035 /* Link seems to be alive hence ignore the DL NAC errors */
4036 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
4037 hba->saved_err &= ~UIC_ERROR;
4038 /* clear NAC error */
4039 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4040 if (!hba->saved_uic_err) {
4041 err_handling = false;
4042 goto out;
4043 }
4044 }
4045out:
4046 spin_unlock_irqrestore(hba->host->host_lock, flags);
4047 return err_handling;
4048}
4049
7a3e97b0 4050/**
e8e7f271
SRT		 4051 * ufshcd_err_handler - handle UFS errors that require s/w attention
4052 * @work: pointer to work structure
7a3e97b0 4053 */
e8e7f271 4054static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 4055{
4056 struct ufs_hba *hba;
e8e7f271
SRT		 4057 unsigned long flags;
4058 u32 err_xfer = 0;
4059 u32 err_tm = 0;
4060 int err = 0;
4061 int tag;
9a47ec7c 4062 bool needs_reset = false;
e8e7f271
SRT		 4063
4064 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 4065
62694735 4066 pm_runtime_get_sync(hba->dev);
1ab27c9c 4067 ufshcd_hold(hba, false);
e8e7f271
SRT		 4068
4069 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 4070 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 4071 goto out;
e8e7f271
SRT		 4072
4073 hba->ufshcd_state = UFSHCD_STATE_RESET;
4074 ufshcd_set_eh_in_progress(hba);
4075
4076 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 4077 ufshcd_complete_requests(hba);
583fa62d
YG		 4078
4079 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4080 bool ret;
4081
4082 spin_unlock_irqrestore(hba->host->host_lock, flags);
4083 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
4084 ret = ufshcd_quirk_dl_nac_errors(hba);
4085 spin_lock_irqsave(hba->host->host_lock, flags);
4086 if (!ret)
4087 goto skip_err_handling;
4088 }
9a47ec7c
YG		 4089 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4090 ((hba->saved_err & UIC_ERROR) &&
4091 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4092 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4093 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4094 needs_reset = true;
e8e7f271 4095
9a47ec7c
YG		 4096 /*
4097 * if host reset is required then skip clearing the pending
4098 * transfers forcefully because they will automatically get
4099 * cleared after link startup.
4100 */
4101 if (needs_reset)
4102 goto skip_pending_xfer_clear;
4103
4104 /* release lock as clear command might sleep */
4105 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4106 /* Clear pending transfer requests */
9a47ec7c
YG		 4107 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4108 if (ufshcd_clear_cmd(hba, tag)) {
4109 err_xfer = true;
4110 goto lock_skip_pending_xfer_clear;
4111 }
4112 }
e8e7f271
SRT		 4113
4114 /* Clear pending task management requests */
9a47ec7c
YG		 4115 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4116 if (ufshcd_clear_tm_cmd(hba, tag)) {
4117 err_tm = true;
4118 goto lock_skip_pending_xfer_clear;
4119 }
4120 }
e8e7f271 4121
9a47ec7c 4122lock_skip_pending_xfer_clear:
e8e7f271 4123 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4124
9a47ec7c
YG		 4125 /* Complete the requests that are cleared by s/w */
4126 ufshcd_complete_requests(hba);
4127
4128 if (err_xfer || err_tm)
4129 needs_reset = true;
4130
4131skip_pending_xfer_clear:
e8e7f271 4132 /* Fatal errors need reset */
9a47ec7c
YG		 4133 if (needs_reset) {
4134 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4135
4136 /*
4137 * ufshcd_reset_and_restore() does the link reinitialization
4138 * which will need atleast one empty doorbell slot to send the
4139 * device management commands (NOP and query commands).
4140 * If there is no slot empty at this moment then free up last
4141 * slot forcefully.
4142 */
4143 if (hba->outstanding_reqs == max_doorbells)
4144 __ufshcd_transfer_req_compl(hba,
4145 (1UL << (hba->nutrs - 1)));
4146
4147 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4148 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4149 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 4150 if (err) {
4151 dev_err(hba->dev, "%s: reset and restore failed\n",
4152 __func__);
4153 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4154 }
4155 /*
4156 * Inform scsi mid-layer that we did reset and allow to handle
4157 * Unit Attention properly.
4158 */
4159 scsi_report_bus_reset(hba->host, 0);
4160 hba->saved_err = 0;
4161 hba->saved_uic_err = 0;
4162 }
9a47ec7c 4163
583fa62d 4164skip_err_handling:
9a47ec7c
YG		 4165 if (!needs_reset) {
4166 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4167 if (hba->saved_err || hba->saved_uic_err)
4168 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4169 __func__, hba->saved_err, hba->saved_uic_err);
4170 }
4171
e8e7f271
SRT		 4172 ufshcd_clear_eh_in_progress(hba);
4173
4174out:
9a47ec7c 4175 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4176 scsi_unblock_requests(hba->host);
1ab27c9c 4177 ufshcd_release(hba);
62694735 4178 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 4179}
4180
4181/**
e8e7f271
SRT		 4182 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4183 * @hba: per-adapter instance
7a3e97b0 4184 */
e8e7f271 4185static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 4186{
4187 u32 reg;
4188
e8e7f271
SRT		 4189 /* PA_INIT_ERROR is fatal and needs UIC reset */
4190 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4191 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4192 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 4193 else if (hba->dev_quirks &
4194 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4195 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4196 hba->uic_error |=
4197 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4198 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4199 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4200 }
e8e7f271
SRT		 4201
4202 /* UIC NL/TL/DME errors needs software retry */
4203 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4204 if (reg)
4205 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4206
4207 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4208 if (reg)
4209 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4210
4211 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4212 if (reg)
4213 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4214
4215 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4216 __func__, hba->uic_error);
4217}
4218
4219/**
4220 * ufshcd_check_errors - Check for errors that need s/w attention
4221 * @hba: per-adapter instance
4222 */
4223static void ufshcd_check_errors(struct ufs_hba *hba)
4224{
4225 bool queue_eh_work = false;
4226
7a3e97b0 4227 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4228 queue_eh_work = true;
7a3e97b0
SY		 4229
4230 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 4231 hba->uic_error = 0;
4232 ufshcd_update_uic_error(hba);
4233 if (hba->uic_error)
4234 queue_eh_work = true;
7a3e97b0 4235 }
e8e7f271
SRT		 4236
4237 if (queue_eh_work) {
9a47ec7c
YG		 4238 /*
4239 * update the transfer error masks to sticky bits, let's do this
4240 * irrespective of current ufshcd_state.
4241 */
4242 hba->saved_err |= hba->errors;
4243 hba->saved_uic_err |= hba->uic_error;
4244
e8e7f271
SRT		 4245 /* handle fatal errors only when link is functional */
4246 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4247 /* block commands from scsi mid-layer */
4248 scsi_block_requests(hba->host);
4249
141f8165 4250 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
e8e7f271
SRT		 4251 schedule_work(&hba->eh_work);
4252 }
3441da7d 4253 }
e8e7f271
SRT		 4254 /*
4255 * if (!queue_eh_work) -
4256 * Other errors are either non-fatal where host recovers
4257 * itself without s/w intervention or errors that will be
4258 * handled by the SCSI core layer.
4259 */
7a3e97b0
SY		 4260}
4261
4262/**
4263 * ufshcd_tmc_handler - handle task management function completion
4264 * @hba: per adapter instance
4265 */
4266static void ufshcd_tmc_handler(struct ufs_hba *hba)
4267{
4268 u32 tm_doorbell;
4269
b873a275 4270 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4271 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4272 wake_up(&hba->tm_wq);
7a3e97b0
SY		 4273}
4274
4275/**
4276 * ufshcd_sl_intr - Interrupt service routine
4277 * @hba: per adapter instance
4278 * @intr_status: contains interrupts generated by the controller
4279 */
4280static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4281{
4282 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4283 if (hba->errors)
e8e7f271 4284 ufshcd_check_errors(hba);
7a3e97b0 4285
53b3d9c3
SJ		 4286 if (intr_status & UFSHCD_UIC_MASK)
4287 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 4288
4289 if (intr_status & UTP_TASK_REQ_COMPL)
4290 ufshcd_tmc_handler(hba);
4291
4292 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4293 ufshcd_transfer_req_compl(hba);
4294}
4295
4296/**
4297 * ufshcd_intr - Main interrupt service routine
4298 * @irq: irq number
4299 * @__hba: pointer to adapter instance
4300 *
4301 * Returns IRQ_HANDLED - If interrupt is valid
4302 * IRQ_NONE - If invalid interrupt
4303 */
4304static irqreturn_t ufshcd_intr(int irq, void *__hba)
4305{
d75f7fe4 4306 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 4307 irqreturn_t retval = IRQ_NONE;
4308 struct ufs_hba *hba = __hba;
4309
4310 spin_lock(hba->host->host_lock);
b873a275 4311 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4312 enabled_intr_status =
4313 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4314
d75f7fe4 4315 if (intr_status)
261ea452 4316 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4317
4318 if (enabled_intr_status) {
4319 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 4320 retval = IRQ_HANDLED;
4321 }
4322 spin_unlock(hba->host->host_lock);
4323 return retval;
4324}
4325
e2933132
SRT		 4326static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4327{
4328 int err = 0;
4329 u32 mask = 1 << tag;
4330 unsigned long flags;
4331
4332 if (!test_bit(tag, &hba->outstanding_tasks))
4333 goto out;
4334
4335 spin_lock_irqsave(hba->host->host_lock, flags);
4336 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4337 spin_unlock_irqrestore(hba->host->host_lock, flags);
4338
4339 /* poll for max. 1 sec to clear door bell register by h/w */
4340 err = ufshcd_wait_for_register(hba,
4341 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4342 mask, 0, 1000, 1000, true);
e2933132
SRT		 4343out:
4344 return err;
4345}
4346
7a3e97b0
SY		 4347/**
4348 * ufshcd_issue_tm_cmd - issues task management commands to controller
4349 * @hba: per adapter instance
e2933132
SRT		 4350 * @lun_id: LUN ID to which TM command is sent
4351 * @task_id: task ID to which the TM command is applicable
4352 * @tm_function: task management function opcode
4353 * @tm_response: task management service response return value
7a3e97b0 4354 *
e2933132 4355 * Returns non-zero value on error, zero on success.
7a3e97b0 4356 */
e2933132
SRT		 4357static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4358 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 4359{
4360 struct utp_task_req_desc *task_req_descp;
4361 struct utp_upiu_task_req *task_req_upiup;
4362 struct Scsi_Host *host;
4363 unsigned long flags;
e2933132 4364 int free_slot;
7a3e97b0 4365 int err;
e2933132 4366 int task_tag;
7a3e97b0
SY		 4367
4368 host = hba->host;
4369
e2933132
SRT		 4370 /*
4371 * Get free slot, sleep if slots are unavailable.
4372 * Even though we use wait_event() which sleeps indefinitely,
4373 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4374 */
4375 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4376 ufshcd_hold(hba, false);
7a3e97b0 4377
e2933132 4378 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 4379 task_req_descp = hba->utmrdl_base_addr;
4380 task_req_descp += free_slot;
4381
4382 /* Configure task request descriptor */
4383 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4384 task_req_descp->header.dword_2 =
4385 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4386
4387 /* Configure task request UPIU */
4388 task_req_upiup =
4389 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4390 task_tag = hba->nutrs + free_slot;
7a3e97b0 4391 task_req_upiup->header.dword_0 =
5a0b0cb9 4392 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4393 lun_id, task_tag);
7a3e97b0 4394 task_req_upiup->header.dword_1 =
5a0b0cb9 4395 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 4396 /*
4397 * The host shall provide the same value for LUN field in the basic
4398 * header and for Input Parameter.
4399 */
e2933132
SRT		 4400 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4401 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 4402
d2877be4
KK		 4403 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
4404
7a3e97b0
SY		 4405 /* send command to the controller */
4406 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 4407
4408 /* Make sure descriptors are ready before ringing the task doorbell */
4409 wmb();
4410
b873a275 4411 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 4412 /* Make sure that doorbell is committed immediately */
4413 wmb();
7a3e97b0
SY		 4414
4415 spin_unlock_irqrestore(host->host_lock, flags);
4416
4417 /* wait until the task management command is completed */
e2933132
SRT		 4418 err = wait_event_timeout(hba->tm_wq,
4419 test_bit(free_slot, &hba->tm_condition),
4420 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4421 if (!err) {
e2933132
SRT		 4422 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4423 __func__, tm_function);
4424 if (ufshcd_clear_tm_cmd(hba, free_slot))
4425 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4426 __func__, free_slot);
4427 err = -ETIMEDOUT;
4428 } else {
4429 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4430 }
e2933132 4431
7a3e97b0 4432 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 4433 ufshcd_put_tm_slot(hba, free_slot);
4434 wake_up(&hba->tm_tag_wq);
4435
1ab27c9c 4436 ufshcd_release(hba);
7a3e97b0
SY		 4437 return err;
4438}
4439
4440/**
3441da7d
SRT		 4441 * ufshcd_eh_device_reset_handler - device reset handler registered to
4442 * scsi layer.
7a3e97b0
SY		 4443 * @cmd: SCSI command pointer
4444 *
4445 * Returns SUCCESS/FAILED
4446 */
3441da7d 4447static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 4448{
4449 struct Scsi_Host *host;
4450 struct ufs_hba *hba;
4451 unsigned int tag;
4452 u32 pos;
4453 int err;
e2933132
SRT		 4454 u8 resp = 0xF;
4455 struct ufshcd_lrb *lrbp;
3441da7d 4456 unsigned long flags;
7a3e97b0
SY		 4457
4458 host = cmd->device->host;
4459 hba = shost_priv(host);
4460 tag = cmd->request->tag;
4461
e2933132
SRT		 4462 lrbp = &hba->lrb[tag];
4463 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4464 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 4465 if (!err)
4466 err = resp;
7a3e97b0 4467 goto out;
e2933132 4468 }
7a3e97b0 4469
3441da7d
SRT		 4470 /* clear the commands that were pending for corresponding LUN */
4471 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4472 if (hba->lrb[pos].lun == lrbp->lun) {
4473 err = ufshcd_clear_cmd(hba, pos);
4474 if (err)
4475 break;
7a3e97b0 4476 }
3441da7d
SRT		 4477 }
4478 spin_lock_irqsave(host->host_lock, flags);
4479 ufshcd_transfer_req_compl(hba);
4480 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4481out:
3441da7d
SRT		 4482 if (!err) {
4483 err = SUCCESS;
4484 } else {
4485 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4486 err = FAILED;
4487 }
7a3e97b0
SY		 4488 return err;
4489}
4490
7a3e97b0
SY		 4491/**
4492 * ufshcd_abort - abort a specific command
4493 * @cmd: SCSI command pointer
4494 *
f20810d8
SRT		 4495 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4496 * command, and in host controller by clearing the door-bell register. There can
4497 * be race between controller sending the command to the device while abort is
4498 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4499 * really issued and then try to abort it.
4500 *
7a3e97b0
SY		 4501 * Returns SUCCESS/FAILED
4502 */
4503static int ufshcd_abort(struct scsi_cmnd *cmd)
4504{
4505 struct Scsi_Host *host;
4506 struct ufs_hba *hba;
4507 unsigned long flags;
4508 unsigned int tag;
f20810d8
SRT		 4509 int err = 0;
4510 int poll_cnt;
e2933132
SRT		 4511 u8 resp = 0xF;
4512 struct ufshcd_lrb *lrbp;
e9d501b1 4513 u32 reg;
7a3e97b0
SY		 4514
4515 host = cmd->device->host;
4516 hba = shost_priv(host);
4517 tag = cmd->request->tag;
14497328
YG		 4518 if (!ufshcd_valid_tag(hba, tag)) {
4519 dev_err(hba->dev,
4520 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4521 __func__, tag, cmd, cmd->request);
4522 BUG();
4523 }
7a3e97b0 4524
1ab27c9c 4525 ufshcd_hold(hba, false);
14497328 4526 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4527 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 4528 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4529 dev_err(hba->dev,
4530 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4531 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4532 goto out;
14497328 4533 }
7a3e97b0 4534
e9d501b1
DR		 4535 if (!(reg & (1 << tag))) {
4536 dev_err(hba->dev,
4537 "%s: cmd was completed, but without a notifying intr, tag = %d",
4538 __func__, tag);
4539 }
4540
f20810d8
SRT		 4541 lrbp = &hba->lrb[tag];
4542 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4543 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4544 UFS_QUERY_TASK, &resp);
4545 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4546 /* cmd pending in the device */
4547 break;
4548 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4549 /*
4550 * cmd not pending in the device, check if it is
4551 * in transition.
4552 */
4553 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4554 if (reg & (1 << tag)) {
4555 /* sleep for max. 200us to stabilize */
4556 usleep_range(100, 200);
4557 continue;
4558 }
4559 /* command completed already */
4560 goto out;
4561 } else {
4562 if (!err)
4563 err = resp; /* service response error */
4564 goto out;
4565 }
4566 }
4567
4568 if (!poll_cnt) {
4569 err = -EBUSY;
7a3e97b0
SY		 4570 goto out;
4571 }
7a3e97b0 4572
e2933132
SRT		 4573 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4574 UFS_ABORT_TASK, &resp);
4575 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4576 if (!err)
4577 err = resp; /* service response error */
7a3e97b0 4578 goto out;
e2933132 4579 }
7a3e97b0 4580
f20810d8
SRT		 4581 err = ufshcd_clear_cmd(hba, tag);
4582 if (err)
4583 goto out;
4584
7a3e97b0
SY		 4585 scsi_dma_unmap(cmd);
4586
4587 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4588 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 4589 hba->lrb[tag].cmd = NULL;
4590 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 4591
4592 clear_bit_unlock(tag, &hba->lrb_in_use);
4593 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4594
7a3e97b0 4595out:
f20810d8
SRT		 4596 if (!err) {
4597 err = SUCCESS;
4598 } else {
4599 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4600 err = FAILED;
4601 }
4602
1ab27c9c
ST		 4603 /*
4604 * This ufshcd_release() corresponds to the original scsi cmd that got
4605 * aborted here (as we won't get any IRQ for it).
4606 */
4607 ufshcd_release(hba);
7a3e97b0
SY		 4608 return err;
4609}
4610
3441da7d
SRT		 4611/**
4612 * ufshcd_host_reset_and_restore - reset and restore host controller
4613 * @hba: per-adapter instance
4614 *
4615 * Note that host controller reset may issue DME_RESET to
4616 * local and remote (device) Uni-Pro stack and the attributes
4617 * are reset to default state.
4618 *
4619 * Returns zero on success, non-zero on failure
4620 */
4621static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4622{
4623 int err;
3441da7d
SRT		 4624 unsigned long flags;
4625
4626 /* Reset the host controller */
4627 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4628 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 4629 spin_unlock_irqrestore(hba->host->host_lock, flags);
4630
4631 err = ufshcd_hba_enable(hba);
4632 if (err)
4633 goto out;
4634
4635 /* Establish the link again and restore the device */
1d337ec2
SRT		 4636 err = ufshcd_probe_hba(hba);
4637
4638 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 4639 err = -EIO;
4640out:
4641 if (err)
4642 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4643
4644 return err;
4645}
4646
4647/**
4648 * ufshcd_reset_and_restore - reset and re-initialize host/device
4649 * @hba: per-adapter instance
4650 *
4651 * Reset and recover device, host and re-establish link. This
4652 * is helpful to recover the communication in fatal error conditions.
4653 *
4654 * Returns zero on success, non-zero on failure
4655 */
4656static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4657{
4658 int err = 0;
4659 unsigned long flags;
1d337ec2 4660 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4661
1d337ec2
SRT		 4662 do {
4663 err = ufshcd_host_reset_and_restore(hba);
4664 } while (err && --retries);
3441da7d
SRT		 4665
4666 /*
4667 * After reset the door-bell might be cleared, complete
4668 * outstanding requests in s/w here.
4669 */
4670 spin_lock_irqsave(hba->host->host_lock, flags);
4671 ufshcd_transfer_req_compl(hba);
4672 ufshcd_tmc_handler(hba);
4673 spin_unlock_irqrestore(hba->host->host_lock, flags);
4674
4675 return err;
4676}
4677
4678/**
4679 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4680 * @cmd - SCSI command pointer
4681 *
4682 * Returns SUCCESS/FAILED
4683 */
4684static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4685{
4686 int err;
4687 unsigned long flags;
4688 struct ufs_hba *hba;
4689
4690 hba = shost_priv(cmd->device->host);
4691
1ab27c9c 4692 ufshcd_hold(hba, false);
3441da7d
SRT		 4693 /*
4694 * Check if there is any race with fatal error handling.
4695 * If so, wait for it to complete. Even though fatal error
4696 * handling does reset and restore in some cases, don't assume
4697 * anything out of it. We are just avoiding race here.
4698 */
4699 do {
4700 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4701 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 4702 hba->ufshcd_state == UFSHCD_STATE_RESET))
4703 break;
4704 spin_unlock_irqrestore(hba->host->host_lock, flags);
4705 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4706 flush_work(&hba->eh_work);
3441da7d
SRT		 4707 } while (1);
4708
4709 hba->ufshcd_state = UFSHCD_STATE_RESET;
4710 ufshcd_set_eh_in_progress(hba);
4711 spin_unlock_irqrestore(hba->host->host_lock, flags);
4712
4713 err = ufshcd_reset_and_restore(hba);
4714
4715 spin_lock_irqsave(hba->host->host_lock, flags);
4716 if (!err) {
4717 err = SUCCESS;
4718 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4719 } else {
4720 err = FAILED;
4721 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4722 }
4723 ufshcd_clear_eh_in_progress(hba);
4724 spin_unlock_irqrestore(hba->host->host_lock, flags);
4725
1ab27c9c 4726 ufshcd_release(hba);
3441da7d
SRT		 4727 return err;
4728}
4729
3a4bf06d
YG		 4730/**
4731 * ufshcd_get_max_icc_level - calculate the ICC level
4732 * @sup_curr_uA: max. current supported by the regulator
4733 * @start_scan: row at the desc table to start scan from
4734 * @buff: power descriptor buffer
4735 *
4736 * Returns calculated max ICC level for specific regulator
4737 */
4738static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4739{
4740 int i;
4741 int curr_uA;
4742 u16 data;
4743 u16 unit;
4744
4745 for (i = start_scan; i >= 0; i--) {
4746 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4747 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4748 ATTR_ICC_LVL_UNIT_OFFSET;
4749 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4750 switch (unit) {
4751 case UFSHCD_NANO_AMP:
4752 curr_uA = curr_uA / 1000;
4753 break;
4754 case UFSHCD_MILI_AMP:
4755 curr_uA = curr_uA * 1000;
4756 break;
4757 case UFSHCD_AMP:
4758 curr_uA = curr_uA * 1000 * 1000;
4759 break;
4760 case UFSHCD_MICRO_AMP:
4761 default:
4762 break;
4763 }
4764 if (sup_curr_uA >= curr_uA)
4765 break;
4766 }
4767 if (i < 0) {
4768 i = 0;
4769 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4770 }
4771
4772 return (u32)i;
4773}
4774
4775/**
4776 * ufshcd_calc_icc_level - calculate the max ICC level
4777 * In case regulators are not initialized we'll return 0
4778 * @hba: per-adapter instance
4779 * @desc_buf: power descriptor buffer to extract ICC levels from.
4780 * @len: length of desc_buff
4781 *
4782 * Returns calculated ICC level
4783 */
4784static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4785 u8 *desc_buf, int len)
4786{
4787 u32 icc_level = 0;
4788
4789 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4790 !hba->vreg_info.vccq2) {
4791 dev_err(hba->dev,
4792 "%s: Regulator capability was not set, actvIccLevel=%d",
4793 __func__, icc_level);
4794 goto out;
4795 }
4796
4797 if (hba->vreg_info.vcc)
4798 icc_level = ufshcd_get_max_icc_level(
4799 hba->vreg_info.vcc->max_uA,
4800 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4801 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4802
4803 if (hba->vreg_info.vccq)
4804 icc_level = ufshcd_get_max_icc_level(
4805 hba->vreg_info.vccq->max_uA,
4806 icc_level,
4807 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4808
4809 if (hba->vreg_info.vccq2)
4810 icc_level = ufshcd_get_max_icc_level(
4811 hba->vreg_info.vccq2->max_uA,
4812 icc_level,
4813 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4814out:
4815 return icc_level;
4816}
4817
61e07359
DR		 4818static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
4819{
4820 int ret = 0;
4821 int retries;
4822
4823 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4824 /* write attribute */
4825 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4826 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
4827 if (!ret)
4828 break;
4829
4830 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
4831 }
4832
4833 return ret;
4834}
4835
3a4bf06d
YG		 4836static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4837{
4838 int ret;
4839 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4840 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4841
4842 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4843 if (ret) {
4844 dev_err(hba->dev,
4845 "%s: Failed reading power descriptor.len = %d ret = %d",
4846 __func__, buff_len, ret);
4847 return;
4848 }
4849
4850 hba->init_prefetch_data.icc_level =
4851 ufshcd_find_max_sup_active_icc_level(hba,
4852 desc_buf, buff_len);
4853 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4854 __func__, hba->init_prefetch_data.icc_level);
4855
61e07359
DR		 4856 ret = ufshcd_set_icc_levels_attr(hba,
4857 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 4858
4859 if (ret)
4860 dev_err(hba->dev,
4861 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4862 __func__, hba->init_prefetch_data.icc_level , ret);
4863
4864}
4865
2a8fa600
SJ		 4866/**
4867 * ufshcd_scsi_add_wlus - Adds required W-LUs
4868 * @hba: per-adapter instance
4869 *
4870 * UFS device specification requires the UFS devices to support 4 well known
4871 * logical units:
4872 * "REPORT_LUNS" (address: 01h)
4873 * "UFS Device" (address: 50h)
4874 * "RPMB" (address: 44h)
4875 * "BOOT" (address: 30h)
4876 * UFS device's power management needs to be controlled by "POWER CONDITION"
4877 * field of SSU (START STOP UNIT) command. But this "power condition" field
4878 * will take effect only when its sent to "UFS device" well known logical unit
4879 * hence we require the scsi_device instance to represent this logical unit in
4880 * order for the UFS host driver to send the SSU command for power management.
4881
4882 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4883 * Block) LU so user space process can control this LU. User space may also
4884 * want to have access to BOOT LU.
4885
4886 * This function adds scsi device instances for each of all well known LUs
4887 * (except "REPORT LUNS" LU).
4888 *
4889 * Returns zero on success (all required W-LUs are added successfully),
4890 * non-zero error value on failure (if failed to add any of the required W-LU).
4891 */
4892static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4893{
4894 int ret = 0;
7c48bfd0
AM		 4895 struct scsi_device *sdev_rpmb;
4896 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4897
4898 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4899 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4900 if (IS_ERR(hba->sdev_ufs_device)) {
4901 ret = PTR_ERR(hba->sdev_ufs_device);
4902 hba->sdev_ufs_device = NULL;
4903 goto out;
4904 }
7c48bfd0 4905 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4906
7c48bfd0 4907 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4908 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4909 if (IS_ERR(sdev_boot)) {
4910 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4911 goto remove_sdev_ufs_device;
4912 }
7c48bfd0 4913 scsi_device_put(sdev_boot);
2a8fa600 4914
7c48bfd0 4915 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4916 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4917 if (IS_ERR(sdev_rpmb)) {
4918 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4919 goto remove_sdev_boot;
4920 }
7c48bfd0 4921 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4922 goto out;
4923
4924remove_sdev_boot:
7c48bfd0 4925 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4926remove_sdev_ufs_device:
4927 scsi_remove_device(hba->sdev_ufs_device);
4928out:
4929 return ret;
4930}
4931
c58ab7aa
YG		 4932static int ufs_get_device_info(struct ufs_hba *hba,
4933 struct ufs_device_info *card_data)
4934{
4935 int err;
4936 u8 model_index;
4937 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
4938 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
4939
4940 err = ufshcd_read_device_desc(hba, desc_buf,
4941 QUERY_DESC_DEVICE_MAX_SIZE);
4942 if (err) {
4943 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
4944 __func__, err);
4945 goto out;
4946 }
4947
4948 /*
4949 * getting vendor (manufacturerID) and Bank Index in big endian
4950 * format
4951 */
4952 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
4953 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
4954
4955 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4956
4957 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
4958 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
4959 if (err) {
4960 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
4961 __func__, err);
4962 goto out;
4963 }
4964
4965 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
4966 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
4967 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
4968 MAX_MODEL_LEN));
4969
4970 /* Null terminate the model string */
4971 card_data->model[MAX_MODEL_LEN] = '\0';
4972
4973out:
4974 return err;
4975}
4976
4977void ufs_advertise_fixup_device(struct ufs_hba *hba)
4978{
4979 int err;
4980 struct ufs_dev_fix *f;
4981 struct ufs_device_info card_data;
4982
4983 card_data.wmanufacturerid = 0;
4984
4985 err = ufs_get_device_info(hba, &card_data);
4986 if (err) {
4987 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
4988 __func__, err);
4989 return;
4990 }
4991
4992 for (f = ufs_fixups; f->quirk; f++) {
4993 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
4994 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
4995 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
4996 !strcmp(f->card.model, UFS_ANY_MODEL)))
4997 hba->dev_quirks |= f->quirk;
4998 }
4999}
5000
37113106
YG		 5001/**
5002 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
5003 * @hba: per-adapter instance
5004 *
5005 * PA_TActivate parameter can be tuned manually if UniPro version is less than
5006 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
5007 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
5008 * the hibern8 exit latency.
5009 *
5010 * Returns zero on success, non-zero error value on failure.
5011 */
5012static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
5013{
5014 int ret = 0;
5015 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
5016
5017 ret = ufshcd_dme_peer_get(hba,
5018 UIC_ARG_MIB_SEL(
5019 RX_MIN_ACTIVATETIME_CAPABILITY,
5020 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5021 &peer_rx_min_activatetime);
5022 if (ret)
5023 goto out;
5024
5025 /* make sure proper unit conversion is applied */
5026 tuned_pa_tactivate =
5027 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
5028 / PA_TACTIVATE_TIME_UNIT_US);
5029 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5030 tuned_pa_tactivate);
5031
5032out:
5033 return ret;
5034}
5035
5036/**
5037 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
5038 * @hba: per-adapter instance
5039 *
5040 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
5041 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
5042 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
5043 * This optimal value can help reduce the hibern8 exit latency.
5044 *
5045 * Returns zero on success, non-zero error value on failure.
5046 */
5047static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
5048{
5049 int ret = 0;
5050 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
5051 u32 max_hibern8_time, tuned_pa_hibern8time;
5052
5053 ret = ufshcd_dme_get(hba,
5054 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
5055 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
5056 &local_tx_hibern8_time_cap);
5057 if (ret)
5058 goto out;
5059
5060 ret = ufshcd_dme_peer_get(hba,
5061 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
5062 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5063 &peer_rx_hibern8_time_cap);
5064 if (ret)
5065 goto out;
5066
5067 max_hibern8_time = max(local_tx_hibern8_time_cap,
5068 peer_rx_hibern8_time_cap);
5069 /* make sure proper unit conversion is applied */
5070 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
5071 / PA_HIBERN8_TIME_UNIT_US);
5072 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
5073 tuned_pa_hibern8time);
5074out:
5075 return ret;
5076}
5077
5078static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
5079{
5080 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
5081 ufshcd_tune_pa_tactivate(hba);
5082 ufshcd_tune_pa_hibern8time(hba);
5083 }
5084
5085 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
5086 /* set 1ms timeout for PA_TACTIVATE */
5087 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
5088}
5089
6ccf44fe 5090/**
1d337ec2
SRT		 5091 * ufshcd_probe_hba - probe hba to detect device and initialize
5092 * @hba: per-adapter instance
5093 *
5094 * Execute link-startup and verify device initialization
6ccf44fe 5095 */
1d337ec2 5096static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 5097{
6ccf44fe
SJ		 5098 int ret;
5099
5100 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 5101 if (ret)
5102 goto out;
5103
5064636c
YG		 5104 ufshcd_init_pwr_info(hba);
5105
afdfff59
YG		 5106 /* set the default level for urgent bkops */
5107 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5108 hba->is_urgent_bkops_lvl_checked = false;
5109
57d104c1
SJ		 5110 /* UniPro link is active now */
5111 ufshcd_set_link_active(hba);
d3e89bac 5112
5a0b0cb9
SRT		 5113 ret = ufshcd_verify_dev_init(hba);
5114 if (ret)
5115 goto out;
68078d5c
DR		 5116
5117 ret = ufshcd_complete_dev_init(hba);
5118 if (ret)
5119 goto out;
5a0b0cb9 5120
c58ab7aa 5121 ufs_advertise_fixup_device(hba);
37113106 5122 ufshcd_tune_unipro_params(hba);
60f01870
YG		 5123
5124 ret = ufshcd_set_vccq_rail_unused(hba,
5125 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5126 if (ret)
5127 goto out;
5128
57d104c1
SJ		 5129 /* UFS device is also active now */
5130 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5131 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 5132 hba->wlun_dev_clr_ua = true;
5133
7eb584db
DR		 5134 if (ufshcd_get_max_pwr_mode(hba)) {
5135 dev_err(hba->dev,
5136 "%s: Failed getting max supported power mode\n",
5137 __func__);
5138 } else {
5139 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 5140 if (ret) {
7eb584db
DR		 5141 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5142 __func__, ret);
8643ae66
DL		 5143 goto out;
5144 }
7eb584db 5145 }
57d104c1 5146
53c12d0e
YG		 5147 /* set the state as operational after switching to desired gear */
5148 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 5149 /*
5150 * If we are in error handling context or in power management callbacks
5151 * context, no need to scan the host
5152 */
5153 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5154 bool flag;
5155
5156 /* clear any previous UFS device information */
5157 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 5158 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5159 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5160 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5161
3a4bf06d
YG		 5162 if (!hba->is_init_prefetch)
5163 ufshcd_init_icc_levels(hba);
5164
2a8fa600
SJ		 5165 /* Add required well known logical units to scsi mid layer */
5166 if (ufshcd_scsi_add_wlus(hba))
5167 goto out;
5168
3441da7d
SRT		 5169 scsi_scan_host(hba->host);
5170 pm_runtime_put_sync(hba->dev);
5171 }
3a4bf06d
YG		 5172
5173 if (!hba->is_init_prefetch)
5174 hba->is_init_prefetch = true;
5175
856b3483 5176 /* Resume devfreq after UFS device is detected */
a508253d 5177 ufshcd_resume_clkscaling(hba);
856b3483 5178
5a0b0cb9 5179out:
1d337ec2
SRT		 5180 /*
5181 * If we failed to initialize the device or the device is not
5182 * present, turn off the power/clocks etc.
5183 */
57d104c1
SJ		 5184 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5185 pm_runtime_put_sync(hba->dev);
1d337ec2 5186 ufshcd_hba_exit(hba);
57d104c1 5187 }
1d337ec2
SRT		 5188
5189 return ret;
5190}
5191
5192/**
5193 * ufshcd_async_scan - asynchronous execution for probing hba
5194 * @data: data pointer to pass to this function
5195 * @cookie: cookie data
5196 */
5197static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5198{
5199 struct ufs_hba *hba = (struct ufs_hba *)data;
5200
5201 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 5202}
5203
f550c65b
YG		 5204static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5205{
5206 unsigned long flags;
5207 struct Scsi_Host *host;
5208 struct ufs_hba *hba;
5209 int index;
5210 bool found = false;
5211
5212 if (!scmd || !scmd->device || !scmd->device->host)
5213 return BLK_EH_NOT_HANDLED;
5214
5215 host = scmd->device->host;
5216 hba = shost_priv(host);
5217 if (!hba)
5218 return BLK_EH_NOT_HANDLED;
5219
5220 spin_lock_irqsave(host->host_lock, flags);
5221
5222 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5223 if (hba->lrb[index].cmd == scmd) {
5224 found = true;
5225 break;
5226 }
5227 }
5228
5229 spin_unlock_irqrestore(host->host_lock, flags);
5230
5231 /*
5232 * Bypass SCSI error handling and reset the block layer timer if this
5233 * SCSI command was not actually dispatched to UFS driver, otherwise
5234 * let SCSI layer handle the error as usual.
5235 */
5236 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5237}
5238
7a3e97b0
SY		 5239static struct scsi_host_template ufshcd_driver_template = {
5240 .module = THIS_MODULE,
5241 .name = UFSHCD,
5242 .proc_name = UFSHCD,
5243 .queuecommand = ufshcd_queuecommand,
5244 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5245 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5246 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5247 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5248 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 5249 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5250 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5251 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 5252 .this_id = -1,
5253 .sg_tablesize = SG_ALL,
5254 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5255 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5256 .max_host_blocked = 1,
c40ecc12 5257 .track_queue_depth = 1,
7a3e97b0
SY		 5258};
5259
57d104c1
SJ		 5260static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5261 int ua)
5262{
7b16a07c 5263 int ret;
57d104c1 5264
7b16a07c
BA		 5265 if (!vreg)
5266 return 0;
57d104c1 5267
7b16a07c
BA		 5268 ret = regulator_set_load(vreg->reg, ua);
5269 if (ret < 0) {
5270 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5271 __func__, vreg->name, ua, ret);
57d104c1
SJ		 5272 }
5273
5274 return ret;
5275}
5276
5277static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5278 struct ufs_vreg *vreg)
5279{
60f01870
YG		 5280 if (!vreg)
5281 return 0;
5282 else if (vreg->unused)
5283 return 0;
5284 else
5285 return ufshcd_config_vreg_load(hba->dev, vreg,
5286 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 5287}
5288
5289static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5290 struct ufs_vreg *vreg)
5291{
60f01870
YG		 5292 if (!vreg)
5293 return 0;
5294 else if (vreg->unused)
5295 return 0;
5296 else
5297 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 5298}
5299
aa497613
SRT		 5300static int ufshcd_config_vreg(struct device *dev,
5301 struct ufs_vreg *vreg, bool on)
5302{
5303 int ret = 0;
5304 struct regulator *reg = vreg->reg;
5305 const char *name = vreg->name;
5306 int min_uV, uA_load;
5307
5308 BUG_ON(!vreg);
5309
5310 if (regulator_count_voltages(reg) > 0) {
5311 min_uV = on ? vreg->min_uV : 0;
5312 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5313 if (ret) {
5314 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5315 __func__, name, ret);
5316 goto out;
5317 }
5318
5319 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 5320 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5321 if (ret)
aa497613 5322 goto out;
aa497613
SRT		 5323 }
5324out:
5325 return ret;
5326}
5327
5328static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5329{
5330 int ret = 0;
5331
60f01870
YG		 5332 if (!vreg)
5333 goto out;
5334 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 5335 goto out;
5336
5337 ret = ufshcd_config_vreg(dev, vreg, true);
5338 if (!ret)
5339 ret = regulator_enable(vreg->reg);
5340
5341 if (!ret)
5342 vreg->enabled = true;
5343 else
5344 dev_err(dev, "%s: %s enable failed, err=%d\n",
5345 __func__, vreg->name, ret);
5346out:
5347 return ret;
5348}
5349
5350static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5351{
5352 int ret = 0;
5353
60f01870
YG		 5354 if (!vreg)
5355 goto out;
5356 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 5357 goto out;
5358
5359 ret = regulator_disable(vreg->reg);
5360
5361 if (!ret) {
5362 /* ignore errors on applying disable config */
5363 ufshcd_config_vreg(dev, vreg, false);
5364 vreg->enabled = false;
5365 } else {
5366 dev_err(dev, "%s: %s disable failed, err=%d\n",
5367 __func__, vreg->name, ret);
5368 }
5369out:
5370 return ret;
5371}
5372
5373static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5374{
5375 int ret = 0;
5376 struct device *dev = hba->dev;
5377 struct ufs_vreg_info *info = &hba->vreg_info;
5378
5379 if (!info)
5380 goto out;
5381
5382 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5383 if (ret)
5384 goto out;
5385
5386 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5387 if (ret)
5388 goto out;
5389
5390 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5391 if (ret)
5392 goto out;
5393
5394out:
5395 if (ret) {
5396 ufshcd_toggle_vreg(dev, info->vccq2, false);
5397 ufshcd_toggle_vreg(dev, info->vccq, false);
5398 ufshcd_toggle_vreg(dev, info->vcc, false);
5399 }
5400 return ret;
5401}
5402
6a771a65
RS		 5403static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5404{
5405 struct ufs_vreg_info *info = &hba->vreg_info;
5406
5407 if (info)
5408 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5409
5410 return 0;
5411}
5412
aa497613
SRT		 5413static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5414{
5415 int ret = 0;
5416
5417 if (!vreg)
5418 goto out;
5419
5420 vreg->reg = devm_regulator_get(dev, vreg->name);
5421 if (IS_ERR(vreg->reg)) {
5422 ret = PTR_ERR(vreg->reg);
5423 dev_err(dev, "%s: %s get failed, err=%d\n",
5424 __func__, vreg->name, ret);
5425 }
5426out:
5427 return ret;
5428}
5429
5430static int ufshcd_init_vreg(struct ufs_hba *hba)
5431{
5432 int ret = 0;
5433 struct device *dev = hba->dev;
5434 struct ufs_vreg_info *info = &hba->vreg_info;
5435
5436 if (!info)
5437 goto out;
5438
5439 ret = ufshcd_get_vreg(dev, info->vcc);
5440 if (ret)
5441 goto out;
5442
5443 ret = ufshcd_get_vreg(dev, info->vccq);
5444 if (ret)
5445 goto out;
5446
5447 ret = ufshcd_get_vreg(dev, info->vccq2);
5448out:
5449 return ret;
5450}
5451
6a771a65
RS		 5452static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5453{
5454 struct ufs_vreg_info *info = &hba->vreg_info;
5455
5456 if (info)
5457 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5458
5459 return 0;
5460}
5461
60f01870
YG		 5462static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5463{
5464 int ret = 0;
5465 struct ufs_vreg_info *info = &hba->vreg_info;
5466
5467 if (!info)
5468 goto out;
5469 else if (!info->vccq)
5470 goto out;
5471
5472 if (unused) {
5473 /* shut off the rail here */
5474 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5475 /*
5476 * Mark this rail as no longer used, so it doesn't get enabled
5477 * later by mistake
5478 */
5479 if (!ret)
5480 info->vccq->unused = true;
5481 } else {
5482 /*
5483 * rail should have been already enabled hence just make sure
5484 * that unused flag is cleared.
5485 */
5486 info->vccq->unused = false;
5487 }
5488out:
5489 return ret;
5490}
5491
57d104c1
SJ		 5492static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5493 bool skip_ref_clk)
c6e79dac
SRT		 5494{
5495 int ret = 0;
5496 struct ufs_clk_info *clki;
5497 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5498 unsigned long flags;
c6e79dac
SRT		 5499
5500 if (!head || list_empty(head))
5501 goto out;
5502
1e879e8f
SJ		 5503 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
5504 if (ret)
5505 return ret;
5506
c6e79dac
SRT		 5507 list_for_each_entry(clki, head, list) {
5508 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 5509 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5510 continue;
5511
c6e79dac
SRT		 5512 if (on && !clki->enabled) {
5513 ret = clk_prepare_enable(clki->clk);
5514 if (ret) {
5515 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5516 __func__, clki->name, ret);
5517 goto out;
5518 }
5519 } else if (!on && clki->enabled) {
5520 clk_disable_unprepare(clki->clk);
5521 }
5522 clki->enabled = on;
5523 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5524 clki->name, on ? "en" : "dis");
5525 }
5526 }
1ab27c9c 5527
1e879e8f
SJ		 5528 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
5529 if (ret)
5530 return ret;
5531
c6e79dac
SRT		 5532out:
5533 if (ret) {
5534 list_for_each_entry(clki, head, list) {
5535 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5536 clk_disable_unprepare(clki->clk);
5537 }
eda910e4 5538 } else if (on) {
1ab27c9c
ST		 5539 spin_lock_irqsave(hba->host->host_lock, flags);
5540 hba->clk_gating.state = CLKS_ON;
5541 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 5542 }
5543 return ret;
5544}
5545
57d104c1
SJ		 5546static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
5547{
5548 return __ufshcd_setup_clocks(hba, on, false);
5549}
5550
c6e79dac
SRT		 5551static int ufshcd_init_clocks(struct ufs_hba *hba)
5552{
5553 int ret = 0;
5554 struct ufs_clk_info *clki;
5555 struct device *dev = hba->dev;
5556 struct list_head *head = &hba->clk_list_head;
5557
5558 if (!head || list_empty(head))
5559 goto out;
5560
5561 list_for_each_entry(clki, head, list) {
5562 if (!clki->name)
5563 continue;
5564
5565 clki->clk = devm_clk_get(dev, clki->name);
5566 if (IS_ERR(clki->clk)) {
5567 ret = PTR_ERR(clki->clk);
5568 dev_err(dev, "%s: %s clk get failed, %d\n",
5569 __func__, clki->name, ret);
5570 goto out;
5571 }
5572
5573 if (clki->max_freq) {
5574 ret = clk_set_rate(clki->clk, clki->max_freq);
5575 if (ret) {
5576 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5577 __func__, clki->name,
5578 clki->max_freq, ret);
5579 goto out;
5580 }
856b3483 5581 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 5582 }
5583 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
5584 clki->name, clk_get_rate(clki->clk));
5585 }
5586out:
5587 return ret;
5588}
5589
5c0c28a8
SRT		 5590static int ufshcd_variant_hba_init(struct ufs_hba *hba)
5591{
5592 int err = 0;
5593
5594 if (!hba->vops)
5595 goto out;
5596
0263bcd0
YG		 5597 err = ufshcd_vops_init(hba);
5598 if (err)
5599 goto out;
5c0c28a8 5600
0263bcd0
YG		 5601 err = ufshcd_vops_setup_regulators(hba, true);
5602 if (err)
5603 goto out_exit;
5c0c28a8
SRT		 5604
5605 goto out;
5606
5c0c28a8 5607out_exit:
0263bcd0 5608 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5609out:
5610 if (err)
5611 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 5612 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 5613 return err;
5614}
5615
5616static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
5617{
5618 if (!hba->vops)
5619 return;
5620
0263bcd0 5621 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 5622
0263bcd0 5623 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5624}
5625
aa497613
SRT		 5626static int ufshcd_hba_init(struct ufs_hba *hba)
5627{
5628 int err;
5629
6a771a65
RS		 5630 /*
5631 * Handle host controller power separately from the UFS device power
5632 * rails as it will help controlling the UFS host controller power
5633 * collapse easily which is different than UFS device power collapse.
5634 * Also, enable the host controller power before we go ahead with rest
5635 * of the initialization here.
5636 */
5637 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 5638 if (err)
5639 goto out;
5640
6a771a65 5641 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 5642 if (err)
5643 goto out;
5644
6a771a65
RS		 5645 err = ufshcd_init_clocks(hba);
5646 if (err)
5647 goto out_disable_hba_vreg;
5648
5649 err = ufshcd_setup_clocks(hba, true);
5650 if (err)
5651 goto out_disable_hba_vreg;
5652
c6e79dac
SRT		 5653 err = ufshcd_init_vreg(hba);
5654 if (err)
5655 goto out_disable_clks;
5656
5657 err = ufshcd_setup_vreg(hba, true);
5658 if (err)
5659 goto out_disable_clks;
5660
aa497613
SRT		 5661 err = ufshcd_variant_hba_init(hba);
5662 if (err)
5663 goto out_disable_vreg;
5664
1d337ec2 5665 hba->is_powered = true;
aa497613
SRT		 5666 goto out;
5667
5668out_disable_vreg:
5669 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 5670out_disable_clks:
5671 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 5672out_disable_hba_vreg:
5673 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 5674out:
5675 return err;
5676}
5677
5678static void ufshcd_hba_exit(struct ufs_hba *hba)
5679{
1d337ec2
SRT		 5680 if (hba->is_powered) {
5681 ufshcd_variant_hba_exit(hba);
5682 ufshcd_setup_vreg(hba, false);
a508253d 5683 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 5684 ufshcd_setup_clocks(hba, false);
5685 ufshcd_setup_hba_vreg(hba, false);
5686 hba->is_powered = false;
5687 }
aa497613
SRT		 5688}
5689
57d104c1
SJ		 5690static int
5691ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
5692{
5693 unsigned char cmd[6] = {REQUEST_SENSE,
5694 0,
5695 0,
5696 0,
dcea0bfb 5697 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 5698 0};
5699 char *buffer;
5700 int ret;
5701
dcea0bfb 5702 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 5703 if (!buffer) {
5704 ret = -ENOMEM;
5705 goto out;
5706 }
5707
5708 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 5709 UFSHCD_REQ_SENSE_SIZE, NULL,
57d104c1
SJ		 5710 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
5711 if (ret)
5712 pr_err("%s: failed with err %d\n", __func__, ret);
5713
5714 kfree(buffer);
5715out:
5716 return ret;
5717}
5718
5719/**
5720 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
5721 * power mode
5722 * @hba: per adapter instance
5723 * @pwr_mode: device power mode to set
5724 *
5725 * Returns 0 if requested power mode is set successfully
5726 * Returns non-zero if failed to set the requested power mode
5727 */
5728static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
5729 enum ufs_dev_pwr_mode pwr_mode)
5730{
5731 unsigned char cmd[6] = { START_STOP };
5732 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 5733 struct scsi_device *sdp;
5734 unsigned long flags;
57d104c1
SJ		 5735 int ret;
5736
7c48bfd0
AM		 5737 spin_lock_irqsave(hba->host->host_lock, flags);
5738 sdp = hba->sdev_ufs_device;
5739 if (sdp) {
5740 ret = scsi_device_get(sdp);
5741 if (!ret && !scsi_device_online(sdp)) {
5742 ret = -ENODEV;
5743 scsi_device_put(sdp);
5744 }
5745 } else {
5746 ret = -ENODEV;
5747 }
5748 spin_unlock_irqrestore(hba->host->host_lock, flags);
5749
5750 if (ret)
5751 return ret;
57d104c1
SJ		 5752
5753 /*
5754 * If scsi commands fail, the scsi mid-layer schedules scsi error-
5755 * handling, which would wait for host to be resumed. Since we know
5756 * we are functional while we are here, skip host resume in error
5757 * handling context.
5758 */
5759 hba->host->eh_noresume = 1;
5760 if (hba->wlun_dev_clr_ua) {
5761 ret = ufshcd_send_request_sense(hba, sdp);
5762 if (ret)
5763 goto out;
5764 /* Unit attention condition is cleared now */
5765 hba->wlun_dev_clr_ua = false;
5766 }
5767
5768 cmd[4] = pwr_mode << 4;
5769
5770 /*
5771 * Current function would be generally called from the power management
5772 * callbacks hence set the REQ_PM flag so that it doesn't resume the
5773 * already suspended childs.
5774 */
5775 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
5776 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
5777 if (ret) {
5778 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 5779 "START_STOP failed for power mode: %d, result %x\n",
5780 pwr_mode, ret);
21045519
HR		 5781 if (driver_byte(ret) & DRIVER_SENSE)
5782 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 5783 }
5784
5785 if (!ret)
5786 hba->curr_dev_pwr_mode = pwr_mode;
5787out:
7c48bfd0 5788 scsi_device_put(sdp);
57d104c1
SJ		 5789 hba->host->eh_noresume = 0;
5790 return ret;
5791}
5792
5793static int ufshcd_link_state_transition(struct ufs_hba *hba,
5794 enum uic_link_state req_link_state,
5795 int check_for_bkops)
5796{
5797 int ret = 0;
5798
5799 if (req_link_state == hba->uic_link_state)
5800 return 0;
5801
5802 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5803 ret = ufshcd_uic_hibern8_enter(hba);
5804 if (!ret)
5805 ufshcd_set_link_hibern8(hba);
5806 else
5807 goto out;
5808 }
5809 /*
5810 * If autobkops is enabled, link can't be turned off because
5811 * turning off the link would also turn off the device.
5812 */
5813 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
5814 (!check_for_bkops || (check_for_bkops &&
5815 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 5816 /*
5817 * Let's make sure that link is in low power mode, we are doing
5818 * this currently by putting the link in Hibern8. Otherway to
5819 * put the link in low power mode is to send the DME end point
5820 * to device and then send the DME reset command to local
5821 * unipro. But putting the link in hibern8 is much faster.
5822 */
5823 ret = ufshcd_uic_hibern8_enter(hba);
5824 if (ret)
5825 goto out;
57d104c1
SJ		 5826 /*
5827 * Change controller state to "reset state" which
5828 * should also put the link in off/reset state
5829 */
596585a2 5830 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 5831 /*
5832 * TODO: Check if we need any delay to make sure that
5833 * controller is reset
5834 */
5835 ufshcd_set_link_off(hba);
5836 }
5837
5838out:
5839 return ret;
5840}
5841
5842static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
5843{
b799fdf7
YG		 5844 /*
5845 * It seems some UFS devices may keep drawing more than sleep current
5846 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
5847 * To avoid this situation, add 2ms delay before putting these UFS
5848 * rails in LPM mode.
5849 */
5850 if (!ufshcd_is_link_active(hba) &&
5851 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
5852 usleep_range(2000, 2100);
5853
57d104c1
SJ		 5854 /*
5855 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
5856 * power.
5857 *
5858 * If UFS device and link is in OFF state, all power supplies (VCC,
5859 * VCCQ, VCCQ2) can be turned off if power on write protect is not
5860 * required. If UFS link is inactive (Hibern8 or OFF state) and device
5861 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
5862 *
5863 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
5864 * in low power state which would save some power.
5865 */
5866 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5867 !hba->dev_info.is_lu_power_on_wp) {
5868 ufshcd_setup_vreg(hba, false);
5869 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5870 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5871 if (!ufshcd_is_link_active(hba)) {
5872 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5873 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
5874 }
5875 }
5876}
5877
5878static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
5879{
5880 int ret = 0;
5881
5882 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5883 !hba->dev_info.is_lu_power_on_wp) {
5884 ret = ufshcd_setup_vreg(hba, true);
5885 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 5886 if (!ret && !ufshcd_is_link_active(hba)) {
5887 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5888 if (ret)
5889 goto vcc_disable;
5890 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5891 if (ret)
5892 goto vccq_lpm;
5893 }
69d72ac8 5894 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 5895 }
5896 goto out;
5897
5898vccq_lpm:
5899 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5900vcc_disable:
5901 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5902out:
5903 return ret;
5904}
5905
5906static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
5907{
5908 if (ufshcd_is_link_off(hba))
5909 ufshcd_setup_hba_vreg(hba, false);
5910}
5911
5912static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
5913{
5914 if (ufshcd_is_link_off(hba))
5915 ufshcd_setup_hba_vreg(hba, true);
5916}
5917
7a3e97b0 5918/**
57d104c1 5919 * ufshcd_suspend - helper function for suspend operations
3b1d0580 5920 * @hba: per adapter instance
57d104c1
SJ		 5921 * @pm_op: desired low power operation type
5922 *
5923 * This function will try to put the UFS device and link into low power
5924 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
5925 * (System PM level).
5926 *
5927 * If this function is called during shutdown, it will make sure that
5928 * both UFS device and UFS link is powered off.
7a3e97b0 5929 *
57d104c1
SJ		 5930 * NOTE: UFS device & link must be active before we enter in this function.
5931 *
5932 * Returns 0 for success and non-zero for failure
7a3e97b0 5933 */
57d104c1 5934static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5935{
57d104c1
SJ		 5936 int ret = 0;
5937 enum ufs_pm_level pm_lvl;
5938 enum ufs_dev_pwr_mode req_dev_pwr_mode;
5939 enum uic_link_state req_link_state;
5940
5941 hba->pm_op_in_progress = 1;
5942 if (!ufshcd_is_shutdown_pm(pm_op)) {
5943 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
5944 hba->rpm_lvl : hba->spm_lvl;
5945 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
5946 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
5947 } else {
5948 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
5949 req_link_state = UIC_LINK_OFF_STATE;
5950 }
5951
7a3e97b0 5952 /*
57d104c1
SJ		 5953 * If we can't transition into any of the low power modes
5954 * just gate the clocks.
7a3e97b0 5955 */
1ab27c9c
ST		 5956 ufshcd_hold(hba, false);
5957 hba->clk_gating.is_suspended = true;
5958
d6fcf81a
SJ		 5959 ufshcd_suspend_clkscaling(hba);
5960
57d104c1
SJ		 5961 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
5962 req_link_state == UIC_LINK_ACTIVE_STATE) {
5963 goto disable_clks;
5964 }
7a3e97b0 5965
57d104c1
SJ		 5966 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
5967 (req_link_state == hba->uic_link_state))
d6fcf81a 5968 goto enable_gating;
57d104c1
SJ		 5969
5970 /* UFS device & link must be active before we enter in this function */
5971 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
5972 ret = -EINVAL;
d6fcf81a 5973 goto enable_gating;
57d104c1
SJ		 5974 }
5975
5976 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 5977 if (ufshcd_can_autobkops_during_suspend(hba)) {
5978 /*
5979 * The device is idle with no requests in the queue,
5980 * allow background operations if bkops status shows
5981 * that performance might be impacted.
5982 */
5983 ret = ufshcd_urgent_bkops(hba);
5984 if (ret)
5985 goto enable_gating;
5986 } else {
5987 /* make sure that auto bkops is disabled */
5988 ufshcd_disable_auto_bkops(hba);
5989 }
57d104c1
SJ		 5990 }
5991
5992 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
5993 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
5994 !ufshcd_is_runtime_pm(pm_op))) {
5995 /* ensure that bkops is disabled */
5996 ufshcd_disable_auto_bkops(hba);
5997 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
5998 if (ret)
1ab27c9c 5999 goto enable_gating;
57d104c1
SJ		 6000 }
6001
6002 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
6003 if (ret)
6004 goto set_dev_active;
6005
6006 ufshcd_vreg_set_lpm(hba);
6007
6008disable_clks:
6009 /*
6010 * Call vendor specific suspend callback. As these callbacks may access
6011 * vendor specific host controller register space call them before the
6012 * host clocks are ON.
6013 */
0263bcd0
YG		 6014 ret = ufshcd_vops_suspend(hba, pm_op);
6015 if (ret)
6016 goto set_link_active;
57d104c1 6017
57d104c1
SJ		 6018 if (!ufshcd_is_link_active(hba))
6019 ufshcd_setup_clocks(hba, false);
6020 else
6021 /* If link is active, device ref_clk can't be switched off */
6022 __ufshcd_setup_clocks(hba, false, true);
6023
1ab27c9c 6024 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 6025 /*
6026 * Disable the host irq as host controller as there won't be any
0263bcd0 6027 * host controller transaction expected till resume.
57d104c1
SJ		 6028 */
6029 ufshcd_disable_irq(hba);
6030 /* Put the host controller in low power mode if possible */
6031 ufshcd_hba_vreg_set_lpm(hba);
6032 goto out;
6033
57d104c1 6034set_link_active:
a508253d 6035 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 6036 ufshcd_vreg_set_hpm(hba);
6037 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
6038 ufshcd_set_link_active(hba);
6039 else if (ufshcd_is_link_off(hba))
6040 ufshcd_host_reset_and_restore(hba);
6041set_dev_active:
6042 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
6043 ufshcd_disable_auto_bkops(hba);
1ab27c9c 6044enable_gating:
d6fcf81a 6045 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 6046 hba->clk_gating.is_suspended = false;
6047 ufshcd_release(hba);
57d104c1
SJ		 6048out:
6049 hba->pm_op_in_progress = 0;
6050 return ret;
7a3e97b0
SY		 6051}
6052
6053/**
57d104c1 6054 * ufshcd_resume - helper function for resume operations
3b1d0580 6055 * @hba: per adapter instance
57d104c1 6056 * @pm_op: runtime PM or system PM
7a3e97b0 6057 *
57d104c1
SJ		 6058 * This function basically brings the UFS device, UniPro link and controller
6059 * to active state.
6060 *
6061 * Returns 0 for success and non-zero for failure
7a3e97b0 6062 */
57d104c1 6063static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6064{
57d104c1
SJ		 6065 int ret;
6066 enum uic_link_state old_link_state;
6067
6068 hba->pm_op_in_progress = 1;
6069 old_link_state = hba->uic_link_state;
6070
6071 ufshcd_hba_vreg_set_hpm(hba);
6072 /* Make sure clocks are enabled before accessing controller */
6073 ret = ufshcd_setup_clocks(hba, true);
6074 if (ret)
6075 goto out;
6076
57d104c1
SJ		 6077 /* enable the host irq as host controller would be active soon */
6078 ret = ufshcd_enable_irq(hba);
6079 if (ret)
6080 goto disable_irq_and_vops_clks;
6081
6082 ret = ufshcd_vreg_set_hpm(hba);
6083 if (ret)
6084 goto disable_irq_and_vops_clks;
6085
7a3e97b0 6086 /*
57d104c1
SJ		 6087 * Call vendor specific resume callback. As these callbacks may access
6088 * vendor specific host controller register space call them when the
6089 * host clocks are ON.
7a3e97b0 6090 */
0263bcd0
YG		 6091 ret = ufshcd_vops_resume(hba, pm_op);
6092 if (ret)
6093 goto disable_vreg;
57d104c1
SJ		 6094
6095 if (ufshcd_is_link_hibern8(hba)) {
6096 ret = ufshcd_uic_hibern8_exit(hba);
6097 if (!ret)
6098 ufshcd_set_link_active(hba);
6099 else
6100 goto vendor_suspend;
6101 } else if (ufshcd_is_link_off(hba)) {
6102 ret = ufshcd_host_reset_and_restore(hba);
6103 /*
6104 * ufshcd_host_reset_and_restore() should have already
6105 * set the link state as active
6106 */
6107 if (ret || !ufshcd_is_link_active(hba))
6108 goto vendor_suspend;
6109 }
6110
6111 if (!ufshcd_is_ufs_dev_active(hba)) {
6112 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6113 if (ret)
6114 goto set_old_link_state;
6115 }
6116
374a246e
SJ		 6117 /*
6118 * If BKOPs operations are urgently needed at this moment then
6119 * keep auto-bkops enabled or else disable it.
6120 */
6121 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 6122 hba->clk_gating.is_suspended = false;
6123
a508253d 6124 ufshcd_resume_clkscaling(hba);
856b3483 6125
1ab27c9c
ST		 6126 /* Schedule clock gating in case of no access to UFS device yet */
6127 ufshcd_release(hba);
57d104c1
SJ		 6128 goto out;
6129
6130set_old_link_state:
6131 ufshcd_link_state_transition(hba, old_link_state, 0);
6132vendor_suspend:
0263bcd0 6133 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 6134disable_vreg:
6135 ufshcd_vreg_set_lpm(hba);
6136disable_irq_and_vops_clks:
6137 ufshcd_disable_irq(hba);
a508253d 6138 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 6139 ufshcd_setup_clocks(hba, false);
6140out:
6141 hba->pm_op_in_progress = 0;
6142 return ret;
6143}
6144
6145/**
6146 * ufshcd_system_suspend - system suspend routine
6147 * @hba: per adapter instance
6148 * @pm_op: runtime PM or system PM
6149 *
6150 * Check the description of ufshcd_suspend() function for more details.
6151 *
6152 * Returns 0 for success and non-zero for failure
6153 */
6154int ufshcd_system_suspend(struct ufs_hba *hba)
6155{
6156 int ret = 0;
6157
6158 if (!hba || !hba->is_powered)
233b594b 6159 return 0;
57d104c1
SJ		 6160
6161 if (pm_runtime_suspended(hba->dev)) {
6162 if (hba->rpm_lvl == hba->spm_lvl)
6163 /*
6164 * There is possibility that device may still be in
6165 * active state during the runtime suspend.
6166 */
6167 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6168 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
6169 goto out;
6170
6171 /*
6172 * UFS device and/or UFS link low power states during runtime
6173 * suspend seems to be different than what is expected during
6174 * system suspend. Hence runtime resume the devic & link and
6175 * let the system suspend low power states to take effect.
6176 * TODO: If resume takes longer time, we might have optimize
6177 * it in future by not resuming everything if possible.
6178 */
6179 ret = ufshcd_runtime_resume(hba);
6180 if (ret)
6181 goto out;
6182 }
6183
6184 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6185out:
e785060e
DR		 6186 if (!ret)
6187 hba->is_sys_suspended = true;
57d104c1
SJ		 6188 return ret;
6189}
6190EXPORT_SYMBOL(ufshcd_system_suspend);
6191
6192/**
6193 * ufshcd_system_resume - system resume routine
6194 * @hba: per adapter instance
6195 *
6196 * Returns 0 for success and non-zero for failure
6197 */
7a3e97b0 6198
57d104c1
SJ		 6199int ufshcd_system_resume(struct ufs_hba *hba)
6200{
e3ce73d6
YG		 6201 if (!hba)
6202 return -EINVAL;
6203
6204 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 6205 /*
6206 * Let the runtime resume take care of resuming
6207 * if runtime suspended.
6208 */
6209 return 0;
6210
6211 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 6212}
57d104c1 6213EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6214
57d104c1
SJ		 6215/**
6216 * ufshcd_runtime_suspend - runtime suspend routine
6217 * @hba: per adapter instance
6218 *
6219 * Check the description of ufshcd_suspend() function for more details.
6220 *
6221 * Returns 0 for success and non-zero for failure
6222 */
66ec6d59
SRT		 6223int ufshcd_runtime_suspend(struct ufs_hba *hba)
6224{
e3ce73d6
YG		 6225 if (!hba)
6226 return -EINVAL;
6227
6228 if (!hba->is_powered)
66ec6d59
SRT		 6229 return 0;
6230
57d104c1 6231 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6232}
6233EXPORT_SYMBOL(ufshcd_runtime_suspend);
6234
57d104c1
SJ		 6235/**
6236 * ufshcd_runtime_resume - runtime resume routine
6237 * @hba: per adapter instance
6238 *
6239 * This function basically brings the UFS device, UniPro link and controller
6240 * to active state. Following operations are done in this function:
6241 *
6242 * 1. Turn on all the controller related clocks
6243 * 2. Bring the UniPro link out of Hibernate state
6244 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6245 * to active state.
6246 * 4. If auto-bkops is enabled on the device, disable it.
6247 *
6248 * So following would be the possible power state after this function return
6249 * successfully:
6250 * S1: UFS device in Active state with VCC rail ON
6251 * UniPro link in Active state
6252 * All the UFS/UniPro controller clocks are ON
6253 *
6254 * Returns 0 for success and non-zero for failure
6255 */
66ec6d59
SRT		 6256int ufshcd_runtime_resume(struct ufs_hba *hba)
6257{
e3ce73d6
YG		 6258 if (!hba)
6259 return -EINVAL;
6260
6261 if (!hba->is_powered)
66ec6d59 6262 return 0;
e3ce73d6
YG		 6263
6264 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6265}
6266EXPORT_SYMBOL(ufshcd_runtime_resume);
6267
6268int ufshcd_runtime_idle(struct ufs_hba *hba)
6269{
6270 return 0;
6271}
6272EXPORT_SYMBOL(ufshcd_runtime_idle);
6273
57d104c1
SJ		 6274/**
6275 * ufshcd_shutdown - shutdown routine
6276 * @hba: per adapter instance
6277 *
6278 * This function would power off both UFS device and UFS link.
6279 *
6280 * Returns 0 always to allow force shutdown even in case of errors.
6281 */
6282int ufshcd_shutdown(struct ufs_hba *hba)
6283{
6284 int ret = 0;
6285
6286 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6287 goto out;
6288
6289 if (pm_runtime_suspended(hba->dev)) {
6290 ret = ufshcd_runtime_resume(hba);
6291 if (ret)
6292 goto out;
6293 }
6294
6295 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6296out:
6297 if (ret)
6298 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6299 /* allow force shutdown even in case of errors */
6300 return 0;
6301}
6302EXPORT_SYMBOL(ufshcd_shutdown);
6303
7a3e97b0 6304/**
3b1d0580 6305 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6306 * data structure memory
3b1d0580 6307 * @hba - per adapter instance
7a3e97b0 6308 */
3b1d0580 6309void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6310{
cfdf9c91 6311 scsi_remove_host(hba->host);
7a3e97b0 6312 /* disable interrupts */
2fbd009b 6313 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6314 ufshcd_hba_stop(hba, true);
7a3e97b0 6315
1ab27c9c 6316 ufshcd_exit_clk_gating(hba);
aa497613 6317 ufshcd_hba_exit(hba);
3b1d0580
VH		 6318}
6319EXPORT_SYMBOL_GPL(ufshcd_remove);
6320
47555a5c
YG		 6321/**
6322 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6323 * @hba: pointer to Host Bus Adapter (HBA)
6324 */
6325void ufshcd_dealloc_host(struct ufs_hba *hba)
6326{
6327 scsi_host_put(hba->host);
6328}
6329EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6330
ca3d7bf9
AM		 6331/**
6332 * ufshcd_set_dma_mask - Set dma mask based on the controller
6333 * addressing capability
6334 * @hba: per adapter instance
6335 *
6336 * Returns 0 for success, non-zero for failure
6337 */
6338static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6339{
6340 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6341 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6342 return 0;
6343 }
6344 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6345}
6346
7a3e97b0 6347/**
5c0c28a8 6348 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 6349 * @dev: pointer to device handle
6350 * @hba_handle: driver private handle
7a3e97b0
SY		 6351 * Returns 0 on success, non-zero value on failure
6352 */
5c0c28a8 6353int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 6354{
6355 struct Scsi_Host *host;
6356 struct ufs_hba *hba;
5c0c28a8 6357 int err = 0;
7a3e97b0 6358
3b1d0580
VH		 6359 if (!dev) {
6360 dev_err(dev,
6361 "Invalid memory reference for dev is NULL\n");
6362 err = -ENODEV;
7a3e97b0
SY		 6363 goto out_error;
6364 }
6365
7a3e97b0
SY		 6366 host = scsi_host_alloc(&ufshcd_driver_template,
6367 sizeof(struct ufs_hba));
6368 if (!host) {
3b1d0580 6369 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6370 err = -ENOMEM;
3b1d0580 6371 goto out_error;
7a3e97b0
SY		 6372 }
6373 hba = shost_priv(host);
7a3e97b0 6374 hba->host = host;
3b1d0580 6375 hba->dev = dev;
5c0c28a8
SRT		 6376 *hba_handle = hba;
6377
6378out_error:
6379 return err;
6380}
6381EXPORT_SYMBOL(ufshcd_alloc_host);
6382
856b3483
ST		 6383static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6384{
6385 int ret = 0;
6386 struct ufs_clk_info *clki;
6387 struct list_head *head = &hba->clk_list_head;
6388
6389 if (!head || list_empty(head))
6390 goto out;
6391
f06fcc71
YG		 6392 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
6393 if (ret)
6394 return ret;
6395
856b3483
ST		 6396 list_for_each_entry(clki, head, list) {
6397 if (!IS_ERR_OR_NULL(clki->clk)) {
6398 if (scale_up && clki->max_freq) {
6399 if (clki->curr_freq == clki->max_freq)
6400 continue;
6401 ret = clk_set_rate(clki->clk, clki->max_freq);
6402 if (ret) {
6403 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6404 __func__, clki->name,
6405 clki->max_freq, ret);
6406 break;
6407 }
6408 clki->curr_freq = clki->max_freq;
6409
6410 } else if (!scale_up && clki->min_freq) {
6411 if (clki->curr_freq == clki->min_freq)
6412 continue;
6413 ret = clk_set_rate(clki->clk, clki->min_freq);
6414 if (ret) {
6415 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6416 __func__, clki->name,
6417 clki->min_freq, ret);
6418 break;
6419 }
6420 clki->curr_freq = clki->min_freq;
6421 }
6422 }
6423 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
6424 clki->name, clk_get_rate(clki->clk));
6425 }
f06fcc71
YG		 6426
6427 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
6428
856b3483
ST		 6429out:
6430 return ret;
6431}
6432
6433static int ufshcd_devfreq_target(struct device *dev,
6434 unsigned long *freq, u32 flags)
6435{
6436 int err = 0;
6437 struct ufs_hba *hba = dev_get_drvdata(dev);
30fc33f1
SJ		 6438 bool release_clk_hold = false;
6439 unsigned long irq_flags;
856b3483
ST		 6440
6441 if (!ufshcd_is_clkscaling_enabled(hba))
6442 return -EINVAL;
6443
30fc33f1
SJ		 6444 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6445 if (ufshcd_eh_in_progress(hba)) {
6446 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6447 return 0;
6448 }
6449
6450 if (ufshcd_is_clkgating_allowed(hba) &&
6451 (hba->clk_gating.state != CLKS_ON)) {
6452 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
6453 /* hold the vote until the scaling work is completed */
6454 hba->clk_gating.active_reqs++;
6455 release_clk_hold = true;
6456 hba->clk_gating.state = CLKS_ON;
6457 } else {
6458 /*
6459 * Clock gating work seems to be running in parallel
6460 * hence skip scaling work to avoid deadlock between
6461 * current scaling work and gating work.
6462 */
6463 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6464 return 0;
6465 }
6466 }
6467 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6468
856b3483
ST		 6469 if (*freq == UINT_MAX)
6470 err = ufshcd_scale_clks(hba, true);
6471 else if (*freq == 0)
6472 err = ufshcd_scale_clks(hba, false);
6473
30fc33f1
SJ		 6474 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6475 if (release_clk_hold)
6476 __ufshcd_release(hba);
6477 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6478
856b3483
ST		 6479 return err;
6480}
6481
6482static int ufshcd_devfreq_get_dev_status(struct device *dev,
6483 struct devfreq_dev_status *stat)
6484{
6485 struct ufs_hba *hba = dev_get_drvdata(dev);
6486 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
6487 unsigned long flags;
6488
6489 if (!ufshcd_is_clkscaling_enabled(hba))
6490 return -EINVAL;
6491
6492 memset(stat, 0, sizeof(*stat));
6493
6494 spin_lock_irqsave(hba->host->host_lock, flags);
6495 if (!scaling->window_start_t)
6496 goto start_window;
6497
6498 if (scaling->is_busy_started)
6499 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
6500 scaling->busy_start_t));
6501
6502 stat->total_time = jiffies_to_usecs((long)jiffies -
6503 (long)scaling->window_start_t);
6504 stat->busy_time = scaling->tot_busy_t;
6505start_window:
6506 scaling->window_start_t = jiffies;
6507 scaling->tot_busy_t = 0;
6508
6509 if (hba->outstanding_reqs) {
6510 scaling->busy_start_t = ktime_get();
6511 scaling->is_busy_started = true;
6512 } else {
6513 scaling->busy_start_t = ktime_set(0, 0);
6514 scaling->is_busy_started = false;
6515 }
6516 spin_unlock_irqrestore(hba->host->host_lock, flags);
6517 return 0;
6518}
6519
6520static struct devfreq_dev_profile ufs_devfreq_profile = {
6521 .polling_ms = 100,
6522 .target = ufshcd_devfreq_target,
6523 .get_dev_status = ufshcd_devfreq_get_dev_status,
6524};
6525
5c0c28a8
SRT		 6526/**
6527 * ufshcd_init - Driver initialization routine
6528 * @hba: per-adapter instance
6529 * @mmio_base: base register address
6530 * @irq: Interrupt line of device
6531 * Returns 0 on success, non-zero value on failure
6532 */
6533int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
6534{
6535 int err;
6536 struct Scsi_Host *host = hba->host;
6537 struct device *dev = hba->dev;
6538
6539 if (!mmio_base) {
6540 dev_err(hba->dev,
6541 "Invalid memory reference for mmio_base is NULL\n");
6542 err = -ENODEV;
6543 goto out_error;
6544 }
6545
3b1d0580
VH		 6546 hba->mmio_base = mmio_base;
6547 hba->irq = irq;
7a3e97b0 6548
aa497613 6549 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 6550 if (err)
6551 goto out_error;
6552
7a3e97b0
SY		 6553 /* Read capabilities registers */
6554 ufshcd_hba_capabilities(hba);
6555
6556 /* Get UFS version supported by the controller */
6557 hba->ufs_version = ufshcd_get_ufs_version(hba);
6558
2fbd009b
SJ		 6559 /* Get Interrupt bit mask per version */
6560 hba->intr_mask = ufshcd_get_intr_mask(hba);
6561
ca3d7bf9
AM		 6562 err = ufshcd_set_dma_mask(hba);
6563 if (err) {
6564 dev_err(hba->dev, "set dma mask failed\n");
6565 goto out_disable;
6566 }
6567
7a3e97b0
SY		 6568 /* Allocate memory for host memory space */
6569 err = ufshcd_memory_alloc(hba);
6570 if (err) {
3b1d0580
VH		 6571 dev_err(hba->dev, "Memory allocation failed\n");
6572 goto out_disable;
7a3e97b0
SY		 6573 }
6574
6575 /* Configure LRB */
6576 ufshcd_host_memory_configure(hba);
6577
6578 host->can_queue = hba->nutrs;
6579 host->cmd_per_lun = hba->nutrs;
6580 host->max_id = UFSHCD_MAX_ID;
0ce147d4 6581 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 6582 host->max_channel = UFSHCD_MAX_CHANNEL;
6583 host->unique_id = host->host_no;
6584 host->max_cmd_len = MAX_CDB_SIZE;
6585
7eb584db
DR		 6586 hba->max_pwr_info.is_valid = false;
6587
7a3e97b0 6588 /* Initailize wait queue for task management */
e2933132
SRT		 6589 init_waitqueue_head(&hba->tm_wq);
6590 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 6591
6592 /* Initialize work queues */
e8e7f271 6593 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 6594 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 6595
6ccf44fe
SJ		 6596 /* Initialize UIC command mutex */
6597 mutex_init(&hba->uic_cmd_mutex);
6598
5a0b0cb9
SRT		 6599 /* Initialize mutex for device management commands */
6600 mutex_init(&hba->dev_cmd.lock);
6601
6602 /* Initialize device management tag acquire wait queue */
6603 init_waitqueue_head(&hba->dev_cmd.tag_wq);
6604
1ab27c9c 6605 ufshcd_init_clk_gating(hba);
199ef13c
YG		 6606
6607 /*
6608 * In order to avoid any spurious interrupt immediately after
6609 * registering UFS controller interrupt handler, clear any pending UFS
6610 * interrupt status and disable all the UFS interrupts.
6611 */
6612 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
6613 REG_INTERRUPT_STATUS);
6614 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
6615 /*
6616 * Make sure that UFS interrupts are disabled and any pending interrupt
6617 * status is cleared before registering UFS interrupt handler.
6618 */
6619 mb();
6620
7a3e97b0 6621 /* IRQ registration */
2953f850 6622 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 6623 if (err) {
3b1d0580 6624 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 6625 goto exit_gating;
57d104c1
SJ		 6626 } else {
6627 hba->is_irq_enabled = true;
7a3e97b0
SY		 6628 }
6629
3b1d0580 6630 err = scsi_add_host(host, hba->dev);
7a3e97b0 6631 if (err) {
3b1d0580 6632 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 6633 goto exit_gating;
7a3e97b0
SY		 6634 }
6635
6ccf44fe
SJ		 6636 /* Host controller enable */
6637 err = ufshcd_hba_enable(hba);
7a3e97b0 6638 if (err) {
6ccf44fe 6639 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 6640 goto out_remove_scsi_host;
7a3e97b0 6641 }
6ccf44fe 6642
856b3483 6643 if (ufshcd_is_clkscaling_enabled(hba)) {
4861ee15 6644 hba->devfreq = devm_devfreq_add_device(dev, &ufs_devfreq_profile,
856b3483
ST		 6645 "simple_ondemand", NULL);
6646 if (IS_ERR(hba->devfreq)) {
6647 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
6648 PTR_ERR(hba->devfreq));
73811c94 6649 err = PTR_ERR(hba->devfreq);
856b3483
ST		 6650 goto out_remove_scsi_host;
6651 }
6652 /* Suspend devfreq until the UFS device is detected */
a508253d 6653 ufshcd_suspend_clkscaling(hba);
856b3483
ST		 6654 }
6655
62694735
SRT		 6656 /* Hold auto suspend until async scan completes */
6657 pm_runtime_get_sync(dev);
6658
57d104c1
SJ		 6659 /*
6660 * The device-initialize-sequence hasn't been invoked yet.
6661 * Set the device to power-off state
6662 */
6663 ufshcd_set_ufs_dev_poweroff(hba);
6664
6ccf44fe
SJ		 6665 async_schedule(ufshcd_async_scan, hba);
6666
7a3e97b0
SY		 6667 return 0;
6668
3b1d0580
VH		 6669out_remove_scsi_host:
6670 scsi_remove_host(hba->host);
1ab27c9c
ST		 6671exit_gating:
6672 ufshcd_exit_clk_gating(hba);
3b1d0580 6673out_disable:
57d104c1 6674 hba->is_irq_enabled = false;
aa497613 6675 ufshcd_hba_exit(hba);
3b1d0580
VH		 6676out_error:
6677 return err;
6678}
6679EXPORT_SYMBOL_GPL(ufshcd_init);
6680
3b1d0580
VH		 6681MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
6682MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 6683MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 6684MODULE_LICENSE("GPL");
6685MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)