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scsi: ufs: Remove superfluous boolean conversions
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
67351119 1// SPDX-License-Identifier: GPL-2.0-or-later
7a3e97b0 2/*
e0eca63e 3 * Universal Flash Storage Host controller driver Core
3b1d0580 4 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 */
11
6ccf44fe 12#include <linux/async.h>
856b3483 13#include <linux/devfreq.h>
b573d484 14#include <linux/nls.h>
54b879b7 15#include <linux/of.h>
ad448378 16#include <linux/bitfield.h>
fb276f77 17#include <linux/blk-pm.h>
c72e79c0 18#include <linux/blkdev.h>
b294ff3e 19#include <scsi/scsi_driver.h>
e0eca63e 20#include "ufshcd.h"
c58ab7aa 21#include "ufs_quirks.h"
53b3d9c3 22#include "unipro.h"
cbb6813e 23#include "ufs-sysfs.h"
b6cacaf2 24#include "ufs-debugfs.h"
c11a1ae9 25#include "ufs-fault-injection.h"
df032bf2 26#include "ufs_bsg.h"
df043c74 27#include "ufshcd-crypto.h"
f02bc975 28#include "ufshpb.h"
3d17b9b5 29#include <asm/unaligned.h>
7a3e97b0 30
7ff5ab47 31#define CREATE_TRACE_POINTS
32#include <trace/events/ufs.h>
33
2fbd009b
SJ		 34#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
35 UTP_TASK_REQ_COMPL |\
36 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 37/* UIC command timeout, unit: ms */
38#define UIC_CMD_TIMEOUT 500
2fbd009b 39
5a0b0cb9
SRT		 40/* NOP OUT retries waiting for NOP IN response */
41#define NOP_OUT_RETRIES 10
782e2efb
DP		 42/* Timeout after 50 msecs if NOP OUT hangs without response */
43#define NOP_OUT_TIMEOUT 50 /* msecs */
5a0b0cb9 44
68078d5c 45/* Query request retries */
10fe5888 46#define QUERY_REQ_RETRIES 3
68078d5c 47/* Query request timeout */
10fe5888 48#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 49
e2933132
SRT		 50/* Task management command timeout */
51#define TM_CMD_TIMEOUT 100 /* msecs */
52
64238fbd
YG		 53/* maximum number of retries for a general UIC command */
54#define UFS_UIC_COMMAND_RETRIES 3
55
1d337ec2
SRT		 56/* maximum number of link-startup retries */
57#define DME_LINKSTARTUP_RETRIES 3
58
87d0b4a6
YG		 59/* Maximum retries for Hibern8 enter */
60#define UIC_HIBERN8_ENTER_RETRIES 3
61
1d337ec2
SRT		 62/* maximum number of reset retries before giving up */
63#define MAX_HOST_RESET_RETRIES 5
64
87bf6a6b
AH		 65/* Maximum number of error handler retries before giving up */
66#define MAX_ERR_HANDLER_RETRIES 5
67
68078d5c
DR		 68/* Expose the flag value from utp_upiu_query.value */
69#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
70
7d568652
SJ		 71/* Interrupt aggregation default timeout, unit: 40us */
72#define INT_AGGR_DEF_TO 0x02
73
49615ba1
SC		 74/* default delay of autosuspend: 2000 ms */
75#define RPM_AUTOSUSPEND_DELAY_MS 2000
76
51dd905b
SC		 77/* Default delay of RPM device flush delayed work */
78#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
79
09f17791
CG		 80/* Default value of wait time before gating device ref clock */
81#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
82
29707fab
KK		 83/* Polling time to wait for fDeviceInit */
84#define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
85
aa497613
SRT		 86#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
87 ({ \
88 int _ret; \
89 if (_on) \
90 _ret = ufshcd_enable_vreg(_dev, _vreg); \
91 else \
92 _ret = ufshcd_disable_vreg(_dev, _vreg); \
93 _ret; \
94 })
95
ba80917d
TW		 96#define ufshcd_hex_dump(prefix_str, buf, len) do { \
97 size_t __len = (len); \
98 print_hex_dump(KERN_ERR, prefix_str, \
99 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
100 16, 4, buf, __len, false); \
101} while (0)
102
103int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
104 const char *prefix)
105{
d6724756
MG		 106 u32 *regs;
107 size_t pos;
108
109 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
110 return -EINVAL;
ba80917d 111
cddaebaf 112 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 113 if (!regs)
114 return -ENOMEM;
115
d6724756
MG		 116 for (pos = 0; pos < len; pos += 4)
117 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
118
ba80917d
TW		 119 ufshcd_hex_dump(prefix, regs, len);
120 kfree(regs);
121
122 return 0;
123}
124EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 125
7a3e97b0
SY		 126enum {
127 UFSHCD_MAX_CHANNEL = 0,
128 UFSHCD_MAX_ID = 1,
945c3cca
BVA		 129 UFSHCD_NUM_RESERVED = 1,
130 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
131 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
7a3e97b0
SY		 132};
133
4693fad7
BVA		 134static const char *const ufshcd_state_name[] = {
135 [UFSHCD_STATE_RESET] = "reset",
136 [UFSHCD_STATE_OPERATIONAL] = "operational",
137 [UFSHCD_STATE_ERROR] = "error",
138 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
139 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
140};
141
3441da7d
SRT		 142/* UFSHCD error handling flags */
143enum {
144 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 145};
146
e8e7f271
SRT		 147/* UFSHCD UIC layer error flags */
148enum {
149 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 150 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
151 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
152 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
153 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
154 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
2355b66e 155 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
e8e7f271
SRT		 156};
157
3441da7d 158#define ufshcd_set_eh_in_progress(h) \
9c490d2d 159 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 160#define ufshcd_eh_in_progress(h) \
9c490d2d 161 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 162#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 163 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 164
cbb6813e 165struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
e2ac7ab2
BVA		 166 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
167 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
168 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
169 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
170 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
171 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
fe1d4c2e
AH		 172 /*
173 * For DeepSleep, the link is first put in hibern8 and then off.
174 * Leaving the link in hibern8 is not supported.
175 */
e2ac7ab2 176 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
57d104c1
SJ		 177};
178
179static inline enum ufs_dev_pwr_mode
180ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
181{
182 return ufs_pm_lvl_states[lvl].dev_state;
183}
184
185static inline enum uic_link_state
186ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
187{
188 return ufs_pm_lvl_states[lvl].link_state;
189}
190
0c8f7586 191static inline enum ufs_pm_level
192ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
193 enum uic_link_state link_state)
194{
195 enum ufs_pm_level lvl;
196
197 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
198 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
199 (ufs_pm_lvl_states[lvl].link_state == link_state))
200 return lvl;
201 }
202
203 /* if no match found, return the level 0 */
204 return UFS_PM_LVL_0;
205}
206
56d4a186
SJ		 207static struct ufs_dev_fix ufs_fixups[] = {
208 /* UFS cards deviations table */
c0a18ee0 209 UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
63522bf3
BH		 210 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
211 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ),
56d4a186 212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
ed0b40ff
SC		 213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
214 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
56d4a186 215 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
ed0b40ff
SC		 216 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
217 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
218 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
219 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 220 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
221 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
222 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
223 UFS_DEVICE_QUIRK_PA_TACTIVATE),
224 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
225 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 226 END_FIX
227};
228
9333d775 229static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 230static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 231static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 232static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 233static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 234static void ufshcd_hba_exit(struct ufs_hba *hba);
68444d73 235static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
1ab27c9c 236static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
cad2e03d 237static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 238static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 239static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
240static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 241static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 242static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 243static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 244static int ufshcd_change_power_mode(struct ufs_hba *hba,
245 struct ufs_pa_layer_attr *pwr_mode);
c72e79c0
CG		 246static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
247static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
248static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
249 struct ufs_vreg *vreg);
307348f6 250static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
3b5f3c0d
YH		 251static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
252static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
dd7143e2
CG		 253static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
254static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
3d17b9b5 255
5231d38c 256static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 257{
57d104c1 258 if (!hba->is_irq_enabled) {
5231d38c 259 enable_irq(hba->irq);
57d104c1
SJ		 260 hba->is_irq_enabled = true;
261 }
57d104c1
SJ		 262}
263
264static inline void ufshcd_disable_irq(struct ufs_hba *hba)
265{
266 if (hba->is_irq_enabled) {
5231d38c 267 disable_irq(hba->irq);
57d104c1
SJ		 268 hba->is_irq_enabled = false;
269 }
270}
3441da7d 271
3d17b9b5
AD		 272static inline void ufshcd_wb_config(struct ufs_hba *hba)
273{
79e3520f 274 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 275 return;
276
3b5f3c0d
YH		 277 ufshcd_wb_toggle(hba, true);
278
279 ufshcd_wb_toggle_flush_during_h8(hba, true);
21acf460
SC		 280 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
281 ufshcd_wb_toggle_flush(hba, true);
3d17b9b5
AD		 282}
283
38135535
SJ		 284static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
285{
286 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
287 scsi_unblock_requests(hba->host);
288}
289
290static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
291{
292 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
293 scsi_block_requests(hba->host);
294}
295
6667e6d9 296static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 297 enum ufs_trace_str_t str_t)
6667e6d9
OS		 298{
299 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
89ac2c3b 300 struct utp_upiu_header *header;
6667e6d9 301
9d5095e7
BH		 302 if (!trace_ufshcd_upiu_enabled())
303 return;
304
89ac2c3b
BH		 305 if (str_t == UFS_CMD_SEND)
306 header = &rq->header;
307 else
308 header = &hba->lrb[tag].ucd_rsp_ptr->header;
309
310 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
867fdc2d 311 UFS_TSF_CDB);
6667e6d9
OS		 312}
313
fb475b74
AA		 314static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
315 enum ufs_trace_str_t str_t,
316 struct utp_upiu_req *rq_rsp)
6667e6d9 317{
9d5095e7
BH		 318 if (!trace_ufshcd_upiu_enabled())
319 return;
6667e6d9 320
be20b51c 321 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
867fdc2d 322 &rq_rsp->qr, UFS_TSF_OSF);
6667e6d9
OS		 323}
324
325static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 326 enum ufs_trace_str_t str_t)
6667e6d9 327{
e8c2da7e 328 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
6667e6d9 329
9d5095e7
BH		 330 if (!trace_ufshcd_upiu_enabled())
331 return;
332
0ed083e9 333 if (str_t == UFS_TM_SEND)
1352eec8
GS		 334 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
335 &descp->upiu_req.req_header,
336 &descp->upiu_req.input_param1,
337 UFS_TSF_TM_INPUT);
0ed083e9 338 else
1352eec8
GS		 339 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
340 &descp->upiu_rsp.rsp_header,
341 &descp->upiu_rsp.output_param1,
342 UFS_TSF_TM_OUTPUT);
6667e6d9
OS		 343}
344
aa5c6979
SC		 345static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
346 struct uic_command *ucmd,
28fa68fc 347 enum ufs_trace_str_t str_t)
aa5c6979
SC		 348{
349 u32 cmd;
350
351 if (!trace_ufshcd_uic_command_enabled())
352 return;
353
28fa68fc 354 if (str_t == UFS_CMD_SEND)
aa5c6979
SC		 355 cmd = ucmd->command;
356 else
357 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
358
28fa68fc 359 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
aa5c6979
SC		 360 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
361 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
362 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
363}
364
28fa68fc
BH		 365static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
366 enum ufs_trace_str_t str_t)
1a07f2d9 367{
2bd3b6b7 368 u64 lba = 0;
69a314d6 369 u8 opcode = 0, group_id = 0;
1a07f2d9 370 u32 intr, doorbell;
e7c3b379 371 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 372 struct scsi_cmnd *cmd = lrbp->cmd;
3f2c1002 373 struct request *rq = scsi_cmd_to_rq(cmd);
1a07f2d9
LS		 374 int transfer_len = -1;
375
44b5de36
BH		 376 if (!cmd)
377 return;
378
44b5de36
BH		 379 /* trace UPIU also */
380 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
f0101af4
BH		 381 if (!trace_ufshcd_command_enabled())
382 return;
383
44b5de36 384 opcode = cmd->cmnd[0];
44b5de36
BH		 385
386 if (opcode == READ_10 || opcode == WRITE_10) {
387 /*
388 * Currently we only fully trace read(10) and write(10) commands
389 */
390 transfer_len =
391 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
2bd3b6b7 392 lba = scsi_get_lba(cmd);
44b5de36
BH		 393 if (opcode == WRITE_10)
394 group_id = lrbp->cmd->cmnd[6];
395 } else if (opcode == UNMAP) {
396 /*
397 * The number of Bytes to be unmapped beginning with the lba.
398 */
3f2c1002 399 transfer_len = blk_rq_bytes(rq);
2bd3b6b7 400 lba = scsi_get_lba(cmd);
1a07f2d9
LS		 401 }
402
403 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
404 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
28fa68fc 405 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
69a314d6 406 doorbell, transfer_len, intr, lba, opcode, group_id);
1a07f2d9
LS		 407}
408
ff8e20c6
DR		 409static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
410{
411 struct ufs_clk_info *clki;
412 struct list_head *head = &hba->clk_list_head;
413
566ec9ad 414 if (list_empty(head))
ff8e20c6
DR		 415 return;
416
417 list_for_each_entry(clki, head, list) {
418 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
419 clki->max_freq)
420 dev_err(hba->dev, "clk: %s, rate: %u\n",
421 clki->name, clki->curr_freq);
422 }
423}
424
e965e5e0
SC		 425static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
426 char *err_name)
ff8e20c6
DR		 427{
428 int i;
27752647 429 bool found = false;
e965e5e0 430 struct ufs_event_hist *e;
ff8e20c6 431
e965e5e0
SC		 432 if (id >= UFS_EVT_CNT)
433 return;
ff8e20c6 434
e965e5e0 435 e = &hba->ufs_stats.event[id];
ff8e20c6 436
e965e5e0
SC		 437 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
438 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
439
440 if (e->tstamp[p] == 0)
ff8e20c6 441 continue;
c5397f13 442 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
e965e5e0 443 e->val[p], ktime_to_us(e->tstamp[p]));
27752647 444 found = true;
ff8e20c6 445 }
27752647
SC		 446
447 if (!found)
fd1fb4d5 448 dev_err(hba->dev, "No record of %s\n", err_name);
bafd09f8
DH		 449 else
450 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
ff8e20c6
DR		 451}
452
e965e5e0 453static void ufshcd_print_evt_hist(struct ufs_hba *hba)
66cc820f 454{
ba80917d 455 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
ff8e20c6 456
e965e5e0
SC		 457 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
458 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
459 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
460 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
461 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
462 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
463 "auto_hibern8_err");
464 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
465 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
466 "link_startup_fail");
467 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
468 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
469 "suspend_fail");
470 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
471 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
472 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
ff8e20c6 473
7c486d91 474 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 475}
476
477static
478void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
479{
480 struct ufshcd_lrb *lrbp;
7fabb77b 481 int prdt_length;
66cc820f
DR		 482 int tag;
483
484 for_each_set_bit(tag, &bitmap, hba->nutrs) {
485 lrbp = &hba->lrb[tag];
486
ff8e20c6
DR		 487 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
488 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 489 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
490 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 491 dev_err(hba->dev,
492 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
493 tag, (u64)lrbp->utrd_dma_addr);
494
66cc820f
DR		 495 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
496 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 497 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
498 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 499 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
500 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 501 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
502 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 503 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
504 sizeof(struct utp_upiu_rsp));
66cc820f 505
7fabb77b
GB		 506 prdt_length = le16_to_cpu(
507 lrbp->utr_descriptor_ptr->prd_table_length);
cc770ce3
EB		 508 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
509 prdt_length /= sizeof(struct ufshcd_sg_entry);
510
7fabb77b
GB		 511 dev_err(hba->dev,
512 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
513 tag, prdt_length,
514 (u64)lrbp->ucd_prdt_dma_addr);
515
516 if (pr_prdt)
66cc820f 517 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 518 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 519 }
520}
521
522static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
523{
66cc820f
DR		 524 int tag;
525
526 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 527 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
528
66cc820f 529 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 530 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 531 }
532}
533
6ba65588
GB		 534static void ufshcd_print_host_state(struct ufs_hba *hba)
535{
3f8af604
CG		 536 struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
537
6ba65588 538 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 539 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
540 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 541 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
542 hba->saved_err, hba->saved_uic_err);
543 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
544 hba->curr_dev_pwr_mode, hba->uic_link_state);
545 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
546 hba->pm_op_in_progress, hba->is_sys_suspended);
547 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
548 hba->auto_bkops_enabled, hba->host->host_self_blocked);
549 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
3f8af604
CG		 550 dev_err(hba->dev,
551 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
552 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
553 hba->ufs_stats.hibern8_exit_cnt);
554 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
555 ktime_to_us(hba->ufs_stats.last_intr_ts),
556 hba->ufs_stats.last_intr_status);
6ba65588
GB		 557 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
558 hba->eh_flags, hba->req_abort_count);
3f8af604
CG		 559 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
560 hba->ufs_version, hba->capabilities, hba->caps);
6ba65588
GB		 561 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
562 hba->dev_quirks);
3f8af604
CG		 563 if (sdev_ufs)
564 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
565 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
566
567 ufshcd_print_clk_freqs(hba);
6ba65588
GB		 568}
569
ff8e20c6
DR		 570/**
571 * ufshcd_print_pwr_info - print power params as saved in hba
572 * power info
573 * @hba: per-adapter instance
574 */
575static void ufshcd_print_pwr_info(struct ufs_hba *hba)
576{
577 static const char * const names[] = {
578 "INVALID MODE",
579 "FAST MODE",
580 "SLOW_MODE",
581 "INVALID MODE",
582 "FASTAUTO_MODE",
583 "SLOWAUTO_MODE",
584 "INVALID MODE",
585 };
586
71bb9ab6
AH		 587 /*
588 * Using dev_dbg to avoid messages during runtime PM to avoid
589 * never-ending cycles of messages written back to storage by user space
590 * causing runtime resume, causing more messages and so on.
591 */
592 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
ff8e20c6
DR		 593 __func__,
594 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
595 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
596 names[hba->pwr_info.pwr_rx],
597 names[hba->pwr_info.pwr_tx],
598 hba->pwr_info.hs_rate);
599}
600
31a5d9ca
SC		 601static void ufshcd_device_reset(struct ufs_hba *hba)
602{
603 int err;
604
605 err = ufshcd_vops_device_reset(hba);
606
607 if (!err) {
608 ufshcd_set_ufs_dev_active(hba);
609 if (ufshcd_is_wb_allowed(hba)) {
4cd48995
BH		 610 hba->dev_info.wb_enabled = false;
611 hba->dev_info.wb_buf_flush_enabled = false;
31a5d9ca
SC		 612 }
613 }
614 if (err != -EOPNOTSUPP)
615 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
616}
617
5c955c10
SC		 618void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
619{
620 if (!us)
621 return;
622
623 if (us < 10)
624 udelay(us);
625 else
626 usleep_range(us, us + tolerance);
627}
628EXPORT_SYMBOL_GPL(ufshcd_delay_us);
629
5cac1095 630/**
5a0b0cb9 631 * ufshcd_wait_for_register - wait for register value to change
5cac1095
BVA		 632 * @hba: per-adapter interface
633 * @reg: mmio register offset
634 * @mask: mask to apply to the read register value
635 * @val: value to wait for
636 * @interval_us: polling interval in microseconds
637 * @timeout_ms: timeout in milliseconds
5a0b0cb9 638 *
5cac1095
BVA		 639 * Return:
640 * -ETIMEDOUT on error, zero on success.
5a0b0cb9 641 */
59a57bb7 642static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
596585a2 643 u32 val, unsigned long interval_us,
5cac1095 644 unsigned long timeout_ms)
5a0b0cb9
SRT		 645{
646 int err = 0;
647 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
648
649 /* ignore bits that we don't intend to wait on */
650 val = val & mask;
651
652 while ((ufshcd_readl(hba, reg) & mask) != val) {
5cac1095 653 usleep_range(interval_us, interval_us + 50);
5a0b0cb9
SRT		 654 if (time_after(jiffies, timeout)) {
655 if ((ufshcd_readl(hba, reg) & mask) != val)
656 err = -ETIMEDOUT;
657 break;
658 }
659 }
660
661 return err;
662}
663
2fbd009b
SJ		 664/**
665 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 666 * @hba: Pointer to adapter instance
2fbd009b
SJ		 667 *
668 * Returns interrupt bit mask per version
669 */
670static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
671{
51428818
CC		 672 if (hba->ufs_version == ufshci_version(1, 0))
673 return INTERRUPT_MASK_ALL_VER_10;
674 if (hba->ufs_version <= ufshci_version(2, 0))
675 return INTERRUPT_MASK_ALL_VER_11;
c01848c6 676
51428818 677 return INTERRUPT_MASK_ALL_VER_21;
2fbd009b
SJ		 678}
679
7a3e97b0
SY		 680/**
681 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 682 * @hba: Pointer to adapter instance
7a3e97b0
SY		 683 *
684 * Returns UFSHCI version supported by the controller
685 */
686static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
687{
51428818
CC		 688 u32 ufshci_ver;
689
0263bcd0 690 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
51428818
CC		 691 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
692 else
693 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
9949e702 694
51428818
CC		 695 /*
696 * UFSHCI v1.x uses a different version scheme, in order
697 * to allow the use of comparisons with the ufshci_version
698 * function, we convert it to the same scheme as ufs 2.0+.
699 */
700 if (ufshci_ver & 0x00010000)
701 return ufshci_version(1, ufshci_ver & 0x00000100);
702
703 return ufshci_ver;
7a3e97b0
SY		 704}
705
706/**
707 * ufshcd_is_device_present - Check if any device connected to
708 * the host controller
5c0c28a8 709 * @hba: pointer to adapter instance
7a3e97b0 710 *
c9e6010b 711 * Returns true if device present, false if no device detected
7a3e97b0 712 */
c9e6010b 713static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 714{
51d1628f 715 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
7a3e97b0
SY		 716}
717
718/**
719 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 720 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 721 *
722 * This function is used to get the OCS field from UTRD
723 * Returns the OCS field in the UTRD
724 */
957d63e7 725static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
7a3e97b0 726{
e8c8e82a 727 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 728}
729
7a3e97b0
SY		 730/**
731 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
732 * @hba: per adapter instance
733 * @pos: position of the bit to be cleared
734 */
735static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
736{
87183841
AA		 737 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
738 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
739 else
740 ufshcd_writel(hba, ~(1 << pos),
741 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 742}
743
744/**
745 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
746 * @hba: per adapter instance
747 * @pos: position of the bit to be cleared
748 */
749static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
750{
87183841
AA		 751 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
752 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
753 else
754 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 755}
756
757/**
758 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
759 * @reg: Register value of host controller status
760 *
761 * Returns integer, 0 on Success and positive value if failed
762 */
763static inline int ufshcd_get_lists_status(u32 reg)
764{
6cf16115 765 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 766}
767
768/**
769 * ufshcd_get_uic_cmd_result - Get the UIC command result
770 * @hba: Pointer to adapter instance
771 *
772 * This function gets the result of UIC command completion
773 * Returns 0 on success, non zero value on error
774 */
775static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
776{
b873a275 777 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 778 MASK_UIC_COMMAND_RESULT;
779}
780
12b4fdb4
SJ		 781/**
782 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
783 * @hba: Pointer to adapter instance
784 *
785 * This function gets UIC command argument3
786 * Returns 0 on success, non zero value on error
787 */
788static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
789{
790 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
791}
792
7a3e97b0 793/**
5a0b0cb9 794 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 795 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 796 */
797static inline int
5a0b0cb9 798ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 799{
5a0b0cb9 800 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 801}
802
803/**
804 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
805 * @ucd_rsp_ptr: pointer to response UPIU
806 *
807 * This function gets the response status and scsi_status from response UPIU
808 * Returns the response result code.
809 */
810static inline int
811ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
812{
813 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
814}
815
1c2623c5
SJ		 816/*
817 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
818 * from response UPIU
819 * @ucd_rsp_ptr: pointer to response UPIU
820 *
821 * Return the data segment length.
822 */
823static inline unsigned int
824ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
825{
826 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
827 MASK_RSP_UPIU_DATA_SEG_LEN;
828}
829
66ec6d59
SRT		 830/**
831 * ufshcd_is_exception_event - Check if the device raised an exception event
832 * @ucd_rsp_ptr: pointer to response UPIU
833 *
834 * The function checks if the device raised an exception event indicated in
835 * the Device Information field of response UPIU.
836 *
837 * Returns true if exception is raised, false otherwise.
838 */
839static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
840{
841 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
51d1628f 842 MASK_RSP_EXCEPTION_EVENT;
66ec6d59
SRT		 843}
844
7a3e97b0 845/**
7d568652 846 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 847 * @hba: per adapter instance
7a3e97b0
SY		 848 */
849static inline void
7d568652 850ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 851{
7d568652
SJ		 852 ufshcd_writel(hba, INT_AGGR_ENABLE |
853 INT_AGGR_COUNTER_AND_TIMER_RESET,
854 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
855}
856
857/**
858 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
859 * @hba: per adapter instance
860 * @cnt: Interrupt aggregation counter threshold
861 * @tmout: Interrupt aggregation timeout value
862 */
863static inline void
864ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
865{
866 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
867 INT_AGGR_COUNTER_THLD_VAL(cnt) |
868 INT_AGGR_TIMEOUT_VAL(tmout),
869 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 870}
871
b852190e
YG		 872/**
873 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
874 * @hba: per adapter instance
875 */
876static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
877{
878 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
879}
880
7a3e97b0
SY		 881/**
882 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
883 * When run-stop registers are set to 1, it indicates the
884 * host controller that it can process the requests
885 * @hba: per adapter instance
886 */
887static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
888{
b873a275
SJ		 889 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
890 REG_UTP_TASK_REQ_LIST_RUN_STOP);
891 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
892 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 893}
894
7a3e97b0
SY		 895/**
896 * ufshcd_hba_start - Start controller initialization sequence
897 * @hba: per adapter instance
898 */
899static inline void ufshcd_hba_start(struct ufs_hba *hba)
900{
df043c74
ST		 901 u32 val = CONTROLLER_ENABLE;
902
903 if (ufshcd_crypto_enable(hba))
904 val |= CRYPTO_GENERAL_ENABLE;
905
906 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 907}
908
909/**
910 * ufshcd_is_hba_active - Get controller state
911 * @hba: per adapter instance
912 *
c9e6010b 913 * Returns false if controller is active, true otherwise
7a3e97b0 914 */
c9e6010b 915static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 916{
4a8eec2b
TK		 917 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
918 ? false : true;
7a3e97b0
SY		 919}
920
37113106
YG		 921u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
922{
923 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
51428818 924 if (hba->ufs_version <= ufshci_version(1, 1))
37113106
YG		 925 return UFS_UNIPRO_VER_1_41;
926 else
927 return UFS_UNIPRO_VER_1_6;
928}
929EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
930
931static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
932{
933 /*
934 * If both host and device support UniPro ver1.6 or later, PA layer
935 * parameters tuning happens during link startup itself.
936 *
937 * We can manually tune PA layer parameters if either host or device
938 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
939 * logic simple, we will only do manual tuning if local unipro version
940 * doesn't support ver1.6 or later.
941 */
942 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
943 return true;
944 else
945 return false;
946}
947
394b949f
SJ		 948/**
949 * ufshcd_set_clk_freq - set UFS controller clock frequencies
950 * @hba: per adapter instance
951 * @scale_up: If True, set max possible frequency othewise set low frequency
952 *
953 * Returns 0 if successful
954 * Returns < 0 for any other errors
955 */
956static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 957{
958 int ret = 0;
959 struct ufs_clk_info *clki;
960 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 961
566ec9ad 962 if (list_empty(head))
a3cd5ec5 963 goto out;
964
a3cd5ec5 965 list_for_each_entry(clki, head, list) {
966 if (!IS_ERR_OR_NULL(clki->clk)) {
967 if (scale_up && clki->max_freq) {
968 if (clki->curr_freq == clki->max_freq)
969 continue;
970
a3cd5ec5 971 ret = clk_set_rate(clki->clk, clki->max_freq);
972 if (ret) {
973 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
974 __func__, clki->name,
975 clki->max_freq, ret);
976 break;
977 }
978 trace_ufshcd_clk_scaling(dev_name(hba->dev),
979 "scaled up", clki->name,
980 clki->curr_freq,
981 clki->max_freq);
982
983 clki->curr_freq = clki->max_freq;
984
985 } else if (!scale_up && clki->min_freq) {
986 if (clki->curr_freq == clki->min_freq)
987 continue;
988
a3cd5ec5 989 ret = clk_set_rate(clki->clk, clki->min_freq);
990 if (ret) {
991 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
992 __func__, clki->name,
993 clki->min_freq, ret);
994 break;
995 }
996 trace_ufshcd_clk_scaling(dev_name(hba->dev),
997 "scaled down", clki->name,
998 clki->curr_freq,
999 clki->min_freq);
1000 clki->curr_freq = clki->min_freq;
1001 }
1002 }
1003 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1004 clki->name, clk_get_rate(clki->clk));
1005 }
1006
394b949f
SJ		 1007out:
1008 return ret;
1009}
1010
1011/**
1012 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1013 * @hba: per adapter instance
1014 * @scale_up: True if scaling up and false if scaling down
1015 *
1016 * Returns 0 if successful
1017 * Returns < 0 for any other errors
1018 */
1019static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1020{
1021 int ret = 0;
1022 ktime_t start = ktime_get();
1023
1024 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1025 if (ret)
1026 goto out;
1027
1028 ret = ufshcd_set_clk_freq(hba, scale_up);
1029 if (ret)
1030 goto out;
1031
a3cd5ec5 1032 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 1033 if (ret)
1034 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 1035
1036out:
394b949f 1037 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 1038 (scale_up ? "up" : "down"),
1039 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1040 return ret;
1041}
1042
1043/**
1044 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1045 * @hba: per adapter instance
1046 * @scale_up: True if scaling up and false if scaling down
1047 *
1048 * Returns true if scaling is required, false otherwise.
1049 */
1050static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1051 bool scale_up)
1052{
1053 struct ufs_clk_info *clki;
1054 struct list_head *head = &hba->clk_list_head;
1055
566ec9ad 1056 if (list_empty(head))
a3cd5ec5 1057 return false;
1058
1059 list_for_each_entry(clki, head, list) {
1060 if (!IS_ERR_OR_NULL(clki->clk)) {
1061 if (scale_up && clki->max_freq) {
1062 if (clki->curr_freq == clki->max_freq)
1063 continue;
1064 return true;
1065 } else if (!scale_up && clki->min_freq) {
1066 if (clki->curr_freq == clki->min_freq)
1067 continue;
1068 return true;
1069 }
1070 }
1071 }
1072
1073 return false;
1074}
1075
8d077ede
BVA		 1076/*
1077 * Determine the number of pending commands by counting the bits in the SCSI
1078 * device budget maps. This approach has been selected because a bit is set in
1079 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1080 * flag. The host_self_blocked flag can be modified by calling
1081 * scsi_block_requests() or scsi_unblock_requests().
1082 */
1083static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1084{
1085 struct scsi_device *sdev;
1086 u32 pending = 0;
1087
99c66a88
BH		 1088 lockdep_assert_held(hba->host->host_lock);
1089 __shost_for_each_device(sdev, hba->host)
8d077ede
BVA		 1090 pending += sbitmap_weight(&sdev->budget_map);
1091
1092 return pending;
1093}
1094
a3cd5ec5 1095static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1096 u64 wait_timeout_us)
1097{
1098 unsigned long flags;
1099 int ret = 0;
1100 u32 tm_doorbell;
8d077ede 1101 u32 tr_pending;
a3cd5ec5 1102 bool timeout = false, do_last_check = false;
1103 ktime_t start;
1104
1105 ufshcd_hold(hba, false);
1106 spin_lock_irqsave(hba->host->host_lock, flags);
1107 /*
1108 * Wait for all the outstanding tasks/transfer requests.
1109 * Verify by checking the doorbell registers are clear.
1110 */
1111 start = ktime_get();
1112 do {
1113 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1114 ret = -EBUSY;
1115 goto out;
1116 }
1117
1118 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
8d077ede
BVA		 1119 tr_pending = ufshcd_pending_cmds(hba);
1120 if (!tm_doorbell && !tr_pending) {
a3cd5ec5 1121 timeout = false;
1122 break;
1123 } else if (do_last_check) {
1124 break;
1125 }
1126
1127 spin_unlock_irqrestore(hba->host->host_lock, flags);
1128 schedule();
1129 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1130 wait_timeout_us) {
1131 timeout = true;
1132 /*
1133 * We might have scheduled out for long time so make
1134 * sure to check if doorbells are cleared by this time
1135 * or not.
1136 */
1137 do_last_check = true;
1138 }
1139 spin_lock_irqsave(hba->host->host_lock, flags);
8d077ede 1140 } while (tm_doorbell || tr_pending);
a3cd5ec5 1141
1142 if (timeout) {
1143 dev_err(hba->dev,
1144 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
8d077ede 1145 __func__, tm_doorbell, tr_pending);
a3cd5ec5 1146 ret = -EBUSY;
1147 }
1148out:
1149 spin_unlock_irqrestore(hba->host->host_lock, flags);
1150 ufshcd_release(hba);
1151 return ret;
1152}
1153
1154/**
1155 * ufshcd_scale_gear - scale up/down UFS gear
1156 * @hba: per adapter instance
1157 * @scale_up: True for scaling up gear and false for scaling down
1158 *
1159 * Returns 0 for success,
1160 * Returns -EBUSY if scaling can't happen at this time
1161 * Returns non-zero for any other errors
1162 */
1163static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1164{
a3cd5ec5 1165 int ret = 0;
1166 struct ufs_pa_layer_attr new_pwr_info;
1167
1168 if (scale_up) {
1169 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1170 sizeof(struct ufs_pa_layer_attr));
1171 } else {
1172 memcpy(&new_pwr_info, &hba->pwr_info,
1173 sizeof(struct ufs_pa_layer_attr));
1174
29b87e92
CG		 1175 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1176 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
a3cd5ec5 1177 /* save the current power mode */
1178 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1179 &hba->pwr_info,
1180 sizeof(struct ufs_pa_layer_attr));
1181
1182 /* scale down gear */
29b87e92
CG		 1183 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1184 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
a3cd5ec5 1185 }
1186 }
1187
1188 /* check if the power mode needs to be changed or not? */
6a9df818 1189 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1190 if (ret)
1191 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1192 __func__, ret,
1193 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1194 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1195
1196 return ret;
1197}
1198
1199static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1200{
1201 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1202 int ret = 0;
1203 /*
1204 * make sure that there are no outstanding requests when
1205 * clock scaling is in progress
1206 */
38135535 1207 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1208 down_write(&hba->clk_scaling_lock);
0e9d4ca4
CG		 1209
1210 if (!hba->clk_scaling.is_allowed ||
1211 ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
a3cd5ec5 1212 ret = -EBUSY;
1213 up_write(&hba->clk_scaling_lock);
38135535 1214 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1215 goto out;
a3cd5ec5 1216 }
1217
0e9d4ca4
CG		 1218 /* let's not get into low power until clock scaling is completed */
1219 ufshcd_hold(hba, false);
1220
1221out:
a3cd5ec5 1222 return ret;
1223}
1224
0e9d4ca4 1225static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
a3cd5ec5 1226{
0e9d4ca4
CG		 1227 if (writelock)
1228 up_write(&hba->clk_scaling_lock);
1229 else
1230 up_read(&hba->clk_scaling_lock);
38135535 1231 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1232 ufshcd_release(hba);
a3cd5ec5 1233}
1234
1235/**
1236 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1237 * @hba: per adapter instance
1238 * @scale_up: True for scaling up and false for scalin down
1239 *
1240 * Returns 0 for success,
1241 * Returns -EBUSY if scaling can't happen at this time
1242 * Returns non-zero for any other errors
1243 */
1244static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1245{
1246 int ret = 0;
0e9d4ca4 1247 bool is_writelock = true;
401f1e44 1248
a3cd5ec5 1249 ret = ufshcd_clock_scaling_prepare(hba);
1250 if (ret)
0e9d4ca4 1251 return ret;
a3cd5ec5 1252
1253 /* scale down the gear before scaling down clocks */
1254 if (!scale_up) {
1255 ret = ufshcd_scale_gear(hba, false);
1256 if (ret)
394b949f 1257 goto out_unprepare;
a3cd5ec5 1258 }
1259
1260 ret = ufshcd_scale_clks(hba, scale_up);
1261 if (ret) {
1262 if (!scale_up)
1263 ufshcd_scale_gear(hba, true);
394b949f 1264 goto out_unprepare;
a3cd5ec5 1265 }
1266
1267 /* scale up the gear after scaling up clocks */
1268 if (scale_up) {
1269 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1270 if (ret) {
a3cd5ec5 1271 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1272 goto out_unprepare;
1273 }
a3cd5ec5 1274 }
1275
3d17b9b5 1276 /* Enable Write Booster if we have scaled up else disable it */
0e9d4ca4
CG		 1277 downgrade_write(&hba->clk_scaling_lock);
1278 is_writelock = false;
3b5f3c0d 1279 ufshcd_wb_toggle(hba, scale_up);
3d17b9b5 1280
394b949f 1281out_unprepare:
0e9d4ca4 1282 ufshcd_clock_scaling_unprepare(hba, is_writelock);
a3cd5ec5 1283 return ret;
1284}
1285
401f1e44 1286static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1287{
1288 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1289 clk_scaling.suspend_work);
1290 unsigned long irq_flags;
1291
1292 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1293 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1294 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1295 return;
1296 }
1297 hba->clk_scaling.is_suspended = true;
1298 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1299
1300 __ufshcd_suspend_clkscaling(hba);
1301}
1302
1303static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1304{
1305 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1306 clk_scaling.resume_work);
1307 unsigned long irq_flags;
1308
1309 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1310 if (!hba->clk_scaling.is_suspended) {
1311 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1312 return;
1313 }
1314 hba->clk_scaling.is_suspended = false;
1315 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1316
1317 devfreq_resume_device(hba->devfreq);
1318}
1319
a3cd5ec5 1320static int ufshcd_devfreq_target(struct device *dev,
1321 unsigned long *freq, u32 flags)
1322{
1323 int ret = 0;
1324 struct ufs_hba *hba = dev_get_drvdata(dev);
1325 ktime_t start;
401f1e44 1326 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1327 struct list_head *clk_list = &hba->clk_list_head;
1328 struct ufs_clk_info *clki;
a3cd5ec5 1329 unsigned long irq_flags;
1330
1331 if (!ufshcd_is_clkscaling_supported(hba))
1332 return -EINVAL;
1333
91831d33
AD		 1334 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1335 /* Override with the closest supported frequency */
1336 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1337 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1338 if (ufshcd_eh_in_progress(hba)) {
1339 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1340 return 0;
1341 }
1342
401f1e44 1343 if (!hba->clk_scaling.active_reqs)
1344 sched_clk_scaling_suspend_work = true;
1345
092b4558
BA		 1346 if (list_empty(clk_list)) {
1347 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1348 goto out;
1349 }
1350
91831d33 1351 /* Decide based on the rounded-off frequency and update */
51d1628f 1352 scale_up = *freq == clki->max_freq;
91831d33
AD		 1353 if (!scale_up)
1354 *freq = clki->min_freq;
1355 /* Update the frequency */
401f1e44 1356 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1357 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1358 ret = 0;
1359 goto out; /* no state change required */
a3cd5ec5 1360 }
1361 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1362
1363 start = ktime_get();
a3cd5ec5 1364 ret = ufshcd_devfreq_scale(hba, scale_up);
1365
a3cd5ec5 1366 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1367 (scale_up ? "up" : "down"),
1368 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1369
401f1e44 1370out:
1371 if (sched_clk_scaling_suspend_work)
1372 queue_work(hba->clk_scaling.workq,
1373 &hba->clk_scaling.suspend_work);
1374
a3cd5ec5 1375 return ret;
1376}
1377
a3cd5ec5 1378static int ufshcd_devfreq_get_dev_status(struct device *dev,
1379 struct devfreq_dev_status *stat)
1380{
1381 struct ufs_hba *hba = dev_get_drvdata(dev);
1382 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1383 unsigned long flags;
91831d33
AD		 1384 struct list_head *clk_list = &hba->clk_list_head;
1385 struct ufs_clk_info *clki;
b1bf66d1 1386 ktime_t curr_t;
a3cd5ec5 1387
1388 if (!ufshcd_is_clkscaling_supported(hba))
1389 return -EINVAL;
1390
1391 memset(stat, 0, sizeof(*stat));
1392
1393 spin_lock_irqsave(hba->host->host_lock, flags);
b1bf66d1 1394 curr_t = ktime_get();
a3cd5ec5 1395 if (!scaling->window_start_t)
1396 goto start_window;
1397
91831d33
AD		 1398 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1399 /*
1400 * If current frequency is 0, then the ondemand governor considers
1401 * there's no initial frequency set. And it always requests to set
1402 * to max. frequency.
1403 */
1404 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1405 if (scaling->is_busy_started)
b1bf66d1
SC		 1406 scaling->tot_busy_t += ktime_us_delta(curr_t,
1407 scaling->busy_start_t);
a3cd5ec5 1408
b1bf66d1 1409 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
a3cd5ec5 1410 stat->busy_time = scaling->tot_busy_t;
1411start_window:
b1bf66d1 1412 scaling->window_start_t = curr_t;
a3cd5ec5 1413 scaling->tot_busy_t = 0;
1414
1415 if (hba->outstanding_reqs) {
b1bf66d1 1416 scaling->busy_start_t = curr_t;
a3cd5ec5 1417 scaling->is_busy_started = true;
1418 } else {
1419 scaling->busy_start_t = 0;
1420 scaling->is_busy_started = false;
1421 }
1422 spin_unlock_irqrestore(hba->host->host_lock, flags);
1423 return 0;
1424}
1425
deac444f
BA		 1426static int ufshcd_devfreq_init(struct ufs_hba *hba)
1427{
092b4558
BA		 1428 struct list_head *clk_list = &hba->clk_list_head;
1429 struct ufs_clk_info *clki;
deac444f
BA		 1430 struct devfreq *devfreq;
1431 int ret;
1432
092b4558
BA		 1433 /* Skip devfreq if we don't have any clocks in the list */
1434 if (list_empty(clk_list))
1435 return 0;
1436
1437 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1438 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1439 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1440
90b8491c
SC		 1441 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1442 &hba->vps->ondemand_data);
092b4558 1443 devfreq = devfreq_add_device(hba->dev,
90b8491c 1444 &hba->vps->devfreq_profile,
deac444f 1445 DEVFREQ_GOV_SIMPLE_ONDEMAND,
90b8491c 1446 &hba->vps->ondemand_data);
deac444f
BA		 1447 if (IS_ERR(devfreq)) {
1448 ret = PTR_ERR(devfreq);
1449 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1450
1451 dev_pm_opp_remove(hba->dev, clki->min_freq);
1452 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1453 return ret;
1454 }
1455
1456 hba->devfreq = devfreq;
1457
1458 return 0;
1459}
1460
092b4558
BA		 1461static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1462{
1463 struct list_head *clk_list = &hba->clk_list_head;
1464 struct ufs_clk_info *clki;
1465
1466 if (!hba->devfreq)
1467 return;
1468
1469 devfreq_remove_device(hba->devfreq);
1470 hba->devfreq = NULL;
1471
1472 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1473 dev_pm_opp_remove(hba->dev, clki->min_freq);
1474 dev_pm_opp_remove(hba->dev, clki->max_freq);
1475}
1476
401f1e44 1477static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1478{
1479 unsigned long flags;
1480
1481 devfreq_suspend_device(hba->devfreq);
1482 spin_lock_irqsave(hba->host->host_lock, flags);
1483 hba->clk_scaling.window_start_t = 0;
1484 spin_unlock_irqrestore(hba->host->host_lock, flags);
1485}
a3cd5ec5 1486
a508253d
GB		 1487static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1488{
401f1e44 1489 unsigned long flags;
1490 bool suspend = false;
1491
f9a7fa34
SC		 1492 cancel_work_sync(&hba->clk_scaling.suspend_work);
1493 cancel_work_sync(&hba->clk_scaling.resume_work);
fcb0c4b0 1494
401f1e44 1495 spin_lock_irqsave(hba->host->host_lock, flags);
1496 if (!hba->clk_scaling.is_suspended) {
1497 suspend = true;
1498 hba->clk_scaling.is_suspended = true;
1499 }
1500 spin_unlock_irqrestore(hba->host->host_lock, flags);
1501
1502 if (suspend)
1503 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1504}
1505
1506static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1507{
401f1e44 1508 unsigned long flags;
1509 bool resume = false;
1510
401f1e44 1511 spin_lock_irqsave(hba->host->host_lock, flags);
1512 if (hba->clk_scaling.is_suspended) {
1513 resume = true;
1514 hba->clk_scaling.is_suspended = false;
1515 }
1516 spin_unlock_irqrestore(hba->host->host_lock, flags);
1517
1518 if (resume)
1519 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1520}
1521
1522static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1523 struct device_attribute *attr, char *buf)
1524{
1525 struct ufs_hba *hba = dev_get_drvdata(dev);
1526
1481b7fe 1527 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
fcb0c4b0
ST		 1528}
1529
1530static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1531 struct device_attribute *attr, const char *buf, size_t count)
1532{
1533 struct ufs_hba *hba = dev_get_drvdata(dev);
1534 u32 value;
9cd20d3f 1535 int err = 0;
fcb0c4b0
ST		 1536
1537 if (kstrtou32(buf, 0, &value))
1538 return -EINVAL;
1539
9cd20d3f
CG		 1540 down(&hba->host_sem);
1541 if (!ufshcd_is_user_access_allowed(hba)) {
1542 err = -EBUSY;
1543 goto out;
1544 }
1545
fcb0c4b0 1546 value = !!value;
0e9d4ca4 1547 if (value == hba->clk_scaling.is_enabled)
fcb0c4b0
ST		 1548 goto out;
1549
b294ff3e 1550 ufshcd_rpm_get_sync(hba);
fcb0c4b0
ST		 1551 ufshcd_hold(hba, false);
1552
0e9d4ca4 1553 hba->clk_scaling.is_enabled = value;
401f1e44 1554
fcb0c4b0
ST		 1555 if (value) {
1556 ufshcd_resume_clkscaling(hba);
1557 } else {
1558 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1559 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1560 if (err)
1561 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1562 __func__, err);
1563 }
fcb0c4b0
ST		 1564
1565 ufshcd_release(hba);
b294ff3e 1566 ufshcd_rpm_put_sync(hba);
fcb0c4b0 1567out:
9cd20d3f
CG		 1568 up(&hba->host_sem);
1569 return err ? err : count;
a508253d
GB		 1570}
1571
4543d9d7 1572static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
a3cd5ec5 1573{
1574 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1575 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1576 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1577 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1578 hba->clk_scaling.enable_attr.attr.mode = 0644;
1579 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1580 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1581}
1582
4543d9d7
CG		 1583static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1584{
1585 if (hba->clk_scaling.enable_attr.attr.name)
1586 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1587}
1588
1589static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1590{
1591 char wq_name[sizeof("ufs_clkscaling_00")];
1592
1593 if (!ufshcd_is_clkscaling_supported(hba))
1594 return;
1595
80d892f4
CG		 1596 if (!hba->clk_scaling.min_gear)
1597 hba->clk_scaling.min_gear = UFS_HS_G1;
1598
4543d9d7
CG		 1599 INIT_WORK(&hba->clk_scaling.suspend_work,
1600 ufshcd_clk_scaling_suspend_work);
1601 INIT_WORK(&hba->clk_scaling.resume_work,
1602 ufshcd_clk_scaling_resume_work);
1603
1604 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1605 hba->host->host_no);
1606 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1607
1608 hba->clk_scaling.is_initialized = true;
1609}
1610
1611static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1612{
1613 if (!hba->clk_scaling.is_initialized)
1614 return;
1615
1616 ufshcd_remove_clk_scaling_sysfs(hba);
1617 destroy_workqueue(hba->clk_scaling.workq);
1618 ufshcd_devfreq_remove(hba);
1619 hba->clk_scaling.is_initialized = false;
1620}
1621
1ab27c9c
ST		 1622static void ufshcd_ungate_work(struct work_struct *work)
1623{
1624 int ret;
1625 unsigned long flags;
1626 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1627 clk_gating.ungate_work);
1628
1629 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1630
1631 spin_lock_irqsave(hba->host->host_lock, flags);
1632 if (hba->clk_gating.state == CLKS_ON) {
1633 spin_unlock_irqrestore(hba->host->host_lock, flags);
1634 goto unblock_reqs;
1635 }
1636
1637 spin_unlock_irqrestore(hba->host->host_lock, flags);
dd7143e2 1638 ufshcd_hba_vreg_set_hpm(hba);
1ab27c9c
ST		 1639 ufshcd_setup_clocks(hba, true);
1640
8b0bbf00
SC		 1641 ufshcd_enable_irq(hba);
1642
1ab27c9c
ST		 1643 /* Exit from hibern8 */
1644 if (ufshcd_can_hibern8_during_gating(hba)) {
1645 /* Prevent gating in this path */
1646 hba->clk_gating.is_suspended = true;
1647 if (ufshcd_is_link_hibern8(hba)) {
1648 ret = ufshcd_uic_hibern8_exit(hba);
1649 if (ret)
1650 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1651 __func__, ret);
1652 else
1653 ufshcd_set_link_active(hba);
1654 }
1655 hba->clk_gating.is_suspended = false;
1656 }
1657unblock_reqs:
38135535 1658 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1659}
1660
1661/**
1662 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1663 * Also, exit from hibern8 mode and set the link as active.
1664 * @hba: per adapter instance
1665 * @async: This indicates whether caller should ungate clocks asynchronously.
1666 */
1667int ufshcd_hold(struct ufs_hba *hba, bool async)
1668{
1669 int rc = 0;
93b6c5db 1670 bool flush_result;
1ab27c9c
ST		 1671 unsigned long flags;
1672
3489c34b
BVA		 1673 if (!ufshcd_is_clkgating_allowed(hba) ||
1674 !hba->clk_gating.is_initialized)
1ab27c9c 1675 goto out;
1ab27c9c
ST		 1676 spin_lock_irqsave(hba->host->host_lock, flags);
1677 hba->clk_gating.active_reqs++;
1678
856b3483 1679start:
1ab27c9c
ST		 1680 switch (hba->clk_gating.state) {
1681 case CLKS_ON:
f2a785ac
VG		 1682 /*
1683 * Wait for the ungate work to complete if in progress.
1684 * Though the clocks may be in ON state, the link could
1685 * still be in hibner8 state if hibern8 is allowed
1686 * during clock gating.
1687 * Make sure we exit hibern8 state also in addition to
1688 * clocks being ON.
1689 */
1690 if (ufshcd_can_hibern8_during_gating(hba) &&
1691 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1692 if (async) {
1693 rc = -EAGAIN;
1694 hba->clk_gating.active_reqs--;
1695 break;
1696 }
f2a785ac 1697 spin_unlock_irqrestore(hba->host->host_lock, flags);
93b6c5db
SC		 1698 flush_result = flush_work(&hba->clk_gating.ungate_work);
1699 if (hba->clk_gating.is_suspended && !flush_result)
1700 goto out;
f2a785ac
VG		 1701 spin_lock_irqsave(hba->host->host_lock, flags);
1702 goto start;
1703 }
1ab27c9c
ST		 1704 break;
1705 case REQ_CLKS_OFF:
1706 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1707 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1708 trace_ufshcd_clk_gating(dev_name(hba->dev),
1709 hba->clk_gating.state);
1ab27c9c
ST		 1710 break;
1711 }
1712 /*
9c490d2d 1713 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1714 * currently running. Hence, fall through to cancel gating
1715 * work and to enable clocks.
1716 */
df561f66 1717 fallthrough;
1ab27c9c 1718 case CLKS_OFF:
1ab27c9c 1719 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1720 trace_ufshcd_clk_gating(dev_name(hba->dev),
1721 hba->clk_gating.state);
da3fecb0
CG		 1722 if (queue_work(hba->clk_gating.clk_gating_workq,
1723 &hba->clk_gating.ungate_work))
1724 ufshcd_scsi_block_requests(hba);
1ab27c9c
ST		 1725 /*
1726 * fall through to check if we should wait for this
1727 * work to be done or not.
1728 */
df561f66 1729 fallthrough;
1ab27c9c
ST		 1730 case REQ_CLKS_ON:
1731 if (async) {
1732 rc = -EAGAIN;
1733 hba->clk_gating.active_reqs--;
1734 break;
1735 }
1736
1737 spin_unlock_irqrestore(hba->host->host_lock, flags);
1738 flush_work(&hba->clk_gating.ungate_work);
1739 /* Make sure state is CLKS_ON before returning */
856b3483 1740 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1741 goto start;
1742 default:
1743 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1744 __func__, hba->clk_gating.state);
1745 break;
1746 }
1747 spin_unlock_irqrestore(hba->host->host_lock, flags);
1748out:
1749 return rc;
1750}
6e3fd44d 1751EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1752
1753static void ufshcd_gate_work(struct work_struct *work)
1754{
1755 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1756 clk_gating.gate_work.work);
1757 unsigned long flags;
4db7a236 1758 int ret;
1ab27c9c
ST		 1759
1760 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1761 /*
1762 * In case you are here to cancel this work the gating state
1763 * would be marked as REQ_CLKS_ON. In this case save time by
1764 * skipping the gating work and exit after changing the clock
1765 * state to CLKS_ON.
1766 */
1767 if (hba->clk_gating.is_suspended ||
18f01374 1768 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1769 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1770 trace_ufshcd_clk_gating(dev_name(hba->dev),
1771 hba->clk_gating.state);
1ab27c9c
ST		 1772 goto rel_lock;
1773 }
1774
1775 if (hba->clk_gating.active_reqs
1776 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
bd0b3538 1777 || hba->outstanding_reqs || hba->outstanding_tasks
1ab27c9c
ST		 1778 || hba->active_uic_cmd || hba->uic_async_done)
1779 goto rel_lock;
1780
1781 spin_unlock_irqrestore(hba->host->host_lock, flags);
1782
1783 /* put the link into hibern8 mode before turning off clocks */
1784 if (ufshcd_can_hibern8_during_gating(hba)) {
4db7a236
CG		 1785 ret = ufshcd_uic_hibern8_enter(hba);
1786 if (ret) {
1ab27c9c 1787 hba->clk_gating.state = CLKS_ON;
4db7a236
CG		 1788 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1789 __func__, ret);
7ff5ab47 1790 trace_ufshcd_clk_gating(dev_name(hba->dev),
1791 hba->clk_gating.state);
1ab27c9c
ST		 1792 goto out;
1793 }
1794 ufshcd_set_link_hibern8(hba);
1795 }
1796
8b0bbf00
SC		 1797 ufshcd_disable_irq(hba);
1798
81309c24 1799 ufshcd_setup_clocks(hba, false);
1ab27c9c 1800
dd7143e2
CG		 1801 /* Put the host controller in low power mode if possible */
1802 ufshcd_hba_vreg_set_lpm(hba);
1ab27c9c
ST		 1803 /*
1804 * In case you are here to cancel this work the gating state
1805 * would be marked as REQ_CLKS_ON. In this case keep the state
1806 * as REQ_CLKS_ON which would anyway imply that clocks are off
1807 * and a request to turn them on is pending. By doing this way,
1808 * we keep the state machine in tact and this would ultimately
1809 * prevent from doing cancel work multiple times when there are
1810 * new requests arriving before the current cancel work is done.
1811 */
1812 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1813 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1814 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1815 trace_ufshcd_clk_gating(dev_name(hba->dev),
1816 hba->clk_gating.state);
1817 }
1ab27c9c
ST		 1818rel_lock:
1819 spin_unlock_irqrestore(hba->host->host_lock, flags);
1820out:
1821 return;
1822}
1823
1824/* host lock must be held before calling this variant */
1825static void __ufshcd_release(struct ufs_hba *hba)
1826{
1827 if (!ufshcd_is_clkgating_allowed(hba))
1828 return;
1829
1830 hba->clk_gating.active_reqs--;
1831
4db7a236
CG		 1832 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1833 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
3489c34b 1834 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
fd62de11
JK		 1835 hba->active_uic_cmd || hba->uic_async_done ||
1836 hba->clk_gating.state == CLKS_OFF)
1ab27c9c
ST		 1837 return;
1838
1839 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1840 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1841 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1842 &hba->clk_gating.gate_work,
1843 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1844}
1845
1846void ufshcd_release(struct ufs_hba *hba)
1847{
1848 unsigned long flags;
1849
1850 spin_lock_irqsave(hba->host->host_lock, flags);
1851 __ufshcd_release(hba);
1852 spin_unlock_irqrestore(hba->host->host_lock, flags);
1853}
6e3fd44d 1854EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1855
1856static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1857 struct device_attribute *attr, char *buf)
1858{
1859 struct ufs_hba *hba = dev_get_drvdata(dev);
1860
bafd09f8 1861 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1ab27c9c
ST		 1862}
1863
1864static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1865 struct device_attribute *attr, const char *buf, size_t count)
1866{
1867 struct ufs_hba *hba = dev_get_drvdata(dev);
1868 unsigned long flags, value;
1869
1870 if (kstrtoul(buf, 0, &value))
1871 return -EINVAL;
1872
1873 spin_lock_irqsave(hba->host->host_lock, flags);
1874 hba->clk_gating.delay_ms = value;
1875 spin_unlock_irqrestore(hba->host->host_lock, flags);
1876 return count;
1877}
1878
b427411a
ST		 1879static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1880 struct device_attribute *attr, char *buf)
1881{
1882 struct ufs_hba *hba = dev_get_drvdata(dev);
1883
bafd09f8 1884 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
b427411a
ST		 1885}
1886
1887static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1888 struct device_attribute *attr, const char *buf, size_t count)
1889{
1890 struct ufs_hba *hba = dev_get_drvdata(dev);
1891 unsigned long flags;
1892 u32 value;
1893
1894 if (kstrtou32(buf, 0, &value))
1895 return -EINVAL;
1896
1897 value = !!value;
b6645112
JK		 1898
1899 spin_lock_irqsave(hba->host->host_lock, flags);
b427411a
ST		 1900 if (value == hba->clk_gating.is_enabled)
1901 goto out;
1902
b6645112
JK		 1903 if (value)
1904 __ufshcd_release(hba);
1905 else
b427411a 1906 hba->clk_gating.active_reqs++;
b427411a
ST		 1907
1908 hba->clk_gating.is_enabled = value;
1909out:
b6645112 1910 spin_unlock_irqrestore(hba->host->host_lock, flags);
b427411a
ST		 1911 return count;
1912}
1913
4543d9d7 1914static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1915{
4543d9d7
CG		 1916 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1917 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1918 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1919 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1920 hba->clk_gating.delay_attr.attr.mode = 0644;
1921 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1922 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
eebcc196 1923
4543d9d7
CG		 1924 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1925 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1926 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1927 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1928 hba->clk_gating.enable_attr.attr.mode = 0644;
1929 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1930 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
eebcc196
VG		 1931}
1932
4543d9d7 1933static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1934{
4543d9d7
CG		 1935 if (hba->clk_gating.delay_attr.attr.name)
1936 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1937 if (hba->clk_gating.enable_attr.attr.name)
1938 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
eebcc196
VG		 1939}
1940
1ab27c9c
ST		 1941static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1942{
10e5e375
VV		 1943 char wq_name[sizeof("ufs_clk_gating_00")];
1944
1ab27c9c
ST		 1945 if (!ufshcd_is_clkgating_allowed(hba))
1946 return;
1947
2dec9475
CG		 1948 hba->clk_gating.state = CLKS_ON;
1949
1ab27c9c
ST		 1950 hba->clk_gating.delay_ms = 150;
1951 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1952 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1953
10e5e375
VV		 1954 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1955 hba->host->host_no);
1956 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
e93e6e49 1957 WQ_MEM_RECLAIM | WQ_HIGHPRI);
10e5e375 1958
4543d9d7 1959 ufshcd_init_clk_gating_sysfs(hba);
b427411a 1960
4543d9d7
CG		 1961 hba->clk_gating.is_enabled = true;
1962 hba->clk_gating.is_initialized = true;
1ab27c9c
ST		 1963}
1964
1965static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1966{
4543d9d7 1967 if (!hba->clk_gating.is_initialized)
1ab27c9c 1968 return;
3489c34b 1969
4543d9d7 1970 ufshcd_remove_clk_gating_sysfs(hba);
3489c34b
BVA		 1971
1972 /* Ungate the clock if necessary. */
1973 ufshcd_hold(hba, false);
4543d9d7 1974 hba->clk_gating.is_initialized = false;
3489c34b
BVA		 1975 ufshcd_release(hba);
1976
1977 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1978}
1979
856b3483
ST		 1980/* Must be called with host lock acquired */
1981static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1982{
401f1e44 1983 bool queue_resume_work = false;
b1bf66d1 1984 ktime_t curr_t = ktime_get();
a45f9371 1985 unsigned long flags;
401f1e44 1986
fcb0c4b0 1987 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1988 return;
1989
a45f9371 1990 spin_lock_irqsave(hba->host->host_lock, flags);
401f1e44 1991 if (!hba->clk_scaling.active_reqs++)
1992 queue_resume_work = true;
1993
a45f9371
CG		 1994 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
1995 spin_unlock_irqrestore(hba->host->host_lock, flags);
401f1e44 1996 return;
a45f9371 1997 }
401f1e44 1998
1999 if (queue_resume_work)
2000 queue_work(hba->clk_scaling.workq,
2001 &hba->clk_scaling.resume_work);
2002
2003 if (!hba->clk_scaling.window_start_t) {
b1bf66d1 2004 hba->clk_scaling.window_start_t = curr_t;
401f1e44 2005 hba->clk_scaling.tot_busy_t = 0;
2006 hba->clk_scaling.is_busy_started = false;
2007 }
2008
856b3483 2009 if (!hba->clk_scaling.is_busy_started) {
b1bf66d1 2010 hba->clk_scaling.busy_start_t = curr_t;
856b3483
ST		 2011 hba->clk_scaling.is_busy_started = true;
2012 }
a45f9371 2013 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483
ST		 2014}
2015
2016static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2017{
2018 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
a45f9371 2019 unsigned long flags;
856b3483 2020
fcb0c4b0 2021 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2022 return;
2023
a45f9371
CG		 2024 spin_lock_irqsave(hba->host->host_lock, flags);
2025 hba->clk_scaling.active_reqs--;
856b3483
ST		 2026 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2027 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2028 scaling->busy_start_t));
8b0e1953 2029 scaling->busy_start_t = 0;
856b3483
ST		 2030 scaling->is_busy_started = false;
2031 }
a45f9371 2032 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2033}
1d8613a2
CG		 2034
2035static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2036{
2037 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2038 return READ;
2039 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2040 return WRITE;
2041 else
2042 return -EINVAL;
2043}
2044
2045static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2046 struct ufshcd_lrb *lrbp)
2047{
2048 struct ufs_hba_monitor *m = &hba->monitor;
2049
2050 return (m->enabled && lrbp && lrbp->cmd &&
2051 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2052 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2053}
2054
2055static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2056{
2057 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2058 unsigned long flags;
1d8613a2 2059
a45f9371 2060 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2
CG		 2061 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2062 hba->monitor.busy_start_ts[dir] = ktime_get();
a45f9371 2063 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d8613a2
CG		 2064}
2065
2066static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2067{
2068 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2069 unsigned long flags;
1d8613a2 2070
a45f9371 2071 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2 2072 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
3f2c1002 2073 struct request *req = scsi_cmd_to_rq(lrbp->cmd);
1d8613a2
CG		 2074 struct ufs_hba_monitor *m = &hba->monitor;
2075 ktime_t now, inc, lat;
2076
2077 now = lrbp->compl_time_stamp;
2078 inc = ktime_sub(now, m->busy_start_ts[dir]);
2079 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2080 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2081
2082 /* Update latencies */
2083 m->nr_req[dir]++;
2084 lat = ktime_sub(now, lrbp->issue_time_stamp);
2085 m->lat_sum[dir] += lat;
2086 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2087 m->lat_max[dir] = lat;
2088 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2089 m->lat_min[dir] = lat;
2090
2091 m->nr_queued[dir]--;
2092 /* Push forward the busy start of monitor */
2093 m->busy_start_ts[dir] = now;
2094 }
a45f9371 2095 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2096}
1d8613a2 2097
7a3e97b0
SY		 2098/**
2099 * ufshcd_send_command - Send SCSI or device management commands
2100 * @hba: per adapter instance
2101 * @task_tag: Task tag of the command
2102 */
2103static inline
2104void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2105{
6edfdcfe 2106 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
1f522c50 2107 unsigned long flags;
6edfdcfe
SC		 2108
2109 lrbp->issue_time_stamp = ktime_get();
2110 lrbp->compl_time_stamp = ktime_set(0, 0);
28fa68fc 2111 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
856b3483 2112 ufshcd_clk_scaling_start_busy(hba);
1d8613a2
CG		 2113 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2114 ufshcd_start_monitor(hba, lrbp);
169f5eb2
BVA		 2115
2116 spin_lock_irqsave(&hba->outstanding_lock, flags);
a024ad0d
BVA		 2117 if (hba->vops && hba->vops->setup_xfer_req)
2118 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
169f5eb2 2119 __set_bit(task_tag, &hba->outstanding_reqs);
1f522c50 2120 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
169f5eb2
BVA		 2121 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2122
ad1a1b9c
GB		 2123 /* Make sure that doorbell is committed immediately */
2124 wmb();
7a3e97b0
SY		 2125}
2126
2127/**
2128 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 2129 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2130 */
2131static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2132{
2133 int len;
1c2623c5
SJ		 2134 if (lrbp->sense_buffer &&
2135 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 2136 int len_to_copy;
2137
5a0b0cb9 2138 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 2139 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 2140
09a5a24f
AA		 2141 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2142 len_to_copy);
7a3e97b0
SY		 2143 }
2144}
2145
68078d5c
DR		 2146/**
2147 * ufshcd_copy_query_response() - Copy the Query Response and the data
2148 * descriptor
2149 * @hba: per adapter instance
8aa29f19 2150 * @lrbp: pointer to local reference block
68078d5c
DR		 2151 */
2152static
c6d4a831 2153int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 2154{
2155 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2156
68078d5c 2157 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 2158
68078d5c 2159 /* Get the descriptor */
1c90836f
AA		 2160 if (hba->dev_cmd.query.descriptor &&
2161 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 2162 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 2163 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 2164 u16 resp_len;
2165 u16 buf_len;
68078d5c
DR		 2166
2167 /* data segment length */
c6d4a831 2168 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 2169 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 2170 buf_len = be16_to_cpu(
2171 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 2172 if (likely(buf_len >= resp_len)) {
2173 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2174 } else {
2175 dev_warn(hba->dev,
3d4881d1
BH		 2176 "%s: rsp size %d is bigger than buffer size %d",
2177 __func__, resp_len, buf_len);
c6d4a831
DR		 2178 return -EINVAL;
2179 }
68078d5c 2180 }
c6d4a831
DR		 2181
2182 return 0;
68078d5c
DR		 2183}
2184
7a3e97b0
SY		 2185/**
2186 * ufshcd_hba_capabilities - Read controller capabilities
2187 * @hba: per adapter instance
df043c74
ST		 2188 *
2189 * Return: 0 on success, negative on error.
7a3e97b0 2190 */
df043c74 2191static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
7a3e97b0 2192{
df043c74
ST		 2193 int err;
2194
b873a275 2195 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 2196
2197 /* nutrs and nutmrs are 0 based values */
2198 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2199 hba->nutmrs =
2200 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
945c3cca 2201 hba->reserved_slot = hba->nutrs - 1;
df043c74
ST		 2202
2203 /* Read crypto capabilities */
2204 err = ufshcd_hba_init_crypto_capabilities(hba);
2205 if (err)
2206 dev_err(hba->dev, "crypto setup failed\n");
2207
2208 return err;
7a3e97b0
SY		 2209}
2210
2211/**
6ccf44fe
SJ		 2212 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2213 * to accept UIC commands
7a3e97b0 2214 * @hba: per adapter instance
6ccf44fe
SJ		 2215 * Return true on success, else false
2216 */
2217static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2218{
2219 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2220 return true;
2221 else
2222 return false;
2223}
2224
53b3d9c3
SJ		 2225/**
2226 * ufshcd_get_upmcrs - Get the power mode change request status
2227 * @hba: Pointer to adapter instance
2228 *
2229 * This function gets the UPMCRS field of HCS register
2230 * Returns value of UPMCRS field
2231 */
2232static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2233{
2234 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2235}
2236
6ccf44fe 2237/**
35c7d874 2238 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
6ccf44fe
SJ		 2239 * @hba: per adapter instance
2240 * @uic_cmd: UIC command
7a3e97b0
SY		 2241 */
2242static inline void
6ccf44fe 2243ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2244{
35c7d874
BVA		 2245 lockdep_assert_held(&hba->uic_cmd_mutex);
2246
6ccf44fe
SJ		 2247 WARN_ON(hba->active_uic_cmd);
2248
2249 hba->active_uic_cmd = uic_cmd;
2250
7a3e97b0 2251 /* Write Args */
6ccf44fe
SJ		 2252 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2253 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2254 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0 2255
28fa68fc 2256 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
aa5c6979 2257
7a3e97b0 2258 /* Write UIC Cmd */
6ccf44fe 2259 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2260 REG_UIC_COMMAND);
7a3e97b0
SY		 2261}
2262
6ccf44fe 2263/**
35c7d874 2264 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
6ccf44fe 2265 * @hba: per adapter instance
8aa29f19 2266 * @uic_cmd: UIC command
6ccf44fe 2267 *
6ccf44fe
SJ		 2268 * Returns 0 only if success.
2269 */
2270static int
2271ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2272{
2273 int ret;
2274 unsigned long flags;
2275
35c7d874
BVA		 2276 lockdep_assert_held(&hba->uic_cmd_mutex);
2277
6ccf44fe 2278 if (wait_for_completion_timeout(&uic_cmd->done,
0f52fcb9 2279 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
6ccf44fe 2280 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
0f52fcb9 2281 } else {
6ccf44fe 2282 ret = -ETIMEDOUT;
0f52fcb9
CG		 2283 dev_err(hba->dev,
2284 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2285 uic_cmd->command, uic_cmd->argument3);
2286
2287 if (!uic_cmd->cmd_active) {
2288 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2289 __func__);
2290 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2291 }
2292 }
6ccf44fe
SJ		 2293
2294 spin_lock_irqsave(hba->host->host_lock, flags);
2295 hba->active_uic_cmd = NULL;
2296 spin_unlock_irqrestore(hba->host->host_lock, flags);
2297
2298 return ret;
2299}
2300
2301/**
2302 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2303 * @hba: per adapter instance
2304 * @uic_cmd: UIC command
d75f7fe4 2305 * @completion: initialize the completion only if this is set to true
6ccf44fe 2306 *
6ccf44fe
SJ		 2307 * Returns 0 only if success.
2308 */
2309static int
d75f7fe4
YG		 2310__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2311 bool completion)
6ccf44fe 2312{
35c7d874
BVA		 2313 lockdep_assert_held(&hba->uic_cmd_mutex);
2314 lockdep_assert_held(hba->host->host_lock);
2315
6ccf44fe
SJ		 2316 if (!ufshcd_ready_for_uic_cmd(hba)) {
2317 dev_err(hba->dev,
2318 "Controller not ready to accept UIC commands\n");
2319 return -EIO;
2320 }
2321
d75f7fe4
YG		 2322 if (completion)
2323 init_completion(&uic_cmd->done);
6ccf44fe 2324
0f52fcb9 2325 uic_cmd->cmd_active = 1;
6ccf44fe 2326 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2327
57d104c1 2328 return 0;
6ccf44fe
SJ		 2329}
2330
2331/**
2332 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2333 * @hba: per adapter instance
2334 * @uic_cmd: UIC command
2335 *
2336 * Returns 0 only if success.
2337 */
e77044c5 2338int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2339{
2340 int ret;
57d104c1 2341 unsigned long flags;
6ccf44fe 2342
a22bcfdb 2343 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2344 return 0;
2345
1ab27c9c 2346 ufshcd_hold(hba, false);
6ccf44fe 2347 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2348 ufshcd_add_delay_before_dme_cmd(hba);
2349
57d104c1 2350 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2351 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2352 spin_unlock_irqrestore(hba->host->host_lock, flags);
2353 if (!ret)
2354 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2355
6ccf44fe
SJ		 2356 mutex_unlock(&hba->uic_cmd_mutex);
2357
1ab27c9c 2358 ufshcd_release(hba);
6ccf44fe
SJ		 2359 return ret;
2360}
2361
7a3e97b0
SY		 2362/**
2363 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2364 * @hba: per adapter instance
2365 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2366 *
2367 * Returns 0 in case of success, non-zero value in case of failure
2368 */
75b1cc4a 2369static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2370{
2371 struct ufshcd_sg_entry *prd_table;
2372 struct scatterlist *sg;
2373 struct scsi_cmnd *cmd;
2374 int sg_segments;
2375 int i;
2376
2377 cmd = lrbp->cmd;
2378 sg_segments = scsi_dma_map(cmd);
2379 if (sg_segments < 0)
2380 return sg_segments;
2381
2382 if (sg_segments) {
26f968d7
AA		 2383
2384 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2385 lrbp->utr_descriptor_ptr->prd_table_length =
2386 cpu_to_le16((sg_segments *
2387 sizeof(struct ufshcd_sg_entry)));
2388 else
2389 lrbp->utr_descriptor_ptr->prd_table_length =
3ad317a1 2390 cpu_to_le16(sg_segments);
7a3e97b0 2391
3ad317a1 2392 prd_table = lrbp->ucd_prdt_ptr;
7a3e97b0
SY		 2393
2394 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1ea7d802
BVA		 2395 const unsigned int len = sg_dma_len(sg);
2396
2397 /*
2398 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2399 * based value that indicates the length, in bytes, of
2400 * the data block. A maximum of length of 256KB may
2401 * exist for any entry. Bits 1:0 of this field shall be
2402 * 11b to indicate Dword granularity. A value of '3'
2403 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2404 */
2405 WARN_ONCE(len > 256 * 1024, "len = %#x\n", len);
2406 prd_table[i].size = cpu_to_le32(len - 1);
2407 prd_table[i].addr = cpu_to_le64(sg->dma_address);
52ac95fe 2408 prd_table[i].reserved = 0;
7a3e97b0
SY		 2409 }
2410 } else {
2411 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2412 }
2413
2414 return 0;
2415}
2416
2417/**
2fbd009b 2418 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2419 * @hba: per adapter instance
2fbd009b 2420 * @intrs: interrupt bits
7a3e97b0 2421 */
2fbd009b 2422static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2423{
2fbd009b
SJ		 2424 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2425
51428818 2426 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2427 u32 rw;
2428 rw = set & INTERRUPT_MASK_RW_VER_10;
2429 set = rw | ((set ^ intrs) & intrs);
2430 } else {
2431 set |= intrs;
2432 }
2433
2434 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2435}
2436
2437/**
2438 * ufshcd_disable_intr - disable interrupts
2439 * @hba: per adapter instance
2440 * @intrs: interrupt bits
2441 */
2442static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2443{
2444 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2445
51428818 2446 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2447 u32 rw;
2448 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2449 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2450 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2451
2452 } else {
2453 set &= ~intrs;
7a3e97b0 2454 }
2fbd009b
SJ		 2455
2456 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2457}
2458
5a0b0cb9
SRT		 2459/**
2460 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2461 * descriptor according to request
2462 * @lrbp: pointer to local reference block
2463 * @upiu_flags: flags required in the header
2464 * @cmd_dir: requests data direction
2465 */
2466static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
a23064c4 2467 u8 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2468{
2469 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2470 u32 data_direction;
2471 u32 dword_0;
df043c74
ST		 2472 u32 dword_1 = 0;
2473 u32 dword_3 = 0;
5a0b0cb9
SRT		 2474
2475 if (cmd_dir == DMA_FROM_DEVICE) {
2476 data_direction = UTP_DEVICE_TO_HOST;
2477 *upiu_flags = UPIU_CMD_FLAGS_READ;
2478 } else if (cmd_dir == DMA_TO_DEVICE) {
2479 data_direction = UTP_HOST_TO_DEVICE;
2480 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2481 } else {
2482 data_direction = UTP_NO_DATA_TRANSFER;
2483 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2484 }
2485
2486 dword_0 = data_direction | (lrbp->command_type
2487 << UPIU_COMMAND_TYPE_OFFSET);
2488 if (lrbp->intr_cmd)
2489 dword_0 |= UTP_REQ_DESC_INT_CMD;
2490
df043c74
ST		 2491 /* Prepare crypto related dwords */
2492 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2493
5a0b0cb9
SRT		 2494 /* Transfer request descriptor header fields */
2495 req_desc->header.dword_0 = cpu_to_le32(dword_0);
df043c74 2496 req_desc->header.dword_1 = cpu_to_le32(dword_1);
5a0b0cb9
SRT		 2497 /*
2498 * assigning invalid value for command status. Controller
2499 * updates OCS on command completion, with the command
2500 * status
2501 */
2502 req_desc->header.dword_2 =
2503 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
df043c74 2504 req_desc->header.dword_3 = cpu_to_le32(dword_3);
51047266
YG		 2505
2506 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2507}
2508
2509/**
2510 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2511 * for scsi commands
8aa29f19
BVA		 2512 * @lrbp: local reference block pointer
2513 * @upiu_flags: flags
5a0b0cb9
SRT		 2514 */
2515static
a23064c4 2516void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
5a0b0cb9 2517{
1b21b8f0 2518 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2519 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2520 unsigned short cdb_len;
5a0b0cb9
SRT		 2521
2522 /* command descriptor fields */
2523 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2524 UPIU_TRANSACTION_COMMAND, upiu_flags,
2525 lrbp->lun, lrbp->task_tag);
2526 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2527 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2528
2529 /* Total EHS length and Data segment length will be zero */
2530 ucd_req_ptr->header.dword_2 = 0;
2531
1b21b8f0 2532 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2533
1b21b8f0 2534 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2535 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2536 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2537
2538 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2539}
2540
68078d5c
DR		 2541/**
2542 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2543 * for query requsts
2544 * @hba: UFS hba
2545 * @lrbp: local reference block pointer
2546 * @upiu_flags: flags
2547 */
2548static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
a23064c4 2549 struct ufshcd_lrb *lrbp, u8 upiu_flags)
68078d5c
DR		 2550{
2551 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2552 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2553 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2554
2555 /* Query request header */
2556 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2557 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2558 lrbp->lun, lrbp->task_tag);
2559 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2560 0, query->request.query_func, 0, 0);
2561
6861285c
ZL		 2562 /* Data segment length only need for WRITE_DESC */
2563 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2564 ucd_req_ptr->header.dword_2 =
2565 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2566 else
2567 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2568
2569 /* Copy the Query Request buffer as is */
2570 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2571 QUERY_OSF_SIZE);
68078d5c
DR		 2572
2573 /* Copy the Descriptor */
c6d4a831 2574 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2575 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2576
51047266 2577 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2578}
2579
5a0b0cb9
SRT		 2580static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2581{
2582 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2583
2584 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2585
2586 /* command descriptor fields */
2587 ucd_req_ptr->header.dword_0 =
2588 UPIU_HEADER_DWORD(
2589 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2590 /* clear rest of the fields of basic header */
2591 ucd_req_ptr->header.dword_1 = 0;
2592 ucd_req_ptr->header.dword_2 = 0;
2593
2594 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2595}
2596
7a3e97b0 2597/**
f273c54b 2598 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
300bb13f 2599 * for Device Management Purposes
8aa29f19
BVA		 2600 * @hba: per adapter instance
2601 * @lrbp: pointer to local reference block
7a3e97b0 2602 */
f273c54b
BH		 2603static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2604 struct ufshcd_lrb *lrbp)
7a3e97b0 2605{
a23064c4 2606 u8 upiu_flags;
5a0b0cb9 2607 int ret = 0;
7a3e97b0 2608
51428818 2609 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2610 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2611 else
2612 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2613
2614 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2615 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2616 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2617 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2618 ufshcd_prepare_utp_nop_upiu(lrbp);
2619 else
2620 ret = -EINVAL;
2621
2622 return ret;
2623}
2624
2625/**
2626 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2627 * for SCSI Purposes
8aa29f19
BVA		 2628 * @hba: per adapter instance
2629 * @lrbp: pointer to local reference block
300bb13f
JP		 2630 */
2631static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2632{
a23064c4 2633 u8 upiu_flags;
300bb13f
JP		 2634 int ret = 0;
2635
51428818 2636 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2637 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2638 else
2639 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2640
2641 if (likely(lrbp->cmd)) {
2642 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2643 lrbp->cmd->sc_data_direction);
2644 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2645 } else {
2646 ret = -EINVAL;
2647 }
5a0b0cb9
SRT		 2648
2649 return ret;
7a3e97b0
SY		 2650}
2651
2a8fa600
SJ		 2652/**
2653 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2654 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2655 *
2656 * Returns SCSI W-LUN id
2657 */
2658static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2659{
2660 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2661}
2662
b294ff3e
AD		 2663static inline bool is_device_wlun(struct scsi_device *sdev)
2664{
2665 return sdev->lun ==
2666 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2667}
2668
eaab9b57
BVA		 2669/*
2670 * Associate the UFS controller queue with the default and poll HCTX types.
2671 * Initialize the mq_map[] arrays.
2672 */
2673static int ufshcd_map_queues(struct Scsi_Host *shost)
2674{
2675 int i, ret;
2676
2677 for (i = 0; i < shost->nr_maps; i++) {
2678 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2679
2680 switch (i) {
2681 case HCTX_TYPE_DEFAULT:
2682 case HCTX_TYPE_POLL:
2683 map->nr_queues = 1;
2684 break;
2685 case HCTX_TYPE_READ:
2686 map->nr_queues = 0;
10af1156 2687 continue;
eaab9b57
BVA		 2688 default:
2689 WARN_ON_ONCE(true);
2690 }
2691 map->queue_offset = 0;
2692 ret = blk_mq_map_queues(map);
2693 WARN_ON_ONCE(ret);
2694 }
2695
2696 return 0;
2697}
2698
4d2b8d40
BVA		 2699static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2700{
2701 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2702 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2703 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2704 i * sizeof(struct utp_transfer_cmd_desc);
2705 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2706 response_upiu);
2707 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2708
2709 lrb->utr_descriptor_ptr = utrdlp + i;
2710 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2711 i * sizeof(struct utp_transfer_req_desc);
2712 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2713 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2714 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2715 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
3ad317a1 2716 lrb->ucd_prdt_ptr = cmd_descp[i].prd_table;
4d2b8d40
BVA		 2717 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2718}
2719
7a3e97b0
SY		 2720/**
2721 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2722 * @host: SCSI host pointer
7a3e97b0 2723 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2724 *
2725 * Returns 0 for success, non-zero in case of failure
2726 */
2727static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2728{
4728ab4a 2729 struct ufs_hba *hba = shost_priv(host);
3f2c1002 2730 int tag = scsi_cmd_to_rq(cmd)->tag;
7a3e97b0 2731 struct ufshcd_lrb *lrbp;
7a3e97b0
SY		 2732 int err = 0;
2733
eaab9b57 2734 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
7a3e97b0 2735
5675c381
BVA		 2736 /*
2737 * Allows the UFS error handler to wait for prior ufshcd_queuecommand()
2738 * calls.
2739 */
2740 rcu_read_lock();
2741
a45f9371
CG		 2742 switch (hba->ufshcd_state) {
2743 case UFSHCD_STATE_OPERATIONAL:
d489f18a 2744 break;
a45f9371 2745 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
d489f18a
AH		 2746 /*
2747 * SCSI error handler can call ->queuecommand() while UFS error
2748 * handler is in progress. Error interrupts could change the
2749 * state from UFSHCD_STATE_RESET to
2750 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2751 * being issued in that case.
2752 */
2753 if (ufshcd_eh_in_progress(hba)) {
2754 err = SCSI_MLQUEUE_HOST_BUSY;
2755 goto out;
2756 }
a45f9371
CG		 2757 break;
2758 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2759 /*
2760 * pm_runtime_get_sync() is used at error handling preparation
2761 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2762 * PM ops, it can never be finished if we let SCSI layer keep
2763 * retrying it, which gets err handler stuck forever. Neither
2764 * can we let the scsi cmd pass through, because UFS is in bad
2765 * state, the scsi cmd may eventually time out, which will get
2766 * err handler blocked for too long. So, just fail the scsi cmd
2767 * sent from PM ops, err handler can recover PM error anyways.
2768 */
2769 if (hba->pm_op_in_progress) {
2770 hba->force_reset = true;
2771 set_host_byte(cmd, DID_BAD_TARGET);
35c3730a 2772 scsi_done(cmd);
a45f9371
CG		 2773 goto out;
2774 }
2775 fallthrough;
2776 case UFSHCD_STATE_RESET:
2777 err = SCSI_MLQUEUE_HOST_BUSY;
2778 goto out;
2779 case UFSHCD_STATE_ERROR:
2780 set_host_byte(cmd, DID_ERROR);
35c3730a 2781 scsi_done(cmd);
a45f9371 2782 goto out;
a45f9371
CG		 2783 }
2784
7fabb77b
GB		 2785 hba->req_abort_count = 0;
2786
1ab27c9c
ST		 2787 err = ufshcd_hold(hba, true);
2788 if (err) {
2789 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2790 goto out;
2791 }
2dec9475
CG		 2792 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2793 (hba->clk_gating.state != CLKS_ON));
1ab27c9c 2794
a45f9371 2795 lrbp = &hba->lrb[tag];
5a0b0cb9 2796 WARN_ON(lrbp->cmd);
7a3e97b0 2797 lrbp->cmd = cmd;
09a5a24f 2798 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2799 lrbp->sense_buffer = cmd->sense_buffer;
2800 lrbp->task_tag = tag;
0ce147d4 2801 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
51d1628f 2802 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
df043c74 2803
3f2c1002 2804 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
df043c74 2805
e0b299e3 2806 lrbp->req_abort_skip = false;
7a3e97b0 2807
09d9e4d0 2808 ufshpb_prep(hba, lrbp);
2fff76f8 2809
300bb13f
JP		 2810 ufshcd_comp_scsi_upiu(hba, lrbp);
2811
75b1cc4a 2812 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2813 if (err) {
2814 lrbp->cmd = NULL;
17c7d35f 2815 ufshcd_release(hba);
7a3e97b0 2816 goto out;
5a0b0cb9 2817 }
7a3e97b0 2818
7a3e97b0 2819 ufshcd_send_command(hba, tag);
5675c381 2820
7a3e97b0 2821out:
5675c381
BVA		 2822 rcu_read_unlock();
2823
88b09900
AH		 2824 if (ufs_trigger_eh()) {
2825 unsigned long flags;
2826
2827 spin_lock_irqsave(hba->host->host_lock, flags);
2828 ufshcd_schedule_eh_work(hba);
2829 spin_unlock_irqrestore(hba->host->host_lock, flags);
2830 }
c11a1ae9 2831
7a3e97b0
SY		 2832 return err;
2833}
2834
5a0b0cb9
SRT		 2835static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2836 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2837{
2838 lrbp->cmd = NULL;
2839 lrbp->sense_bufflen = 0;
2840 lrbp->sense_buffer = NULL;
2841 lrbp->task_tag = tag;
2842 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9 2843 lrbp->intr_cmd = true; /* No interrupt aggregation */
df043c74 2844 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5a0b0cb9
SRT		 2845 hba->dev_cmd.type = cmd_type;
2846
f273c54b 2847 return ufshcd_compose_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2848}
2849
2850static int
2851ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2852{
2853 int err = 0;
2854 unsigned long flags;
2855 u32 mask = 1 << tag;
2856
2857 /* clear outstanding transaction before retry */
2858 spin_lock_irqsave(hba->host->host_lock, flags);
2859 ufshcd_utrl_clear(hba, tag);
2860 spin_unlock_irqrestore(hba->host->host_lock, flags);
2861
2862 /*
32424902 2863 * wait for h/w to clear corresponding bit in door-bell.
5a0b0cb9
SRT		 2864 * max. wait is 1 sec.
2865 */
2866 err = ufshcd_wait_for_register(hba,
2867 REG_UTP_TRANSFER_REQ_DOOR_BELL,
5cac1095 2868 mask, ~mask, 1000, 1000);
5a0b0cb9
SRT		 2869
2870 return err;
2871}
2872
c6d4a831
DR		 2873static int
2874ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2875{
2876 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2877
2878 /* Get the UPIU response */
2879 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2880 UPIU_RSP_CODE_OFFSET;
2881 return query_res->response;
2882}
2883
5a0b0cb9
SRT		 2884/**
2885 * ufshcd_dev_cmd_completion() - handles device management command responses
2886 * @hba: per adapter instance
2887 * @lrbp: pointer to local reference block
2888 */
2889static int
2890ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2891{
2892 int resp;
2893 int err = 0;
2894
ff8e20c6 2895 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2896 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2897
2898 switch (resp) {
2899 case UPIU_TRANSACTION_NOP_IN:
2900 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2901 err = -EINVAL;
2902 dev_err(hba->dev, "%s: unexpected response %x\n",
2903 __func__, resp);
2904 }
2905 break;
68078d5c 2906 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2907 err = ufshcd_check_query_response(hba, lrbp);
2908 if (!err)
2909 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2910 break;
5a0b0cb9
SRT		 2911 case UPIU_TRANSACTION_REJECT_UPIU:
2912 /* TODO: handle Reject UPIU Response */
2913 err = -EPERM;
2914 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2915 __func__);
2916 break;
2917 default:
2918 err = -EINVAL;
2919 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2920 __func__, resp);
2921 break;
2922 }
2923
2924 return err;
2925}
2926
2927static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2928 struct ufshcd_lrb *lrbp, int max_timeout)
2929{
2930 int err = 0;
2931 unsigned long time_left;
2932 unsigned long flags;
2933
2934 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2935 msecs_to_jiffies(max_timeout));
2936
2937 spin_lock_irqsave(hba->host->host_lock, flags);
2938 hba->dev_cmd.complete = NULL;
2939 if (likely(time_left)) {
2940 err = ufshcd_get_tr_ocs(lrbp);
2941 if (!err)
2942 err = ufshcd_dev_cmd_completion(hba, lrbp);
2943 }
2944 spin_unlock_irqrestore(hba->host->host_lock, flags);
2945
2946 if (!time_left) {
2947 err = -ETIMEDOUT;
a48353f6
YG		 2948 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2949 __func__, lrbp->task_tag);
5a0b0cb9 2950 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2951 /* successfully cleared the command, retry if needed */
5a0b0cb9 2952 err = -EAGAIN;
a48353f6
YG		 2953 /*
2954 * in case of an error, after clearing the doorbell,
2955 * we also need to clear the outstanding_request
2956 * field in hba
2957 */
169f5eb2
BVA		 2958 spin_lock_irqsave(&hba->outstanding_lock, flags);
2959 __clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2960 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5a0b0cb9
SRT		 2961 }
2962
2963 return err;
2964}
2965
5a0b0cb9
SRT		 2966/**
2967 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2968 * @hba: UFS hba
2969 * @cmd_type: specifies the type (NOP, Query...)
d0b2b70e 2970 * @timeout: timeout in milliseconds
5a0b0cb9 2971 *
68078d5c
DR		 2972 * NOTE: Since there is only one available tag for device management commands,
2973 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2974 */
2975static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2976 enum dev_cmd_type cmd_type, int timeout)
2977{
8a686f26 2978 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 2979 const u32 tag = hba->reserved_slot;
5a0b0cb9
SRT		 2980 struct ufshcd_lrb *lrbp;
2981 int err;
5a0b0cb9 2982
945c3cca
BVA		 2983 /* Protects use of hba->reserved_slot. */
2984 lockdep_assert_held(&hba->dev_cmd.lock);
a3cd5ec5 2985
945c3cca 2986 down_read(&hba->clk_scaling_lock);
5a0b0cb9 2987
a45f9371 2988 lrbp = &hba->lrb[tag];
5a0b0cb9
SRT		 2989 WARN_ON(lrbp->cmd);
2990 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2991 if (unlikely(err))
eb783bb8 2992 goto out;
5a0b0cb9
SRT		 2993
2994 hba->dev_cmd.complete = &wait;
2995
fb475b74 2996 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5a0b0cb9 2997
a45f9371 2998 ufshcd_send_command(hba, tag);
5a0b0cb9 2999 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
fb475b74
AA		 3000 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3001 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6667e6d9 3002
eb783bb8 3003out:
a3cd5ec5 3004 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 3005 return err;
3006}
3007
d44a5f98
DR		 3008/**
3009 * ufshcd_init_query() - init the query response and request parameters
3010 * @hba: per-adapter instance
3011 * @request: address of the request pointer to be initialized
3012 * @response: address of the response pointer to be initialized
3013 * @opcode: operation to perform
3014 * @idn: flag idn to access
3015 * @index: LU number to access
3016 * @selector: query/flag/descriptor further identification
3017 */
3018static inline void ufshcd_init_query(struct ufs_hba *hba,
3019 struct ufs_query_req **request, struct ufs_query_res **response,
3020 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3021{
3022 *request = &hba->dev_cmd.query.request;
3023 *response = &hba->dev_cmd.query.response;
3024 memset(*request, 0, sizeof(struct ufs_query_req));
3025 memset(*response, 0, sizeof(struct ufs_query_res));
3026 (*request)->upiu_req.opcode = opcode;
3027 (*request)->upiu_req.idn = idn;
3028 (*request)->upiu_req.index = index;
3029 (*request)->upiu_req.selector = selector;
3030}
3031
dc3c8d3a 3032static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1f34eedf 3033 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
dc3c8d3a
YG		 3034{
3035 int ret;
3036 int retries;
3037
3038 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1f34eedf 3039 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
dc3c8d3a
YG		 3040 if (ret)
3041 dev_dbg(hba->dev,
3042 "%s: failed with error %d, retries %d\n",
3043 __func__, ret, retries);
3044 else
3045 break;
3046 }
3047
3048 if (ret)
3049 dev_err(hba->dev,
3050 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3051 __func__, opcode, idn, ret, retries);
3052 return ret;
3053}
3054
68078d5c
DR		 3055/**
3056 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 3057 * @hba: per-adapter instance
3058 * @opcode: flag query to perform
3059 * @idn: flag idn to access
1f34eedf 3060 * @index: flag index to access
8aa29f19 3061 * @flag_res: the flag value after the query request completes
68078d5c
DR		 3062 *
3063 * Returns 0 for success, non-zero in case of failure
3064 */
dc3c8d3a 3065int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 3066 enum flag_idn idn, u8 index, bool *flag_res)
68078d5c 3067{
d44a5f98
DR		 3068 struct ufs_query_req *request = NULL;
3069 struct ufs_query_res *response = NULL;
1f34eedf 3070 int err, selector = 0;
e5ad406c 3071 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 3072
3073 BUG_ON(!hba);
3074
1ab27c9c 3075 ufshcd_hold(hba, false);
68078d5c 3076 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3077 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3078 selector);
68078d5c
DR		 3079
3080 switch (opcode) {
3081 case UPIU_QUERY_OPCODE_SET_FLAG:
3082 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3083 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3084 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3085 break;
3086 case UPIU_QUERY_OPCODE_READ_FLAG:
3087 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3088 if (!flag_res) {
3089 /* No dummy reads */
3090 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3091 __func__);
3092 err = -EINVAL;
3093 goto out_unlock;
3094 }
3095 break;
3096 default:
3097 dev_err(hba->dev,
3098 "%s: Expected query flag opcode but got = %d\n",
3099 __func__, opcode);
3100 err = -EINVAL;
3101 goto out_unlock;
3102 }
68078d5c 3103
e5ad406c 3104 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 3105
3106 if (err) {
3107 dev_err(hba->dev,
3108 "%s: Sending flag query for idn %d failed, err = %d\n",
3109 __func__, idn, err);
3110 goto out_unlock;
3111 }
3112
3113 if (flag_res)
e8c8e82a 3114 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 3115 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3116
3117out_unlock:
3118 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3119 ufshcd_release(hba);
68078d5c
DR		 3120 return err;
3121}
3122
66ec6d59
SRT		 3123/**
3124 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 3125 * @hba: per-adapter instance
3126 * @opcode: attribute opcode
3127 * @idn: attribute idn to access
3128 * @index: index field
3129 * @selector: selector field
3130 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 3131 *
3132 * Returns 0 for success, non-zero in case of failure
3133*/
ec92b59c
SN		 3134int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3135 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 3136{
d44a5f98
DR		 3137 struct ufs_query_req *request = NULL;
3138 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 3139 int err;
3140
3141 BUG_ON(!hba);
3142
3143 if (!attr_val) {
3144 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3145 __func__, opcode);
8ca1a40b 3146 return -EINVAL;
66ec6d59
SRT		 3147 }
3148
8ca1a40b 3149 ufshcd_hold(hba, false);
3150
66ec6d59 3151 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3152 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3153 selector);
66ec6d59
SRT		 3154
3155 switch (opcode) {
3156 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3157 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 3158 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 3159 break;
3160 case UPIU_QUERY_OPCODE_READ_ATTR:
3161 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3162 break;
3163 default:
3164 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3165 __func__, opcode);
3166 err = -EINVAL;
3167 goto out_unlock;
3168 }
3169
d44a5f98 3170 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 3171
3172 if (err) {
4b761b58
YG		 3173 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3174 __func__, opcode, idn, index, err);
66ec6d59
SRT		 3175 goto out_unlock;
3176 }
3177
e8c8e82a 3178 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 3179
3180out_unlock:
3181 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3182 ufshcd_release(hba);
66ec6d59
SRT		 3183 return err;
3184}
3185
5e86ae44
YG		 3186/**
3187 * ufshcd_query_attr_retry() - API function for sending query
3188 * attribute with retries
3189 * @hba: per-adapter instance
3190 * @opcode: attribute opcode
3191 * @idn: attribute idn to access
3192 * @index: index field
3193 * @selector: selector field
3194 * @attr_val: the attribute value after the query request
3195 * completes
3196 *
3197 * Returns 0 for success, non-zero in case of failure
3198*/
41d8a933 3199int ufshcd_query_attr_retry(struct ufs_hba *hba,
5e86ae44
YG		 3200 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3201 u32 *attr_val)
3202{
3203 int ret = 0;
3204 u32 retries;
3205
68c9fcfd 3206 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 3207 ret = ufshcd_query_attr(hba, opcode, idn, index,
3208 selector, attr_val);
3209 if (ret)
3210 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3211 __func__, ret, retries);
3212 else
3213 break;
3214 }
3215
3216 if (ret)
3217 dev_err(hba->dev,
3218 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3219 __func__, idn, ret, QUERY_REQ_RETRIES);
3220 return ret;
3221}
3222
a70e91b8 3223static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 3224 enum query_opcode opcode, enum desc_idn idn, u8 index,
3225 u8 selector, u8 *desc_buf, int *buf_len)
3226{
3227 struct ufs_query_req *request = NULL;
3228 struct ufs_query_res *response = NULL;
3229 int err;
3230
3231 BUG_ON(!hba);
3232
3233 if (!desc_buf) {
3234 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3235 __func__, opcode);
8ca1a40b 3236 return -EINVAL;
d44a5f98
DR		 3237 }
3238
a4b0e8a4 3239 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 3240 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3241 __func__, *buf_len);
8ca1a40b 3242 return -EINVAL;
d44a5f98
DR		 3243 }
3244
8ca1a40b 3245 ufshcd_hold(hba, false);
3246
d44a5f98
DR		 3247 mutex_lock(&hba->dev_cmd.lock);
3248 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3249 selector);
3250 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3251 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3252
3253 switch (opcode) {
3254 case UPIU_QUERY_OPCODE_WRITE_DESC:
3255 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3256 break;
3257 case UPIU_QUERY_OPCODE_READ_DESC:
3258 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3259 break;
3260 default:
3261 dev_err(hba->dev,
3262 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3263 __func__, opcode);
3264 err = -EINVAL;
3265 goto out_unlock;
3266 }
3267
3268 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3269
3270 if (err) {
4b761b58
YG		 3271 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3272 __func__, opcode, idn, index, err);
d44a5f98
DR		 3273 goto out_unlock;
3274 }
3275
ea2aab24 3276 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3277
3278out_unlock:
cfcbae38 3279 hba->dev_cmd.query.descriptor = NULL;
d44a5f98 3280 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3281 ufshcd_release(hba);
d44a5f98
DR		 3282 return err;
3283}
3284
a70e91b8 3285/**
8aa29f19
BVA		 3286 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3287 * @hba: per-adapter instance
3288 * @opcode: attribute opcode
3289 * @idn: attribute idn to access
3290 * @index: index field
3291 * @selector: selector field
3292 * @desc_buf: the buffer that contains the descriptor
3293 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3294 *
3295 * Returns 0 for success, non-zero in case of failure.
3296 * The buf_len parameter will contain, on return, the length parameter
3297 * received on the response.
3298 */
2238d31c
SN		 3299int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3300 enum query_opcode opcode,
3301 enum desc_idn idn, u8 index,
3302 u8 selector,
3303 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3304{
3305 int err;
3306 int retries;
3307
3308 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3309 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3310 selector, desc_buf, buf_len);
3311 if (!err || err == -EINVAL)
3312 break;
3313 }
3314
3315 return err;
3316}
a70e91b8 3317
a4b0e8a4
PM		 3318/**
3319 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3320 * @hba: Pointer to adapter instance
3321 * @desc_id: descriptor idn value
3322 * @desc_len: mapped desc length (out)
a4b0e8a4 3323 */
7a0bf85b
BH		 3324void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3325 int *desc_len)
a4b0e8a4 3326{
7a0bf85b
BH		 3327 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3328 desc_id == QUERY_DESC_IDN_RFU_1)
a4b0e8a4 3329 *desc_len = 0;
7a0bf85b
BH		 3330 else
3331 *desc_len = hba->desc_size[desc_id];
a4b0e8a4
PM		 3332}
3333EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3334
7a0bf85b 3335static void ufshcd_update_desc_length(struct ufs_hba *hba,
72fb690e 3336 enum desc_idn desc_id, int desc_index,
7a0bf85b
BH		 3337 unsigned char desc_len)
3338{
3339 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
72fb690e
BH		 3340 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3341 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3342 * than the RPMB unit, however, both descriptors share the same
3343 * desc_idn, to cover both unit descriptors with one length, we
3344 * choose the normal unit descriptor length by desc_index.
3345 */
7a0bf85b
BH		 3346 hba->desc_size[desc_id] = desc_len;
3347}
3348
da461cec
SJ		 3349/**
3350 * ufshcd_read_desc_param - read the specified descriptor parameter
3351 * @hba: Pointer to adapter instance
3352 * @desc_id: descriptor idn value
3353 * @desc_index: descriptor index
3354 * @param_offset: offset of the parameter to read
3355 * @param_read_buf: pointer to buffer where parameter would be read
3356 * @param_size: sizeof(param_read_buf)
3357 *
3358 * Return 0 in case of success, non-zero otherwise
3359 */
45bced87
SN		 3360int ufshcd_read_desc_param(struct ufs_hba *hba,
3361 enum desc_idn desc_id,
3362 int desc_index,
3363 u8 param_offset,
3364 u8 *param_read_buf,
3365 u8 param_size)
da461cec
SJ		 3366{
3367 int ret;
3368 u8 *desc_buf;
a4b0e8a4 3369 int buff_len;
da461cec
SJ		 3370 bool is_kmalloc = true;
3371
a4b0e8a4
PM		 3372 /* Safety check */
3373 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3374 return -EINVAL;
3375
7a0bf85b
BH		 3376 /* Get the length of descriptor */
3377 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3378 if (!buff_len) {
1699f980
CG		 3379 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3380 return -EINVAL;
3381 }
3382
3383 if (param_offset >= buff_len) {
3384 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3385 __func__, param_offset, desc_id, buff_len);
7a0bf85b 3386 return -EINVAL;
a4b0e8a4
PM		 3387 }
3388
3389 /* Check whether we need temp memory */
3390 if (param_offset != 0 || param_size < buff_len) {
1699f980 3391 desc_buf = kzalloc(buff_len, GFP_KERNEL);
da461cec
SJ		 3392 if (!desc_buf)
3393 return -ENOMEM;
a4b0e8a4
PM		 3394 } else {
3395 desc_buf = param_read_buf;
3396 is_kmalloc = false;
da461cec
SJ		 3397 }
3398
a4b0e8a4 3399 /* Request for full descriptor */
a70e91b8 3400 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3401 desc_id, desc_index, 0,
3402 desc_buf, &buff_len);
da461cec 3403
bde44bb6 3404 if (ret) {
1699f980 3405 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
bde44bb6 3406 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3407 goto out;
3408 }
3409
bde44bb6 3410 /* Sanity check */
3411 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1699f980 3412 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
bde44bb6 3413 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3414 ret = -EINVAL;
3415 goto out;
3416 }
3417
7a0bf85b
BH		 3418 /* Update descriptor length */
3419 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
72fb690e 3420 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
7a0bf85b 3421
1699f980
CG		 3422 if (is_kmalloc) {
3423 /* Make sure we don't copy more data than available */
d3d9c457
BVA		 3424 if (param_offset >= buff_len)
3425 ret = -EINVAL;
3426 else
3427 memcpy(param_read_buf, &desc_buf[param_offset],
3428 min_t(u32, param_size, buff_len - param_offset));
1699f980 3429 }
da461cec
SJ		 3430out:
3431 if (is_kmalloc)
3432 kfree(desc_buf);
3433 return ret;
3434}
3435
4b828fe1
TW		 3436/**
3437 * struct uc_string_id - unicode string
3438 *
3439 * @len: size of this descriptor inclusive
3440 * @type: descriptor type
3441 * @uc: unicode string character
3442 */
3443struct uc_string_id {
3444 u8 len;
3445 u8 type;
ec38c0ad 3446 wchar_t uc[];
4b828fe1
TW		 3447} __packed;
3448
3449/* replace non-printable or non-ASCII characters with spaces */
3450static inline char ufshcd_remove_non_printable(u8 ch)
3451{
3452 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3453}
3454
b573d484
YG		 3455/**
3456 * ufshcd_read_string_desc - read string descriptor
3457 * @hba: pointer to adapter instance
3458 * @desc_index: descriptor index
4b828fe1
TW		 3459 * @buf: pointer to buffer where descriptor would be read,
3460 * the caller should free the memory.
b573d484 3461 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3462 * null terminated string.
b573d484 3463 *
4b828fe1
TW		 3464 * Return:
3465 * * string size on success.
3466 * * -ENOMEM: on allocation failure
3467 * * -EINVAL: on a wrong parameter
b573d484 3468 */
4b828fe1
TW		 3469int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3470 u8 **buf, bool ascii)
b573d484 3471{
4b828fe1
TW		 3472 struct uc_string_id *uc_str;
3473 u8 *str;
3474 int ret;
b573d484 3475
4b828fe1
TW		 3476 if (!buf)
3477 return -EINVAL;
b573d484 3478
4b828fe1
TW		 3479 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3480 if (!uc_str)
3481 return -ENOMEM;
b573d484 3482
c4607a09
BH		 3483 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3484 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
4b828fe1
TW		 3485 if (ret < 0) {
3486 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3487 QUERY_REQ_RETRIES, ret);
3488 str = NULL;
3489 goto out;
3490 }
3491
3492 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3493 dev_dbg(hba->dev, "String Desc is of zero length\n");
3494 str = NULL;
3495 ret = 0;
b573d484
YG		 3496 goto out;
3497 }
3498
3499 if (ascii) {
4b828fe1 3500 ssize_t ascii_len;
b573d484 3501 int i;
b573d484 3502 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3503 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3504 str = kzalloc(ascii_len, GFP_KERNEL);
3505 if (!str) {
3506 ret = -ENOMEM;
fcbefc3b 3507 goto out;
b573d484
YG		 3508 }
3509
3510 /*
3511 * the descriptor contains string in UTF16 format
3512 * we need to convert to utf-8 so it can be displayed
3513 */
4b828fe1
TW		 3514 ret = utf16s_to_utf8s(uc_str->uc,
3515 uc_str->len - QUERY_DESC_HDR_SIZE,
3516 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3517
3518 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3519 for (i = 0; i < ret; i++)
3520 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3521
4b828fe1
TW		 3522 str[ret++] = '\0';
3523
3524 } else {
5f57704d 3525 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3526 if (!str) {
3527 ret = -ENOMEM;
3528 goto out;
3529 }
4b828fe1 3530 ret = uc_str->len;
b573d484
YG		 3531 }
3532out:
4b828fe1
TW		 3533 *buf = str;
3534 kfree(uc_str);
3535 return ret;
b573d484 3536}
b573d484 3537
da461cec
SJ		 3538/**
3539 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3540 * @hba: Pointer to adapter instance
3541 * @lun: lun id
3542 * @param_offset: offset of the parameter to read
3543 * @param_read_buf: pointer to buffer where parameter would be read
3544 * @param_size: sizeof(param_read_buf)
3545 *
3546 * Return 0 in case of success, non-zero otherwise
3547 */
3548static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3549 int lun,
3550 enum unit_desc_param param_offset,
3551 u8 *param_read_buf,
3552 u32 param_size)
3553{
3554 /*
3555 * Unit descriptors are only available for general purpose LUs (LUN id
3556 * from 0 to 7) and RPMB Well known LU.
3557 */
a2fca52e 3558 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
da461cec
SJ		 3559 return -EOPNOTSUPP;
3560
3561 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3562 param_offset, param_read_buf, param_size);
3563}
3564
09f17791
CG		 3565static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3566{
3567 int err = 0;
3568 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3569
3570 if (hba->dev_info.wspecversion >= 0x300) {
3571 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3572 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3573 &gating_wait);
3574 if (err)
3575 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3576 err, gating_wait);
3577
3578 if (gating_wait == 0) {
3579 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3580 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3581 gating_wait);
3582 }
3583
3584 hba->dev_info.clk_gating_wait_us = gating_wait;
3585 }
3586
3587 return err;
3588}
3589
7a3e97b0
SY		 3590/**
3591 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3592 * @hba: per adapter instance
3593 *
3594 * 1. Allocate DMA memory for Command Descriptor array
3595 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3596 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3597 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3598 * (UTMRDL)
3599 * 4. Allocate memory for local reference block(lrb).
3600 *
3601 * Returns 0 for success, non-zero in case of failure
3602 */
3603static int ufshcd_memory_alloc(struct ufs_hba *hba)
3604{
3605 size_t utmrdl_size, utrdl_size, ucdl_size;
3606
3607 /* Allocate memory for UTP command descriptors */
3608 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3609 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3610 ucdl_size,
3611 &hba->ucdl_dma_addr,
3612 GFP_KERNEL);
7a3e97b0
SY		 3613
3614 /*
3615 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3616 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3617 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3618 * be aligned to 128 bytes as well
3619 */
3620 if (!hba->ucdl_base_addr ||
3621 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3622 dev_err(hba->dev,
7a3e97b0
SY		 3623 "Command Descriptor Memory allocation failed\n");
3624 goto out;
3625 }
3626
3627 /*
3628 * Allocate memory for UTP Transfer descriptors
3629 * UFSHCI requires 1024 byte alignment of UTRD
3630 */
3631 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3632 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3633 utrdl_size,
3634 &hba->utrdl_dma_addr,
3635 GFP_KERNEL);
7a3e97b0
SY		 3636 if (!hba->utrdl_base_addr ||
3637 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3638 dev_err(hba->dev,
7a3e97b0
SY		 3639 "Transfer Descriptor Memory allocation failed\n");
3640 goto out;
3641 }
3642
3643 /*
3644 * Allocate memory for UTP Task Management descriptors
3645 * UFSHCI requires 1024 byte alignment of UTMRD
3646 */
3647 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3648 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3649 utmrdl_size,
3650 &hba->utmrdl_dma_addr,
3651 GFP_KERNEL);
7a3e97b0
SY		 3652 if (!hba->utmrdl_base_addr ||
3653 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3654 dev_err(hba->dev,
7a3e97b0
SY		 3655 "Task Management Descriptor Memory allocation failed\n");
3656 goto out;
3657 }
3658
3659 /* Allocate memory for local reference block */
a86854d0
KC		 3660 hba->lrb = devm_kcalloc(hba->dev,
3661 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3662 GFP_KERNEL);
7a3e97b0 3663 if (!hba->lrb) {
3b1d0580 3664 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3665 goto out;
3666 }
3667 return 0;
3668out:
7a3e97b0
SY		 3669 return -ENOMEM;
3670}
3671
3672/**
3673 * ufshcd_host_memory_configure - configure local reference block with
3674 * memory offsets
3675 * @hba: per adapter instance
3676 *
3677 * Configure Host memory space
3678 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3679 * address.
3680 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3681 * and PRDT offset.
3682 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3683 * into local reference block.
3684 */
3685static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3686{
7a3e97b0
SY		 3687 struct utp_transfer_req_desc *utrdlp;
3688 dma_addr_t cmd_desc_dma_addr;
3689 dma_addr_t cmd_desc_element_addr;
3690 u16 response_offset;
3691 u16 prdt_offset;
3692 int cmd_desc_size;
3693 int i;
3694
3695 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3696
3697 response_offset =
3698 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3699 prdt_offset =
3700 offsetof(struct utp_transfer_cmd_desc, prd_table);
3701
3702 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3703 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3704
3705 for (i = 0; i < hba->nutrs; i++) {
3706 /* Configure UTRD with command descriptor base address */
3707 cmd_desc_element_addr =
3708 (cmd_desc_dma_addr + (cmd_desc_size * i));
3709 utrdlp[i].command_desc_base_addr_lo =
3710 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3711 utrdlp[i].command_desc_base_addr_hi =
3712 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3713
3714 /* Response upiu and prdt offset should be in double words */
26f968d7
AA		 3715 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3716 utrdlp[i].response_upiu_offset =
3717 cpu_to_le16(response_offset);
3718 utrdlp[i].prd_table_offset =
3719 cpu_to_le16(prdt_offset);
3720 utrdlp[i].response_upiu_length =
3721 cpu_to_le16(ALIGNED_UPIU_SIZE);
3722 } else {
3723 utrdlp[i].response_upiu_offset =
3724 cpu_to_le16(response_offset >> 2);
3725 utrdlp[i].prd_table_offset =
3726 cpu_to_le16(prdt_offset >> 2);
3727 utrdlp[i].response_upiu_length =
3728 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3729 }
7a3e97b0 3730
4d2b8d40 3731 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3732 }
3733}
3734
3735/**
3736 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3737 * @hba: per adapter instance
3738 *
3739 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3740 * in order to initialize the Unipro link startup procedure.
3741 * Once the Unipro links are up, the device connected to the controller
3742 * is detected.
3743 *
3744 * Returns 0 on success, non-zero value on failure
3745 */
3746static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3747{
6ccf44fe
SJ		 3748 struct uic_command uic_cmd = {0};
3749 int ret;
7a3e97b0 3750
6ccf44fe 3751 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3752
6ccf44fe
SJ		 3753 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3754 if (ret)
ff8e20c6 3755 dev_dbg(hba->dev,
6ccf44fe
SJ		 3756 "dme-link-startup: error code %d\n", ret);
3757 return ret;
7a3e97b0 3758}
39bf2d83
AA		 3759/**
3760 * ufshcd_dme_reset - UIC command for DME_RESET
3761 * @hba: per adapter instance
3762 *
3763 * DME_RESET command is issued in order to reset UniPro stack.
3764 * This function now deals with cold reset.
3765 *
3766 * Returns 0 on success, non-zero value on failure
3767 */
3768static int ufshcd_dme_reset(struct ufs_hba *hba)
3769{
3770 struct uic_command uic_cmd = {0};
3771 int ret;
3772
3773 uic_cmd.command = UIC_CMD_DME_RESET;
3774
3775 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3776 if (ret)
3777 dev_err(hba->dev,
3778 "dme-reset: error code %d\n", ret);
3779
3780 return ret;
3781}
3782
fc85a74e
SC		 3783int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3784 int agreed_gear,
3785 int adapt_val)
3786{
3787 int ret;
3788
3789 if (agreed_gear != UFS_HS_G4)
66df79cc 3790 adapt_val = PA_NO_ADAPT;
fc85a74e
SC		 3791
3792 ret = ufshcd_dme_set(hba,
3793 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3794 adapt_val);
3795 return ret;
3796}
3797EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3798
39bf2d83
AA		 3799/**
3800 * ufshcd_dme_enable - UIC command for DME_ENABLE
3801 * @hba: per adapter instance
3802 *
3803 * DME_ENABLE command is issued in order to enable UniPro stack.
3804 *
3805 * Returns 0 on success, non-zero value on failure
3806 */
3807static int ufshcd_dme_enable(struct ufs_hba *hba)
3808{
3809 struct uic_command uic_cmd = {0};
3810 int ret;
3811
3812 uic_cmd.command = UIC_CMD_DME_ENABLE;
3813
3814 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3815 if (ret)
3816 dev_err(hba->dev,
1fa05700 3817 "dme-enable: error code %d\n", ret);
39bf2d83
AA		 3818
3819 return ret;
3820}
7a3e97b0 3821
cad2e03d
YG		 3822static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3823{
3824 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3825 unsigned long min_sleep_time_us;
3826
3827 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3828 return;
3829
3830 /*
3831 * last_dme_cmd_tstamp will be 0 only for 1st call to
3832 * this function
3833 */
3834 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3835 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3836 } else {
3837 unsigned long delta =
3838 (unsigned long) ktime_to_us(
3839 ktime_sub(ktime_get(),
3840 hba->last_dme_cmd_tstamp));
3841
3842 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3843 min_sleep_time_us =
3844 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3845 else
3846 return; /* no more delay required */
3847 }
3848
3849 /* allow sleep for extra 50us if needed */
3850 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3851}
3852
12b4fdb4
SJ		 3853/**
3854 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3855 * @hba: per adapter instance
3856 * @attr_sel: uic command argument1
3857 * @attr_set: attribute set type as uic command argument2
3858 * @mib_val: setting value as uic command argument3
3859 * @peer: indicate whether peer or local
3860 *
3861 * Returns 0 on success, non-zero value on failure
3862 */
3863int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3864 u8 attr_set, u32 mib_val, u8 peer)
3865{
3866 struct uic_command uic_cmd = {0};
3867 static const char *const action[] = {
3868 "dme-set",
3869 "dme-peer-set"
3870 };
3871 const char *set = action[!!peer];
3872 int ret;
64238fbd 3873 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3874
3875 uic_cmd.command = peer ?
3876 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3877 uic_cmd.argument1 = attr_sel;
3878 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3879 uic_cmd.argument3 = mib_val;
3880
64238fbd
YG		 3881 do {
3882 /* for peer attributes we retry upon failure */
3883 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3884 if (ret)
3885 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3886 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3887 } while (ret && peer && --retries);
3888
f37e9f8c 3889 if (ret)
64238fbd 3890 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3891 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3892 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3893
3894 return ret;
3895}
3896EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3897
3898/**
3899 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3900 * @hba: per adapter instance
3901 * @attr_sel: uic command argument1
3902 * @mib_val: the value of the attribute as returned by the UIC command
3903 * @peer: indicate whether peer or local
3904 *
3905 * Returns 0 on success, non-zero value on failure
3906 */
3907int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3908 u32 *mib_val, u8 peer)
3909{
3910 struct uic_command uic_cmd = {0};
3911 static const char *const action[] = {
3912 "dme-get",
3913 "dme-peer-get"
3914 };
3915 const char *get = action[!!peer];
3916 int ret;
64238fbd 3917 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3918 struct ufs_pa_layer_attr orig_pwr_info;
3919 struct ufs_pa_layer_attr temp_pwr_info;
3920 bool pwr_mode_change = false;
3921
3922 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3923 orig_pwr_info = hba->pwr_info;
3924 temp_pwr_info = orig_pwr_info;
3925
3926 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3927 orig_pwr_info.pwr_rx == FAST_MODE) {
3928 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3929 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3930 pwr_mode_change = true;
3931 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3932 orig_pwr_info.pwr_rx == SLOW_MODE) {
3933 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3934 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3935 pwr_mode_change = true;
3936 }
3937 if (pwr_mode_change) {
3938 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3939 if (ret)
3940 goto out;
3941 }
3942 }
12b4fdb4
SJ		 3943
3944 uic_cmd.command = peer ?
3945 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3946 uic_cmd.argument1 = attr_sel;
3947
64238fbd
YG		 3948 do {
3949 /* for peer attributes we retry upon failure */
3950 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3951 if (ret)
3952 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3953 get, UIC_GET_ATTR_ID(attr_sel), ret);
3954 } while (ret && peer && --retries);
3955
f37e9f8c 3956 if (ret)
64238fbd 3957 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3958 get, UIC_GET_ATTR_ID(attr_sel),
3959 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3960
64238fbd 3961 if (mib_val && !ret)
12b4fdb4 3962 *mib_val = uic_cmd.argument3;
874237f7
YG		 3963
3964 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3965 && pwr_mode_change)
3966 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3967out:
3968 return ret;
3969}
3970EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3971
53b3d9c3 3972/**
57d104c1
SJ		 3973 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3974 * state) and waits for it to take effect.
3975 *
53b3d9c3 3976 * @hba: per adapter instance
57d104c1
SJ		 3977 * @cmd: UIC command to execute
3978 *
3979 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3980 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3981 * and device UniPro link and hence it's final completion would be indicated by
3982 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3983 * addition to normal UIC command completion Status (UCCS). This function only
3984 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3985 *
3986 * Returns 0 on success, non-zero value on failure
3987 */
57d104c1 3988static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3989{
8a686f26 3990 DECLARE_COMPLETION_ONSTACK(uic_async_done);
53b3d9c3
SJ		 3991 unsigned long flags;
3992 u8 status;
3993 int ret;
d75f7fe4 3994 bool reenable_intr = false;
53b3d9c3 3995
53b3d9c3 3996 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d 3997 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3998
3999 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236
CG		 4000 if (ufshcd_is_link_broken(hba)) {
4001 ret = -ENOLINK;
4002 goto out_unlock;
4003 }
57d104c1 4004 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 4005 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4006 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4007 /*
4008 * Make sure UIC command completion interrupt is disabled before
4009 * issuing UIC command.
4010 */
4011 wmb();
4012 reenable_intr = true;
57d104c1 4013 }
d75f7fe4
YG		 4014 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4015 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 4016 if (ret) {
4017 dev_err(hba->dev,
4018 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4019 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 4020 goto out;
4021 }
4022
57d104c1 4023 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 4024 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4025 dev_err(hba->dev,
57d104c1
SJ		 4026 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4027 cmd->command, cmd->argument3);
0f52fcb9
CG		 4028
4029 if (!cmd->cmd_active) {
4030 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4031 __func__);
4032 goto check_upmcrs;
4033 }
4034
53b3d9c3
SJ		 4035 ret = -ETIMEDOUT;
4036 goto out;
4037 }
4038
0f52fcb9 4039check_upmcrs:
53b3d9c3
SJ		 4040 status = ufshcd_get_upmcrs(hba);
4041 if (status != PWR_LOCAL) {
4042 dev_err(hba->dev,
479da360 4043 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 4044 cmd->command, status);
53b3d9c3
SJ		 4045 ret = (status != PWR_OK) ? status : -1;
4046 }
4047out:
7942f7b5
VG		 4048 if (ret) {
4049 ufshcd_print_host_state(hba);
4050 ufshcd_print_pwr_info(hba);
e965e5e0 4051 ufshcd_print_evt_hist(hba);
7942f7b5
VG		 4052 }
4053
53b3d9c3 4054 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 4055 hba->active_uic_cmd = NULL;
57d104c1 4056 hba->uic_async_done = NULL;
d75f7fe4
YG		 4057 if (reenable_intr)
4058 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4db7a236
CG		 4059 if (ret) {
4060 ufshcd_set_link_broken(hba);
88b09900 4061 ufshcd_schedule_eh_work(hba);
4db7a236
CG		 4062 }
4063out_unlock:
53b3d9c3
SJ		 4064 spin_unlock_irqrestore(hba->host->host_lock, flags);
4065 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 4066
53b3d9c3
SJ		 4067 return ret;
4068}
4069
57d104c1
SJ		 4070/**
4071 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4072 * using DME_SET primitives.
4073 * @hba: per adapter instance
4074 * @mode: powr mode value
4075 *
4076 * Returns 0 on success, non-zero value on failure
4077 */
4078static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4079{
4080 struct uic_command uic_cmd = {0};
1ab27c9c 4081 int ret;
57d104c1 4082
c3a2f9ee
YG		 4083 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4084 ret = ufshcd_dme_set(hba,
4085 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4086 if (ret) {
4087 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4088 __func__, ret);
4089 goto out;
4090 }
4091 }
4092
57d104c1
SJ		 4093 uic_cmd.command = UIC_CMD_DME_SET;
4094 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4095 uic_cmd.argument3 = mode;
1ab27c9c
ST		 4096 ufshcd_hold(hba, false);
4097 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4098 ufshcd_release(hba);
57d104c1 4099
c3a2f9ee 4100out:
1ab27c9c 4101 return ret;
57d104c1
SJ		 4102}
4103
087c5efa 4104int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 4105{
4106 int ret;
4107 unsigned long flags;
4108
4109 spin_lock_irqsave(hba->host->host_lock, flags);
4110 hba->ufshcd_state = UFSHCD_STATE_RESET;
4111 ufshcd_set_eh_in_progress(hba);
4112 spin_unlock_irqrestore(hba->host->host_lock, flags);
4113
ebdd1dfd 4114 /* Reset the attached device */
31a5d9ca 4115 ufshcd_device_reset(hba);
ebdd1dfd 4116
53c12d0e
YG		 4117 ret = ufshcd_host_reset_and_restore(hba);
4118
4119 spin_lock_irqsave(hba->host->host_lock, flags);
4120 if (ret)
4121 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4122 ufshcd_clear_eh_in_progress(hba);
4123 spin_unlock_irqrestore(hba->host->host_lock, flags);
4124
4125 if (ret)
4126 dev_err(hba->dev, "%s: link recovery failed, err %d",
4127 __func__, ret);
4128
4129 return ret;
4130}
087c5efa 4131EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 4132
525943a5 4133int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 4134{
87d0b4a6 4135 int ret;
57d104c1 4136 struct uic_command uic_cmd = {0};
911a0771 4137 ktime_t start = ktime_get();
57d104c1 4138
ee32c909
KK		 4139 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4140
57d104c1 4141 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 4142 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4143 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4144 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 4145
4db7a236 4146 if (ret)
87d0b4a6
YG		 4147 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4148 __func__, ret);
4db7a236 4149 else
ee32c909
KK		 4150 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4151 POST_CHANGE);
53c12d0e 4152
87d0b4a6
YG		 4153 return ret;
4154}
525943a5 4155EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
87d0b4a6 4156
9d19bf7a 4157int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 4158{
4159 struct uic_command uic_cmd = {0};
4160 int ret;
911a0771 4161 ktime_t start = ktime_get();
57d104c1 4162
ee32c909
KK		 4163 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4164
57d104c1
SJ		 4165 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4166 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4167 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4168 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4169
57d104c1 4170 if (ret) {
53c12d0e
YG		 4171 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4172 __func__, ret);
ff8e20c6 4173 } else {
ee32c909
KK		 4174 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4175 POST_CHANGE);
ff8e20c6
DR		 4176 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4177 hba->ufs_stats.hibern8_exit_cnt++;
4178 }
57d104c1
SJ		 4179
4180 return ret;
4181}
9d19bf7a 4182EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 4183
ba7af5ec
SC		 4184void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4185{
4186 unsigned long flags;
be7594a4 4187 bool update = false;
ba7af5ec 4188
be7594a4 4189 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 4190 return;
4191
4192 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 4193 if (hba->ahit != ahit) {
4194 hba->ahit = ahit;
4195 update = true;
4196 }
ba7af5ec 4197 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4 4198
b294ff3e
AD		 4199 if (update &&
4200 !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4201 ufshcd_rpm_get_sync(hba);
be7594a4
CG		 4202 ufshcd_hold(hba, false);
4203 ufshcd_auto_hibern8_enable(hba);
4204 ufshcd_release(hba);
b294ff3e 4205 ufshcd_rpm_put_sync(hba);
be7594a4 4206 }
ba7af5ec
SC		 4207}
4208EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4209
71d848b8 4210void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 4211{
4212 unsigned long flags;
4213
499f7a96 4214 if (!ufshcd_is_auto_hibern8_supported(hba))
ad448378
AH		 4215 return;
4216
4217 spin_lock_irqsave(hba->host->host_lock, flags);
4218 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4219 spin_unlock_irqrestore(hba->host->host_lock, flags);
4220}
4221
5064636c
YG		 4222 /**
4223 * ufshcd_init_pwr_info - setting the POR (power on reset)
4224 * values in hba power info
4225 * @hba: per-adapter instance
4226 */
4227static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4228{
4229 hba->pwr_info.gear_rx = UFS_PWM_G1;
4230 hba->pwr_info.gear_tx = UFS_PWM_G1;
4231 hba->pwr_info.lane_rx = 1;
4232 hba->pwr_info.lane_tx = 1;
4233 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4234 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4235 hba->pwr_info.hs_rate = 0;
4236}
4237
d3e89bac 4238/**
7eb584db
DR		 4239 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4240 * @hba: per-adapter instance
d3e89bac 4241 */
7eb584db 4242static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 4243{
7eb584db
DR		 4244 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4245
4246 if (hba->max_pwr_info.is_valid)
4247 return 0;
4248
2349b533 4249 pwr_info->pwr_tx = FAST_MODE;
4250 pwr_info->pwr_rx = FAST_MODE;
7eb584db 4251 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4252
4253 /* Get the connected lane count */
7eb584db
DR		 4254 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4255 &pwr_info->lane_rx);
4256 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4257 &pwr_info->lane_tx);
4258
4259 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4260 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4261 __func__,
4262 pwr_info->lane_rx,
4263 pwr_info->lane_tx);
4264 return -EINVAL;
4265 }
d3e89bac
SJ		 4266
4267 /*
4268 * First, get the maximum gears of HS speed.
4269 * If a zero value, it means there is no HSGEAR capability.
4270 * Then, get the maximum gears of PWM speed.
4271 */
7eb584db
DR		 4272 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4273 if (!pwr_info->gear_rx) {
4274 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4275 &pwr_info->gear_rx);
4276 if (!pwr_info->gear_rx) {
4277 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4278 __func__, pwr_info->gear_rx);
4279 return -EINVAL;
4280 }
2349b533 4281 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4282 }
4283
7eb584db
DR		 4284 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4285 &pwr_info->gear_tx);
4286 if (!pwr_info->gear_tx) {
d3e89bac 4287 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4288 &pwr_info->gear_tx);
4289 if (!pwr_info->gear_tx) {
4290 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4291 __func__, pwr_info->gear_tx);
4292 return -EINVAL;
4293 }
2349b533 4294 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4295 }
4296
4297 hba->max_pwr_info.is_valid = true;
4298 return 0;
4299}
4300
4301static int ufshcd_change_power_mode(struct ufs_hba *hba,
4302 struct ufs_pa_layer_attr *pwr_mode)
4303{
4304 int ret;
4305
4306 /* if already configured to the requested pwr_mode */
2355b66e
CG		 4307 if (!hba->force_pmc &&
4308 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
7eb584db
DR		 4309 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4310 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4311 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4312 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4313 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4314 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4315 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4316 return 0;
d3e89bac
SJ		 4317 }
4318
4319 /*
4320 * Configure attributes for power mode change with below.
4321 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4322 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4323 * - PA_HSSERIES
4324 */
7eb584db
DR		 4325 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4326 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4327 pwr_mode->lane_rx);
4328 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4329 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4330 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4331 else
4332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4333
7eb584db
DR		 4334 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4336 pwr_mode->lane_tx);
4337 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4338 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4339 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4340 else
4341 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4342
7eb584db
DR		 4343 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4344 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4345 pwr_mode->pwr_rx == FAST_MODE ||
4346 pwr_mode->pwr_tx == FAST_MODE)
4347 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4348 pwr_mode->hs_rate);
d3e89bac 4349
b1d0d2eb
KK		 4350 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4352 DL_FC0ProtectionTimeOutVal_Default);
4353 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4354 DL_TC0ReplayTimeOutVal_Default);
4355 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4356 DL_AFC0ReqTimeOutVal_Default);
4357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4358 DL_FC1ProtectionTimeOutVal_Default);
4359 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4360 DL_TC1ReplayTimeOutVal_Default);
4361 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4362 DL_AFC1ReqTimeOutVal_Default);
4363
4364 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4365 DL_FC0ProtectionTimeOutVal_Default);
4366 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4367 DL_TC0ReplayTimeOutVal_Default);
4368 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4369 DL_AFC0ReqTimeOutVal_Default);
4370 }
08342537 4371
7eb584db
DR		 4372 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4373 | pwr_mode->pwr_tx);
4374
4375 if (ret) {
d3e89bac 4376 dev_err(hba->dev,
7eb584db
DR		 4377 "%s: power mode change failed %d\n", __func__, ret);
4378 } else {
0263bcd0
YG		 4379 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4380 pwr_mode);
7eb584db
DR		 4381
4382 memcpy(&hba->pwr_info, pwr_mode,
4383 sizeof(struct ufs_pa_layer_attr));
4384 }
4385
4386 return ret;
4387}
4388
4389/**
4390 * ufshcd_config_pwr_mode - configure a new power mode
4391 * @hba: per-adapter instance
4392 * @desired_pwr_mode: desired power configuration
4393 */
0d846e70 4394int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4395 struct ufs_pa_layer_attr *desired_pwr_mode)
4396{
4397 struct ufs_pa_layer_attr final_params = { 0 };
4398 int ret;
4399
0263bcd0
YG		 4400 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4401 desired_pwr_mode, &final_params);
4402
4403 if (ret)
7eb584db
DR		 4404 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4405
4406 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4407
4408 return ret;
4409}
0d846e70 4410EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4411
68078d5c
DR		 4412/**
4413 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4414 * @hba: per-adapter instance
68078d5c
DR		 4415 *
4416 * Set fDeviceInit flag and poll until device toggles it.
4417 */
4418static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4419{
dc3c8d3a 4420 int err;
7dfdcc39 4421 bool flag_res = true;
29707fab 4422 ktime_t timeout;
68078d5c 4423
dc3c8d3a 4424 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4425 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
68078d5c
DR		 4426 if (err) {
4427 dev_err(hba->dev,
4428 "%s setting fDeviceInit flag failed with error %d\n",
4429 __func__, err);
4430 goto out;
4431 }
4432
29707fab
KK		 4433 /* Poll fDeviceInit flag to be cleared */
4434 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4435 do {
4436 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4437 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4438 if (!flag_res)
4439 break;
a4e6496f 4440 usleep_range(500, 1000);
29707fab 4441 } while (ktime_before(ktime_get(), timeout));
dc3c8d3a 4442
29707fab 4443 if (err) {
68078d5c 4444 dev_err(hba->dev,
29707fab
KK		 4445 "%s reading fDeviceInit flag failed with error %d\n",
4446 __func__, err);
4447 } else if (flag_res) {
68078d5c 4448 dev_err(hba->dev,
29707fab
KK		 4449 "%s fDeviceInit was not cleared by the device\n",
4450 __func__);
4451 err = -EBUSY;
4452 }
68078d5c
DR		 4453out:
4454 return err;
4455}
4456
7a3e97b0
SY		 4457/**
4458 * ufshcd_make_hba_operational - Make UFS controller operational
4459 * @hba: per adapter instance
4460 *
4461 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4462 * 1. Enable required interrupts
4463 * 2. Configure interrupt aggregation
897efe62 4464 * 3. Program UTRL and UTMRL base address
5c0c28a8 4465 * 4. Configure run-stop-registers
7a3e97b0
SY		 4466 *
4467 * Returns 0 on success, non-zero value on failure
4468 */
9d19bf7a 4469int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4470{
4471 int err = 0;
4472 u32 reg;
4473
6ccf44fe
SJ		 4474 /* Enable required interrupts */
4475 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4476
4477 /* Configure interrupt aggregation */
b852190e
YG		 4478 if (ufshcd_is_intr_aggr_allowed(hba))
4479 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4480 else
4481 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4482
4483 /* Configure UTRL and UTMRL base address registers */
4484 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4485 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4486 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4487 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4488 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4489 REG_UTP_TASK_REQ_LIST_BASE_L);
4490 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4491 REG_UTP_TASK_REQ_LIST_BASE_H);
4492
897efe62
YG		 4493 /*
4494 * Make sure base address and interrupt setup are updated before
4495 * enabling the run/stop registers below.
4496 */
4497 wmb();
4498
7a3e97b0
SY		 4499 /*
4500 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4501 */
5c0c28a8 4502 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4503 if (!(ufshcd_get_lists_status(reg))) {
4504 ufshcd_enable_run_stop_reg(hba);
4505 } else {
3b1d0580 4506 dev_err(hba->dev,
7a3e97b0
SY		 4507 "Host controller not ready to process requests");
4508 err = -EIO;
7a3e97b0
SY		 4509 }
4510
7a3e97b0
SY		 4511 return err;
4512}
9d19bf7a 4513EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4514
596585a2
YG		 4515/**
4516 * ufshcd_hba_stop - Send controller to reset state
4517 * @hba: per adapter instance
596585a2 4518 */
3a95f5b3 4519void ufshcd_hba_stop(struct ufs_hba *hba)
596585a2 4520{
5cac1095 4521 unsigned long flags;
596585a2
YG		 4522 int err;
4523
5cac1095
BVA		 4524 /*
4525 * Obtain the host lock to prevent that the controller is disabled
4526 * while the UFS interrupt handler is active on another CPU.
4527 */
4528 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4529 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
5cac1095
BVA		 4530 spin_unlock_irqrestore(hba->host->host_lock, flags);
4531
596585a2
YG		 4532 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4533 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
5cac1095 4534 10, 1);
596585a2
YG		 4535 if (err)
4536 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4537}
3a95f5b3 4538EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
596585a2 4539
7a3e97b0 4540/**
39bf2d83 4541 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4542 * @hba: per adapter instance
4543 *
4544 * The controller resets itself and controller firmware initialization
4545 * sequence kicks off. When controller is ready it will set
4546 * the Host Controller Enable bit to 1.
4547 *
4548 * Returns 0 on success, non-zero value on failure
4549 */
39bf2d83 4550static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0 4551{
6081b12c
SC		 4552 int retry_outer = 3;
4553 int retry_inner;
7a3e97b0 4554
6081b12c 4555start:
596585a2 4556 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4557 /* change controller state to "reset state" */
5cac1095 4558 ufshcd_hba_stop(hba);
7a3e97b0 4559
57d104c1
SJ		 4560 /* UniPro link is disabled at this point */
4561 ufshcd_set_link_off(hba);
4562
0263bcd0 4563 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4564
7a3e97b0
SY		 4565 /* start controller initialization sequence */
4566 ufshcd_hba_start(hba);
4567
4568 /*
4569 * To initialize a UFS host controller HCE bit must be set to 1.
4570 * During initialization the HCE bit value changes from 1->0->1.
4571 * When the host controller completes initialization sequence
4572 * it sets the value of HCE bit to 1. The same HCE bit is read back
4573 * to check if the controller has completed initialization sequence.
4574 * So without this delay the value HCE = 1, set in the previous
4575 * instruction might be read back.
4576 * This delay can be changed based on the controller.
4577 */
90b8491c 4578 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
7a3e97b0
SY		 4579
4580 /* wait for the host controller to complete initialization */
6081b12c 4581 retry_inner = 50;
7a3e97b0 4582 while (ufshcd_is_hba_active(hba)) {
6081b12c
SC		 4583 if (retry_inner) {
4584 retry_inner--;
7a3e97b0 4585 } else {
3b1d0580 4586 dev_err(hba->dev,
7a3e97b0 4587 "Controller enable failed\n");
6081b12c
SC		 4588 if (retry_outer) {
4589 retry_outer--;
4590 goto start;
4591 }
7a3e97b0
SY		 4592 return -EIO;
4593 }
9fc305ef 4594 usleep_range(1000, 1100);
7a3e97b0 4595 }
5c0c28a8 4596
1d337ec2 4597 /* enable UIC related interrupts */
57d104c1 4598 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4599
0263bcd0 4600 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4601
7a3e97b0
SY		 4602 return 0;
4603}
39bf2d83
AA		 4604
4605int ufshcd_hba_enable(struct ufs_hba *hba)
4606{
4607 int ret;
4608
4609 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4610 ufshcd_set_link_off(hba);
4611 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4612
4613 /* enable UIC related interrupts */
4614 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4615 ret = ufshcd_dme_reset(hba);
4616 if (!ret) {
4617 ret = ufshcd_dme_enable(hba);
4618 if (!ret)
4619 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4620 if (ret)
4621 dev_err(hba->dev,
4622 "Host controller enable failed with non-hce\n");
4623 }
4624 } else {
4625 ret = ufshcd_hba_execute_hce(hba);
4626 }
4627
4628 return ret;
4629}
9d19bf7a
SC		 4630EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4631
7ca38cf3
YG		 4632static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4633{
ba0320fb 4634 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4635
4636 if (!peer)
4637 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4638 &tx_lanes);
4639 else
4640 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4641 &tx_lanes);
4642 for (i = 0; i < tx_lanes; i++) {
4643 if (!peer)
4644 err = ufshcd_dme_set(hba,
4645 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4646 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4647 0);
4648 else
4649 err = ufshcd_dme_peer_set(hba,
4650 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4651 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4652 0);
4653 if (err) {
4654 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4655 __func__, peer, i, err);
4656 break;
4657 }
4658 }
4659
4660 return err;
4661}
4662
4663static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4664{
4665 return ufshcd_disable_tx_lcc(hba, true);
4666}
4667
e965e5e0 4668void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
8808b4e9 4669{
e965e5e0
SC		 4670 struct ufs_event_hist *e;
4671
4672 if (id >= UFS_EVT_CNT)
4673 return;
4674
4675 e = &hba->ufs_stats.event[id];
4676 e->val[e->pos] = val;
4677 e->tstamp[e->pos] = ktime_get();
b6cacaf2 4678 e->cnt += 1;
e965e5e0 4679 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
172614a9
SC		 4680
4681 ufshcd_vops_event_notify(hba, id, &val);
8808b4e9 4682}
e965e5e0 4683EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
8808b4e9 4684
7a3e97b0 4685/**
6ccf44fe 4686 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4687 * @hba: per adapter instance
4688 *
6ccf44fe 4689 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4690 */
6ccf44fe 4691static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4692{
6ccf44fe 4693 int ret;
1d337ec2 4694 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4695 bool link_startup_again = false;
7a3e97b0 4696
7caf489b 4697 /*
4698 * If UFS device isn't active then we will have to issue link startup
4699 * 2 times to make sure the device state move to active.
4700 */
4701 if (!ufshcd_is_ufs_dev_active(hba))
4702 link_startup_again = true;
7a3e97b0 4703
7caf489b 4704link_startup:
1d337ec2 4705 do {
0263bcd0 4706 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4707
1d337ec2 4708 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4709
1d337ec2
SRT		 4710 /* check if device is detected by inter-connect layer */
4711 if (!ret && !ufshcd_is_device_present(hba)) {
e965e5e0
SC		 4712 ufshcd_update_evt_hist(hba,
4713 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4714 0);
1d337ec2
SRT		 4715 dev_err(hba->dev, "%s: Device not present\n", __func__);
4716 ret = -ENXIO;
4717 goto out;
4718 }
6ccf44fe 4719
1d337ec2
SRT		 4720 /*
4721 * DME link lost indication is only received when link is up,
4722 * but we can't be sure if the link is up until link startup
4723 * succeeds. So reset the local Uni-Pro and try again.
4724 */
8808b4e9 4725 if (ret && ufshcd_hba_enable(hba)) {
e965e5e0
SC		 4726 ufshcd_update_evt_hist(hba,
4727 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4728 (u32)ret);
1d337ec2 4729 goto out;
8808b4e9 4730 }
1d337ec2
SRT		 4731 } while (ret && retries--);
4732
8808b4e9 4733 if (ret) {
1d337ec2 4734 /* failed to get the link up... retire */
e965e5e0
SC		 4735 ufshcd_update_evt_hist(hba,
4736 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4737 (u32)ret);
5c0c28a8 4738 goto out;
8808b4e9 4739 }
5c0c28a8 4740
7caf489b 4741 if (link_startup_again) {
4742 link_startup_again = false;
4743 retries = DME_LINKSTARTUP_RETRIES;
4744 goto link_startup;
4745 }
4746
d2aebb9b 4747 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4748 ufshcd_init_pwr_info(hba);
4749 ufshcd_print_pwr_info(hba);
4750
7ca38cf3
YG		 4751 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4752 ret = ufshcd_disable_device_tx_lcc(hba);
4753 if (ret)
4754 goto out;
4755 }
4756
5c0c28a8 4757 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4758 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4759 if (ret)
4760 goto out;
7a3e97b0 4761
2355b66e
CG		 4762 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4763 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5c0c28a8 4764 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4765out:
7942f7b5 4766 if (ret) {
6ccf44fe 4767 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4768 ufshcd_print_host_state(hba);
4769 ufshcd_print_pwr_info(hba);
e965e5e0 4770 ufshcd_print_evt_hist(hba);
7942f7b5 4771 }
6ccf44fe 4772 return ret;
7a3e97b0
SY		 4773}
4774
5a0b0cb9
SRT		 4775/**
4776 * ufshcd_verify_dev_init() - Verify device initialization
4777 * @hba: per-adapter instance
4778 *
4779 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4780 * device Transport Protocol (UTP) layer is ready after a reset.
4781 * If the UTP layer at the device side is not initialized, it may
4782 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4783 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4784 */
4785static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4786{
4787 int err = 0;
4788 int retries;
4789
1ab27c9c 4790 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4791 mutex_lock(&hba->dev_cmd.lock);
4792 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4793 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1cbc9ad3 4794 hba->nop_out_timeout);
5a0b0cb9
SRT		 4795
4796 if (!err || err == -ETIMEDOUT)
4797 break;
4798
4799 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4800 }
4801 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4802 ufshcd_release(hba);
5a0b0cb9
SRT		 4803
4804 if (err)
4805 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4806 return err;
4807}
4808
0ce147d4
SJ		 4809/**
4810 * ufshcd_set_queue_depth - set lun queue depth
4811 * @sdev: pointer to SCSI device
4812 *
4813 * Read bLUQueueDepth value and activate scsi tagged command
4814 * queueing. For WLUN, queue depth is set to 1. For best-effort
4815 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4816 * value that host can queue.
4817 */
4818static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4819{
4820 int ret = 0;
4821 u8 lun_qdepth;
4822 struct ufs_hba *hba;
4823
4824 hba = shost_priv(sdev->host);
4825
4826 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4827 ret = ufshcd_read_unit_desc_param(hba,
4828 ufshcd_scsi_to_upiu_lun(sdev->lun),
4829 UNIT_DESC_PARAM_LU_Q_DEPTH,
4830 &lun_qdepth,
4831 sizeof(lun_qdepth));
0ce147d4
SJ		 4832
4833 /* Some WLUN doesn't support unit descriptor */
4834 if (ret == -EOPNOTSUPP)
4835 lun_qdepth = 1;
4836 else if (!lun_qdepth)
4837 /* eventually, we can figure out the real queue depth */
4838 lun_qdepth = hba->nutrs;
4839 else
4840 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4841
4842 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4843 __func__, lun_qdepth);
db5ed4df 4844 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4845}
4846
57d104c1
SJ		 4847/*
4848 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4849 * @hba: per-adapter instance
4850 * @lun: UFS device lun id
4851 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4852 *
4853 * Returns 0 in case of success and b_lu_write_protect status would be returned
4854 * @b_lu_write_protect parameter.
4855 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4856 * Returns -EINVAL in case of invalid parameters passed to this function.
4857 */
4858static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4859 u8 lun,
4860 u8 *b_lu_write_protect)
4861{
4862 int ret;
4863
4864 if (!b_lu_write_protect)
4865 ret = -EINVAL;
4866 /*
4867 * According to UFS device spec, RPMB LU can't be write
4868 * protected so skip reading bLUWriteProtect parameter for
4869 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4870 */
1baa8011 4871 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4872 ret = -ENOTSUPP;
4873 else
4874 ret = ufshcd_read_unit_desc_param(hba,
4875 lun,
4876 UNIT_DESC_PARAM_LU_WR_PROTECT,
4877 b_lu_write_protect,
4878 sizeof(*b_lu_write_protect));
4879 return ret;
4880}
4881
4882/**
4883 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4884 * status
4885 * @hba: per-adapter instance
4886 * @sdev: pointer to SCSI device
4887 *
4888 */
4889static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4890 struct scsi_device *sdev)
4891{
4892 if (hba->dev_info.f_power_on_wp_en &&
4893 !hba->dev_info.is_lu_power_on_wp) {
4894 u8 b_lu_write_protect;
4895
4896 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4897 &b_lu_write_protect) &&
4898 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4899 hba->dev_info.is_lu_power_on_wp = true;
4900 }
4901}
4902
b294ff3e
AD		 4903/**
4904 * ufshcd_setup_links - associate link b/w device wlun and other luns
4905 * @sdev: pointer to SCSI device
4906 * @hba: pointer to ufs hba
4907 */
4908static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4909{
4910 struct device_link *link;
4911
4912 /*
4913 * Device wlun is the supplier & rest of the luns are consumers.
4914 * This ensures that device wlun suspends after all other luns.
4915 */
4916 if (hba->sdev_ufs_device) {
4917 link = device_link_add(&sdev->sdev_gendev,
4918 &hba->sdev_ufs_device->sdev_gendev,
4919 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4920 if (!link) {
4921 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4922 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4923 return;
4924 }
4925 hba->luns_avail--;
4926 /* Ignore REPORT_LUN wlun probing */
4927 if (hba->luns_avail == 1) {
4928 ufshcd_rpm_put(hba);
4929 return;
4930 }
4931 } else {
4932 /*
4933 * Device wlun is probed. The assumption is that WLUNs are
4934 * scanned before other LUNs.
4935 */
4936 hba->luns_avail--;
4937 }
4938}
4939
7a3e97b0
SY		 4940/**
4941 * ufshcd_slave_alloc - handle initial SCSI device configurations
4942 * @sdev: pointer to SCSI device
4943 *
4944 * Returns success
4945 */
4946static int ufshcd_slave_alloc(struct scsi_device *sdev)
4947{
4948 struct ufs_hba *hba;
4949
4950 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4951
4952 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4953 sdev->use_10_for_ms = 1;
a3a76391
CG		 4954
4955 /* DBD field should be set to 1 in mode sense(10) */
4956 sdev->set_dbd_for_ms = 1;
7a3e97b0 4957
e8e7f271
SRT		 4958 /* allow SCSI layer to restart the device in case of errors */
4959 sdev->allow_restart = 1;
4264fd61 4960
b2a6c522
SRT		 4961 /* REPORT SUPPORTED OPERATION CODES is not supported */
4962 sdev->no_report_opcodes = 1;
4963
84af7e8b
SRT		 4964 /* WRITE_SAME command is not supported */
4965 sdev->no_write_same = 1;
e8e7f271 4966
0ce147d4 4967 ufshcd_set_queue_depth(sdev);
4264fd61 4968
57d104c1
SJ		 4969 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4970
b294ff3e
AD		 4971 ufshcd_setup_links(hba, sdev);
4972
7a3e97b0
SY		 4973 return 0;
4974}
4975
4264fd61
SRT		 4976/**
4977 * ufshcd_change_queue_depth - change queue depth
4978 * @sdev: pointer to SCSI device
4979 * @depth: required depth to set
4264fd61 4980 *
db5ed4df 4981 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4982 */
db5ed4df 4983static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61 4984{
fc21da8a 4985 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
4264fd61
SRT		 4986}
4987
f02bc975
DP		 4988static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
4989{
4990 /* skip well-known LU */
41d8a933
DP		 4991 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4992 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
f02bc975
DP		 4993 return;
4994
4995 ufshpb_destroy_lu(hba, sdev);
4996}
4997
4998static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
4999{
5000 /* skip well-known LU */
5001 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5002 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5003 return;
5004
5005 ufshpb_init_hpb_lu(hba, sdev);
5006}
5007
eeda4749
AM		 5008/**
5009 * ufshcd_slave_configure - adjust SCSI device configurations
5010 * @sdev: pointer to SCSI device
5011 */
5012static int ufshcd_slave_configure(struct scsi_device *sdev)
5013{
49615ba1 5014 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 5015 struct request_queue *q = sdev->request_queue;
5016
f02bc975
DP		 5017 ufshcd_hpb_configure(hba, sdev);
5018
eeda4749 5019 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2b2bfc8a
KK		 5020 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5021 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
b294ff3e
AD		 5022 /*
5023 * Block runtime-pm until all consumers are added.
5024 * Refer ufshcd_setup_links().
5025 */
5026 if (is_device_wlun(sdev))
5027 pm_runtime_get_noresume(&sdev->sdev_gendev);
5028 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
49615ba1 5029 sdev->rpm_autosuspend = 1;
71bb9ab6
AH		 5030 /*
5031 * Do not print messages during runtime PM to avoid never-ending cycles
5032 * of messages written back to storage by user space causing runtime
5033 * resume, causing more messages and so on.
5034 */
5035 sdev->silence_suspend = 1;
49615ba1 5036
cb77cb5a 5037 ufshcd_crypto_register(hba, q);
df043c74 5038
eeda4749
AM		 5039 return 0;
5040}
5041
7a3e97b0
SY		 5042/**
5043 * ufshcd_slave_destroy - remove SCSI device configurations
5044 * @sdev: pointer to SCSI device
5045 */
5046static void ufshcd_slave_destroy(struct scsi_device *sdev)
5047{
5048 struct ufs_hba *hba;
bf25967a 5049 unsigned long flags;
7a3e97b0
SY		 5050
5051 hba = shost_priv(sdev->host);
f02bc975
DP		 5052
5053 ufshcd_hpb_destroy(hba, sdev);
5054
0ce147d4 5055 /* Drop the reference as it won't be needed anymore */
7c48bfd0 5056 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
7c48bfd0 5057 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 5058 hba->sdev_ufs_device = NULL;
7c48bfd0 5059 spin_unlock_irqrestore(hba->host->host_lock, flags);
bf25967a
AH		 5060 } else if (hba->sdev_ufs_device) {
5061 struct device *supplier = NULL;
5062
5063 /* Ensure UFS Device WLUN exists and does not disappear */
5064 spin_lock_irqsave(hba->host->host_lock, flags);
5065 if (hba->sdev_ufs_device) {
5066 supplier = &hba->sdev_ufs_device->sdev_gendev;
5067 get_device(supplier);
5068 }
5069 spin_unlock_irqrestore(hba->host->host_lock, flags);
5070
5071 if (supplier) {
5072 /*
5073 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5074 * device will not have been registered but can still
5075 * have a device link holding a reference to the device.
5076 */
5077 device_link_remove(&sdev->sdev_gendev, supplier);
5078 put_device(supplier);
5079 }
7c48bfd0 5080 }
7a3e97b0
SY		 5081}
5082
7a3e97b0
SY		 5083/**
5084 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 5085 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5086 * @scsi_status: SCSI command status
5087 *
5088 * Returns value base on SCSI command status
5089 */
5090static inline int
5091ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5092{
5093 int result = 0;
5094
5095 switch (scsi_status) {
7a3e97b0 5096 case SAM_STAT_CHECK_CONDITION:
1c2623c5 5097 ufshcd_copy_sense_data(lrbp);
df561f66 5098 fallthrough;
1c2623c5 5099 case SAM_STAT_GOOD:
db83d8a5 5100 result |= DID_OK << 16 | scsi_status;
7a3e97b0
SY		 5101 break;
5102 case SAM_STAT_TASK_SET_FULL:
1c2623c5 5103 case SAM_STAT_BUSY:
7a3e97b0 5104 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 5105 ufshcd_copy_sense_data(lrbp);
5106 result |= scsi_status;
7a3e97b0
SY		 5107 break;
5108 default:
5109 result |= DID_ERROR << 16;
5110 break;
5111 } /* end of switch */
5112
5113 return result;
5114}
5115
5116/**
5117 * ufshcd_transfer_rsp_status - Get overall status of the response
5118 * @hba: per adapter instance
8aa29f19 5119 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5120 *
5121 * Returns result of the command to notify SCSI midlayer
5122 */
5123static inline int
5124ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5125{
5126 int result = 0;
5127 int scsi_status;
957d63e7 5128 enum utp_ocs ocs;
7a3e97b0
SY		 5129
5130 /* overall command status of utrd */
5131 ocs = ufshcd_get_tr_ocs(lrbp);
5132
d779a6e9
KK		 5133 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5134 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5135 MASK_RSP_UPIU_RESULT)
5136 ocs = OCS_SUCCESS;
5137 }
5138
7a3e97b0
SY		 5139 switch (ocs) {
5140 case OCS_SUCCESS:
5a0b0cb9 5141 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 5142 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 5143 switch (result) {
5144 case UPIU_TRANSACTION_RESPONSE:
5145 /*
5146 * get the response UPIU result to extract
5147 * the SCSI command status
5148 */
5149 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5150
5151 /*
5152 * get the result based on SCSI status response
5153 * to notify the SCSI midlayer of the command status
5154 */
5155 scsi_status = result & MASK_SCSI_STATUS;
5156 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 5157
f05ac2e5
YG		 5158 /*
5159 * Currently we are only supporting BKOPs exception
5160 * events hence we can ignore BKOPs exception event
5161 * during power management callbacks. BKOPs exception
5162 * event is not expected to be raised in runtime suspend
5163 * callback as it allows the urgent bkops.
5164 * During system suspend, we are anyway forcefully
5165 * disabling the bkops and if urgent bkops is needed
5166 * it will be enabled on system resume. Long term
5167 * solution could be to abort the system suspend if
5168 * UFS device needs urgent BKOPs.
5169 */
5170 if (!hba->pm_op_in_progress &&
aa53f580 5171 !ufshcd_eh_in_progress(hba) &&
b294ff3e
AD		 5172 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5173 /* Flushed in suspend */
5174 schedule_work(&hba->eeh_work);
4b5f4907
DP		 5175
5176 if (scsi_status == SAM_STAT_GOOD)
5177 ufshpb_rsp_upiu(hba, lrbp);
5a0b0cb9
SRT		 5178 break;
5179 case UPIU_TRANSACTION_REJECT_UPIU:
5180 /* TODO: handle Reject UPIU Response */
5181 result = DID_ERROR << 16;
3b1d0580 5182 dev_err(hba->dev,
5a0b0cb9
SRT		 5183 "Reject UPIU not fully implemented\n");
5184 break;
5185 default:
5a0b0cb9
SRT		 5186 dev_err(hba->dev,
5187 "Unexpected request response code = %x\n",
5188 result);
e0347d89 5189 result = DID_ERROR << 16;
7a3e97b0
SY		 5190 break;
5191 }
7a3e97b0
SY		 5192 break;
5193 case OCS_ABORTED:
5194 result |= DID_ABORT << 16;
5195 break;
e8e7f271
SRT		 5196 case OCS_INVALID_COMMAND_STATUS:
5197 result |= DID_REQUEUE << 16;
5198 break;
7a3e97b0
SY		 5199 case OCS_INVALID_CMD_TABLE_ATTR:
5200 case OCS_INVALID_PRDT_ATTR:
5201 case OCS_MISMATCH_DATA_BUF_SIZE:
5202 case OCS_MISMATCH_RESP_UPIU_SIZE:
5203 case OCS_PEER_COMM_FAILURE:
5204 case OCS_FATAL_ERROR:
5e7341e1
ST		 5205 case OCS_DEVICE_FATAL_ERROR:
5206 case OCS_INVALID_CRYPTO_CONFIG:
5207 case OCS_GENERAL_CRYPTO_ERROR:
7a3e97b0
SY		 5208 default:
5209 result |= DID_ERROR << 16;
3b1d0580 5210 dev_err(hba->dev,
ff8e20c6
DR		 5211 "OCS error from controller = %x for tag %d\n",
5212 ocs, lrbp->task_tag);
e965e5e0 5213 ufshcd_print_evt_hist(hba);
6ba65588 5214 ufshcd_print_host_state(hba);
7a3e97b0
SY		 5215 break;
5216 } /* end of switch */
5217
eeb1b55b
JK		 5218 if ((host_byte(result) != DID_OK) &&
5219 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
66cc820f 5220 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 5221 return result;
5222}
5223
a45f9371
CG		 5224static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5225 u32 intr_mask)
5226{
5227 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5228 !ufshcd_is_auto_hibern8_enabled(hba))
5229 return false;
5230
5231 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5232 return false;
5233
5234 if (hba->active_uic_cmd &&
5235 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5236 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5237 return false;
5238
5239 return true;
5240}
5241
6ccf44fe
SJ		 5242/**
5243 * ufshcd_uic_cmd_compl - handle completion of uic command
5244 * @hba: per adapter instance
53b3d9c3 5245 * @intr_status: interrupt status generated by the controller
9333d775
VG		 5246 *
5247 * Returns
5248 * IRQ_HANDLED - If interrupt is valid
5249 * IRQ_NONE - If invalid interrupt
6ccf44fe 5250 */
9333d775 5251static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 5252{
9333d775
VG		 5253 irqreturn_t retval = IRQ_NONE;
5254
a45f9371
CG		 5255 spin_lock(hba->host->host_lock);
5256 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5257 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5258
53b3d9c3 5259 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 5260 hba->active_uic_cmd->argument2 |=
5261 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 5262 hba->active_uic_cmd->argument3 =
5263 ufshcd_get_dme_attr_val(hba);
0f52fcb9
CG		 5264 if (!hba->uic_async_done)
5265 hba->active_uic_cmd->cmd_active = 0;
6ccf44fe 5266 complete(&hba->active_uic_cmd->done);
9333d775 5267 retval = IRQ_HANDLED;
6ccf44fe 5268 }
53b3d9c3 5269
9333d775 5270 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
0f52fcb9 5271 hba->active_uic_cmd->cmd_active = 0;
57d104c1 5272 complete(hba->uic_async_done);
9333d775
VG		 5273 retval = IRQ_HANDLED;
5274 }
aa5c6979
SC		 5275
5276 if (retval == IRQ_HANDLED)
5277 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
28fa68fc 5278 UFS_CMD_COMP);
a45f9371 5279 spin_unlock(hba->host->host_lock);
9333d775 5280 return retval;
6ccf44fe
SJ		 5281}
5282
6f8dafde
BVA		 5283/* Release the resources allocated for processing a SCSI command. */
5284static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5285 struct ufshcd_lrb *lrbp)
5286{
5287 struct scsi_cmnd *cmd = lrbp->cmd;
5288
5289 scsi_dma_unmap(cmd);
5290 lrbp->cmd = NULL; /* Mark the command as completed. */
5291 ufshcd_release(hba);
5292 ufshcd_clk_scaling_update_busy(hba);
5293}
5294
7a3e97b0 5295/**
9a47ec7c 5296 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 5297 * @hba: per adapter instance
73dc3c4a 5298 * @completed_reqs: bitmask that indicates which requests to complete
7a3e97b0 5299 */
9a47ec7c 5300static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
11682523 5301 unsigned long completed_reqs)
7a3e97b0 5302{
5a0b0cb9
SRT		 5303 struct ufshcd_lrb *lrbp;
5304 struct scsi_cmnd *cmd;
7a3e97b0 5305 int index;
e9d501b1 5306
e9d501b1
DR		 5307 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5308 lrbp = &hba->lrb[index];
a3170376 5309 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 5310 cmd = lrbp->cmd;
5311 if (cmd) {
1d8613a2
CG		 5312 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5313 ufshcd_update_monitor(hba, lrbp);
28fa68fc 5314 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
6f8dafde
BVA		 5315 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
5316 ufshcd_release_scsi_cmd(hba, lrbp);
e9d501b1 5317 /* Do not touch lrbp after scsi done */
35c3730a 5318 scsi_done(cmd);
300bb13f
JP		 5319 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5320 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 5321 if (hba->dev_cmd.complete) {
5322 ufshcd_add_command_trace(hba, index,
28fa68fc 5323 UFS_DEV_COMP);
e9d501b1 5324 complete(hba->dev_cmd.complete);
3eb9dcc0 5325 ufshcd_clk_scaling_update_busy(hba);
1a07f2d9 5326 }
e9d501b1
DR		 5327 }
5328 }
7a3e97b0
SY		 5329}
5330
eaab9b57
BVA		 5331/*
5332 * Returns > 0 if one or more commands have been completed or 0 if no
5333 * requests have been completed.
5334 */
5335static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5336{
5337 struct ufs_hba *hba = shost_priv(shost);
5338 unsigned long completed_reqs, flags;
5339 u32 tr_doorbell;
5340
5341 spin_lock_irqsave(&hba->outstanding_lock, flags);
5342 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5343 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5344 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5345 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5346 hba->outstanding_reqs);
5347 hba->outstanding_reqs &= ~completed_reqs;
5348 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5349
5350 if (completed_reqs)
5351 __ufshcd_transfer_req_compl(hba, completed_reqs);
5352
5353 return completed_reqs;
5354}
5355
9a47ec7c 5356/**
1f522c50 5357 * ufshcd_transfer_req_compl - handle SCSI and query command completion
9a47ec7c 5358 * @hba: per adapter instance
9333d775
VG		 5359 *
5360 * Returns
5361 * IRQ_HANDLED - If interrupt is valid
5362 * IRQ_NONE - If invalid interrupt
9a47ec7c 5363 */
11682523 5364static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c 5365{
9a47ec7c
YG		 5366 /* Resetting interrupt aggregation counters first and reading the
5367 * DOOR_BELL afterward allows us to handle all the completed requests.
5368 * In order to prevent other interrupts starvation the DB is read once
5369 * after reset. The down side of this solution is the possibility of
5370 * false interrupt if device completes another request after resetting
5371 * aggregation and before reading the DB.
5372 */
b638b5eb
AA		 5373 if (ufshcd_is_intr_aggr_allowed(hba) &&
5374 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 5375 ufshcd_reset_intr_aggr(hba);
5376
c11a1ae9
BVA		 5377 if (ufs_fail_completion())
5378 return IRQ_HANDLED;
5379
eaab9b57
BVA		 5380 /*
5381 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5382 * do not want polling to trigger spurious interrupt complaints.
5383 */
5384 ufshcd_poll(hba->host, 0);
9a47ec7c 5385
eaab9b57 5386 return IRQ_HANDLED;
9a47ec7c
YG		 5387}
5388
7deedfda 5389int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
cd469475
AH		 5390{
5391 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5392 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5393 &ee_ctrl_mask);
5394}
5395
7deedfda 5396int ufshcd_write_ee_control(struct ufs_hba *hba)
cd469475
AH		 5397{
5398 int err;
5399
5400 mutex_lock(&hba->ee_ctrl_mutex);
5401 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5402 mutex_unlock(&hba->ee_ctrl_mutex);
5403 if (err)
5404 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5405 __func__, err);
5406 return err;
5407}
5408
5409int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5410 u16 set, u16 clr)
5411{
5412 u16 new_mask, ee_ctrl_mask;
5413 int err = 0;
5414
5415 mutex_lock(&hba->ee_ctrl_mutex);
5416 new_mask = (*mask & ~clr) | set;
5417 ee_ctrl_mask = new_mask | *other_mask;
5418 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5419 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5420 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5421 if (!err) {
5422 hba->ee_ctrl_mask = ee_ctrl_mask;
5423 *mask = new_mask;
5424 }
5425 mutex_unlock(&hba->ee_ctrl_mutex);
5426 return err;
5427}
5428
66ec6d59
SRT		 5429/**
5430 * ufshcd_disable_ee - disable exception event
5431 * @hba: per-adapter instance
5432 * @mask: exception event to disable
5433 *
5434 * Disables exception event in the device so that the EVENT_ALERT
5435 * bit is not set.
5436 *
5437 * Returns zero on success, non-zero error value on failure.
5438 */
cd469475 5439static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5440{
cd469475 5441 return ufshcd_update_ee_drv_mask(hba, 0, mask);
66ec6d59
SRT		 5442}
5443
5444/**
5445 * ufshcd_enable_ee - enable exception event
5446 * @hba: per-adapter instance
5447 * @mask: exception event to enable
5448 *
5449 * Enable corresponding exception event in the device to allow
5450 * device to alert host in critical scenarios.
5451 *
5452 * Returns zero on success, non-zero error value on failure.
5453 */
cd469475 5454static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5455{
cd469475 5456 return ufshcd_update_ee_drv_mask(hba, mask, 0);
66ec6d59
SRT		 5457}
5458
5459/**
5460 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5461 * @hba: per-adapter instance
5462 *
5463 * Allow device to manage background operations on its own. Enabling
5464 * this might lead to inconsistent latencies during normal data transfers
5465 * as the device is allowed to manage its own way of handling background
5466 * operations.
5467 *
5468 * Returns zero on success, non-zero on failure.
5469 */
5470static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5471{
5472 int err = 0;
5473
5474 if (hba->auto_bkops_enabled)
5475 goto out;
5476
dc3c8d3a 5477 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 5478 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5479 if (err) {
5480 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5481 __func__, err);
5482 goto out;
5483 }
5484
5485 hba->auto_bkops_enabled = true;
7ff5ab47 5486 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5487
5488 /* No need of URGENT_BKOPS exception from the device */
5489 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5490 if (err)
5491 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5492 __func__, err);
5493out:
5494 return err;
5495}
5496
5497/**
5498 * ufshcd_disable_auto_bkops - block device in doing background operations
5499 * @hba: per-adapter instance
5500 *
5501 * Disabling background operations improves command response latency but
5502 * has drawback of device moving into critical state where the device is
5503 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5504 * host is idle so that BKOPS are managed effectively without any negative
5505 * impacts.
5506 *
5507 * Returns zero on success, non-zero on failure.
5508 */
5509static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5510{
5511 int err = 0;
5512
5513 if (!hba->auto_bkops_enabled)
5514 goto out;
5515
5516 /*
5517 * If host assisted BKOPs is to be enabled, make sure
5518 * urgent bkops exception is allowed.
5519 */
5520 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5521 if (err) {
5522 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5523 __func__, err);
5524 goto out;
5525 }
5526
dc3c8d3a 5527 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
1f34eedf 5528 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5529 if (err) {
5530 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5531 __func__, err);
5532 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5533 goto out;
5534 }
5535
5536 hba->auto_bkops_enabled = false;
7ff5ab47 5537 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5538 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5539out:
5540 return err;
5541}
5542
5543/**
4e768e76 5544 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5545 * @hba: per adapter instance
5546 *
5547 * After a device reset the device may toggle the BKOPS_EN flag
5548 * to default value. The s/w tracking variables should be updated
4e768e76 5549 * as well. This function would change the auto-bkops state based on
5550 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5551 */
4e768e76 5552static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5553{
4e768e76 5554 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5555 hba->auto_bkops_enabled = false;
5556 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5557 ufshcd_enable_auto_bkops(hba);
5558 } else {
5559 hba->auto_bkops_enabled = true;
5560 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5561 ufshcd_disable_auto_bkops(hba);
5562 }
7b6668d8 5563 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
24366c2a 5564 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5565}
5566
5567static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5568{
5e86ae44 5569 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5570 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5571}
5572
5573/**
57d104c1 5574 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5575 * @hba: per-adapter instance
57d104c1 5576 * @status: bkops_status value
66ec6d59 5577 *
57d104c1
SJ		 5578 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5579 * flag in the device to permit background operations if the device
5580 * bkops_status is greater than or equal to "status" argument passed to
5581 * this function, disable otherwise.
5582 *
5583 * Returns 0 for success, non-zero in case of failure.
5584 *
5585 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5586 * to know whether auto bkops is enabled or disabled after this function
5587 * returns control to it.
66ec6d59 5588 */
57d104c1
SJ		 5589static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5590 enum bkops_status status)
66ec6d59
SRT		 5591{
5592 int err;
57d104c1 5593 u32 curr_status = 0;
66ec6d59 5594
57d104c1 5595 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5596 if (err) {
5597 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5598 __func__, err);
5599 goto out;
57d104c1
SJ		 5600 } else if (curr_status > BKOPS_STATUS_MAX) {
5601 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5602 __func__, curr_status);
5603 err = -EINVAL;
5604 goto out;
66ec6d59
SRT		 5605 }
5606
57d104c1 5607 if (curr_status >= status)
66ec6d59 5608 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5609 else
5610 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5611out:
5612 return err;
5613}
5614
57d104c1
SJ		 5615/**
5616 * ufshcd_urgent_bkops - handle urgent bkops exception event
5617 * @hba: per-adapter instance
5618 *
5619 * Enable fBackgroundOpsEn flag in the device to permit background
5620 * operations.
5621 *
5622 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5623 * and negative error value for any other failure.
5624 */
5625static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5626{
afdfff59 5627 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5628}
5629
66ec6d59
SRT		 5630static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5631{
5e86ae44 5632 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5633 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5634}
5635
afdfff59
YG		 5636static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5637{
5638 int err;
5639 u32 curr_status = 0;
5640
5641 if (hba->is_urgent_bkops_lvl_checked)
5642 goto enable_auto_bkops;
5643
5644 err = ufshcd_get_bkops_status(hba, &curr_status);
5645 if (err) {
5646 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5647 __func__, err);
5648 goto out;
5649 }
5650
5651 /*
5652 * We are seeing that some devices are raising the urgent bkops
5653 * exception events even when BKOPS status doesn't indicate performace
5654 * impacted or critical. Handle these device by determining their urgent
5655 * bkops status at runtime.
5656 */
5657 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5658 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5659 __func__, curr_status);
5660 /* update the current status as the urgent bkops level */
5661 hba->urgent_bkops_lvl = curr_status;
5662 hba->is_urgent_bkops_lvl_checked = true;
5663 }
5664
5665enable_auto_bkops:
5666 err = ufshcd_enable_auto_bkops(hba);
5667out:
5668 if (err < 0)
5669 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5670 __func__, err);
5671}
5672
322c4b29
AA		 5673static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5674{
5675 u32 value;
5676
5677 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5678 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5679 return;
5680
5681 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5682
5683 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5684
5685 /*
5686 * A placeholder for the platform vendors to add whatever additional
5687 * steps required
5688 */
5689}
5690
3b5f3c0d 5691static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
3d17b9b5 5692{
6f8d5a6a 5693 u8 index;
3b5f3c0d
YH		 5694 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5695 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5696
5697 index = ufshcd_wb_get_query_index(hba);
5698 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5699}
5700
5701int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5702{
5703 int ret;
3d17b9b5 5704
79e3520f 5705 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 5706 return 0;
5707
4cd48995 5708 if (!(enable ^ hba->dev_info.wb_enabled))
3d17b9b5 5709 return 0;
3d17b9b5 5710
3b5f3c0d 5711 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
3d17b9b5 5712 if (ret) {
3b5f3c0d 5713 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
3d17b9b5
AD		 5714 __func__, enable ? "enable" : "disable", ret);
5715 return ret;
5716 }
5717
4cd48995 5718 hba->dev_info.wb_enabled = enable;
3b5f3c0d
YH		 5719 dev_info(hba->dev, "%s Write Booster %s\n",
5720 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5721
5722 return ret;
5723}
5724
3b5f3c0d 5725static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
3d17b9b5 5726{
3b5f3c0d 5727 int ret;
3d17b9b5 5728
3b5f3c0d
YH		 5729 ret = __ufshcd_wb_toggle(hba, set,
5730 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5731 if (ret) {
5732 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5733 __func__, set ? "enable" : "disable", ret);
5734 return;
5735 }
5736 dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5737 __func__, set ? "enabled" : "disabled");
3d17b9b5
AD		 5738}
5739
3b5f3c0d 5740static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
3d17b9b5
AD		 5741{
5742 int ret;
5743
d3ba622d
BH		 5744 if (!ufshcd_is_wb_allowed(hba) ||
5745 hba->dev_info.wb_buf_flush_enabled == enable)
3b5f3c0d 5746 return;
3d17b9b5 5747
3b5f3c0d 5748 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
3d17b9b5 5749 if (ret) {
d3ba622d
BH		 5750 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5751 enable ? "enable" : "disable", ret);
3b5f3c0d 5752 return;
3d17b9b5
AD		 5753 }
5754
d3ba622d
BH		 5755 hba->dev_info.wb_buf_flush_enabled = enable;
5756
3b5f3c0d
YH		 5757 dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5758 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5759}
5760
5761static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5762 u32 avail_buf)
5763{
5764 u32 cur_buf;
5765 int ret;
e31011ab 5766 u8 index;
3d17b9b5 5767
e31011ab 5768 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5769 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5770 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
e31011ab 5771 index, 0, &cur_buf);
3d17b9b5
AD		 5772 if (ret) {
5773 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5774 __func__, ret);
5775 return false;
5776 }
5777
5778 if (!cur_buf) {
5779 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5780 cur_buf);
5781 return false;
5782 }
d14734ae
SC		 5783 /* Let it continue to flush when available buffer exceeds threshold */
5784 if (avail_buf < hba->vps->wb_flush_threshold)
3d17b9b5
AD		 5785 return true;
5786
5787 return false;
5788}
5789
f681d107
JC		 5790static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5791{
5792 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
5793 ufshcd_wb_toggle_flush(hba, false);
5794
5795 ufshcd_wb_toggle_flush_during_h8(hba, false);
5796 ufshcd_wb_toggle(hba, false);
5797 hba->caps &= ~UFSHCD_CAP_WB_EN;
5798
5799 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5800}
5801
5802static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5803{
5804 u32 lifetime;
5805 int ret;
5806 u8 index;
5807
5808 index = ufshcd_wb_get_query_index(hba);
5809 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5810 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5811 index, 0, &lifetime);
5812 if (ret) {
5813 dev_err(hba->dev,
5814 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
5815 __func__, ret);
5816 return false;
5817 }
5818
5819 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
5820 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
5821 __func__, lifetime);
5822 return false;
5823 }
5824
5825 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
5826 __func__, lifetime);
5827
5828 return true;
5829}
5830
51dd905b 5831static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
3d17b9b5
AD		 5832{
5833 int ret;
5834 u32 avail_buf;
e31011ab 5835 u8 index;
3d17b9b5 5836
79e3520f 5837 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5 5838 return false;
f681d107
JC		 5839
5840 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
5841 ufshcd_wb_force_disable(hba);
5842 return false;
5843 }
5844
3d17b9b5
AD		 5845 /*
5846 * The ufs device needs the vcc to be ON to flush.
5847 * With user-space reduction enabled, it's enough to enable flush
5848 * by checking only the available buffer. The threshold
5849 * defined here is > 90% full.
5850 * With user-space preserved enabled, the current-buffer
5851 * should be checked too because the wb buffer size can reduce
5852 * when disk tends to be full. This info is provided by current
5853 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5854 * keeping vcc on when current buffer is empty.
5855 */
e31011ab 5856 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5857 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5858 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
e31011ab 5859 index, 0, &avail_buf);
3d17b9b5
AD		 5860 if (ret) {
5861 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5862 __func__, ret);
5863 return false;
5864 }
5865
5866 if (!hba->dev_info.b_presrv_uspc_en) {
d14734ae 5867 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
3d17b9b5
AD		 5868 return true;
5869 return false;
5870 }
5871
5872 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5873}
5874
51dd905b
SC		 5875static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5876{
5877 struct ufs_hba *hba = container_of(to_delayed_work(work),
5878 struct ufs_hba,
5879 rpm_dev_flush_recheck_work);
5880 /*
5881 * To prevent unnecessary VCC power drain after device finishes
5882 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5883 * after a certain delay to recheck the threshold by next runtime
5884 * suspend.
5885 */
b294ff3e
AD		 5886 ufshcd_rpm_get_sync(hba);
5887 ufshcd_rpm_put_sync(hba);
51dd905b
SC		 5888}
5889
66ec6d59
SRT		 5890/**
5891 * ufshcd_exception_event_handler - handle exceptions raised by device
5892 * @work: pointer to work data
5893 *
5894 * Read bExceptionEventStatus attribute from the device and handle the
5895 * exception event accordingly.
5896 */
5897static void ufshcd_exception_event_handler(struct work_struct *work)
5898{
5899 struct ufs_hba *hba;
5900 int err;
5901 u32 status = 0;
5902 hba = container_of(work, struct ufs_hba, eeh_work);
5903
03e1d28e 5904 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5905 err = ufshcd_get_ee_status(hba, &status);
5906 if (err) {
5907 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5908 __func__, err);
5909 goto out;
5910 }
5911
f7733625
AH		 5912 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5913
cd469475 5914 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
afdfff59
YG		 5915 ufshcd_bkops_exception_event_handler(hba);
5916
322c4b29
AA		 5917 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
5918 ufshcd_temp_exception_event_handler(hba, status);
5919
7deedfda 5920 ufs_debugfs_exception_event(hba, status);
66ec6d59 5921out:
03e1d28e 5922 ufshcd_scsi_unblock_requests(hba);
66ec6d59
SRT		 5923}
5924
9a47ec7c
YG		 5925/* Complete requests that have door-bell cleared */
5926static void ufshcd_complete_requests(struct ufs_hba *hba)
5927{
11682523 5928 ufshcd_transfer_req_compl(hba);
9a47ec7c
YG		 5929 ufshcd_tmc_handler(hba);
5930}
5931
583fa62d
YG		 5932/**
5933 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5934 * to recover from the DL NAC errors or not.
5935 * @hba: per-adapter instance
5936 *
5937 * Returns true if error handling is required, false otherwise
5938 */
5939static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5940{
5941 unsigned long flags;
5942 bool err_handling = true;
5943
5944 spin_lock_irqsave(hba->host->host_lock, flags);
5945 /*
5946 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5947 * device fatal error and/or DL NAC & REPLAY timeout errors.
5948 */
5949 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5950 goto out;
5951
5952 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5953 ((hba->saved_err & UIC_ERROR) &&
5954 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5955 goto out;
5956
5957 if ((hba->saved_err & UIC_ERROR) &&
5958 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5959 int err;
5960 /*
5961 * wait for 50ms to see if we can get any other errors or not.
5962 */
5963 spin_unlock_irqrestore(hba->host->host_lock, flags);
5964 msleep(50);
5965 spin_lock_irqsave(hba->host->host_lock, flags);
5966
5967 /*
5968 * now check if we have got any other severe errors other than
5969 * DL NAC error?
5970 */
5971 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5972 ((hba->saved_err & UIC_ERROR) &&
5973 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5974 goto out;
5975
5976 /*
5977 * As DL NAC is the only error received so far, send out NOP
5978 * command to confirm if link is still active or not.
5979 * - If we don't get any response then do error recovery.
5980 * - If we get response then clear the DL NAC error bit.
5981 */
5982
5983 spin_unlock_irqrestore(hba->host->host_lock, flags);
5984 err = ufshcd_verify_dev_init(hba);
5985 spin_lock_irqsave(hba->host->host_lock, flags);
5986
5987 if (err)
5988 goto out;
5989
5990 /* Link seems to be alive hence ignore the DL NAC errors */
5991 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5992 hba->saved_err &= ~UIC_ERROR;
5993 /* clear NAC error */
5994 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
b0008625 5995 if (!hba->saved_uic_err)
583fa62d 5996 err_handling = false;
583fa62d
YG		 5997 }
5998out:
5999 spin_unlock_irqrestore(hba->host->host_lock, flags);
6000 return err_handling;
6001}
6002
88b09900
AH		 6003/* host lock must be held before calling this func */
6004static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6005{
6006 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6007 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6008}
6009
267a59f6 6010void ufshcd_schedule_eh_work(struct ufs_hba *hba)
88b09900 6011{
267a59f6
BVA		 6012 lockdep_assert_held(hba->host->host_lock);
6013
88b09900
AH		 6014 /* handle fatal errors only when link is not in error state */
6015 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6016 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6017 ufshcd_is_saved_err_fatal(hba))
6018 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6019 else
6020 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6021 queue_work(hba->eh_wq, &hba->eh_work);
6022 }
6023}
6024
348e1bc5
SC		 6025static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6026{
6027 down_write(&hba->clk_scaling_lock);
6028 hba->clk_scaling.is_allowed = allow;
6029 up_write(&hba->clk_scaling_lock);
6030}
6031
6032static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6033{
6034 if (suspend) {
6035 if (hba->clk_scaling.is_enabled)
6036 ufshcd_suspend_clkscaling(hba);
6037 ufshcd_clk_scaling_allow(hba, false);
6038 } else {
6039 ufshcd_clk_scaling_allow(hba, true);
6040 if (hba->clk_scaling.is_enabled)
6041 ufshcd_resume_clkscaling(hba);
6042 }
6043}
6044
c72e79c0
CG		 6045static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6046{
b294ff3e
AD		 6047 ufshcd_rpm_get_sync(hba);
6048 if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
6049 hba->is_sys_suspended) {
88a92d6a
CG		 6050 enum ufs_pm_op pm_op;
6051
c72e79c0 6052 /*
b294ff3e 6053 * Don't assume anything of resume, if
c72e79c0
CG		 6054 * resume fails, irq and clocks can be OFF, and powers
6055 * can be OFF or in LPM.
6056 */
6057 ufshcd_setup_hba_vreg(hba, true);
6058 ufshcd_enable_irq(hba);
6059 ufshcd_setup_vreg(hba, true);
6060 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6061 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6062 ufshcd_hold(hba, false);
6063 if (!ufshcd_is_clkgating_allowed(hba))
6064 ufshcd_setup_clocks(hba, true);
6065 ufshcd_release(hba);
88a92d6a
CG		 6066 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6067 ufshcd_vops_resume(hba, pm_op);
c72e79c0
CG		 6068 } else {
6069 ufshcd_hold(hba, false);
348e1bc5
SC		 6070 if (ufshcd_is_clkscaling_supported(hba) &&
6071 hba->clk_scaling.is_enabled)
c72e79c0 6072 ufshcd_suspend_clkscaling(hba);
348e1bc5 6073 ufshcd_clk_scaling_allow(hba, false);
c72e79c0 6074 }
aa53f580
CG		 6075 ufshcd_scsi_block_requests(hba);
6076 /* Drain ufshcd_queuecommand() */
5675c381 6077 synchronize_rcu();
aa53f580 6078 cancel_work_sync(&hba->eeh_work);
c72e79c0
CG		 6079}
6080
6081static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6082{
aa53f580 6083 ufshcd_scsi_unblock_requests(hba);
c72e79c0 6084 ufshcd_release(hba);
348e1bc5
SC		 6085 if (ufshcd_is_clkscaling_supported(hba))
6086 ufshcd_clk_scaling_suspend(hba, false);
b294ff3e 6087 ufshcd_rpm_put(hba);
c72e79c0
CG		 6088}
6089
6090static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6091{
9cd20d3f 6092 return (!hba->is_powered || hba->shutting_down ||
b294ff3e 6093 !hba->sdev_ufs_device ||
9cd20d3f 6094 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
c72e79c0 6095 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
9cd20d3f 6096 ufshcd_is_link_broken(hba))));
c72e79c0
CG		 6097}
6098
6099#ifdef CONFIG_PM
6100static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6101{
6102 struct Scsi_Host *shost = hba->host;
6103 struct scsi_device *sdev;
6104 struct request_queue *q;
6105 int ret;
6106
88a92d6a 6107 hba->is_sys_suspended = false;
c72e79c0 6108 /*
b294ff3e 6109 * Set RPM status of wlun device to RPM_ACTIVE,
c72e79c0
CG		 6110 * this also clears its runtime error.
6111 */
b294ff3e
AD		 6112 ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
6113
6114 /* hba device might have a runtime error otherwise */
6115 if (ret)
6116 ret = pm_runtime_set_active(hba->dev);
c72e79c0 6117 /*
b294ff3e
AD		 6118 * If wlun device had runtime error, we also need to resume those
6119 * consumer scsi devices in case any of them has failed to be
6120 * resumed due to supplier runtime resume failure. This is to unblock
c72e79c0
CG		 6121 * blk_queue_enter in case there are bios waiting inside it.
6122 */
6123 if (!ret) {
6124 shost_for_each_device(sdev, shost) {
6125 q = sdev->request_queue;
6126 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6127 q->rpm_status == RPM_SUSPENDING))
6128 pm_request_resume(q->dev);
6129 }
6130 }
6131}
6132#else
6133static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6134{
6135}
6136#endif
6137
2355b66e
CG		 6138static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6139{
6140 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6141 u32 mode;
6142
6143 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6144
6145 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6146 return true;
6147
6148 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6149 return true;
6150
6151 return false;
6152}
6153
7a3e97b0 6154/**
e8e7f271 6155 * ufshcd_err_handler - handle UFS errors that require s/w attention
88b09900 6156 * @work: pointer to work structure
7a3e97b0 6157 */
88b09900 6158static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0 6159{
87bf6a6b 6160 int retries = MAX_ERR_HANDLER_RETRIES;
88b09900 6161 struct ufs_hba *hba;
e8e7f271 6162 unsigned long flags;
87bf6a6b
AH		 6163 bool needs_restore;
6164 bool needs_reset;
6165 bool err_xfer;
6166 bool err_tm;
6167 int pmc_err;
e8e7f271
SRT		 6168 int tag;
6169
88b09900
AH		 6170 hba = container_of(work, struct ufs_hba, eh_work);
6171
4693fad7
BVA		 6172 dev_info(hba->dev,
6173 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6174 __func__, ufshcd_state_name[hba->ufshcd_state],
6175 hba->is_powered, hba->shutting_down, hba->saved_err,
6176 hba->saved_uic_err, hba->force_reset,
6177 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6178
9cd20d3f 6179 down(&hba->host_sem);
e8e7f271 6180 spin_lock_irqsave(hba->host->host_lock, flags);
c72e79c0 6181 if (ufshcd_err_handling_should_stop(hba)) {
4db7a236
CG		 6182 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6183 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6184 spin_unlock_irqrestore(hba->host->host_lock, flags);
9cd20d3f 6185 up(&hba->host_sem);
4db7a236
CG		 6186 return;
6187 }
6188 ufshcd_set_eh_in_progress(hba);
6189 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6190 ufshcd_err_handling_prepare(hba);
a45f9371
CG		 6191 /* Complete requests that have door-bell cleared by h/w */
6192 ufshcd_complete_requests(hba);
e8e7f271 6193 spin_lock_irqsave(hba->host->host_lock, flags);
87bf6a6b
AH		 6194again:
6195 needs_restore = false;
6196 needs_reset = false;
6197 err_xfer = false;
6198 err_tm = false;
6199
aa53f580
CG		 6200 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6201 hba->ufshcd_state = UFSHCD_STATE_RESET;
88a92d6a
CG		 6202 /*
6203 * A full reset and restore might have happened after preparation
6204 * is finished, double check whether we should stop.
6205 */
6206 if (ufshcd_err_handling_should_stop(hba))
6207 goto skip_err_handling;
6208
583fa62d
YG		 6209 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6210 bool ret;
6211
6212 spin_unlock_irqrestore(hba->host->host_lock, flags);
6213 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6214 ret = ufshcd_quirk_dl_nac_errors(hba);
6215 spin_lock_irqsave(hba->host->host_lock, flags);
88a92d6a 6216 if (!ret && ufshcd_err_handling_should_stop(hba))
583fa62d
YG		 6217 goto skip_err_handling;
6218 }
4db7a236 6219
2355b66e
CG		 6220 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6221 (hba->saved_uic_err &&
6222 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
c3be8d1e
CG		 6223 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6224
6225 spin_unlock_irqrestore(hba->host->host_lock, flags);
6226 ufshcd_print_host_state(hba);
6227 ufshcd_print_pwr_info(hba);
e965e5e0 6228 ufshcd_print_evt_hist(hba);
c3be8d1e
CG		 6229 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6230 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6231 spin_lock_irqsave(hba->host->host_lock, flags);
6232 }
6233
9a47ec7c
YG		 6234 /*
6235 * if host reset is required then skip clearing the pending
2df74b69
CG		 6236 * transfers forcefully because they will get cleared during
6237 * host reset and restore
9a47ec7c 6238 */
88a92d6a
CG		 6239 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6240 ufshcd_is_saved_err_fatal(hba) ||
6241 ((hba->saved_err & UIC_ERROR) &&
6242 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6243 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6244 needs_reset = true;
2355b66e 6245 goto do_reset;
88a92d6a 6246 }
9a47ec7c 6247
2355b66e
CG		 6248 /*
6249 * If LINERESET was caught, UFS might have been put to PWM mode,
6250 * check if power mode restore is needed.
6251 */
6252 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6253 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6254 if (!hba->saved_uic_err)
6255 hba->saved_err &= ~UIC_ERROR;
6256 spin_unlock_irqrestore(hba->host->host_lock, flags);
6257 if (ufshcd_is_pwr_mode_restore_needed(hba))
6258 needs_restore = true;
6259 spin_lock_irqsave(hba->host->host_lock, flags);
6260 if (!hba->saved_err && !needs_restore)
6261 goto skip_err_handling;
6262 }
9a47ec7c 6263
2355b66e 6264 hba->silence_err_logs = true;
9a47ec7c
YG		 6265 /* release lock as clear command might sleep */
6266 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6267 /* Clear pending transfer requests */
9a47ec7c 6268 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
307348f6 6269 if (ufshcd_try_to_abort_task(hba, tag)) {
9a47ec7c
YG		 6270 err_xfer = true;
6271 goto lock_skip_pending_xfer_clear;
6272 }
4693fad7
BVA		 6273 dev_err(hba->dev, "Aborted tag %d / CDB %#02x\n", tag,
6274 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1);
9a47ec7c 6275 }
e8e7f271
SRT		 6276
6277 /* Clear pending task management requests */
9a47ec7c
YG		 6278 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6279 if (ufshcd_clear_tm_cmd(hba, tag)) {
6280 err_tm = true;
6281 goto lock_skip_pending_xfer_clear;
6282 }
6283 }
e8e7f271 6284
9a47ec7c 6285lock_skip_pending_xfer_clear:
11682523
BVA		 6286 /* Complete the requests that are cleared by s/w */
6287 ufshcd_complete_requests(hba);
9a47ec7c 6288
a45f9371
CG		 6289 spin_lock_irqsave(hba->host->host_lock, flags);
6290 hba->silence_err_logs = false;
2355b66e 6291 if (err_xfer || err_tm) {
9a47ec7c 6292 needs_reset = true;
2355b66e
CG		 6293 goto do_reset;
6294 }
9a47ec7c 6295
2355b66e
CG		 6296 /*
6297 * After all reqs and tasks are cleared from doorbell,
6298 * now it is safe to retore power mode.
6299 */
6300 if (needs_restore) {
6301 spin_unlock_irqrestore(hba->host->host_lock, flags);
6302 /*
6303 * Hold the scaling lock just in case dev cmds
6304 * are sent via bsg and/or sysfs.
6305 */
6306 down_write(&hba->clk_scaling_lock);
6307 hba->force_pmc = true;
6308 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6309 if (pmc_err) {
6310 needs_reset = true;
6311 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6312 __func__, pmc_err);
6313 }
6314 hba->force_pmc = false;
6315 ufshcd_print_pwr_info(hba);
6316 up_write(&hba->clk_scaling_lock);
6317 spin_lock_irqsave(hba->host->host_lock, flags);
6318 }
9a47ec7c 6319
2355b66e 6320do_reset:
e8e7f271 6321 /* Fatal errors need reset */
9a47ec7c 6322 if (needs_reset) {
87bf6a6b
AH		 6323 int err;
6324
4db7a236 6325 hba->force_reset = false;
9a47ec7c 6326 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6327 err = ufshcd_reset_and_restore(hba);
4db7a236
CG		 6328 if (err)
6329 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6330 __func__, err);
c72e79c0
CG		 6331 else
6332 ufshcd_recover_pm_error(hba);
9a47ec7c 6333 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6334 }
9a47ec7c 6335
583fa62d 6336skip_err_handling:
9a47ec7c 6337 if (!needs_reset) {
4db7a236
CG		 6338 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6339 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
9a47ec7c
YG		 6340 if (hba->saved_err || hba->saved_uic_err)
6341 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6342 __func__, hba->saved_err, hba->saved_uic_err);
6343 }
87bf6a6b
AH		 6344 /* Exit in an operational state or dead */
6345 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6346 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6347 if (--retries)
6348 goto again;
6349 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6350 }
e8e7f271 6351 ufshcd_clear_eh_in_progress(hba);
9a47ec7c 6352 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6353 ufshcd_err_handling_unprepare(hba);
9cd20d3f 6354 up(&hba->host_sem);
4693fad7
BVA		 6355
6356 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6357 ufshcd_state_name[hba->ufshcd_state]);
7a3e97b0
SY		 6358}
6359
6360/**
e8e7f271
SRT		 6361 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6362 * @hba: per-adapter instance
9333d775
VG		 6363 *
6364 * Returns
6365 * IRQ_HANDLED - If interrupt is valid
6366 * IRQ_NONE - If invalid interrupt
7a3e97b0 6367 */
9333d775 6368static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 6369{
6370 u32 reg;
9333d775 6371 irqreturn_t retval = IRQ_NONE;
7a3e97b0 6372
2355b66e 6373 /* PHY layer error */
fb7b45f0 6374 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
fb7b45f0 6375 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
2355b66e 6376 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6377 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
fb7b45f0
DR		 6378 /*
6379 * To know whether this error is fatal or not, DB timeout
6380 * must be checked but this error is handled separately.
6381 */
2355b66e
CG		 6382 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6383 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6384 __func__);
6385
6386 /* Got a LINERESET indication. */
6387 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6388 struct uic_command *cmd = NULL;
6389
6390 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6391 if (hba->uic_async_done && hba->active_uic_cmd)
6392 cmd = hba->active_uic_cmd;
6393 /*
6394 * Ignore the LINERESET during power mode change
6395 * operation via DME_SET command.
6396 */
6397 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6398 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6399 }
9333d775 6400 retval |= IRQ_HANDLED;
ff8e20c6 6401 }
fb7b45f0 6402
e8e7f271
SRT		 6403 /* PA_INIT_ERROR is fatal and needs UIC reset */
6404 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 6405 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6406 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6407 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
ff8e20c6 6408
9333d775
VG		 6409 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6410 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6411 else if (hba->dev_quirks &
6412 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6413 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6414 hba->uic_error |=
6415 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6416 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6417 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6418 }
6419 retval |= IRQ_HANDLED;
583fa62d 6420 }
e8e7f271
SRT		 6421
6422 /* UIC NL/TL/DME errors needs software retry */
6423 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 6424 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6425 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6426 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
e8e7f271 6427 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 6428 retval |= IRQ_HANDLED;
ff8e20c6 6429 }
e8e7f271
SRT		 6430
6431 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 6432 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6433 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6434 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
e8e7f271 6435 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 6436 retval |= IRQ_HANDLED;
ff8e20c6 6437 }
e8e7f271
SRT		 6438
6439 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 6440 if ((reg & UIC_DME_ERROR) &&
6441 (reg & UIC_DME_ERROR_CODE_MASK)) {
e965e5e0 6442 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
e8e7f271 6443 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 6444 retval |= IRQ_HANDLED;
ff8e20c6 6445 }
e8e7f271
SRT		 6446
6447 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6448 __func__, hba->uic_error);
9333d775 6449 return retval;
e8e7f271
SRT		 6450}
6451
6452/**
6453 * ufshcd_check_errors - Check for errors that need s/w attention
6454 * @hba: per-adapter instance
a45f9371 6455 * @intr_status: interrupt status generated by the controller
9333d775
VG		 6456 *
6457 * Returns
6458 * IRQ_HANDLED - If interrupt is valid
6459 * IRQ_NONE - If invalid interrupt
e8e7f271 6460 */
a45f9371 6461static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
e8e7f271
SRT		 6462{
6463 bool queue_eh_work = false;
9333d775 6464 irqreturn_t retval = IRQ_NONE;
e8e7f271 6465
a45f9371
CG		 6466 spin_lock(hba->host->host_lock);
6467 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6468
d3c615bf 6469 if (hba->errors & INT_FATAL_ERRORS) {
e965e5e0
SC		 6470 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6471 hba->errors);
e8e7f271 6472 queue_eh_work = true;
d3c615bf 6473 }
7a3e97b0
SY		 6474
6475 if (hba->errors & UIC_ERROR) {
e8e7f271 6476 hba->uic_error = 0;
9333d775 6477 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 6478 if (hba->uic_error)
6479 queue_eh_work = true;
7a3e97b0 6480 }
e8e7f271 6481
82174440
SC		 6482 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6483 dev_err(hba->dev,
6484 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6485 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6486 "Enter" : "Exit",
6487 hba->errors, ufshcd_get_upmcrs(hba));
e965e5e0 6488 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
d3c615bf 6489 hba->errors);
4db7a236 6490 ufshcd_set_link_broken(hba);
82174440
SC		 6491 queue_eh_work = true;
6492 }
6493
e8e7f271 6494 if (queue_eh_work) {
9a47ec7c
YG		 6495 /*
6496 * update the transfer error masks to sticky bits, let's do this
6497 * irrespective of current ufshcd_state.
6498 */
6499 hba->saved_err |= hba->errors;
6500 hba->saved_uic_err |= hba->uic_error;
6501
4db7a236 6502 /* dump controller state before resetting */
ace3804b
CG		 6503 if ((hba->saved_err &
6504 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
2355b66e
CG		 6505 (hba->saved_uic_err &&
6506 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
4db7a236 6507 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
66cc820f
DR		 6508 __func__, hba->saved_err,
6509 hba->saved_uic_err);
c3be8d1e
CG		 6510 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6511 "host_regs: ");
4db7a236 6512 ufshcd_print_pwr_info(hba);
e8e7f271 6513 }
88b09900 6514 ufshcd_schedule_eh_work(hba);
9333d775 6515 retval |= IRQ_HANDLED;
3441da7d 6516 }
e8e7f271
SRT		 6517 /*
6518 * if (!queue_eh_work) -
6519 * Other errors are either non-fatal where host recovers
6520 * itself without s/w intervention or errors that will be
6521 * handled by the SCSI core layer.
6522 */
a45f9371
CG		 6523 hba->errors = 0;
6524 hba->uic_error = 0;
6525 spin_unlock(hba->host->host_lock);
9333d775 6526 return retval;
7a3e97b0
SY		 6527}
6528
6529/**
6530 * ufshcd_tmc_handler - handle task management function completion
6531 * @hba: per adapter instance
9333d775
VG		 6532 *
6533 * Returns
6534 * IRQ_HANDLED - If interrupt is valid
6535 * IRQ_NONE - If invalid interrupt
7a3e97b0 6536 */
9333d775 6537static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 6538{
f5ef336f
AH		 6539 unsigned long flags, pending, issued;
6540 irqreturn_t ret = IRQ_NONE;
6541 int tag;
6542
a45f9371 6543 spin_lock_irqsave(hba->host->host_lock, flags);
5cb37a26 6544 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
f5ef336f
AH		 6545 issued = hba->outstanding_tasks & ~pending;
6546 for_each_set_bit(tag, &issued, hba->nutmrs) {
6547 struct request *req = hba->tmf_rqs[tag];
6548 struct completion *c = req->end_io_data;
6549
6550 complete(c);
6551 ret = IRQ_HANDLED;
6552 }
a45f9371
CG		 6553 spin_unlock_irqrestore(hba->host->host_lock, flags);
6554
f5ef336f 6555 return ret;
7a3e97b0
SY		 6556}
6557
6558/**
6559 * ufshcd_sl_intr - Interrupt service routine
6560 * @hba: per adapter instance
6561 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 6562 *
6563 * Returns
6564 * IRQ_HANDLED - If interrupt is valid
6565 * IRQ_NONE - If invalid interrupt
7a3e97b0 6566 */
9333d775 6567static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 6568{
9333d775
VG		 6569 irqreturn_t retval = IRQ_NONE;
6570
53b3d9c3 6571 if (intr_status & UFSHCD_UIC_MASK)
9333d775 6572 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0 6573
a45f9371
CG		 6574 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6575 retval |= ufshcd_check_errors(hba, intr_status);
6576
7a3e97b0 6577 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 6578 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 6579
6580 if (intr_status & UTP_TRANSFER_REQ_COMPL)
11682523 6581 retval |= ufshcd_transfer_req_compl(hba);
9333d775
VG		 6582
6583 return retval;
7a3e97b0
SY		 6584}
6585
6586/**
6587 * ufshcd_intr - Main interrupt service routine
6588 * @irq: irq number
6589 * @__hba: pointer to adapter instance
6590 *
9333d775
VG		 6591 * Returns
6592 * IRQ_HANDLED - If interrupt is valid
6593 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 6594 */
6595static irqreturn_t ufshcd_intr(int irq, void *__hba)
6596{
127d5f7c 6597 u32 intr_status, enabled_intr_status = 0;
7a3e97b0
SY		 6598 irqreturn_t retval = IRQ_NONE;
6599 struct ufs_hba *hba = __hba;
7f6ba4f1 6600 int retries = hba->nutrs;
7a3e97b0 6601
b873a275 6602 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
3f8af604
CG		 6603 hba->ufs_stats.last_intr_status = intr_status;
6604 hba->ufs_stats.last_intr_ts = ktime_get();
7a3e97b0 6605
7f6ba4f1
VG		 6606 /*
6607 * There could be max of hba->nutrs reqs in flight and in worst case
6608 * if the reqs get finished 1 by 1 after the interrupt status is
6609 * read, make sure we handle them by checking the interrupt status
6610 * again in a loop until we process all of the reqs before returning.
6611 */
127d5f7c 6612 while (intr_status && retries--) {
7f6ba4f1
VG		 6613 enabled_intr_status =
6614 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
60ec3755 6615 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 6616 if (enabled_intr_status)
6617 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 6618
6619 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
127d5f7c 6620 }
d75f7fe4 6621
eeb1b55b 6622 if (enabled_intr_status && retval == IRQ_NONE &&
40d2fd05
BVA		 6623 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6624 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
eeb1b55b
JK		 6625 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6626 __func__,
6627 intr_status,
6628 hba->ufs_stats.last_intr_status,
6629 enabled_intr_status);
9333d775
VG		 6630 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6631 }
6632
7a3e97b0
SY		 6633 return retval;
6634}
6635
e2933132
SRT		 6636static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6637{
6638 int err = 0;
6639 u32 mask = 1 << tag;
6640 unsigned long flags;
6641
6642 if (!test_bit(tag, &hba->outstanding_tasks))
6643 goto out;
6644
6645 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 6646 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 6647 spin_unlock_irqrestore(hba->host->host_lock, flags);
6648
6649 /* poll for max. 1 sec to clear door bell register by h/w */
6650 err = ufshcd_wait_for_register(hba,
6651 REG_UTP_TASK_REQ_DOOR_BELL,
5cac1095 6652 mask, 0, 1000, 1000);
4693fad7
BVA		 6653
6654 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6655 tag, err ? "succeeded" : "failed");
6656
e2933132
SRT		 6657out:
6658 return err;
6659}
6660
c6049cd9
CH		 6661static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6662 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 6663{
69a6c269 6664 struct request_queue *q = hba->tmf_queue;
c6049cd9 6665 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 6666 DECLARE_COMPLETION_ONSTACK(wait);
6667 struct request *req;
7a3e97b0 6668 unsigned long flags;
4b42d557 6669 int task_tag, err;
7a3e97b0 6670
e2933132 6671 /*
0bf6d96c 6672 * blk_mq_alloc_request() is used here only to get a free tag.
e2933132 6673 */
0bf6d96c 6674 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
eeb1b55b
JK		 6675 if (IS_ERR(req))
6676 return PTR_ERR(req);
6677
69a6c269 6678 req->end_io_data = &wait;
1ab27c9c 6679 ufshcd_hold(hba, false);
7a3e97b0 6680
e2933132 6681 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0 6682
4b42d557 6683 task_tag = req->tag;
eaab9b57
BVA		 6684 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6685 task_tag);
f5ef336f 6686 hba->tmf_rqs[req->tag] = req;
1352eec8 6687 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
c6049cd9 6688
4b42d557
CG		 6689 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6690 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
d2877be4 6691
7a3e97b0 6692 /* send command to the controller */
4b42d557 6693 __set_bit(task_tag, &hba->outstanding_tasks);
897efe62 6694
4b42d557 6695 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 6696 /* Make sure that doorbell is committed immediately */
6697 wmb();
7a3e97b0
SY		 6698
6699 spin_unlock_irqrestore(host->host_lock, flags);
6700
28fa68fc 6701 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6667e6d9 6702
7a3e97b0 6703 /* wait until the task management command is completed */
69a6c269 6704 err = wait_for_completion_io_timeout(&wait,
e2933132 6705 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 6706 if (!err) {
28fa68fc 6707 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
e2933132
SRT		 6708 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6709 __func__, tm_function);
4b42d557
CG		 6710 if (ufshcd_clear_tm_cmd(hba, task_tag))
6711 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6712 __func__, task_tag);
e2933132
SRT		 6713 err = -ETIMEDOUT;
6714 } else {
c6049cd9 6715 err = 0;
4b42d557 6716 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
c6049cd9 6717
28fa68fc 6718 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7a3e97b0 6719 }
e2933132 6720
b557217c 6721 spin_lock_irqsave(hba->host->host_lock, flags);
f5ef336f 6722 hba->tmf_rqs[req->tag] = NULL;
4b42d557 6723 __clear_bit(task_tag, &hba->outstanding_tasks);
b557217c
SC		 6724 spin_unlock_irqrestore(hba->host->host_lock, flags);
6725
4b42d557 6726 ufshcd_release(hba);
0bf6d96c 6727 blk_mq_free_request(req);
e2933132 6728
7a3e97b0
SY		 6729 return err;
6730}
6731
c6049cd9
CH		 6732/**
6733 * ufshcd_issue_tm_cmd - issues task management commands to controller
6734 * @hba: per adapter instance
6735 * @lun_id: LUN ID to which TM command is sent
6736 * @task_id: task ID to which the TM command is applicable
6737 * @tm_function: task management function opcode
6738 * @tm_response: task management service response return value
6739 *
6740 * Returns non-zero value on error, zero on success.
6741 */
6742static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6743 u8 tm_function, u8 *tm_response)
6744{
6745 struct utp_task_req_desc treq = { { 0 }, };
957d63e7
BVA		 6746 enum utp_ocs ocs_value;
6747 int err;
c6049cd9
CH		 6748
6749 /* Configure task request descriptor */
6750 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6751 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6752
6753 /* Configure task request UPIU */
1352eec8 6754 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
c6049cd9 6755 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
1352eec8 6756 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
c6049cd9
CH		 6757
6758 /*
6759 * The host shall provide the same value for LUN field in the basic
6760 * header and for Input Parameter.
6761 */
1352eec8
GS		 6762 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6763 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
c6049cd9
CH		 6764
6765 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6766 if (err == -ETIMEDOUT)
6767 return err;
6768
6769 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6770 if (ocs_value != OCS_SUCCESS)
6771 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6772 __func__, ocs_value);
6773 else if (tm_response)
1352eec8 6774 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
c6049cd9
CH		 6775 MASK_TM_SERVICE_RESP;
6776 return err;
6777}
6778
5e0a86ee
AA		 6779/**
6780 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6781 * @hba: per-adapter instance
6782 * @req_upiu: upiu request
6783 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6784 * @desc_buff: pointer to descriptor buffer, NULL if NA
6785 * @buff_len: descriptor size, 0 if NA
d0e9760d 6786 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6787 * @desc_op: descriptor operation
6788 *
6789 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6790 * Therefore, it "rides" the device management infrastructure: uses its tag and
6791 * tasks work queues.
6792 *
6793 * Since there is only one available tag for device management commands,
6794 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6795 */
6796static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6797 struct utp_upiu_req *req_upiu,
6798 struct utp_upiu_req *rsp_upiu,
6799 u8 *desc_buff, int *buff_len,
7f674c38 6800 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6801 enum query_opcode desc_op)
6802{
8a686f26 6803 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 6804 const u32 tag = hba->reserved_slot;
5e0a86ee
AA		 6805 struct ufshcd_lrb *lrbp;
6806 int err = 0;
a23064c4 6807 u8 upiu_flags;
5e0a86ee 6808
945c3cca
BVA		 6809 /* Protects use of hba->reserved_slot. */
6810 lockdep_assert_held(&hba->dev_cmd.lock);
5e0a86ee 6811
945c3cca 6812 down_read(&hba->clk_scaling_lock);
5e0a86ee 6813
a45f9371 6814 lrbp = &hba->lrb[tag];
7a7e66c6 6815 WARN_ON(lrbp->cmd);
5e0a86ee
AA		 6816 lrbp->cmd = NULL;
6817 lrbp->sense_bufflen = 0;
6818 lrbp->sense_buffer = NULL;
6819 lrbp->task_tag = tag;
6820 lrbp->lun = 0;
6821 lrbp->intr_cmd = true;
df043c74 6822 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5e0a86ee
AA		 6823 hba->dev_cmd.type = cmd_type;
6824
51428818 6825 if (hba->ufs_version <= ufshci_version(1, 1))
5e0a86ee 6826 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
51428818 6827 else
5e0a86ee 6828 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5e0a86ee
AA		 6829
6830 /* update the task tag in the request upiu */
6831 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6832
6833 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6834
6835 /* just copy the upiu request as it is */
6836 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6837 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6838 /* The Data Segment Area is optional depending upon the query
6839 * function value. for WRITE DESCRIPTOR, the data segment
6840 * follows right after the tsf.
6841 */
6842 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6843 *buff_len = 0;
6844 }
6845
6846 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6847
6848 hba->dev_cmd.complete = &wait;
6849
10542489 6850 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5e0a86ee 6851
a45f9371 6852 ufshcd_send_command(hba, tag);
5e0a86ee
AA		 6853 /*
6854 * ignore the returning value here - ufshcd_check_query_response is
6855 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6856 * read the response directly ignoring all errors.
6857 */
6858 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6859
6860 /* just copy the upiu response as it is */
6861 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6862 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6863 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6864 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6865 MASK_QUERY_DATA_SEG_LEN;
6866
6867 if (*buff_len >= resp_len) {
6868 memcpy(desc_buff, descp, resp_len);
6869 *buff_len = resp_len;
6870 } else {
3d4881d1
BH		 6871 dev_warn(hba->dev,
6872 "%s: rsp size %d is bigger than buffer size %d",
6873 __func__, resp_len, *buff_len);
4bbbe242
AA		 6874 *buff_len = 0;
6875 err = -EINVAL;
6876 }
6877 }
10542489
BH		 6878 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6879 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
5e0a86ee 6880
5e0a86ee
AA		 6881 up_read(&hba->clk_scaling_lock);
6882 return err;
6883}
6884
6885/**
6886 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6887 * @hba: per-adapter instance
6888 * @req_upiu: upiu request
6889 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6890 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6891 * @desc_buff: pointer to descriptor buffer, NULL if NA
6892 * @buff_len: descriptor size, 0 if NA
6893 * @desc_op: descriptor operation
6894 *
6895 * Supports UTP Transfer requests (nop and query), and UTP Task
6896 * Management requests.
6897 * It is up to the caller to fill the upiu conent properly, as it will
6898 * be copied without any further input validations.
6899 */
6900int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6901 struct utp_upiu_req *req_upiu,
6902 struct utp_upiu_req *rsp_upiu,
6903 int msgcode,
6904 u8 *desc_buff, int *buff_len,
6905 enum query_opcode desc_op)
6906{
6907 int err;
7f674c38 6908 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee 6909 struct utp_task_req_desc treq = { { 0 }, };
957d63e7 6910 enum utp_ocs ocs_value;
5e0a86ee
AA		 6911 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6912
5e0a86ee
AA		 6913 switch (msgcode) {
6914 case UPIU_TRANSACTION_NOP_OUT:
6915 cmd_type = DEV_CMD_TYPE_NOP;
df561f66 6916 fallthrough;
5e0a86ee
AA		 6917 case UPIU_TRANSACTION_QUERY_REQ:
6918 ufshcd_hold(hba, false);
6919 mutex_lock(&hba->dev_cmd.lock);
6920 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6921 desc_buff, buff_len,
6922 cmd_type, desc_op);
6923 mutex_unlock(&hba->dev_cmd.lock);
6924 ufshcd_release(hba);
6925
6926 break;
6927 case UPIU_TRANSACTION_TASK_REQ:
6928 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6929 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6930
1352eec8 6931 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
5e0a86ee
AA		 6932
6933 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6934 if (err == -ETIMEDOUT)
6935 break;
6936
6937 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6938 if (ocs_value != OCS_SUCCESS) {
6939 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6940 ocs_value);
6941 break;
6942 }
6943
1352eec8 6944 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
5e0a86ee
AA		 6945
6946 break;
6947 default:
6948 err = -EINVAL;
6949
6950 break;
6951 }
6952
5e0a86ee
AA		 6953 return err;
6954}
6955
7a3e97b0 6956/**
3441da7d
SRT		 6957 * ufshcd_eh_device_reset_handler - device reset handler registered to
6958 * scsi layer.
7a3e97b0
SY		 6959 * @cmd: SCSI command pointer
6960 *
6961 * Returns SUCCESS/FAILED
6962 */
3441da7d 6963static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6964{
6965 struct Scsi_Host *host;
6966 struct ufs_hba *hba;
7a3e97b0
SY		 6967 u32 pos;
6968 int err;
35fc4cd3 6969 u8 resp = 0xF, lun;
7a3e97b0
SY		 6970
6971 host = cmd->device->host;
6972 hba = shost_priv(host);
7a3e97b0 6973
35fc4cd3
CG		 6974 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6975 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
e2933132 6976 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6977 if (!err)
6978 err = resp;
7a3e97b0 6979 goto out;
e2933132 6980 }
7a3e97b0 6981
3441da7d
SRT		 6982 /* clear the commands that were pending for corresponding LUN */
6983 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
35fc4cd3 6984 if (hba->lrb[pos].lun == lun) {
3441da7d
SRT		 6985 err = ufshcd_clear_cmd(hba, pos);
6986 if (err)
6987 break;
11682523 6988 __ufshcd_transfer_req_compl(hba, 1U << pos);
7a3e97b0 6989 }
3441da7d 6990 }
7fabb77b 6991
7a3e97b0 6992out:
7fabb77b 6993 hba->req_abort_count = 0;
e965e5e0 6994 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
3441da7d
SRT		 6995 if (!err) {
6996 err = SUCCESS;
6997 } else {
6998 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6999 err = FAILED;
7000 }
7a3e97b0
SY		 7001 return err;
7002}
7003
e0b299e3
GB		 7004static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7005{
7006 struct ufshcd_lrb *lrbp;
7007 int tag;
7008
7009 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7010 lrbp = &hba->lrb[tag];
7011 lrbp->req_abort_skip = true;
7012 }
7013}
7014
7a3e97b0 7015/**
307348f6 7016 * ufshcd_try_to_abort_task - abort a specific task
d23ec0b6
LJ		 7017 * @hba: Pointer to adapter instance
7018 * @tag: Task tag/index to be aborted
7a3e97b0 7019 *
f20810d8
SRT		 7020 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7021 * command, and in host controller by clearing the door-bell register. There can
7022 * be race between controller sending the command to the device while abort is
7023 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7024 * really issued and then try to abort it.
7025 *
307348f6
CG		 7026 * Returns zero on success, non-zero on failure
7027 */
7028static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7029{
7030 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7031 int err = 0;
7032 int poll_cnt;
7033 u8 resp = 0xF;
7034 u32 reg;
7035
7036 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7037 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7038 UFS_QUERY_TASK, &resp);
7039 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7040 /* cmd pending in the device */
7041 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7042 __func__, tag);
7043 break;
7044 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7045 /*
7046 * cmd not pending in the device, check if it is
7047 * in transition.
7048 */
7049 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7050 __func__, tag);
7051 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7052 if (reg & (1 << tag)) {
7053 /* sleep for max. 200us to stabilize */
7054 usleep_range(100, 200);
7055 continue;
7056 }
7057 /* command completed already */
7058 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7059 __func__, tag);
7060 goto out;
7061 } else {
7062 dev_err(hba->dev,
7063 "%s: no response from device. tag = %d, err %d\n",
7064 __func__, tag, err);
7065 if (!err)
7066 err = resp; /* service response error */
7067 goto out;
7068 }
7069 }
7070
7071 if (!poll_cnt) {
7072 err = -EBUSY;
7073 goto out;
7074 }
7075
7076 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7077 UFS_ABORT_TASK, &resp);
7078 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7079 if (!err) {
7080 err = resp; /* service response error */
7081 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7082 __func__, tag, err);
7083 }
7084 goto out;
7085 }
7086
7087 err = ufshcd_clear_cmd(hba, tag);
7088 if (err)
7089 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7090 __func__, tag, err);
7091
7092out:
7093 return err;
7094}
7095
7096/**
7097 * ufshcd_abort - scsi host template eh_abort_handler callback
7098 * @cmd: SCSI command pointer
7099 *
7a3e97b0
SY		 7100 * Returns SUCCESS/FAILED
7101 */
7102static int ufshcd_abort(struct scsi_cmnd *cmd)
7103{
4728ab4a
BVA		 7104 struct Scsi_Host *host = cmd->device->host;
7105 struct ufs_hba *hba = shost_priv(host);
3f2c1002 7106 int tag = scsi_cmd_to_rq(cmd)->tag;
4728ab4a 7107 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7a3e97b0 7108 unsigned long flags;
64180742 7109 int err = FAILED;
1fbaa02d 7110 bool outstanding;
e9d501b1 7111 u32 reg;
7a3e97b0 7112
4728ab4a 7113 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7a3e97b0 7114
1ab27c9c 7115 ufshcd_hold(hba, false);
14497328 7116 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
64180742 7117 /* If command is already aborted/completed, return FAILED. */
14497328
YG		 7118 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7119 dev_err(hba->dev,
7120 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7121 __func__, tag, hba->outstanding_reqs, reg);
64180742 7122 goto release;
14497328 7123 }
7a3e97b0 7124
66cc820f 7125 /* Print Transfer Request of aborted task */
d87a1f6d 7126 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 7127
7fabb77b
GB		 7128 /*
7129 * Print detailed info about aborted request.
7130 * As more than one request might get aborted at the same time,
7131 * print full information only for the first aborted request in order
7132 * to reduce repeated printouts. For other aborted requests only print
7133 * basic details.
7134 */
7a7e66c6 7135 scsi_print_command(cmd);
7fabb77b 7136 if (!hba->req_abort_count) {
e965e5e0
SC		 7137 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7138 ufshcd_print_evt_hist(hba);
6ba65588 7139 ufshcd_print_host_state(hba);
7fabb77b
GB		 7140 ufshcd_print_pwr_info(hba);
7141 ufshcd_print_trs(hba, 1 << tag, true);
7142 } else {
7143 ufshcd_print_trs(hba, 1 << tag, false);
7144 }
7145 hba->req_abort_count++;
e0b299e3 7146
d87a1f6d
BH		 7147 if (!(reg & (1 << tag))) {
7148 dev_err(hba->dev,
7149 "%s: cmd was completed, but without a notifying intr, tag = %d",
7150 __func__, tag);
11682523 7151 __ufshcd_transfer_req_compl(hba, 1UL << tag);
64180742 7152 goto release;
d87a1f6d
BH		 7153 }
7154
7a7e66c6
CG		 7155 /*
7156 * Task abort to the device W-LUN is illegal. When this command
7157 * will fail, due to spec violation, scsi err handling next step
7158 * will be to send LU reset which, again, is a spec violation.
7159 * To avoid these unnecessary/illegal steps, first we clean up
a45f9371 7160 * the lrb taken by this cmd and re-set it in outstanding_reqs,
88b09900 7161 * then queue the eh_work and bail.
7a7e66c6
CG		 7162 */
7163 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7164 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
64180742 7165
7a7e66c6 7166 spin_lock_irqsave(host->host_lock, flags);
a45f9371 7167 hba->force_reset = true;
88b09900 7168 ufshcd_schedule_eh_work(hba);
7a7e66c6 7169 spin_unlock_irqrestore(host->host_lock, flags);
64180742 7170 goto release;
7a7e66c6
CG		 7171 }
7172
e0b299e3 7173 /* Skip task abort in case previous aborts failed and report failure */
64180742
BVA		 7174 if (lrbp->req_abort_skip) {
7175 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7176 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7177 goto release;
7178 }
f20810d8 7179
64180742
BVA		 7180 err = ufshcd_try_to_abort_task(hba, tag);
7181 if (err) {
f20810d8 7182 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 7183 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8 7184 err = FAILED;
64180742 7185 goto release;
f20810d8
SRT		 7186 }
7187
1fbaa02d
BVA		 7188 /*
7189 * Clear the corresponding bit from outstanding_reqs since the command
7190 * has been aborted successfully.
7191 */
7192 spin_lock_irqsave(&hba->outstanding_lock, flags);
7193 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7194 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7195
7196 if (outstanding)
7197 ufshcd_release_scsi_cmd(hba, lrbp);
7198
64180742
BVA		 7199 err = SUCCESS;
7200
7201release:
7202 /* Matches the ufshcd_hold() call at the start of this function. */
1ab27c9c 7203 ufshcd_release(hba);
7a3e97b0
SY		 7204 return err;
7205}
7206
3441da7d
SRT		 7207/**
7208 * ufshcd_host_reset_and_restore - reset and restore host controller
7209 * @hba: per-adapter instance
7210 *
7211 * Note that host controller reset may issue DME_RESET to
7212 * local and remote (device) Uni-Pro stack and the attributes
7213 * are reset to default state.
7214 *
7215 * Returns zero on success, non-zero on failure
7216 */
7217static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7218{
7219 int err;
3441da7d 7220
2df74b69
CG		 7221 /*
7222 * Stop the host controller and complete the requests
7223 * cleared by h/w
7224 */
f02bc975 7225 ufshpb_reset_host(hba);
5cac1095 7226 ufshcd_hba_stop(hba);
2df74b69 7227 hba->silence_err_logs = true;
11682523 7228 ufshcd_complete_requests(hba);
2df74b69 7229 hba->silence_err_logs = false;
3441da7d 7230
a3cd5ec5 7231 /* scale up clocks to max frequency before full reinitialization */
394b949f 7232 ufshcd_set_clk_freq(hba, true);
a3cd5ec5 7233
3441da7d 7234 err = ufshcd_hba_enable(hba);
3441da7d
SRT		 7235
7236 /* Establish the link again and restore the device */
1918651f 7237 if (!err)
4ee7ee53
JK		 7238 err = ufshcd_probe_hba(hba, false);
7239
3441da7d
SRT		 7240 if (err)
7241 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
e965e5e0 7242 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
3441da7d
SRT		 7243 return err;
7244}
7245
7246/**
7247 * ufshcd_reset_and_restore - reset and re-initialize host/device
7248 * @hba: per-adapter instance
7249 *
7250 * Reset and recover device, host and re-establish link. This
7251 * is helpful to recover the communication in fatal error conditions.
7252 *
7253 * Returns zero on success, non-zero on failure
7254 */
7255static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7256{
54a40453
AH		 7257 u32 saved_err = 0;
7258 u32 saved_uic_err = 0;
3441da7d 7259 int err = 0;
4db7a236 7260 unsigned long flags;
1d337ec2 7261 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 7262
4db7a236 7263 spin_lock_irqsave(hba->host->host_lock, flags);
1d337ec2 7264 do {
54a40453
AH		 7265 /*
7266 * This is a fresh start, cache and clear saved error first,
7267 * in case new error generated during reset and restore.
7268 */
7269 saved_err |= hba->saved_err;
7270 saved_uic_err |= hba->saved_uic_err;
7271 hba->saved_err = 0;
7272 hba->saved_uic_err = 0;
7273 hba->force_reset = false;
7274 hba->ufshcd_state = UFSHCD_STATE_RESET;
7275 spin_unlock_irqrestore(hba->host->host_lock, flags);
7276
d8d9f793 7277 /* Reset the attached device */
31a5d9ca 7278 ufshcd_device_reset(hba);
d8d9f793 7279
1d337ec2 7280 err = ufshcd_host_reset_and_restore(hba);
54a40453
AH		 7281
7282 spin_lock_irqsave(hba->host->host_lock, flags);
7283 if (err)
7284 continue;
7285 /* Do not exit unless operational or dead */
7286 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7287 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7288 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7289 err = -EAGAIN;
1d337ec2 7290 } while (err && --retries);
3441da7d 7291
4db7a236
CG		 7292 /*
7293 * Inform scsi mid-layer that we did reset and allow to handle
7294 * Unit Attention properly.
7295 */
7296 scsi_report_bus_reset(hba->host, 0);
7297 if (err) {
88a92d6a 7298 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4db7a236
CG		 7299 hba->saved_err |= saved_err;
7300 hba->saved_uic_err |= saved_uic_err;
7301 }
7302 spin_unlock_irqrestore(hba->host->host_lock, flags);
7303
3441da7d
SRT		 7304 return err;
7305}
7306
7307/**
7308 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 7309 * @cmd: SCSI command pointer
3441da7d
SRT		 7310 *
7311 * Returns SUCCESS/FAILED
7312 */
7313static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7314{
4db7a236 7315 int err = SUCCESS;
3441da7d
SRT		 7316 unsigned long flags;
7317 struct ufs_hba *hba;
7318
7319 hba = shost_priv(cmd->device->host);
7320
4db7a236
CG		 7321 spin_lock_irqsave(hba->host->host_lock, flags);
7322 hba->force_reset = true;
88b09900 7323 ufshcd_schedule_eh_work(hba);
4db7a236 7324 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
3441da7d
SRT		 7325 spin_unlock_irqrestore(hba->host->host_lock, flags);
7326
88b09900 7327 flush_work(&hba->eh_work);
3441da7d
SRT		 7328
7329 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236 7330 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
3441da7d 7331 err = FAILED;
3441da7d
SRT		 7332 spin_unlock_irqrestore(hba->host->host_lock, flags);
7333
7334 return err;
7335}
7336
3a4bf06d
YG		 7337/**
7338 * ufshcd_get_max_icc_level - calculate the ICC level
7339 * @sup_curr_uA: max. current supported by the regulator
7340 * @start_scan: row at the desc table to start scan from
7341 * @buff: power descriptor buffer
7342 *
7343 * Returns calculated max ICC level for specific regulator
7344 */
7345static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7346{
7347 int i;
7348 int curr_uA;
7349 u16 data;
7350 u16 unit;
7351
7352 for (i = start_scan; i >= 0; i--) {
d79713f9 7353 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 7354 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7355 ATTR_ICC_LVL_UNIT_OFFSET;
7356 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7357 switch (unit) {
7358 case UFSHCD_NANO_AMP:
7359 curr_uA = curr_uA / 1000;
7360 break;
7361 case UFSHCD_MILI_AMP:
7362 curr_uA = curr_uA * 1000;
7363 break;
7364 case UFSHCD_AMP:
7365 curr_uA = curr_uA * 1000 * 1000;
7366 break;
7367 case UFSHCD_MICRO_AMP:
7368 default:
7369 break;
7370 }
7371 if (sup_curr_uA >= curr_uA)
7372 break;
7373 }
7374 if (i < 0) {
7375 i = 0;
7376 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7377 }
7378
7379 return (u32)i;
7380}
7381
7382/**
11eea9b3 7383 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
3a4bf06d
YG		 7384 * In case regulators are not initialized we'll return 0
7385 * @hba: per-adapter instance
7386 * @desc_buf: power descriptor buffer to extract ICC levels from.
7387 * @len: length of desc_buff
7388 *
7389 * Returns calculated ICC level
7390 */
7391static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7392 u8 *desc_buf, int len)
7393{
7394 u32 icc_level = 0;
7395
7396 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7397 !hba->vreg_info.vccq2) {
71bb9ab6
AH		 7398 /*
7399 * Using dev_dbg to avoid messages during runtime PM to avoid
7400 * never-ending cycles of messages written back to storage by
7401 * user space causing runtime resume, causing more messages and
7402 * so on.
7403 */
7404 dev_dbg(hba->dev,
3a4bf06d
YG		 7405 "%s: Regulator capability was not set, actvIccLevel=%d",
7406 __func__, icc_level);
7407 goto out;
7408 }
7409
0873045f 7410 if (hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 7411 icc_level = ufshcd_get_max_icc_level(
7412 hba->vreg_info.vcc->max_uA,
7413 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7414 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7415
0873045f 7416 if (hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 7417 icc_level = ufshcd_get_max_icc_level(
7418 hba->vreg_info.vccq->max_uA,
7419 icc_level,
7420 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7421
0873045f 7422 if (hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 7423 icc_level = ufshcd_get_max_icc_level(
7424 hba->vreg_info.vccq2->max_uA,
7425 icc_level,
7426 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7427out:
7428 return icc_level;
7429}
7430
e89860f1 7431static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 7432{
7433 int ret;
7a0bf85b 7434 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
bbe21d7a 7435 u8 *desc_buf;
e89860f1 7436 u32 icc_level;
bbe21d7a
KC		 7437
7438 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7439 if (!desc_buf)
7440 return;
3a4bf06d 7441
c4607a09
BH		 7442 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7443 desc_buf, buff_len);
3a4bf06d
YG		 7444 if (ret) {
7445 dev_err(hba->dev,
7446 "%s: Failed reading power descriptor.len = %d ret = %d",
7447 __func__, buff_len, ret);
bbe21d7a 7448 goto out;
3a4bf06d
YG		 7449 }
7450
e89860f1
CG		 7451 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7452 buff_len);
7453 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 7454
dbd34a61 7455 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 7456 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 7457
7458 if (ret)
7459 dev_err(hba->dev,
7460 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 7461 __func__, icc_level, ret);
3a4bf06d 7462
bbe21d7a
KC		 7463out:
7464 kfree(desc_buf);
3a4bf06d
YG		 7465}
7466
fb276f77
CG		 7467static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7468{
7469 scsi_autopm_get_device(sdev);
7470 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7471 if (sdev->rpm_autosuspend)
7472 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7473 RPM_AUTOSUSPEND_DELAY_MS);
7474 scsi_autopm_put_device(sdev);
7475}
7476
2a8fa600
SJ		 7477/**
7478 * ufshcd_scsi_add_wlus - Adds required W-LUs
7479 * @hba: per-adapter instance
7480 *
7481 * UFS device specification requires the UFS devices to support 4 well known
7482 * logical units:
7483 * "REPORT_LUNS" (address: 01h)
7484 * "UFS Device" (address: 50h)
7485 * "RPMB" (address: 44h)
7486 * "BOOT" (address: 30h)
7487 * UFS device's power management needs to be controlled by "POWER CONDITION"
7488 * field of SSU (START STOP UNIT) command. But this "power condition" field
7489 * will take effect only when its sent to "UFS device" well known logical unit
7490 * hence we require the scsi_device instance to represent this logical unit in
7491 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 7492 *
2a8fa600
SJ		 7493 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7494 * Block) LU so user space process can control this LU. User space may also
7495 * want to have access to BOOT LU.
8aa29f19 7496 *
2a8fa600
SJ		 7497 * This function adds scsi device instances for each of all well known LUs
7498 * (except "REPORT LUNS" LU).
7499 *
7500 * Returns zero on success (all required W-LUs are added successfully),
7501 * non-zero error value on failure (if failed to add any of the required W-LU).
7502 */
7503static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7504{
7505 int ret = 0;
59830c09 7506 struct scsi_device *sdev_boot, *sdev_rpmb;
2a8fa600
SJ		 7507
7508 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7509 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7510 if (IS_ERR(hba->sdev_ufs_device)) {
7511 ret = PTR_ERR(hba->sdev_ufs_device);
7512 hba->sdev_ufs_device = NULL;
7513 goto out;
7514 }
7c48bfd0 7515 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 7516
59830c09 7517 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7518 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
59830c09
BVA		 7519 if (IS_ERR(sdev_rpmb)) {
7520 ret = PTR_ERR(sdev_rpmb);
3d21fbde 7521 goto remove_sdev_ufs_device;
2a8fa600 7522 }
59830c09
BVA		 7523 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7524 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 7525
7526 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7527 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 7528 if (IS_ERR(sdev_boot)) {
3d21fbde 7529 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 7530 } else {
7531 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 7532 scsi_device_put(sdev_boot);
fb276f77 7533 }
2a8fa600
SJ		 7534 goto out;
7535
2a8fa600
SJ		 7536remove_sdev_ufs_device:
7537 scsi_remove_device(hba->sdev_ufs_device);
7538out:
7539 return ret;
7540}
7541
3d17b9b5
AD		 7542static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7543{
a7f1e69d 7544 struct ufs_dev_info *dev_info = &hba->dev_info;
6f8d5a6a
SC		 7545 u8 lun;
7546 u32 d_lu_wb_buf_alloc;
e8d03813 7547 u32 ext_ufs_feature;
6f8d5a6a 7548
817d7e14
SC		 7549 if (!ufshcd_is_wb_allowed(hba))
7550 return;
f681d107 7551
a7f1e69d
SC		 7552 /*
7553 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7554 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7555 * enabled
7556 */
7557 if (!(dev_info->wspecversion >= 0x310 ||
7558 dev_info->wspecversion == 0x220 ||
7559 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7560 goto wb_disabled;
817d7e14 7561
7a0bf85b
BH		 7562 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7563 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
817d7e14
SC		 7564 goto wb_disabled;
7565
e8d03813
BH		 7566 ext_ufs_feature = get_unaligned_be32(desc_buf +
7567 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
817d7e14 7568
e8d03813 7569 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
817d7e14
SC		 7570 goto wb_disabled;
7571
3d17b9b5 7572 /*
ae1ce1fc
BH		 7573 * WB may be supported but not configured while provisioning. The spec
7574 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7575 * buffer configured.
3d17b9b5 7576 */
4cd48995 7577 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
3d17b9b5 7578
a7f1e69d 7579 dev_info->b_presrv_uspc_en =
3d17b9b5
AD		 7580 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7581
4cd48995 7582 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
e8d03813
BH		 7583 if (!get_unaligned_be32(desc_buf +
7584 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
6f8d5a6a
SC		 7585 goto wb_disabled;
7586 } else {
7587 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7588 d_lu_wb_buf_alloc = 0;
7589 ufshcd_read_unit_desc_param(hba,
7590 lun,
7591 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7592 (u8 *)&d_lu_wb_buf_alloc,
7593 sizeof(d_lu_wb_buf_alloc));
7594 if (d_lu_wb_buf_alloc) {
a7f1e69d 7595 dev_info->wb_dedicated_lu = lun;
6f8d5a6a
SC		 7596 break;
7597 }
7598 }
817d7e14 7599
6f8d5a6a
SC		 7600 if (!d_lu_wb_buf_alloc)
7601 goto wb_disabled;
7602 }
f681d107
JC		 7603
7604 if (!ufshcd_is_wb_buf_lifetime_available(hba))
7605 goto wb_disabled;
7606
817d7e14
SC		 7607 return;
7608
7609wb_disabled:
7610 hba->caps &= ~UFSHCD_CAP_WB_EN;
7611}
7612
e88e2d32
AA		 7613static void ufshcd_temp_notif_probe(struct ufs_hba *hba, u8 *desc_buf)
7614{
7615 struct ufs_dev_info *dev_info = &hba->dev_info;
7616 u32 ext_ufs_feature;
7617 u8 mask = 0;
7618
7619 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7620 return;
7621
7622 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7623
7624 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7625 mask |= MASK_EE_TOO_LOW_TEMP;
7626
7627 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7628 mask |= MASK_EE_TOO_HIGH_TEMP;
7629
7630 if (mask) {
7631 ufshcd_enable_ee(hba, mask);
7632 ufs_hwmon_probe(hba, mask);
7633 }
7634}
7635
8db269a5 7636void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
817d7e14
SC		 7637{
7638 struct ufs_dev_fix *f;
7639 struct ufs_dev_info *dev_info = &hba->dev_info;
7640
8db269a5
SC		 7641 if (!fixups)
7642 return;
7643
7644 for (f = fixups; f->quirk; f++) {
817d7e14
SC		 7645 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7646 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7647 ((dev_info->model &&
7648 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7649 !strcmp(f->model, UFS_ANY_MODEL)))
7650 hba->dev_quirks |= f->quirk;
7651 }
3d17b9b5 7652}
8db269a5 7653EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
3d17b9b5 7654
c28c00ba
SC		 7655static void ufs_fixup_device_setup(struct ufs_hba *hba)
7656{
7657 /* fix by general quirk table */
8db269a5 7658 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
c28c00ba
SC		 7659
7660 /* allow vendors to fix quirks */
7661 ufshcd_vops_fixup_dev_quirks(hba);
7662}
7663
09750066 7664static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 7665{
7666 int err;
7667 u8 model_index;
f02bc975 7668 u8 b_ufs_feature_sup;
bbe21d7a 7669 u8 *desc_buf;
09750066 7670 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 7671
458a45f5 7672 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 7673 if (!desc_buf) {
7674 err = -ENOMEM;
7675 goto out;
7676 }
c58ab7aa 7677
c4607a09 7678 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7a0bf85b 7679 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
c58ab7aa
YG		 7680 if (err) {
7681 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7682 __func__, err);
7683 goto out;
7684 }
7685
7686 /*
7687 * getting vendor (manufacturerID) and Bank Index in big endian
7688 * format
7689 */
09750066 7690 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 7691 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7692
09f17791
CG		 7693 /* getting Specification Version in big endian format */
7694 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7695 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
f02bc975 7696 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
09f17791 7697
c58ab7aa 7698 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5 7699
f02bc975
DP		 7700 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7701 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
41d8a933
DP		 7702 bool hpb_en = false;
7703
f02bc975 7704 ufshpb_get_dev_info(hba, desc_buf);
41d8a933
DP		 7705
7706 if (!ufshpb_is_legacy(hba))
7707 err = ufshcd_query_flag_retry(hba,
7708 UPIU_QUERY_OPCODE_READ_FLAG,
7709 QUERY_FLAG_IDN_HPB_EN, 0,
7710 &hpb_en);
7711
7712 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7713 dev_info->hpb_enabled = true;
f02bc975
DP		 7714 }
7715
4b828fe1 7716 err = ufshcd_read_string_desc(hba, model_index,
09750066 7717 &dev_info->model, SD_ASCII_STD);
4b828fe1 7718 if (err < 0) {
c58ab7aa
YG		 7719 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7720 __func__, err);
7721 goto out;
7722 }
7723
b294ff3e
AD		 7724 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7725 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7726
817d7e14
SC		 7727 ufs_fixup_device_setup(hba);
7728
a7f1e69d 7729 ufshcd_wb_probe(hba, desc_buf);
817d7e14 7730
e88e2d32
AA		 7731 ufshcd_temp_notif_probe(hba, desc_buf);
7732
4b828fe1
TW		 7733 /*
7734 * ufshcd_read_string_desc returns size of the string
7735 * reset the error value
7736 */
7737 err = 0;
c58ab7aa
YG		 7738
7739out:
bbe21d7a 7740 kfree(desc_buf);
c58ab7aa
YG		 7741 return err;
7742}
7743
09750066 7744static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 7745{
09750066
BH		 7746 struct ufs_dev_info *dev_info = &hba->dev_info;
7747
7748 kfree(dev_info->model);
7749 dev_info->model = NULL;
4b828fe1
TW		 7750}
7751
37113106
YG		 7752/**
7753 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7754 * @hba: per-adapter instance
7755 *
7756 * PA_TActivate parameter can be tuned manually if UniPro version is less than
7757 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7758 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7759 * the hibern8 exit latency.
7760 *
7761 * Returns zero on success, non-zero error value on failure.
7762 */
7763static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7764{
7765 int ret = 0;
7766 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7767
7768 ret = ufshcd_dme_peer_get(hba,
7769 UIC_ARG_MIB_SEL(
7770 RX_MIN_ACTIVATETIME_CAPABILITY,
7771 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7772 &peer_rx_min_activatetime);
7773 if (ret)
7774 goto out;
7775
7776 /* make sure proper unit conversion is applied */
7777 tuned_pa_tactivate =
7778 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7779 / PA_TACTIVATE_TIME_UNIT_US);
7780 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7781 tuned_pa_tactivate);
7782
7783out:
7784 return ret;
7785}
7786
7787/**
7788 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7789 * @hba: per-adapter instance
7790 *
7791 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7792 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7793 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7794 * This optimal value can help reduce the hibern8 exit latency.
7795 *
7796 * Returns zero on success, non-zero error value on failure.
7797 */
7798static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7799{
7800 int ret = 0;
7801 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7802 u32 max_hibern8_time, tuned_pa_hibern8time;
7803
7804 ret = ufshcd_dme_get(hba,
7805 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7806 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7807 &local_tx_hibern8_time_cap);
7808 if (ret)
7809 goto out;
7810
7811 ret = ufshcd_dme_peer_get(hba,
7812 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7813 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7814 &peer_rx_hibern8_time_cap);
7815 if (ret)
7816 goto out;
7817
7818 max_hibern8_time = max(local_tx_hibern8_time_cap,
7819 peer_rx_hibern8_time_cap);
7820 /* make sure proper unit conversion is applied */
7821 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7822 / PA_HIBERN8_TIME_UNIT_US);
7823 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7824 tuned_pa_hibern8time);
7825out:
7826 return ret;
7827}
7828
c6a6db43 7829/**
7830 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7831 * less than device PA_TACTIVATE time.
7832 * @hba: per-adapter instance
7833 *
7834 * Some UFS devices require host PA_TACTIVATE to be lower than device
7835 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7836 * for such devices.
7837 *
7838 * Returns zero on success, non-zero error value on failure.
7839 */
7840static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7841{
7842 int ret = 0;
7843 u32 granularity, peer_granularity;
7844 u32 pa_tactivate, peer_pa_tactivate;
7845 u32 pa_tactivate_us, peer_pa_tactivate_us;
7846 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7847
7848 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7849 &granularity);
7850 if (ret)
7851 goto out;
7852
7853 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7854 &peer_granularity);
7855 if (ret)
7856 goto out;
7857
7858 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7859 (granularity > PA_GRANULARITY_MAX_VAL)) {
7860 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7861 __func__, granularity);
7862 return -EINVAL;
7863 }
7864
7865 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7866 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7867 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7868 __func__, peer_granularity);
7869 return -EINVAL;
7870 }
7871
7872 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7873 if (ret)
7874 goto out;
7875
7876 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7877 &peer_pa_tactivate);
7878 if (ret)
7879 goto out;
7880
7881 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7882 peer_pa_tactivate_us = peer_pa_tactivate *
7883 gran_to_us_table[peer_granularity - 1];
7884
9008661e 7885 if (pa_tactivate_us >= peer_pa_tactivate_us) {
c6a6db43 7886 u32 new_peer_pa_tactivate;
7887
7888 new_peer_pa_tactivate = pa_tactivate_us /
7889 gran_to_us_table[peer_granularity - 1];
7890 new_peer_pa_tactivate++;
7891 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7892 new_peer_pa_tactivate);
7893 }
7894
7895out:
7896 return ret;
7897}
7898
09750066 7899static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 7900{
7901 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7902 ufshcd_tune_pa_tactivate(hba);
7903 ufshcd_tune_pa_hibern8time(hba);
7904 }
7905
e91ed9e0
CG		 7906 ufshcd_vops_apply_dev_quirks(hba);
7907
37113106
YG		 7908 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7909 /* set 1ms timeout for PA_TACTIVATE */
7910 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 7911
7912 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7913 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 7914}
7915
ff8e20c6
DR		 7916static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7917{
ff8e20c6
DR		 7918 hba->ufs_stats.hibern8_exit_cnt = 0;
7919 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 7920 hba->req_abort_count = 0;
ff8e20c6
DR		 7921}
7922
731f0621
BH		 7923static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7924{
7925 int err;
7926 size_t buff_len;
7927 u8 *desc_buf;
7928
7a0bf85b 7929 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
731f0621
BH		 7930 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7931 if (!desc_buf) {
7932 err = -ENOMEM;
7933 goto out;
7934 }
7935
c4607a09
BH		 7936 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7937 desc_buf, buff_len);
731f0621
BH		 7938 if (err) {
7939 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7940 __func__, err);
7941 goto out;
7942 }
7943
7944 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7945 hba->dev_info.max_lu_supported = 32;
7946 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7947 hba->dev_info.max_lu_supported = 8;
7948
f02bc975
DP		 7949 if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7950 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7951 ufshpb_get_geo_info(hba, desc_buf);
7952
731f0621
BH		 7953out:
7954 kfree(desc_buf);
7955 return err;
7956}
7957
9e1e8a75
SJ		 7958static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7959 {19200000, REF_CLK_FREQ_19_2_MHZ},
7960 {26000000, REF_CLK_FREQ_26_MHZ},
7961 {38400000, REF_CLK_FREQ_38_4_MHZ},
7962 {52000000, REF_CLK_FREQ_52_MHZ},
7963 {0, REF_CLK_FREQ_INVAL},
7964};
7965
7966static enum ufs_ref_clk_freq
7967ufs_get_bref_clk_from_hz(unsigned long freq)
7968{
7969 int i;
7970
7971 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7972 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7973 return ufs_ref_clk_freqs[i].val;
7974
7975 return REF_CLK_FREQ_INVAL;
7976}
7977
7978void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7979{
7980 unsigned long freq;
7981
7982 freq = clk_get_rate(refclk);
7983
7984 hba->dev_ref_clk_freq =
7985 ufs_get_bref_clk_from_hz(freq);
7986
7987 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7988 dev_err(hba->dev,
7989 "invalid ref_clk setting = %ld\n", freq);
7990}
7991
7992static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7993{
7994 int err;
7995 u32 ref_clk;
7996 u32 freq = hba->dev_ref_clk_freq;
7997
7998 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7999 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8000
8001 if (err) {
8002 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8003 err);
8004 goto out;
8005 }
8006
8007 if (ref_clk == freq)
8008 goto out; /* nothing to update */
8009
8010 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8011 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8012
8013 if (err) {
8014 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8015 ufs_ref_clk_freqs[freq].freq_hz);
8016 goto out;
8017 }
8018
8019 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8020 ufs_ref_clk_freqs[freq].freq_hz);
8021
8022out:
8023 return err;
8024}
8025
1b9e2141
BH		 8026static int ufshcd_device_params_init(struct ufs_hba *hba)
8027{
8028 bool flag;
7a0bf85b 8029 int ret, i;
1b9e2141 8030
7a0bf85b
BH		 8031 /* Init device descriptor sizes */
8032 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
8033 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
1b9e2141 8034
731f0621
BH		 8035 /* Init UFS geometry descriptor related parameters */
8036 ret = ufshcd_device_geo_params_init(hba);
8037 if (ret)
8038 goto out;
8039
1b9e2141
BH		 8040 /* Check and apply UFS device quirks */
8041 ret = ufs_get_device_desc(hba);
8042 if (ret) {
8043 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8044 __func__, ret);
8045 goto out;
8046 }
8047
09f17791
CG		 8048 ufshcd_get_ref_clk_gating_wait(hba);
8049
1b9e2141 8050 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 8051 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
1b9e2141
BH		 8052 hba->dev_info.f_power_on_wp_en = flag;
8053
2b35b2ad
BH		 8054 /* Probe maximum power mode co-supported by both UFS host and device */
8055 if (ufshcd_get_max_pwr_mode(hba))
8056 dev_err(hba->dev,
8057 "%s: Failed getting max supported power mode\n",
8058 __func__);
1b9e2141
BH		 8059out:
8060 return ret;
8061}
8062
8063/**
8064 * ufshcd_add_lus - probe and add UFS logical units
8065 * @hba: per-adapter instance
8066 */
8067static int ufshcd_add_lus(struct ufs_hba *hba)
8068{
8069 int ret;
8070
1b9e2141
BH		 8071 /* Add required well known logical units to scsi mid layer */
8072 ret = ufshcd_scsi_add_wlus(hba);
8073 if (ret)
8074 goto out;
8075
8076 /* Initialize devfreq after UFS device is detected */
8077 if (ufshcd_is_clkscaling_supported(hba)) {
8078 memcpy(&hba->clk_scaling.saved_pwr_info.info,
8079 &hba->pwr_info,
8080 sizeof(struct ufs_pa_layer_attr));
8081 hba->clk_scaling.saved_pwr_info.is_valid = true;
1b9e2141 8082 hba->clk_scaling.is_allowed = true;
1b9e2141 8083
b058fa86
SC		 8084 ret = ufshcd_devfreq_init(hba);
8085 if (ret)
8086 goto out;
8087
8088 hba->clk_scaling.is_enabled = true;
8089 ufshcd_init_clk_scaling_sysfs(hba);
1b9e2141
BH		 8090 }
8091
8092 ufs_bsg_probe(hba);
f02bc975 8093 ufshpb_init(hba);
1b9e2141
BH		 8094 scsi_scan_host(hba->host);
8095 pm_runtime_put_sync(hba->dev);
8096
1b9e2141
BH		 8097out:
8098 return ret;
8099}
8100
6ccf44fe 8101/**
568dd995 8102 * ufshcd_probe_hba - probe hba to detect device and initialize it
1d337ec2 8103 * @hba: per-adapter instance
568dd995 8104 * @init_dev_params: whether or not to call ufshcd_device_params_init().
1d337ec2
SRT		 8105 *
8106 * Execute link-startup and verify device initialization
6ccf44fe 8107 */
568dd995 8108static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
6ccf44fe 8109{
6ccf44fe 8110 int ret;
4db7a236 8111 unsigned long flags;
7ff5ab47 8112 ktime_t start = ktime_get();
6ccf44fe 8113
aa53f580
CG		 8114 hba->ufshcd_state = UFSHCD_STATE_RESET;
8115
6ccf44fe 8116 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 8117 if (ret)
8118 goto out;
8119
10fb4f87 8120 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8121 goto out;
8122
ff8e20c6
DR		 8123 /* Debug counters initialization */
8124 ufshcd_clear_dbg_ufs_stats(hba);
8125
57d104c1
SJ		 8126 /* UniPro link is active now */
8127 ufshcd_set_link_active(hba);
d3e89bac 8128
1b9e2141 8129 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 8130 ret = ufshcd_verify_dev_init(hba);
8131 if (ret)
8132 goto out;
68078d5c 8133
1b9e2141 8134 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 8135 ret = ufshcd_complete_dev_init(hba);
8136 if (ret)
8137 goto out;
5a0b0cb9 8138
1b9e2141
BH		 8139 /*
8140 * Initialize UFS device parameters used by driver, these
8141 * parameters are associated with UFS descriptors.
8142 */
568dd995 8143 if (init_dev_params) {
1b9e2141
BH		 8144 ret = ufshcd_device_params_init(hba);
8145 if (ret)
8146 goto out;
93fdd5ac
TW		 8147 }
8148
09750066 8149 ufshcd_tune_unipro_params(hba);
4b828fe1 8150
57d104c1
SJ		 8151 /* UFS device is also active now */
8152 ufshcd_set_ufs_dev_active(hba);
66ec6d59 8153 ufshcd_force_reset_auto_bkops(hba);
57d104c1 8154
2b35b2ad
BH		 8155 /* Gear up to HS gear if supported */
8156 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 8157 /*
8158 * Set the right value to bRefClkFreq before attempting to
8159 * switch to HS gears.
8160 */
8161 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8162 ufshcd_set_dev_ref_clk(hba);
7eb584db 8163 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 8164 if (ret) {
7eb584db
DR		 8165 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8166 __func__, ret);
8643ae66
DL		 8167 goto out;
8168 }
6a9df818 8169 ufshcd_print_pwr_info(hba);
7eb584db 8170 }
57d104c1 8171
e89860f1
CG		 8172 /*
8173 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8174 * and for removable UFS card as well, hence always set the parameter.
8175 * Note: Error handler may issue the device reset hence resetting
8176 * bActiveICCLevel as well so it is always safe to set this here.
8177 */
8178 ufshcd_set_active_icc_lvl(hba);
8179
3d17b9b5 8180 ufshcd_wb_config(hba);
cd469475
AH		 8181 if (hba->ee_usr_mask)
8182 ufshcd_write_ee_control(hba);
71d848b8
CG		 8183 /* Enable Auto-Hibernate if configured */
8184 ufshcd_auto_hibern8_enable(hba);
8185
f02bc975 8186 ufshpb_reset(hba);
5a0b0cb9 8187out:
4db7a236
CG		 8188 spin_lock_irqsave(hba->host->host_lock, flags);
8189 if (ret)
8190 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8191 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8192 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8193 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d337ec2 8194
7ff5ab47 8195 trace_ufshcd_init(dev_name(hba->dev), ret,
8196 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8197 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 8198 return ret;
8199}
8200
8201/**
8202 * ufshcd_async_scan - asynchronous execution for probing hba
8203 * @data: data pointer to pass to this function
8204 * @cookie: cookie data
8205 */
8206static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8207{
8208 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 8209 int ret;
1d337ec2 8210
9cd20d3f 8211 down(&hba->host_sem);
1b9e2141
BH		 8212 /* Initialize hba, detect and initialize UFS device */
8213 ret = ufshcd_probe_hba(hba, true);
9cd20d3f 8214 up(&hba->host_sem);
1b9e2141
BH		 8215 if (ret)
8216 goto out;
8217
8218 /* Probe and add UFS logical units */
8219 ret = ufshcd_add_lus(hba);
8220out:
8221 /*
8222 * If we failed to initialize the device or the device is not
8223 * present, turn off the power/clocks etc.
8224 */
8225 if (ret) {
8226 pm_runtime_put_sync(hba->dev);
1b9e2141
BH		 8227 ufshcd_hba_exit(hba);
8228 }
6ccf44fe
SJ		 8229}
8230
d829fc8a
SN		 8231static const struct attribute_group *ufshcd_driver_groups[] = {
8232 &ufs_sysfs_unit_descriptor_group,
ec92b59c 8233 &ufs_sysfs_lun_attributes_group,
f02bc975
DP		 8234#ifdef CONFIG_SCSI_UFS_HPB
8235 &ufs_sysfs_hpb_stat_group,
41d8a933 8236 &ufs_sysfs_hpb_param_group,
f02bc975 8237#endif
d829fc8a
SN		 8238 NULL,
8239};
8240
90b8491c
SC		 8241static struct ufs_hba_variant_params ufs_hba_vps = {
8242 .hba_enable_delay_us = 1000,
d14734ae 8243 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
90b8491c
SC		 8244 .devfreq_profile.polling_ms = 100,
8245 .devfreq_profile.target = ufshcd_devfreq_target,
8246 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8247 .ondemand_data.upthreshold = 70,
8248 .ondemand_data.downdifferential = 5,
8249};
8250
7a3e97b0
SY		 8251static struct scsi_host_template ufshcd_driver_template = {
8252 .module = THIS_MODULE,
8253 .name = UFSHCD,
8254 .proc_name = UFSHCD,
eaab9b57 8255 .map_queues = ufshcd_map_queues,
7a3e97b0 8256 .queuecommand = ufshcd_queuecommand,
eaab9b57 8257 .mq_poll = ufshcd_poll,
7a3e97b0 8258 .slave_alloc = ufshcd_slave_alloc,
eeda4749 8259 .slave_configure = ufshcd_slave_configure,
7a3e97b0 8260 .slave_destroy = ufshcd_slave_destroy,
4264fd61 8261 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 8262 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 8263 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8264 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 8265 .this_id = -1,
8266 .sg_tablesize = SG_ALL,
8267 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8268 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 8269 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 8270 .max_host_blocked = 1,
c40ecc12 8271 .track_queue_depth = 1,
d829fc8a 8272 .sdev_groups = ufshcd_driver_groups,
4af14d11 8273 .dma_boundary = PAGE_SIZE - 1,
49615ba1 8274 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 8275};
8276
57d104c1
SJ		 8277static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8278 int ua)
8279{
7b16a07c 8280 int ret;
57d104c1 8281
7b16a07c
BA		 8282 if (!vreg)
8283 return 0;
57d104c1 8284
0487fff7
SC		 8285 /*
8286 * "set_load" operation shall be required on those regulators
8287 * which specifically configured current limitation. Otherwise
8288 * zero max_uA may cause unexpected behavior when regulator is
8289 * enabled or set as high power mode.
8290 */
8291 if (!vreg->max_uA)
8292 return 0;
8293
7b16a07c
BA		 8294 ret = regulator_set_load(vreg->reg, ua);
8295 if (ret < 0) {
8296 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8297 __func__, vreg->name, ua, ret);
57d104c1
SJ		 8298 }
8299
8300 return ret;
8301}
8302
8303static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8304 struct ufs_vreg *vreg)
8305{
73067981 8306 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 8307}
8308
8309static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8310 struct ufs_vreg *vreg)
8311{
7c7cfdcf
AH		 8312 if (!vreg)
8313 return 0;
8314
73067981 8315 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 8316}
8317
aa497613
SRT		 8318static int ufshcd_config_vreg(struct device *dev,
8319 struct ufs_vreg *vreg, bool on)
8320{
8321 int ret = 0;
72753590
GS		 8322 struct regulator *reg;
8323 const char *name;
aa497613
SRT		 8324 int min_uV, uA_load;
8325
8326 BUG_ON(!vreg);
8327
72753590
GS		 8328 reg = vreg->reg;
8329 name = vreg->name;
8330
aa497613 8331 if (regulator_count_voltages(reg) > 0) {
90d88f47
AD		 8332 uA_load = on ? vreg->max_uA : 0;
8333 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8334 if (ret)
8335 goto out;
8336
3b141e8c
SC		 8337 if (vreg->min_uV && vreg->max_uV) {
8338 min_uV = on ? vreg->min_uV : 0;
8339 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
b0008625 8340 if (ret)
3b141e8c
SC		 8341 dev_err(dev,
8342 "%s: %s set voltage failed, err=%d\n",
aa497613 8343 __func__, name, ret);
aa497613 8344 }
aa497613
SRT		 8345 }
8346out:
8347 return ret;
8348}
8349
8350static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8351{
8352 int ret = 0;
8353
73067981 8354 if (!vreg || vreg->enabled)
aa497613
SRT		 8355 goto out;
8356
8357 ret = ufshcd_config_vreg(dev, vreg, true);
8358 if (!ret)
8359 ret = regulator_enable(vreg->reg);
8360
8361 if (!ret)
8362 vreg->enabled = true;
8363 else
8364 dev_err(dev, "%s: %s enable failed, err=%d\n",
8365 __func__, vreg->name, ret);
8366out:
8367 return ret;
8368}
8369
8370static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8371{
8372 int ret = 0;
8373
f8162ac7 8374 if (!vreg || !vreg->enabled || vreg->always_on)
aa497613
SRT		 8375 goto out;
8376
8377 ret = regulator_disable(vreg->reg);
8378
8379 if (!ret) {
8380 /* ignore errors on applying disable config */
8381 ufshcd_config_vreg(dev, vreg, false);
8382 vreg->enabled = false;
8383 } else {
8384 dev_err(dev, "%s: %s disable failed, err=%d\n",
8385 __func__, vreg->name, ret);
8386 }
8387out:
8388 return ret;
8389}
8390
8391static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8392{
8393 int ret = 0;
8394 struct device *dev = hba->dev;
8395 struct ufs_vreg_info *info = &hba->vreg_info;
8396
aa497613
SRT		 8397 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8398 if (ret)
8399 goto out;
8400
8401 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8402 if (ret)
8403 goto out;
8404
8405 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
aa497613
SRT		 8406
8407out:
8408 if (ret) {
8409 ufshcd_toggle_vreg(dev, info->vccq2, false);
8410 ufshcd_toggle_vreg(dev, info->vccq, false);
8411 ufshcd_toggle_vreg(dev, info->vcc, false);
8412 }
8413 return ret;
8414}
8415
6a771a65
RS		 8416static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8417{
8418 struct ufs_vreg_info *info = &hba->vreg_info;
8419
60b7b823 8420 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 8421}
8422
aa497613
SRT		 8423static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8424{
8425 int ret = 0;
8426
8427 if (!vreg)
8428 goto out;
8429
8430 vreg->reg = devm_regulator_get(dev, vreg->name);
8431 if (IS_ERR(vreg->reg)) {
8432 ret = PTR_ERR(vreg->reg);
8433 dev_err(dev, "%s: %s get failed, err=%d\n",
8434 __func__, vreg->name, ret);
8435 }
8436out:
8437 return ret;
8438}
8439
8440static int ufshcd_init_vreg(struct ufs_hba *hba)
8441{
8442 int ret = 0;
8443 struct device *dev = hba->dev;
8444 struct ufs_vreg_info *info = &hba->vreg_info;
8445
aa497613
SRT		 8446 ret = ufshcd_get_vreg(dev, info->vcc);
8447 if (ret)
8448 goto out;
8449
8450 ret = ufshcd_get_vreg(dev, info->vccq);
b0008625
BH		 8451 if (!ret)
8452 ret = ufshcd_get_vreg(dev, info->vccq2);
aa497613
SRT		 8453out:
8454 return ret;
8455}
8456
6a771a65
RS		 8457static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8458{
8459 struct ufs_vreg_info *info = &hba->vreg_info;
8460
8461 if (info)
8462 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8463
8464 return 0;
8465}
8466
81309c24 8467static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
c6e79dac
SRT		 8468{
8469 int ret = 0;
8470 struct ufs_clk_info *clki;
8471 struct list_head *head = &hba->clk_list_head;
1ab27c9c 8472 unsigned long flags;
911a0771 8473 ktime_t start = ktime_get();
8474 bool clk_state_changed = false;
c6e79dac 8475
566ec9ad 8476 if (list_empty(head))
c6e79dac
SRT		 8477 goto out;
8478
38f3242e
CG		 8479 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8480 if (ret)
8481 return ret;
1e879e8f 8482
c6e79dac
SRT		 8483 list_for_each_entry(clki, head, list) {
8484 if (!IS_ERR_OR_NULL(clki->clk)) {
81309c24
CG		 8485 /*
8486 * Don't disable clocks which are needed
8487 * to keep the link active.
8488 */
8489 if (ufshcd_is_link_active(hba) &&
8490 clki->keep_link_active)
57d104c1
SJ		 8491 continue;
8492
911a0771 8493 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 8494 if (on && !clki->enabled) {
8495 ret = clk_prepare_enable(clki->clk);
8496 if (ret) {
8497 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8498 __func__, clki->name, ret);
8499 goto out;
8500 }
8501 } else if (!on && clki->enabled) {
8502 clk_disable_unprepare(clki->clk);
8503 }
8504 clki->enabled = on;
8505 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8506 clki->name, on ? "en" : "dis");
8507 }
8508 }
1ab27c9c 8509
38f3242e
CG		 8510 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8511 if (ret)
8512 return ret;
1e879e8f 8513
c6e79dac
SRT		 8514out:
8515 if (ret) {
8516 list_for_each_entry(clki, head, list) {
8517 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8518 clk_disable_unprepare(clki->clk);
8519 }
7ff5ab47 8520 } else if (!ret && on) {
1ab27c9c
ST		 8521 spin_lock_irqsave(hba->host->host_lock, flags);
8522 hba->clk_gating.state = CLKS_ON;
7ff5ab47 8523 trace_ufshcd_clk_gating(dev_name(hba->dev),
8524 hba->clk_gating.state);
1ab27c9c 8525 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 8526 }
7ff5ab47 8527
911a0771 8528 if (clk_state_changed)
8529 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8530 (on ? "on" : "off"),
8531 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 8532 return ret;
8533}
8534
8535static int ufshcd_init_clocks(struct ufs_hba *hba)
8536{
8537 int ret = 0;
8538 struct ufs_clk_info *clki;
8539 struct device *dev = hba->dev;
8540 struct list_head *head = &hba->clk_list_head;
8541
566ec9ad 8542 if (list_empty(head))
c6e79dac
SRT		 8543 goto out;
8544
8545 list_for_each_entry(clki, head, list) {
8546 if (!clki->name)
8547 continue;
8548
8549 clki->clk = devm_clk_get(dev, clki->name);
8550 if (IS_ERR(clki->clk)) {
8551 ret = PTR_ERR(clki->clk);
8552 dev_err(dev, "%s: %s clk get failed, %d\n",
8553 __func__, clki->name, ret);
8554 goto out;
8555 }
8556
9e1e8a75
SJ		 8557 /*
8558 * Parse device ref clk freq as per device tree "ref_clk".
8559 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8560 * in ufshcd_alloc_host().
8561 */
8562 if (!strcmp(clki->name, "ref_clk"))
8563 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8564
c6e79dac
SRT		 8565 if (clki->max_freq) {
8566 ret = clk_set_rate(clki->clk, clki->max_freq);
8567 if (ret) {
8568 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8569 __func__, clki->name,
8570 clki->max_freq, ret);
8571 goto out;
8572 }
856b3483 8573 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 8574 }
8575 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8576 clki->name, clk_get_rate(clki->clk));
8577 }
8578out:
8579 return ret;
8580}
8581
5c0c28a8
SRT		 8582static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8583{
8584 int err = 0;
8585
8586 if (!hba->vops)
8587 goto out;
8588
0263bcd0 8589 err = ufshcd_vops_init(hba);
5c0c28a8
SRT		 8590 if (err)
8591 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 8592 __func__, ufshcd_get_var_name(hba), err);
ade921a8 8593out:
5c0c28a8
SRT		 8594 return err;
8595}
8596
8597static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8598{
8599 if (!hba->vops)
8600 return;
8601
0263bcd0 8602 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 8603}
8604
aa497613
SRT		 8605static int ufshcd_hba_init(struct ufs_hba *hba)
8606{
8607 int err;
8608
6a771a65
RS		 8609 /*
8610 * Handle host controller power separately from the UFS device power
8611 * rails as it will help controlling the UFS host controller power
8612 * collapse easily which is different than UFS device power collapse.
8613 * Also, enable the host controller power before we go ahead with rest
8614 * of the initialization here.
8615 */
8616 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 8617 if (err)
8618 goto out;
8619
6a771a65 8620 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 8621 if (err)
8622 goto out;
8623
6a771a65
RS		 8624 err = ufshcd_init_clocks(hba);
8625 if (err)
8626 goto out_disable_hba_vreg;
8627
8628 err = ufshcd_setup_clocks(hba, true);
8629 if (err)
8630 goto out_disable_hba_vreg;
8631
c6e79dac
SRT		 8632 err = ufshcd_init_vreg(hba);
8633 if (err)
8634 goto out_disable_clks;
8635
8636 err = ufshcd_setup_vreg(hba, true);
8637 if (err)
8638 goto out_disable_clks;
8639
aa497613
SRT		 8640 err = ufshcd_variant_hba_init(hba);
8641 if (err)
8642 goto out_disable_vreg;
8643
b6cacaf2
AH		 8644 ufs_debugfs_hba_init(hba);
8645
1d337ec2 8646 hba->is_powered = true;
aa497613
SRT		 8647 goto out;
8648
8649out_disable_vreg:
8650 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 8651out_disable_clks:
8652 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 8653out_disable_hba_vreg:
8654 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 8655out:
8656 return err;
8657}
8658
8659static void ufshcd_hba_exit(struct ufs_hba *hba)
8660{
1d337ec2 8661 if (hba->is_powered) {
4543d9d7
CG		 8662 ufshcd_exit_clk_scaling(hba);
8663 ufshcd_exit_clk_gating(hba);
88b09900
AH		 8664 if (hba->eh_wq)
8665 destroy_workqueue(hba->eh_wq);
b6cacaf2 8666 ufs_debugfs_hba_exit(hba);
1d337ec2
SRT		 8667 ufshcd_variant_hba_exit(hba);
8668 ufshcd_setup_vreg(hba, false);
8669 ufshcd_setup_clocks(hba, false);
8670 ufshcd_setup_hba_vreg(hba, false);
8671 hba->is_powered = false;
09750066 8672 ufs_put_device_desc(hba);
1d337ec2 8673 }
aa497613
SRT		 8674}
8675
57d104c1
SJ		 8676/**
8677 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8678 * power mode
8679 * @hba: per adapter instance
8680 * @pwr_mode: device power mode to set
8681 *
8682 * Returns 0 if requested power mode is set successfully
ad6c8a42 8683 * Returns < 0 if failed to set the requested power mode
57d104c1
SJ		 8684 */
8685static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8686 enum ufs_dev_pwr_mode pwr_mode)
8687{
8688 unsigned char cmd[6] = { START_STOP };
8689 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 8690 struct scsi_device *sdp;
8691 unsigned long flags;
af21c3fd 8692 int ret, retries;
57d104c1 8693
7c48bfd0
AM		 8694 spin_lock_irqsave(hba->host->host_lock, flags);
8695 sdp = hba->sdev_ufs_device;
8696 if (sdp) {
8697 ret = scsi_device_get(sdp);
8698 if (!ret && !scsi_device_online(sdp)) {
8699 ret = -ENODEV;
8700 scsi_device_put(sdp);
8701 }
8702 } else {
8703 ret = -ENODEV;
8704 }
8705 spin_unlock_irqrestore(hba->host->host_lock, flags);
8706
8707 if (ret)
8708 return ret;
57d104c1
SJ		 8709
8710 /*
8711 * If scsi commands fail, the scsi mid-layer schedules scsi error-
8712 * handling, which would wait for host to be resumed. Since we know
8713 * we are functional while we are here, skip host resume in error
8714 * handling context.
8715 */
8716 hba->host->eh_noresume = 1;
57d104c1
SJ		 8717
8718 cmd[4] = pwr_mode << 4;
8719
8720 /*
8721 * Current function would be generally called from the power management
e8064021 8722 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 8723 * already suspended childs.
8724 */
af21c3fd
JK		 8725 for (retries = 3; retries > 0; --retries) {
8726 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8727 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8728 if (!scsi_status_is_check_condition(ret) ||
8729 !scsi_sense_valid(&sshdr) ||
8730 sshdr.sense_key != UNIT_ATTENTION)
8731 break;
8732 }
57d104c1
SJ		 8733 if (ret) {
8734 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 8735 "START_STOP failed for power mode: %d, result %x\n",
8736 pwr_mode, ret);
ad6c8a42
KK		 8737 if (ret > 0) {
8738 if (scsi_sense_valid(&sshdr))
8739 scsi_print_sense_hdr(sdp, NULL, &sshdr);
8740 ret = -EIO;
8741 }
57d104c1
SJ		 8742 }
8743
8744 if (!ret)
8745 hba->curr_dev_pwr_mode = pwr_mode;
1918651f 8746
7c48bfd0 8747 scsi_device_put(sdp);
57d104c1
SJ		 8748 hba->host->eh_noresume = 0;
8749 return ret;
8750}
8751
8752static int ufshcd_link_state_transition(struct ufs_hba *hba,
8753 enum uic_link_state req_link_state,
8754 int check_for_bkops)
8755{
8756 int ret = 0;
8757
8758 if (req_link_state == hba->uic_link_state)
8759 return 0;
8760
8761 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8762 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236 8763 if (!ret) {
57d104c1 8764 ufshcd_set_link_hibern8(hba);
4db7a236
CG		 8765 } else {
8766 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8767 __func__, ret);
57d104c1 8768 goto out;
4db7a236 8769 }
57d104c1
SJ		 8770 }
8771 /*
8772 * If autobkops is enabled, link can't be turned off because
fe1d4c2e
AH		 8773 * turning off the link would also turn off the device, except in the
8774 * case of DeepSleep where the device is expected to remain powered.
57d104c1
SJ		 8775 */
8776 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 8777 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 8778 /*
8779 * Let's make sure that link is in low power mode, we are doing
8780 * this currently by putting the link in Hibern8. Otherway to
8781 * put the link in low power mode is to send the DME end point
8782 * to device and then send the DME reset command to local
8783 * unipro. But putting the link in hibern8 is much faster.
fe1d4c2e
AH		 8784 *
8785 * Note also that putting the link in Hibern8 is a requirement
8786 * for entering DeepSleep.
f3099fbd
YG		 8787 */
8788 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236
CG		 8789 if (ret) {
8790 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8791 __func__, ret);
f3099fbd 8792 goto out;
4db7a236 8793 }
57d104c1
SJ		 8794 /*
8795 * Change controller state to "reset state" which
8796 * should also put the link in off/reset state
8797 */
5cac1095 8798 ufshcd_hba_stop(hba);
57d104c1
SJ		 8799 /*
8800 * TODO: Check if we need any delay to make sure that
8801 * controller is reset
8802 */
8803 ufshcd_set_link_off(hba);
8804 }
8805
8806out:
8807 return ret;
8808}
8809
8810static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8811{
c4df6eed
SC		 8812 bool vcc_off = false;
8813
b799fdf7
YG		 8814 /*
8815 * It seems some UFS devices may keep drawing more than sleep current
8816 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8817 * To avoid this situation, add 2ms delay before putting these UFS
8818 * rails in LPM mode.
8819 */
8820 if (!ufshcd_is_link_active(hba) &&
8821 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8822 usleep_range(2000, 2100);
8823
57d104c1
SJ		 8824 /*
8825 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8826 * power.
8827 *
8828 * If UFS device and link is in OFF state, all power supplies (VCC,
8829 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8830 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8831 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8832 *
8833 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8834 * in low power state which would save some power.
3d17b9b5
AD		 8835 *
8836 * If Write Booster is enabled and the device needs to flush the WB
8837 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 8838 */
8839 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8840 !hba->dev_info.is_lu_power_on_wp) {
8841 ufshcd_setup_vreg(hba, false);
c4df6eed 8842 vcc_off = true;
57d104c1 8843 } else if (!ufshcd_is_ufs_dev_active(hba)) {
51dd905b 8844 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
c4df6eed 8845 vcc_off = true;
23043dd8 8846 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
57d104c1
SJ		 8847 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8848 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8849 }
8850 }
c4df6eed
SC		 8851
8852 /*
8853 * Some UFS devices require delay after VCC power rail is turned-off.
8854 */
8855 if (vcc_off && hba->vreg_info.vcc &&
8856 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8857 usleep_range(5000, 5100);
57d104c1
SJ		 8858}
8859
9bb25e5d 8860#ifdef CONFIG_PM
57d104c1
SJ		 8861static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8862{
8863 int ret = 0;
8864
8865 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8866 !hba->dev_info.is_lu_power_on_wp) {
8867 ret = ufshcd_setup_vreg(hba, true);
8868 } else if (!ufshcd_is_ufs_dev_active(hba)) {
23043dd8 8869 if (!ufshcd_is_link_active(hba)) {
57d104c1
SJ		 8870 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8871 if (ret)
8872 goto vcc_disable;
8873 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8874 if (ret)
8875 goto vccq_lpm;
8876 }
69d72ac8 8877 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 8878 }
8879 goto out;
8880
8881vccq_lpm:
8882 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8883vcc_disable:
8884 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8885out:
8886 return ret;
8887}
9bb25e5d 8888#endif /* CONFIG_PM */
57d104c1
SJ		 8889
8890static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8891{
dd7143e2 8892 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8893 ufshcd_setup_hba_vreg(hba, false);
8894}
8895
8896static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8897{
dd7143e2 8898 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 8899 ufshcd_setup_hba_vreg(hba, true);
8900}
8901
b294ff3e 8902static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8903{
57d104c1 8904 int ret = 0;
fe1d4c2e 8905 int check_for_bkops;
57d104c1
SJ		 8906 enum ufs_pm_level pm_lvl;
8907 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8908 enum uic_link_state req_link_state;
8909
b294ff3e 8910 hba->pm_op_in_progress = true;
4c6cb9ed
BVA		 8911 if (pm_op != UFS_SHUTDOWN_PM) {
8912 pm_lvl = pm_op == UFS_RUNTIME_PM ?
57d104c1
SJ		 8913 hba->rpm_lvl : hba->spm_lvl;
8914 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8915 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8916 } else {
8917 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8918 req_link_state = UIC_LINK_OFF_STATE;
8919 }
8920
f02bc975
DP		 8921 ufshpb_suspend(hba);
8922
7a3e97b0 8923 /*
57d104c1
SJ		 8924 * If we can't transition into any of the low power modes
8925 * just gate the clocks.
7a3e97b0 8926 */
1ab27c9c
ST		 8927 ufshcd_hold(hba, false);
8928 hba->clk_gating.is_suspended = true;
8929
348e1bc5
SC		 8930 if (ufshcd_is_clkscaling_supported(hba))
8931 ufshcd_clk_scaling_suspend(hba, true);
d6fcf81a 8932
57d104c1
SJ		 8933 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8934 req_link_state == UIC_LINK_ACTIVE_STATE) {
b294ff3e 8935 goto vops_suspend;
57d104c1 8936 }
7a3e97b0 8937
57d104c1
SJ		 8938 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8939 (req_link_state == hba->uic_link_state))
b294ff3e 8940 goto enable_scaling;
57d104c1
SJ		 8941
8942 /* UFS device & link must be active before we enter in this function */
8943 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8944 ret = -EINVAL;
b294ff3e 8945 goto enable_scaling;
57d104c1
SJ		 8946 }
8947
4c6cb9ed 8948 if (pm_op == UFS_RUNTIME_PM) {
374a246e
SJ		 8949 if (ufshcd_can_autobkops_during_suspend(hba)) {
8950 /*
8951 * The device is idle with no requests in the queue,
8952 * allow background operations if bkops status shows
8953 * that performance might be impacted.
8954 */
8955 ret = ufshcd_urgent_bkops(hba);
8956 if (ret)
b294ff3e 8957 goto enable_scaling;
374a246e
SJ		 8958 } else {
8959 /* make sure that auto bkops is disabled */
8960 ufshcd_disable_auto_bkops(hba);
8961 }
3d17b9b5 8962 /*
51dd905b
SC		 8963 * If device needs to do BKOP or WB buffer flush during
8964 * Hibern8, keep device power mode as "active power mode"
8965 * and VCC supply.
3d17b9b5 8966 */
51dd905b
SC		 8967 hba->dev_info.b_rpm_dev_flush_capable =
8968 hba->auto_bkops_enabled ||
8969 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8970 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8971 ufshcd_is_auto_hibern8_enabled(hba))) &&
8972 ufshcd_wb_need_flush(hba));
8973 }
8974
6948a96a
KK		 8975 flush_work(&hba->eeh_work);
8976
9561f584
PW		 8977 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
8978 if (ret)
8979 goto enable_scaling;
8980
51dd905b 8981 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
4c6cb9ed 8982 if (pm_op != UFS_RUNTIME_PM)
51dd905b
SC		 8983 /* ensure that bkops is disabled */
8984 ufshcd_disable_auto_bkops(hba);
57d104c1 8985
51dd905b
SC		 8986 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8987 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8988 if (ret)
b294ff3e 8989 goto enable_scaling;
51dd905b 8990 }
57d104c1
SJ		 8991 }
8992
fe1d4c2e
AH		 8993 /*
8994 * In the case of DeepSleep, the device is expected to remain powered
8995 * with the link off, so do not check for bkops.
8996 */
8997 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8998 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
57d104c1
SJ		 8999 if (ret)
9000 goto set_dev_active;
9001
b294ff3e 9002vops_suspend:
57d104c1
SJ		 9003 /*
9004 * Call vendor specific suspend callback. As these callbacks may access
9005 * vendor specific host controller register space call them before the
9006 * host clocks are ON.
9007 */
9561f584 9008 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
0263bcd0
YG		 9009 if (ret)
9010 goto set_link_active;
57d104c1
SJ		 9011 goto out;
9012
57d104c1 9013set_link_active:
fe1d4c2e
AH		 9014 /*
9015 * Device hardware reset is required to exit DeepSleep. Also, for
9016 * DeepSleep, the link is off so host reset and restore will be done
9017 * further below.
9018 */
9019 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9020 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9021 WARN_ON(!ufshcd_is_link_off(hba));
9022 }
57d104c1
SJ		 9023 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9024 ufshcd_set_link_active(hba);
9025 else if (ufshcd_is_link_off(hba))
9026 ufshcd_host_reset_and_restore(hba);
9027set_dev_active:
fe1d4c2e
AH		 9028 /* Can also get here needing to exit DeepSleep */
9029 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9030 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9031 ufshcd_host_reset_and_restore(hba);
9032 }
57d104c1
SJ		 9033 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9034 ufshcd_disable_auto_bkops(hba);
b294ff3e 9035enable_scaling:
348e1bc5
SC		 9036 if (ufshcd_is_clkscaling_supported(hba))
9037 ufshcd_clk_scaling_suspend(hba, false);
9038
51dd905b 9039 hba->dev_info.b_rpm_dev_flush_capable = false;
57d104c1 9040out:
51dd905b
SC		 9041 if (hba->dev_info.b_rpm_dev_flush_capable) {
9042 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9043 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9044 }
9045
b294ff3e
AD		 9046 if (ret) {
9047 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9048 hba->clk_gating.is_suspended = false;
9049 ufshcd_release(hba);
f02bc975 9050 ufshpb_resume(hba);
b294ff3e
AD		 9051 }
9052 hba->pm_op_in_progress = false;
57d104c1 9053 return ret;
7a3e97b0
SY		 9054}
9055
75d645a6 9056#ifdef CONFIG_PM
b294ff3e 9057static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 9058{
57d104c1 9059 int ret;
b294ff3e 9060 enum uic_link_state old_link_state = hba->uic_link_state;
57d104c1 9061
b294ff3e 9062 hba->pm_op_in_progress = true;
57d104c1 9063
7a3e97b0 9064 /*
57d104c1
SJ		 9065 * Call vendor specific resume callback. As these callbacks may access
9066 * vendor specific host controller register space call them when the
9067 * host clocks are ON.
7a3e97b0 9068 */
0263bcd0
YG		 9069 ret = ufshcd_vops_resume(hba, pm_op);
9070 if (ret)
b294ff3e 9071 goto out;
57d104c1 9072
fe1d4c2e
AH		 9073 /* For DeepSleep, the only supported option is to have the link off */
9074 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9075
57d104c1
SJ		 9076 if (ufshcd_is_link_hibern8(hba)) {
9077 ret = ufshcd_uic_hibern8_exit(hba);
4db7a236 9078 if (!ret) {
57d104c1 9079 ufshcd_set_link_active(hba);
4db7a236
CG		 9080 } else {
9081 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9082 __func__, ret);
57d104c1 9083 goto vendor_suspend;
4db7a236 9084 }
57d104c1 9085 } else if (ufshcd_is_link_off(hba)) {
57d104c1 9086 /*
089f5b64
AD		 9087 * A full initialization of the host and the device is
9088 * required since the link was put to off during suspend.
fe1d4c2e
AH		 9089 * Note, in the case of DeepSleep, the device will exit
9090 * DeepSleep due to device reset.
089f5b64
AD		 9091 */
9092 ret = ufshcd_reset_and_restore(hba);
9093 /*
9094 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 9095 * set the link state as active
9096 */
9097 if (ret || !ufshcd_is_link_active(hba))
9098 goto vendor_suspend;
9099 }
9100
9101 if (!ufshcd_is_ufs_dev_active(hba)) {
9102 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9103 if (ret)
9104 goto set_old_link_state;
9105 }
9106
4e768e76 9107 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9108 ufshcd_enable_auto_bkops(hba);
9109 else
9110 /*
9111 * If BKOPs operations are urgently needed at this moment then
9112 * keep auto-bkops enabled or else disable it.
9113 */
9114 ufshcd_urgent_bkops(hba);
9115
cd469475
AH		 9116 if (hba->ee_usr_mask)
9117 ufshcd_write_ee_control(hba);
9118
348e1bc5
SC		 9119 if (ufshcd_is_clkscaling_supported(hba))
9120 ufshcd_clk_scaling_suspend(hba, false);
856b3483 9121
51dd905b
SC		 9122 if (hba->dev_info.b_rpm_dev_flush_capable) {
9123 hba->dev_info.b_rpm_dev_flush_capable = false;
9124 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9125 }
9126
b294ff3e
AD		 9127 /* Enable Auto-Hibernate if configured */
9128 ufshcd_auto_hibern8_enable(hba);
f02bc975
DP		 9129
9130 ufshpb_resume(hba);
57d104c1
SJ		 9131 goto out;
9132
9133set_old_link_state:
9134 ufshcd_link_state_transition(hba, old_link_state, 0);
9135vendor_suspend:
9561f584
PW		 9136 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9137 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
b294ff3e
AD		 9138out:
9139 if (ret)
9140 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9141 hba->clk_gating.is_suspended = false;
9142 ufshcd_release(hba);
9143 hba->pm_op_in_progress = false;
9144 return ret;
9145}
9146
9147static int ufshcd_wl_runtime_suspend(struct device *dev)
9148{
9149 struct scsi_device *sdev = to_scsi_device(dev);
9150 struct ufs_hba *hba;
9151 int ret;
9152 ktime_t start = ktime_get();
9153
9154 hba = shost_priv(sdev->host);
9155
9156 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9157 if (ret)
9158 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9159
9160 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9161 ktime_to_us(ktime_sub(ktime_get(), start)),
9162 hba->curr_dev_pwr_mode, hba->uic_link_state);
9163
9164 return ret;
9165}
9166
9167static int ufshcd_wl_runtime_resume(struct device *dev)
9168{
9169 struct scsi_device *sdev = to_scsi_device(dev);
9170 struct ufs_hba *hba;
9171 int ret = 0;
9172 ktime_t start = ktime_get();
9173
9174 hba = shost_priv(sdev->host);
9175
9176 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9177 if (ret)
9178 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9179
9180 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9181 ktime_to_us(ktime_sub(ktime_get(), start)),
9182 hba->curr_dev_pwr_mode, hba->uic_link_state);
9183
9184 return ret;
9185}
75d645a6 9186#endif
b294ff3e
AD		 9187
9188#ifdef CONFIG_PM_SLEEP
9189static int ufshcd_wl_suspend(struct device *dev)
9190{
9191 struct scsi_device *sdev = to_scsi_device(dev);
9192 struct ufs_hba *hba;
9193 int ret = 0;
9194 ktime_t start = ktime_get();
9195
9196 hba = shost_priv(sdev->host);
9197 down(&hba->host_sem);
9198
9199 if (pm_runtime_suspended(dev))
9200 goto out;
9201
9202 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9203 if (ret) {
9204 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9205 up(&hba->host_sem);
9206 }
9207
9208out:
9209 if (!ret)
9210 hba->is_sys_suspended = true;
9211 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9212 ktime_to_us(ktime_sub(ktime_get(), start)),
9213 hba->curr_dev_pwr_mode, hba->uic_link_state);
9214
9215 return ret;
9216}
9217
9218static int ufshcd_wl_resume(struct device *dev)
9219{
9220 struct scsi_device *sdev = to_scsi_device(dev);
9221 struct ufs_hba *hba;
9222 int ret = 0;
9223 ktime_t start = ktime_get();
9224
9225 hba = shost_priv(sdev->host);
9226
9227 if (pm_runtime_suspended(dev))
9228 goto out;
9229
9230 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9231 if (ret)
9232 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9233out:
9234 trace_ufshcd_wl_resume(dev_name(dev), ret,
9235 ktime_to_us(ktime_sub(ktime_get(), start)),
9236 hba->curr_dev_pwr_mode, hba->uic_link_state);
9237 if (!ret)
9238 hba->is_sys_suspended = false;
9239 up(&hba->host_sem);
9240 return ret;
9241}
9242#endif
9243
9244static void ufshcd_wl_shutdown(struct device *dev)
9245{
9246 struct scsi_device *sdev = to_scsi_device(dev);
9247 struct ufs_hba *hba;
9248
9249 hba = shost_priv(sdev->host);
9250
9251 down(&hba->host_sem);
9252 hba->shutting_down = true;
9253 up(&hba->host_sem);
9254
9255 /* Turn on everything while shutting down */
9256 ufshcd_rpm_get_sync(hba);
9257 scsi_device_quiesce(sdev);
9258 shost_for_each_device(sdev, hba->host) {
9259 if (sdev == hba->sdev_ufs_device)
9260 continue;
9261 scsi_device_quiesce(sdev);
9262 }
9263 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9264}
9265
9266/**
9267 * ufshcd_suspend - helper function for suspend operations
9268 * @hba: per adapter instance
9269 *
9270 * This function will put disable irqs, turn off clocks
9271 * and set vreg and hba-vreg in lpm mode.
b294ff3e
AD		 9272 */
9273static int ufshcd_suspend(struct ufs_hba *hba)
9274{
9275 int ret;
9276
9277 if (!hba->is_powered)
9278 return 0;
9279 /*
9280 * Disable the host irq as host controller as there won't be any
9281 * host controller transaction expected till resume.
9282 */
57d104c1 9283 ufshcd_disable_irq(hba);
b294ff3e
AD		 9284 ret = ufshcd_setup_clocks(hba, false);
9285 if (ret) {
9286 ufshcd_enable_irq(hba);
9287 return ret;
9288 }
2dec9475
CG		 9289 if (ufshcd_is_clkgating_allowed(hba)) {
9290 hba->clk_gating.state = CLKS_OFF;
9291 trace_ufshcd_clk_gating(dev_name(hba->dev),
9292 hba->clk_gating.state);
9293 }
b294ff3e
AD		 9294
9295 ufshcd_vreg_set_lpm(hba);
9296 /* Put the host controller in low power mode if possible */
9297 ufshcd_hba_vreg_set_lpm(hba);
9298 return ret;
9299}
9300
9bb25e5d 9301#ifdef CONFIG_PM
b294ff3e
AD		 9302/**
9303 * ufshcd_resume - helper function for resume operations
9304 * @hba: per adapter instance
9305 *
9306 * This function basically turns on the regulators, clocks and
9307 * irqs of the hba.
b294ff3e
AD		 9308 *
9309 * Returns 0 for success and non-zero for failure
9310 */
9311static int ufshcd_resume(struct ufs_hba *hba)
9312{
9313 int ret;
9314
9315 if (!hba->is_powered)
9316 return 0;
9317
9318 ufshcd_hba_vreg_set_hpm(hba);
9319 ret = ufshcd_vreg_set_hpm(hba);
9320 if (ret)
9321 goto out;
9322
9323 /* Make sure clocks are enabled before accessing controller */
9324 ret = ufshcd_setup_clocks(hba, true);
9325 if (ret)
9326 goto disable_vreg;
9327
9328 /* enable the host irq as host controller would be active soon */
9329 ufshcd_enable_irq(hba);
9330 goto out;
9331
528db9e5
ZC		 9332disable_vreg:
9333 ufshcd_vreg_set_lpm(hba);
57d104c1 9334out:
8808b4e9 9335 if (ret)
e965e5e0 9336 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
57d104c1
SJ		 9337 return ret;
9338}
9bb25e5d 9339#endif /* CONFIG_PM */
57d104c1 9340
9bb25e5d 9341#ifdef CONFIG_PM_SLEEP
57d104c1 9342/**
f1ecbe1e
BVA		 9343 * ufshcd_system_suspend - system suspend callback
9344 * @dev: Device associated with the UFS controller.
57d104c1 9345 *
f1ecbe1e
BVA		 9346 * Executed before putting the system into a sleep state in which the contents
9347 * of main memory are preserved.
57d104c1
SJ		 9348 *
9349 * Returns 0 for success and non-zero for failure
9350 */
f1ecbe1e 9351int ufshcd_system_suspend(struct device *dev)
57d104c1 9352{
f1ecbe1e 9353 struct ufs_hba *hba = dev_get_drvdata(dev);
57d104c1 9354 int ret = 0;
7ff5ab47 9355 ktime_t start = ktime_get();
57d104c1 9356
b294ff3e 9357 if (pm_runtime_suspended(hba->dev))
0b257734 9358 goto out;
57d104c1 9359
b294ff3e 9360 ret = ufshcd_suspend(hba);
57d104c1 9361out:
7ff5ab47 9362 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9363 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9364 hba->curr_dev_pwr_mode, hba->uic_link_state);
57d104c1
SJ		 9365 return ret;
9366}
9367EXPORT_SYMBOL(ufshcd_system_suspend);
9368
9369/**
f1ecbe1e
BVA		 9370 * ufshcd_system_resume - system resume callback
9371 * @dev: Device associated with the UFS controller.
9372 *
9373 * Executed after waking the system up from a sleep state in which the contents
9374 * of main memory were preserved.
57d104c1
SJ		 9375 *
9376 * Returns 0 for success and non-zero for failure
9377 */
f1ecbe1e 9378int ufshcd_system_resume(struct device *dev)
57d104c1 9379{
f1ecbe1e 9380 struct ufs_hba *hba = dev_get_drvdata(dev);
7ff5ab47 9381 ktime_t start = ktime_get();
f1ecbe1e 9382 int ret = 0;
7ff5ab47 9383
b294ff3e 9384 if (pm_runtime_suspended(hba->dev))
7ff5ab47 9385 goto out;
b294ff3e
AD		 9386
9387 ret = ufshcd_resume(hba);
9388
7ff5ab47 9389out:
9390 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9391 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9392 hba->curr_dev_pwr_mode, hba->uic_link_state);
b294ff3e 9393
7ff5ab47 9394 return ret;
7a3e97b0 9395}
57d104c1 9396EXPORT_SYMBOL(ufshcd_system_resume);
9bb25e5d 9397#endif /* CONFIG_PM_SLEEP */
3b1d0580 9398
9bb25e5d 9399#ifdef CONFIG_PM
57d104c1 9400/**
f1ecbe1e
BVA		 9401 * ufshcd_runtime_suspend - runtime suspend callback
9402 * @dev: Device associated with the UFS controller.
57d104c1
SJ		 9403 *
9404 * Check the description of ufshcd_suspend() function for more details.
9405 *
9406 * Returns 0 for success and non-zero for failure
9407 */
f1ecbe1e 9408int ufshcd_runtime_suspend(struct device *dev)
66ec6d59 9409{
f1ecbe1e 9410 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9411 int ret;
7ff5ab47 9412 ktime_t start = ktime_get();
9413
b294ff3e
AD		 9414 ret = ufshcd_suspend(hba);
9415
7ff5ab47 9416 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9417 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9418 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9419 return ret;
66ec6d59
SRT		 9420}
9421EXPORT_SYMBOL(ufshcd_runtime_suspend);
9422
57d104c1
SJ		 9423/**
9424 * ufshcd_runtime_resume - runtime resume routine
f1ecbe1e 9425 * @dev: Device associated with the UFS controller.
57d104c1 9426 *
b294ff3e 9427 * This function basically brings controller
57d104c1
SJ		 9428 * to active state. Following operations are done in this function:
9429 *
9430 * 1. Turn on all the controller related clocks
b294ff3e 9431 * 2. Turn ON VCC rail
57d104c1 9432 */
f1ecbe1e 9433int ufshcd_runtime_resume(struct device *dev)
66ec6d59 9434{
f1ecbe1e 9435 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9436 int ret;
7ff5ab47 9437 ktime_t start = ktime_get();
9438
b294ff3e
AD		 9439 ret = ufshcd_resume(hba);
9440
7ff5ab47 9441 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9442 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9443 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9444 return ret;
66ec6d59
SRT		 9445}
9446EXPORT_SYMBOL(ufshcd_runtime_resume);
9bb25e5d 9447#endif /* CONFIG_PM */
66ec6d59 9448
57d104c1
SJ		 9449/**
9450 * ufshcd_shutdown - shutdown routine
9451 * @hba: per adapter instance
9452 *
b294ff3e
AD		 9453 * This function would turn off both UFS device and UFS hba
9454 * regulators. It would also disable clocks.
57d104c1
SJ		 9455 *
9456 * Returns 0 always to allow force shutdown even in case of errors.
9457 */
9458int ufshcd_shutdown(struct ufs_hba *hba)
9459{
57d104c1
SJ		 9460 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9461 goto out;
9462
e92643db 9463 pm_runtime_get_sync(hba->dev);
57d104c1 9464
b294ff3e 9465 ufshcd_suspend(hba);
57d104c1 9466out:
88a92d6a 9467 hba->is_powered = false;
57d104c1
SJ		 9468 /* allow force shutdown even in case of errors */
9469 return 0;
9470}
9471EXPORT_SYMBOL(ufshcd_shutdown);
9472
7a3e97b0 9473/**
3b1d0580 9474 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 9475 * data structure memory
8aa29f19 9476 * @hba: per adapter instance
7a3e97b0 9477 */
3b1d0580 9478void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 9479{
b294ff3e
AD		 9480 if (hba->sdev_ufs_device)
9481 ufshcd_rpm_get_sync(hba);
e88e2d32 9482 ufs_hwmon_remove(hba);
df032bf2 9483 ufs_bsg_remove(hba);
4b5f4907 9484 ufshpb_remove(hba);
cbb6813e 9485 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 9486 blk_cleanup_queue(hba->tmf_queue);
9487 blk_mq_free_tag_set(&hba->tmf_tag_set);
cfdf9c91 9488 scsi_remove_host(hba->host);
7a3e97b0 9489 /* disable interrupts */
2fbd009b 9490 ufshcd_disable_intr(hba, hba->intr_mask);
5cac1095 9491 ufshcd_hba_stop(hba);
aa497613 9492 ufshcd_hba_exit(hba);
3b1d0580
VH		 9493}
9494EXPORT_SYMBOL_GPL(ufshcd_remove);
9495
47555a5c
YG		 9496/**
9497 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9498 * @hba: pointer to Host Bus Adapter (HBA)
9499 */
9500void ufshcd_dealloc_host(struct ufs_hba *hba)
9501{
9502 scsi_host_put(hba->host);
9503}
9504EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9505
ca3d7bf9
AM		 9506/**
9507 * ufshcd_set_dma_mask - Set dma mask based on the controller
9508 * addressing capability
9509 * @hba: per adapter instance
9510 *
9511 * Returns 0 for success, non-zero for failure
9512 */
9513static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9514{
9515 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9516 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9517 return 0;
9518 }
9519 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9520}
9521
7a3e97b0 9522/**
5c0c28a8 9523 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 9524 * @dev: pointer to device handle
9525 * @hba_handle: driver private handle
7a3e97b0
SY		 9526 * Returns 0 on success, non-zero value on failure
9527 */
5c0c28a8 9528int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 9529{
9530 struct Scsi_Host *host;
9531 struct ufs_hba *hba;
5c0c28a8 9532 int err = 0;
7a3e97b0 9533
3b1d0580
VH		 9534 if (!dev) {
9535 dev_err(dev,
9536 "Invalid memory reference for dev is NULL\n");
9537 err = -ENODEV;
7a3e97b0
SY		 9538 goto out_error;
9539 }
9540
7a3e97b0
SY		 9541 host = scsi_host_alloc(&ufshcd_driver_template,
9542 sizeof(struct ufs_hba));
9543 if (!host) {
3b1d0580 9544 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 9545 err = -ENOMEM;
3b1d0580 9546 goto out_error;
7a3e97b0 9547 }
eaab9b57 9548 host->nr_maps = HCTX_TYPE_POLL + 1;
7a3e97b0 9549 hba = shost_priv(host);
7a3e97b0 9550 hba->host = host;
3b1d0580 9551 hba->dev = dev;
9e1e8a75 9552 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
1cbc9ad3 9553 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
566ec9ad 9554 INIT_LIST_HEAD(&hba->clk_list_head);
169f5eb2
BVA		 9555 spin_lock_init(&hba->outstanding_lock);
9556
9557 *hba_handle = hba;
566ec9ad 9558
5c0c28a8
SRT		 9559out_error:
9560 return err;
9561}
9562EXPORT_SYMBOL(ufshcd_alloc_host);
9563
69a6c269
BVA		 9564/* This function exists because blk_mq_alloc_tag_set() requires this. */
9565static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9566 const struct blk_mq_queue_data *qd)
9567{
9568 WARN_ON_ONCE(true);
9569 return BLK_STS_NOTSUPP;
9570}
9571
9572static const struct blk_mq_ops ufshcd_tmf_ops = {
9573 .queue_rq = ufshcd_queue_tmf,
9574};
9575
5c0c28a8
SRT		 9576/**
9577 * ufshcd_init - Driver initialization routine
9578 * @hba: per-adapter instance
9579 * @mmio_base: base register address
9580 * @irq: Interrupt line of device
9581 * Returns 0 on success, non-zero value on failure
9582 */
9583int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9584{
9585 int err;
9586 struct Scsi_Host *host = hba->host;
9587 struct device *dev = hba->dev;
88b09900 9588 char eh_wq_name[sizeof("ufs_eh_wq_00")];
5c0c28a8 9589
21ad0e49
BVA		 9590 /*
9591 * dev_set_drvdata() must be called before any callbacks are registered
9592 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
9593 * sysfs).
9594 */
9595 dev_set_drvdata(dev, hba);
9596
5c0c28a8
SRT		 9597 if (!mmio_base) {
9598 dev_err(hba->dev,
9599 "Invalid memory reference for mmio_base is NULL\n");
9600 err = -ENODEV;
9601 goto out_error;
9602 }
9603
3b1d0580
VH		 9604 hba->mmio_base = mmio_base;
9605 hba->irq = irq;
90b8491c 9606 hba->vps = &ufs_hba_vps;
7a3e97b0 9607
aa497613 9608 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 9609 if (err)
9610 goto out_error;
9611
7a3e97b0 9612 /* Read capabilities registers */
df043c74
ST		 9613 err = ufshcd_hba_capabilities(hba);
9614 if (err)
9615 goto out_disable;
7a3e97b0
SY		 9616
9617 /* Get UFS version supported by the controller */
9618 hba->ufs_version = ufshcd_get_ufs_version(hba);
9619
2fbd009b
SJ		 9620 /* Get Interrupt bit mask per version */
9621 hba->intr_mask = ufshcd_get_intr_mask(hba);
9622
ca3d7bf9
AM		 9623 err = ufshcd_set_dma_mask(hba);
9624 if (err) {
9625 dev_err(hba->dev, "set dma mask failed\n");
9626 goto out_disable;
9627 }
9628
7a3e97b0
SY		 9629 /* Allocate memory for host memory space */
9630 err = ufshcd_memory_alloc(hba);
9631 if (err) {
3b1d0580
VH		 9632 dev_err(hba->dev, "Memory allocation failed\n");
9633 goto out_disable;
7a3e97b0
SY		 9634 }
9635
9636 /* Configure LRB */
9637 ufshcd_host_memory_configure(hba);
9638
945c3cca
BVA		 9639 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9640 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
7a3e97b0 9641 host->max_id = UFSHCD_MAX_ID;
0ce147d4 9642 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 9643 host->max_channel = UFSHCD_MAX_CHANNEL;
9644 host->unique_id = host->host_no;
a851b2bd 9645 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 9646
7eb584db
DR		 9647 hba->max_pwr_info.is_valid = false;
9648
88b09900
AH		 9649 /* Initialize work queues */
9650 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9651 hba->host->host_no);
9652 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9653 if (!hba->eh_wq) {
9654 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9655 __func__);
9656 err = -ENOMEM;
9657 goto out_disable;
9658 }
9659 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 9660 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 9661
9cd20d3f 9662 sema_init(&hba->host_sem, 1);
88a92d6a 9663
6ccf44fe
SJ		 9664 /* Initialize UIC command mutex */
9665 mutex_init(&hba->uic_cmd_mutex);
9666
5a0b0cb9
SRT		 9667 /* Initialize mutex for device management commands */
9668 mutex_init(&hba->dev_cmd.lock);
9669
cd469475
AH		 9670 /* Initialize mutex for exception event control */
9671 mutex_init(&hba->ee_ctrl_mutex);
9672
a3cd5ec5 9673 init_rwsem(&hba->clk_scaling_lock);
9674
1ab27c9c 9675 ufshcd_init_clk_gating(hba);
199ef13c 9676
eebcc196
VG		 9677 ufshcd_init_clk_scaling(hba);
9678
199ef13c
YG		 9679 /*
9680 * In order to avoid any spurious interrupt immediately after
9681 * registering UFS controller interrupt handler, clear any pending UFS
9682 * interrupt status and disable all the UFS interrupts.
9683 */
9684 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9685 REG_INTERRUPT_STATUS);
9686 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9687 /*
9688 * Make sure that UFS interrupts are disabled and any pending interrupt
9689 * status is cleared before registering UFS interrupt handler.
9690 */
9691 mb();
9692
7a3e97b0 9693 /* IRQ registration */
2953f850 9694 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 9695 if (err) {
3b1d0580 9696 dev_err(hba->dev, "request irq failed\n");
4543d9d7 9697 goto out_disable;
57d104c1
SJ		 9698 } else {
9699 hba->is_irq_enabled = true;
7a3e97b0
SY		 9700 }
9701
3b1d0580 9702 err = scsi_add_host(host, hba->dev);
7a3e97b0 9703 if (err) {
3b1d0580 9704 dev_err(hba->dev, "scsi_add_host failed\n");
4543d9d7 9705 goto out_disable;
7a3e97b0
SY		 9706 }
9707
69a6c269
BVA		 9708 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9709 .nr_hw_queues = 1,
9710 .queue_depth = hba->nutmrs,
9711 .ops = &ufshcd_tmf_ops,
9712 .flags = BLK_MQ_F_NO_SCHED,
9713 };
9714 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9715 if (err < 0)
511a083b 9716 goto out_remove_scsi_host;
69a6c269
BVA		 9717 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9718 if (IS_ERR(hba->tmf_queue)) {
9719 err = PTR_ERR(hba->tmf_queue);
9720 goto free_tmf_tag_set;
9721 }
f5ef336f
AH		 9722 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
9723 sizeof(*hba->tmf_rqs), GFP_KERNEL);
9724 if (!hba->tmf_rqs) {
9725 err = -ENOMEM;
9726 goto free_tmf_queue;
9727 }
69a6c269 9728
d8d9f793 9729 /* Reset the attached device */
31a5d9ca 9730 ufshcd_device_reset(hba);
d8d9f793 9731
df043c74
ST		 9732 ufshcd_init_crypto(hba);
9733
6ccf44fe
SJ		 9734 /* Host controller enable */
9735 err = ufshcd_hba_enable(hba);
7a3e97b0 9736 if (err) {
6ccf44fe 9737 dev_err(hba->dev, "Host controller enable failed\n");
e965e5e0 9738 ufshcd_print_evt_hist(hba);
6ba65588 9739 ufshcd_print_host_state(hba);
69a6c269 9740 goto free_tmf_queue;
7a3e97b0 9741 }
6ccf44fe 9742
0c8f7586 9743 /*
9744 * Set the default power management level for runtime and system PM.
9745 * Default power saving mode is to keep UFS link in Hibern8 state
9746 * and UFS device in sleep state.
9747 */
9748 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9749 UFS_SLEEP_PWR_MODE,
9750 UIC_LINK_HIBERN8_STATE);
9751 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9752 UFS_SLEEP_PWR_MODE,
9753 UIC_LINK_HIBERN8_STATE);
9754
51dd905b
SC		 9755 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9756 ufshcd_rpm_dev_flush_recheck_work);
9757
ad448378 9758 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 9759 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 9760 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9761 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9762 }
9763
62694735
SRT		 9764 /* Hold auto suspend until async scan completes */
9765 pm_runtime_get_sync(dev);
38135535 9766 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 9767 /*
7caf489b 9768 * We are assuming that device wasn't put in sleep/power-down
9769 * state exclusively during the boot stage before kernel.
9770 * This assumption helps avoid doing link startup twice during
9771 * ufshcd_probe_hba().
57d104c1 9772 */
7caf489b 9773 ufshcd_set_ufs_dev_active(hba);
57d104c1 9774
6ccf44fe 9775 async_schedule(ufshcd_async_scan, hba);
cbb6813e 9776 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 9777
1084514c 9778 device_enable_async_suspend(dev);
7a3e97b0
SY		 9779 return 0;
9780
69a6c269
BVA		 9781free_tmf_queue:
9782 blk_cleanup_queue(hba->tmf_queue);
9783free_tmf_tag_set:
9784 blk_mq_free_tag_set(&hba->tmf_tag_set);
3b1d0580
VH		 9785out_remove_scsi_host:
9786 scsi_remove_host(hba->host);
3b1d0580 9787out_disable:
57d104c1 9788 hba->is_irq_enabled = false;
aa497613 9789 ufshcd_hba_exit(hba);
3b1d0580
VH		 9790out_error:
9791 return err;
9792}
9793EXPORT_SYMBOL_GPL(ufshcd_init);
9794
b294ff3e
AD		 9795void ufshcd_resume_complete(struct device *dev)
9796{
9797 struct ufs_hba *hba = dev_get_drvdata(dev);
9798
9799 if (hba->complete_put) {
9800 ufshcd_rpm_put(hba);
9801 hba->complete_put = false;
9802 }
b294ff3e
AD		 9803}
9804EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9805
ddba1cf7
AH		 9806static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
9807{
9808 struct device *dev = &hba->sdev_ufs_device->sdev_gendev;
9809 enum ufs_dev_pwr_mode dev_pwr_mode;
9810 enum uic_link_state link_state;
9811 unsigned long flags;
9812 bool res;
9813
9814 spin_lock_irqsave(&dev->power.lock, flags);
9815 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
9816 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
9817 res = pm_runtime_suspended(dev) &&
9818 hba->curr_dev_pwr_mode == dev_pwr_mode &&
9819 hba->uic_link_state == link_state &&
9820 !hba->dev_info.b_rpm_dev_flush_capable;
9821 spin_unlock_irqrestore(&dev->power.lock, flags);
9822
9823 return res;
9824}
9825
9826int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
b294ff3e
AD		 9827{
9828 struct ufs_hba *hba = dev_get_drvdata(dev);
9829 int ret;
9830
9831 /*
9832 * SCSI assumes that runtime-pm and system-pm for scsi drivers
9833 * are same. And it doesn't wake up the device for system-suspend
9834 * if it's runtime suspended. But ufs doesn't follow that.
9835 * Refer ufshcd_resume_complete()
9836 */
9837 if (hba->sdev_ufs_device) {
ddba1cf7
AH		 9838 /* Prevent runtime suspend */
9839 ufshcd_rpm_get_noresume(hba);
9840 /*
9841 * Check if already runtime suspended in same state as system
9842 * suspend would be.
9843 */
9844 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
9845 /* RPM state is not ok for SPM, so runtime resume */
9846 ret = ufshcd_rpm_resume(hba);
9847 if (ret < 0 && ret != -EACCES) {
9848 ufshcd_rpm_put(hba);
9849 return ret;
9850 }
b294ff3e
AD		 9851 }
9852 hba->complete_put = true;
9853 }
b294ff3e
AD		 9854 return 0;
9855}
ddba1cf7
AH		 9856EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
9857
9858int ufshcd_suspend_prepare(struct device *dev)
9859{
9860 return __ufshcd_suspend_prepare(dev, true);
9861}
b294ff3e
AD		 9862EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9863
9864#ifdef CONFIG_PM_SLEEP
9865static int ufshcd_wl_poweroff(struct device *dev)
9866{
9867 struct scsi_device *sdev = to_scsi_device(dev);
9868 struct ufs_hba *hba = shost_priv(sdev->host);
9869
9870 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9871 return 0;
9872}
9873#endif
9874
9875static int ufshcd_wl_probe(struct device *dev)
9876{
9877 struct scsi_device *sdev = to_scsi_device(dev);
9878
9879 if (!is_device_wlun(sdev))
9880 return -ENODEV;
9881
9882 blk_pm_runtime_init(sdev->request_queue, dev);
9883 pm_runtime_set_autosuspend_delay(dev, 0);
9884 pm_runtime_allow(dev);
9885
9886 return 0;
9887}
9888
9889static int ufshcd_wl_remove(struct device *dev)
9890{
9891 pm_runtime_forbid(dev);
9892 return 0;
9893}
9894
9895static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9896#ifdef CONFIG_PM_SLEEP
9897 .suspend = ufshcd_wl_suspend,
9898 .resume = ufshcd_wl_resume,
9899 .freeze = ufshcd_wl_suspend,
9900 .thaw = ufshcd_wl_resume,
9901 .poweroff = ufshcd_wl_poweroff,
9902 .restore = ufshcd_wl_resume,
9903#endif
9904 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9905};
9906
9907/*
9908 * ufs_dev_wlun_template - describes ufs device wlun
9909 * ufs-device wlun - used to send pm commands
9910 * All luns are consumers of ufs-device wlun.
9911 *
9912 * Currently, no sd driver is present for wluns.
9913 * Hence the no specific pm operations are performed.
9914 * With ufs design, SSU should be sent to ufs-device wlun.
9915 * Hence register a scsi driver for ufs wluns only.
9916 */
9917static struct scsi_driver ufs_dev_wlun_template = {
9918 .gendrv = {
9919 .name = "ufs_device_wlun",
9920 .owner = THIS_MODULE,
9921 .probe = ufshcd_wl_probe,
9922 .remove = ufshcd_wl_remove,
9923 .pm = &ufshcd_wl_pm_ops,
9924 .shutdown = ufshcd_wl_shutdown,
9925 },
9926};
9927
b6cacaf2
AH		 9928static int __init ufshcd_core_init(void)
9929{
b294ff3e
AD		 9930 int ret;
9931
9a868c8a
BVA		 9932 /* Verify that there are no gaps in struct utp_transfer_cmd_desc. */
9933 static_assert(sizeof(struct utp_transfer_cmd_desc) ==
9934 2 * ALIGNED_UPIU_SIZE +
9935 SG_ALL * sizeof(struct ufshcd_sg_entry));
9936
b6cacaf2 9937 ufs_debugfs_init();
b294ff3e
AD		 9938
9939 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9940 if (ret)
edc0596c 9941 ufs_debugfs_exit();
b294ff3e 9942 return ret;
b6cacaf2
AH		 9943}
9944
9945static void __exit ufshcd_core_exit(void)
9946{
9947 ufs_debugfs_exit();
b294ff3e 9948 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
b6cacaf2
AH		 9949}
9950
9951module_init(ufshcd_core_init);
9952module_exit(ufshcd_core_exit);
9953
3b1d0580
VH		 9954MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9955MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 9956MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 9957MODULE_LICENSE("GPL");
9958MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)