scsi: ufs: sysfs: reworking of the rpm_lvl and spm_lvl entries
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT
35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY
38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
cbb6813e 47#include "ufs-sysfs.h"
7a3e97b0 48
7ff5ab47 49#define CREATE_TRACE_POINTS
50#include <trace/events/ufs.h>
51
dcea0bfb
GB
52#define UFSHCD_REQ_SENSE_SIZE 18
53
2fbd009b
SJ
54#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
55 UTP_TASK_REQ_COMPL |\
56 UFSHCD_ERROR_MASK)
6ccf44fe
SJ
57/* UIC command timeout, unit: ms */
58#define UIC_CMD_TIMEOUT 500
2fbd009b 59
5a0b0cb9
SRT
60/* NOP OUT retries waiting for NOP IN response */
61#define NOP_OUT_RETRIES 10
62/* Timeout after 30 msecs if NOP OUT hangs without response */
63#define NOP_OUT_TIMEOUT 30 /* msecs */
64
68078d5c 65/* Query request retries */
10fe5888 66#define QUERY_REQ_RETRIES 3
68078d5c 67/* Query request timeout */
10fe5888 68#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 69
e2933132
SRT
70/* Task management command timeout */
71#define TM_CMD_TIMEOUT 100 /* msecs */
72
64238fbd
YG
73/* maximum number of retries for a general UIC command */
74#define UFS_UIC_COMMAND_RETRIES 3
75
1d337ec2
SRT
76/* maximum number of link-startup retries */
77#define DME_LINKSTARTUP_RETRIES 3
78
87d0b4a6
YG
79/* Maximum retries for Hibern8 enter */
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
1d337ec2
SRT
82/* maximum number of reset retries before giving up */
83#define MAX_HOST_RESET_RETRIES 5
84
68078d5c
DR
85/* Expose the flag value from utp_upiu_query.value */
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
7d568652
SJ
88/* Interrupt aggregation default timeout, unit: 40us */
89#define INT_AGGR_DEF_TO 0x02
90
aa497613
SRT
91#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
92 ({ \
93 int _ret; \
94 if (_on) \
95 _ret = ufshcd_enable_vreg(_dev, _vreg); \
96 else \
97 _ret = ufshcd_disable_vreg(_dev, _vreg); \
98 _ret; \
99 })
100
66cc820f
DR
101#define ufshcd_hex_dump(prefix_str, buf, len) \
102print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
103
7a3e97b0
SY
104enum {
105 UFSHCD_MAX_CHANNEL = 0,
106 UFSHCD_MAX_ID = 1,
7a3e97b0
SY
107 UFSHCD_CMD_PER_LUN = 32,
108 UFSHCD_CAN_QUEUE = 32,
109};
110
111/* UFSHCD states */
112enum {
7a3e97b0
SY
113 UFSHCD_STATE_RESET,
114 UFSHCD_STATE_ERROR,
3441da7d 115 UFSHCD_STATE_OPERATIONAL,
141f8165 116 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT
117};
118
119/* UFSHCD error handling flags */
120enum {
121 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY
122};
123
e8e7f271
SRT
124/* UFSHCD UIC layer error flags */
125enum {
126 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG
127 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
128 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
129 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
130 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
131 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT
132};
133
3441da7d 134#define ufshcd_set_eh_in_progress(h) \
9c490d2d 135 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 136#define ufshcd_eh_in_progress(h) \
9c490d2d 137 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 138#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 139 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 140
57d104c1
SJ
141#define ufshcd_set_ufs_dev_active(h) \
142 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
143#define ufshcd_set_ufs_dev_sleep(h) \
144 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
145#define ufshcd_set_ufs_dev_poweroff(h) \
146 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
147#define ufshcd_is_ufs_dev_active(h) \
148 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
149#define ufshcd_is_ufs_dev_sleep(h) \
150 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
151#define ufshcd_is_ufs_dev_poweroff(h) \
152 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
153
cbb6813e 154struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ
155 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
156 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
157 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
158 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
159 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
161};
162
163static inline enum ufs_dev_pwr_mode
164ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
165{
166 return ufs_pm_lvl_states[lvl].dev_state;
167}
168
169static inline enum uic_link_state
170ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].link_state;
173}
174
0c8f7586 175static inline enum ufs_pm_level
176ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
177 enum uic_link_state link_state)
178{
179 enum ufs_pm_level lvl;
180
181 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
182 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
183 (ufs_pm_lvl_states[lvl].link_state == link_state))
184 return lvl;
185 }
186
187 /* if no match found, return the level 0 */
188 return UFS_PM_LVL_0;
189}
190
56d4a186
SJ
191static struct ufs_dev_fix ufs_fixups[] = {
192 /* UFS cards deviations table */
193 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
194 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
195 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
196 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
197 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
198 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
199 UFS_DEVICE_NO_FASTAUTO),
200 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
201 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
202 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
203 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
204 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
205 UFS_DEVICE_QUIRK_PA_TACTIVATE),
206 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
207 UFS_DEVICE_QUIRK_PA_TACTIVATE),
208 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
209 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
210 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
211
212 END_FIX
213};
214
3441da7d
SRT
215static void ufshcd_tmc_handler(struct ufs_hba *hba);
216static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 217static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 218static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 219static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT
220static void ufshcd_hba_exit(struct ufs_hba *hba);
221static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST
222static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
223 bool skip_ref_clk);
224static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 225static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST
226static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
227static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 228static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 229static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST
230static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
231static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 232static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 233static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 234static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR
235static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
236 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG
237static int ufshcd_change_power_mode(struct ufs_hba *hba,
238 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG
239static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
240{
241 return tag >= 0 && tag < hba->nutrs;
242}
57d104c1
SJ
243
244static inline int ufshcd_enable_irq(struct ufs_hba *hba)
245{
246 int ret = 0;
247
248 if (!hba->is_irq_enabled) {
249 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
250 hba);
251 if (ret)
252 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
253 __func__, ret);
254 hba->is_irq_enabled = true;
255 }
256
257 return ret;
258}
259
260static inline void ufshcd_disable_irq(struct ufs_hba *hba)
261{
262 if (hba->is_irq_enabled) {
263 free_irq(hba->irq, hba);
264 hba->is_irq_enabled = false;
265 }
266}
3441da7d 267
b573d484
YG
268/* replace non-printable or non-ASCII characters with spaces */
269static inline void ufshcd_remove_non_printable(char *val)
270{
271 if (!val)
272 return;
273
274 if (*val < 0x20 || *val > 0x7e)
275 *val = ' ';
276}
277
1a07f2d9
LS
278static void ufshcd_add_command_trace(struct ufs_hba *hba,
279 unsigned int tag, const char *str)
280{
281 sector_t lba = -1;
282 u8 opcode = 0;
283 u32 intr, doorbell;
284 struct ufshcd_lrb *lrbp;
285 int transfer_len = -1;
286
287 if (!trace_ufshcd_command_enabled())
288 return;
289
290 lrbp = &hba->lrb[tag];
291
292 if (lrbp->cmd) { /* data phase exists */
293 opcode = (u8)(*lrbp->cmd->cmnd);
294 if ((opcode == READ_10) || (opcode == WRITE_10)) {
295 /*
296 * Currently we only fully trace read(10) and write(10)
297 * commands
298 */
299 if (lrbp->cmd->request && lrbp->cmd->request->bio)
300 lba =
301 lrbp->cmd->request->bio->bi_iter.bi_sector;
302 transfer_len = be32_to_cpu(
303 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
304 }
305 }
306
307 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
308 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
309 trace_ufshcd_command(dev_name(hba->dev), str, tag,
310 doorbell, transfer_len, intr, lba, opcode);
311}
312
ff8e20c6
DR
313static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
314{
315 struct ufs_clk_info *clki;
316 struct list_head *head = &hba->clk_list_head;
317
566ec9ad 318 if (list_empty(head))
ff8e20c6
DR
319 return;
320
321 list_for_each_entry(clki, head, list) {
322 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
323 clki->max_freq)
324 dev_err(hba->dev, "clk: %s, rate: %u\n",
325 clki->name, clki->curr_freq);
326 }
327}
328
329static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
330 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
331{
332 int i;
333
334 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
335 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
336
337 if (err_hist->reg[p] == 0)
338 continue;
339 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
340 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
341 }
342}
343
66cc820f
DR
344static void ufshcd_print_host_regs(struct ufs_hba *hba)
345{
346 /*
347 * hex_dump reads its data without the readl macro. This might
348 * cause inconsistency issues on some platform, as the printed
349 * values may be from cache and not the most recent value.
350 * To know whether you are looking at an un-cached version verify
351 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
352 * during platform/pci probe function.
353 */
354 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
355 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
356 hba->ufs_version, hba->capabilities);
357 dev_err(hba->dev,
358 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
359 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR
360 dev_err(hba->dev,
361 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
362 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
363 hba->ufs_stats.hibern8_exit_cnt);
364
365 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
366 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
367 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
368 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
369 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
370
371 ufshcd_print_clk_freqs(hba);
372
373 if (hba->vops && hba->vops->dbg_register_dump)
374 hba->vops->dbg_register_dump(hba);
66cc820f
DR
375}
376
377static
378void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
379{
380 struct ufshcd_lrb *lrbp;
7fabb77b 381 int prdt_length;
66cc820f
DR
382 int tag;
383
384 for_each_set_bit(tag, &bitmap, hba->nutrs) {
385 lrbp = &hba->lrb[tag];
386
ff8e20c6
DR
387 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
388 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL
389 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
390 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR
391 dev_err(hba->dev,
392 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
393 tag, (u64)lrbp->utrd_dma_addr);
394
66cc820f
DR
395 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
396 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR
397 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
398 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR
399 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
400 sizeof(struct utp_upiu_req));
ff8e20c6
DR
401 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
402 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR
403 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
404 sizeof(struct utp_upiu_rsp));
66cc820f 405
7fabb77b
GB
406 prdt_length = le16_to_cpu(
407 lrbp->utr_descriptor_ptr->prd_table_length);
408 dev_err(hba->dev,
409 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
410 tag, prdt_length,
411 (u64)lrbp->ucd_prdt_dma_addr);
412
413 if (pr_prdt)
66cc820f 414 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 415 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR
416 }
417}
418
419static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
420{
421 struct utp_task_req_desc *tmrdp;
422 int tag;
423
424 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
425 tmrdp = &hba->utmrdl_base_addr[tag];
426 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
427 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
428 sizeof(struct request_desc_header));
429 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
430 tag);
431 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
432 sizeof(struct utp_upiu_req));
433 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
434 tag);
435 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
436 sizeof(struct utp_task_req_desc));
437 }
438}
439
6ba65588
GB
440static void ufshcd_print_host_state(struct ufs_hba *hba)
441{
442 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
443 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 444 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB
445 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
446 hba->saved_err, hba->saved_uic_err);
447 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
448 hba->curr_dev_pwr_mode, hba->uic_link_state);
449 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
450 hba->pm_op_in_progress, hba->is_sys_suspended);
451 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
452 hba->auto_bkops_enabled, hba->host->host_self_blocked);
453 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
454 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
455 hba->eh_flags, hba->req_abort_count);
456 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
457 hba->capabilities, hba->caps);
458 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
459 hba->dev_quirks);
460}
461
ff8e20c6
DR
462/**
463 * ufshcd_print_pwr_info - print power params as saved in hba
464 * power info
465 * @hba: per-adapter instance
466 */
467static void ufshcd_print_pwr_info(struct ufs_hba *hba)
468{
469 static const char * const names[] = {
470 "INVALID MODE",
471 "FAST MODE",
472 "SLOW_MODE",
473 "INVALID MODE",
474 "FASTAUTO_MODE",
475 "SLOWAUTO_MODE",
476 "INVALID MODE",
477 };
478
479 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
480 __func__,
481 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
482 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
483 names[hba->pwr_info.pwr_rx],
484 names[hba->pwr_info.pwr_tx],
485 hba->pwr_info.hs_rate);
486}
487
5a0b0cb9
SRT
488/*
489 * ufshcd_wait_for_register - wait for register value to change
490 * @hba - per-adapter interface
491 * @reg - mmio register offset
492 * @mask - mask to apply to read register value
493 * @val - wait condition
494 * @interval_us - polling interval in microsecs
495 * @timeout_ms - timeout in millisecs
596585a2 496 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT
497 *
498 * Returns -ETIMEDOUT on error, zero on success
499 */
596585a2
YG
500int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
501 u32 val, unsigned long interval_us,
502 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT
503{
504 int err = 0;
505 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
506
507 /* ignore bits that we don't intend to wait on */
508 val = val & mask;
509
510 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG
511 if (can_sleep)
512 usleep_range(interval_us, interval_us + 50);
513 else
514 udelay(interval_us);
5a0b0cb9
SRT
515 if (time_after(jiffies, timeout)) {
516 if ((ufshcd_readl(hba, reg) & mask) != val)
517 err = -ETIMEDOUT;
518 break;
519 }
520 }
521
522 return err;
523}
524
2fbd009b
SJ
525/**
526 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 527 * @hba: Pointer to adapter instance
2fbd009b
SJ
528 *
529 * Returns interrupt bit mask per version
530 */
531static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
532{
c01848c6
YG
533 u32 intr_mask = 0;
534
535 switch (hba->ufs_version) {
536 case UFSHCI_VERSION_10:
537 intr_mask = INTERRUPT_MASK_ALL_VER_10;
538 break;
c01848c6
YG
539 case UFSHCI_VERSION_11:
540 case UFSHCI_VERSION_20:
541 intr_mask = INTERRUPT_MASK_ALL_VER_11;
542 break;
c01848c6
YG
543 case UFSHCI_VERSION_21:
544 default:
545 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 546 break;
c01848c6
YG
547 }
548
549 return intr_mask;
2fbd009b
SJ
550}
551
7a3e97b0
SY
552/**
553 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 554 * @hba: Pointer to adapter instance
7a3e97b0
SY
555 *
556 * Returns UFSHCI version supported by the controller
557 */
558static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
559{
0263bcd0
YG
560 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
561 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 562
b873a275 563 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY
564}
565
566/**
567 * ufshcd_is_device_present - Check if any device connected to
568 * the host controller
5c0c28a8 569 * @hba: pointer to adapter instance
7a3e97b0 570 *
c9e6010b 571 * Returns true if device present, false if no device detected
7a3e97b0 572 */
c9e6010b 573static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 574{
5c0c28a8 575 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 576 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY
577}
578
579/**
580 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 581 * @lrbp: pointer to local command reference block
7a3e97b0
SY
582 *
583 * This function is used to get the OCS field from UTRD
584 * Returns the OCS field in the UTRD
585 */
586static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
587{
e8c8e82a 588 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY
589}
590
591/**
592 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
593 * @task_req_descp: pointer to utp_task_req_desc structure
594 *
595 * This function is used to get the OCS field from UTMRD
596 * Returns the OCS field in the UTMRD
597 */
598static inline int
599ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
600{
e8c8e82a 601 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY
602}
603
604/**
605 * ufshcd_get_tm_free_slot - get a free slot for task management request
606 * @hba: per adapter instance
e2933132 607 * @free_slot: pointer to variable with available slot value
7a3e97b0 608 *
e2933132
SRT
609 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
610 * Returns 0 if free slot is not available, else return 1 with tag value
611 * in @free_slot.
7a3e97b0 612 */
e2933132 613static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 614{
e2933132
SRT
615 int tag;
616 bool ret = false;
617
618 if (!free_slot)
619 goto out;
620
621 do {
622 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
623 if (tag >= hba->nutmrs)
624 goto out;
625 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
626
627 *free_slot = tag;
628 ret = true;
629out:
630 return ret;
631}
632
633static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
634{
635 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY
636}
637
638/**
639 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
640 * @hba: per adapter instance
641 * @pos: position of the bit to be cleared
642 */
643static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
644{
b873a275 645 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY
646}
647
a48353f6
YG
648/**
649 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
650 * @hba: per adapter instance
651 * @tag: position of the bit to be cleared
652 */
653static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
654{
655 __clear_bit(tag, &hba->outstanding_reqs);
656}
657
7a3e97b0
SY
658/**
659 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
660 * @reg: Register value of host controller status
661 *
662 * Returns integer, 0 on Success and positive value if failed
663 */
664static inline int ufshcd_get_lists_status(u32 reg)
665{
6cf16115 666 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY
667}
668
669/**
670 * ufshcd_get_uic_cmd_result - Get the UIC command result
671 * @hba: Pointer to adapter instance
672 *
673 * This function gets the result of UIC command completion
674 * Returns 0 on success, non zero value on error
675 */
676static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
677{
b873a275 678 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY
679 MASK_UIC_COMMAND_RESULT;
680}
681
12b4fdb4
SJ
682/**
683 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
684 * @hba: Pointer to adapter instance
685 *
686 * This function gets UIC command argument3
687 * Returns 0 on success, non zero value on error
688 */
689static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
690{
691 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
692}
693
7a3e97b0 694/**
5a0b0cb9 695 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 696 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY
697 */
698static inline int
5a0b0cb9 699ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 700{
5a0b0cb9 701 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY
702}
703
704/**
705 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
706 * @ucd_rsp_ptr: pointer to response UPIU
707 *
708 * This function gets the response status and scsi_status from response UPIU
709 * Returns the response result code.
710 */
711static inline int
712ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
713{
714 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
715}
716
1c2623c5
SJ
717/*
718 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
719 * from response UPIU
720 * @ucd_rsp_ptr: pointer to response UPIU
721 *
722 * Return the data segment length.
723 */
724static inline unsigned int
725ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
726{
727 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
728 MASK_RSP_UPIU_DATA_SEG_LEN;
729}
730
66ec6d59
SRT
731/**
732 * ufshcd_is_exception_event - Check if the device raised an exception event
733 * @ucd_rsp_ptr: pointer to response UPIU
734 *
735 * The function checks if the device raised an exception event indicated in
736 * the Device Information field of response UPIU.
737 *
738 * Returns true if exception is raised, false otherwise.
739 */
740static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
741{
742 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
743 MASK_RSP_EXCEPTION_EVENT ? true : false;
744}
745
7a3e97b0 746/**
7d568652 747 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 748 * @hba: per adapter instance
7a3e97b0
SY
749 */
750static inline void
7d568652 751ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 752{
7d568652
SJ
753 ufshcd_writel(hba, INT_AGGR_ENABLE |
754 INT_AGGR_COUNTER_AND_TIMER_RESET,
755 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
756}
757
758/**
759 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
760 * @hba: per adapter instance
761 * @cnt: Interrupt aggregation counter threshold
762 * @tmout: Interrupt aggregation timeout value
763 */
764static inline void
765ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
766{
767 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
768 INT_AGGR_COUNTER_THLD_VAL(cnt) |
769 INT_AGGR_TIMEOUT_VAL(tmout),
770 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY
771}
772
b852190e
YG
773/**
774 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
775 * @hba: per adapter instance
776 */
777static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
778{
779 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
780}
781
7a3e97b0
SY
782/**
783 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
784 * When run-stop registers are set to 1, it indicates the
785 * host controller that it can process the requests
786 * @hba: per adapter instance
787 */
788static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
789{
b873a275
SJ
790 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
791 REG_UTP_TASK_REQ_LIST_RUN_STOP);
792 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
793 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY
794}
795
7a3e97b0
SY
796/**
797 * ufshcd_hba_start - Start controller initialization sequence
798 * @hba: per adapter instance
799 */
800static inline void ufshcd_hba_start(struct ufs_hba *hba)
801{
b873a275 802 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY
803}
804
805/**
806 * ufshcd_is_hba_active - Get controller state
807 * @hba: per adapter instance
808 *
c9e6010b 809 * Returns false if controller is active, true otherwise
7a3e97b0 810 */
c9e6010b 811static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 812{
4a8eec2b
TK
813 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
814 ? false : true;
7a3e97b0
SY
815}
816
37113106
YG
817u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
818{
819 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
820 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
821 (hba->ufs_version == UFSHCI_VERSION_11))
822 return UFS_UNIPRO_VER_1_41;
823 else
824 return UFS_UNIPRO_VER_1_6;
825}
826EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
827
828static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
829{
830 /*
831 * If both host and device support UniPro ver1.6 or later, PA layer
832 * parameters tuning happens during link startup itself.
833 *
834 * We can manually tune PA layer parameters if either host or device
835 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
836 * logic simple, we will only do manual tuning if local unipro version
837 * doesn't support ver1.6 or later.
838 */
839 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
840 return true;
841 else
842 return false;
843}
844
a3cd5ec5 845static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
846{
847 int ret = 0;
848 struct ufs_clk_info *clki;
849 struct list_head *head = &hba->clk_list_head;
850 ktime_t start = ktime_get();
851 bool clk_state_changed = false;
852
566ec9ad 853 if (list_empty(head))
a3cd5ec5 854 goto out;
855
856 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
857 if (ret)
858 return ret;
859
860 list_for_each_entry(clki, head, list) {
861 if (!IS_ERR_OR_NULL(clki->clk)) {
862 if (scale_up && clki->max_freq) {
863 if (clki->curr_freq == clki->max_freq)
864 continue;
865
866 clk_state_changed = true;
867 ret = clk_set_rate(clki->clk, clki->max_freq);
868 if (ret) {
869 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
870 __func__, clki->name,
871 clki->max_freq, ret);
872 break;
873 }
874 trace_ufshcd_clk_scaling(dev_name(hba->dev),
875 "scaled up", clki->name,
876 clki->curr_freq,
877 clki->max_freq);
878
879 clki->curr_freq = clki->max_freq;
880
881 } else if (!scale_up && clki->min_freq) {
882 if (clki->curr_freq == clki->min_freq)
883 continue;
884
885 clk_state_changed = true;
886 ret = clk_set_rate(clki->clk, clki->min_freq);
887 if (ret) {
888 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
889 __func__, clki->name,
890 clki->min_freq, ret);
891 break;
892 }
893 trace_ufshcd_clk_scaling(dev_name(hba->dev),
894 "scaled down", clki->name,
895 clki->curr_freq,
896 clki->min_freq);
897 clki->curr_freq = clki->min_freq;
898 }
899 }
900 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
901 clki->name, clk_get_rate(clki->clk));
902 }
903
904 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
905
906out:
907 if (clk_state_changed)
908 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
909 (scale_up ? "up" : "down"),
910 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
911 return ret;
912}
913
914/**
915 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
916 * @hba: per adapter instance
917 * @scale_up: True if scaling up and false if scaling down
918 *
919 * Returns true if scaling is required, false otherwise.
920 */
921static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
922 bool scale_up)
923{
924 struct ufs_clk_info *clki;
925 struct list_head *head = &hba->clk_list_head;
926
566ec9ad 927 if (list_empty(head))
a3cd5ec5 928 return false;
929
930 list_for_each_entry(clki, head, list) {
931 if (!IS_ERR_OR_NULL(clki->clk)) {
932 if (scale_up && clki->max_freq) {
933 if (clki->curr_freq == clki->max_freq)
934 continue;
935 return true;
936 } else if (!scale_up && clki->min_freq) {
937 if (clki->curr_freq == clki->min_freq)
938 continue;
939 return true;
940 }
941 }
942 }
943
944 return false;
945}
946
947static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
948 u64 wait_timeout_us)
949{
950 unsigned long flags;
951 int ret = 0;
952 u32 tm_doorbell;
953 u32 tr_doorbell;
954 bool timeout = false, do_last_check = false;
955 ktime_t start;
956
957 ufshcd_hold(hba, false);
958 spin_lock_irqsave(hba->host->host_lock, flags);
959 /*
960 * Wait for all the outstanding tasks/transfer requests.
961 * Verify by checking the doorbell registers are clear.
962 */
963 start = ktime_get();
964 do {
965 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
966 ret = -EBUSY;
967 goto out;
968 }
969
970 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
971 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
972 if (!tm_doorbell && !tr_doorbell) {
973 timeout = false;
974 break;
975 } else if (do_last_check) {
976 break;
977 }
978
979 spin_unlock_irqrestore(hba->host->host_lock, flags);
980 schedule();
981 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
982 wait_timeout_us) {
983 timeout = true;
984 /*
985 * We might have scheduled out for long time so make
986 * sure to check if doorbells are cleared by this time
987 * or not.
988 */
989 do_last_check = true;
990 }
991 spin_lock_irqsave(hba->host->host_lock, flags);
992 } while (tm_doorbell || tr_doorbell);
993
994 if (timeout) {
995 dev_err(hba->dev,
996 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
997 __func__, tm_doorbell, tr_doorbell);
998 ret = -EBUSY;
999 }
1000out:
1001 spin_unlock_irqrestore(hba->host->host_lock, flags);
1002 ufshcd_release(hba);
1003 return ret;
1004}
1005
1006/**
1007 * ufshcd_scale_gear - scale up/down UFS gear
1008 * @hba: per adapter instance
1009 * @scale_up: True for scaling up gear and false for scaling down
1010 *
1011 * Returns 0 for success,
1012 * Returns -EBUSY if scaling can't happen at this time
1013 * Returns non-zero for any other errors
1014 */
1015static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1016{
1017 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1018 int ret = 0;
1019 struct ufs_pa_layer_attr new_pwr_info;
1020
1021 if (scale_up) {
1022 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1023 sizeof(struct ufs_pa_layer_attr));
1024 } else {
1025 memcpy(&new_pwr_info, &hba->pwr_info,
1026 sizeof(struct ufs_pa_layer_attr));
1027
1028 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1029 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1030 /* save the current power mode */
1031 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1032 &hba->pwr_info,
1033 sizeof(struct ufs_pa_layer_attr));
1034
1035 /* scale down gear */
1036 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1037 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1038 }
1039 }
1040
1041 /* check if the power mode needs to be changed or not? */
1042 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1043
1044 if (ret)
1045 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1046 __func__, ret,
1047 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1048 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1049
1050 return ret;
1051}
1052
1053static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1054{
1055 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1056 int ret = 0;
1057 /*
1058 * make sure that there are no outstanding requests when
1059 * clock scaling is in progress
1060 */
1061 scsi_block_requests(hba->host);
1062 down_write(&hba->clk_scaling_lock);
1063 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1064 ret = -EBUSY;
1065 up_write(&hba->clk_scaling_lock);
1066 scsi_unblock_requests(hba->host);
1067 }
1068
1069 return ret;
1070}
1071
1072static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1073{
1074 up_write(&hba->clk_scaling_lock);
1075 scsi_unblock_requests(hba->host);
1076}
1077
1078/**
1079 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1080 * @hba: per adapter instance
1081 * @scale_up: True for scaling up and false for scalin down
1082 *
1083 * Returns 0 for success,
1084 * Returns -EBUSY if scaling can't happen at this time
1085 * Returns non-zero for any other errors
1086 */
1087static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1088{
1089 int ret = 0;
1090
401f1e44 1091 /* let's not get into low power until clock scaling is completed */
1092 ufshcd_hold(hba, false);
1093
a3cd5ec5 1094 ret = ufshcd_clock_scaling_prepare(hba);
1095 if (ret)
1096 return ret;
1097
1098 /* scale down the gear before scaling down clocks */
1099 if (!scale_up) {
1100 ret = ufshcd_scale_gear(hba, false);
1101 if (ret)
1102 goto out;
1103 }
1104
1105 ret = ufshcd_scale_clks(hba, scale_up);
1106 if (ret) {
1107 if (!scale_up)
1108 ufshcd_scale_gear(hba, true);
1109 goto out;
1110 }
1111
1112 /* scale up the gear after scaling up clocks */
1113 if (scale_up) {
1114 ret = ufshcd_scale_gear(hba, true);
1115 if (ret) {
1116 ufshcd_scale_clks(hba, false);
1117 goto out;
1118 }
1119 }
1120
1121 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1122
1123out:
1124 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1125 ufshcd_release(hba);
a3cd5ec5 1126 return ret;
1127}
1128
401f1e44 1129static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1130{
1131 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1132 clk_scaling.suspend_work);
1133 unsigned long irq_flags;
1134
1135 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1136 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1137 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1138 return;
1139 }
1140 hba->clk_scaling.is_suspended = true;
1141 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1142
1143 __ufshcd_suspend_clkscaling(hba);
1144}
1145
1146static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1147{
1148 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1149 clk_scaling.resume_work);
1150 unsigned long irq_flags;
1151
1152 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1153 if (!hba->clk_scaling.is_suspended) {
1154 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1155 return;
1156 }
1157 hba->clk_scaling.is_suspended = false;
1158 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1159
1160 devfreq_resume_device(hba->devfreq);
1161}
1162
a3cd5ec5 1163static int ufshcd_devfreq_target(struct device *dev,
1164 unsigned long *freq, u32 flags)
1165{
1166 int ret = 0;
1167 struct ufs_hba *hba = dev_get_drvdata(dev);
1168 ktime_t start;
401f1e44 1169 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5 1170 unsigned long irq_flags;
1171
1172 if (!ufshcd_is_clkscaling_supported(hba))
1173 return -EINVAL;
1174
1175 if ((*freq > 0) && (*freq < UINT_MAX)) {
1176 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1177 return -EINVAL;
1178 }
1179
a3cd5ec5 1180 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1181 if (ufshcd_eh_in_progress(hba)) {
1182 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1183 return 0;
1184 }
1185
401f1e44 1186 if (!hba->clk_scaling.active_reqs)
1187 sched_clk_scaling_suspend_work = true;
1188
1189 scale_up = (*freq == UINT_MAX) ? true : false;
1190 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1191 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1192 ret = 0;
1193 goto out; /* no state change required */
a3cd5ec5 1194 }
1195 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1196
1197 start = ktime_get();
a3cd5ec5 1198 ret = ufshcd_devfreq_scale(hba, scale_up);
1199
a3cd5ec5 1200 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1201 (scale_up ? "up" : "down"),
1202 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1203
401f1e44 1204out:
1205 if (sched_clk_scaling_suspend_work)
1206 queue_work(hba->clk_scaling.workq,
1207 &hba->clk_scaling.suspend_work);
1208
a3cd5ec5 1209 return ret;
1210}
1211
1212
1213static int ufshcd_devfreq_get_dev_status(struct device *dev,
1214 struct devfreq_dev_status *stat)
1215{
1216 struct ufs_hba *hba = dev_get_drvdata(dev);
1217 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1218 unsigned long flags;
1219
1220 if (!ufshcd_is_clkscaling_supported(hba))
1221 return -EINVAL;
1222
1223 memset(stat, 0, sizeof(*stat));
1224
1225 spin_lock_irqsave(hba->host->host_lock, flags);
1226 if (!scaling->window_start_t)
1227 goto start_window;
1228
1229 if (scaling->is_busy_started)
1230 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1231 scaling->busy_start_t));
1232
1233 stat->total_time = jiffies_to_usecs((long)jiffies -
1234 (long)scaling->window_start_t);
1235 stat->busy_time = scaling->tot_busy_t;
1236start_window:
1237 scaling->window_start_t = jiffies;
1238 scaling->tot_busy_t = 0;
1239
1240 if (hba->outstanding_reqs) {
1241 scaling->busy_start_t = ktime_get();
1242 scaling->is_busy_started = true;
1243 } else {
1244 scaling->busy_start_t = 0;
1245 scaling->is_busy_started = false;
1246 }
1247 spin_unlock_irqrestore(hba->host->host_lock, flags);
1248 return 0;
1249}
1250
1251static struct devfreq_dev_profile ufs_devfreq_profile = {
1252 .polling_ms = 100,
1253 .target = ufshcd_devfreq_target,
1254 .get_dev_status = ufshcd_devfreq_get_dev_status,
1255};
1256
401f1e44 1257static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1258{
1259 unsigned long flags;
1260
1261 devfreq_suspend_device(hba->devfreq);
1262 spin_lock_irqsave(hba->host->host_lock, flags);
1263 hba->clk_scaling.window_start_t = 0;
1264 spin_unlock_irqrestore(hba->host->host_lock, flags);
1265}
a3cd5ec5 1266
a508253d
GB
1267static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1268{
401f1e44 1269 unsigned long flags;
1270 bool suspend = false;
1271
fcb0c4b0
ST
1272 if (!ufshcd_is_clkscaling_supported(hba))
1273 return;
1274
401f1e44 1275 spin_lock_irqsave(hba->host->host_lock, flags);
1276 if (!hba->clk_scaling.is_suspended) {
1277 suspend = true;
1278 hba->clk_scaling.is_suspended = true;
1279 }
1280 spin_unlock_irqrestore(hba->host->host_lock, flags);
1281
1282 if (suspend)
1283 __ufshcd_suspend_clkscaling(hba);
a508253d
GB
1284}
1285
1286static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1287{
401f1e44 1288 unsigned long flags;
1289 bool resume = false;
1290
1291 if (!ufshcd_is_clkscaling_supported(hba))
1292 return;
1293
1294 spin_lock_irqsave(hba->host->host_lock, flags);
1295 if (hba->clk_scaling.is_suspended) {
1296 resume = true;
1297 hba->clk_scaling.is_suspended = false;
1298 }
1299 spin_unlock_irqrestore(hba->host->host_lock, flags);
1300
1301 if (resume)
1302 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST
1303}
1304
1305static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1306 struct device_attribute *attr, char *buf)
1307{
1308 struct ufs_hba *hba = dev_get_drvdata(dev);
1309
1310 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1311}
1312
1313static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1314 struct device_attribute *attr, const char *buf, size_t count)
1315{
1316 struct ufs_hba *hba = dev_get_drvdata(dev);
1317 u32 value;
1318 int err;
1319
1320 if (kstrtou32(buf, 0, &value))
1321 return -EINVAL;
1322
1323 value = !!value;
1324 if (value == hba->clk_scaling.is_allowed)
1325 goto out;
1326
1327 pm_runtime_get_sync(hba->dev);
1328 ufshcd_hold(hba, false);
1329
401f1e44 1330 cancel_work_sync(&hba->clk_scaling.suspend_work);
1331 cancel_work_sync(&hba->clk_scaling.resume_work);
1332
1333 hba->clk_scaling.is_allowed = value;
1334
fcb0c4b0
ST
1335 if (value) {
1336 ufshcd_resume_clkscaling(hba);
1337 } else {
1338 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1339 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST
1340 if (err)
1341 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1342 __func__, err);
1343 }
fcb0c4b0
ST
1344
1345 ufshcd_release(hba);
1346 pm_runtime_put_sync(hba->dev);
1347out:
1348 return count;
a508253d
GB
1349}
1350
a3cd5ec5 1351static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1352{
1353 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1354 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1355 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1356 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1357 hba->clk_scaling.enable_attr.attr.mode = 0644;
1358 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1359 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1360}
1361
1ab27c9c
ST
1362static void ufshcd_ungate_work(struct work_struct *work)
1363{
1364 int ret;
1365 unsigned long flags;
1366 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1367 clk_gating.ungate_work);
1368
1369 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1370
1371 spin_lock_irqsave(hba->host->host_lock, flags);
1372 if (hba->clk_gating.state == CLKS_ON) {
1373 spin_unlock_irqrestore(hba->host->host_lock, flags);
1374 goto unblock_reqs;
1375 }
1376
1377 spin_unlock_irqrestore(hba->host->host_lock, flags);
1378 ufshcd_setup_clocks(hba, true);
1379
1380 /* Exit from hibern8 */
1381 if (ufshcd_can_hibern8_during_gating(hba)) {
1382 /* Prevent gating in this path */
1383 hba->clk_gating.is_suspended = true;
1384 if (ufshcd_is_link_hibern8(hba)) {
1385 ret = ufshcd_uic_hibern8_exit(hba);
1386 if (ret)
1387 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1388 __func__, ret);
1389 else
1390 ufshcd_set_link_active(hba);
1391 }
1392 hba->clk_gating.is_suspended = false;
1393 }
1394unblock_reqs:
1395 scsi_unblock_requests(hba->host);
1396}
1397
1398/**
1399 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1400 * Also, exit from hibern8 mode and set the link as active.
1401 * @hba: per adapter instance
1402 * @async: This indicates whether caller should ungate clocks asynchronously.
1403 */
1404int ufshcd_hold(struct ufs_hba *hba, bool async)
1405{
1406 int rc = 0;
1407 unsigned long flags;
1408
1409 if (!ufshcd_is_clkgating_allowed(hba))
1410 goto out;
1ab27c9c
ST
1411 spin_lock_irqsave(hba->host->host_lock, flags);
1412 hba->clk_gating.active_reqs++;
1413
53c12d0e
YG
1414 if (ufshcd_eh_in_progress(hba)) {
1415 spin_unlock_irqrestore(hba->host->host_lock, flags);
1416 return 0;
1417 }
1418
856b3483 1419start:
1ab27c9c
ST
1420 switch (hba->clk_gating.state) {
1421 case CLKS_ON:
f2a785ac
VG
1422 /*
1423 * Wait for the ungate work to complete if in progress.
1424 * Though the clocks may be in ON state, the link could
1425 * still be in hibner8 state if hibern8 is allowed
1426 * during clock gating.
1427 * Make sure we exit hibern8 state also in addition to
1428 * clocks being ON.
1429 */
1430 if (ufshcd_can_hibern8_during_gating(hba) &&
1431 ufshcd_is_link_hibern8(hba)) {
1432 spin_unlock_irqrestore(hba->host->host_lock, flags);
1433 flush_work(&hba->clk_gating.ungate_work);
1434 spin_lock_irqsave(hba->host->host_lock, flags);
1435 goto start;
1436 }
1ab27c9c
ST
1437 break;
1438 case REQ_CLKS_OFF:
1439 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1440 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1441 trace_ufshcd_clk_gating(dev_name(hba->dev),
1442 hba->clk_gating.state);
1ab27c9c
ST
1443 break;
1444 }
1445 /*
9c490d2d 1446 * If we are here, it means gating work is either done or
1ab27c9c
ST
1447 * currently running. Hence, fall through to cancel gating
1448 * work and to enable clocks.
1449 */
1450 case CLKS_OFF:
1451 scsi_block_requests(hba->host);
1452 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1453 trace_ufshcd_clk_gating(dev_name(hba->dev),
1454 hba->clk_gating.state);
1ab27c9c
ST
1455 schedule_work(&hba->clk_gating.ungate_work);
1456 /*
1457 * fall through to check if we should wait for this
1458 * work to be done or not.
1459 */
1460 case REQ_CLKS_ON:
1461 if (async) {
1462 rc = -EAGAIN;
1463 hba->clk_gating.active_reqs--;
1464 break;
1465 }
1466
1467 spin_unlock_irqrestore(hba->host->host_lock, flags);
1468 flush_work(&hba->clk_gating.ungate_work);
1469 /* Make sure state is CLKS_ON before returning */
856b3483 1470 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST
1471 goto start;
1472 default:
1473 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1474 __func__, hba->clk_gating.state);
1475 break;
1476 }
1477 spin_unlock_irqrestore(hba->host->host_lock, flags);
1478out:
1479 return rc;
1480}
6e3fd44d 1481EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST
1482
1483static void ufshcd_gate_work(struct work_struct *work)
1484{
1485 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1486 clk_gating.gate_work.work);
1487 unsigned long flags;
1488
1489 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG
1490 /*
1491 * In case you are here to cancel this work the gating state
1492 * would be marked as REQ_CLKS_ON. In this case save time by
1493 * skipping the gating work and exit after changing the clock
1494 * state to CLKS_ON.
1495 */
1496 if (hba->clk_gating.is_suspended ||
1497 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1498 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1499 trace_ufshcd_clk_gating(dev_name(hba->dev),
1500 hba->clk_gating.state);
1ab27c9c
ST
1501 goto rel_lock;
1502 }
1503
1504 if (hba->clk_gating.active_reqs
1505 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1506 || hba->lrb_in_use || hba->outstanding_tasks
1507 || hba->active_uic_cmd || hba->uic_async_done)
1508 goto rel_lock;
1509
1510 spin_unlock_irqrestore(hba->host->host_lock, flags);
1511
1512 /* put the link into hibern8 mode before turning off clocks */
1513 if (ufshcd_can_hibern8_during_gating(hba)) {
1514 if (ufshcd_uic_hibern8_enter(hba)) {
1515 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1516 trace_ufshcd_clk_gating(dev_name(hba->dev),
1517 hba->clk_gating.state);
1ab27c9c
ST
1518 goto out;
1519 }
1520 ufshcd_set_link_hibern8(hba);
1521 }
1522
1523 if (!ufshcd_is_link_active(hba))
1524 ufshcd_setup_clocks(hba, false);
1525 else
1526 /* If link is active, device ref_clk can't be switched off */
1527 __ufshcd_setup_clocks(hba, false, true);
1528
1529 /*
1530 * In case you are here to cancel this work the gating state
1531 * would be marked as REQ_CLKS_ON. In this case keep the state
1532 * as REQ_CLKS_ON which would anyway imply that clocks are off
1533 * and a request to turn them on is pending. By doing this way,
1534 * we keep the state machine in tact and this would ultimately
1535 * prevent from doing cancel work multiple times when there are
1536 * new requests arriving before the current cancel work is done.
1537 */
1538 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1539 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1540 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1541 trace_ufshcd_clk_gating(dev_name(hba->dev),
1542 hba->clk_gating.state);
1543 }
1ab27c9c
ST
1544rel_lock:
1545 spin_unlock_irqrestore(hba->host->host_lock, flags);
1546out:
1547 return;
1548}
1549
1550/* host lock must be held before calling this variant */
1551static void __ufshcd_release(struct ufs_hba *hba)
1552{
1553 if (!ufshcd_is_clkgating_allowed(hba))
1554 return;
1555
1556 hba->clk_gating.active_reqs--;
1557
1558 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1559 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1560 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG
1561 || hba->active_uic_cmd || hba->uic_async_done
1562 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST
1563 return;
1564
1565 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1566 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST
1567 schedule_delayed_work(&hba->clk_gating.gate_work,
1568 msecs_to_jiffies(hba->clk_gating.delay_ms));
1569}
1570
1571void ufshcd_release(struct ufs_hba *hba)
1572{
1573 unsigned long flags;
1574
1575 spin_lock_irqsave(hba->host->host_lock, flags);
1576 __ufshcd_release(hba);
1577 spin_unlock_irqrestore(hba->host->host_lock, flags);
1578}
6e3fd44d 1579EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST
1580
1581static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1582 struct device_attribute *attr, char *buf)
1583{
1584 struct ufs_hba *hba = dev_get_drvdata(dev);
1585
1586 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1587}
1588
1589static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1590 struct device_attribute *attr, const char *buf, size_t count)
1591{
1592 struct ufs_hba *hba = dev_get_drvdata(dev);
1593 unsigned long flags, value;
1594
1595 if (kstrtoul(buf, 0, &value))
1596 return -EINVAL;
1597
1598 spin_lock_irqsave(hba->host->host_lock, flags);
1599 hba->clk_gating.delay_ms = value;
1600 spin_unlock_irqrestore(hba->host->host_lock, flags);
1601 return count;
1602}
1603
b427411a
ST
1604static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1605 struct device_attribute *attr, char *buf)
1606{
1607 struct ufs_hba *hba = dev_get_drvdata(dev);
1608
1609 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1610}
1611
1612static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1613 struct device_attribute *attr, const char *buf, size_t count)
1614{
1615 struct ufs_hba *hba = dev_get_drvdata(dev);
1616 unsigned long flags;
1617 u32 value;
1618
1619 if (kstrtou32(buf, 0, &value))
1620 return -EINVAL;
1621
1622 value = !!value;
1623 if (value == hba->clk_gating.is_enabled)
1624 goto out;
1625
1626 if (value) {
1627 ufshcd_release(hba);
1628 } else {
1629 spin_lock_irqsave(hba->host->host_lock, flags);
1630 hba->clk_gating.active_reqs++;
1631 spin_unlock_irqrestore(hba->host->host_lock, flags);
1632 }
1633
1634 hba->clk_gating.is_enabled = value;
1635out:
1636 return count;
1637}
1638
1ab27c9c
ST
1639static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1640{
1641 if (!ufshcd_is_clkgating_allowed(hba))
1642 return;
1643
1644 hba->clk_gating.delay_ms = 150;
1645 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1646 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1647
b427411a
ST
1648 hba->clk_gating.is_enabled = true;
1649
1ab27c9c
ST
1650 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1651 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1652 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1653 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1654 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST
1655 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1656 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST
1657
1658 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1659 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1660 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1661 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1662 hba->clk_gating.enable_attr.attr.mode = 0644;
1663 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1664 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST
1665}
1666
1667static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1668{
1669 if (!ufshcd_is_clkgating_allowed(hba))
1670 return;
1671 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1672 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM
1673 cancel_work_sync(&hba->clk_gating.ungate_work);
1674 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST
1675}
1676
856b3483
ST
1677/* Must be called with host lock acquired */
1678static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1679{
401f1e44 1680 bool queue_resume_work = false;
1681
fcb0c4b0 1682 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST
1683 return;
1684
401f1e44 1685 if (!hba->clk_scaling.active_reqs++)
1686 queue_resume_work = true;
1687
1688 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1689 return;
1690
1691 if (queue_resume_work)
1692 queue_work(hba->clk_scaling.workq,
1693 &hba->clk_scaling.resume_work);
1694
1695 if (!hba->clk_scaling.window_start_t) {
1696 hba->clk_scaling.window_start_t = jiffies;
1697 hba->clk_scaling.tot_busy_t = 0;
1698 hba->clk_scaling.is_busy_started = false;
1699 }
1700
856b3483
ST
1701 if (!hba->clk_scaling.is_busy_started) {
1702 hba->clk_scaling.busy_start_t = ktime_get();
1703 hba->clk_scaling.is_busy_started = true;
1704 }
1705}
1706
1707static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1708{
1709 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1710
fcb0c4b0 1711 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST
1712 return;
1713
1714 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1715 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1716 scaling->busy_start_t));
8b0e1953 1717 scaling->busy_start_t = 0;
856b3483
ST
1718 scaling->is_busy_started = false;
1719 }
1720}
7a3e97b0
SY
1721/**
1722 * ufshcd_send_command - Send SCSI or device management commands
1723 * @hba: per adapter instance
1724 * @task_tag: Task tag of the command
1725 */
1726static inline
1727void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1728{
ff8e20c6 1729 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1730 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
856b3483 1731 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1732 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1733 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB
1734 /* Make sure that doorbell is committed immediately */
1735 wmb();
1a07f2d9 1736 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY
1737}
1738
1739/**
1740 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1741 * @lrbp: pointer to local reference block
7a3e97b0
SY
1742 */
1743static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1744{
1745 int len;
1c2623c5
SJ
1746 if (lrbp->sense_buffer &&
1747 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG
1748 int len_to_copy;
1749
5a0b0cb9 1750 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG
1751 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1752
7a3e97b0 1753 memcpy(lrbp->sense_buffer,
5a0b0cb9 1754 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1755 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY
1756 }
1757}
1758
68078d5c
DR
1759/**
1760 * ufshcd_copy_query_response() - Copy the Query Response and the data
1761 * descriptor
1762 * @hba: per adapter instance
8aa29f19 1763 * @lrbp: pointer to local reference block
68078d5c
DR
1764 */
1765static
c6d4a831 1766int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR
1767{
1768 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1769
68078d5c 1770 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1771
68078d5c
DR
1772 /* Get the descriptor */
1773 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1774 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1775 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR
1776 u16 resp_len;
1777 u16 buf_len;
68078d5c
DR
1778
1779 /* data segment length */
c6d4a831 1780 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1781 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT
1782 buf_len = be16_to_cpu(
1783 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR
1784 if (likely(buf_len >= resp_len)) {
1785 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1786 } else {
1787 dev_warn(hba->dev,
1788 "%s: Response size is bigger than buffer",
1789 __func__);
1790 return -EINVAL;
1791 }
68078d5c 1792 }
c6d4a831
DR
1793
1794 return 0;
68078d5c
DR
1795}
1796
7a3e97b0
SY
1797/**
1798 * ufshcd_hba_capabilities - Read controller capabilities
1799 * @hba: per adapter instance
1800 */
1801static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1802{
b873a275 1803 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY
1804
1805 /* nutrs and nutmrs are 0 based values */
1806 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1807 hba->nutmrs =
1808 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1809}
1810
1811/**
6ccf44fe
SJ
1812 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1813 * to accept UIC commands
7a3e97b0 1814 * @hba: per adapter instance
6ccf44fe
SJ
1815 * Return true on success, else false
1816 */
1817static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1818{
1819 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1820 return true;
1821 else
1822 return false;
1823}
1824
53b3d9c3
SJ
1825/**
1826 * ufshcd_get_upmcrs - Get the power mode change request status
1827 * @hba: Pointer to adapter instance
1828 *
1829 * This function gets the UPMCRS field of HCS register
1830 * Returns value of UPMCRS field
1831 */
1832static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1833{
1834 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1835}
1836
6ccf44fe
SJ
1837/**
1838 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1839 * @hba: per adapter instance
1840 * @uic_cmd: UIC command
1841 *
1842 * Mutex must be held.
7a3e97b0
SY
1843 */
1844static inline void
6ccf44fe 1845ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1846{
6ccf44fe
SJ
1847 WARN_ON(hba->active_uic_cmd);
1848
1849 hba->active_uic_cmd = uic_cmd;
1850
7a3e97b0 1851 /* Write Args */
6ccf44fe
SJ
1852 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1853 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1854 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY
1855
1856 /* Write UIC Cmd */
6ccf44fe 1857 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1858 REG_UIC_COMMAND);
7a3e97b0
SY
1859}
1860
6ccf44fe
SJ
1861/**
1862 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1863 * @hba: per adapter instance
8aa29f19 1864 * @uic_cmd: UIC command
6ccf44fe
SJ
1865 *
1866 * Must be called with mutex held.
1867 * Returns 0 only if success.
1868 */
1869static int
1870ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1871{
1872 int ret;
1873 unsigned long flags;
1874
1875 if (wait_for_completion_timeout(&uic_cmd->done,
1876 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1877 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1878 else
1879 ret = -ETIMEDOUT;
1880
1881 spin_lock_irqsave(hba->host->host_lock, flags);
1882 hba->active_uic_cmd = NULL;
1883 spin_unlock_irqrestore(hba->host->host_lock, flags);
1884
1885 return ret;
1886}
1887
1888/**
1889 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1890 * @hba: per adapter instance
1891 * @uic_cmd: UIC command
d75f7fe4 1892 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ
1893 *
1894 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1895 * with mutex held and host_lock locked.
6ccf44fe
SJ
1896 * Returns 0 only if success.
1897 */
1898static int
d75f7fe4
YG
1899__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1900 bool completion)
6ccf44fe 1901{
6ccf44fe
SJ
1902 if (!ufshcd_ready_for_uic_cmd(hba)) {
1903 dev_err(hba->dev,
1904 "Controller not ready to accept UIC commands\n");
1905 return -EIO;
1906 }
1907
d75f7fe4
YG
1908 if (completion)
1909 init_completion(&uic_cmd->done);
6ccf44fe 1910
6ccf44fe 1911 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1912
57d104c1 1913 return 0;
6ccf44fe
SJ
1914}
1915
1916/**
1917 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1918 * @hba: per adapter instance
1919 * @uic_cmd: UIC command
1920 *
1921 * Returns 0 only if success.
1922 */
1923static int
1924ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1925{
1926 int ret;
57d104c1 1927 unsigned long flags;
6ccf44fe 1928
1ab27c9c 1929 ufshcd_hold(hba, false);
6ccf44fe 1930 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG
1931 ufshcd_add_delay_before_dme_cmd(hba);
1932
57d104c1 1933 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1934 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ
1935 spin_unlock_irqrestore(hba->host->host_lock, flags);
1936 if (!ret)
1937 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1938
6ccf44fe
SJ
1939 mutex_unlock(&hba->uic_cmd_mutex);
1940
1ab27c9c 1941 ufshcd_release(hba);
6ccf44fe
SJ
1942 return ret;
1943}
1944
7a3e97b0
SY
1945/**
1946 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA
1947 * @hba: per adapter instance
1948 * @lrbp: pointer to local reference block
7a3e97b0
SY
1949 *
1950 * Returns 0 in case of success, non-zero value in case of failure
1951 */
75b1cc4a 1952static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY
1953{
1954 struct ufshcd_sg_entry *prd_table;
1955 struct scatterlist *sg;
1956 struct scsi_cmnd *cmd;
1957 int sg_segments;
1958 int i;
1959
1960 cmd = lrbp->cmd;
1961 sg_segments = scsi_dma_map(cmd);
1962 if (sg_segments < 0)
1963 return sg_segments;
1964
1965 if (sg_segments) {
75b1cc4a
KK
1966 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1967 lrbp->utr_descriptor_ptr->prd_table_length =
1968 cpu_to_le16((u16)(sg_segments *
1969 sizeof(struct ufshcd_sg_entry)));
1970 else
1971 lrbp->utr_descriptor_ptr->prd_table_length =
1972 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY
1973
1974 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1975
1976 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1977 prd_table[i].size =
1978 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1979 prd_table[i].base_addr =
1980 cpu_to_le32(lower_32_bits(sg->dma_address));
1981 prd_table[i].upper_addr =
1982 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1983 prd_table[i].reserved = 0;
7a3e97b0
SY
1984 }
1985 } else {
1986 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1987 }
1988
1989 return 0;
1990}
1991
1992/**
2fbd009b 1993 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1994 * @hba: per adapter instance
2fbd009b 1995 * @intrs: interrupt bits
7a3e97b0 1996 */
2fbd009b 1997static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1998{
2fbd009b
SJ
1999 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2000
2001 if (hba->ufs_version == UFSHCI_VERSION_10) {
2002 u32 rw;
2003 rw = set & INTERRUPT_MASK_RW_VER_10;
2004 set = rw | ((set ^ intrs) & intrs);
2005 } else {
2006 set |= intrs;
2007 }
2008
2009 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2010}
2011
2012/**
2013 * ufshcd_disable_intr - disable interrupts
2014 * @hba: per adapter instance
2015 * @intrs: interrupt bits
2016 */
2017static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2018{
2019 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2020
2021 if (hba->ufs_version == UFSHCI_VERSION_10) {
2022 u32 rw;
2023 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2024 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2025 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2026
2027 } else {
2028 set &= ~intrs;
7a3e97b0 2029 }
2fbd009b
SJ
2030
2031 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY
2032}
2033
5a0b0cb9
SRT
2034/**
2035 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2036 * descriptor according to request
2037 * @lrbp: pointer to local reference block
2038 * @upiu_flags: flags required in the header
2039 * @cmd_dir: requests data direction
2040 */
2041static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2042 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT
2043{
2044 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2045 u32 data_direction;
2046 u32 dword_0;
2047
2048 if (cmd_dir == DMA_FROM_DEVICE) {
2049 data_direction = UTP_DEVICE_TO_HOST;
2050 *upiu_flags = UPIU_CMD_FLAGS_READ;
2051 } else if (cmd_dir == DMA_TO_DEVICE) {
2052 data_direction = UTP_HOST_TO_DEVICE;
2053 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2054 } else {
2055 data_direction = UTP_NO_DATA_TRANSFER;
2056 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2057 }
2058
2059 dword_0 = data_direction | (lrbp->command_type
2060 << UPIU_COMMAND_TYPE_OFFSET);
2061 if (lrbp->intr_cmd)
2062 dword_0 |= UTP_REQ_DESC_INT_CMD;
2063
2064 /* Transfer request descriptor header fields */
2065 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG
2066 /* dword_1 is reserved, hence it is set to 0 */
2067 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT
2068 /*
2069 * assigning invalid value for command status. Controller
2070 * updates OCS on command completion, with the command
2071 * status
2072 */
2073 req_desc->header.dword_2 =
2074 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG
2075 /* dword_3 is reserved, hence it is set to 0 */
2076 req_desc->header.dword_3 = 0;
51047266
YG
2077
2078 req_desc->prd_table_length = 0;
5a0b0cb9
SRT
2079}
2080
2081/**
2082 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2083 * for scsi commands
8aa29f19
BVA
2084 * @lrbp: local reference block pointer
2085 * @upiu_flags: flags
5a0b0cb9
SRT
2086 */
2087static
2088void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2089{
2090 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2091 unsigned short cdb_len;
5a0b0cb9
SRT
2092
2093 /* command descriptor fields */
2094 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2095 UPIU_TRANSACTION_COMMAND, upiu_flags,
2096 lrbp->lun, lrbp->task_tag);
2097 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2098 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2099
2100 /* Total EHS length and Data segment length will be zero */
2101 ucd_req_ptr->header.dword_2 = 0;
2102
2103 ucd_req_ptr->sc.exp_data_transfer_len =
2104 cpu_to_be32(lrbp->cmd->sdb.length);
2105
52ac95fe
YG
2106 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2107 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2108 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2109
2110 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT
2111}
2112
68078d5c
DR
2113/**
2114 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2115 * for query requsts
2116 * @hba: UFS hba
2117 * @lrbp: local reference block pointer
2118 * @upiu_flags: flags
2119 */
2120static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2121 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2122{
2123 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2124 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2125 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR
2126 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2127
2128 /* Query request header */
2129 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2130 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2131 lrbp->lun, lrbp->task_tag);
2132 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2133 0, query->request.query_func, 0, 0);
2134
6861285c
ZL
2135 /* Data segment length only need for WRITE_DESC */
2136 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2137 ucd_req_ptr->header.dword_2 =
2138 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2139 else
2140 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR
2141
2142 /* Copy the Query Request buffer as is */
2143 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2144 QUERY_OSF_SIZE);
68078d5c
DR
2145
2146 /* Copy the Descriptor */
c6d4a831
DR
2147 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2148 memcpy(descp, query->descriptor, len);
2149
51047266 2150 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR
2151}
2152
5a0b0cb9
SRT
2153static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2154{
2155 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2156
2157 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2158
2159 /* command descriptor fields */
2160 ucd_req_ptr->header.dword_0 =
2161 UPIU_HEADER_DWORD(
2162 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG
2163 /* clear rest of the fields of basic header */
2164 ucd_req_ptr->header.dword_1 = 0;
2165 ucd_req_ptr->header.dword_2 = 0;
2166
2167 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT
2168}
2169
7a3e97b0 2170/**
300bb13f
JP
2171 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2172 * for Device Management Purposes
8aa29f19
BVA
2173 * @hba: per adapter instance
2174 * @lrbp: pointer to local reference block
7a3e97b0 2175 */
300bb13f 2176static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2177{
7a3e97b0 2178 u32 upiu_flags;
5a0b0cb9 2179 int ret = 0;
7a3e97b0 2180
83dc7e3d 2181 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2182 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2183 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2184 else
2185 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP
2186
2187 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2188 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2189 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2190 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2191 ufshcd_prepare_utp_nop_upiu(lrbp);
2192 else
2193 ret = -EINVAL;
2194
2195 return ret;
2196}
2197
2198/**
2199 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2200 * for SCSI Purposes
8aa29f19
BVA
2201 * @hba: per adapter instance
2202 * @lrbp: pointer to local reference block
300bb13f
JP
2203 */
2204static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2205{
2206 u32 upiu_flags;
2207 int ret = 0;
2208
83dc7e3d 2209 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2210 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2211 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2212 else
2213 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP
2214
2215 if (likely(lrbp->cmd)) {
2216 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2217 lrbp->cmd->sc_data_direction);
2218 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2219 } else {
2220 ret = -EINVAL;
2221 }
5a0b0cb9
SRT
2222
2223 return ret;
7a3e97b0
SY
2224}
2225
2a8fa600
SJ
2226/**
2227 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2228 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ
2229 *
2230 * Returns SCSI W-LUN id
2231 */
2232static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2233{
2234 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2235}
2236
7a3e97b0
SY
2237/**
2238 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2239 * @host: SCSI host pointer
7a3e97b0 2240 * @cmd: command from SCSI Midlayer
7a3e97b0
SY
2241 *
2242 * Returns 0 for success, non-zero in case of failure
2243 */
2244static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2245{
2246 struct ufshcd_lrb *lrbp;
2247 struct ufs_hba *hba;
2248 unsigned long flags;
2249 int tag;
2250 int err = 0;
2251
2252 hba = shost_priv(host);
2253
2254 tag = cmd->request->tag;
14497328
YG
2255 if (!ufshcd_valid_tag(hba, tag)) {
2256 dev_err(hba->dev,
2257 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2258 __func__, tag, cmd, cmd->request);
2259 BUG();
2260 }
7a3e97b0 2261
a3cd5ec5 2262 if (!down_read_trylock(&hba->clk_scaling_lock))
2263 return SCSI_MLQUEUE_HOST_BUSY;
2264
3441da7d
SRT
2265 spin_lock_irqsave(hba->host->host_lock, flags);
2266 switch (hba->ufshcd_state) {
2267 case UFSHCD_STATE_OPERATIONAL:
2268 break;
141f8165 2269 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2270 case UFSHCD_STATE_RESET:
7a3e97b0 2271 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT
2272 goto out_unlock;
2273 case UFSHCD_STATE_ERROR:
2274 set_host_byte(cmd, DID_ERROR);
2275 cmd->scsi_done(cmd);
2276 goto out_unlock;
2277 default:
2278 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2279 __func__, hba->ufshcd_state);
2280 set_host_byte(cmd, DID_BAD_TARGET);
2281 cmd->scsi_done(cmd);
2282 goto out_unlock;
7a3e97b0 2283 }
53c12d0e
YG
2284
2285 /* if error handling is in progress, don't issue commands */
2286 if (ufshcd_eh_in_progress(hba)) {
2287 set_host_byte(cmd, DID_ERROR);
2288 cmd->scsi_done(cmd);
2289 goto out_unlock;
2290 }
3441da7d 2291 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2292
7fabb77b
GB
2293 hba->req_abort_count = 0;
2294
5a0b0cb9
SRT
2295 /* acquire the tag to make sure device cmds don't use it */
2296 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2297 /*
2298 * Dev manage command in progress, requeue the command.
2299 * Requeuing the command helps in cases where the request *may*
2300 * find different tag instead of waiting for dev manage command
2301 * completion.
2302 */
2303 err = SCSI_MLQUEUE_HOST_BUSY;
2304 goto out;
2305 }
2306
1ab27c9c
ST
2307 err = ufshcd_hold(hba, true);
2308 if (err) {
2309 err = SCSI_MLQUEUE_HOST_BUSY;
2310 clear_bit_unlock(tag, &hba->lrb_in_use);
2311 goto out;
2312 }
2313 WARN_ON(hba->clk_gating.state != CLKS_ON);
2314
7a3e97b0
SY
2315 lrbp = &hba->lrb[tag];
2316
5a0b0cb9 2317 WARN_ON(lrbp->cmd);
7a3e97b0 2318 lrbp->cmd = cmd;
dcea0bfb 2319 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY
2320 lrbp->sense_buffer = cmd->sense_buffer;
2321 lrbp->task_tag = tag;
0ce147d4 2322 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2323 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2324 lrbp->req_abort_skip = false;
7a3e97b0 2325
300bb13f
JP
2326 ufshcd_comp_scsi_upiu(hba, lrbp);
2327
75b1cc4a 2328 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT
2329 if (err) {
2330 lrbp->cmd = NULL;
2331 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2332 goto out;
5a0b0cb9 2333 }
ad1a1b9c
GB
2334 /* Make sure descriptors are ready before ringing the doorbell */
2335 wmb();
7a3e97b0
SY
2336
2337 /* issue command to the controller */
2338 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2339 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2340 ufshcd_send_command(hba, tag);
3441da7d 2341out_unlock:
7a3e97b0
SY
2342 spin_unlock_irqrestore(hba->host->host_lock, flags);
2343out:
a3cd5ec5 2344 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY
2345 return err;
2346}
2347
5a0b0cb9
SRT
2348static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2349 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2350{
2351 lrbp->cmd = NULL;
2352 lrbp->sense_bufflen = 0;
2353 lrbp->sense_buffer = NULL;
2354 lrbp->task_tag = tag;
2355 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT
2356 lrbp->intr_cmd = true; /* No interrupt aggregation */
2357 hba->dev_cmd.type = cmd_type;
2358
300bb13f 2359 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT
2360}
2361
2362static int
2363ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2364{
2365 int err = 0;
2366 unsigned long flags;
2367 u32 mask = 1 << tag;
2368
2369 /* clear outstanding transaction before retry */
2370 spin_lock_irqsave(hba->host->host_lock, flags);
2371 ufshcd_utrl_clear(hba, tag);
2372 spin_unlock_irqrestore(hba->host->host_lock, flags);
2373
2374 /*
2375 * wait for for h/w to clear corresponding bit in door-bell.
2376 * max. wait is 1 sec.
2377 */
2378 err = ufshcd_wait_for_register(hba,
2379 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2380 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT
2381
2382 return err;
2383}
2384
c6d4a831
DR
2385static int
2386ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2387{
2388 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2389
2390 /* Get the UPIU response */
2391 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2392 UPIU_RSP_CODE_OFFSET;
2393 return query_res->response;
2394}
2395
5a0b0cb9
SRT
2396/**
2397 * ufshcd_dev_cmd_completion() - handles device management command responses
2398 * @hba: per adapter instance
2399 * @lrbp: pointer to local reference block
2400 */
2401static int
2402ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2403{
2404 int resp;
2405 int err = 0;
2406
ff8e20c6 2407 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT
2408 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2409
2410 switch (resp) {
2411 case UPIU_TRANSACTION_NOP_IN:
2412 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2413 err = -EINVAL;
2414 dev_err(hba->dev, "%s: unexpected response %x\n",
2415 __func__, resp);
2416 }
2417 break;
68078d5c 2418 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR
2419 err = ufshcd_check_query_response(hba, lrbp);
2420 if (!err)
2421 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2422 break;
5a0b0cb9
SRT
2423 case UPIU_TRANSACTION_REJECT_UPIU:
2424 /* TODO: handle Reject UPIU Response */
2425 err = -EPERM;
2426 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2427 __func__);
2428 break;
2429 default:
2430 err = -EINVAL;
2431 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2432 __func__, resp);
2433 break;
2434 }
2435
2436 return err;
2437}
2438
2439static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2440 struct ufshcd_lrb *lrbp, int max_timeout)
2441{
2442 int err = 0;
2443 unsigned long time_left;
2444 unsigned long flags;
2445
2446 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2447 msecs_to_jiffies(max_timeout));
2448
ad1a1b9c
GB
2449 /* Make sure descriptors are ready before ringing the doorbell */
2450 wmb();
5a0b0cb9
SRT
2451 spin_lock_irqsave(hba->host->host_lock, flags);
2452 hba->dev_cmd.complete = NULL;
2453 if (likely(time_left)) {
2454 err = ufshcd_get_tr_ocs(lrbp);
2455 if (!err)
2456 err = ufshcd_dev_cmd_completion(hba, lrbp);
2457 }
2458 spin_unlock_irqrestore(hba->host->host_lock, flags);
2459
2460 if (!time_left) {
2461 err = -ETIMEDOUT;
a48353f6
YG
2462 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2463 __func__, lrbp->task_tag);
5a0b0cb9 2464 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2465 /* successfully cleared the command, retry if needed */
5a0b0cb9 2466 err = -EAGAIN;
a48353f6
YG
2467 /*
2468 * in case of an error, after clearing the doorbell,
2469 * we also need to clear the outstanding_request
2470 * field in hba
2471 */
2472 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT
2473 }
2474
2475 return err;
2476}
2477
2478/**
2479 * ufshcd_get_dev_cmd_tag - Get device management command tag
2480 * @hba: per-adapter instance
8aa29f19 2481 * @tag_out: pointer to variable with available slot value
5a0b0cb9
SRT
2482 *
2483 * Get a free slot and lock it until device management command
2484 * completes.
2485 *
2486 * Returns false if free slot is unavailable for locking, else
2487 * return true with tag value in @tag.
2488 */
2489static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2490{
2491 int tag;
2492 bool ret = false;
2493 unsigned long tmp;
2494
2495 if (!tag_out)
2496 goto out;
2497
2498 do {
2499 tmp = ~hba->lrb_in_use;
2500 tag = find_last_bit(&tmp, hba->nutrs);
2501 if (tag >= hba->nutrs)
2502 goto out;
2503 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2504
2505 *tag_out = tag;
2506 ret = true;
2507out:
2508 return ret;
2509}
2510
2511static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2512{
2513 clear_bit_unlock(tag, &hba->lrb_in_use);
2514}
2515
2516/**
2517 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA
2518 * @hba: UFS hba
2519 * @cmd_type: specifies the type (NOP, Query...)
2520 * @timeout: time in seconds
5a0b0cb9 2521 *
68078d5c
DR
2522 * NOTE: Since there is only one available tag for device management commands,
2523 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT
2524 */
2525static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2526 enum dev_cmd_type cmd_type, int timeout)
2527{
2528 struct ufshcd_lrb *lrbp;
2529 int err;
2530 int tag;
2531 struct completion wait;
2532 unsigned long flags;
2533
a3cd5ec5 2534 down_read(&hba->clk_scaling_lock);
2535
5a0b0cb9
SRT
2536 /*
2537 * Get free slot, sleep if slots are unavailable.
2538 * Even though we use wait_event() which sleeps indefinitely,
2539 * the maximum wait time is bounded by SCSI request timeout.
2540 */
2541 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2542
2543 init_completion(&wait);
2544 lrbp = &hba->lrb[tag];
2545 WARN_ON(lrbp->cmd);
2546 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2547 if (unlikely(err))
2548 goto out_put_tag;
2549
2550 hba->dev_cmd.complete = &wait;
2551
e3dfdc53
YG
2552 /* Make sure descriptors are ready before ringing the doorbell */
2553 wmb();
5a0b0cb9 2554 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2555 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT
2556 ufshcd_send_command(hba, tag);
2557 spin_unlock_irqrestore(hba->host->host_lock, flags);
2558
2559 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2560
2561out_put_tag:
2562 ufshcd_put_dev_cmd_tag(hba, tag);
2563 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2564 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT
2565 return err;
2566}
2567
d44a5f98
DR
2568/**
2569 * ufshcd_init_query() - init the query response and request parameters
2570 * @hba: per-adapter instance
2571 * @request: address of the request pointer to be initialized
2572 * @response: address of the response pointer to be initialized
2573 * @opcode: operation to perform
2574 * @idn: flag idn to access
2575 * @index: LU number to access
2576 * @selector: query/flag/descriptor further identification
2577 */
2578static inline void ufshcd_init_query(struct ufs_hba *hba,
2579 struct ufs_query_req **request, struct ufs_query_res **response,
2580 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2581{
2582 *request = &hba->dev_cmd.query.request;
2583 *response = &hba->dev_cmd.query.response;
2584 memset(*request, 0, sizeof(struct ufs_query_req));
2585 memset(*response, 0, sizeof(struct ufs_query_res));
2586 (*request)->upiu_req.opcode = opcode;
2587 (*request)->upiu_req.idn = idn;
2588 (*request)->upiu_req.index = index;
2589 (*request)->upiu_req.selector = selector;
2590}
2591
dc3c8d3a
YG
2592static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2593 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2594{
2595 int ret;
2596 int retries;
2597
2598 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2599 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2600 if (ret)
2601 dev_dbg(hba->dev,
2602 "%s: failed with error %d, retries %d\n",
2603 __func__, ret, retries);
2604 else
2605 break;
2606 }
2607
2608 if (ret)
2609 dev_err(hba->dev,
2610 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2611 __func__, opcode, idn, ret, retries);
2612 return ret;
2613}
2614
68078d5c
DR
2615/**
2616 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA
2617 * @hba: per-adapter instance
2618 * @opcode: flag query to perform
2619 * @idn: flag idn to access
2620 * @flag_res: the flag value after the query request completes
68078d5c
DR
2621 *
2622 * Returns 0 for success, non-zero in case of failure
2623 */
dc3c8d3a 2624int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR
2625 enum flag_idn idn, bool *flag_res)
2626{
d44a5f98
DR
2627 struct ufs_query_req *request = NULL;
2628 struct ufs_query_res *response = NULL;
2629 int err, index = 0, selector = 0;
e5ad406c 2630 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR
2631
2632 BUG_ON(!hba);
2633
1ab27c9c 2634 ufshcd_hold(hba, false);
68078d5c 2635 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR
2636 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2637 selector);
68078d5c
DR
2638
2639 switch (opcode) {
2640 case UPIU_QUERY_OPCODE_SET_FLAG:
2641 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2642 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2643 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2644 break;
2645 case UPIU_QUERY_OPCODE_READ_FLAG:
2646 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2647 if (!flag_res) {
2648 /* No dummy reads */
2649 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2650 __func__);
2651 err = -EINVAL;
2652 goto out_unlock;
2653 }
2654 break;
2655 default:
2656 dev_err(hba->dev,
2657 "%s: Expected query flag opcode but got = %d\n",
2658 __func__, opcode);
2659 err = -EINVAL;
2660 goto out_unlock;
2661 }
68078d5c 2662
e5ad406c 2663 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR
2664
2665 if (err) {
2666 dev_err(hba->dev,
2667 "%s: Sending flag query for idn %d failed, err = %d\n",
2668 __func__, idn, err);
2669 goto out_unlock;
2670 }
2671
2672 if (flag_res)
e8c8e82a 2673 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR
2674 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2675
2676out_unlock:
2677 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2678 ufshcd_release(hba);
68078d5c
DR
2679 return err;
2680}
2681
66ec6d59
SRT
2682/**
2683 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA
2684 * @hba: per-adapter instance
2685 * @opcode: attribute opcode
2686 * @idn: attribute idn to access
2687 * @index: index field
2688 * @selector: selector field
2689 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT
2690 *
2691 * Returns 0 for success, non-zero in case of failure
2692*/
ec92b59c
SN
2693int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2694 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2695{
d44a5f98
DR
2696 struct ufs_query_req *request = NULL;
2697 struct ufs_query_res *response = NULL;
66ec6d59
SRT
2698 int err;
2699
2700 BUG_ON(!hba);
2701
1ab27c9c 2702 ufshcd_hold(hba, false);
66ec6d59
SRT
2703 if (!attr_val) {
2704 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2705 __func__, opcode);
2706 err = -EINVAL;
2707 goto out;
2708 }
2709
2710 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR
2711 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2712 selector);
66ec6d59
SRT
2713
2714 switch (opcode) {
2715 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2716 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2717 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT
2718 break;
2719 case UPIU_QUERY_OPCODE_READ_ATTR:
2720 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2721 break;
2722 default:
2723 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2724 __func__, opcode);
2725 err = -EINVAL;
2726 goto out_unlock;
2727 }
2728
d44a5f98 2729 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT
2730
2731 if (err) {
4b761b58
YG
2732 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2733 __func__, opcode, idn, index, err);
66ec6d59
SRT
2734 goto out_unlock;
2735 }
2736
e8c8e82a 2737 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT
2738
2739out_unlock:
2740 mutex_unlock(&hba->dev_cmd.lock);
2741out:
1ab27c9c 2742 ufshcd_release(hba);
66ec6d59
SRT
2743 return err;
2744}
2745
5e86ae44
YG
2746/**
2747 * ufshcd_query_attr_retry() - API function for sending query
2748 * attribute with retries
2749 * @hba: per-adapter instance
2750 * @opcode: attribute opcode
2751 * @idn: attribute idn to access
2752 * @index: index field
2753 * @selector: selector field
2754 * @attr_val: the attribute value after the query request
2755 * completes
2756 *
2757 * Returns 0 for success, non-zero in case of failure
2758*/
2759static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2760 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2761 u32 *attr_val)
2762{
2763 int ret = 0;
2764 u32 retries;
2765
2766 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2767 ret = ufshcd_query_attr(hba, opcode, idn, index,
2768 selector, attr_val);
2769 if (ret)
2770 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2771 __func__, ret, retries);
2772 else
2773 break;
2774 }
2775
2776 if (ret)
2777 dev_err(hba->dev,
2778 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2779 __func__, idn, ret, QUERY_REQ_RETRIES);
2780 return ret;
2781}
2782
a70e91b8 2783static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR
2784 enum query_opcode opcode, enum desc_idn idn, u8 index,
2785 u8 selector, u8 *desc_buf, int *buf_len)
2786{
2787 struct ufs_query_req *request = NULL;
2788 struct ufs_query_res *response = NULL;
2789 int err;
2790
2791 BUG_ON(!hba);
2792
1ab27c9c 2793 ufshcd_hold(hba, false);
d44a5f98
DR
2794 if (!desc_buf) {
2795 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2796 __func__, opcode);
2797 err = -EINVAL;
2798 goto out;
2799 }
2800
a4b0e8a4 2801 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR
2802 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2803 __func__, *buf_len);
2804 err = -EINVAL;
2805 goto out;
2806 }
2807
2808 mutex_lock(&hba->dev_cmd.lock);
2809 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2810 selector);
2811 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2812 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR
2813
2814 switch (opcode) {
2815 case UPIU_QUERY_OPCODE_WRITE_DESC:
2816 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2817 break;
2818 case UPIU_QUERY_OPCODE_READ_DESC:
2819 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2820 break;
2821 default:
2822 dev_err(hba->dev,
2823 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2824 __func__, opcode);
2825 err = -EINVAL;
2826 goto out_unlock;
2827 }
2828
2829 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2830
2831 if (err) {
4b761b58
YG
2832 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2833 __func__, opcode, idn, index, err);
d44a5f98
DR
2834 goto out_unlock;
2835 }
2836
2837 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2838 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR
2839
2840out_unlock:
2841 mutex_unlock(&hba->dev_cmd.lock);
2842out:
1ab27c9c 2843 ufshcd_release(hba);
d44a5f98
DR
2844 return err;
2845}
2846
a70e91b8 2847/**
8aa29f19
BVA
2848 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2849 * @hba: per-adapter instance
2850 * @opcode: attribute opcode
2851 * @idn: attribute idn to access
2852 * @index: index field
2853 * @selector: selector field
2854 * @desc_buf: the buffer that contains the descriptor
2855 * @buf_len: length parameter passed to the device
a70e91b8
YG
2856 *
2857 * Returns 0 for success, non-zero in case of failure.
2858 * The buf_len parameter will contain, on return, the length parameter
2859 * received on the response.
2860 */
2238d31c
SN
2861int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2862 enum query_opcode opcode,
2863 enum desc_idn idn, u8 index,
2864 u8 selector,
2865 u8 *desc_buf, int *buf_len)
a70e91b8
YG
2866{
2867 int err;
2868 int retries;
2869
2870 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2871 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2872 selector, desc_buf, buf_len);
2873 if (!err || err == -EINVAL)
2874 break;
2875 }
2876
2877 return err;
2878}
a70e91b8 2879
a4b0e8a4
PM
2880/**
2881 * ufshcd_read_desc_length - read the specified descriptor length from header
2882 * @hba: Pointer to adapter instance
2883 * @desc_id: descriptor idn value
2884 * @desc_index: descriptor index
2885 * @desc_length: pointer to variable to read the length of descriptor
2886 *
2887 * Return 0 in case of success, non-zero otherwise
2888 */
2889static int ufshcd_read_desc_length(struct ufs_hba *hba,
2890 enum desc_idn desc_id,
2891 int desc_index,
2892 int *desc_length)
2893{
2894 int ret;
2895 u8 header[QUERY_DESC_HDR_SIZE];
2896 int header_len = QUERY_DESC_HDR_SIZE;
2897
2898 if (desc_id >= QUERY_DESC_IDN_MAX)
2899 return -EINVAL;
2900
2901 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2902 desc_id, desc_index, 0, header,
2903 &header_len);
2904
2905 if (ret) {
2906 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
2907 __func__, desc_id);
2908 return ret;
2909 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
2910 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
2911 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
2912 desc_id);
2913 ret = -EINVAL;
2914 }
2915
2916 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
2917 return ret;
2918
2919}
2920
2921/**
2922 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
2923 * @hba: Pointer to adapter instance
2924 * @desc_id: descriptor idn value
2925 * @desc_len: mapped desc length (out)
2926 *
2927 * Return 0 in case of success, non-zero otherwise
2928 */
2929int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
2930 enum desc_idn desc_id, int *desc_len)
2931{
2932 switch (desc_id) {
2933 case QUERY_DESC_IDN_DEVICE:
2934 *desc_len = hba->desc_size.dev_desc;
2935 break;
2936 case QUERY_DESC_IDN_POWER:
2937 *desc_len = hba->desc_size.pwr_desc;
2938 break;
2939 case QUERY_DESC_IDN_GEOMETRY:
2940 *desc_len = hba->desc_size.geom_desc;
2941 break;
2942 case QUERY_DESC_IDN_CONFIGURATION:
2943 *desc_len = hba->desc_size.conf_desc;
2944 break;
2945 case QUERY_DESC_IDN_UNIT:
2946 *desc_len = hba->desc_size.unit_desc;
2947 break;
2948 case QUERY_DESC_IDN_INTERCONNECT:
2949 *desc_len = hba->desc_size.interc_desc;
2950 break;
2951 case QUERY_DESC_IDN_STRING:
2952 *desc_len = QUERY_DESC_MAX_SIZE;
2953 break;
c648c2d2
SN
2954 case QUERY_DESC_IDN_HEALTH:
2955 *desc_len = hba->desc_size.hlth_desc;
2956 break;
a4b0e8a4
PM
2957 case QUERY_DESC_IDN_RFU_0:
2958 case QUERY_DESC_IDN_RFU_1:
2959 *desc_len = 0;
2960 break;
2961 default:
2962 *desc_len = 0;
2963 return -EINVAL;
2964 }
2965 return 0;
2966}
2967EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
2968
da461cec
SJ
2969/**
2970 * ufshcd_read_desc_param - read the specified descriptor parameter
2971 * @hba: Pointer to adapter instance
2972 * @desc_id: descriptor idn value
2973 * @desc_index: descriptor index
2974 * @param_offset: offset of the parameter to read
2975 * @param_read_buf: pointer to buffer where parameter would be read
2976 * @param_size: sizeof(param_read_buf)
2977 *
2978 * Return 0 in case of success, non-zero otherwise
2979 */
45bced87
SN
2980int ufshcd_read_desc_param(struct ufs_hba *hba,
2981 enum desc_idn desc_id,
2982 int desc_index,
2983 u8 param_offset,
2984 u8 *param_read_buf,
2985 u8 param_size)
da461cec
SJ
2986{
2987 int ret;
2988 u8 *desc_buf;
a4b0e8a4 2989 int buff_len;
da461cec
SJ
2990 bool is_kmalloc = true;
2991
a4b0e8a4
PM
2992 /* Safety check */
2993 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ
2994 return -EINVAL;
2995
a4b0e8a4
PM
2996 /* Get the max length of descriptor from structure filled up at probe
2997 * time.
2998 */
2999 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3000
a4b0e8a4
PM
3001 /* Sanity checks */
3002 if (ret || !buff_len) {
3003 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3004 __func__);
3005 return ret;
3006 }
3007
3008 /* Check whether we need temp memory */
3009 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ
3010 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3011 if (!desc_buf)
3012 return -ENOMEM;
a4b0e8a4
PM
3013 } else {
3014 desc_buf = param_read_buf;
3015 is_kmalloc = false;
da461cec
SJ
3016 }
3017
a4b0e8a4 3018 /* Request for full descriptor */
a70e91b8 3019 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM
3020 desc_id, desc_index, 0,
3021 desc_buf, &buff_len);
da461cec 3022
bde44bb6 3023 if (ret) {
3024 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3025 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ
3026 goto out;
3027 }
3028
bde44bb6 3029 /* Sanity check */
3030 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3031 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3032 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3033 ret = -EINVAL;
3034 goto out;
3035 }
3036
a4b0e8a4
PM
3037 /* Check wherher we will not copy more data, than available */
3038 if (is_kmalloc && param_size > buff_len)
3039 param_size = buff_len;
bde44bb6 3040
da461cec
SJ
3041 if (is_kmalloc)
3042 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3043out:
3044 if (is_kmalloc)
3045 kfree(desc_buf);
3046 return ret;
3047}
3048
3049static inline int ufshcd_read_desc(struct ufs_hba *hba,
3050 enum desc_idn desc_id,
3051 int desc_index,
3052 u8 *buf,
3053 u32 size)
3054{
3055 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3056}
3057
3058static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3059 u8 *buf,
3060 u32 size)
3061{
dbd34a61 3062 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ
3063}
3064
8209b6d5 3065static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG
3066{
3067 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3068}
b573d484
YG
3069
3070/**
3071 * ufshcd_read_string_desc - read string descriptor
3072 * @hba: pointer to adapter instance
3073 * @desc_index: descriptor index
3074 * @buf: pointer to buffer where descriptor would be read
3075 * @size: size of buf
3076 * @ascii: if true convert from unicode to ascii characters
3077 *
3078 * Return 0 in case of success, non-zero otherwise
3079 */
2238d31c
SN
3080int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3081 u8 *buf, u32 size, bool ascii)
b573d484
YG
3082{
3083 int err = 0;
3084
3085 err = ufshcd_read_desc(hba,
3086 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3087
3088 if (err) {
3089 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3090 __func__, QUERY_REQ_RETRIES, err);
3091 goto out;
3092 }
3093
3094 if (ascii) {
3095 int desc_len;
3096 int ascii_len;
3097 int i;
3098 char *buff_ascii;
3099
3100 desc_len = buf[0];
3101 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3102 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3103 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3104 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3105 __func__);
3106 err = -ENOMEM;
3107 goto out;
3108 }
3109
3110 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3111 if (!buff_ascii) {
3112 err = -ENOMEM;
fcbefc3b 3113 goto out;
b573d484
YG
3114 }
3115
3116 /*
3117 * the descriptor contains string in UTF16 format
3118 * we need to convert to utf-8 so it can be displayed
3119 */
3120 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3121 desc_len - QUERY_DESC_HDR_SIZE,
3122 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3123
3124 /* replace non-printable or non-ASCII characters with spaces */
3125 for (i = 0; i < ascii_len; i++)
3126 ufshcd_remove_non_printable(&buff_ascii[i]);
3127
3128 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3129 size - QUERY_DESC_HDR_SIZE);
3130 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3131 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG
3132 kfree(buff_ascii);
3133 }
3134out:
3135 return err;
3136}
b573d484 3137
da461cec
SJ
3138/**
3139 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3140 * @hba: Pointer to adapter instance
3141 * @lun: lun id
3142 * @param_offset: offset of the parameter to read
3143 * @param_read_buf: pointer to buffer where parameter would be read
3144 * @param_size: sizeof(param_read_buf)
3145 *
3146 * Return 0 in case of success, non-zero otherwise
3147 */
3148static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3149 int lun,
3150 enum unit_desc_param param_offset,
3151 u8 *param_read_buf,
3152 u32 param_size)
3153{
3154 /*
3155 * Unit descriptors are only available for general purpose LUs (LUN id
3156 * from 0 to 7) and RPMB Well known LU.
3157 */
d829fc8a 3158 if (!ufs_is_valid_unit_desc_lun(lun))
da461cec
SJ
3159 return -EOPNOTSUPP;
3160
3161 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3162 param_offset, param_read_buf, param_size);
3163}
3164
7a3e97b0
SY
3165/**
3166 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3167 * @hba: per adapter instance
3168 *
3169 * 1. Allocate DMA memory for Command Descriptor array
3170 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3171 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3172 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3173 * (UTMRDL)
3174 * 4. Allocate memory for local reference block(lrb).
3175 *
3176 * Returns 0 for success, non-zero in case of failure
3177 */
3178static int ufshcd_memory_alloc(struct ufs_hba *hba)
3179{
3180 size_t utmrdl_size, utrdl_size, ucdl_size;
3181
3182 /* Allocate memory for UTP command descriptors */
3183 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ
3184 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3185 ucdl_size,
3186 &hba->ucdl_dma_addr,
3187 GFP_KERNEL);
7a3e97b0
SY
3188
3189 /*
3190 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3191 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3192 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3193 * be aligned to 128 bytes as well
3194 */
3195 if (!hba->ucdl_base_addr ||
3196 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3197 dev_err(hba->dev,
7a3e97b0
SY
3198 "Command Descriptor Memory allocation failed\n");
3199 goto out;
3200 }
3201
3202 /*
3203 * Allocate memory for UTP Transfer descriptors
3204 * UFSHCI requires 1024 byte alignment of UTRD
3205 */
3206 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ
3207 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3208 utrdl_size,
3209 &hba->utrdl_dma_addr,
3210 GFP_KERNEL);
7a3e97b0
SY
3211 if (!hba->utrdl_base_addr ||
3212 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3213 dev_err(hba->dev,
7a3e97b0
SY
3214 "Transfer Descriptor Memory allocation failed\n");
3215 goto out;
3216 }
3217
3218 /*
3219 * Allocate memory for UTP Task Management descriptors
3220 * UFSHCI requires 1024 byte alignment of UTMRD
3221 */
3222 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ
3223 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3224 utmrdl_size,
3225 &hba->utmrdl_dma_addr,
3226 GFP_KERNEL);
7a3e97b0
SY
3227 if (!hba->utmrdl_base_addr ||
3228 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3229 dev_err(hba->dev,
7a3e97b0
SY
3230 "Task Management Descriptor Memory allocation failed\n");
3231 goto out;
3232 }
3233
3234 /* Allocate memory for local reference block */
2953f850
SJ
3235 hba->lrb = devm_kzalloc(hba->dev,
3236 hba->nutrs * sizeof(struct ufshcd_lrb),
3237 GFP_KERNEL);
7a3e97b0 3238 if (!hba->lrb) {
3b1d0580 3239 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY
3240 goto out;
3241 }
3242 return 0;
3243out:
7a3e97b0
SY
3244 return -ENOMEM;
3245}
3246
3247/**
3248 * ufshcd_host_memory_configure - configure local reference block with
3249 * memory offsets
3250 * @hba: per adapter instance
3251 *
3252 * Configure Host memory space
3253 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3254 * address.
3255 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3256 * and PRDT offset.
3257 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3258 * into local reference block.
3259 */
3260static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3261{
3262 struct utp_transfer_cmd_desc *cmd_descp;
3263 struct utp_transfer_req_desc *utrdlp;
3264 dma_addr_t cmd_desc_dma_addr;
3265 dma_addr_t cmd_desc_element_addr;
3266 u16 response_offset;
3267 u16 prdt_offset;
3268 int cmd_desc_size;
3269 int i;
3270
3271 utrdlp = hba->utrdl_base_addr;
3272 cmd_descp = hba->ucdl_base_addr;
3273
3274 response_offset =
3275 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3276 prdt_offset =
3277 offsetof(struct utp_transfer_cmd_desc, prd_table);
3278
3279 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3280 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3281
3282 for (i = 0; i < hba->nutrs; i++) {
3283 /* Configure UTRD with command descriptor base address */
3284 cmd_desc_element_addr =
3285 (cmd_desc_dma_addr + (cmd_desc_size * i));
3286 utrdlp[i].command_desc_base_addr_lo =
3287 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3288 utrdlp[i].command_desc_base_addr_hi =
3289 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3290
3291 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK
3292 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3293 utrdlp[i].response_upiu_offset =
3294 cpu_to_le16(response_offset);
3295 utrdlp[i].prd_table_offset =
3296 cpu_to_le16(prdt_offset);
3297 utrdlp[i].response_upiu_length =
3298 cpu_to_le16(ALIGNED_UPIU_SIZE);
3299 } else {
3300 utrdlp[i].response_upiu_offset =
7a3e97b0 3301 cpu_to_le16((response_offset >> 2));
75b1cc4a 3302 utrdlp[i].prd_table_offset =
7a3e97b0 3303 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3304 utrdlp[i].response_upiu_length =
3ca316c5 3305 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3306 }
7a3e97b0
SY
3307
3308 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR
3309 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3310 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT
3311 hba->lrb[i].ucd_req_ptr =
3312 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3313 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY
3314 hba->lrb[i].ucd_rsp_ptr =
3315 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR
3316 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3317 response_offset;
7a3e97b0
SY
3318 hba->lrb[i].ucd_prdt_ptr =
3319 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR
3320 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3321 prdt_offset;
7a3e97b0
SY
3322 }
3323}
3324
3325/**
3326 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3327 * @hba: per adapter instance
3328 *
3329 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3330 * in order to initialize the Unipro link startup procedure.
3331 * Once the Unipro links are up, the device connected to the controller
3332 * is detected.
3333 *
3334 * Returns 0 on success, non-zero value on failure
3335 */
3336static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3337{
6ccf44fe
SJ
3338 struct uic_command uic_cmd = {0};
3339 int ret;
7a3e97b0 3340
6ccf44fe 3341 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3342
6ccf44fe
SJ
3343 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3344 if (ret)
ff8e20c6 3345 dev_dbg(hba->dev,
6ccf44fe
SJ
3346 "dme-link-startup: error code %d\n", ret);
3347 return ret;
7a3e97b0
SY
3348}
3349
cad2e03d
YG
3350static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3351{
3352 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3353 unsigned long min_sleep_time_us;
3354
3355 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3356 return;
3357
3358 /*
3359 * last_dme_cmd_tstamp will be 0 only for 1st call to
3360 * this function
3361 */
3362 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3363 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3364 } else {
3365 unsigned long delta =
3366 (unsigned long) ktime_to_us(
3367 ktime_sub(ktime_get(),
3368 hba->last_dme_cmd_tstamp));
3369
3370 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3371 min_sleep_time_us =
3372 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3373 else
3374 return; /* no more delay required */
3375 }
3376
3377 /* allow sleep for extra 50us if needed */
3378 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3379}
3380
12b4fdb4
SJ
3381/**
3382 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3383 * @hba: per adapter instance
3384 * @attr_sel: uic command argument1
3385 * @attr_set: attribute set type as uic command argument2
3386 * @mib_val: setting value as uic command argument3
3387 * @peer: indicate whether peer or local
3388 *
3389 * Returns 0 on success, non-zero value on failure
3390 */
3391int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3392 u8 attr_set, u32 mib_val, u8 peer)
3393{
3394 struct uic_command uic_cmd = {0};
3395 static const char *const action[] = {
3396 "dme-set",
3397 "dme-peer-set"
3398 };
3399 const char *set = action[!!peer];
3400 int ret;
64238fbd 3401 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ
3402
3403 uic_cmd.command = peer ?
3404 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3405 uic_cmd.argument1 = attr_sel;
3406 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3407 uic_cmd.argument3 = mib_val;
3408
64238fbd
YG
3409 do {
3410 /* for peer attributes we retry upon failure */
3411 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3412 if (ret)
3413 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3414 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3415 } while (ret && peer && --retries);
3416
f37e9f8c 3417 if (ret)
64238fbd 3418 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG
3419 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3420 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ
3421
3422 return ret;
3423}
3424EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3425
3426/**
3427 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3428 * @hba: per adapter instance
3429 * @attr_sel: uic command argument1
3430 * @mib_val: the value of the attribute as returned by the UIC command
3431 * @peer: indicate whether peer or local
3432 *
3433 * Returns 0 on success, non-zero value on failure
3434 */
3435int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3436 u32 *mib_val, u8 peer)
3437{
3438 struct uic_command uic_cmd = {0};
3439 static const char *const action[] = {
3440 "dme-get",
3441 "dme-peer-get"
3442 };
3443 const char *get = action[!!peer];
3444 int ret;
64238fbd 3445 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG
3446 struct ufs_pa_layer_attr orig_pwr_info;
3447 struct ufs_pa_layer_attr temp_pwr_info;
3448 bool pwr_mode_change = false;
3449
3450 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3451 orig_pwr_info = hba->pwr_info;
3452 temp_pwr_info = orig_pwr_info;
3453
3454 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3455 orig_pwr_info.pwr_rx == FAST_MODE) {
3456 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3457 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3458 pwr_mode_change = true;
3459 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3460 orig_pwr_info.pwr_rx == SLOW_MODE) {
3461 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3462 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3463 pwr_mode_change = true;
3464 }
3465 if (pwr_mode_change) {
3466 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3467 if (ret)
3468 goto out;
3469 }
3470 }
12b4fdb4
SJ
3471
3472 uic_cmd.command = peer ?
3473 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3474 uic_cmd.argument1 = attr_sel;
3475
64238fbd
YG
3476 do {
3477 /* for peer attributes we retry upon failure */
3478 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3479 if (ret)
3480 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3481 get, UIC_GET_ATTR_ID(attr_sel), ret);
3482 } while (ret && peer && --retries);
3483
f37e9f8c 3484 if (ret)
64238fbd 3485 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG
3486 get, UIC_GET_ATTR_ID(attr_sel),
3487 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3488
64238fbd 3489 if (mib_val && !ret)
12b4fdb4 3490 *mib_val = uic_cmd.argument3;
874237f7
YG
3491
3492 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3493 && pwr_mode_change)
3494 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ
3495out:
3496 return ret;
3497}
3498EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3499
53b3d9c3 3500/**
57d104c1
SJ
3501 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3502 * state) and waits for it to take effect.
3503 *
53b3d9c3 3504 * @hba: per adapter instance
57d104c1
SJ
3505 * @cmd: UIC command to execute
3506 *
3507 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3508 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3509 * and device UniPro link and hence it's final completion would be indicated by
3510 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3511 * addition to normal UIC command completion Status (UCCS). This function only
3512 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ
3513 *
3514 * Returns 0 on success, non-zero value on failure
3515 */
57d104c1 3516static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3517{
57d104c1 3518 struct completion uic_async_done;
53b3d9c3
SJ
3519 unsigned long flags;
3520 u8 status;
3521 int ret;
d75f7fe4 3522 bool reenable_intr = false;
53b3d9c3 3523
53b3d9c3 3524 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3525 init_completion(&uic_async_done);
cad2e03d 3526 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ
3527
3528 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3529 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG
3530 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3531 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3532 /*
3533 * Make sure UIC command completion interrupt is disabled before
3534 * issuing UIC command.
3535 */
3536 wmb();
3537 reenable_intr = true;
57d104c1 3538 }
d75f7fe4
YG
3539 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3540 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ
3541 if (ret) {
3542 dev_err(hba->dev,
3543 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3544 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ
3545 goto out;
3546 }
3547
57d104c1 3548 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ
3549 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3550 dev_err(hba->dev,
57d104c1
SJ
3551 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3552 cmd->command, cmd->argument3);
53b3d9c3
SJ
3553 ret = -ETIMEDOUT;
3554 goto out;
3555 }
3556
3557 status = ufshcd_get_upmcrs(hba);
3558 if (status != PWR_LOCAL) {
3559 dev_err(hba->dev,
479da360 3560 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3561 cmd->command, status);
53b3d9c3
SJ
3562 ret = (status != PWR_OK) ? status : -1;
3563 }
3564out:
7942f7b5
VG
3565 if (ret) {
3566 ufshcd_print_host_state(hba);
3567 ufshcd_print_pwr_info(hba);
3568 ufshcd_print_host_regs(hba);
3569 }
3570
53b3d9c3 3571 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3572 hba->active_uic_cmd = NULL;
57d104c1 3573 hba->uic_async_done = NULL;
d75f7fe4
YG
3574 if (reenable_intr)
3575 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ
3576 spin_unlock_irqrestore(hba->host->host_lock, flags);
3577 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3578
53b3d9c3
SJ
3579 return ret;
3580}
3581
57d104c1
SJ
3582/**
3583 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3584 * using DME_SET primitives.
3585 * @hba: per adapter instance
3586 * @mode: powr mode value
3587 *
3588 * Returns 0 on success, non-zero value on failure
3589 */
3590static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3591{
3592 struct uic_command uic_cmd = {0};
1ab27c9c 3593 int ret;
57d104c1 3594
c3a2f9ee
YG
3595 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3596 ret = ufshcd_dme_set(hba,
3597 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3598 if (ret) {
3599 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3600 __func__, ret);
3601 goto out;
3602 }
3603 }
3604
57d104c1
SJ
3605 uic_cmd.command = UIC_CMD_DME_SET;
3606 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3607 uic_cmd.argument3 = mode;
1ab27c9c
ST
3608 ufshcd_hold(hba, false);
3609 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3610 ufshcd_release(hba);
57d104c1 3611
c3a2f9ee 3612out:
1ab27c9c 3613 return ret;
57d104c1
SJ
3614}
3615
53c12d0e
YG
3616static int ufshcd_link_recovery(struct ufs_hba *hba)
3617{
3618 int ret;
3619 unsigned long flags;
3620
3621 spin_lock_irqsave(hba->host->host_lock, flags);
3622 hba->ufshcd_state = UFSHCD_STATE_RESET;
3623 ufshcd_set_eh_in_progress(hba);
3624 spin_unlock_irqrestore(hba->host->host_lock, flags);
3625
3626 ret = ufshcd_host_reset_and_restore(hba);
3627
3628 spin_lock_irqsave(hba->host->host_lock, flags);
3629 if (ret)
3630 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3631 ufshcd_clear_eh_in_progress(hba);
3632 spin_unlock_irqrestore(hba->host->host_lock, flags);
3633
3634 if (ret)
3635 dev_err(hba->dev, "%s: link recovery failed, err %d",
3636 __func__, ret);
3637
3638 return ret;
3639}
3640
87d0b4a6 3641static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3642{
87d0b4a6 3643 int ret;
57d104c1 3644 struct uic_command uic_cmd = {0};
911a0771 3645 ktime_t start = ktime_get();
57d104c1 3646
ee32c909
KK
3647 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3648
57d104c1 3649 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3650 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3651 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3652 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3653
53c12d0e 3654 if (ret) {
87d0b4a6
YG
3655 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3656 __func__, ret);
3657
53c12d0e
YG
3658 /*
3659 * If link recovery fails then return error so that caller
3660 * don't retry the hibern8 enter again.
3661 */
3662 if (ufshcd_link_recovery(hba))
3663 ret = -ENOLINK;
ee32c909
KK
3664 } else
3665 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3666 POST_CHANGE);
53c12d0e 3667
87d0b4a6
YG
3668 return ret;
3669}
3670
3671static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3672{
3673 int ret = 0, retries;
57d104c1 3674
87d0b4a6
YG
3675 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3676 ret = __ufshcd_uic_hibern8_enter(hba);
3677 if (!ret || ret == -ENOLINK)
3678 goto out;
3679 }
3680out:
3681 return ret;
57d104c1
SJ
3682}
3683
3684static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3685{
3686 struct uic_command uic_cmd = {0};
3687 int ret;
911a0771 3688 ktime_t start = ktime_get();
57d104c1 3689
ee32c909
KK
3690 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3691
57d104c1
SJ
3692 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3693 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3694 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3695 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3696
57d104c1 3697 if (ret) {
53c12d0e
YG
3698 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3699 __func__, ret);
3700 ret = ufshcd_link_recovery(hba);
ff8e20c6 3701 } else {
ee32c909
KK
3702 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3703 POST_CHANGE);
ff8e20c6
DR
3704 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3705 hba->ufs_stats.hibern8_exit_cnt++;
3706 }
57d104c1
SJ
3707
3708 return ret;
3709}
3710
5064636c
YG
3711 /**
3712 * ufshcd_init_pwr_info - setting the POR (power on reset)
3713 * values in hba power info
3714 * @hba: per-adapter instance
3715 */
3716static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3717{
3718 hba->pwr_info.gear_rx = UFS_PWM_G1;
3719 hba->pwr_info.gear_tx = UFS_PWM_G1;
3720 hba->pwr_info.lane_rx = 1;
3721 hba->pwr_info.lane_tx = 1;
3722 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3723 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3724 hba->pwr_info.hs_rate = 0;
3725}
3726
d3e89bac 3727/**
7eb584db
DR
3728 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3729 * @hba: per-adapter instance
d3e89bac 3730 */
7eb584db 3731static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3732{
7eb584db
DR
3733 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3734
3735 if (hba->max_pwr_info.is_valid)
3736 return 0;
3737
2349b533 3738 pwr_info->pwr_tx = FAST_MODE;
3739 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3740 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ
3741
3742 /* Get the connected lane count */
7eb584db
DR
3743 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3744 &pwr_info->lane_rx);
3745 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3746 &pwr_info->lane_tx);
3747
3748 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3749 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3750 __func__,
3751 pwr_info->lane_rx,
3752 pwr_info->lane_tx);
3753 return -EINVAL;
3754 }
d3e89bac
SJ
3755
3756 /*
3757 * First, get the maximum gears of HS speed.
3758 * If a zero value, it means there is no HSGEAR capability.
3759 * Then, get the maximum gears of PWM speed.
3760 */
7eb584db
DR
3761 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3762 if (!pwr_info->gear_rx) {
3763 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3764 &pwr_info->gear_rx);
3765 if (!pwr_info->gear_rx) {
3766 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3767 __func__, pwr_info->gear_rx);
3768 return -EINVAL;
3769 }
2349b533 3770 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ
3771 }
3772
7eb584db
DR
3773 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3774 &pwr_info->gear_tx);
3775 if (!pwr_info->gear_tx) {
d3e89bac 3776 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR
3777 &pwr_info->gear_tx);
3778 if (!pwr_info->gear_tx) {
3779 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3780 __func__, pwr_info->gear_tx);
3781 return -EINVAL;
3782 }
2349b533 3783 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR
3784 }
3785
3786 hba->max_pwr_info.is_valid = true;
3787 return 0;
3788}
3789
3790static int ufshcd_change_power_mode(struct ufs_hba *hba,
3791 struct ufs_pa_layer_attr *pwr_mode)
3792{
3793 int ret;
3794
3795 /* if already configured to the requested pwr_mode */
3796 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3797 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3798 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3799 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3800 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3801 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3802 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3803 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3804 return 0;
d3e89bac
SJ
3805 }
3806
3807 /*
3808 * Configure attributes for power mode change with below.
3809 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3810 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3811 * - PA_HSSERIES
3812 */
7eb584db
DR
3813 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3814 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3815 pwr_mode->lane_rx);
3816 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3817 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3818 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR
3819 else
3820 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3821
7eb584db
DR
3822 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3823 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3824 pwr_mode->lane_tx);
3825 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3826 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 3827 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR
3828 else
3829 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 3830
7eb584db
DR
3831 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3832 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3833 pwr_mode->pwr_rx == FAST_MODE ||
3834 pwr_mode->pwr_tx == FAST_MODE)
3835 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3836 pwr_mode->hs_rate);
d3e89bac 3837
7eb584db
DR
3838 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3839 | pwr_mode->pwr_tx);
3840
3841 if (ret) {
d3e89bac 3842 dev_err(hba->dev,
7eb584db
DR
3843 "%s: power mode change failed %d\n", __func__, ret);
3844 } else {
0263bcd0
YG
3845 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3846 pwr_mode);
7eb584db
DR
3847
3848 memcpy(&hba->pwr_info, pwr_mode,
3849 sizeof(struct ufs_pa_layer_attr));
3850 }
3851
3852 return ret;
3853}
3854
3855/**
3856 * ufshcd_config_pwr_mode - configure a new power mode
3857 * @hba: per-adapter instance
3858 * @desired_pwr_mode: desired power configuration
3859 */
3860static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3861 struct ufs_pa_layer_attr *desired_pwr_mode)
3862{
3863 struct ufs_pa_layer_attr final_params = { 0 };
3864 int ret;
3865
0263bcd0
YG
3866 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3867 desired_pwr_mode, &final_params);
3868
3869 if (ret)
7eb584db
DR
3870 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3871
3872 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5 3873 if (!ret)
3874 ufshcd_print_pwr_info(hba);
d3e89bac
SJ
3875
3876 return ret;
3877}
3878
68078d5c
DR
3879/**
3880 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 3881 * @hba: per-adapter instance
68078d5c
DR
3882 *
3883 * Set fDeviceInit flag and poll until device toggles it.
3884 */
3885static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3886{
dc3c8d3a
YG
3887 int i;
3888 int err;
68078d5c
DR
3889 bool flag_res = 1;
3890
dc3c8d3a
YG
3891 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3892 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR
3893 if (err) {
3894 dev_err(hba->dev,
3895 "%s setting fDeviceInit flag failed with error %d\n",
3896 __func__, err);
3897 goto out;
3898 }
3899
dc3c8d3a
YG
3900 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3901 for (i = 0; i < 1000 && !err && flag_res; i++)
3902 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3903 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3904
68078d5c
DR
3905 if (err)
3906 dev_err(hba->dev,
3907 "%s reading fDeviceInit flag failed with error %d\n",
3908 __func__, err);
3909 else if (flag_res)
3910 dev_err(hba->dev,
3911 "%s fDeviceInit was not cleared by the device\n",
3912 __func__);
3913
3914out:
3915 return err;
3916}
3917
7a3e97b0
SY
3918/**
3919 * ufshcd_make_hba_operational - Make UFS controller operational
3920 * @hba: per adapter instance
3921 *
3922 * To bring UFS host controller to operational state,
5c0c28a8
SRT
3923 * 1. Enable required interrupts
3924 * 2. Configure interrupt aggregation
897efe62 3925 * 3. Program UTRL and UTMRL base address
5c0c28a8 3926 * 4. Configure run-stop-registers
7a3e97b0
SY
3927 *
3928 * Returns 0 on success, non-zero value on failure
3929 */
3930static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3931{
3932 int err = 0;
3933 u32 reg;
3934
6ccf44fe
SJ
3935 /* Enable required interrupts */
3936 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3937
3938 /* Configure interrupt aggregation */
b852190e
YG
3939 if (ufshcd_is_intr_aggr_allowed(hba))
3940 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3941 else
3942 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ
3943
3944 /* Configure UTRL and UTMRL base address registers */
3945 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3946 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3947 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3948 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3949 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3950 REG_UTP_TASK_REQ_LIST_BASE_L);
3951 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3952 REG_UTP_TASK_REQ_LIST_BASE_H);
3953
897efe62
YG
3954 /*
3955 * Make sure base address and interrupt setup are updated before
3956 * enabling the run/stop registers below.
3957 */
3958 wmb();
3959
7a3e97b0
SY
3960 /*
3961 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3962 */
5c0c28a8 3963 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY
3964 if (!(ufshcd_get_lists_status(reg))) {
3965 ufshcd_enable_run_stop_reg(hba);
3966 } else {
3b1d0580 3967 dev_err(hba->dev,
7a3e97b0
SY
3968 "Host controller not ready to process requests");
3969 err = -EIO;
3970 goto out;
3971 }
3972
7a3e97b0
SY
3973out:
3974 return err;
3975}
3976
596585a2
YG
3977/**
3978 * ufshcd_hba_stop - Send controller to reset state
3979 * @hba: per adapter instance
3980 * @can_sleep: perform sleep or just spin
3981 */
3982static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3983{
3984 int err;
3985
3986 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3987 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3988 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3989 10, 1, can_sleep);
3990 if (err)
3991 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3992}
3993
7a3e97b0
SY
3994/**
3995 * ufshcd_hba_enable - initialize the controller
3996 * @hba: per adapter instance
3997 *
3998 * The controller resets itself and controller firmware initialization
3999 * sequence kicks off. When controller is ready it will set
4000 * the Host Controller Enable bit to 1.
4001 *
4002 * Returns 0 on success, non-zero value on failure
4003 */
4004static int ufshcd_hba_enable(struct ufs_hba *hba)
4005{
4006 int retry;
4007
4008 /*
4009 * msleep of 1 and 5 used in this function might result in msleep(20),
4010 * but it was necessary to send the UFS FPGA to reset mode during
4011 * development and testing of this driver. msleep can be changed to
4012 * mdelay and retry count can be reduced based on the controller.
4013 */
596585a2 4014 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4015 /* change controller state to "reset state" */
596585a2 4016 ufshcd_hba_stop(hba, true);
7a3e97b0 4017
57d104c1
SJ
4018 /* UniPro link is disabled at this point */
4019 ufshcd_set_link_off(hba);
4020
0263bcd0 4021 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4022
7a3e97b0
SY
4023 /* start controller initialization sequence */
4024 ufshcd_hba_start(hba);
4025
4026 /*
4027 * To initialize a UFS host controller HCE bit must be set to 1.
4028 * During initialization the HCE bit value changes from 1->0->1.
4029 * When the host controller completes initialization sequence
4030 * it sets the value of HCE bit to 1. The same HCE bit is read back
4031 * to check if the controller has completed initialization sequence.
4032 * So without this delay the value HCE = 1, set in the previous
4033 * instruction might be read back.
4034 * This delay can be changed based on the controller.
4035 */
4036 msleep(1);
4037
4038 /* wait for the host controller to complete initialization */
4039 retry = 10;
4040 while (ufshcd_is_hba_active(hba)) {
4041 if (retry) {
4042 retry--;
4043 } else {
3b1d0580 4044 dev_err(hba->dev,
7a3e97b0
SY
4045 "Controller enable failed\n");
4046 return -EIO;
4047 }
4048 msleep(5);
4049 }
5c0c28a8 4050
1d337ec2 4051 /* enable UIC related interrupts */
57d104c1 4052 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4053
0263bcd0 4054 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4055
7a3e97b0
SY
4056 return 0;
4057}
4058
7ca38cf3
YG
4059static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4060{
4061 int tx_lanes, i, err = 0;
4062
4063 if (!peer)
4064 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4065 &tx_lanes);
4066 else
4067 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4068 &tx_lanes);
4069 for (i = 0; i < tx_lanes; i++) {
4070 if (!peer)
4071 err = ufshcd_dme_set(hba,
4072 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4073 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4074 0);
4075 else
4076 err = ufshcd_dme_peer_set(hba,
4077 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4078 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4079 0);
4080 if (err) {
4081 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4082 __func__, peer, i, err);
4083 break;
4084 }
4085 }
4086
4087 return err;
4088}
4089
4090static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4091{
4092 return ufshcd_disable_tx_lcc(hba, true);
4093}
4094
7a3e97b0 4095/**
6ccf44fe 4096 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY
4097 * @hba: per adapter instance
4098 *
6ccf44fe 4099 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4100 */
6ccf44fe 4101static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4102{
6ccf44fe 4103 int ret;
1d337ec2 4104 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4105 bool link_startup_again = false;
7a3e97b0 4106
7caf489b 4107 /*
4108 * If UFS device isn't active then we will have to issue link startup
4109 * 2 times to make sure the device state move to active.
4110 */
4111 if (!ufshcd_is_ufs_dev_active(hba))
4112 link_startup_again = true;
7a3e97b0 4113
7caf489b 4114link_startup:
1d337ec2 4115 do {
0263bcd0 4116 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4117
1d337ec2 4118 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4119
1d337ec2
SRT
4120 /* check if device is detected by inter-connect layer */
4121 if (!ret && !ufshcd_is_device_present(hba)) {
4122 dev_err(hba->dev, "%s: Device not present\n", __func__);
4123 ret = -ENXIO;
4124 goto out;
4125 }
6ccf44fe 4126
1d337ec2
SRT
4127 /*
4128 * DME link lost indication is only received when link is up,
4129 * but we can't be sure if the link is up until link startup
4130 * succeeds. So reset the local Uni-Pro and try again.
4131 */
4132 if (ret && ufshcd_hba_enable(hba))
4133 goto out;
4134 } while (ret && retries--);
4135
4136 if (ret)
4137 /* failed to get the link up... retire */
5c0c28a8 4138 goto out;
5c0c28a8 4139
7caf489b 4140 if (link_startup_again) {
4141 link_startup_again = false;
4142 retries = DME_LINKSTARTUP_RETRIES;
4143 goto link_startup;
4144 }
4145
d2aebb9b 4146 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4147 ufshcd_init_pwr_info(hba);
4148 ufshcd_print_pwr_info(hba);
4149
7ca38cf3
YG
4150 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4151 ret = ufshcd_disable_device_tx_lcc(hba);
4152 if (ret)
4153 goto out;
4154 }
4155
5c0c28a8 4156 /* Include any host controller configuration via UIC commands */
0263bcd0
YG
4157 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4158 if (ret)
4159 goto out;
7a3e97b0 4160
5c0c28a8 4161 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4162out:
7942f7b5 4163 if (ret) {
6ccf44fe 4164 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG
4165 ufshcd_print_host_state(hba);
4166 ufshcd_print_pwr_info(hba);
4167 ufshcd_print_host_regs(hba);
4168 }
6ccf44fe 4169 return ret;
7a3e97b0
SY
4170}
4171
5a0b0cb9
SRT
4172/**
4173 * ufshcd_verify_dev_init() - Verify device initialization
4174 * @hba: per-adapter instance
4175 *
4176 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4177 * device Transport Protocol (UTP) layer is ready after a reset.
4178 * If the UTP layer at the device side is not initialized, it may
4179 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4180 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4181 */
4182static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4183{
4184 int err = 0;
4185 int retries;
4186
1ab27c9c 4187 ufshcd_hold(hba, false);
5a0b0cb9
SRT
4188 mutex_lock(&hba->dev_cmd.lock);
4189 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4190 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4191 NOP_OUT_TIMEOUT);
4192
4193 if (!err || err == -ETIMEDOUT)
4194 break;
4195
4196 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4197 }
4198 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4199 ufshcd_release(hba);
5a0b0cb9
SRT
4200
4201 if (err)
4202 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4203 return err;
4204}
4205
0ce147d4
SJ
4206/**
4207 * ufshcd_set_queue_depth - set lun queue depth
4208 * @sdev: pointer to SCSI device
4209 *
4210 * Read bLUQueueDepth value and activate scsi tagged command
4211 * queueing. For WLUN, queue depth is set to 1. For best-effort
4212 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4213 * value that host can queue.
4214 */
4215static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4216{
4217 int ret = 0;
4218 u8 lun_qdepth;
4219 struct ufs_hba *hba;
4220
4221 hba = shost_priv(sdev->host);
4222
4223 lun_qdepth = hba->nutrs;
dbd34a61
SM
4224 ret = ufshcd_read_unit_desc_param(hba,
4225 ufshcd_scsi_to_upiu_lun(sdev->lun),
4226 UNIT_DESC_PARAM_LU_Q_DEPTH,
4227 &lun_qdepth,
4228 sizeof(lun_qdepth));
0ce147d4
SJ
4229
4230 /* Some WLUN doesn't support unit descriptor */
4231 if (ret == -EOPNOTSUPP)
4232 lun_qdepth = 1;
4233 else if (!lun_qdepth)
4234 /* eventually, we can figure out the real queue depth */
4235 lun_qdepth = hba->nutrs;
4236 else
4237 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4238
4239 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4240 __func__, lun_qdepth);
db5ed4df 4241 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ
4242}
4243
57d104c1
SJ
4244/*
4245 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4246 * @hba: per-adapter instance
4247 * @lun: UFS device lun id
4248 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4249 *
4250 * Returns 0 in case of success and b_lu_write_protect status would be returned
4251 * @b_lu_write_protect parameter.
4252 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4253 * Returns -EINVAL in case of invalid parameters passed to this function.
4254 */
4255static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4256 u8 lun,
4257 u8 *b_lu_write_protect)
4258{
4259 int ret;
4260
4261 if (!b_lu_write_protect)
4262 ret = -EINVAL;
4263 /*
4264 * According to UFS device spec, RPMB LU can't be write
4265 * protected so skip reading bLUWriteProtect parameter for
4266 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4267 */
4268 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4269 ret = -ENOTSUPP;
4270 else
4271 ret = ufshcd_read_unit_desc_param(hba,
4272 lun,
4273 UNIT_DESC_PARAM_LU_WR_PROTECT,
4274 b_lu_write_protect,
4275 sizeof(*b_lu_write_protect));
4276 return ret;
4277}
4278
4279/**
4280 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4281 * status
4282 * @hba: per-adapter instance
4283 * @sdev: pointer to SCSI device
4284 *
4285 */
4286static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4287 struct scsi_device *sdev)
4288{
4289 if (hba->dev_info.f_power_on_wp_en &&
4290 !hba->dev_info.is_lu_power_on_wp) {
4291 u8 b_lu_write_protect;
4292
4293 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4294 &b_lu_write_protect) &&
4295 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4296 hba->dev_info.is_lu_power_on_wp = true;
4297 }
4298}
4299
7a3e97b0
SY
4300/**
4301 * ufshcd_slave_alloc - handle initial SCSI device configurations
4302 * @sdev: pointer to SCSI device
4303 *
4304 * Returns success
4305 */
4306static int ufshcd_slave_alloc(struct scsi_device *sdev)
4307{
4308 struct ufs_hba *hba;
4309
4310 hba = shost_priv(sdev->host);
7a3e97b0
SY
4311
4312 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4313 sdev->use_10_for_ms = 1;
7a3e97b0 4314
e8e7f271
SRT
4315 /* allow SCSI layer to restart the device in case of errors */
4316 sdev->allow_restart = 1;
4264fd61 4317
b2a6c522
SRT
4318 /* REPORT SUPPORTED OPERATION CODES is not supported */
4319 sdev->no_report_opcodes = 1;
4320
e8e7f271 4321
0ce147d4 4322 ufshcd_set_queue_depth(sdev);
4264fd61 4323
57d104c1
SJ
4324 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4325
7a3e97b0
SY
4326 return 0;
4327}
4328
4264fd61
SRT
4329/**
4330 * ufshcd_change_queue_depth - change queue depth
4331 * @sdev: pointer to SCSI device
4332 * @depth: required depth to set
4264fd61 4333 *
db5ed4df 4334 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4335 */
db5ed4df 4336static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT
4337{
4338 struct ufs_hba *hba = shost_priv(sdev->host);
4339
4340 if (depth > hba->nutrs)
4341 depth = hba->nutrs;
db5ed4df 4342 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT
4343}
4344
eeda4749
AM
4345/**
4346 * ufshcd_slave_configure - adjust SCSI device configurations
4347 * @sdev: pointer to SCSI device
4348 */
4349static int ufshcd_slave_configure(struct scsi_device *sdev)
4350{
4351 struct request_queue *q = sdev->request_queue;
4352
4353 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4354 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4355
4356 return 0;
4357}
4358
7a3e97b0
SY
4359/**
4360 * ufshcd_slave_destroy - remove SCSI device configurations
4361 * @sdev: pointer to SCSI device
4362 */
4363static void ufshcd_slave_destroy(struct scsi_device *sdev)
4364{
4365 struct ufs_hba *hba;
4366
4367 hba = shost_priv(sdev->host);
0ce147d4 4368 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM
4369 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4370 unsigned long flags;
4371
4372 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4373 hba->sdev_ufs_device = NULL;
7c48bfd0
AM
4374 spin_unlock_irqrestore(hba->host->host_lock, flags);
4375 }
7a3e97b0
SY
4376}
4377
4378/**
4379 * ufshcd_task_req_compl - handle task management request completion
4380 * @hba: per adapter instance
4381 * @index: index of the completed request
e2933132 4382 * @resp: task management service response
7a3e97b0 4383 *
e2933132 4384 * Returns non-zero value on error, zero on success
7a3e97b0 4385 */
e2933132 4386static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY
4387{
4388 struct utp_task_req_desc *task_req_descp;
4389 struct utp_upiu_task_rsp *task_rsp_upiup;
4390 unsigned long flags;
4391 int ocs_value;
4392 int task_result;
4393
4394 spin_lock_irqsave(hba->host->host_lock, flags);
4395
4396 /* Clear completed tasks from outstanding_tasks */
4397 __clear_bit(index, &hba->outstanding_tasks);
4398
4399 task_req_descp = hba->utmrdl_base_addr;
4400 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4401
4402 if (ocs_value == OCS_SUCCESS) {
4403 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4404 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK
4405 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4406 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT
4407 if (resp)
4408 *resp = (u8)task_result;
7a3e97b0 4409 } else {
e2933132
SRT
4410 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4411 __func__, ocs_value);
7a3e97b0
SY
4412 }
4413 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT
4414
4415 return ocs_value;
7a3e97b0
SY
4416}
4417
7a3e97b0
SY
4418/**
4419 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4420 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY
4421 * @scsi_status: SCSI command status
4422 *
4423 * Returns value base on SCSI command status
4424 */
4425static inline int
4426ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4427{
4428 int result = 0;
4429
4430 switch (scsi_status) {
7a3e97b0 4431 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ
4432 ufshcd_copy_sense_data(lrbp);
4433 case SAM_STAT_GOOD:
7a3e97b0
SY
4434 result |= DID_OK << 16 |
4435 COMMAND_COMPLETE << 8 |
1c2623c5 4436 scsi_status;
7a3e97b0
SY
4437 break;
4438 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4439 case SAM_STAT_BUSY:
7a3e97b0 4440 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ
4441 ufshcd_copy_sense_data(lrbp);
4442 result |= scsi_status;
7a3e97b0
SY
4443 break;
4444 default:
4445 result |= DID_ERROR << 16;
4446 break;
4447 } /* end of switch */
4448
4449 return result;
4450}
4451
4452/**
4453 * ufshcd_transfer_rsp_status - Get overall status of the response
4454 * @hba: per adapter instance
8aa29f19 4455 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY
4456 *
4457 * Returns result of the command to notify SCSI midlayer
4458 */
4459static inline int
4460ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4461{
4462 int result = 0;
4463 int scsi_status;
4464 int ocs;
4465
4466 /* overall command status of utrd */
4467 ocs = ufshcd_get_tr_ocs(lrbp);
4468
4469 switch (ocs) {
4470 case OCS_SUCCESS:
5a0b0cb9 4471 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4472 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT
4473 switch (result) {
4474 case UPIU_TRANSACTION_RESPONSE:
4475 /*
4476 * get the response UPIU result to extract
4477 * the SCSI command status
4478 */
4479 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4480
4481 /*
4482 * get the result based on SCSI status response
4483 * to notify the SCSI midlayer of the command status
4484 */
4485 scsi_status = result & MASK_SCSI_STATUS;
4486 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4487
f05ac2e5
YG
4488 /*
4489 * Currently we are only supporting BKOPs exception
4490 * events hence we can ignore BKOPs exception event
4491 * during power management callbacks. BKOPs exception
4492 * event is not expected to be raised in runtime suspend
4493 * callback as it allows the urgent bkops.
4494 * During system suspend, we are anyway forcefully
4495 * disabling the bkops and if urgent bkops is needed
4496 * it will be enabled on system resume. Long term
4497 * solution could be to abort the system suspend if
4498 * UFS device needs urgent BKOPs.
4499 */
4500 if (!hba->pm_op_in_progress &&
4501 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4502 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT
4503 break;
4504 case UPIU_TRANSACTION_REJECT_UPIU:
4505 /* TODO: handle Reject UPIU Response */
4506 result = DID_ERROR << 16;
3b1d0580 4507 dev_err(hba->dev,
5a0b0cb9
SRT
4508 "Reject UPIU not fully implemented\n");
4509 break;
4510 default:
4511 result = DID_ERROR << 16;
4512 dev_err(hba->dev,
4513 "Unexpected request response code = %x\n",
4514 result);
7a3e97b0
SY
4515 break;
4516 }
7a3e97b0
SY
4517 break;
4518 case OCS_ABORTED:
4519 result |= DID_ABORT << 16;
4520 break;
e8e7f271
SRT
4521 case OCS_INVALID_COMMAND_STATUS:
4522 result |= DID_REQUEUE << 16;
4523 break;
7a3e97b0
SY
4524 case OCS_INVALID_CMD_TABLE_ATTR:
4525 case OCS_INVALID_PRDT_ATTR:
4526 case OCS_MISMATCH_DATA_BUF_SIZE:
4527 case OCS_MISMATCH_RESP_UPIU_SIZE:
4528 case OCS_PEER_COMM_FAILURE:
4529 case OCS_FATAL_ERROR:
4530 default:
4531 result |= DID_ERROR << 16;
3b1d0580 4532 dev_err(hba->dev,
ff8e20c6
DR
4533 "OCS error from controller = %x for tag %d\n",
4534 ocs, lrbp->task_tag);
4535 ufshcd_print_host_regs(hba);
6ba65588 4536 ufshcd_print_host_state(hba);
7a3e97b0
SY
4537 break;
4538 } /* end of switch */
4539
66cc820f
DR
4540 if (host_byte(result) != DID_OK)
4541 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY
4542 return result;
4543}
4544
6ccf44fe
SJ
4545/**
4546 * ufshcd_uic_cmd_compl - handle completion of uic command
4547 * @hba: per adapter instance
53b3d9c3 4548 * @intr_status: interrupt status generated by the controller
6ccf44fe 4549 */
53b3d9c3 4550static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4551{
53b3d9c3 4552 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ
4553 hba->active_uic_cmd->argument2 |=
4554 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ
4555 hba->active_uic_cmd->argument3 =
4556 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ
4557 complete(&hba->active_uic_cmd->done);
4558 }
53b3d9c3 4559
57d104c1
SJ
4560 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4561 complete(hba->uic_async_done);
6ccf44fe
SJ
4562}
4563
7a3e97b0 4564/**
9a47ec7c 4565 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4566 * @hba: per adapter instance
9a47ec7c 4567 * @completed_reqs: requests to complete
7a3e97b0 4568 */
9a47ec7c
YG
4569static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4570 unsigned long completed_reqs)
7a3e97b0 4571{
5a0b0cb9
SRT
4572 struct ufshcd_lrb *lrbp;
4573 struct scsi_cmnd *cmd;
7a3e97b0
SY
4574 int result;
4575 int index;
e9d501b1 4576
e9d501b1
DR
4577 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4578 lrbp = &hba->lrb[index];
4579 cmd = lrbp->cmd;
4580 if (cmd) {
1a07f2d9 4581 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR
4582 result = ufshcd_transfer_rsp_status(hba, lrbp);
4583 scsi_dma_unmap(cmd);
4584 cmd->result = result;
4585 /* Mark completed command as NULL in LRB */
4586 lrbp->cmd = NULL;
4587 clear_bit_unlock(index, &hba->lrb_in_use);
4588 /* Do not touch lrbp after scsi done */
4589 cmd->scsi_done(cmd);
1ab27c9c 4590 __ufshcd_release(hba);
300bb13f
JP
4591 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4592 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS
4593 if (hba->dev_cmd.complete) {
4594 ufshcd_add_command_trace(hba, index,
4595 "dev_complete");
e9d501b1 4596 complete(hba->dev_cmd.complete);
1a07f2d9 4597 }
e9d501b1 4598 }
401f1e44 4599 if (ufshcd_is_clkscaling_supported(hba))
4600 hba->clk_scaling.active_reqs--;
09017188
ZL
4601
4602 lrbp->compl_time_stamp = ktime_get();
e9d501b1 4603 }
7a3e97b0
SY
4604
4605 /* clear corresponding bits of completed commands */
4606 hba->outstanding_reqs ^= completed_reqs;
4607
856b3483
ST
4608 ufshcd_clk_scaling_update_busy(hba);
4609
5a0b0cb9
SRT
4610 /* we might have free'd some tags above */
4611 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY
4612}
4613
9a47ec7c
YG
4614/**
4615 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4616 * @hba: per adapter instance
4617 */
4618static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4619{
4620 unsigned long completed_reqs;
4621 u32 tr_doorbell;
4622
4623 /* Resetting interrupt aggregation counters first and reading the
4624 * DOOR_BELL afterward allows us to handle all the completed requests.
4625 * In order to prevent other interrupts starvation the DB is read once
4626 * after reset. The down side of this solution is the possibility of
4627 * false interrupt if device completes another request after resetting
4628 * aggregation and before reading the DB.
4629 */
4630 if (ufshcd_is_intr_aggr_allowed(hba))
4631 ufshcd_reset_intr_aggr(hba);
4632
4633 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4634 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4635
4636 __ufshcd_transfer_req_compl(hba, completed_reqs);
4637}
4638
66ec6d59
SRT
4639/**
4640 * ufshcd_disable_ee - disable exception event
4641 * @hba: per-adapter instance
4642 * @mask: exception event to disable
4643 *
4644 * Disables exception event in the device so that the EVENT_ALERT
4645 * bit is not set.
4646 *
4647 * Returns zero on success, non-zero error value on failure.
4648 */
4649static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4650{
4651 int err = 0;
4652 u32 val;
4653
4654 if (!(hba->ee_ctrl_mask & mask))
4655 goto out;
4656
4657 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4658 val &= MASK_EE_STATUS;
5e86ae44 4659 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT
4660 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4661 if (!err)
4662 hba->ee_ctrl_mask &= ~mask;
4663out:
4664 return err;
4665}
4666
4667/**
4668 * ufshcd_enable_ee - enable exception event
4669 * @hba: per-adapter instance
4670 * @mask: exception event to enable
4671 *
4672 * Enable corresponding exception event in the device to allow
4673 * device to alert host in critical scenarios.
4674 *
4675 * Returns zero on success, non-zero error value on failure.
4676 */
4677static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4678{
4679 int err = 0;
4680 u32 val;
4681
4682 if (hba->ee_ctrl_mask & mask)
4683 goto out;
4684
4685 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4686 val &= MASK_EE_STATUS;
5e86ae44 4687 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT
4688 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4689 if (!err)
4690 hba->ee_ctrl_mask |= mask;
4691out:
4692 return err;
4693}
4694
4695/**
4696 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4697 * @hba: per-adapter instance
4698 *
4699 * Allow device to manage background operations on its own. Enabling
4700 * this might lead to inconsistent latencies during normal data transfers
4701 * as the device is allowed to manage its own way of handling background
4702 * operations.
4703 *
4704 * Returns zero on success, non-zero on failure.
4705 */
4706static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4707{
4708 int err = 0;
4709
4710 if (hba->auto_bkops_enabled)
4711 goto out;
4712
dc3c8d3a 4713 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT
4714 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4715 if (err) {
4716 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4717 __func__, err);
4718 goto out;
4719 }
4720
4721 hba->auto_bkops_enabled = true;
7ff5ab47 4722 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT
4723
4724 /* No need of URGENT_BKOPS exception from the device */
4725 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4726 if (err)
4727 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4728 __func__, err);
4729out:
4730 return err;
4731}
4732
4733/**
4734 * ufshcd_disable_auto_bkops - block device in doing background operations
4735 * @hba: per-adapter instance
4736 *
4737 * Disabling background operations improves command response latency but
4738 * has drawback of device moving into critical state where the device is
4739 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4740 * host is idle so that BKOPS are managed effectively without any negative
4741 * impacts.
4742 *
4743 * Returns zero on success, non-zero on failure.
4744 */
4745static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4746{
4747 int err = 0;
4748
4749 if (!hba->auto_bkops_enabled)
4750 goto out;
4751
4752 /*
4753 * If host assisted BKOPs is to be enabled, make sure
4754 * urgent bkops exception is allowed.
4755 */
4756 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4757 if (err) {
4758 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4759 __func__, err);
4760 goto out;
4761 }
4762
dc3c8d3a 4763 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT
4764 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4765 if (err) {
4766 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4767 __func__, err);
4768 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4769 goto out;
4770 }
4771
4772 hba->auto_bkops_enabled = false;
7ff5ab47 4773 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT
4774out:
4775 return err;
4776}
4777
4778/**
4e768e76 4779 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT
4780 * @hba: per adapter instance
4781 *
4782 * After a device reset the device may toggle the BKOPS_EN flag
4783 * to default value. The s/w tracking variables should be updated
4e768e76 4784 * as well. This function would change the auto-bkops state based on
4785 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4786 */
4e768e76 4787static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4788{
4e768e76 4789 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4790 hba->auto_bkops_enabled = false;
4791 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4792 ufshcd_enable_auto_bkops(hba);
4793 } else {
4794 hba->auto_bkops_enabled = true;
4795 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4796 ufshcd_disable_auto_bkops(hba);
4797 }
66ec6d59
SRT
4798}
4799
4800static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4801{
5e86ae44 4802 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT
4803 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4804}
4805
4806/**
57d104c1 4807 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4808 * @hba: per-adapter instance
57d104c1 4809 * @status: bkops_status value
66ec6d59 4810 *
57d104c1
SJ
4811 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4812 * flag in the device to permit background operations if the device
4813 * bkops_status is greater than or equal to "status" argument passed to
4814 * this function, disable otherwise.
4815 *
4816 * Returns 0 for success, non-zero in case of failure.
4817 *
4818 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4819 * to know whether auto bkops is enabled or disabled after this function
4820 * returns control to it.
66ec6d59 4821 */
57d104c1
SJ
4822static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4823 enum bkops_status status)
66ec6d59
SRT
4824{
4825 int err;
57d104c1 4826 u32 curr_status = 0;
66ec6d59 4827
57d104c1 4828 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT
4829 if (err) {
4830 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4831 __func__, err);
4832 goto out;
57d104c1
SJ
4833 } else if (curr_status > BKOPS_STATUS_MAX) {
4834 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4835 __func__, curr_status);
4836 err = -EINVAL;
4837 goto out;
66ec6d59
SRT
4838 }
4839
57d104c1 4840 if (curr_status >= status)
66ec6d59 4841 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ
4842 else
4843 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT
4844out:
4845 return err;
4846}
4847
57d104c1
SJ
4848/**
4849 * ufshcd_urgent_bkops - handle urgent bkops exception event
4850 * @hba: per-adapter instance
4851 *
4852 * Enable fBackgroundOpsEn flag in the device to permit background
4853 * operations.
4854 *
4855 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4856 * and negative error value for any other failure.
4857 */
4858static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4859{
afdfff59 4860 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ
4861}
4862
66ec6d59
SRT
4863static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4864{
5e86ae44 4865 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT
4866 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4867}
4868
afdfff59
YG
4869static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4870{
4871 int err;
4872 u32 curr_status = 0;
4873
4874 if (hba->is_urgent_bkops_lvl_checked)
4875 goto enable_auto_bkops;
4876
4877 err = ufshcd_get_bkops_status(hba, &curr_status);
4878 if (err) {
4879 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4880 __func__, err);
4881 goto out;
4882 }
4883
4884 /*
4885 * We are seeing that some devices are raising the urgent bkops
4886 * exception events even when BKOPS status doesn't indicate performace
4887 * impacted or critical. Handle these device by determining their urgent
4888 * bkops status at runtime.
4889 */
4890 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4891 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4892 __func__, curr_status);
4893 /* update the current status as the urgent bkops level */
4894 hba->urgent_bkops_lvl = curr_status;
4895 hba->is_urgent_bkops_lvl_checked = true;
4896 }
4897
4898enable_auto_bkops:
4899 err = ufshcd_enable_auto_bkops(hba);
4900out:
4901 if (err < 0)
4902 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4903 __func__, err);
4904}
4905
66ec6d59
SRT
4906/**
4907 * ufshcd_exception_event_handler - handle exceptions raised by device
4908 * @work: pointer to work data
4909 *
4910 * Read bExceptionEventStatus attribute from the device and handle the
4911 * exception event accordingly.
4912 */
4913static void ufshcd_exception_event_handler(struct work_struct *work)
4914{
4915 struct ufs_hba *hba;
4916 int err;
4917 u32 status = 0;
4918 hba = container_of(work, struct ufs_hba, eeh_work);
4919
62694735 4920 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT
4921 err = ufshcd_get_ee_status(hba, &status);
4922 if (err) {
4923 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4924 __func__, err);
4925 goto out;
4926 }
4927
4928 status &= hba->ee_ctrl_mask;
afdfff59
YG
4929
4930 if (status & MASK_EE_URGENT_BKOPS)
4931 ufshcd_bkops_exception_event_handler(hba);
4932
66ec6d59 4933out:
62694735 4934 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT
4935 return;
4936}
4937
9a47ec7c
YG
4938/* Complete requests that have door-bell cleared */
4939static void ufshcd_complete_requests(struct ufs_hba *hba)
4940{
4941 ufshcd_transfer_req_compl(hba);
4942 ufshcd_tmc_handler(hba);
4943}
4944
583fa62d
YG
4945/**
4946 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4947 * to recover from the DL NAC errors or not.
4948 * @hba: per-adapter instance
4949 *
4950 * Returns true if error handling is required, false otherwise
4951 */
4952static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4953{
4954 unsigned long flags;
4955 bool err_handling = true;
4956
4957 spin_lock_irqsave(hba->host->host_lock, flags);
4958 /*
4959 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4960 * device fatal error and/or DL NAC & REPLAY timeout errors.
4961 */
4962 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4963 goto out;
4964
4965 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4966 ((hba->saved_err & UIC_ERROR) &&
4967 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4968 goto out;
4969
4970 if ((hba->saved_err & UIC_ERROR) &&
4971 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4972 int err;
4973 /*
4974 * wait for 50ms to see if we can get any other errors or not.
4975 */
4976 spin_unlock_irqrestore(hba->host->host_lock, flags);
4977 msleep(50);
4978 spin_lock_irqsave(hba->host->host_lock, flags);
4979
4980 /*
4981 * now check if we have got any other severe errors other than
4982 * DL NAC error?
4983 */
4984 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4985 ((hba->saved_err & UIC_ERROR) &&
4986 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4987 goto out;
4988
4989 /*
4990 * As DL NAC is the only error received so far, send out NOP
4991 * command to confirm if link is still active or not.
4992 * - If we don't get any response then do error recovery.
4993 * - If we get response then clear the DL NAC error bit.
4994 */
4995
4996 spin_unlock_irqrestore(hba->host->host_lock, flags);
4997 err = ufshcd_verify_dev_init(hba);
4998 spin_lock_irqsave(hba->host->host_lock, flags);
4999
5000 if (err)
5001 goto out;
5002
5003 /* Link seems to be alive hence ignore the DL NAC errors */
5004 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5005 hba->saved_err &= ~UIC_ERROR;
5006 /* clear NAC error */
5007 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5008 if (!hba->saved_uic_err) {
5009 err_handling = false;
5010 goto out;
5011 }
5012 }
5013out:
5014 spin_unlock_irqrestore(hba->host->host_lock, flags);
5015 return err_handling;
5016}
5017
7a3e97b0 5018/**
e8e7f271
SRT
5019 * ufshcd_err_handler - handle UFS errors that require s/w attention
5020 * @work: pointer to work structure
7a3e97b0 5021 */
e8e7f271 5022static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY
5023{
5024 struct ufs_hba *hba;
e8e7f271
SRT
5025 unsigned long flags;
5026 u32 err_xfer = 0;
5027 u32 err_tm = 0;
5028 int err = 0;
5029 int tag;
9a47ec7c 5030 bool needs_reset = false;
e8e7f271
SRT
5031
5032 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5033
62694735 5034 pm_runtime_get_sync(hba->dev);
1ab27c9c 5035 ufshcd_hold(hba, false);
e8e7f271
SRT
5036
5037 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5038 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5039 goto out;
e8e7f271
SRT
5040
5041 hba->ufshcd_state = UFSHCD_STATE_RESET;
5042 ufshcd_set_eh_in_progress(hba);
5043
5044 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5045 ufshcd_complete_requests(hba);
583fa62d
YG
5046
5047 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5048 bool ret;
5049
5050 spin_unlock_irqrestore(hba->host->host_lock, flags);
5051 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5052 ret = ufshcd_quirk_dl_nac_errors(hba);
5053 spin_lock_irqsave(hba->host->host_lock, flags);
5054 if (!ret)
5055 goto skip_err_handling;
5056 }
9a47ec7c
YG
5057 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5058 ((hba->saved_err & UIC_ERROR) &&
5059 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5060 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5061 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5062 needs_reset = true;
e8e7f271 5063
9a47ec7c
YG
5064 /*
5065 * if host reset is required then skip clearing the pending
5066 * transfers forcefully because they will automatically get
5067 * cleared after link startup.
5068 */
5069 if (needs_reset)
5070 goto skip_pending_xfer_clear;
5071
5072 /* release lock as clear command might sleep */
5073 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5074 /* Clear pending transfer requests */
9a47ec7c
YG
5075 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5076 if (ufshcd_clear_cmd(hba, tag)) {
5077 err_xfer = true;
5078 goto lock_skip_pending_xfer_clear;
5079 }
5080 }
e8e7f271
SRT
5081
5082 /* Clear pending task management requests */
9a47ec7c
YG
5083 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5084 if (ufshcd_clear_tm_cmd(hba, tag)) {
5085 err_tm = true;
5086 goto lock_skip_pending_xfer_clear;
5087 }
5088 }
e8e7f271 5089
9a47ec7c 5090lock_skip_pending_xfer_clear:
e8e7f271 5091 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5092
9a47ec7c
YG
5093 /* Complete the requests that are cleared by s/w */
5094 ufshcd_complete_requests(hba);
5095
5096 if (err_xfer || err_tm)
5097 needs_reset = true;
5098
5099skip_pending_xfer_clear:
e8e7f271 5100 /* Fatal errors need reset */
9a47ec7c
YG
5101 if (needs_reset) {
5102 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5103
5104 /*
5105 * ufshcd_reset_and_restore() does the link reinitialization
5106 * which will need atleast one empty doorbell slot to send the
5107 * device management commands (NOP and query commands).
5108 * If there is no slot empty at this moment then free up last
5109 * slot forcefully.
5110 */
5111 if (hba->outstanding_reqs == max_doorbells)
5112 __ufshcd_transfer_req_compl(hba,
5113 (1UL << (hba->nutrs - 1)));
5114
5115 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5116 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5117 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT
5118 if (err) {
5119 dev_err(hba->dev, "%s: reset and restore failed\n",
5120 __func__);
5121 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5122 }
5123 /*
5124 * Inform scsi mid-layer that we did reset and allow to handle
5125 * Unit Attention properly.
5126 */
5127 scsi_report_bus_reset(hba->host, 0);
5128 hba->saved_err = 0;
5129 hba->saved_uic_err = 0;
5130 }
9a47ec7c 5131
583fa62d 5132skip_err_handling:
9a47ec7c
YG
5133 if (!needs_reset) {
5134 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5135 if (hba->saved_err || hba->saved_uic_err)
5136 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5137 __func__, hba->saved_err, hba->saved_uic_err);
5138 }
5139
e8e7f271
SRT
5140 ufshcd_clear_eh_in_progress(hba);
5141
5142out:
9a47ec7c 5143 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5144 scsi_unblock_requests(hba->host);
1ab27c9c 5145 ufshcd_release(hba);
62694735 5146 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY
5147}
5148
ff8e20c6
DR
5149static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5150 u32 reg)
5151{
5152 reg_hist->reg[reg_hist->pos] = reg;
5153 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5154 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5155}
5156
7a3e97b0 5157/**
e8e7f271
SRT
5158 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5159 * @hba: per-adapter instance
7a3e97b0 5160 */
e8e7f271 5161static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY
5162{
5163 u32 reg;
5164
fb7b45f0
DR
5165 /* PHY layer lane error */
5166 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5167 /* Ignore LINERESET indication, as this is not an error */
5168 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5169 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR
5170 /*
5171 * To know whether this error is fatal or not, DB timeout
5172 * must be checked but this error is handled separately.
5173 */
5174 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR
5175 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5176 }
fb7b45f0 5177
e8e7f271
SRT
5178 /* PA_INIT_ERROR is fatal and needs UIC reset */
5179 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR
5180 if (reg)
5181 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5182
e8e7f271
SRT
5183 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5184 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG
5185 else if (hba->dev_quirks &
5186 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5187 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5188 hba->uic_error |=
5189 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5190 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5191 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5192 }
e8e7f271
SRT
5193
5194 /* UIC NL/TL/DME errors needs software retry */
5195 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR
5196 if (reg) {
5197 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5198 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5199 }
e8e7f271
SRT
5200
5201 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR
5202 if (reg) {
5203 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5204 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5205 }
e8e7f271
SRT
5206
5207 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR
5208 if (reg) {
5209 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5210 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5211 }
e8e7f271
SRT
5212
5213 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5214 __func__, hba->uic_error);
5215}
5216
5217/**
5218 * ufshcd_check_errors - Check for errors that need s/w attention
5219 * @hba: per-adapter instance
5220 */
5221static void ufshcd_check_errors(struct ufs_hba *hba)
5222{
5223 bool queue_eh_work = false;
5224
7a3e97b0 5225 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5226 queue_eh_work = true;
7a3e97b0
SY
5227
5228 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT
5229 hba->uic_error = 0;
5230 ufshcd_update_uic_error(hba);
5231 if (hba->uic_error)
5232 queue_eh_work = true;
7a3e97b0 5233 }
e8e7f271
SRT
5234
5235 if (queue_eh_work) {
9a47ec7c
YG
5236 /*
5237 * update the transfer error masks to sticky bits, let's do this
5238 * irrespective of current ufshcd_state.
5239 */
5240 hba->saved_err |= hba->errors;
5241 hba->saved_uic_err |= hba->uic_error;
5242
e8e7f271
SRT
5243 /* handle fatal errors only when link is functional */
5244 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5245 /* block commands from scsi mid-layer */
5246 scsi_block_requests(hba->host);
5247
141f8165 5248 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR
5249
5250 /* dump controller state before resetting */
5251 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5252 bool pr_prdt = !!(hba->saved_err &
5253 SYSTEM_BUS_FATAL_ERROR);
5254
5255 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5256 __func__, hba->saved_err,
5257 hba->saved_uic_err);
5258
5259 ufshcd_print_host_regs(hba);
5260 ufshcd_print_pwr_info(hba);
5261 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5262 ufshcd_print_trs(hba, hba->outstanding_reqs,
5263 pr_prdt);
5264 }
e8e7f271
SRT
5265 schedule_work(&hba->eh_work);
5266 }
3441da7d 5267 }
e8e7f271
SRT
5268 /*
5269 * if (!queue_eh_work) -
5270 * Other errors are either non-fatal where host recovers
5271 * itself without s/w intervention or errors that will be
5272 * handled by the SCSI core layer.
5273 */
7a3e97b0
SY
5274}
5275
5276/**
5277 * ufshcd_tmc_handler - handle task management function completion
5278 * @hba: per adapter instance
5279 */
5280static void ufshcd_tmc_handler(struct ufs_hba *hba)
5281{
5282 u32 tm_doorbell;
5283
b873a275 5284 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5285 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5286 wake_up(&hba->tm_wq);
7a3e97b0
SY
5287}
5288
5289/**
5290 * ufshcd_sl_intr - Interrupt service routine
5291 * @hba: per adapter instance
5292 * @intr_status: contains interrupts generated by the controller
5293 */
5294static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5295{
5296 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5297 if (hba->errors)
e8e7f271 5298 ufshcd_check_errors(hba);
7a3e97b0 5299
53b3d9c3
SJ
5300 if (intr_status & UFSHCD_UIC_MASK)
5301 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY
5302
5303 if (intr_status & UTP_TASK_REQ_COMPL)
5304 ufshcd_tmc_handler(hba);
5305
5306 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5307 ufshcd_transfer_req_compl(hba);
5308}
5309
5310/**
5311 * ufshcd_intr - Main interrupt service routine
5312 * @irq: irq number
5313 * @__hba: pointer to adapter instance
5314 *
5315 * Returns IRQ_HANDLED - If interrupt is valid
5316 * IRQ_NONE - If invalid interrupt
5317 */
5318static irqreturn_t ufshcd_intr(int irq, void *__hba)
5319{
d75f7fe4 5320 u32 intr_status, enabled_intr_status;
7a3e97b0
SY
5321 irqreturn_t retval = IRQ_NONE;
5322 struct ufs_hba *hba = __hba;
5323
5324 spin_lock(hba->host->host_lock);
b873a275 5325 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG
5326 enabled_intr_status =
5327 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5328
d75f7fe4 5329 if (intr_status)
261ea452 5330 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG
5331
5332 if (enabled_intr_status) {
5333 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY
5334 retval = IRQ_HANDLED;
5335 }
5336 spin_unlock(hba->host->host_lock);
5337 return retval;
5338}
5339
e2933132
SRT
5340static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5341{
5342 int err = 0;
5343 u32 mask = 1 << tag;
5344 unsigned long flags;
5345
5346 if (!test_bit(tag, &hba->outstanding_tasks))
5347 goto out;
5348
5349 spin_lock_irqsave(hba->host->host_lock, flags);
5350 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
5351 spin_unlock_irqrestore(hba->host->host_lock, flags);
5352
5353 /* poll for max. 1 sec to clear door bell register by h/w */
5354 err = ufshcd_wait_for_register(hba,
5355 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5356 mask, 0, 1000, 1000, true);
e2933132
SRT
5357out:
5358 return err;
5359}
5360
7a3e97b0
SY
5361/**
5362 * ufshcd_issue_tm_cmd - issues task management commands to controller
5363 * @hba: per adapter instance
e2933132
SRT
5364 * @lun_id: LUN ID to which TM command is sent
5365 * @task_id: task ID to which the TM command is applicable
5366 * @tm_function: task management function opcode
5367 * @tm_response: task management service response return value
7a3e97b0 5368 *
e2933132 5369 * Returns non-zero value on error, zero on success.
7a3e97b0 5370 */
e2933132
SRT
5371static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5372 u8 tm_function, u8 *tm_response)
7a3e97b0
SY
5373{
5374 struct utp_task_req_desc *task_req_descp;
5375 struct utp_upiu_task_req *task_req_upiup;
5376 struct Scsi_Host *host;
5377 unsigned long flags;
e2933132 5378 int free_slot;
7a3e97b0 5379 int err;
e2933132 5380 int task_tag;
7a3e97b0
SY
5381
5382 host = hba->host;
5383
e2933132
SRT
5384 /*
5385 * Get free slot, sleep if slots are unavailable.
5386 * Even though we use wait_event() which sleeps indefinitely,
5387 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5388 */
5389 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5390 ufshcd_hold(hba, false);
7a3e97b0 5391
e2933132 5392 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY
5393 task_req_descp = hba->utmrdl_base_addr;
5394 task_req_descp += free_slot;
5395
5396 /* Configure task request descriptor */
5397 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5398 task_req_descp->header.dword_2 =
5399 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5400
5401 /* Configure task request UPIU */
5402 task_req_upiup =
5403 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5404 task_tag = hba->nutrs + free_slot;
7a3e97b0 5405 task_req_upiup->header.dword_0 =
5a0b0cb9 5406 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5407 lun_id, task_tag);
7a3e97b0 5408 task_req_upiup->header.dword_1 =
5a0b0cb9 5409 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ
5410 /*
5411 * The host shall provide the same value for LUN field in the basic
5412 * header and for Input Parameter.
5413 */
e2933132
SRT
5414 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5415 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5416
d2877be4
KK
5417 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5418
7a3e97b0
SY
5419 /* send command to the controller */
5420 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG
5421
5422 /* Make sure descriptors are ready before ringing the task doorbell */
5423 wmb();
5424
b873a275 5425 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB
5426 /* Make sure that doorbell is committed immediately */
5427 wmb();
7a3e97b0
SY
5428
5429 spin_unlock_irqrestore(host->host_lock, flags);
5430
5431 /* wait until the task management command is completed */
e2933132
SRT
5432 err = wait_event_timeout(hba->tm_wq,
5433 test_bit(free_slot, &hba->tm_condition),
5434 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5435 if (!err) {
e2933132
SRT
5436 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5437 __func__, tm_function);
5438 if (ufshcd_clear_tm_cmd(hba, free_slot))
5439 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5440 __func__, free_slot);
5441 err = -ETIMEDOUT;
5442 } else {
5443 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5444 }
e2933132 5445
7a3e97b0 5446 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT
5447 ufshcd_put_tm_slot(hba, free_slot);
5448 wake_up(&hba->tm_tag_wq);
5449
1ab27c9c 5450 ufshcd_release(hba);
7a3e97b0
SY
5451 return err;
5452}
5453
5454/**
3441da7d
SRT
5455 * ufshcd_eh_device_reset_handler - device reset handler registered to
5456 * scsi layer.
7a3e97b0
SY
5457 * @cmd: SCSI command pointer
5458 *
5459 * Returns SUCCESS/FAILED
5460 */
3441da7d 5461static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY
5462{
5463 struct Scsi_Host *host;
5464 struct ufs_hba *hba;
5465 unsigned int tag;
5466 u32 pos;
5467 int err;
e2933132
SRT
5468 u8 resp = 0xF;
5469 struct ufshcd_lrb *lrbp;
3441da7d 5470 unsigned long flags;
7a3e97b0
SY
5471
5472 host = cmd->device->host;
5473 hba = shost_priv(host);
5474 tag = cmd->request->tag;
5475
e2933132
SRT
5476 lrbp = &hba->lrb[tag];
5477 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5478 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT
5479 if (!err)
5480 err = resp;
7a3e97b0 5481 goto out;
e2933132 5482 }
7a3e97b0 5483
3441da7d
SRT
5484 /* clear the commands that were pending for corresponding LUN */
5485 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5486 if (hba->lrb[pos].lun == lrbp->lun) {
5487 err = ufshcd_clear_cmd(hba, pos);
5488 if (err)
5489 break;
7a3e97b0 5490 }
3441da7d
SRT
5491 }
5492 spin_lock_irqsave(host->host_lock, flags);
5493 ufshcd_transfer_req_compl(hba);
5494 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5495
7a3e97b0 5496out:
7fabb77b 5497 hba->req_abort_count = 0;
3441da7d
SRT
5498 if (!err) {
5499 err = SUCCESS;
5500 } else {
5501 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5502 err = FAILED;
5503 }
7a3e97b0
SY
5504 return err;
5505}
5506
e0b299e3
GB
5507static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5508{
5509 struct ufshcd_lrb *lrbp;
5510 int tag;
5511
5512 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5513 lrbp = &hba->lrb[tag];
5514 lrbp->req_abort_skip = true;
5515 }
5516}
5517
7a3e97b0
SY
5518/**
5519 * ufshcd_abort - abort a specific command
5520 * @cmd: SCSI command pointer
5521 *
f20810d8
SRT
5522 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5523 * command, and in host controller by clearing the door-bell register. There can
5524 * be race between controller sending the command to the device while abort is
5525 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5526 * really issued and then try to abort it.
5527 *
7a3e97b0
SY
5528 * Returns SUCCESS/FAILED
5529 */
5530static int ufshcd_abort(struct scsi_cmnd *cmd)
5531{
5532 struct Scsi_Host *host;
5533 struct ufs_hba *hba;
5534 unsigned long flags;
5535 unsigned int tag;
f20810d8
SRT
5536 int err = 0;
5537 int poll_cnt;
e2933132
SRT
5538 u8 resp = 0xF;
5539 struct ufshcd_lrb *lrbp;
e9d501b1 5540 u32 reg;
7a3e97b0
SY
5541
5542 host = cmd->device->host;
5543 hba = shost_priv(host);
5544 tag = cmd->request->tag;
e7d38257 5545 lrbp = &hba->lrb[tag];
14497328
YG
5546 if (!ufshcd_valid_tag(hba, tag)) {
5547 dev_err(hba->dev,
5548 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5549 __func__, tag, cmd, cmd->request);
5550 BUG();
5551 }
7a3e97b0 5552
e7d38257
DR
5553 /*
5554 * Task abort to the device W-LUN is illegal. When this command
5555 * will fail, due to spec violation, scsi err handling next step
5556 * will be to send LU reset which, again, is a spec violation.
5557 * To avoid these unnecessary/illegal step we skip to the last error
5558 * handling stage: reset and restore.
5559 */
5560 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5561 return ufshcd_eh_host_reset_handler(cmd);
5562
1ab27c9c 5563 ufshcd_hold(hba, false);
14497328 5564 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5565 /* If command is already aborted/completed, return SUCCESS */
14497328
YG
5566 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5567 dev_err(hba->dev,
5568 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5569 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5570 goto out;
14497328 5571 }
7a3e97b0 5572
e9d501b1
DR
5573 if (!(reg & (1 << tag))) {
5574 dev_err(hba->dev,
5575 "%s: cmd was completed, but without a notifying intr, tag = %d",
5576 __func__, tag);
5577 }
5578
66cc820f
DR
5579 /* Print Transfer Request of aborted task */
5580 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5581
7fabb77b
GB
5582 /*
5583 * Print detailed info about aborted request.
5584 * As more than one request might get aborted at the same time,
5585 * print full information only for the first aborted request in order
5586 * to reduce repeated printouts. For other aborted requests only print
5587 * basic details.
5588 */
5589 scsi_print_command(hba->lrb[tag].cmd);
5590 if (!hba->req_abort_count) {
5591 ufshcd_print_host_regs(hba);
6ba65588 5592 ufshcd_print_host_state(hba);
7fabb77b
GB
5593 ufshcd_print_pwr_info(hba);
5594 ufshcd_print_trs(hba, 1 << tag, true);
5595 } else {
5596 ufshcd_print_trs(hba, 1 << tag, false);
5597 }
5598 hba->req_abort_count++;
e0b299e3
GB
5599
5600 /* Skip task abort in case previous aborts failed and report failure */
5601 if (lrbp->req_abort_skip) {
5602 err = -EIO;
5603 goto out;
5604 }
5605
f20810d8
SRT
5606 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5607 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5608 UFS_QUERY_TASK, &resp);
5609 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5610 /* cmd pending in the device */
ff8e20c6
DR
5611 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5612 __func__, tag);
f20810d8
SRT
5613 break;
5614 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT
5615 /*
5616 * cmd not pending in the device, check if it is
5617 * in transition.
5618 */
ff8e20c6
DR
5619 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5620 __func__, tag);
f20810d8
SRT
5621 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5622 if (reg & (1 << tag)) {
5623 /* sleep for max. 200us to stabilize */
5624 usleep_range(100, 200);
5625 continue;
5626 }
5627 /* command completed already */
ff8e20c6
DR
5628 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5629 __func__, tag);
f20810d8
SRT
5630 goto out;
5631 } else {
ff8e20c6
DR
5632 dev_err(hba->dev,
5633 "%s: no response from device. tag = %d, err %d\n",
5634 __func__, tag, err);
f20810d8
SRT
5635 if (!err)
5636 err = resp; /* service response error */
5637 goto out;
5638 }
5639 }
5640
5641 if (!poll_cnt) {
5642 err = -EBUSY;
7a3e97b0
SY
5643 goto out;
5644 }
7a3e97b0 5645
e2933132
SRT
5646 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5647 UFS_ABORT_TASK, &resp);
5648 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5649 if (!err) {
f20810d8 5650 err = resp; /* service response error */
ff8e20c6
DR
5651 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5652 __func__, tag, err);
5653 }
7a3e97b0 5654 goto out;
e2933132 5655 }
7a3e97b0 5656
f20810d8 5657 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR
5658 if (err) {
5659 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5660 __func__, tag, err);
f20810d8 5661 goto out;
ff8e20c6 5662 }
f20810d8 5663
7a3e97b0
SY
5664 scsi_dma_unmap(cmd);
5665
5666 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5667 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY
5668 hba->lrb[tag].cmd = NULL;
5669 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT
5670
5671 clear_bit_unlock(tag, &hba->lrb_in_use);
5672 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5673
7a3e97b0 5674out:
f20810d8
SRT
5675 if (!err) {
5676 err = SUCCESS;
5677 } else {
5678 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5679 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT
5680 err = FAILED;
5681 }
5682
1ab27c9c
ST
5683 /*
5684 * This ufshcd_release() corresponds to the original scsi cmd that got
5685 * aborted here (as we won't get any IRQ for it).
5686 */
5687 ufshcd_release(hba);
7a3e97b0
SY
5688 return err;
5689}
5690
3441da7d
SRT
5691/**
5692 * ufshcd_host_reset_and_restore - reset and restore host controller
5693 * @hba: per-adapter instance
5694 *
5695 * Note that host controller reset may issue DME_RESET to
5696 * local and remote (device) Uni-Pro stack and the attributes
5697 * are reset to default state.
5698 *
5699 * Returns zero on success, non-zero on failure
5700 */
5701static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5702{
5703 int err;
3441da7d
SRT
5704 unsigned long flags;
5705
5706 /* Reset the host controller */
5707 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5708 ufshcd_hba_stop(hba, false);
3441da7d
SRT
5709 spin_unlock_irqrestore(hba->host->host_lock, flags);
5710
a3cd5ec5 5711 /* scale up clocks to max frequency before full reinitialization */
5712 ufshcd_scale_clks(hba, true);
5713
3441da7d
SRT
5714 err = ufshcd_hba_enable(hba);
5715 if (err)
5716 goto out;
5717
5718 /* Establish the link again and restore the device */
1d337ec2
SRT
5719 err = ufshcd_probe_hba(hba);
5720
5721 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT
5722 err = -EIO;
5723out:
5724 if (err)
5725 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5726
5727 return err;
5728}
5729
5730/**
5731 * ufshcd_reset_and_restore - reset and re-initialize host/device
5732 * @hba: per-adapter instance
5733 *
5734 * Reset and recover device, host and re-establish link. This
5735 * is helpful to recover the communication in fatal error conditions.
5736 *
5737 * Returns zero on success, non-zero on failure
5738 */
5739static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5740{
5741 int err = 0;
5742 unsigned long flags;
1d337ec2 5743 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5744
1d337ec2
SRT
5745 do {
5746 err = ufshcd_host_reset_and_restore(hba);
5747 } while (err && --retries);
3441da7d
SRT
5748
5749 /*
5750 * After reset the door-bell might be cleared, complete
5751 * outstanding requests in s/w here.
5752 */
5753 spin_lock_irqsave(hba->host->host_lock, flags);
5754 ufshcd_transfer_req_compl(hba);
5755 ufshcd_tmc_handler(hba);
5756 spin_unlock_irqrestore(hba->host->host_lock, flags);
5757
5758 return err;
5759}
5760
5761/**
5762 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 5763 * @cmd: SCSI command pointer
3441da7d
SRT
5764 *
5765 * Returns SUCCESS/FAILED
5766 */
5767static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5768{
5769 int err;
5770 unsigned long flags;
5771 struct ufs_hba *hba;
5772
5773 hba = shost_priv(cmd->device->host);
5774
1ab27c9c 5775 ufshcd_hold(hba, false);
3441da7d
SRT
5776 /*
5777 * Check if there is any race with fatal error handling.
5778 * If so, wait for it to complete. Even though fatal error
5779 * handling does reset and restore in some cases, don't assume
5780 * anything out of it. We are just avoiding race here.
5781 */
5782 do {
5783 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5784 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL
5785 hba->ufshcd_state == UFSHCD_STATE_RESET ||
5786 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT
5787 break;
5788 spin_unlock_irqrestore(hba->host->host_lock, flags);
5789 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 5790 flush_work(&hba->eh_work);
3441da7d
SRT
5791 } while (1);
5792
5793 hba->ufshcd_state = UFSHCD_STATE_RESET;
5794 ufshcd_set_eh_in_progress(hba);
5795 spin_unlock_irqrestore(hba->host->host_lock, flags);
5796
5797 err = ufshcd_reset_and_restore(hba);
5798
5799 spin_lock_irqsave(hba->host->host_lock, flags);
5800 if (!err) {
5801 err = SUCCESS;
5802 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5803 } else {
5804 err = FAILED;
5805 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5806 }
5807 ufshcd_clear_eh_in_progress(hba);
5808 spin_unlock_irqrestore(hba->host->host_lock, flags);
5809
1ab27c9c 5810 ufshcd_release(hba);
3441da7d
SRT
5811 return err;
5812}
5813
3a4bf06d
YG
5814/**
5815 * ufshcd_get_max_icc_level - calculate the ICC level
5816 * @sup_curr_uA: max. current supported by the regulator
5817 * @start_scan: row at the desc table to start scan from
5818 * @buff: power descriptor buffer
5819 *
5820 * Returns calculated max ICC level for specific regulator
5821 */
5822static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5823{
5824 int i;
5825 int curr_uA;
5826 u16 data;
5827 u16 unit;
5828
5829 for (i = start_scan; i >= 0; i--) {
d79713f9 5830 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG
5831 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5832 ATTR_ICC_LVL_UNIT_OFFSET;
5833 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5834 switch (unit) {
5835 case UFSHCD_NANO_AMP:
5836 curr_uA = curr_uA / 1000;
5837 break;
5838 case UFSHCD_MILI_AMP:
5839 curr_uA = curr_uA * 1000;
5840 break;
5841 case UFSHCD_AMP:
5842 curr_uA = curr_uA * 1000 * 1000;
5843 break;
5844 case UFSHCD_MICRO_AMP:
5845 default:
5846 break;
5847 }
5848 if (sup_curr_uA >= curr_uA)
5849 break;
5850 }
5851 if (i < 0) {
5852 i = 0;
5853 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5854 }
5855
5856 return (u32)i;
5857}
5858
5859/**
5860 * ufshcd_calc_icc_level - calculate the max ICC level
5861 * In case regulators are not initialized we'll return 0
5862 * @hba: per-adapter instance
5863 * @desc_buf: power descriptor buffer to extract ICC levels from.
5864 * @len: length of desc_buff
5865 *
5866 * Returns calculated ICC level
5867 */
5868static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5869 u8 *desc_buf, int len)
5870{
5871 u32 icc_level = 0;
5872
5873 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5874 !hba->vreg_info.vccq2) {
5875 dev_err(hba->dev,
5876 "%s: Regulator capability was not set, actvIccLevel=%d",
5877 __func__, icc_level);
5878 goto out;
5879 }
5880
5881 if (hba->vreg_info.vcc)
5882 icc_level = ufshcd_get_max_icc_level(
5883 hba->vreg_info.vcc->max_uA,
5884 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5885 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5886
5887 if (hba->vreg_info.vccq)
5888 icc_level = ufshcd_get_max_icc_level(
5889 hba->vreg_info.vccq->max_uA,
5890 icc_level,
5891 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5892
5893 if (hba->vreg_info.vccq2)
5894 icc_level = ufshcd_get_max_icc_level(
5895 hba->vreg_info.vccq2->max_uA,
5896 icc_level,
5897 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5898out:
5899 return icc_level;
5900}
5901
5902static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5903{
5904 int ret;
a4b0e8a4
PM
5905 int buff_len = hba->desc_size.pwr_desc;
5906 u8 desc_buf[hba->desc_size.pwr_desc];
3a4bf06d
YG
5907
5908 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5909 if (ret) {
5910 dev_err(hba->dev,
5911 "%s: Failed reading power descriptor.len = %d ret = %d",
5912 __func__, buff_len, ret);
5913 return;
5914 }
5915
5916 hba->init_prefetch_data.icc_level =
5917 ufshcd_find_max_sup_active_icc_level(hba,
5918 desc_buf, buff_len);
5919 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5920 __func__, hba->init_prefetch_data.icc_level);
5921
dbd34a61
SM
5922 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5923 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
5924 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG
5925
5926 if (ret)
5927 dev_err(hba->dev,
5928 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5929 __func__, hba->init_prefetch_data.icc_level , ret);
5930
5931}
5932
2a8fa600
SJ
5933/**
5934 * ufshcd_scsi_add_wlus - Adds required W-LUs
5935 * @hba: per-adapter instance
5936 *
5937 * UFS device specification requires the UFS devices to support 4 well known
5938 * logical units:
5939 * "REPORT_LUNS" (address: 01h)
5940 * "UFS Device" (address: 50h)
5941 * "RPMB" (address: 44h)
5942 * "BOOT" (address: 30h)
5943 * UFS device's power management needs to be controlled by "POWER CONDITION"
5944 * field of SSU (START STOP UNIT) command. But this "power condition" field
5945 * will take effect only when its sent to "UFS device" well known logical unit
5946 * hence we require the scsi_device instance to represent this logical unit in
5947 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 5948 *
2a8fa600
SJ
5949 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5950 * Block) LU so user space process can control this LU. User space may also
5951 * want to have access to BOOT LU.
8aa29f19 5952 *
2a8fa600
SJ
5953 * This function adds scsi device instances for each of all well known LUs
5954 * (except "REPORT LUNS" LU).
5955 *
5956 * Returns zero on success (all required W-LUs are added successfully),
5957 * non-zero error value on failure (if failed to add any of the required W-LU).
5958 */
5959static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5960{
5961 int ret = 0;
7c48bfd0
AM
5962 struct scsi_device *sdev_rpmb;
5963 struct scsi_device *sdev_boot;
2a8fa600
SJ
5964
5965 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5966 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5967 if (IS_ERR(hba->sdev_ufs_device)) {
5968 ret = PTR_ERR(hba->sdev_ufs_device);
5969 hba->sdev_ufs_device = NULL;
5970 goto out;
5971 }
7c48bfd0 5972 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 5973
7c48bfd0 5974 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5975 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM
5976 if (IS_ERR(sdev_rpmb)) {
5977 ret = PTR_ERR(sdev_rpmb);
3d21fbde 5978 goto remove_sdev_ufs_device;
2a8fa600 5979 }
7c48bfd0 5980 scsi_device_put(sdev_rpmb);
3d21fbde
HK
5981
5982 sdev_boot = __scsi_add_device(hba->host, 0, 0,
5983 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
5984 if (IS_ERR(sdev_boot))
5985 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
5986 else
5987 scsi_device_put(sdev_boot);
2a8fa600
SJ
5988 goto out;
5989
2a8fa600
SJ
5990remove_sdev_ufs_device:
5991 scsi_remove_device(hba->sdev_ufs_device);
5992out:
5993 return ret;
5994}
5995
93fdd5ac
TW
5996static int ufs_get_device_desc(struct ufs_hba *hba,
5997 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG
5998{
5999 int err;
6000 u8 model_index;
a4b0e8a4
PM
6001 u8 str_desc_buf[QUERY_DESC_MAX_SIZE + 1] = {0};
6002 u8 desc_buf[hba->desc_size.dev_desc];
c58ab7aa 6003
a4b0e8a4 6004 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG
6005 if (err) {
6006 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6007 __func__, err);
6008 goto out;
6009 }
6010
6011 /*
6012 * getting vendor (manufacturerID) and Bank Index in big endian
6013 * format
6014 */
93fdd5ac 6015 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG
6016 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6017
6018 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6019
6020 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
8aa29f19 6021 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
c58ab7aa
YG
6022 if (err) {
6023 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6024 __func__, err);
6025 goto out;
6026 }
6027
a4b0e8a4 6028 str_desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
93fdd5ac 6029 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG
6030 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6031 MAX_MODEL_LEN));
6032
6033 /* Null terminate the model string */
93fdd5ac 6034 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG
6035
6036out:
6037 return err;
6038}
6039
93fdd5ac
TW
6040static void ufs_fixup_device_setup(struct ufs_hba *hba,
6041 struct ufs_dev_desc *dev_desc)
c58ab7aa 6042{
c58ab7aa 6043 struct ufs_dev_fix *f;
c58ab7aa
YG
6044
6045 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW
6046 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6047 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6048 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG
6049 !strcmp(f->card.model, UFS_ANY_MODEL)))
6050 hba->dev_quirks |= f->quirk;
6051 }
6052}
6053
37113106
YG
6054/**
6055 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6056 * @hba: per-adapter instance
6057 *
6058 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6059 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6060 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6061 * the hibern8 exit latency.
6062 *
6063 * Returns zero on success, non-zero error value on failure.
6064 */
6065static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6066{
6067 int ret = 0;
6068 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6069
6070 ret = ufshcd_dme_peer_get(hba,
6071 UIC_ARG_MIB_SEL(
6072 RX_MIN_ACTIVATETIME_CAPABILITY,
6073 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6074 &peer_rx_min_activatetime);
6075 if (ret)
6076 goto out;
6077
6078 /* make sure proper unit conversion is applied */
6079 tuned_pa_tactivate =
6080 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6081 / PA_TACTIVATE_TIME_UNIT_US);
6082 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6083 tuned_pa_tactivate);
6084
6085out:
6086 return ret;
6087}
6088
6089/**
6090 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6091 * @hba: per-adapter instance
6092 *
6093 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6094 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6095 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6096 * This optimal value can help reduce the hibern8 exit latency.
6097 *
6098 * Returns zero on success, non-zero error value on failure.
6099 */
6100static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6101{
6102 int ret = 0;
6103 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6104 u32 max_hibern8_time, tuned_pa_hibern8time;
6105
6106 ret = ufshcd_dme_get(hba,
6107 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6108 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6109 &local_tx_hibern8_time_cap);
6110 if (ret)
6111 goto out;
6112
6113 ret = ufshcd_dme_peer_get(hba,
6114 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6115 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6116 &peer_rx_hibern8_time_cap);
6117 if (ret)
6118 goto out;
6119
6120 max_hibern8_time = max(local_tx_hibern8_time_cap,
6121 peer_rx_hibern8_time_cap);
6122 /* make sure proper unit conversion is applied */
6123 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6124 / PA_HIBERN8_TIME_UNIT_US);
6125 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6126 tuned_pa_hibern8time);
6127out:
6128 return ret;
6129}
6130
c6a6db43 6131/**
6132 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6133 * less than device PA_TACTIVATE time.
6134 * @hba: per-adapter instance
6135 *
6136 * Some UFS devices require host PA_TACTIVATE to be lower than device
6137 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6138 * for such devices.
6139 *
6140 * Returns zero on success, non-zero error value on failure.
6141 */
6142static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6143{
6144 int ret = 0;
6145 u32 granularity, peer_granularity;
6146 u32 pa_tactivate, peer_pa_tactivate;
6147 u32 pa_tactivate_us, peer_pa_tactivate_us;
6148 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6149
6150 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6151 &granularity);
6152 if (ret)
6153 goto out;
6154
6155 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6156 &peer_granularity);
6157 if (ret)
6158 goto out;
6159
6160 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6161 (granularity > PA_GRANULARITY_MAX_VAL)) {
6162 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6163 __func__, granularity);
6164 return -EINVAL;
6165 }
6166
6167 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6168 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6169 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6170 __func__, peer_granularity);
6171 return -EINVAL;
6172 }
6173
6174 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6175 if (ret)
6176 goto out;
6177
6178 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6179 &peer_pa_tactivate);
6180 if (ret)
6181 goto out;
6182
6183 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6184 peer_pa_tactivate_us = peer_pa_tactivate *
6185 gran_to_us_table[peer_granularity - 1];
6186
6187 if (pa_tactivate_us > peer_pa_tactivate_us) {
6188 u32 new_peer_pa_tactivate;
6189
6190 new_peer_pa_tactivate = pa_tactivate_us /
6191 gran_to_us_table[peer_granularity - 1];
6192 new_peer_pa_tactivate++;
6193 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6194 new_peer_pa_tactivate);
6195 }
6196
6197out:
6198 return ret;
6199}
6200
37113106
YG
6201static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6202{
6203 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6204 ufshcd_tune_pa_tactivate(hba);
6205 ufshcd_tune_pa_hibern8time(hba);
6206 }
6207
6208 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6209 /* set 1ms timeout for PA_TACTIVATE */
6210 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 6211
6212 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6213 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ
6214
6215 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG
6216}
6217
ff8e20c6
DR
6218static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6219{
6220 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6221
6222 hba->ufs_stats.hibern8_exit_cnt = 0;
6223 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6224
6225 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6226 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6227 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6228 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6229 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB
6230
6231 hba->req_abort_count = 0;
ff8e20c6
DR
6232}
6233
a4b0e8a4
PM
6234static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6235{
6236 int err;
6237
6238 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6239 &hba->desc_size.dev_desc);
6240 if (err)
6241 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6242
6243 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6244 &hba->desc_size.pwr_desc);
6245 if (err)
6246 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6247
6248 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6249 &hba->desc_size.interc_desc);
6250 if (err)
6251 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6252
6253 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6254 &hba->desc_size.conf_desc);
6255 if (err)
6256 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6257
6258 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6259 &hba->desc_size.unit_desc);
6260 if (err)
6261 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6262
6263 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6264 &hba->desc_size.geom_desc);
6265 if (err)
6266 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2
SN
6267 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6268 &hba->desc_size.hlth_desc);
6269 if (err)
6270 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM
6271}
6272
6273static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6274{
6275 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6276 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6277 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6278 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6279 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6280 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2 6281 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM
6282}
6283
6ccf44fe 6284/**
1d337ec2
SRT
6285 * ufshcd_probe_hba - probe hba to detect device and initialize
6286 * @hba: per-adapter instance
6287 *
6288 * Execute link-startup and verify device initialization
6ccf44fe 6289 */
1d337ec2 6290static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6291{
93fdd5ac 6292 struct ufs_dev_desc card = {0};
6ccf44fe 6293 int ret;
7ff5ab47 6294 ktime_t start = ktime_get();
6ccf44fe
SJ
6295
6296 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT
6297 if (ret)
6298 goto out;
6299
afdfff59
YG
6300 /* set the default level for urgent bkops */
6301 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6302 hba->is_urgent_bkops_lvl_checked = false;
6303
ff8e20c6
DR
6304 /* Debug counters initialization */
6305 ufshcd_clear_dbg_ufs_stats(hba);
6306
57d104c1
SJ
6307 /* UniPro link is active now */
6308 ufshcd_set_link_active(hba);
d3e89bac 6309
5a0b0cb9
SRT
6310 ret = ufshcd_verify_dev_init(hba);
6311 if (ret)
6312 goto out;
68078d5c
DR
6313
6314 ret = ufshcd_complete_dev_init(hba);
6315 if (ret)
6316 goto out;
5a0b0cb9 6317
a4b0e8a4
PM
6318 /* Init check for device descriptor sizes */
6319 ufshcd_init_desc_sizes(hba);
6320
93fdd5ac
TW
6321 ret = ufs_get_device_desc(hba, &card);
6322 if (ret) {
6323 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6324 __func__, ret);
6325 goto out;
6326 }
6327
6328 ufs_fixup_device_setup(hba, &card);
37113106 6329 ufshcd_tune_unipro_params(hba);
60f01870
YG
6330
6331 ret = ufshcd_set_vccq_rail_unused(hba,
6332 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6333 if (ret)
6334 goto out;
6335
57d104c1
SJ
6336 /* UFS device is also active now */
6337 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6338 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ
6339 hba->wlun_dev_clr_ua = true;
6340
7eb584db
DR
6341 if (ufshcd_get_max_pwr_mode(hba)) {
6342 dev_err(hba->dev,
6343 "%s: Failed getting max supported power mode\n",
6344 __func__);
6345 } else {
6346 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6347 if (ret) {
7eb584db
DR
6348 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6349 __func__, ret);
8643ae66
DL
6350 goto out;
6351 }
7eb584db 6352 }
57d104c1 6353
53c12d0e
YG
6354 /* set the state as operational after switching to desired gear */
6355 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6356
57d104c1
SJ
6357 /*
6358 * If we are in error handling context or in power management callbacks
6359 * context, no need to scan the host
6360 */
6361 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6362 bool flag;
6363
6364 /* clear any previous UFS device information */
6365 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG
6366 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6367 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6368 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6369
3a4bf06d
YG
6370 if (!hba->is_init_prefetch)
6371 ufshcd_init_icc_levels(hba);
6372
2a8fa600
SJ
6373 /* Add required well known logical units to scsi mid layer */
6374 if (ufshcd_scsi_add_wlus(hba))
6375 goto out;
6376
0701e49d 6377 /* Initialize devfreq after UFS device is detected */
6378 if (ufshcd_is_clkscaling_supported(hba)) {
6379 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6380 &hba->pwr_info,
6381 sizeof(struct ufs_pa_layer_attr));
6382 hba->clk_scaling.saved_pwr_info.is_valid = true;
6383 if (!hba->devfreq) {
6384 hba->devfreq = devm_devfreq_add_device(hba->dev,
6385 &ufs_devfreq_profile,
6386 "simple_ondemand",
6387 NULL);
6388 if (IS_ERR(hba->devfreq)) {
6389 ret = PTR_ERR(hba->devfreq);
6390 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6391 ret);
6392 goto out;
6393 }
6394 }
6395 hba->clk_scaling.is_allowed = true;
6396 }
6397
3441da7d
SRT
6398 scsi_scan_host(hba->host);
6399 pm_runtime_put_sync(hba->dev);
6400 }
3a4bf06d
YG
6401
6402 if (!hba->is_init_prefetch)
6403 hba->is_init_prefetch = true;
6404
5a0b0cb9 6405out:
1d337ec2
SRT
6406 /*
6407 * If we failed to initialize the device or the device is not
6408 * present, turn off the power/clocks etc.
6409 */
57d104c1
SJ
6410 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6411 pm_runtime_put_sync(hba->dev);
1d337ec2 6412 ufshcd_hba_exit(hba);
57d104c1 6413 }
1d337ec2 6414
7ff5ab47 6415 trace_ufshcd_init(dev_name(hba->dev), ret,
6416 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6417 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT
6418 return ret;
6419}
6420
6421/**
6422 * ufshcd_async_scan - asynchronous execution for probing hba
6423 * @data: data pointer to pass to this function
6424 * @cookie: cookie data
6425 */
6426static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6427{
6428 struct ufs_hba *hba = (struct ufs_hba *)data;
6429
6430 ufshcd_probe_hba(hba);
6ccf44fe
SJ
6431}
6432
f550c65b
YG
6433static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6434{
6435 unsigned long flags;
6436 struct Scsi_Host *host;
6437 struct ufs_hba *hba;
6438 int index;
6439 bool found = false;
6440
6441 if (!scmd || !scmd->device || !scmd->device->host)
6442 return BLK_EH_NOT_HANDLED;
6443
6444 host = scmd->device->host;
6445 hba = shost_priv(host);
6446 if (!hba)
6447 return BLK_EH_NOT_HANDLED;
6448
6449 spin_lock_irqsave(host->host_lock, flags);
6450
6451 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6452 if (hba->lrb[index].cmd == scmd) {
6453 found = true;
6454 break;
6455 }
6456 }
6457
6458 spin_unlock_irqrestore(host->host_lock, flags);
6459
6460 /*
6461 * Bypass SCSI error handling and reset the block layer timer if this
6462 * SCSI command was not actually dispatched to UFS driver, otherwise
6463 * let SCSI layer handle the error as usual.
6464 */
6465 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6466}
6467
d829fc8a
SN
6468static const struct attribute_group *ufshcd_driver_groups[] = {
6469 &ufs_sysfs_unit_descriptor_group,
ec92b59c 6470 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN
6471 NULL,
6472};
6473
7a3e97b0
SY
6474static struct scsi_host_template ufshcd_driver_template = {
6475 .module = THIS_MODULE,
6476 .name = UFSHCD,
6477 .proc_name = UFSHCD,
6478 .queuecommand = ufshcd_queuecommand,
6479 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6480 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6481 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6482 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6483 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT
6484 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6485 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6486 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY
6487 .this_id = -1,
6488 .sg_tablesize = SG_ALL,
6489 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6490 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6491 .max_host_blocked = 1,
c40ecc12 6492 .track_queue_depth = 1,
d829fc8a 6493 .sdev_groups = ufshcd_driver_groups,
7a3e97b0
SY
6494};
6495
57d104c1
SJ
6496static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6497 int ua)
6498{
7b16a07c 6499 int ret;
57d104c1 6500
7b16a07c
BA
6501 if (!vreg)
6502 return 0;
57d104c1 6503
7b16a07c
BA
6504 ret = regulator_set_load(vreg->reg, ua);
6505 if (ret < 0) {
6506 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6507 __func__, vreg->name, ua, ret);
57d104c1
SJ
6508 }
6509
6510 return ret;
6511}
6512
6513static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6514 struct ufs_vreg *vreg)
6515{
60f01870
YG
6516 if (!vreg)
6517 return 0;
6518 else if (vreg->unused)
6519 return 0;
6520 else
6521 return ufshcd_config_vreg_load(hba->dev, vreg,
6522 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ
6523}
6524
6525static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6526 struct ufs_vreg *vreg)
6527{
60f01870
YG
6528 if (!vreg)
6529 return 0;
6530 else if (vreg->unused)
6531 return 0;
6532 else
6533 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ
6534}
6535
aa497613
SRT
6536static int ufshcd_config_vreg(struct device *dev,
6537 struct ufs_vreg *vreg, bool on)
6538{
6539 int ret = 0;
72753590
GS
6540 struct regulator *reg;
6541 const char *name;
aa497613
SRT
6542 int min_uV, uA_load;
6543
6544 BUG_ON(!vreg);
6545
72753590
GS
6546 reg = vreg->reg;
6547 name = vreg->name;
6548
aa497613
SRT
6549 if (regulator_count_voltages(reg) > 0) {
6550 min_uV = on ? vreg->min_uV : 0;
6551 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6552 if (ret) {
6553 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6554 __func__, name, ret);
6555 goto out;
6556 }
6557
6558 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ
6559 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6560 if (ret)
aa497613 6561 goto out;
aa497613
SRT
6562 }
6563out:
6564 return ret;
6565}
6566
6567static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6568{
6569 int ret = 0;
6570
60f01870
YG
6571 if (!vreg)
6572 goto out;
6573 else if (vreg->enabled || vreg->unused)
aa497613
SRT
6574 goto out;
6575
6576 ret = ufshcd_config_vreg(dev, vreg, true);
6577 if (!ret)
6578 ret = regulator_enable(vreg->reg);
6579
6580 if (!ret)
6581 vreg->enabled = true;
6582 else
6583 dev_err(dev, "%s: %s enable failed, err=%d\n",
6584 __func__, vreg->name, ret);
6585out:
6586 return ret;
6587}
6588
6589static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6590{
6591 int ret = 0;
6592
60f01870
YG
6593 if (!vreg)
6594 goto out;
6595 else if (!vreg->enabled || vreg->unused)
aa497613
SRT
6596 goto out;
6597
6598 ret = regulator_disable(vreg->reg);
6599
6600 if (!ret) {
6601 /* ignore errors on applying disable config */
6602 ufshcd_config_vreg(dev, vreg, false);
6603 vreg->enabled = false;
6604 } else {
6605 dev_err(dev, "%s: %s disable failed, err=%d\n",
6606 __func__, vreg->name, ret);
6607 }
6608out:
6609 return ret;
6610}
6611
6612static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6613{
6614 int ret = 0;
6615 struct device *dev = hba->dev;
6616 struct ufs_vreg_info *info = &hba->vreg_info;
6617
6618 if (!info)
6619 goto out;
6620
6621 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6622 if (ret)
6623 goto out;
6624
6625 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6626 if (ret)
6627 goto out;
6628
6629 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6630 if (ret)
6631 goto out;
6632
6633out:
6634 if (ret) {
6635 ufshcd_toggle_vreg(dev, info->vccq2, false);
6636 ufshcd_toggle_vreg(dev, info->vccq, false);
6637 ufshcd_toggle_vreg(dev, info->vcc, false);
6638 }
6639 return ret;
6640}
6641
6a771a65
RS
6642static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6643{
6644 struct ufs_vreg_info *info = &hba->vreg_info;
6645
6646 if (info)
6647 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6648
6649 return 0;
6650}
6651
aa497613
SRT
6652static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6653{
6654 int ret = 0;
6655
6656 if (!vreg)
6657 goto out;
6658
6659 vreg->reg = devm_regulator_get(dev, vreg->name);
6660 if (IS_ERR(vreg->reg)) {
6661 ret = PTR_ERR(vreg->reg);
6662 dev_err(dev, "%s: %s get failed, err=%d\n",
6663 __func__, vreg->name, ret);
6664 }
6665out:
6666 return ret;
6667}
6668
6669static int ufshcd_init_vreg(struct ufs_hba *hba)
6670{
6671 int ret = 0;
6672 struct device *dev = hba->dev;
6673 struct ufs_vreg_info *info = &hba->vreg_info;
6674
6675 if (!info)
6676 goto out;
6677
6678 ret = ufshcd_get_vreg(dev, info->vcc);
6679 if (ret)
6680 goto out;
6681
6682 ret = ufshcd_get_vreg(dev, info->vccq);
6683 if (ret)
6684 goto out;
6685
6686 ret = ufshcd_get_vreg(dev, info->vccq2);
6687out:
6688 return ret;
6689}
6690
6a771a65
RS
6691static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6692{
6693 struct ufs_vreg_info *info = &hba->vreg_info;
6694
6695 if (info)
6696 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6697
6698 return 0;
6699}
6700
60f01870
YG
6701static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6702{
6703 int ret = 0;
6704 struct ufs_vreg_info *info = &hba->vreg_info;
6705
6706 if (!info)
6707 goto out;
6708 else if (!info->vccq)
6709 goto out;
6710
6711 if (unused) {
6712 /* shut off the rail here */
6713 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6714 /*
6715 * Mark this rail as no longer used, so it doesn't get enabled
6716 * later by mistake
6717 */
6718 if (!ret)
6719 info->vccq->unused = true;
6720 } else {
6721 /*
6722 * rail should have been already enabled hence just make sure
6723 * that unused flag is cleared.
6724 */
6725 info->vccq->unused = false;
6726 }
6727out:
6728 return ret;
6729}
6730
57d104c1
SJ
6731static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6732 bool skip_ref_clk)
c6e79dac
SRT
6733{
6734 int ret = 0;
6735 struct ufs_clk_info *clki;
6736 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6737 unsigned long flags;
911a0771 6738 ktime_t start = ktime_get();
6739 bool clk_state_changed = false;
c6e79dac 6740
566ec9ad 6741 if (list_empty(head))
c6e79dac
SRT
6742 goto out;
6743
1e879e8f
SJ
6744 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6745 if (ret)
6746 return ret;
6747
c6e79dac
SRT
6748 list_for_each_entry(clki, head, list) {
6749 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ
6750 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6751 continue;
6752
911a0771 6753 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT
6754 if (on && !clki->enabled) {
6755 ret = clk_prepare_enable(clki->clk);
6756 if (ret) {
6757 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
6758 __func__, clki->name, ret);
6759 goto out;
6760 }
6761 } else if (!on && clki->enabled) {
6762 clk_disable_unprepare(clki->clk);
6763 }
6764 clki->enabled = on;
6765 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
6766 clki->name, on ? "en" : "dis");
6767 }
6768 }
1ab27c9c 6769
1e879e8f
SJ
6770 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
6771 if (ret)
6772 return ret;
6773
c6e79dac
SRT
6774out:
6775 if (ret) {
6776 list_for_each_entry(clki, head, list) {
6777 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
6778 clk_disable_unprepare(clki->clk);
6779 }
7ff5ab47 6780 } else if (!ret && on) {
1ab27c9c
ST
6781 spin_lock_irqsave(hba->host->host_lock, flags);
6782 hba->clk_gating.state = CLKS_ON;
7ff5ab47 6783 trace_ufshcd_clk_gating(dev_name(hba->dev),
6784 hba->clk_gating.state);
1ab27c9c 6785 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 6786 }
7ff5ab47 6787
911a0771 6788 if (clk_state_changed)
6789 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
6790 (on ? "on" : "off"),
6791 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT
6792 return ret;
6793}
6794
57d104c1
SJ
6795static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6796{
6797 return __ufshcd_setup_clocks(hba, on, false);
6798}
6799
c6e79dac
SRT
6800static int ufshcd_init_clocks(struct ufs_hba *hba)
6801{
6802 int ret = 0;
6803 struct ufs_clk_info *clki;
6804 struct device *dev = hba->dev;
6805 struct list_head *head = &hba->clk_list_head;
6806
566ec9ad 6807 if (list_empty(head))
c6e79dac
SRT
6808 goto out;
6809
6810 list_for_each_entry(clki, head, list) {
6811 if (!clki->name)
6812 continue;
6813
6814 clki->clk = devm_clk_get(dev, clki->name);
6815 if (IS_ERR(clki->clk)) {
6816 ret = PTR_ERR(clki->clk);
6817 dev_err(dev, "%s: %s clk get failed, %d\n",
6818 __func__, clki->name, ret);
6819 goto out;
6820 }
6821
6822 if (clki->max_freq) {
6823 ret = clk_set_rate(clki->clk, clki->max_freq);
6824 if (ret) {
6825 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6826 __func__, clki->name,
6827 clki->max_freq, ret);
6828 goto out;
6829 }
856b3483 6830 clki->curr_freq = clki->max_freq;
c6e79dac
SRT
6831 }
6832 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6833 clki->name, clk_get_rate(clki->clk));
6834 }
6835out:
6836 return ret;
6837}
6838
5c0c28a8
SRT
6839static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6840{
6841 int err = 0;
6842
6843 if (!hba->vops)
6844 goto out;
6845
0263bcd0
YG
6846 err = ufshcd_vops_init(hba);
6847 if (err)
6848 goto out;
5c0c28a8 6849
0263bcd0
YG
6850 err = ufshcd_vops_setup_regulators(hba, true);
6851 if (err)
6852 goto out_exit;
5c0c28a8
SRT
6853
6854 goto out;
6855
5c0c28a8 6856out_exit:
0263bcd0 6857 ufshcd_vops_exit(hba);
5c0c28a8
SRT
6858out:
6859 if (err)
6860 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 6861 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT
6862 return err;
6863}
6864
6865static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6866{
6867 if (!hba->vops)
6868 return;
6869
0263bcd0 6870 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 6871
0263bcd0 6872 ufshcd_vops_exit(hba);
5c0c28a8
SRT
6873}
6874
aa497613
SRT
6875static int ufshcd_hba_init(struct ufs_hba *hba)
6876{
6877 int err;
6878
6a771a65
RS
6879 /*
6880 * Handle host controller power separately from the UFS device power
6881 * rails as it will help controlling the UFS host controller power
6882 * collapse easily which is different than UFS device power collapse.
6883 * Also, enable the host controller power before we go ahead with rest
6884 * of the initialization here.
6885 */
6886 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT
6887 if (err)
6888 goto out;
6889
6a771a65 6890 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT
6891 if (err)
6892 goto out;
6893
6a771a65
RS
6894 err = ufshcd_init_clocks(hba);
6895 if (err)
6896 goto out_disable_hba_vreg;
6897
6898 err = ufshcd_setup_clocks(hba, true);
6899 if (err)
6900 goto out_disable_hba_vreg;
6901
c6e79dac
SRT
6902 err = ufshcd_init_vreg(hba);
6903 if (err)
6904 goto out_disable_clks;
6905
6906 err = ufshcd_setup_vreg(hba, true);
6907 if (err)
6908 goto out_disable_clks;
6909
aa497613
SRT
6910 err = ufshcd_variant_hba_init(hba);
6911 if (err)
6912 goto out_disable_vreg;
6913
1d337ec2 6914 hba->is_powered = true;
aa497613
SRT
6915 goto out;
6916
6917out_disable_vreg:
6918 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT
6919out_disable_clks:
6920 ufshcd_setup_clocks(hba, false);
6a771a65
RS
6921out_disable_hba_vreg:
6922 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT
6923out:
6924 return err;
6925}
6926
6927static void ufshcd_hba_exit(struct ufs_hba *hba)
6928{
1d337ec2
SRT
6929 if (hba->is_powered) {
6930 ufshcd_variant_hba_exit(hba);
6931 ufshcd_setup_vreg(hba, false);
a508253d 6932 ufshcd_suspend_clkscaling(hba);
401f1e44 6933 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d 6934 if (hba->devfreq)
6935 ufshcd_suspend_clkscaling(hba);
401f1e44 6936 destroy_workqueue(hba->clk_scaling.workq);
6937 }
1d337ec2
SRT
6938 ufshcd_setup_clocks(hba, false);
6939 ufshcd_setup_hba_vreg(hba, false);
6940 hba->is_powered = false;
6941 }
aa497613
SRT
6942}
6943
57d104c1
SJ
6944static int
6945ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6946{
6947 unsigned char cmd[6] = {REQUEST_SENSE,
6948 0,
6949 0,
6950 0,
dcea0bfb 6951 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ
6952 0};
6953 char *buffer;
6954 int ret;
6955
dcea0bfb 6956 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ
6957 if (!buffer) {
6958 ret = -ENOMEM;
6959 goto out;
6960 }
6961
fcbfffe2
CH
6962 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
6963 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
6964 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ
6965 if (ret)
6966 pr_err("%s: failed with err %d\n", __func__, ret);
6967
6968 kfree(buffer);
6969out:
6970 return ret;
6971}
6972
6973/**
6974 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6975 * power mode
6976 * @hba: per adapter instance
6977 * @pwr_mode: device power mode to set
6978 *
6979 * Returns 0 if requested power mode is set successfully
6980 * Returns non-zero if failed to set the requested power mode
6981 */
6982static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
6983 enum ufs_dev_pwr_mode pwr_mode)
6984{
6985 unsigned char cmd[6] = { START_STOP };
6986 struct scsi_sense_hdr sshdr;
7c48bfd0
AM
6987 struct scsi_device *sdp;
6988 unsigned long flags;
57d104c1
SJ
6989 int ret;
6990
7c48bfd0
AM
6991 spin_lock_irqsave(hba->host->host_lock, flags);
6992 sdp = hba->sdev_ufs_device;
6993 if (sdp) {
6994 ret = scsi_device_get(sdp);
6995 if (!ret && !scsi_device_online(sdp)) {
6996 ret = -ENODEV;
6997 scsi_device_put(sdp);
6998 }
6999 } else {
7000 ret = -ENODEV;
7001 }
7002 spin_unlock_irqrestore(hba->host->host_lock, flags);
7003
7004 if (ret)
7005 return ret;
57d104c1
SJ
7006
7007 /*
7008 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7009 * handling, which would wait for host to be resumed. Since we know
7010 * we are functional while we are here, skip host resume in error
7011 * handling context.
7012 */
7013 hba->host->eh_noresume = 1;
7014 if (hba->wlun_dev_clr_ua) {
7015 ret = ufshcd_send_request_sense(hba, sdp);
7016 if (ret)
7017 goto out;
7018 /* Unit attention condition is cleared now */
7019 hba->wlun_dev_clr_ua = false;
7020 }
7021
7022 cmd[4] = pwr_mode << 4;
7023
7024 /*
7025 * Current function would be generally called from the power management
e8064021 7026 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ
7027 * already suspended childs.
7028 */
fcbfffe2
CH
7029 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7030 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ
7031 if (ret) {
7032 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR
7033 "START_STOP failed for power mode: %d, result %x\n",
7034 pwr_mode, ret);
21045519
HR
7035 if (driver_byte(ret) & DRIVER_SENSE)
7036 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ
7037 }
7038
7039 if (!ret)
7040 hba->curr_dev_pwr_mode = pwr_mode;
7041out:
7c48bfd0 7042 scsi_device_put(sdp);
57d104c1
SJ
7043 hba->host->eh_noresume = 0;
7044 return ret;
7045}
7046
7047static int ufshcd_link_state_transition(struct ufs_hba *hba,
7048 enum uic_link_state req_link_state,
7049 int check_for_bkops)
7050{
7051 int ret = 0;
7052
7053 if (req_link_state == hba->uic_link_state)
7054 return 0;
7055
7056 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7057 ret = ufshcd_uic_hibern8_enter(hba);
7058 if (!ret)
7059 ufshcd_set_link_hibern8(hba);
7060 else
7061 goto out;
7062 }
7063 /*
7064 * If autobkops is enabled, link can't be turned off because
7065 * turning off the link would also turn off the device.
7066 */
7067 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7068 (!check_for_bkops || (check_for_bkops &&
7069 !hba->auto_bkops_enabled))) {
f3099fbd
YG
7070 /*
7071 * Let's make sure that link is in low power mode, we are doing
7072 * this currently by putting the link in Hibern8. Otherway to
7073 * put the link in low power mode is to send the DME end point
7074 * to device and then send the DME reset command to local
7075 * unipro. But putting the link in hibern8 is much faster.
7076 */
7077 ret = ufshcd_uic_hibern8_enter(hba);
7078 if (ret)
7079 goto out;
57d104c1
SJ
7080 /*
7081 * Change controller state to "reset state" which
7082 * should also put the link in off/reset state
7083 */
596585a2 7084 ufshcd_hba_stop(hba, true);
57d104c1
SJ
7085 /*
7086 * TODO: Check if we need any delay to make sure that
7087 * controller is reset
7088 */
7089 ufshcd_set_link_off(hba);
7090 }
7091
7092out:
7093 return ret;
7094}
7095
7096static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7097{
b799fdf7
YG
7098 /*
7099 * It seems some UFS devices may keep drawing more than sleep current
7100 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7101 * To avoid this situation, add 2ms delay before putting these UFS
7102 * rails in LPM mode.
7103 */
7104 if (!ufshcd_is_link_active(hba) &&
7105 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7106 usleep_range(2000, 2100);
7107
57d104c1
SJ
7108 /*
7109 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7110 * power.
7111 *
7112 * If UFS device and link is in OFF state, all power supplies (VCC,
7113 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7114 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7115 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7116 *
7117 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7118 * in low power state which would save some power.
7119 */
7120 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7121 !hba->dev_info.is_lu_power_on_wp) {
7122 ufshcd_setup_vreg(hba, false);
7123 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7124 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7125 if (!ufshcd_is_link_active(hba)) {
7126 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7127 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7128 }
7129 }
7130}
7131
7132static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7133{
7134 int ret = 0;
7135
7136 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7137 !hba->dev_info.is_lu_power_on_wp) {
7138 ret = ufshcd_setup_vreg(hba, true);
7139 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ
7140 if (!ret && !ufshcd_is_link_active(hba)) {
7141 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7142 if (ret)
7143 goto vcc_disable;
7144 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7145 if (ret)
7146 goto vccq_lpm;
7147 }
69d72ac8 7148 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ
7149 }
7150 goto out;
7151
7152vccq_lpm:
7153 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7154vcc_disable:
7155 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7156out:
7157 return ret;
7158}
7159
7160static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7161{
7162 if (ufshcd_is_link_off(hba))
7163 ufshcd_setup_hba_vreg(hba, false);
7164}
7165
7166static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7167{
7168 if (ufshcd_is_link_off(hba))
7169 ufshcd_setup_hba_vreg(hba, true);
7170}
7171
7a3e97b0 7172/**
57d104c1 7173 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7174 * @hba: per adapter instance
57d104c1
SJ
7175 * @pm_op: desired low power operation type
7176 *
7177 * This function will try to put the UFS device and link into low power
7178 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7179 * (System PM level).
7180 *
7181 * If this function is called during shutdown, it will make sure that
7182 * both UFS device and UFS link is powered off.
7a3e97b0 7183 *
57d104c1
SJ
7184 * NOTE: UFS device & link must be active before we enter in this function.
7185 *
7186 * Returns 0 for success and non-zero for failure
7a3e97b0 7187 */
57d104c1 7188static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7189{
57d104c1
SJ
7190 int ret = 0;
7191 enum ufs_pm_level pm_lvl;
7192 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7193 enum uic_link_state req_link_state;
7194
7195 hba->pm_op_in_progress = 1;
7196 if (!ufshcd_is_shutdown_pm(pm_op)) {
7197 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7198 hba->rpm_lvl : hba->spm_lvl;
7199 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7200 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7201 } else {
7202 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7203 req_link_state = UIC_LINK_OFF_STATE;
7204 }
7205
7a3e97b0 7206 /*
57d104c1
SJ
7207 * If we can't transition into any of the low power modes
7208 * just gate the clocks.
7a3e97b0 7209 */
1ab27c9c
ST
7210 ufshcd_hold(hba, false);
7211 hba->clk_gating.is_suspended = true;
7212
401f1e44 7213 if (hba->clk_scaling.is_allowed) {
7214 cancel_work_sync(&hba->clk_scaling.suspend_work);
7215 cancel_work_sync(&hba->clk_scaling.resume_work);
7216 ufshcd_suspend_clkscaling(hba);
7217 }
d6fcf81a 7218
57d104c1
SJ
7219 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7220 req_link_state == UIC_LINK_ACTIVE_STATE) {
7221 goto disable_clks;
7222 }
7a3e97b0 7223
57d104c1
SJ
7224 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7225 (req_link_state == hba->uic_link_state))
d6fcf81a 7226 goto enable_gating;
57d104c1
SJ
7227
7228 /* UFS device & link must be active before we enter in this function */
7229 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7230 ret = -EINVAL;
d6fcf81a 7231 goto enable_gating;
57d104c1
SJ
7232 }
7233
7234 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ
7235 if (ufshcd_can_autobkops_during_suspend(hba)) {
7236 /*
7237 * The device is idle with no requests in the queue,
7238 * allow background operations if bkops status shows
7239 * that performance might be impacted.
7240 */
7241 ret = ufshcd_urgent_bkops(hba);
7242 if (ret)
7243 goto enable_gating;
7244 } else {
7245 /* make sure that auto bkops is disabled */
7246 ufshcd_disable_auto_bkops(hba);
7247 }
57d104c1
SJ
7248 }
7249
7250 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7251 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7252 !ufshcd_is_runtime_pm(pm_op))) {
7253 /* ensure that bkops is disabled */
7254 ufshcd_disable_auto_bkops(hba);
7255 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7256 if (ret)
1ab27c9c 7257 goto enable_gating;
57d104c1
SJ
7258 }
7259
7260 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7261 if (ret)
7262 goto set_dev_active;
7263
7264 ufshcd_vreg_set_lpm(hba);
7265
7266disable_clks:
7267 /*
7268 * Call vendor specific suspend callback. As these callbacks may access
7269 * vendor specific host controller register space call them before the
7270 * host clocks are ON.
7271 */
0263bcd0
YG
7272 ret = ufshcd_vops_suspend(hba, pm_op);
7273 if (ret)
7274 goto set_link_active;
57d104c1 7275
57d104c1
SJ
7276 if (!ufshcd_is_link_active(hba))
7277 ufshcd_setup_clocks(hba, false);
7278 else
7279 /* If link is active, device ref_clk can't be switched off */
7280 __ufshcd_setup_clocks(hba, false, true);
7281
1ab27c9c 7282 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7283 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ
7284 /*
7285 * Disable the host irq as host controller as there won't be any
0263bcd0 7286 * host controller transaction expected till resume.
57d104c1
SJ
7287 */
7288 ufshcd_disable_irq(hba);
7289 /* Put the host controller in low power mode if possible */
7290 ufshcd_hba_vreg_set_lpm(hba);
7291 goto out;
7292
57d104c1 7293set_link_active:
401f1e44 7294 if (hba->clk_scaling.is_allowed)
7295 ufshcd_resume_clkscaling(hba);
57d104c1
SJ
7296 ufshcd_vreg_set_hpm(hba);
7297 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7298 ufshcd_set_link_active(hba);
7299 else if (ufshcd_is_link_off(hba))
7300 ufshcd_host_reset_and_restore(hba);
7301set_dev_active:
7302 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7303 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7304enable_gating:
401f1e44 7305 if (hba->clk_scaling.is_allowed)
7306 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST
7307 hba->clk_gating.is_suspended = false;
7308 ufshcd_release(hba);
57d104c1
SJ
7309out:
7310 hba->pm_op_in_progress = 0;
7311 return ret;
7a3e97b0
SY
7312}
7313
7314/**
57d104c1 7315 * ufshcd_resume - helper function for resume operations
3b1d0580 7316 * @hba: per adapter instance
57d104c1 7317 * @pm_op: runtime PM or system PM
7a3e97b0 7318 *
57d104c1
SJ
7319 * This function basically brings the UFS device, UniPro link and controller
7320 * to active state.
7321 *
7322 * Returns 0 for success and non-zero for failure
7a3e97b0 7323 */
57d104c1 7324static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7325{
57d104c1
SJ
7326 int ret;
7327 enum uic_link_state old_link_state;
7328
7329 hba->pm_op_in_progress = 1;
7330 old_link_state = hba->uic_link_state;
7331
7332 ufshcd_hba_vreg_set_hpm(hba);
7333 /* Make sure clocks are enabled before accessing controller */
7334 ret = ufshcd_setup_clocks(hba, true);
7335 if (ret)
7336 goto out;
7337
57d104c1
SJ
7338 /* enable the host irq as host controller would be active soon */
7339 ret = ufshcd_enable_irq(hba);
7340 if (ret)
7341 goto disable_irq_and_vops_clks;
7342
7343 ret = ufshcd_vreg_set_hpm(hba);
7344 if (ret)
7345 goto disable_irq_and_vops_clks;
7346
7a3e97b0 7347 /*
57d104c1
SJ
7348 * Call vendor specific resume callback. As these callbacks may access
7349 * vendor specific host controller register space call them when the
7350 * host clocks are ON.
7a3e97b0 7351 */
0263bcd0
YG
7352 ret = ufshcd_vops_resume(hba, pm_op);
7353 if (ret)
7354 goto disable_vreg;
57d104c1
SJ
7355
7356 if (ufshcd_is_link_hibern8(hba)) {
7357 ret = ufshcd_uic_hibern8_exit(hba);
7358 if (!ret)
7359 ufshcd_set_link_active(hba);
7360 else
7361 goto vendor_suspend;
7362 } else if (ufshcd_is_link_off(hba)) {
7363 ret = ufshcd_host_reset_and_restore(hba);
7364 /*
7365 * ufshcd_host_reset_and_restore() should have already
7366 * set the link state as active
7367 */
7368 if (ret || !ufshcd_is_link_active(hba))
7369 goto vendor_suspend;
7370 }
7371
7372 if (!ufshcd_is_ufs_dev_active(hba)) {
7373 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7374 if (ret)
7375 goto set_old_link_state;
7376 }
7377
4e768e76 7378 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7379 ufshcd_enable_auto_bkops(hba);
7380 else
7381 /*
7382 * If BKOPs operations are urgently needed at this moment then
7383 * keep auto-bkops enabled or else disable it.
7384 */
7385 ufshcd_urgent_bkops(hba);
7386
1ab27c9c
ST
7387 hba->clk_gating.is_suspended = false;
7388
fcb0c4b0
ST
7389 if (hba->clk_scaling.is_allowed)
7390 ufshcd_resume_clkscaling(hba);
856b3483 7391
1ab27c9c
ST
7392 /* Schedule clock gating in case of no access to UFS device yet */
7393 ufshcd_release(hba);
57d104c1
SJ
7394 goto out;
7395
7396set_old_link_state:
7397 ufshcd_link_state_transition(hba, old_link_state, 0);
7398vendor_suspend:
0263bcd0 7399 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ
7400disable_vreg:
7401 ufshcd_vreg_set_lpm(hba);
7402disable_irq_and_vops_clks:
7403 ufshcd_disable_irq(hba);
401f1e44 7404 if (hba->clk_scaling.is_allowed)
7405 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ
7406 ufshcd_setup_clocks(hba, false);
7407out:
7408 hba->pm_op_in_progress = 0;
7409 return ret;
7410}
7411
7412/**
7413 * ufshcd_system_suspend - system suspend routine
7414 * @hba: per adapter instance
57d104c1
SJ
7415 *
7416 * Check the description of ufshcd_suspend() function for more details.
7417 *
7418 * Returns 0 for success and non-zero for failure
7419 */
7420int ufshcd_system_suspend(struct ufs_hba *hba)
7421{
7422 int ret = 0;
7ff5ab47 7423 ktime_t start = ktime_get();
57d104c1
SJ
7424
7425 if (!hba || !hba->is_powered)
233b594b 7426 return 0;
57d104c1 7427
0b257734 7428 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7429 hba->curr_dev_pwr_mode) &&
7430 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7431 hba->uic_link_state))
7432 goto out;
57d104c1 7433
0b257734 7434 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ
7435 /*
7436 * UFS device and/or UFS link low power states during runtime
7437 * suspend seems to be different than what is expected during
7438 * system suspend. Hence runtime resume the devic & link and
7439 * let the system suspend low power states to take effect.
7440 * TODO: If resume takes longer time, we might have optimize
7441 * it in future by not resuming everything if possible.
7442 */
7443 ret = ufshcd_runtime_resume(hba);
7444 if (ret)
7445 goto out;
7446 }
7447
7448 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7449out:
7ff5ab47 7450 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7451 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7452 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR
7453 if (!ret)
7454 hba->is_sys_suspended = true;
57d104c1
SJ
7455 return ret;
7456}
7457EXPORT_SYMBOL(ufshcd_system_suspend);
7458
7459/**
7460 * ufshcd_system_resume - system resume routine
7461 * @hba: per adapter instance
7462 *
7463 * Returns 0 for success and non-zero for failure
7464 */
7a3e97b0 7465
57d104c1
SJ
7466int ufshcd_system_resume(struct ufs_hba *hba)
7467{
7ff5ab47 7468 int ret = 0;
7469 ktime_t start = ktime_get();
7470
e3ce73d6
YG
7471 if (!hba)
7472 return -EINVAL;
7473
7474 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ
7475 /*
7476 * Let the runtime resume take care of resuming
7477 * if runtime suspended.
7478 */
7ff5ab47 7479 goto out;
7480 else
7481 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7482out:
7483 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7484 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7485 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7486 return ret;
7a3e97b0 7487}
57d104c1 7488EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7489
57d104c1
SJ
7490/**
7491 * ufshcd_runtime_suspend - runtime suspend routine
7492 * @hba: per adapter instance
7493 *
7494 * Check the description of ufshcd_suspend() function for more details.
7495 *
7496 * Returns 0 for success and non-zero for failure
7497 */
66ec6d59
SRT
7498int ufshcd_runtime_suspend(struct ufs_hba *hba)
7499{
7ff5ab47 7500 int ret = 0;
7501 ktime_t start = ktime_get();
7502
e3ce73d6
YG
7503 if (!hba)
7504 return -EINVAL;
7505
7506 if (!hba->is_powered)
7ff5ab47 7507 goto out;
7508 else
7509 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7510out:
7511 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7512 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7513 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7514 return ret;
66ec6d59
SRT
7515}
7516EXPORT_SYMBOL(ufshcd_runtime_suspend);
7517
57d104c1
SJ
7518/**
7519 * ufshcd_runtime_resume - runtime resume routine
7520 * @hba: per adapter instance
7521 *
7522 * This function basically brings the UFS device, UniPro link and controller
7523 * to active state. Following operations are done in this function:
7524 *
7525 * 1. Turn on all the controller related clocks
7526 * 2. Bring the UniPro link out of Hibernate state
7527 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7528 * to active state.
7529 * 4. If auto-bkops is enabled on the device, disable it.
7530 *
7531 * So following would be the possible power state after this function return
7532 * successfully:
7533 * S1: UFS device in Active state with VCC rail ON
7534 * UniPro link in Active state
7535 * All the UFS/UniPro controller clocks are ON
7536 *
7537 * Returns 0 for success and non-zero for failure
7538 */
66ec6d59
SRT
7539int ufshcd_runtime_resume(struct ufs_hba *hba)
7540{
7ff5ab47 7541 int ret = 0;
7542 ktime_t start = ktime_get();
7543
e3ce73d6
YG
7544 if (!hba)
7545 return -EINVAL;
7546
7547 if (!hba->is_powered)
7ff5ab47 7548 goto out;
7549 else
7550 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7551out:
7552 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7553 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7554 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7555 return ret;
66ec6d59
SRT
7556}
7557EXPORT_SYMBOL(ufshcd_runtime_resume);
7558
7559int ufshcd_runtime_idle(struct ufs_hba *hba)
7560{
7561 return 0;
7562}
7563EXPORT_SYMBOL(ufshcd_runtime_idle);
7564
57d104c1
SJ
7565/**
7566 * ufshcd_shutdown - shutdown routine
7567 * @hba: per adapter instance
7568 *
7569 * This function would power off both UFS device and UFS link.
7570 *
7571 * Returns 0 always to allow force shutdown even in case of errors.
7572 */
7573int ufshcd_shutdown(struct ufs_hba *hba)
7574{
7575 int ret = 0;
7576
7577 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7578 goto out;
7579
7580 if (pm_runtime_suspended(hba->dev)) {
7581 ret = ufshcd_runtime_resume(hba);
7582 if (ret)
7583 goto out;
7584 }
7585
7586 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7587out:
7588 if (ret)
7589 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7590 /* allow force shutdown even in case of errors */
7591 return 0;
7592}
7593EXPORT_SYMBOL(ufshcd_shutdown);
7594
7a3e97b0 7595/**
3b1d0580 7596 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7597 * data structure memory
8aa29f19 7598 * @hba: per adapter instance
7a3e97b0 7599 */
3b1d0580 7600void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7601{
cbb6813e 7602 ufs_sysfs_remove_nodes(hba->dev);
cfdf9c91 7603 scsi_remove_host(hba->host);
7a3e97b0 7604 /* disable interrupts */
2fbd009b 7605 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7606 ufshcd_hba_stop(hba, true);
7a3e97b0 7607
1ab27c9c 7608 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST
7609 if (ufshcd_is_clkscaling_supported(hba))
7610 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7611 ufshcd_hba_exit(hba);
3b1d0580
VH
7612}
7613EXPORT_SYMBOL_GPL(ufshcd_remove);
7614
47555a5c
YG
7615/**
7616 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7617 * @hba: pointer to Host Bus Adapter (HBA)
7618 */
7619void ufshcd_dealloc_host(struct ufs_hba *hba)
7620{
7621 scsi_host_put(hba->host);
7622}
7623EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7624
ca3d7bf9
AM
7625/**
7626 * ufshcd_set_dma_mask - Set dma mask based on the controller
7627 * addressing capability
7628 * @hba: per adapter instance
7629 *
7630 * Returns 0 for success, non-zero for failure
7631 */
7632static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7633{
7634 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7635 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7636 return 0;
7637 }
7638 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7639}
7640
7a3e97b0 7641/**
5c0c28a8 7642 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH
7643 * @dev: pointer to device handle
7644 * @hba_handle: driver private handle
7a3e97b0
SY
7645 * Returns 0 on success, non-zero value on failure
7646 */
5c0c28a8 7647int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY
7648{
7649 struct Scsi_Host *host;
7650 struct ufs_hba *hba;
5c0c28a8 7651 int err = 0;
7a3e97b0 7652
3b1d0580
VH
7653 if (!dev) {
7654 dev_err(dev,
7655 "Invalid memory reference for dev is NULL\n");
7656 err = -ENODEV;
7a3e97b0
SY
7657 goto out_error;
7658 }
7659
7a3e97b0
SY
7660 host = scsi_host_alloc(&ufshcd_driver_template,
7661 sizeof(struct ufs_hba));
7662 if (!host) {
3b1d0580 7663 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7664 err = -ENOMEM;
3b1d0580 7665 goto out_error;
7a3e97b0
SY
7666 }
7667 hba = shost_priv(host);
7a3e97b0 7668 hba->host = host;
3b1d0580 7669 hba->dev = dev;
5c0c28a8
SRT
7670 *hba_handle = hba;
7671
566ec9ad
SM
7672 INIT_LIST_HEAD(&hba->clk_list_head);
7673
5c0c28a8
SRT
7674out_error:
7675 return err;
7676}
7677EXPORT_SYMBOL(ufshcd_alloc_host);
7678
7679/**
7680 * ufshcd_init - Driver initialization routine
7681 * @hba: per-adapter instance
7682 * @mmio_base: base register address
7683 * @irq: Interrupt line of device
7684 * Returns 0 on success, non-zero value on failure
7685 */
7686int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7687{
7688 int err;
7689 struct Scsi_Host *host = hba->host;
7690 struct device *dev = hba->dev;
7691
7692 if (!mmio_base) {
7693 dev_err(hba->dev,
7694 "Invalid memory reference for mmio_base is NULL\n");
7695 err = -ENODEV;
7696 goto out_error;
7697 }
7698
3b1d0580
VH
7699 hba->mmio_base = mmio_base;
7700 hba->irq = irq;
7a3e97b0 7701
a4b0e8a4
PM
7702 /* Set descriptor lengths to specification defaults */
7703 ufshcd_def_desc_sizes(hba);
7704
aa497613 7705 err = ufshcd_hba_init(hba);
5c0c28a8
SRT
7706 if (err)
7707 goto out_error;
7708
7a3e97b0
SY
7709 /* Read capabilities registers */
7710 ufshcd_hba_capabilities(hba);
7711
7712 /* Get UFS version supported by the controller */
7713 hba->ufs_version = ufshcd_get_ufs_version(hba);
7714
c01848c6
YG
7715 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7716 (hba->ufs_version != UFSHCI_VERSION_11) &&
7717 (hba->ufs_version != UFSHCI_VERSION_20) &&
7718 (hba->ufs_version != UFSHCI_VERSION_21))
7719 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7720 hba->ufs_version);
7721
2fbd009b
SJ
7722 /* Get Interrupt bit mask per version */
7723 hba->intr_mask = ufshcd_get_intr_mask(hba);
7724
ca3d7bf9
AM
7725 err = ufshcd_set_dma_mask(hba);
7726 if (err) {
7727 dev_err(hba->dev, "set dma mask failed\n");
7728 goto out_disable;
7729 }
7730
7a3e97b0
SY
7731 /* Allocate memory for host memory space */
7732 err = ufshcd_memory_alloc(hba);
7733 if (err) {
3b1d0580
VH
7734 dev_err(hba->dev, "Memory allocation failed\n");
7735 goto out_disable;
7a3e97b0
SY
7736 }
7737
7738 /* Configure LRB */
7739 ufshcd_host_memory_configure(hba);
7740
7741 host->can_queue = hba->nutrs;
7742 host->cmd_per_lun = hba->nutrs;
7743 host->max_id = UFSHCD_MAX_ID;
0ce147d4 7744 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY
7745 host->max_channel = UFSHCD_MAX_CHANNEL;
7746 host->unique_id = host->host_no;
7747 host->max_cmd_len = MAX_CDB_SIZE;
7748
7eb584db
DR
7749 hba->max_pwr_info.is_valid = false;
7750
7a3e97b0 7751 /* Initailize wait queue for task management */
e2933132
SRT
7752 init_waitqueue_head(&hba->tm_wq);
7753 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY
7754
7755 /* Initialize work queues */
e8e7f271 7756 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 7757 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 7758
6ccf44fe
SJ
7759 /* Initialize UIC command mutex */
7760 mutex_init(&hba->uic_cmd_mutex);
7761
5a0b0cb9
SRT
7762 /* Initialize mutex for device management commands */
7763 mutex_init(&hba->dev_cmd.lock);
7764
a3cd5ec5 7765 init_rwsem(&hba->clk_scaling_lock);
7766
5a0b0cb9
SRT
7767 /* Initialize device management tag acquire wait queue */
7768 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7769
1ab27c9c 7770 ufshcd_init_clk_gating(hba);
199ef13c
YG
7771
7772 /*
7773 * In order to avoid any spurious interrupt immediately after
7774 * registering UFS controller interrupt handler, clear any pending UFS
7775 * interrupt status and disable all the UFS interrupts.
7776 */
7777 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7778 REG_INTERRUPT_STATUS);
7779 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7780 /*
7781 * Make sure that UFS interrupts are disabled and any pending interrupt
7782 * status is cleared before registering UFS interrupt handler.
7783 */
7784 mb();
7785
7a3e97b0 7786 /* IRQ registration */
2953f850 7787 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 7788 if (err) {
3b1d0580 7789 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 7790 goto exit_gating;
57d104c1
SJ
7791 } else {
7792 hba->is_irq_enabled = true;
7a3e97b0
SY
7793 }
7794
3b1d0580 7795 err = scsi_add_host(host, hba->dev);
7a3e97b0 7796 if (err) {
3b1d0580 7797 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 7798 goto exit_gating;
7a3e97b0
SY
7799 }
7800
6ccf44fe
SJ
7801 /* Host controller enable */
7802 err = ufshcd_hba_enable(hba);
7a3e97b0 7803 if (err) {
6ccf44fe 7804 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 7805 ufshcd_print_host_regs(hba);
6ba65588 7806 ufshcd_print_host_state(hba);
3b1d0580 7807 goto out_remove_scsi_host;
7a3e97b0 7808 }
6ccf44fe 7809
fcb0c4b0 7810 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44 7811 char wq_name[sizeof("ufs_clkscaling_00")];
7812
401f1e44 7813 INIT_WORK(&hba->clk_scaling.suspend_work,
7814 ufshcd_clk_scaling_suspend_work);
7815 INIT_WORK(&hba->clk_scaling.resume_work,
7816 ufshcd_clk_scaling_resume_work);
7817
d985c6ea 7818 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
401f1e44 7819 host->host_no);
7820 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
7821
fcb0c4b0 7822 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST
7823 }
7824
0c8f7586 7825 /*
7826 * Set the default power management level for runtime and system PM.
7827 * Default power saving mode is to keep UFS link in Hibern8 state
7828 * and UFS device in sleep state.
7829 */
7830 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7831 UFS_SLEEP_PWR_MODE,
7832 UIC_LINK_HIBERN8_STATE);
7833 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7834 UFS_SLEEP_PWR_MODE,
7835 UIC_LINK_HIBERN8_STATE);
7836
62694735
SRT
7837 /* Hold auto suspend until async scan completes */
7838 pm_runtime_get_sync(dev);
7839
57d104c1 7840 /*
7caf489b 7841 * We are assuming that device wasn't put in sleep/power-down
7842 * state exclusively during the boot stage before kernel.
7843 * This assumption helps avoid doing link startup twice during
7844 * ufshcd_probe_hba().
57d104c1 7845 */
7caf489b 7846 ufshcd_set_ufs_dev_active(hba);
57d104c1 7847
6ccf44fe 7848 async_schedule(ufshcd_async_scan, hba);
cbb6813e 7849 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 7850
7a3e97b0
SY
7851 return 0;
7852
3b1d0580
VH
7853out_remove_scsi_host:
7854 scsi_remove_host(hba->host);
1ab27c9c
ST
7855exit_gating:
7856 ufshcd_exit_clk_gating(hba);
3b1d0580 7857out_disable:
57d104c1 7858 hba->is_irq_enabled = false;
aa497613 7859 ufshcd_hba_exit(hba);
3b1d0580
VH
7860out_error:
7861 return err;
7862}
7863EXPORT_SYMBOL_GPL(ufshcd_init);
7864
3b1d0580
VH
7865MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
7866MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 7867MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY
7868MODULE_LICENSE("GPL");
7869MODULE_VERSION(UFSHCD_DRIVER_VERSION);