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scsi: ufs: optimize system suspend handling
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
dcea0bfb
GB		 48#define UFSHCD_REQ_SENSE_SIZE 18
49
2fbd009b
SJ		 50#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
51 UTP_TASK_REQ_COMPL |\
52 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 53/* UIC command timeout, unit: ms */
54#define UIC_CMD_TIMEOUT 500
2fbd009b 55
5a0b0cb9
SRT		 56/* NOP OUT retries waiting for NOP IN response */
57#define NOP_OUT_RETRIES 10
58/* Timeout after 30 msecs if NOP OUT hangs without response */
59#define NOP_OUT_TIMEOUT 30 /* msecs */
60
68078d5c 61/* Query request retries */
10fe5888 62#define QUERY_REQ_RETRIES 3
68078d5c 63/* Query request timeout */
10fe5888 64#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 65
e2933132
SRT		 66/* Task management command timeout */
67#define TM_CMD_TIMEOUT 100 /* msecs */
68
64238fbd
YG		 69/* maximum number of retries for a general UIC command */
70#define UFS_UIC_COMMAND_RETRIES 3
71
1d337ec2
SRT		 72/* maximum number of link-startup retries */
73#define DME_LINKSTARTUP_RETRIES 3
74
87d0b4a6
YG		 75/* Maximum retries for Hibern8 enter */
76#define UIC_HIBERN8_ENTER_RETRIES 3
77
1d337ec2
SRT		 78/* maximum number of reset retries before giving up */
79#define MAX_HOST_RESET_RETRIES 5
80
68078d5c
DR		 81/* Expose the flag value from utp_upiu_query.value */
82#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
83
7d568652
SJ		 84/* Interrupt aggregation default timeout, unit: 40us */
85#define INT_AGGR_DEF_TO 0x02
86
aa497613
SRT		 87#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
88 ({ \
89 int _ret; \
90 if (_on) \
91 _ret = ufshcd_enable_vreg(_dev, _vreg); \
92 else \
93 _ret = ufshcd_disable_vreg(_dev, _vreg); \
94 _ret; \
95 })
96
da461cec
SJ		 97static u32 ufs_query_desc_max_size[] = {
98 QUERY_DESC_DEVICE_MAX_SIZE,
99 QUERY_DESC_CONFIGURAION_MAX_SIZE,
100 QUERY_DESC_UNIT_MAX_SIZE,
101 QUERY_DESC_RFU_MAX_SIZE,
102 QUERY_DESC_INTERCONNECT_MAX_SIZE,
103 QUERY_DESC_STRING_MAX_SIZE,
104 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 105 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 106 QUERY_DESC_POWER_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108};
109
7a3e97b0
SY		 110enum {
111 UFSHCD_MAX_CHANNEL = 0,
112 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 113 UFSHCD_CMD_PER_LUN = 32,
114 UFSHCD_CAN_QUEUE = 32,
115};
116
117/* UFSHCD states */
118enum {
7a3e97b0
SY		 119 UFSHCD_STATE_RESET,
120 UFSHCD_STATE_ERROR,
3441da7d 121 UFSHCD_STATE_OPERATIONAL,
141f8165 122 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 123};
124
125/* UFSHCD error handling flags */
126enum {
127 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 128};
129
e8e7f271
SRT		 130/* UFSHCD UIC layer error flags */
131enum {
132 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 133 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
134 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
135 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
136 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
137 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 138};
139
7a3e97b0
SY		 140/* Interrupt configuration options */
141enum {
142 UFSHCD_INT_DISABLE,
143 UFSHCD_INT_ENABLE,
144 UFSHCD_INT_CLEAR,
145};
146
3441da7d
SRT		 147#define ufshcd_set_eh_in_progress(h) \
148 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
149#define ufshcd_eh_in_progress(h) \
150 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
151#define ufshcd_clear_eh_in_progress(h) \
152 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
153
57d104c1
SJ		 154#define ufshcd_set_ufs_dev_active(h) \
155 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
156#define ufshcd_set_ufs_dev_sleep(h) \
157 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
158#define ufshcd_set_ufs_dev_poweroff(h) \
159 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
160#define ufshcd_is_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
162#define ufshcd_is_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
164#define ufshcd_is_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
166
167static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
168 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
169 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
170 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
171 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
172 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
173 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
174};
175
176static inline enum ufs_dev_pwr_mode
177ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
178{
179 return ufs_pm_lvl_states[lvl].dev_state;
180}
181
182static inline enum uic_link_state
183ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].link_state;
186}
187
3441da7d
SRT		 188static void ufshcd_tmc_handler(struct ufs_hba *hba);
189static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 190static int ufshcd_reset_and_restore(struct ufs_hba *hba);
191static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 192static void ufshcd_hba_exit(struct ufs_hba *hba);
193static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 194static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
195 bool skip_ref_clk);
196static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 197static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 198static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
199static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 200static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ		 201static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
202static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 203static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
204 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 205static int ufshcd_change_power_mode(struct ufs_hba *hba,
206 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 207static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
208{
209 return tag >= 0 && tag < hba->nutrs;
210}
57d104c1
SJ		 211
212static inline int ufshcd_enable_irq(struct ufs_hba *hba)
213{
214 int ret = 0;
215
216 if (!hba->is_irq_enabled) {
217 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
218 hba);
219 if (ret)
220 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
221 __func__, ret);
222 hba->is_irq_enabled = true;
223 }
224
225 return ret;
226}
227
228static inline void ufshcd_disable_irq(struct ufs_hba *hba)
229{
230 if (hba->is_irq_enabled) {
231 free_irq(hba->irq, hba);
232 hba->is_irq_enabled = false;
233 }
234}
3441da7d 235
b573d484
YG		 236/* replace non-printable or non-ASCII characters with spaces */
237static inline void ufshcd_remove_non_printable(char *val)
238{
239 if (!val)
240 return;
241
242 if (*val < 0x20 || *val > 0x7e)
243 *val = ' ';
244}
245
5a0b0cb9
SRT		 246/*
247 * ufshcd_wait_for_register - wait for register value to change
248 * @hba - per-adapter interface
249 * @reg - mmio register offset
250 * @mask - mask to apply to read register value
251 * @val - wait condition
252 * @interval_us - polling interval in microsecs
253 * @timeout_ms - timeout in millisecs
596585a2 254 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 255 *
256 * Returns -ETIMEDOUT on error, zero on success
257 */
596585a2
YG		 258int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
259 u32 val, unsigned long interval_us,
260 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 261{
262 int err = 0;
263 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
264
265 /* ignore bits that we don't intend to wait on */
266 val = val & mask;
267
268 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 269 if (can_sleep)
270 usleep_range(interval_us, interval_us + 50);
271 else
272 udelay(interval_us);
5a0b0cb9
SRT		 273 if (time_after(jiffies, timeout)) {
274 if ((ufshcd_readl(hba, reg) & mask) != val)
275 err = -ETIMEDOUT;
276 break;
277 }
278 }
279
280 return err;
281}
282
2fbd009b
SJ		 283/**
284 * ufshcd_get_intr_mask - Get the interrupt bit mask
285 * @hba - Pointer to adapter instance
286 *
287 * Returns interrupt bit mask per version
288 */
289static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
290{
291 if (hba->ufs_version == UFSHCI_VERSION_10)
292 return INTERRUPT_MASK_ALL_VER_10;
293 else
294 return INTERRUPT_MASK_ALL_VER_11;
295}
296
7a3e97b0
SY		 297/**
298 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
299 * @hba - Pointer to adapter instance
300 *
301 * Returns UFSHCI version supported by the controller
302 */
303static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
304{
0263bcd0
YG		 305 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
306 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 307
b873a275 308 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 309}
310
311/**
312 * ufshcd_is_device_present - Check if any device connected to
313 * the host controller
5c0c28a8 314 * @hba: pointer to adapter instance
7a3e97b0 315 *
73ec513a 316 * Returns 1 if device present, 0 if no device detected
7a3e97b0 317 */
5c0c28a8 318static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 319{
5c0c28a8
SRT		 320 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
321 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 322}
323
324/**
325 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
326 * @lrb: pointer to local command reference block
327 *
328 * This function is used to get the OCS field from UTRD
329 * Returns the OCS field in the UTRD
330 */
331static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
332{
e8c8e82a 333 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 334}
335
336/**
337 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
338 * @task_req_descp: pointer to utp_task_req_desc structure
339 *
340 * This function is used to get the OCS field from UTMRD
341 * Returns the OCS field in the UTMRD
342 */
343static inline int
344ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
345{
e8c8e82a 346 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 347}
348
349/**
350 * ufshcd_get_tm_free_slot - get a free slot for task management request
351 * @hba: per adapter instance
e2933132 352 * @free_slot: pointer to variable with available slot value
7a3e97b0 353 *
e2933132
SRT		 354 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
355 * Returns 0 if free slot is not available, else return 1 with tag value
356 * in @free_slot.
7a3e97b0 357 */
e2933132 358static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 359{
e2933132
SRT		 360 int tag;
361 bool ret = false;
362
363 if (!free_slot)
364 goto out;
365
366 do {
367 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
368 if (tag >= hba->nutmrs)
369 goto out;
370 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
371
372 *free_slot = tag;
373 ret = true;
374out:
375 return ret;
376}
377
378static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
379{
380 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 381}
382
383/**
384 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
385 * @hba: per adapter instance
386 * @pos: position of the bit to be cleared
387 */
388static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
389{
b873a275 390 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 391}
392
a48353f6
YG		 393/**
394 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
395 * @hba: per adapter instance
396 * @tag: position of the bit to be cleared
397 */
398static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
399{
400 __clear_bit(tag, &hba->outstanding_reqs);
401}
402
7a3e97b0
SY		 403/**
404 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
405 * @reg: Register value of host controller status
406 *
407 * Returns integer, 0 on Success and positive value if failed
408 */
409static inline int ufshcd_get_lists_status(u32 reg)
410{
411 /*
412 * The mask 0xFF is for the following HCS register bits
413 * Bit Description
414 * 0 Device Present
415 * 1 UTRLRDY
416 * 2 UTMRLRDY
417 * 3 UCRDY
897efe62 418 * 4-7 reserved
7a3e97b0 419 */
897efe62 420 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 421}
422
423/**
424 * ufshcd_get_uic_cmd_result - Get the UIC command result
425 * @hba: Pointer to adapter instance
426 *
427 * This function gets the result of UIC command completion
428 * Returns 0 on success, non zero value on error
429 */
430static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
431{
b873a275 432 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 433 MASK_UIC_COMMAND_RESULT;
434}
435
12b4fdb4
SJ		 436/**
437 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
438 * @hba: Pointer to adapter instance
439 *
440 * This function gets UIC command argument3
441 * Returns 0 on success, non zero value on error
442 */
443static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
444{
445 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
446}
447
7a3e97b0 448/**
5a0b0cb9 449 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 450 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 451 */
452static inline int
5a0b0cb9 453ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 454{
5a0b0cb9 455 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 456}
457
458/**
459 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
460 * @ucd_rsp_ptr: pointer to response UPIU
461 *
462 * This function gets the response status and scsi_status from response UPIU
463 * Returns the response result code.
464 */
465static inline int
466ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
467{
468 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
469}
470
1c2623c5
SJ		 471/*
472 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
473 * from response UPIU
474 * @ucd_rsp_ptr: pointer to response UPIU
475 *
476 * Return the data segment length.
477 */
478static inline unsigned int
479ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
480{
481 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
482 MASK_RSP_UPIU_DATA_SEG_LEN;
483}
484
66ec6d59
SRT		 485/**
486 * ufshcd_is_exception_event - Check if the device raised an exception event
487 * @ucd_rsp_ptr: pointer to response UPIU
488 *
489 * The function checks if the device raised an exception event indicated in
490 * the Device Information field of response UPIU.
491 *
492 * Returns true if exception is raised, false otherwise.
493 */
494static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
495{
496 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
497 MASK_RSP_EXCEPTION_EVENT ? true : false;
498}
499
7a3e97b0 500/**
7d568652 501 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 502 * @hba: per adapter instance
7a3e97b0
SY		 503 */
504static inline void
7d568652 505ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 506{
7d568652
SJ		 507 ufshcd_writel(hba, INT_AGGR_ENABLE |
508 INT_AGGR_COUNTER_AND_TIMER_RESET,
509 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
510}
511
512/**
513 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
514 * @hba: per adapter instance
515 * @cnt: Interrupt aggregation counter threshold
516 * @tmout: Interrupt aggregation timeout value
517 */
518static inline void
519ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
520{
521 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
522 INT_AGGR_COUNTER_THLD_VAL(cnt) |
523 INT_AGGR_TIMEOUT_VAL(tmout),
524 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 525}
526
b852190e
YG		 527/**
528 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
529 * @hba: per adapter instance
530 */
531static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
532{
533 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
534}
535
7a3e97b0
SY		 536/**
537 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
538 * When run-stop registers are set to 1, it indicates the
539 * host controller that it can process the requests
540 * @hba: per adapter instance
541 */
542static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
543{
b873a275
SJ		 544 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
545 REG_UTP_TASK_REQ_LIST_RUN_STOP);
546 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
547 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 548}
549
7a3e97b0
SY		 550/**
551 * ufshcd_hba_start - Start controller initialization sequence
552 * @hba: per adapter instance
553 */
554static inline void ufshcd_hba_start(struct ufs_hba *hba)
555{
b873a275 556 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 557}
558
559/**
560 * ufshcd_is_hba_active - Get controller state
561 * @hba: per adapter instance
562 *
563 * Returns zero if controller is active, 1 otherwise
564 */
565static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
566{
b873a275 567 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 568}
569
37113106
YG		 570u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
571{
572 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
573 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
574 (hba->ufs_version == UFSHCI_VERSION_11))
575 return UFS_UNIPRO_VER_1_41;
576 else
577 return UFS_UNIPRO_VER_1_6;
578}
579EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
580
581static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
582{
583 /*
584 * If both host and device support UniPro ver1.6 or later, PA layer
585 * parameters tuning happens during link startup itself.
586 *
587 * We can manually tune PA layer parameters if either host or device
588 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
589 * logic simple, we will only do manual tuning if local unipro version
590 * doesn't support ver1.6 or later.
591 */
592 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
593 return true;
594 else
595 return false;
596}
597
a508253d
GB		 598static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
599{
600 if (ufshcd_is_clkscaling_enabled(hba)) {
601 devfreq_suspend_device(hba->devfreq);
602 hba->clk_scaling.window_start_t = 0;
603 }
604}
605
606static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
607{
608 if (ufshcd_is_clkscaling_enabled(hba))
609 devfreq_resume_device(hba->devfreq);
610}
611
1ab27c9c
ST		 612static void ufshcd_ungate_work(struct work_struct *work)
613{
614 int ret;
615 unsigned long flags;
616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
617 clk_gating.ungate_work);
618
619 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
620
621 spin_lock_irqsave(hba->host->host_lock, flags);
622 if (hba->clk_gating.state == CLKS_ON) {
623 spin_unlock_irqrestore(hba->host->host_lock, flags);
624 goto unblock_reqs;
625 }
626
627 spin_unlock_irqrestore(hba->host->host_lock, flags);
628 ufshcd_setup_clocks(hba, true);
629
630 /* Exit from hibern8 */
631 if (ufshcd_can_hibern8_during_gating(hba)) {
632 /* Prevent gating in this path */
633 hba->clk_gating.is_suspended = true;
634 if (ufshcd_is_link_hibern8(hba)) {
635 ret = ufshcd_uic_hibern8_exit(hba);
636 if (ret)
637 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
638 __func__, ret);
639 else
640 ufshcd_set_link_active(hba);
641 }
642 hba->clk_gating.is_suspended = false;
643 }
644unblock_reqs:
a508253d 645 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 646 scsi_unblock_requests(hba->host);
647}
648
649/**
650 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
651 * Also, exit from hibern8 mode and set the link as active.
652 * @hba: per adapter instance
653 * @async: This indicates whether caller should ungate clocks asynchronously.
654 */
655int ufshcd_hold(struct ufs_hba *hba, bool async)
656{
657 int rc = 0;
658 unsigned long flags;
659
660 if (!ufshcd_is_clkgating_allowed(hba))
661 goto out;
1ab27c9c
ST		 662 spin_lock_irqsave(hba->host->host_lock, flags);
663 hba->clk_gating.active_reqs++;
664
53c12d0e
YG		 665 if (ufshcd_eh_in_progress(hba)) {
666 spin_unlock_irqrestore(hba->host->host_lock, flags);
667 return 0;
668 }
669
856b3483 670start:
1ab27c9c
ST		 671 switch (hba->clk_gating.state) {
672 case CLKS_ON:
f2a785ac
VG		 673 /*
674 * Wait for the ungate work to complete if in progress.
675 * Though the clocks may be in ON state, the link could
676 * still be in hibner8 state if hibern8 is allowed
677 * during clock gating.
678 * Make sure we exit hibern8 state also in addition to
679 * clocks being ON.
680 */
681 if (ufshcd_can_hibern8_during_gating(hba) &&
682 ufshcd_is_link_hibern8(hba)) {
683 spin_unlock_irqrestore(hba->host->host_lock, flags);
684 flush_work(&hba->clk_gating.ungate_work);
685 spin_lock_irqsave(hba->host->host_lock, flags);
686 goto start;
687 }
1ab27c9c
ST		 688 break;
689 case REQ_CLKS_OFF:
690 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
691 hba->clk_gating.state = CLKS_ON;
692 break;
693 }
694 /*
695 * If we here, it means gating work is either done or
696 * currently running. Hence, fall through to cancel gating
697 * work and to enable clocks.
698 */
699 case CLKS_OFF:
700 scsi_block_requests(hba->host);
701 hba->clk_gating.state = REQ_CLKS_ON;
702 schedule_work(&hba->clk_gating.ungate_work);
703 /*
704 * fall through to check if we should wait for this
705 * work to be done or not.
706 */
707 case REQ_CLKS_ON:
708 if (async) {
709 rc = -EAGAIN;
710 hba->clk_gating.active_reqs--;
711 break;
712 }
713
714 spin_unlock_irqrestore(hba->host->host_lock, flags);
715 flush_work(&hba->clk_gating.ungate_work);
716 /* Make sure state is CLKS_ON before returning */
856b3483 717 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 718 goto start;
719 default:
720 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
721 __func__, hba->clk_gating.state);
722 break;
723 }
724 spin_unlock_irqrestore(hba->host->host_lock, flags);
725out:
726 return rc;
727}
6e3fd44d 728EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 729
730static void ufshcd_gate_work(struct work_struct *work)
731{
732 struct ufs_hba *hba = container_of(work, struct ufs_hba,
733 clk_gating.gate_work.work);
734 unsigned long flags;
735
736 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 737 /*
738 * In case you are here to cancel this work the gating state
739 * would be marked as REQ_CLKS_ON. In this case save time by
740 * skipping the gating work and exit after changing the clock
741 * state to CLKS_ON.
742 */
743 if (hba->clk_gating.is_suspended ||
744 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c
ST		 745 hba->clk_gating.state = CLKS_ON;
746 goto rel_lock;
747 }
748
749 if (hba->clk_gating.active_reqs
750 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
751 || hba->lrb_in_use || hba->outstanding_tasks
752 || hba->active_uic_cmd || hba->uic_async_done)
753 goto rel_lock;
754
755 spin_unlock_irqrestore(hba->host->host_lock, flags);
756
757 /* put the link into hibern8 mode before turning off clocks */
758 if (ufshcd_can_hibern8_during_gating(hba)) {
759 if (ufshcd_uic_hibern8_enter(hba)) {
760 hba->clk_gating.state = CLKS_ON;
761 goto out;
762 }
763 ufshcd_set_link_hibern8(hba);
764 }
765
a508253d 766 ufshcd_suspend_clkscaling(hba);
856b3483 767
1ab27c9c
ST		 768 if (!ufshcd_is_link_active(hba))
769 ufshcd_setup_clocks(hba, false);
770 else
771 /* If link is active, device ref_clk can't be switched off */
772 __ufshcd_setup_clocks(hba, false, true);
773
774 /*
775 * In case you are here to cancel this work the gating state
776 * would be marked as REQ_CLKS_ON. In this case keep the state
777 * as REQ_CLKS_ON which would anyway imply that clocks are off
778 * and a request to turn them on is pending. By doing this way,
779 * we keep the state machine in tact and this would ultimately
780 * prevent from doing cancel work multiple times when there are
781 * new requests arriving before the current cancel work is done.
782 */
783 spin_lock_irqsave(hba->host->host_lock, flags);
784 if (hba->clk_gating.state == REQ_CLKS_OFF)
785 hba->clk_gating.state = CLKS_OFF;
786
787rel_lock:
788 spin_unlock_irqrestore(hba->host->host_lock, flags);
789out:
790 return;
791}
792
793/* host lock must be held before calling this variant */
794static void __ufshcd_release(struct ufs_hba *hba)
795{
796 if (!ufshcd_is_clkgating_allowed(hba))
797 return;
798
799 hba->clk_gating.active_reqs--;
800
801 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
802 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
803 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 804 || hba->active_uic_cmd || hba->uic_async_done
805 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 806 return;
807
808 hba->clk_gating.state = REQ_CLKS_OFF;
809 schedule_delayed_work(&hba->clk_gating.gate_work,
810 msecs_to_jiffies(hba->clk_gating.delay_ms));
811}
812
813void ufshcd_release(struct ufs_hba *hba)
814{
815 unsigned long flags;
816
817 spin_lock_irqsave(hba->host->host_lock, flags);
818 __ufshcd_release(hba);
819 spin_unlock_irqrestore(hba->host->host_lock, flags);
820}
6e3fd44d 821EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 822
823static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
824 struct device_attribute *attr, char *buf)
825{
826 struct ufs_hba *hba = dev_get_drvdata(dev);
827
828 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
829}
830
831static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
832 struct device_attribute *attr, const char *buf, size_t count)
833{
834 struct ufs_hba *hba = dev_get_drvdata(dev);
835 unsigned long flags, value;
836
837 if (kstrtoul(buf, 0, &value))
838 return -EINVAL;
839
840 spin_lock_irqsave(hba->host->host_lock, flags);
841 hba->clk_gating.delay_ms = value;
842 spin_unlock_irqrestore(hba->host->host_lock, flags);
843 return count;
844}
845
846static void ufshcd_init_clk_gating(struct ufs_hba *hba)
847{
848 if (!ufshcd_is_clkgating_allowed(hba))
849 return;
850
851 hba->clk_gating.delay_ms = 150;
852 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
853 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
854
855 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
856 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
857 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
858 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
859 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
860 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
861 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
862}
863
864static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
865{
866 if (!ufshcd_is_clkgating_allowed(hba))
867 return;
868 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM		 869 cancel_work_sync(&hba->clk_gating.ungate_work);
870 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 871}
872
856b3483
ST		 873/* Must be called with host lock acquired */
874static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
875{
876 if (!ufshcd_is_clkscaling_enabled(hba))
877 return;
878
879 if (!hba->clk_scaling.is_busy_started) {
880 hba->clk_scaling.busy_start_t = ktime_get();
881 hba->clk_scaling.is_busy_started = true;
882 }
883}
884
885static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
886{
887 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
888
889 if (!ufshcd_is_clkscaling_enabled(hba))
890 return;
891
892 if (!hba->outstanding_reqs && scaling->is_busy_started) {
893 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
894 scaling->busy_start_t));
895 scaling->busy_start_t = ktime_set(0, 0);
896 scaling->is_busy_started = false;
897 }
898}
7a3e97b0
SY		 899/**
900 * ufshcd_send_command - Send SCSI or device management commands
901 * @hba: per adapter instance
902 * @task_tag: Task tag of the command
903 */
904static inline
905void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
906{
856b3483 907 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 908 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 909 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 910 /* Make sure that doorbell is committed immediately */
911 wmb();
7a3e97b0
SY		 912}
913
914/**
915 * ufshcd_copy_sense_data - Copy sense data in case of check condition
916 * @lrb - pointer to local reference block
917 */
918static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
919{
920 int len;
1c2623c5
SJ		 921 if (lrbp->sense_buffer &&
922 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 923 int len_to_copy;
924
5a0b0cb9 925 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 926 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
927
7a3e97b0 928 memcpy(lrbp->sense_buffer,
5a0b0cb9 929 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 930 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 931 }
932}
933
68078d5c
DR		 934/**
935 * ufshcd_copy_query_response() - Copy the Query Response and the data
936 * descriptor
937 * @hba: per adapter instance
938 * @lrb - pointer to local reference block
939 */
940static
c6d4a831 941int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 942{
943 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
944
68078d5c 945 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 946
68078d5c
DR		 947 /* Get the descriptor */
948 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 949 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 950 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 951 u16 resp_len;
952 u16 buf_len;
68078d5c
DR		 953
954 /* data segment length */
c6d4a831 955 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 956 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 957 buf_len = be16_to_cpu(
958 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 959 if (likely(buf_len >= resp_len)) {
960 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
961 } else {
962 dev_warn(hba->dev,
963 "%s: Response size is bigger than buffer",
964 __func__);
965 return -EINVAL;
966 }
68078d5c 967 }
c6d4a831
DR		 968
969 return 0;
68078d5c
DR		 970}
971
7a3e97b0
SY		 972/**
973 * ufshcd_hba_capabilities - Read controller capabilities
974 * @hba: per adapter instance
975 */
976static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
977{
b873a275 978 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 979
980 /* nutrs and nutmrs are 0 based values */
981 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
982 hba->nutmrs =
983 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
984}
985
986/**
6ccf44fe
SJ		 987 * ufshcd_ready_for_uic_cmd - Check if controller is ready
988 * to accept UIC commands
7a3e97b0 989 * @hba: per adapter instance
6ccf44fe
SJ		 990 * Return true on success, else false
991 */
992static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
993{
994 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
995 return true;
996 else
997 return false;
998}
999
53b3d9c3
SJ		 1000/**
1001 * ufshcd_get_upmcrs - Get the power mode change request status
1002 * @hba: Pointer to adapter instance
1003 *
1004 * This function gets the UPMCRS field of HCS register
1005 * Returns value of UPMCRS field
1006 */
1007static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1008{
1009 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1010}
1011
6ccf44fe
SJ		 1012/**
1013 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1014 * @hba: per adapter instance
1015 * @uic_cmd: UIC command
1016 *
1017 * Mutex must be held.
7a3e97b0
SY		 1018 */
1019static inline void
6ccf44fe 1020ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1021{
6ccf44fe
SJ		 1022 WARN_ON(hba->active_uic_cmd);
1023
1024 hba->active_uic_cmd = uic_cmd;
1025
7a3e97b0 1026 /* Write Args */
6ccf44fe
SJ		 1027 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1028 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1029 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1030
1031 /* Write UIC Cmd */
6ccf44fe 1032 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1033 REG_UIC_COMMAND);
7a3e97b0
SY		 1034}
1035
6ccf44fe
SJ		 1036/**
1037 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1038 * @hba: per adapter instance
1039 * @uic_command: UIC command
1040 *
1041 * Must be called with mutex held.
1042 * Returns 0 only if success.
1043 */
1044static int
1045ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1046{
1047 int ret;
1048 unsigned long flags;
1049
1050 if (wait_for_completion_timeout(&uic_cmd->done,
1051 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1052 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1053 else
1054 ret = -ETIMEDOUT;
1055
1056 spin_lock_irqsave(hba->host->host_lock, flags);
1057 hba->active_uic_cmd = NULL;
1058 spin_unlock_irqrestore(hba->host->host_lock, flags);
1059
1060 return ret;
1061}
1062
1063/**
1064 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1065 * @hba: per adapter instance
1066 * @uic_cmd: UIC command
d75f7fe4 1067 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1068 *
1069 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1070 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1071 * Returns 0 only if success.
1072 */
1073static int
d75f7fe4
YG		 1074__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1075 bool completion)
6ccf44fe 1076{
6ccf44fe
SJ		 1077 if (!ufshcd_ready_for_uic_cmd(hba)) {
1078 dev_err(hba->dev,
1079 "Controller not ready to accept UIC commands\n");
1080 return -EIO;
1081 }
1082
d75f7fe4
YG		 1083 if (completion)
1084 init_completion(&uic_cmd->done);
6ccf44fe 1085
6ccf44fe 1086 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1087
57d104c1 1088 return 0;
6ccf44fe
SJ		 1089}
1090
1091/**
1092 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1093 * @hba: per adapter instance
1094 * @uic_cmd: UIC command
1095 *
1096 * Returns 0 only if success.
1097 */
1098static int
1099ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1100{
1101 int ret;
57d104c1 1102 unsigned long flags;
6ccf44fe 1103
1ab27c9c 1104 ufshcd_hold(hba, false);
6ccf44fe 1105 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1106 ufshcd_add_delay_before_dme_cmd(hba);
1107
57d104c1 1108 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1109 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1110 spin_unlock_irqrestore(hba->host->host_lock, flags);
1111 if (!ret)
1112 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1113
6ccf44fe
SJ		 1114 mutex_unlock(&hba->uic_cmd_mutex);
1115
1ab27c9c 1116 ufshcd_release(hba);
6ccf44fe
SJ		 1117 return ret;
1118}
1119
7a3e97b0
SY		 1120/**
1121 * ufshcd_map_sg - Map scatter-gather list to prdt
1122 * @lrbp - pointer to local reference block
1123 *
1124 * Returns 0 in case of success, non-zero value in case of failure
1125 */
75b1cc4a 1126static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1127{
1128 struct ufshcd_sg_entry *prd_table;
1129 struct scatterlist *sg;
1130 struct scsi_cmnd *cmd;
1131 int sg_segments;
1132 int i;
1133
1134 cmd = lrbp->cmd;
1135 sg_segments = scsi_dma_map(cmd);
1136 if (sg_segments < 0)
1137 return sg_segments;
1138
1139 if (sg_segments) {
75b1cc4a
KK		 1140 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1141 lrbp->utr_descriptor_ptr->prd_table_length =
1142 cpu_to_le16((u16)(sg_segments *
1143 sizeof(struct ufshcd_sg_entry)));
1144 else
1145 lrbp->utr_descriptor_ptr->prd_table_length =
1146 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 1147
1148 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1149
1150 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1151 prd_table[i].size =
1152 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1153 prd_table[i].base_addr =
1154 cpu_to_le32(lower_32_bits(sg->dma_address));
1155 prd_table[i].upper_addr =
1156 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1157 prd_table[i].reserved = 0;
7a3e97b0
SY		 1158 }
1159 } else {
1160 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1161 }
1162
1163 return 0;
1164}
1165
1166/**
2fbd009b 1167 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1168 * @hba: per adapter instance
2fbd009b 1169 * @intrs: interrupt bits
7a3e97b0 1170 */
2fbd009b 1171static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1172{
2fbd009b
SJ		 1173 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1174
1175 if (hba->ufs_version == UFSHCI_VERSION_10) {
1176 u32 rw;
1177 rw = set & INTERRUPT_MASK_RW_VER_10;
1178 set = rw | ((set ^ intrs) & intrs);
1179 } else {
1180 set |= intrs;
1181 }
1182
1183 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1184}
1185
1186/**
1187 * ufshcd_disable_intr - disable interrupts
1188 * @hba: per adapter instance
1189 * @intrs: interrupt bits
1190 */
1191static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1192{
1193 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1194
1195 if (hba->ufs_version == UFSHCI_VERSION_10) {
1196 u32 rw;
1197 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1198 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1199 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1200
1201 } else {
1202 set &= ~intrs;
7a3e97b0 1203 }
2fbd009b
SJ		 1204
1205 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1206}
1207
5a0b0cb9
SRT		 1208/**
1209 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1210 * descriptor according to request
1211 * @lrbp: pointer to local reference block
1212 * @upiu_flags: flags required in the header
1213 * @cmd_dir: requests data direction
1214 */
1215static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1216 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 1217{
1218 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1219 u32 data_direction;
1220 u32 dword_0;
1221
1222 if (cmd_dir == DMA_FROM_DEVICE) {
1223 data_direction = UTP_DEVICE_TO_HOST;
1224 *upiu_flags = UPIU_CMD_FLAGS_READ;
1225 } else if (cmd_dir == DMA_TO_DEVICE) {
1226 data_direction = UTP_HOST_TO_DEVICE;
1227 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1228 } else {
1229 data_direction = UTP_NO_DATA_TRANSFER;
1230 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1231 }
1232
1233 dword_0 = data_direction | (lrbp->command_type
1234 << UPIU_COMMAND_TYPE_OFFSET);
1235 if (lrbp->intr_cmd)
1236 dword_0 |= UTP_REQ_DESC_INT_CMD;
1237
1238 /* Transfer request descriptor header fields */
1239 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1240 /* dword_1 is reserved, hence it is set to 0 */
1241 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1242 /*
1243 * assigning invalid value for command status. Controller
1244 * updates OCS on command completion, with the command
1245 * status
1246 */
1247 req_desc->header.dword_2 =
1248 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1249 /* dword_3 is reserved, hence it is set to 0 */
1250 req_desc->header.dword_3 = 0;
51047266
YG		 1251
1252 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1253}
1254
1255/**
1256 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1257 * for scsi commands
1258 * @lrbp - local reference block pointer
1259 * @upiu_flags - flags
1260 */
1261static
1262void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1263{
1264 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1265 unsigned short cdb_len;
5a0b0cb9
SRT		 1266
1267 /* command descriptor fields */
1268 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1269 UPIU_TRANSACTION_COMMAND, upiu_flags,
1270 lrbp->lun, lrbp->task_tag);
1271 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1272 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1273
1274 /* Total EHS length and Data segment length will be zero */
1275 ucd_req_ptr->header.dword_2 = 0;
1276
1277 ucd_req_ptr->sc.exp_data_transfer_len =
1278 cpu_to_be32(lrbp->cmd->sdb.length);
1279
52ac95fe
YG		 1280 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1281 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1282 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1283
1284 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1285}
1286
68078d5c
DR		 1287/**
1288 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1289 * for query requsts
1290 * @hba: UFS hba
1291 * @lrbp: local reference block pointer
1292 * @upiu_flags: flags
1293 */
1294static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1295 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1296{
1297 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1298 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1299 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1300 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1301
1302 /* Query request header */
1303 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1304 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1305 lrbp->lun, lrbp->task_tag);
1306 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1307 0, query->request.query_func, 0, 0);
1308
6861285c
ZL		 1309 /* Data segment length only need for WRITE_DESC */
1310 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1311 ucd_req_ptr->header.dword_2 =
1312 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
1313 else
1314 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 1315
1316 /* Copy the Query Request buffer as is */
1317 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1318 QUERY_OSF_SIZE);
68078d5c
DR		 1319
1320 /* Copy the Descriptor */
c6d4a831
DR		 1321 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1322 memcpy(descp, query->descriptor, len);
1323
51047266 1324 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1325}
1326
5a0b0cb9
SRT		 1327static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1328{
1329 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1330
1331 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1332
1333 /* command descriptor fields */
1334 ucd_req_ptr->header.dword_0 =
1335 UPIU_HEADER_DWORD(
1336 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1337 /* clear rest of the fields of basic header */
1338 ucd_req_ptr->header.dword_1 = 0;
1339 ucd_req_ptr->header.dword_2 = 0;
1340
1341 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1342}
1343
7a3e97b0 1344/**
300bb13f
JP		 1345 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1346 * for Device Management Purposes
5a0b0cb9 1347 * @hba - per adapter instance
7a3e97b0
SY		 1348 * @lrb - pointer to local reference block
1349 */
300bb13f 1350static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1351{
7a3e97b0 1352 u32 upiu_flags;
5a0b0cb9 1353 int ret = 0;
7a3e97b0 1354
300bb13f
JP		 1355 if (hba->ufs_version == UFSHCI_VERSION_20)
1356 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1357 else
1358 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1359
1360 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1361 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1362 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1363 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1364 ufshcd_prepare_utp_nop_upiu(lrbp);
1365 else
1366 ret = -EINVAL;
1367
1368 return ret;
1369}
1370
1371/**
1372 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1373 * for SCSI Purposes
1374 * @hba - per adapter instance
1375 * @lrb - pointer to local reference block
1376 */
1377static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1378{
1379 u32 upiu_flags;
1380 int ret = 0;
1381
1382 if (hba->ufs_version == UFSHCI_VERSION_20)
1383 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1384 else
1385 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1386
1387 if (likely(lrbp->cmd)) {
1388 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1389 lrbp->cmd->sc_data_direction);
1390 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1391 } else {
1392 ret = -EINVAL;
1393 }
5a0b0cb9
SRT		 1394
1395 return ret;
7a3e97b0
SY		 1396}
1397
0ce147d4
SJ		 1398/*
1399 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1400 * @scsi_lun: scsi LUN id
1401 *
1402 * Returns UPIU LUN id
1403 */
1404static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1405{
1406 if (scsi_is_wlun(scsi_lun))
1407 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1408 | UFS_UPIU_WLUN_ID;
1409 else
1410 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1411}
1412
2a8fa600
SJ		 1413/**
1414 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1415 * @scsi_lun: UPIU W-LUN id
1416 *
1417 * Returns SCSI W-LUN id
1418 */
1419static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1420{
1421 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1422}
1423
7a3e97b0
SY		 1424/**
1425 * ufshcd_queuecommand - main entry point for SCSI requests
1426 * @cmd: command from SCSI Midlayer
1427 * @done: call back function
1428 *
1429 * Returns 0 for success, non-zero in case of failure
1430 */
1431static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1432{
1433 struct ufshcd_lrb *lrbp;
1434 struct ufs_hba *hba;
1435 unsigned long flags;
1436 int tag;
1437 int err = 0;
1438
1439 hba = shost_priv(host);
1440
1441 tag = cmd->request->tag;
14497328
YG		 1442 if (!ufshcd_valid_tag(hba, tag)) {
1443 dev_err(hba->dev,
1444 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1445 __func__, tag, cmd, cmd->request);
1446 BUG();
1447 }
7a3e97b0 1448
3441da7d
SRT		 1449 spin_lock_irqsave(hba->host->host_lock, flags);
1450 switch (hba->ufshcd_state) {
1451 case UFSHCD_STATE_OPERATIONAL:
1452 break;
141f8165 1453 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 1454 case UFSHCD_STATE_RESET:
7a3e97b0 1455 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1456 goto out_unlock;
1457 case UFSHCD_STATE_ERROR:
1458 set_host_byte(cmd, DID_ERROR);
1459 cmd->scsi_done(cmd);
1460 goto out_unlock;
1461 default:
1462 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1463 __func__, hba->ufshcd_state);
1464 set_host_byte(cmd, DID_BAD_TARGET);
1465 cmd->scsi_done(cmd);
1466 goto out_unlock;
7a3e97b0 1467 }
53c12d0e
YG		 1468
1469 /* if error handling is in progress, don't issue commands */
1470 if (ufshcd_eh_in_progress(hba)) {
1471 set_host_byte(cmd, DID_ERROR);
1472 cmd->scsi_done(cmd);
1473 goto out_unlock;
1474 }
3441da7d 1475 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1476
5a0b0cb9
SRT		 1477 /* acquire the tag to make sure device cmds don't use it */
1478 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1479 /*
1480 * Dev manage command in progress, requeue the command.
1481 * Requeuing the command helps in cases where the request *may*
1482 * find different tag instead of waiting for dev manage command
1483 * completion.
1484 */
1485 err = SCSI_MLQUEUE_HOST_BUSY;
1486 goto out;
1487 }
1488
1ab27c9c
ST		 1489 err = ufshcd_hold(hba, true);
1490 if (err) {
1491 err = SCSI_MLQUEUE_HOST_BUSY;
1492 clear_bit_unlock(tag, &hba->lrb_in_use);
1493 goto out;
1494 }
1495 WARN_ON(hba->clk_gating.state != CLKS_ON);
1496
7a3e97b0
SY		 1497 lrbp = &hba->lrb[tag];
1498
5a0b0cb9 1499 WARN_ON(lrbp->cmd);
7a3e97b0 1500 lrbp->cmd = cmd;
dcea0bfb 1501 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 1502 lrbp->sense_buffer = cmd->sense_buffer;
1503 lrbp->task_tag = tag;
0ce147d4 1504 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1505 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1506
300bb13f
JP		 1507 ufshcd_comp_scsi_upiu(hba, lrbp);
1508
75b1cc4a 1509 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 1510 if (err) {
1511 lrbp->cmd = NULL;
1512 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1513 goto out;
5a0b0cb9 1514 }
ad1a1b9c
GB		 1515 /* Make sure descriptors are ready before ringing the doorbell */
1516 wmb();
7a3e97b0
SY		 1517
1518 /* issue command to the controller */
1519 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1520 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 1521 ufshcd_send_command(hba, tag);
3441da7d 1522out_unlock:
7a3e97b0
SY		 1523 spin_unlock_irqrestore(hba->host->host_lock, flags);
1524out:
1525 return err;
1526}
1527
5a0b0cb9
SRT		 1528static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1529 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1530{
1531 lrbp->cmd = NULL;
1532 lrbp->sense_bufflen = 0;
1533 lrbp->sense_buffer = NULL;
1534 lrbp->task_tag = tag;
1535 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 1536 lrbp->intr_cmd = true; /* No interrupt aggregation */
1537 hba->dev_cmd.type = cmd_type;
1538
300bb13f 1539 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 1540}
1541
1542static int
1543ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1544{
1545 int err = 0;
1546 unsigned long flags;
1547 u32 mask = 1 << tag;
1548
1549 /* clear outstanding transaction before retry */
1550 spin_lock_irqsave(hba->host->host_lock, flags);
1551 ufshcd_utrl_clear(hba, tag);
1552 spin_unlock_irqrestore(hba->host->host_lock, flags);
1553
1554 /*
1555 * wait for for h/w to clear corresponding bit in door-bell.
1556 * max. wait is 1 sec.
1557 */
1558 err = ufshcd_wait_for_register(hba,
1559 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1560 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 1561
1562 return err;
1563}
1564
c6d4a831
DR		 1565static int
1566ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1567{
1568 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1569
1570 /* Get the UPIU response */
1571 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1572 UPIU_RSP_CODE_OFFSET;
1573 return query_res->response;
1574}
1575
5a0b0cb9
SRT		 1576/**
1577 * ufshcd_dev_cmd_completion() - handles device management command responses
1578 * @hba: per adapter instance
1579 * @lrbp: pointer to local reference block
1580 */
1581static int
1582ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1583{
1584 int resp;
1585 int err = 0;
1586
1587 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1588
1589 switch (resp) {
1590 case UPIU_TRANSACTION_NOP_IN:
1591 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1592 err = -EINVAL;
1593 dev_err(hba->dev, "%s: unexpected response %x\n",
1594 __func__, resp);
1595 }
1596 break;
68078d5c 1597 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1598 err = ufshcd_check_query_response(hba, lrbp);
1599 if (!err)
1600 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1601 break;
5a0b0cb9
SRT		 1602 case UPIU_TRANSACTION_REJECT_UPIU:
1603 /* TODO: handle Reject UPIU Response */
1604 err = -EPERM;
1605 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1606 __func__);
1607 break;
1608 default:
1609 err = -EINVAL;
1610 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1611 __func__, resp);
1612 break;
1613 }
1614
1615 return err;
1616}
1617
1618static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1619 struct ufshcd_lrb *lrbp, int max_timeout)
1620{
1621 int err = 0;
1622 unsigned long time_left;
1623 unsigned long flags;
1624
1625 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1626 msecs_to_jiffies(max_timeout));
1627
ad1a1b9c
GB		 1628 /* Make sure descriptors are ready before ringing the doorbell */
1629 wmb();
5a0b0cb9
SRT		 1630 spin_lock_irqsave(hba->host->host_lock, flags);
1631 hba->dev_cmd.complete = NULL;
1632 if (likely(time_left)) {
1633 err = ufshcd_get_tr_ocs(lrbp);
1634 if (!err)
1635 err = ufshcd_dev_cmd_completion(hba, lrbp);
1636 }
1637 spin_unlock_irqrestore(hba->host->host_lock, flags);
1638
1639 if (!time_left) {
1640 err = -ETIMEDOUT;
a48353f6
YG		 1641 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1642 __func__, lrbp->task_tag);
5a0b0cb9 1643 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1644 /* successfully cleared the command, retry if needed */
5a0b0cb9 1645 err = -EAGAIN;
a48353f6
YG		 1646 /*
1647 * in case of an error, after clearing the doorbell,
1648 * we also need to clear the outstanding_request
1649 * field in hba
1650 */
1651 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1652 }
1653
1654 return err;
1655}
1656
1657/**
1658 * ufshcd_get_dev_cmd_tag - Get device management command tag
1659 * @hba: per-adapter instance
1660 * @tag: pointer to variable with available slot value
1661 *
1662 * Get a free slot and lock it until device management command
1663 * completes.
1664 *
1665 * Returns false if free slot is unavailable for locking, else
1666 * return true with tag value in @tag.
1667 */
1668static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1669{
1670 int tag;
1671 bool ret = false;
1672 unsigned long tmp;
1673
1674 if (!tag_out)
1675 goto out;
1676
1677 do {
1678 tmp = ~hba->lrb_in_use;
1679 tag = find_last_bit(&tmp, hba->nutrs);
1680 if (tag >= hba->nutrs)
1681 goto out;
1682 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1683
1684 *tag_out = tag;
1685 ret = true;
1686out:
1687 return ret;
1688}
1689
1690static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1691{
1692 clear_bit_unlock(tag, &hba->lrb_in_use);
1693}
1694
1695/**
1696 * ufshcd_exec_dev_cmd - API for sending device management requests
1697 * @hba - UFS hba
1698 * @cmd_type - specifies the type (NOP, Query...)
1699 * @timeout - time in seconds
1700 *
68078d5c
DR		 1701 * NOTE: Since there is only one available tag for device management commands,
1702 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1703 */
1704static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1705 enum dev_cmd_type cmd_type, int timeout)
1706{
1707 struct ufshcd_lrb *lrbp;
1708 int err;
1709 int tag;
1710 struct completion wait;
1711 unsigned long flags;
1712
1713 /*
1714 * Get free slot, sleep if slots are unavailable.
1715 * Even though we use wait_event() which sleeps indefinitely,
1716 * the maximum wait time is bounded by SCSI request timeout.
1717 */
1718 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1719
1720 init_completion(&wait);
1721 lrbp = &hba->lrb[tag];
1722 WARN_ON(lrbp->cmd);
1723 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1724 if (unlikely(err))
1725 goto out_put_tag;
1726
1727 hba->dev_cmd.complete = &wait;
1728
e3dfdc53
YG		 1729 /* Make sure descriptors are ready before ringing the doorbell */
1730 wmb();
5a0b0cb9 1731 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 1732 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 1733 ufshcd_send_command(hba, tag);
1734 spin_unlock_irqrestore(hba->host->host_lock, flags);
1735
1736 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1737
1738out_put_tag:
1739 ufshcd_put_dev_cmd_tag(hba, tag);
1740 wake_up(&hba->dev_cmd.tag_wq);
1741 return err;
1742}
1743
d44a5f98
DR		 1744/**
1745 * ufshcd_init_query() - init the query response and request parameters
1746 * @hba: per-adapter instance
1747 * @request: address of the request pointer to be initialized
1748 * @response: address of the response pointer to be initialized
1749 * @opcode: operation to perform
1750 * @idn: flag idn to access
1751 * @index: LU number to access
1752 * @selector: query/flag/descriptor further identification
1753 */
1754static inline void ufshcd_init_query(struct ufs_hba *hba,
1755 struct ufs_query_req **request, struct ufs_query_res **response,
1756 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1757{
1758 *request = &hba->dev_cmd.query.request;
1759 *response = &hba->dev_cmd.query.response;
1760 memset(*request, 0, sizeof(struct ufs_query_req));
1761 memset(*response, 0, sizeof(struct ufs_query_res));
1762 (*request)->upiu_req.opcode = opcode;
1763 (*request)->upiu_req.idn = idn;
1764 (*request)->upiu_req.index = index;
1765 (*request)->upiu_req.selector = selector;
1766}
1767
dc3c8d3a
YG		 1768static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1769 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
1770{
1771 int ret;
1772 int retries;
1773
1774 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1775 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1776 if (ret)
1777 dev_dbg(hba->dev,
1778 "%s: failed with error %d, retries %d\n",
1779 __func__, ret, retries);
1780 else
1781 break;
1782 }
1783
1784 if (ret)
1785 dev_err(hba->dev,
1786 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1787 __func__, opcode, idn, ret, retries);
1788 return ret;
1789}
1790
68078d5c
DR		 1791/**
1792 * ufshcd_query_flag() - API function for sending flag query requests
1793 * hba: per-adapter instance
1794 * query_opcode: flag query to perform
1795 * idn: flag idn to access
1796 * flag_res: the flag value after the query request completes
1797 *
1798 * Returns 0 for success, non-zero in case of failure
1799 */
dc3c8d3a 1800int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 1801 enum flag_idn idn, bool *flag_res)
1802{
d44a5f98
DR		 1803 struct ufs_query_req *request = NULL;
1804 struct ufs_query_res *response = NULL;
1805 int err, index = 0, selector = 0;
e5ad406c 1806 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 1807
1808 BUG_ON(!hba);
1809
1ab27c9c 1810 ufshcd_hold(hba, false);
68078d5c 1811 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1812 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1813 selector);
68078d5c
DR		 1814
1815 switch (opcode) {
1816 case UPIU_QUERY_OPCODE_SET_FLAG:
1817 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1818 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1819 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1820 break;
1821 case UPIU_QUERY_OPCODE_READ_FLAG:
1822 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1823 if (!flag_res) {
1824 /* No dummy reads */
1825 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1826 __func__);
1827 err = -EINVAL;
1828 goto out_unlock;
1829 }
1830 break;
1831 default:
1832 dev_err(hba->dev,
1833 "%s: Expected query flag opcode but got = %d\n",
1834 __func__, opcode);
1835 err = -EINVAL;
1836 goto out_unlock;
1837 }
68078d5c 1838
e5ad406c 1839 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 1840
1841 if (err) {
1842 dev_err(hba->dev,
1843 "%s: Sending flag query for idn %d failed, err = %d\n",
1844 __func__, idn, err);
1845 goto out_unlock;
1846 }
1847
1848 if (flag_res)
e8c8e82a 1849 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1850 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1851
1852out_unlock:
1853 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1854 ufshcd_release(hba);
68078d5c
DR		 1855 return err;
1856}
1857
66ec6d59
SRT		 1858/**
1859 * ufshcd_query_attr - API function for sending attribute requests
1860 * hba: per-adapter instance
1861 * opcode: attribute opcode
1862 * idn: attribute idn to access
1863 * index: index field
1864 * selector: selector field
1865 * attr_val: the attribute value after the query request completes
1866 *
1867 * Returns 0 for success, non-zero in case of failure
1868*/
bdbe5d2f 1869static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1870 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1871{
d44a5f98
DR		 1872 struct ufs_query_req *request = NULL;
1873 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1874 int err;
1875
1876 BUG_ON(!hba);
1877
1ab27c9c 1878 ufshcd_hold(hba, false);
66ec6d59
SRT		 1879 if (!attr_val) {
1880 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1881 __func__, opcode);
1882 err = -EINVAL;
1883 goto out;
1884 }
1885
1886 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1887 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1888 selector);
66ec6d59
SRT		 1889
1890 switch (opcode) {
1891 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1892 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1893 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1894 break;
1895 case UPIU_QUERY_OPCODE_READ_ATTR:
1896 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1897 break;
1898 default:
1899 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1900 __func__, opcode);
1901 err = -EINVAL;
1902 goto out_unlock;
1903 }
1904
d44a5f98 1905 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1906
1907 if (err) {
4b761b58
YG		 1908 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1909 __func__, opcode, idn, index, err);
66ec6d59
SRT		 1910 goto out_unlock;
1911 }
1912
e8c8e82a 1913 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1914
1915out_unlock:
1916 mutex_unlock(&hba->dev_cmd.lock);
1917out:
1ab27c9c 1918 ufshcd_release(hba);
66ec6d59
SRT		 1919 return err;
1920}
1921
5e86ae44
YG		 1922/**
1923 * ufshcd_query_attr_retry() - API function for sending query
1924 * attribute with retries
1925 * @hba: per-adapter instance
1926 * @opcode: attribute opcode
1927 * @idn: attribute idn to access
1928 * @index: index field
1929 * @selector: selector field
1930 * @attr_val: the attribute value after the query request
1931 * completes
1932 *
1933 * Returns 0 for success, non-zero in case of failure
1934*/
1935static int ufshcd_query_attr_retry(struct ufs_hba *hba,
1936 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1937 u32 *attr_val)
1938{
1939 int ret = 0;
1940 u32 retries;
1941
1942 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1943 ret = ufshcd_query_attr(hba, opcode, idn, index,
1944 selector, attr_val);
1945 if (ret)
1946 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
1947 __func__, ret, retries);
1948 else
1949 break;
1950 }
1951
1952 if (ret)
1953 dev_err(hba->dev,
1954 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
1955 __func__, idn, ret, QUERY_REQ_RETRIES);
1956 return ret;
1957}
1958
a70e91b8 1959static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1960 enum query_opcode opcode, enum desc_idn idn, u8 index,
1961 u8 selector, u8 *desc_buf, int *buf_len)
1962{
1963 struct ufs_query_req *request = NULL;
1964 struct ufs_query_res *response = NULL;
1965 int err;
1966
1967 BUG_ON(!hba);
1968
1ab27c9c 1969 ufshcd_hold(hba, false);
d44a5f98
DR		 1970 if (!desc_buf) {
1971 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1972 __func__, opcode);
1973 err = -EINVAL;
1974 goto out;
1975 }
1976
1977 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1978 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1979 __func__, *buf_len);
1980 err = -EINVAL;
1981 goto out;
1982 }
1983
1984 mutex_lock(&hba->dev_cmd.lock);
1985 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1986 selector);
1987 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1988 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1989
1990 switch (opcode) {
1991 case UPIU_QUERY_OPCODE_WRITE_DESC:
1992 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1993 break;
1994 case UPIU_QUERY_OPCODE_READ_DESC:
1995 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1996 break;
1997 default:
1998 dev_err(hba->dev,
1999 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2000 __func__, opcode);
2001 err = -EINVAL;
2002 goto out_unlock;
2003 }
2004
2005 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2006
2007 if (err) {
4b761b58
YG		 2008 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2009 __func__, opcode, idn, index, err);
d44a5f98
DR		 2010 goto out_unlock;
2011 }
2012
2013 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2014 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2015
2016out_unlock:
2017 mutex_unlock(&hba->dev_cmd.lock);
2018out:
1ab27c9c 2019 ufshcd_release(hba);
d44a5f98
DR		 2020 return err;
2021}
2022
a70e91b8
YG		 2023/**
2024 * ufshcd_query_descriptor_retry - API function for sending descriptor
2025 * requests
2026 * hba: per-adapter instance
2027 * opcode: attribute opcode
2028 * idn: attribute idn to access
2029 * index: index field
2030 * selector: selector field
2031 * desc_buf: the buffer that contains the descriptor
2032 * buf_len: length parameter passed to the device
2033 *
2034 * Returns 0 for success, non-zero in case of failure.
2035 * The buf_len parameter will contain, on return, the length parameter
2036 * received on the response.
2037 */
2038int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2039 enum query_opcode opcode, enum desc_idn idn, u8 index,
2040 u8 selector, u8 *desc_buf, int *buf_len)
2041{
2042 int err;
2043 int retries;
2044
2045 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2046 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2047 selector, desc_buf, buf_len);
2048 if (!err || err == -EINVAL)
2049 break;
2050 }
2051
2052 return err;
2053}
2054EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2055
da461cec
SJ		 2056/**
2057 * ufshcd_read_desc_param - read the specified descriptor parameter
2058 * @hba: Pointer to adapter instance
2059 * @desc_id: descriptor idn value
2060 * @desc_index: descriptor index
2061 * @param_offset: offset of the parameter to read
2062 * @param_read_buf: pointer to buffer where parameter would be read
2063 * @param_size: sizeof(param_read_buf)
2064 *
2065 * Return 0 in case of success, non-zero otherwise
2066 */
2067static int ufshcd_read_desc_param(struct ufs_hba *hba,
2068 enum desc_idn desc_id,
2069 int desc_index,
2070 u32 param_offset,
2071 u8 *param_read_buf,
2072 u32 param_size)
2073{
2074 int ret;
2075 u8 *desc_buf;
2076 u32 buff_len;
2077 bool is_kmalloc = true;
2078
2079 /* safety checks */
2080 if (desc_id >= QUERY_DESC_IDN_MAX)
2081 return -EINVAL;
2082
2083 buff_len = ufs_query_desc_max_size[desc_id];
2084 if ((param_offset + param_size) > buff_len)
2085 return -EINVAL;
2086
2087 if (!param_offset && (param_size == buff_len)) {
2088 /* memory space already available to hold full descriptor */
2089 desc_buf = param_read_buf;
2090 is_kmalloc = false;
2091 } else {
2092 /* allocate memory to hold full descriptor */
2093 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2094 if (!desc_buf)
2095 return -ENOMEM;
2096 }
2097
a70e91b8
YG		 2098 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2099 desc_id, desc_index, 0, desc_buf,
2100 &buff_len);
da461cec 2101
bde44bb6 2102 if (ret) {
2103 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2104 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 2105
2106 goto out;
2107 }
2108
bde44bb6 2109 /* Sanity check */
2110 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2111 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2112 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2113 ret = -EINVAL;
2114 goto out;
2115 }
2116
2117 /*
2118 * While reading variable size descriptors (like string descriptor),
2119 * some UFS devices may report the "LENGTH" (field in "Transaction
2120 * Specific fields" of Query Response UPIU) same as what was requested
2121 * in Query Request UPIU instead of reporting the actual size of the
2122 * variable size descriptor.
2123 * Although it's safe to ignore the "LENGTH" field for variable size
2124 * descriptors as we can always derive the length of the descriptor from
2125 * the descriptor header fields. Hence this change impose the length
2126 * match check only for fixed size descriptors (for which we always
2127 * request the correct size as part of Query Request UPIU).
2128 */
2129 if ((desc_id != QUERY_DESC_IDN_STRING) &&
2130 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
2131 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
2132 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
2133 ret = -EINVAL;
2134 goto out;
2135 }
2136
da461cec
SJ		 2137 if (is_kmalloc)
2138 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2139out:
2140 if (is_kmalloc)
2141 kfree(desc_buf);
2142 return ret;
2143}
2144
2145static inline int ufshcd_read_desc(struct ufs_hba *hba,
2146 enum desc_idn desc_id,
2147 int desc_index,
2148 u8 *buf,
2149 u32 size)
2150{
2151 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2152}
2153
2154static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2155 u8 *buf,
2156 u32 size)
2157{
61e07359
DR		 2158 int err = 0;
2159 int retries;
2160
2161 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2162 /* Read descriptor*/
2163 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2164 if (!err)
2165 break;
2166 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2167 }
2168
2169 return err;
da461cec
SJ		 2170}
2171
b573d484
YG		 2172int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2173{
2174 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2175}
2176EXPORT_SYMBOL(ufshcd_read_device_desc);
2177
2178/**
2179 * ufshcd_read_string_desc - read string descriptor
2180 * @hba: pointer to adapter instance
2181 * @desc_index: descriptor index
2182 * @buf: pointer to buffer where descriptor would be read
2183 * @size: size of buf
2184 * @ascii: if true convert from unicode to ascii characters
2185 *
2186 * Return 0 in case of success, non-zero otherwise
2187 */
2188int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2189 u32 size, bool ascii)
2190{
2191 int err = 0;
2192
2193 err = ufshcd_read_desc(hba,
2194 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2195
2196 if (err) {
2197 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2198 __func__, QUERY_REQ_RETRIES, err);
2199 goto out;
2200 }
2201
2202 if (ascii) {
2203 int desc_len;
2204 int ascii_len;
2205 int i;
2206 char *buff_ascii;
2207
2208 desc_len = buf[0];
2209 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2210 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2211 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2212 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2213 __func__);
2214 err = -ENOMEM;
2215 goto out;
2216 }
2217
2218 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2219 if (!buff_ascii) {
2220 err = -ENOMEM;
fcbefc3b 2221 goto out;
b573d484
YG		 2222 }
2223
2224 /*
2225 * the descriptor contains string in UTF16 format
2226 * we need to convert to utf-8 so it can be displayed
2227 */
2228 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2229 desc_len - QUERY_DESC_HDR_SIZE,
2230 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2231
2232 /* replace non-printable or non-ASCII characters with spaces */
2233 for (i = 0; i < ascii_len; i++)
2234 ufshcd_remove_non_printable(&buff_ascii[i]);
2235
2236 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2237 size - QUERY_DESC_HDR_SIZE);
2238 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2239 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 2240 kfree(buff_ascii);
2241 }
2242out:
2243 return err;
2244}
2245EXPORT_SYMBOL(ufshcd_read_string_desc);
2246
da461cec
SJ		 2247/**
2248 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2249 * @hba: Pointer to adapter instance
2250 * @lun: lun id
2251 * @param_offset: offset of the parameter to read
2252 * @param_read_buf: pointer to buffer where parameter would be read
2253 * @param_size: sizeof(param_read_buf)
2254 *
2255 * Return 0 in case of success, non-zero otherwise
2256 */
2257static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2258 int lun,
2259 enum unit_desc_param param_offset,
2260 u8 *param_read_buf,
2261 u32 param_size)
2262{
2263 /*
2264 * Unit descriptors are only available for general purpose LUs (LUN id
2265 * from 0 to 7) and RPMB Well known LU.
2266 */
0ce147d4 2267 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 2268 return -EOPNOTSUPP;
2269
2270 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2271 param_offset, param_read_buf, param_size);
2272}
2273
7a3e97b0
SY		 2274/**
2275 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2276 * @hba: per adapter instance
2277 *
2278 * 1. Allocate DMA memory for Command Descriptor array
2279 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2280 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2281 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2282 * (UTMRDL)
2283 * 4. Allocate memory for local reference block(lrb).
2284 *
2285 * Returns 0 for success, non-zero in case of failure
2286 */
2287static int ufshcd_memory_alloc(struct ufs_hba *hba)
2288{
2289 size_t utmrdl_size, utrdl_size, ucdl_size;
2290
2291 /* Allocate memory for UTP command descriptors */
2292 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 2293 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2294 ucdl_size,
2295 &hba->ucdl_dma_addr,
2296 GFP_KERNEL);
7a3e97b0
SY		 2297
2298 /*
2299 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2300 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2301 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2302 * be aligned to 128 bytes as well
2303 */
2304 if (!hba->ucdl_base_addr ||
2305 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2306 dev_err(hba->dev,
7a3e97b0
SY		 2307 "Command Descriptor Memory allocation failed\n");
2308 goto out;
2309 }
2310
2311 /*
2312 * Allocate memory for UTP Transfer descriptors
2313 * UFSHCI requires 1024 byte alignment of UTRD
2314 */
2315 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2316 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2317 utrdl_size,
2318 &hba->utrdl_dma_addr,
2319 GFP_KERNEL);
7a3e97b0
SY		 2320 if (!hba->utrdl_base_addr ||
2321 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2322 dev_err(hba->dev,
7a3e97b0
SY		 2323 "Transfer Descriptor Memory allocation failed\n");
2324 goto out;
2325 }
2326
2327 /*
2328 * Allocate memory for UTP Task Management descriptors
2329 * UFSHCI requires 1024 byte alignment of UTMRD
2330 */
2331 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2332 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2333 utmrdl_size,
2334 &hba->utmrdl_dma_addr,
2335 GFP_KERNEL);
7a3e97b0
SY		 2336 if (!hba->utmrdl_base_addr ||
2337 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2338 dev_err(hba->dev,
7a3e97b0
SY		 2339 "Task Management Descriptor Memory allocation failed\n");
2340 goto out;
2341 }
2342
2343 /* Allocate memory for local reference block */
2953f850
SJ		 2344 hba->lrb = devm_kzalloc(hba->dev,
2345 hba->nutrs * sizeof(struct ufshcd_lrb),
2346 GFP_KERNEL);
7a3e97b0 2347 if (!hba->lrb) {
3b1d0580 2348 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2349 goto out;
2350 }
2351 return 0;
2352out:
7a3e97b0
SY		 2353 return -ENOMEM;
2354}
2355
2356/**
2357 * ufshcd_host_memory_configure - configure local reference block with
2358 * memory offsets
2359 * @hba: per adapter instance
2360 *
2361 * Configure Host memory space
2362 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2363 * address.
2364 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2365 * and PRDT offset.
2366 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2367 * into local reference block.
2368 */
2369static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2370{
2371 struct utp_transfer_cmd_desc *cmd_descp;
2372 struct utp_transfer_req_desc *utrdlp;
2373 dma_addr_t cmd_desc_dma_addr;
2374 dma_addr_t cmd_desc_element_addr;
2375 u16 response_offset;
2376 u16 prdt_offset;
2377 int cmd_desc_size;
2378 int i;
2379
2380 utrdlp = hba->utrdl_base_addr;
2381 cmd_descp = hba->ucdl_base_addr;
2382
2383 response_offset =
2384 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2385 prdt_offset =
2386 offsetof(struct utp_transfer_cmd_desc, prd_table);
2387
2388 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2389 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2390
2391 for (i = 0; i < hba->nutrs; i++) {
2392 /* Configure UTRD with command descriptor base address */
2393 cmd_desc_element_addr =
2394 (cmd_desc_dma_addr + (cmd_desc_size * i));
2395 utrdlp[i].command_desc_base_addr_lo =
2396 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2397 utrdlp[i].command_desc_base_addr_hi =
2398 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2399
2400 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 2401 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
2402 utrdlp[i].response_upiu_offset =
2403 cpu_to_le16(response_offset);
2404 utrdlp[i].prd_table_offset =
2405 cpu_to_le16(prdt_offset);
2406 utrdlp[i].response_upiu_length =
2407 cpu_to_le16(ALIGNED_UPIU_SIZE);
2408 } else {
2409 utrdlp[i].response_upiu_offset =
7a3e97b0 2410 cpu_to_le16((response_offset >> 2));
75b1cc4a 2411 utrdlp[i].prd_table_offset =
7a3e97b0 2412 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 2413 utrdlp[i].response_upiu_length =
3ca316c5 2414 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 2415 }
7a3e97b0
SY		 2416
2417 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2418 hba->lrb[i].ucd_req_ptr =
2419 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2420 hba->lrb[i].ucd_rsp_ptr =
2421 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2422 hba->lrb[i].ucd_prdt_ptr =
2423 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2424 }
2425}
2426
2427/**
2428 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2429 * @hba: per adapter instance
2430 *
2431 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2432 * in order to initialize the Unipro link startup procedure.
2433 * Once the Unipro links are up, the device connected to the controller
2434 * is detected.
2435 *
2436 * Returns 0 on success, non-zero value on failure
2437 */
2438static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2439{
6ccf44fe
SJ		 2440 struct uic_command uic_cmd = {0};
2441 int ret;
7a3e97b0 2442
6ccf44fe 2443 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2444
6ccf44fe
SJ		 2445 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2446 if (ret)
2447 dev_err(hba->dev,
2448 "dme-link-startup: error code %d\n", ret);
2449 return ret;
7a3e97b0
SY		 2450}
2451
cad2e03d
YG		 2452static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2453{
2454 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2455 unsigned long min_sleep_time_us;
2456
2457 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2458 return;
2459
2460 /*
2461 * last_dme_cmd_tstamp will be 0 only for 1st call to
2462 * this function
2463 */
2464 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2465 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2466 } else {
2467 unsigned long delta =
2468 (unsigned long) ktime_to_us(
2469 ktime_sub(ktime_get(),
2470 hba->last_dme_cmd_tstamp));
2471
2472 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2473 min_sleep_time_us =
2474 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2475 else
2476 return; /* no more delay required */
2477 }
2478
2479 /* allow sleep for extra 50us if needed */
2480 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2481}
2482
12b4fdb4
SJ		 2483/**
2484 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2485 * @hba: per adapter instance
2486 * @attr_sel: uic command argument1
2487 * @attr_set: attribute set type as uic command argument2
2488 * @mib_val: setting value as uic command argument3
2489 * @peer: indicate whether peer or local
2490 *
2491 * Returns 0 on success, non-zero value on failure
2492 */
2493int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2494 u8 attr_set, u32 mib_val, u8 peer)
2495{
2496 struct uic_command uic_cmd = {0};
2497 static const char *const action[] = {
2498 "dme-set",
2499 "dme-peer-set"
2500 };
2501 const char *set = action[!!peer];
2502 int ret;
64238fbd 2503 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 2504
2505 uic_cmd.command = peer ?
2506 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2507 uic_cmd.argument1 = attr_sel;
2508 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2509 uic_cmd.argument3 = mib_val;
2510
64238fbd
YG		 2511 do {
2512 /* for peer attributes we retry upon failure */
2513 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2514 if (ret)
2515 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2516 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2517 } while (ret && peer && --retries);
2518
f37e9f8c 2519 if (ret)
64238fbd 2520 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 2521 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2522 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 2523
2524 return ret;
2525}
2526EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2527
2528/**
2529 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2530 * @hba: per adapter instance
2531 * @attr_sel: uic command argument1
2532 * @mib_val: the value of the attribute as returned by the UIC command
2533 * @peer: indicate whether peer or local
2534 *
2535 * Returns 0 on success, non-zero value on failure
2536 */
2537int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2538 u32 *mib_val, u8 peer)
2539{
2540 struct uic_command uic_cmd = {0};
2541 static const char *const action[] = {
2542 "dme-get",
2543 "dme-peer-get"
2544 };
2545 const char *get = action[!!peer];
2546 int ret;
64238fbd 2547 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 2548 struct ufs_pa_layer_attr orig_pwr_info;
2549 struct ufs_pa_layer_attr temp_pwr_info;
2550 bool pwr_mode_change = false;
2551
2552 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2553 orig_pwr_info = hba->pwr_info;
2554 temp_pwr_info = orig_pwr_info;
2555
2556 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2557 orig_pwr_info.pwr_rx == FAST_MODE) {
2558 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2559 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2560 pwr_mode_change = true;
2561 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2562 orig_pwr_info.pwr_rx == SLOW_MODE) {
2563 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2564 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2565 pwr_mode_change = true;
2566 }
2567 if (pwr_mode_change) {
2568 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2569 if (ret)
2570 goto out;
2571 }
2572 }
12b4fdb4
SJ		 2573
2574 uic_cmd.command = peer ?
2575 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2576 uic_cmd.argument1 = attr_sel;
2577
64238fbd
YG		 2578 do {
2579 /* for peer attributes we retry upon failure */
2580 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2581 if (ret)
2582 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2583 get, UIC_GET_ATTR_ID(attr_sel), ret);
2584 } while (ret && peer && --retries);
2585
f37e9f8c 2586 if (ret)
64238fbd 2587 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 2588 get, UIC_GET_ATTR_ID(attr_sel),
2589 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 2590
64238fbd 2591 if (mib_val && !ret)
12b4fdb4 2592 *mib_val = uic_cmd.argument3;
874237f7
YG		 2593
2594 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2595 && pwr_mode_change)
2596 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2597out:
2598 return ret;
2599}
2600EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2601
53b3d9c3 2602/**
57d104c1
SJ		 2603 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2604 * state) and waits for it to take effect.
2605 *
53b3d9c3 2606 * @hba: per adapter instance
57d104c1
SJ		 2607 * @cmd: UIC command to execute
2608 *
2609 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2610 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2611 * and device UniPro link and hence it's final completion would be indicated by
2612 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2613 * addition to normal UIC command completion Status (UCCS). This function only
2614 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2615 *
2616 * Returns 0 on success, non-zero value on failure
2617 */
57d104c1 2618static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2619{
57d104c1 2620 struct completion uic_async_done;
53b3d9c3
SJ		 2621 unsigned long flags;
2622 u8 status;
2623 int ret;
d75f7fe4 2624 bool reenable_intr = false;
53b3d9c3 2625
53b3d9c3 2626 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2627 init_completion(&uic_async_done);
cad2e03d 2628 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2629
2630 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2631 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 2632 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2633 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2634 /*
2635 * Make sure UIC command completion interrupt is disabled before
2636 * issuing UIC command.
2637 */
2638 wmb();
2639 reenable_intr = true;
57d104c1 2640 }
d75f7fe4
YG		 2641 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2642 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 2643 if (ret) {
2644 dev_err(hba->dev,
2645 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2646 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2647 goto out;
2648 }
2649
57d104c1 2650 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2651 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2652 dev_err(hba->dev,
57d104c1
SJ		 2653 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2654 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2655 ret = -ETIMEDOUT;
2656 goto out;
2657 }
2658
2659 status = ufshcd_get_upmcrs(hba);
2660 if (status != PWR_LOCAL) {
2661 dev_err(hba->dev,
73615428 2662 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2663 cmd->command, status);
53b3d9c3
SJ		 2664 ret = (status != PWR_OK) ? status : -1;
2665 }
2666out:
2667 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2668 hba->active_uic_cmd = NULL;
57d104c1 2669 hba->uic_async_done = NULL;
d75f7fe4
YG		 2670 if (reenable_intr)
2671 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 2672 spin_unlock_irqrestore(hba->host->host_lock, flags);
2673 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2674
53b3d9c3
SJ		 2675 return ret;
2676}
2677
57d104c1
SJ		 2678/**
2679 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2680 * using DME_SET primitives.
2681 * @hba: per adapter instance
2682 * @mode: powr mode value
2683 *
2684 * Returns 0 on success, non-zero value on failure
2685 */
2686static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2687{
2688 struct uic_command uic_cmd = {0};
1ab27c9c 2689 int ret;
57d104c1 2690
c3a2f9ee
YG		 2691 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2692 ret = ufshcd_dme_set(hba,
2693 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2694 if (ret) {
2695 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2696 __func__, ret);
2697 goto out;
2698 }
2699 }
2700
57d104c1
SJ		 2701 uic_cmd.command = UIC_CMD_DME_SET;
2702 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2703 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2704 ufshcd_hold(hba, false);
2705 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2706 ufshcd_release(hba);
57d104c1 2707
c3a2f9ee 2708out:
1ab27c9c 2709 return ret;
57d104c1
SJ		 2710}
2711
53c12d0e
YG		 2712static int ufshcd_link_recovery(struct ufs_hba *hba)
2713{
2714 int ret;
2715 unsigned long flags;
2716
2717 spin_lock_irqsave(hba->host->host_lock, flags);
2718 hba->ufshcd_state = UFSHCD_STATE_RESET;
2719 ufshcd_set_eh_in_progress(hba);
2720 spin_unlock_irqrestore(hba->host->host_lock, flags);
2721
2722 ret = ufshcd_host_reset_and_restore(hba);
2723
2724 spin_lock_irqsave(hba->host->host_lock, flags);
2725 if (ret)
2726 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2727 ufshcd_clear_eh_in_progress(hba);
2728 spin_unlock_irqrestore(hba->host->host_lock, flags);
2729
2730 if (ret)
2731 dev_err(hba->dev, "%s: link recovery failed, err %d",
2732 __func__, ret);
2733
2734 return ret;
2735}
2736
87d0b4a6 2737static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 2738{
87d0b4a6 2739 int ret;
57d104c1
SJ		 2740 struct uic_command uic_cmd = {0};
2741
ee32c909
KK		 2742 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
2743
57d104c1 2744 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG		 2745 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2746
53c12d0e 2747 if (ret) {
87d0b4a6
YG		 2748 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
2749 __func__, ret);
2750
53c12d0e
YG		 2751 /*
2752 * If link recovery fails then return error so that caller
2753 * don't retry the hibern8 enter again.
2754 */
2755 if (ufshcd_link_recovery(hba))
2756 ret = -ENOLINK;
ee32c909
KK		 2757 } else
2758 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
2759 POST_CHANGE);
53c12d0e 2760
87d0b4a6
YG		 2761 return ret;
2762}
2763
2764static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2765{
2766 int ret = 0, retries;
57d104c1 2767
87d0b4a6
YG		 2768 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
2769 ret = __ufshcd_uic_hibern8_enter(hba);
2770 if (!ret || ret == -ENOLINK)
2771 goto out;
2772 }
2773out:
2774 return ret;
57d104c1
SJ		 2775}
2776
2777static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2778{
2779 struct uic_command uic_cmd = {0};
2780 int ret;
2781
ee32c909
KK		 2782 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
2783
57d104c1
SJ		 2784 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2785 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2786 if (ret) {
53c12d0e
YG		 2787 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
2788 __func__, ret);
2789 ret = ufshcd_link_recovery(hba);
ee32c909
KK		 2790 } else
2791 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
2792 POST_CHANGE);
57d104c1
SJ		 2793
2794 return ret;
2795}
2796
5064636c
YG		 2797 /**
2798 * ufshcd_init_pwr_info - setting the POR (power on reset)
2799 * values in hba power info
2800 * @hba: per-adapter instance
2801 */
2802static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2803{
2804 hba->pwr_info.gear_rx = UFS_PWM_G1;
2805 hba->pwr_info.gear_tx = UFS_PWM_G1;
2806 hba->pwr_info.lane_rx = 1;
2807 hba->pwr_info.lane_tx = 1;
2808 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2809 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2810 hba->pwr_info.hs_rate = 0;
2811}
2812
d3e89bac 2813/**
7eb584db
DR		 2814 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2815 * @hba: per-adapter instance
d3e89bac 2816 */
7eb584db 2817static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2818{
7eb584db
DR		 2819 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2820
2821 if (hba->max_pwr_info.is_valid)
2822 return 0;
2823
2824 pwr_info->pwr_tx = FASTAUTO_MODE;
2825 pwr_info->pwr_rx = FASTAUTO_MODE;
2826 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2827
2828 /* Get the connected lane count */
7eb584db
DR		 2829 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2830 &pwr_info->lane_rx);
2831 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2832 &pwr_info->lane_tx);
2833
2834 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2835 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2836 __func__,
2837 pwr_info->lane_rx,
2838 pwr_info->lane_tx);
2839 return -EINVAL;
2840 }
d3e89bac
SJ		 2841
2842 /*
2843 * First, get the maximum gears of HS speed.
2844 * If a zero value, it means there is no HSGEAR capability.
2845 * Then, get the maximum gears of PWM speed.
2846 */
7eb584db
DR		 2847 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2848 if (!pwr_info->gear_rx) {
2849 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2850 &pwr_info->gear_rx);
2851 if (!pwr_info->gear_rx) {
2852 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2853 __func__, pwr_info->gear_rx);
2854 return -EINVAL;
2855 }
2856 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2857 }
2858
7eb584db
DR		 2859 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2860 &pwr_info->gear_tx);
2861 if (!pwr_info->gear_tx) {
d3e89bac 2862 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2863 &pwr_info->gear_tx);
2864 if (!pwr_info->gear_tx) {
2865 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2866 __func__, pwr_info->gear_tx);
2867 return -EINVAL;
2868 }
2869 pwr_info->pwr_tx = SLOWAUTO_MODE;
2870 }
2871
2872 hba->max_pwr_info.is_valid = true;
2873 return 0;
2874}
2875
2876static int ufshcd_change_power_mode(struct ufs_hba *hba,
2877 struct ufs_pa_layer_attr *pwr_mode)
2878{
2879 int ret;
2880
2881 /* if already configured to the requested pwr_mode */
2882 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2883 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2884 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2885 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2886 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2887 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2888 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2889 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2890 return 0;
d3e89bac
SJ		 2891 }
2892
2893 /*
2894 * Configure attributes for power mode change with below.
2895 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2896 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2897 * - PA_HSSERIES
2898 */
7eb584db
DR		 2899 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2900 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2901 pwr_mode->lane_rx);
2902 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2903 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2904 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2905 else
2906 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2907
7eb584db
DR		 2908 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2909 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2910 pwr_mode->lane_tx);
2911 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2912 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2913 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2914 else
2915 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2916
7eb584db
DR		 2917 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2918 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2919 pwr_mode->pwr_rx == FAST_MODE ||
2920 pwr_mode->pwr_tx == FAST_MODE)
2921 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2922 pwr_mode->hs_rate);
d3e89bac 2923
7eb584db
DR		 2924 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2925 | pwr_mode->pwr_tx);
2926
2927 if (ret) {
d3e89bac 2928 dev_err(hba->dev,
7eb584db
DR		 2929 "%s: power mode change failed %d\n", __func__, ret);
2930 } else {
0263bcd0
YG		 2931 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2932 pwr_mode);
7eb584db
DR		 2933
2934 memcpy(&hba->pwr_info, pwr_mode,
2935 sizeof(struct ufs_pa_layer_attr));
2936 }
2937
2938 return ret;
2939}
2940
2941/**
2942 * ufshcd_config_pwr_mode - configure a new power mode
2943 * @hba: per-adapter instance
2944 * @desired_pwr_mode: desired power configuration
2945 */
2946static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2947 struct ufs_pa_layer_attr *desired_pwr_mode)
2948{
2949 struct ufs_pa_layer_attr final_params = { 0 };
2950 int ret;
2951
0263bcd0
YG		 2952 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2953 desired_pwr_mode, &final_params);
2954
2955 if (ret)
7eb584db
DR		 2956 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2957
2958 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2959
2960 return ret;
2961}
2962
68078d5c
DR		 2963/**
2964 * ufshcd_complete_dev_init() - checks device readiness
2965 * hba: per-adapter instance
2966 *
2967 * Set fDeviceInit flag and poll until device toggles it.
2968 */
2969static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2970{
dc3c8d3a
YG		 2971 int i;
2972 int err;
68078d5c
DR		 2973 bool flag_res = 1;
2974
dc3c8d3a
YG		 2975 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2976 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 2977 if (err) {
2978 dev_err(hba->dev,
2979 "%s setting fDeviceInit flag failed with error %d\n",
2980 __func__, err);
2981 goto out;
2982 }
2983
dc3c8d3a
YG		 2984 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
2985 for (i = 0; i < 1000 && !err && flag_res; i++)
2986 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
2987 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2988
68078d5c
DR		 2989 if (err)
2990 dev_err(hba->dev,
2991 "%s reading fDeviceInit flag failed with error %d\n",
2992 __func__, err);
2993 else if (flag_res)
2994 dev_err(hba->dev,
2995 "%s fDeviceInit was not cleared by the device\n",
2996 __func__);
2997
2998out:
2999 return err;
3000}
3001
7a3e97b0
SY		 3002/**
3003 * ufshcd_make_hba_operational - Make UFS controller operational
3004 * @hba: per adapter instance
3005 *
3006 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3007 * 1. Enable required interrupts
3008 * 2. Configure interrupt aggregation
897efe62 3009 * 3. Program UTRL and UTMRL base address
5c0c28a8 3010 * 4. Configure run-stop-registers
7a3e97b0
SY		 3011 *
3012 * Returns 0 on success, non-zero value on failure
3013 */
3014static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3015{
3016 int err = 0;
3017 u32 reg;
3018
6ccf44fe
SJ		 3019 /* Enable required interrupts */
3020 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3021
3022 /* Configure interrupt aggregation */
b852190e
YG		 3023 if (ufshcd_is_intr_aggr_allowed(hba))
3024 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3025 else
3026 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3027
3028 /* Configure UTRL and UTMRL base address registers */
3029 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3030 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3031 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3032 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3033 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3034 REG_UTP_TASK_REQ_LIST_BASE_L);
3035 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3036 REG_UTP_TASK_REQ_LIST_BASE_H);
3037
897efe62
YG		 3038 /*
3039 * Make sure base address and interrupt setup are updated before
3040 * enabling the run/stop registers below.
3041 */
3042 wmb();
3043
7a3e97b0
SY		 3044 /*
3045 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3046 */
5c0c28a8 3047 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3048 if (!(ufshcd_get_lists_status(reg))) {
3049 ufshcd_enable_run_stop_reg(hba);
3050 } else {
3b1d0580 3051 dev_err(hba->dev,
7a3e97b0
SY		 3052 "Host controller not ready to process requests");
3053 err = -EIO;
3054 goto out;
3055 }
3056
7a3e97b0
SY		 3057out:
3058 return err;
3059}
3060
596585a2
YG		 3061/**
3062 * ufshcd_hba_stop - Send controller to reset state
3063 * @hba: per adapter instance
3064 * @can_sleep: perform sleep or just spin
3065 */
3066static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3067{
3068 int err;
3069
3070 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3071 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3072 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3073 10, 1, can_sleep);
3074 if (err)
3075 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3076}
3077
7a3e97b0
SY		 3078/**
3079 * ufshcd_hba_enable - initialize the controller
3080 * @hba: per adapter instance
3081 *
3082 * The controller resets itself and controller firmware initialization
3083 * sequence kicks off. When controller is ready it will set
3084 * the Host Controller Enable bit to 1.
3085 *
3086 * Returns 0 on success, non-zero value on failure
3087 */
3088static int ufshcd_hba_enable(struct ufs_hba *hba)
3089{
3090 int retry;
3091
3092 /*
3093 * msleep of 1 and 5 used in this function might result in msleep(20),
3094 * but it was necessary to send the UFS FPGA to reset mode during
3095 * development and testing of this driver. msleep can be changed to
3096 * mdelay and retry count can be reduced based on the controller.
3097 */
596585a2 3098 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3099 /* change controller state to "reset state" */
596585a2 3100 ufshcd_hba_stop(hba, true);
7a3e97b0 3101
57d104c1
SJ		 3102 /* UniPro link is disabled at this point */
3103 ufshcd_set_link_off(hba);
3104
0263bcd0 3105 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3106
7a3e97b0
SY		 3107 /* start controller initialization sequence */
3108 ufshcd_hba_start(hba);
3109
3110 /*
3111 * To initialize a UFS host controller HCE bit must be set to 1.
3112 * During initialization the HCE bit value changes from 1->0->1.
3113 * When the host controller completes initialization sequence
3114 * it sets the value of HCE bit to 1. The same HCE bit is read back
3115 * to check if the controller has completed initialization sequence.
3116 * So without this delay the value HCE = 1, set in the previous
3117 * instruction might be read back.
3118 * This delay can be changed based on the controller.
3119 */
3120 msleep(1);
3121
3122 /* wait for the host controller to complete initialization */
3123 retry = 10;
3124 while (ufshcd_is_hba_active(hba)) {
3125 if (retry) {
3126 retry--;
3127 } else {
3b1d0580 3128 dev_err(hba->dev,
7a3e97b0
SY		 3129 "Controller enable failed\n");
3130 return -EIO;
3131 }
3132 msleep(5);
3133 }
5c0c28a8 3134
1d337ec2 3135 /* enable UIC related interrupts */
57d104c1 3136 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3137
0263bcd0 3138 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3139
7a3e97b0
SY		 3140 return 0;
3141}
3142
7ca38cf3
YG		 3143static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3144{
3145 int tx_lanes, i, err = 0;
3146
3147 if (!peer)
3148 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3149 &tx_lanes);
3150 else
3151 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3152 &tx_lanes);
3153 for (i = 0; i < tx_lanes; i++) {
3154 if (!peer)
3155 err = ufshcd_dme_set(hba,
3156 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3157 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3158 0);
3159 else
3160 err = ufshcd_dme_peer_set(hba,
3161 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3162 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3163 0);
3164 if (err) {
3165 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3166 __func__, peer, i, err);
3167 break;
3168 }
3169 }
3170
3171 return err;
3172}
3173
3174static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3175{
3176 return ufshcd_disable_tx_lcc(hba, true);
3177}
3178
7a3e97b0 3179/**
6ccf44fe 3180 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 3181 * @hba: per adapter instance
3182 *
6ccf44fe 3183 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3184 */
6ccf44fe 3185static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3186{
6ccf44fe 3187 int ret;
1d337ec2 3188 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 3189 bool link_startup_again = false;
7a3e97b0 3190
7caf489b 3191 /*
3192 * If UFS device isn't active then we will have to issue link startup
3193 * 2 times to make sure the device state move to active.
3194 */
3195 if (!ufshcd_is_ufs_dev_active(hba))
3196 link_startup_again = true;
3197
3198link_startup:
1d337ec2 3199 do {
0263bcd0 3200 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3201
1d337ec2 3202 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3203
1d337ec2
SRT		 3204 /* check if device is detected by inter-connect layer */
3205 if (!ret && !ufshcd_is_device_present(hba)) {
3206 dev_err(hba->dev, "%s: Device not present\n", __func__);
3207 ret = -ENXIO;
3208 goto out;
3209 }
6ccf44fe 3210
1d337ec2
SRT		 3211 /*
3212 * DME link lost indication is only received when link is up,
3213 * but we can't be sure if the link is up until link startup
3214 * succeeds. So reset the local Uni-Pro and try again.
3215 */
3216 if (ret && ufshcd_hba_enable(hba))
3217 goto out;
3218 } while (ret && retries--);
3219
3220 if (ret)
3221 /* failed to get the link up... retire */
5c0c28a8 3222 goto out;
5c0c28a8 3223
7caf489b 3224 if (link_startup_again) {
3225 link_startup_again = false;
3226 retries = DME_LINKSTARTUP_RETRIES;
3227 goto link_startup;
3228 }
3229
7ca38cf3
YG		 3230 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3231 ret = ufshcd_disable_device_tx_lcc(hba);
3232 if (ret)
3233 goto out;
3234 }
3235
5c0c28a8 3236 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 3237 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3238 if (ret)
3239 goto out;
7a3e97b0 3240
5c0c28a8 3241 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 3242out:
3243 if (ret)
3244 dev_err(hba->dev, "link startup failed %d\n", ret);
3245 return ret;
7a3e97b0
SY		 3246}
3247
5a0b0cb9
SRT		 3248/**
3249 * ufshcd_verify_dev_init() - Verify device initialization
3250 * @hba: per-adapter instance
3251 *
3252 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3253 * device Transport Protocol (UTP) layer is ready after a reset.
3254 * If the UTP layer at the device side is not initialized, it may
3255 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3256 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3257 */
3258static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3259{
3260 int err = 0;
3261 int retries;
3262
1ab27c9c 3263 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 3264 mutex_lock(&hba->dev_cmd.lock);
3265 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3266 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3267 NOP_OUT_TIMEOUT);
3268
3269 if (!err || err == -ETIMEDOUT)
3270 break;
3271
3272 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3273 }
3274 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3275 ufshcd_release(hba);
5a0b0cb9
SRT		 3276
3277 if (err)
3278 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3279 return err;
3280}
3281
0ce147d4
SJ		 3282/**
3283 * ufshcd_set_queue_depth - set lun queue depth
3284 * @sdev: pointer to SCSI device
3285 *
3286 * Read bLUQueueDepth value and activate scsi tagged command
3287 * queueing. For WLUN, queue depth is set to 1. For best-effort
3288 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3289 * value that host can queue.
3290 */
3291static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3292{
3293 int ret = 0;
3294 u8 lun_qdepth;
61e07359 3295 int retries;
0ce147d4
SJ		 3296 struct ufs_hba *hba;
3297
3298 hba = shost_priv(sdev->host);
3299
3300 lun_qdepth = hba->nutrs;
61e07359
DR		 3301 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3302 /* Read descriptor*/
3303 ret = ufshcd_read_unit_desc_param(hba,
3304 ufshcd_scsi_to_upiu_lun(sdev->lun),
3305 UNIT_DESC_PARAM_LU_Q_DEPTH,
3306 &lun_qdepth,
3307 sizeof(lun_qdepth));
3308 if (!ret || ret == -ENOTSUPP)
3309 break;
3310
3311 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
3312 }
0ce147d4
SJ		 3313
3314 /* Some WLUN doesn't support unit descriptor */
3315 if (ret == -EOPNOTSUPP)
3316 lun_qdepth = 1;
3317 else if (!lun_qdepth)
3318 /* eventually, we can figure out the real queue depth */
3319 lun_qdepth = hba->nutrs;
3320 else
3321 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3322
3323 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3324 __func__, lun_qdepth);
db5ed4df 3325 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 3326}
3327
57d104c1
SJ		 3328/*
3329 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3330 * @hba: per-adapter instance
3331 * @lun: UFS device lun id
3332 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3333 *
3334 * Returns 0 in case of success and b_lu_write_protect status would be returned
3335 * @b_lu_write_protect parameter.
3336 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3337 * Returns -EINVAL in case of invalid parameters passed to this function.
3338 */
3339static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3340 u8 lun,
3341 u8 *b_lu_write_protect)
3342{
3343 int ret;
3344
3345 if (!b_lu_write_protect)
3346 ret = -EINVAL;
3347 /*
3348 * According to UFS device spec, RPMB LU can't be write
3349 * protected so skip reading bLUWriteProtect parameter for
3350 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3351 */
3352 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3353 ret = -ENOTSUPP;
3354 else
3355 ret = ufshcd_read_unit_desc_param(hba,
3356 lun,
3357 UNIT_DESC_PARAM_LU_WR_PROTECT,
3358 b_lu_write_protect,
3359 sizeof(*b_lu_write_protect));
3360 return ret;
3361}
3362
3363/**
3364 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3365 * status
3366 * @hba: per-adapter instance
3367 * @sdev: pointer to SCSI device
3368 *
3369 */
3370static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3371 struct scsi_device *sdev)
3372{
3373 if (hba->dev_info.f_power_on_wp_en &&
3374 !hba->dev_info.is_lu_power_on_wp) {
3375 u8 b_lu_write_protect;
3376
3377 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3378 &b_lu_write_protect) &&
3379 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3380 hba->dev_info.is_lu_power_on_wp = true;
3381 }
3382}
3383
7a3e97b0
SY		 3384/**
3385 * ufshcd_slave_alloc - handle initial SCSI device configurations
3386 * @sdev: pointer to SCSI device
3387 *
3388 * Returns success
3389 */
3390static int ufshcd_slave_alloc(struct scsi_device *sdev)
3391{
3392 struct ufs_hba *hba;
3393
3394 hba = shost_priv(sdev->host);
7a3e97b0
SY		 3395
3396 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3397 sdev->use_10_for_ms = 1;
7a3e97b0 3398
e8e7f271
SRT		 3399 /* allow SCSI layer to restart the device in case of errors */
3400 sdev->allow_restart = 1;
4264fd61 3401
b2a6c522
SRT		 3402 /* REPORT SUPPORTED OPERATION CODES is not supported */
3403 sdev->no_report_opcodes = 1;
3404
e8e7f271 3405
0ce147d4 3406 ufshcd_set_queue_depth(sdev);
4264fd61 3407
57d104c1
SJ		 3408 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3409
7a3e97b0
SY		 3410 return 0;
3411}
3412
4264fd61
SRT		 3413/**
3414 * ufshcd_change_queue_depth - change queue depth
3415 * @sdev: pointer to SCSI device
3416 * @depth: required depth to set
4264fd61 3417 *
db5ed4df 3418 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3419 */
db5ed4df 3420static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 3421{
3422 struct ufs_hba *hba = shost_priv(sdev->host);
3423
3424 if (depth > hba->nutrs)
3425 depth = hba->nutrs;
db5ed4df 3426 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3427}
3428
eeda4749
AM		 3429/**
3430 * ufshcd_slave_configure - adjust SCSI device configurations
3431 * @sdev: pointer to SCSI device
3432 */
3433static int ufshcd_slave_configure(struct scsi_device *sdev)
3434{
3435 struct request_queue *q = sdev->request_queue;
3436
3437 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3438 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3439
3440 return 0;
3441}
3442
7a3e97b0
SY		 3443/**
3444 * ufshcd_slave_destroy - remove SCSI device configurations
3445 * @sdev: pointer to SCSI device
3446 */
3447static void ufshcd_slave_destroy(struct scsi_device *sdev)
3448{
3449 struct ufs_hba *hba;
3450
3451 hba = shost_priv(sdev->host);
0ce147d4 3452 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3453 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3454 unsigned long flags;
3455
3456 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3457 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3458 spin_unlock_irqrestore(hba->host->host_lock, flags);
3459 }
7a3e97b0
SY		 3460}
3461
3462/**
3463 * ufshcd_task_req_compl - handle task management request completion
3464 * @hba: per adapter instance
3465 * @index: index of the completed request
e2933132 3466 * @resp: task management service response
7a3e97b0 3467 *
e2933132 3468 * Returns non-zero value on error, zero on success
7a3e97b0 3469 */
e2933132 3470static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3471{
3472 struct utp_task_req_desc *task_req_descp;
3473 struct utp_upiu_task_rsp *task_rsp_upiup;
3474 unsigned long flags;
3475 int ocs_value;
3476 int task_result;
3477
3478 spin_lock_irqsave(hba->host->host_lock, flags);
3479
3480 /* Clear completed tasks from outstanding_tasks */
3481 __clear_bit(index, &hba->outstanding_tasks);
3482
3483 task_req_descp = hba->utmrdl_base_addr;
3484 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3485
3486 if (ocs_value == OCS_SUCCESS) {
3487 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3488 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 3489 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3490 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 3491 if (resp)
3492 *resp = (u8)task_result;
7a3e97b0 3493 } else {
e2933132
SRT		 3494 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3495 __func__, ocs_value);
7a3e97b0
SY		 3496 }
3497 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3498
3499 return ocs_value;
7a3e97b0
SY		 3500}
3501
7a3e97b0
SY		 3502/**
3503 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3504 * @lrb: pointer to local reference block of completed command
3505 * @scsi_status: SCSI command status
3506 *
3507 * Returns value base on SCSI command status
3508 */
3509static inline int
3510ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3511{
3512 int result = 0;
3513
3514 switch (scsi_status) {
7a3e97b0 3515 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3516 ufshcd_copy_sense_data(lrbp);
3517 case SAM_STAT_GOOD:
7a3e97b0
SY		 3518 result |= DID_OK << 16 |
3519 COMMAND_COMPLETE << 8 |
1c2623c5 3520 scsi_status;
7a3e97b0
SY		 3521 break;
3522 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3523 case SAM_STAT_BUSY:
7a3e97b0 3524 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3525 ufshcd_copy_sense_data(lrbp);
3526 result |= scsi_status;
7a3e97b0
SY		 3527 break;
3528 default:
3529 result |= DID_ERROR << 16;
3530 break;
3531 } /* end of switch */
3532
3533 return result;
3534}
3535
3536/**
3537 * ufshcd_transfer_rsp_status - Get overall status of the response
3538 * @hba: per adapter instance
3539 * @lrb: pointer to local reference block of completed command
3540 *
3541 * Returns result of the command to notify SCSI midlayer
3542 */
3543static inline int
3544ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3545{
3546 int result = 0;
3547 int scsi_status;
3548 int ocs;
3549
3550 /* overall command status of utrd */
3551 ocs = ufshcd_get_tr_ocs(lrbp);
3552
3553 switch (ocs) {
3554 case OCS_SUCCESS:
5a0b0cb9 3555 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3556
5a0b0cb9
SRT		 3557 switch (result) {
3558 case UPIU_TRANSACTION_RESPONSE:
3559 /*
3560 * get the response UPIU result to extract
3561 * the SCSI command status
3562 */
3563 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3564
3565 /*
3566 * get the result based on SCSI status response
3567 * to notify the SCSI midlayer of the command status
3568 */
3569 scsi_status = result & MASK_SCSI_STATUS;
3570 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3571
f05ac2e5
YG		 3572 /*
3573 * Currently we are only supporting BKOPs exception
3574 * events hence we can ignore BKOPs exception event
3575 * during power management callbacks. BKOPs exception
3576 * event is not expected to be raised in runtime suspend
3577 * callback as it allows the urgent bkops.
3578 * During system suspend, we are anyway forcefully
3579 * disabling the bkops and if urgent bkops is needed
3580 * it will be enabled on system resume. Long term
3581 * solution could be to abort the system suspend if
3582 * UFS device needs urgent BKOPs.
3583 */
3584 if (!hba->pm_op_in_progress &&
3585 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3586 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3587 break;
3588 case UPIU_TRANSACTION_REJECT_UPIU:
3589 /* TODO: handle Reject UPIU Response */
3590 result = DID_ERROR << 16;
3b1d0580 3591 dev_err(hba->dev,
5a0b0cb9
SRT		 3592 "Reject UPIU not fully implemented\n");
3593 break;
3594 default:
3595 result = DID_ERROR << 16;
3596 dev_err(hba->dev,
3597 "Unexpected request response code = %x\n",
3598 result);
7a3e97b0
SY		 3599 break;
3600 }
7a3e97b0
SY		 3601 break;
3602 case OCS_ABORTED:
3603 result |= DID_ABORT << 16;
3604 break;
e8e7f271
SRT		 3605 case OCS_INVALID_COMMAND_STATUS:
3606 result |= DID_REQUEUE << 16;
3607 break;
7a3e97b0
SY		 3608 case OCS_INVALID_CMD_TABLE_ATTR:
3609 case OCS_INVALID_PRDT_ATTR:
3610 case OCS_MISMATCH_DATA_BUF_SIZE:
3611 case OCS_MISMATCH_RESP_UPIU_SIZE:
3612 case OCS_PEER_COMM_FAILURE:
3613 case OCS_FATAL_ERROR:
3614 default:
3615 result |= DID_ERROR << 16;
3b1d0580 3616 dev_err(hba->dev,
7a3e97b0
SY		 3617 "OCS error from controller = %x\n", ocs);
3618 break;
3619 } /* end of switch */
3620
3621 return result;
3622}
3623
6ccf44fe
SJ		 3624/**
3625 * ufshcd_uic_cmd_compl - handle completion of uic command
3626 * @hba: per adapter instance
53b3d9c3 3627 * @intr_status: interrupt status generated by the controller
6ccf44fe 3628 */
53b3d9c3 3629static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3630{
53b3d9c3 3631 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3632 hba->active_uic_cmd->argument2 |=
3633 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3634 hba->active_uic_cmd->argument3 =
3635 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3636 complete(&hba->active_uic_cmd->done);
3637 }
53b3d9c3 3638
57d104c1
SJ		 3639 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3640 complete(hba->uic_async_done);
6ccf44fe
SJ		 3641}
3642
7a3e97b0 3643/**
9a47ec7c 3644 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3645 * @hba: per adapter instance
9a47ec7c 3646 * @completed_reqs: requests to complete
7a3e97b0 3647 */
9a47ec7c
YG		 3648static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3649 unsigned long completed_reqs)
7a3e97b0 3650{
5a0b0cb9
SRT		 3651 struct ufshcd_lrb *lrbp;
3652 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3653 int result;
3654 int index;
e9d501b1 3655
e9d501b1
DR		 3656 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3657 lrbp = &hba->lrb[index];
3658 cmd = lrbp->cmd;
3659 if (cmd) {
3660 result = ufshcd_transfer_rsp_status(hba, lrbp);
3661 scsi_dma_unmap(cmd);
3662 cmd->result = result;
3663 /* Mark completed command as NULL in LRB */
3664 lrbp->cmd = NULL;
3665 clear_bit_unlock(index, &hba->lrb_in_use);
3666 /* Do not touch lrbp after scsi done */
3667 cmd->scsi_done(cmd);
1ab27c9c 3668 __ufshcd_release(hba);
300bb13f
JP		 3669 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3670 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR		 3671 if (hba->dev_cmd.complete)
3672 complete(hba->dev_cmd.complete);
3673 }
3674 }
7a3e97b0
SY		 3675
3676 /* clear corresponding bits of completed commands */
3677 hba->outstanding_reqs ^= completed_reqs;
3678
856b3483
ST		 3679 ufshcd_clk_scaling_update_busy(hba);
3680
5a0b0cb9
SRT		 3681 /* we might have free'd some tags above */
3682 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3683}
3684
9a47ec7c
YG		 3685/**
3686 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3687 * @hba: per adapter instance
3688 */
3689static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3690{
3691 unsigned long completed_reqs;
3692 u32 tr_doorbell;
3693
3694 /* Resetting interrupt aggregation counters first and reading the
3695 * DOOR_BELL afterward allows us to handle all the completed requests.
3696 * In order to prevent other interrupts starvation the DB is read once
3697 * after reset. The down side of this solution is the possibility of
3698 * false interrupt if device completes another request after resetting
3699 * aggregation and before reading the DB.
3700 */
3701 if (ufshcd_is_intr_aggr_allowed(hba))
3702 ufshcd_reset_intr_aggr(hba);
3703
3704 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3705 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3706
3707 __ufshcd_transfer_req_compl(hba, completed_reqs);
3708}
3709
66ec6d59
SRT		 3710/**
3711 * ufshcd_disable_ee - disable exception event
3712 * @hba: per-adapter instance
3713 * @mask: exception event to disable
3714 *
3715 * Disables exception event in the device so that the EVENT_ALERT
3716 * bit is not set.
3717 *
3718 * Returns zero on success, non-zero error value on failure.
3719 */
3720static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3721{
3722 int err = 0;
3723 u32 val;
3724
3725 if (!(hba->ee_ctrl_mask & mask))
3726 goto out;
3727
3728 val = hba->ee_ctrl_mask & ~mask;
3729 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3730 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3731 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3732 if (!err)
3733 hba->ee_ctrl_mask &= ~mask;
3734out:
3735 return err;
3736}
3737
3738/**
3739 * ufshcd_enable_ee - enable exception event
3740 * @hba: per-adapter instance
3741 * @mask: exception event to enable
3742 *
3743 * Enable corresponding exception event in the device to allow
3744 * device to alert host in critical scenarios.
3745 *
3746 * Returns zero on success, non-zero error value on failure.
3747 */
3748static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3749{
3750 int err = 0;
3751 u32 val;
3752
3753 if (hba->ee_ctrl_mask & mask)
3754 goto out;
3755
3756 val = hba->ee_ctrl_mask | mask;
3757 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3758 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3759 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3760 if (!err)
3761 hba->ee_ctrl_mask |= mask;
3762out:
3763 return err;
3764}
3765
3766/**
3767 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3768 * @hba: per-adapter instance
3769 *
3770 * Allow device to manage background operations on its own. Enabling
3771 * this might lead to inconsistent latencies during normal data transfers
3772 * as the device is allowed to manage its own way of handling background
3773 * operations.
3774 *
3775 * Returns zero on success, non-zero on failure.
3776 */
3777static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3778{
3779 int err = 0;
3780
3781 if (hba->auto_bkops_enabled)
3782 goto out;
3783
dc3c8d3a 3784 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 3785 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3786 if (err) {
3787 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3788 __func__, err);
3789 goto out;
3790 }
3791
3792 hba->auto_bkops_enabled = true;
3793
3794 /* No need of URGENT_BKOPS exception from the device */
3795 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3796 if (err)
3797 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3798 __func__, err);
3799out:
3800 return err;
3801}
3802
3803/**
3804 * ufshcd_disable_auto_bkops - block device in doing background operations
3805 * @hba: per-adapter instance
3806 *
3807 * Disabling background operations improves command response latency but
3808 * has drawback of device moving into critical state where the device is
3809 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3810 * host is idle so that BKOPS are managed effectively without any negative
3811 * impacts.
3812 *
3813 * Returns zero on success, non-zero on failure.
3814 */
3815static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3816{
3817 int err = 0;
3818
3819 if (!hba->auto_bkops_enabled)
3820 goto out;
3821
3822 /*
3823 * If host assisted BKOPs is to be enabled, make sure
3824 * urgent bkops exception is allowed.
3825 */
3826 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3827 if (err) {
3828 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3829 __func__, err);
3830 goto out;
3831 }
3832
dc3c8d3a 3833 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 3834 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3835 if (err) {
3836 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3837 __func__, err);
3838 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3839 goto out;
3840 }
3841
3842 hba->auto_bkops_enabled = false;
3843out:
3844 return err;
3845}
3846
3847/**
3848 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3849 * @hba: per adapter instance
3850 *
3851 * After a device reset the device may toggle the BKOPS_EN flag
3852 * to default value. The s/w tracking variables should be updated
3853 * as well. Do this by forcing enable of auto bkops.
3854 */
3855static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3856{
3857 hba->auto_bkops_enabled = false;
3858 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3859 ufshcd_enable_auto_bkops(hba);
3860}
3861
3862static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3863{
5e86ae44 3864 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3865 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3866}
3867
3868/**
57d104c1 3869 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3870 * @hba: per-adapter instance
57d104c1 3871 * @status: bkops_status value
66ec6d59 3872 *
57d104c1
SJ		 3873 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3874 * flag in the device to permit background operations if the device
3875 * bkops_status is greater than or equal to "status" argument passed to
3876 * this function, disable otherwise.
3877 *
3878 * Returns 0 for success, non-zero in case of failure.
3879 *
3880 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3881 * to know whether auto bkops is enabled or disabled after this function
3882 * returns control to it.
66ec6d59 3883 */
57d104c1
SJ		 3884static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3885 enum bkops_status status)
66ec6d59
SRT		 3886{
3887 int err;
57d104c1 3888 u32 curr_status = 0;
66ec6d59 3889
57d104c1 3890 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3891 if (err) {
3892 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3893 __func__, err);
3894 goto out;
57d104c1
SJ		 3895 } else if (curr_status > BKOPS_STATUS_MAX) {
3896 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3897 __func__, curr_status);
3898 err = -EINVAL;
3899 goto out;
66ec6d59
SRT		 3900 }
3901
57d104c1 3902 if (curr_status >= status)
66ec6d59 3903 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3904 else
3905 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3906out:
3907 return err;
3908}
3909
57d104c1
SJ		 3910/**
3911 * ufshcd_urgent_bkops - handle urgent bkops exception event
3912 * @hba: per-adapter instance
3913 *
3914 * Enable fBackgroundOpsEn flag in the device to permit background
3915 * operations.
3916 *
3917 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3918 * and negative error value for any other failure.
3919 */
3920static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3921{
afdfff59 3922 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 3923}
3924
66ec6d59
SRT		 3925static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3926{
5e86ae44 3927 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3928 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3929}
3930
afdfff59
YG		 3931static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
3932{
3933 int err;
3934 u32 curr_status = 0;
3935
3936 if (hba->is_urgent_bkops_lvl_checked)
3937 goto enable_auto_bkops;
3938
3939 err = ufshcd_get_bkops_status(hba, &curr_status);
3940 if (err) {
3941 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3942 __func__, err);
3943 goto out;
3944 }
3945
3946 /*
3947 * We are seeing that some devices are raising the urgent bkops
3948 * exception events even when BKOPS status doesn't indicate performace
3949 * impacted or critical. Handle these device by determining their urgent
3950 * bkops status at runtime.
3951 */
3952 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
3953 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
3954 __func__, curr_status);
3955 /* update the current status as the urgent bkops level */
3956 hba->urgent_bkops_lvl = curr_status;
3957 hba->is_urgent_bkops_lvl_checked = true;
3958 }
3959
3960enable_auto_bkops:
3961 err = ufshcd_enable_auto_bkops(hba);
3962out:
3963 if (err < 0)
3964 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3965 __func__, err);
3966}
3967
66ec6d59
SRT		 3968/**
3969 * ufshcd_exception_event_handler - handle exceptions raised by device
3970 * @work: pointer to work data
3971 *
3972 * Read bExceptionEventStatus attribute from the device and handle the
3973 * exception event accordingly.
3974 */
3975static void ufshcd_exception_event_handler(struct work_struct *work)
3976{
3977 struct ufs_hba *hba;
3978 int err;
3979 u32 status = 0;
3980 hba = container_of(work, struct ufs_hba, eeh_work);
3981
62694735 3982 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3983 err = ufshcd_get_ee_status(hba, &status);
3984 if (err) {
3985 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3986 __func__, err);
3987 goto out;
3988 }
3989
3990 status &= hba->ee_ctrl_mask;
afdfff59
YG		 3991
3992 if (status & MASK_EE_URGENT_BKOPS)
3993 ufshcd_bkops_exception_event_handler(hba);
3994
66ec6d59 3995out:
62694735 3996 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3997 return;
3998}
3999
9a47ec7c
YG		 4000/* Complete requests that have door-bell cleared */
4001static void ufshcd_complete_requests(struct ufs_hba *hba)
4002{
4003 ufshcd_transfer_req_compl(hba);
4004 ufshcd_tmc_handler(hba);
4005}
4006
583fa62d
YG		 4007/**
4008 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4009 * to recover from the DL NAC errors or not.
4010 * @hba: per-adapter instance
4011 *
4012 * Returns true if error handling is required, false otherwise
4013 */
4014static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4015{
4016 unsigned long flags;
4017 bool err_handling = true;
4018
4019 spin_lock_irqsave(hba->host->host_lock, flags);
4020 /*
4021 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4022 * device fatal error and/or DL NAC & REPLAY timeout errors.
4023 */
4024 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4025 goto out;
4026
4027 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4028 ((hba->saved_err & UIC_ERROR) &&
4029 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4030 goto out;
4031
4032 if ((hba->saved_err & UIC_ERROR) &&
4033 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4034 int err;
4035 /*
4036 * wait for 50ms to see if we can get any other errors or not.
4037 */
4038 spin_unlock_irqrestore(hba->host->host_lock, flags);
4039 msleep(50);
4040 spin_lock_irqsave(hba->host->host_lock, flags);
4041
4042 /*
4043 * now check if we have got any other severe errors other than
4044 * DL NAC error?
4045 */
4046 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4047 ((hba->saved_err & UIC_ERROR) &&
4048 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4049 goto out;
4050
4051 /*
4052 * As DL NAC is the only error received so far, send out NOP
4053 * command to confirm if link is still active or not.
4054 * - If we don't get any response then do error recovery.
4055 * - If we get response then clear the DL NAC error bit.
4056 */
4057
4058 spin_unlock_irqrestore(hba->host->host_lock, flags);
4059 err = ufshcd_verify_dev_init(hba);
4060 spin_lock_irqsave(hba->host->host_lock, flags);
4061
4062 if (err)
4063 goto out;
4064
4065 /* Link seems to be alive hence ignore the DL NAC errors */
4066 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
4067 hba->saved_err &= ~UIC_ERROR;
4068 /* clear NAC error */
4069 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4070 if (!hba->saved_uic_err) {
4071 err_handling = false;
4072 goto out;
4073 }
4074 }
4075out:
4076 spin_unlock_irqrestore(hba->host->host_lock, flags);
4077 return err_handling;
4078}
4079
7a3e97b0 4080/**
e8e7f271
SRT		 4081 * ufshcd_err_handler - handle UFS errors that require s/w attention
4082 * @work: pointer to work structure
7a3e97b0 4083 */
e8e7f271 4084static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 4085{
4086 struct ufs_hba *hba;
e8e7f271
SRT		 4087 unsigned long flags;
4088 u32 err_xfer = 0;
4089 u32 err_tm = 0;
4090 int err = 0;
4091 int tag;
9a47ec7c 4092 bool needs_reset = false;
e8e7f271
SRT		 4093
4094 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 4095
62694735 4096 pm_runtime_get_sync(hba->dev);
1ab27c9c 4097 ufshcd_hold(hba, false);
e8e7f271
SRT		 4098
4099 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 4100 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 4101 goto out;
e8e7f271
SRT		 4102
4103 hba->ufshcd_state = UFSHCD_STATE_RESET;
4104 ufshcd_set_eh_in_progress(hba);
4105
4106 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 4107 ufshcd_complete_requests(hba);
583fa62d
YG		 4108
4109 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4110 bool ret;
4111
4112 spin_unlock_irqrestore(hba->host->host_lock, flags);
4113 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
4114 ret = ufshcd_quirk_dl_nac_errors(hba);
4115 spin_lock_irqsave(hba->host->host_lock, flags);
4116 if (!ret)
4117 goto skip_err_handling;
4118 }
9a47ec7c
YG		 4119 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4120 ((hba->saved_err & UIC_ERROR) &&
4121 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4122 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4123 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4124 needs_reset = true;
e8e7f271 4125
9a47ec7c
YG		 4126 /*
4127 * if host reset is required then skip clearing the pending
4128 * transfers forcefully because they will automatically get
4129 * cleared after link startup.
4130 */
4131 if (needs_reset)
4132 goto skip_pending_xfer_clear;
4133
4134 /* release lock as clear command might sleep */
4135 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4136 /* Clear pending transfer requests */
9a47ec7c
YG		 4137 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4138 if (ufshcd_clear_cmd(hba, tag)) {
4139 err_xfer = true;
4140 goto lock_skip_pending_xfer_clear;
4141 }
4142 }
e8e7f271
SRT		 4143
4144 /* Clear pending task management requests */
9a47ec7c
YG		 4145 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4146 if (ufshcd_clear_tm_cmd(hba, tag)) {
4147 err_tm = true;
4148 goto lock_skip_pending_xfer_clear;
4149 }
4150 }
e8e7f271 4151
9a47ec7c 4152lock_skip_pending_xfer_clear:
e8e7f271 4153 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4154
9a47ec7c
YG		 4155 /* Complete the requests that are cleared by s/w */
4156 ufshcd_complete_requests(hba);
4157
4158 if (err_xfer || err_tm)
4159 needs_reset = true;
4160
4161skip_pending_xfer_clear:
e8e7f271 4162 /* Fatal errors need reset */
9a47ec7c
YG		 4163 if (needs_reset) {
4164 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4165
4166 /*
4167 * ufshcd_reset_and_restore() does the link reinitialization
4168 * which will need atleast one empty doorbell slot to send the
4169 * device management commands (NOP and query commands).
4170 * If there is no slot empty at this moment then free up last
4171 * slot forcefully.
4172 */
4173 if (hba->outstanding_reqs == max_doorbells)
4174 __ufshcd_transfer_req_compl(hba,
4175 (1UL << (hba->nutrs - 1)));
4176
4177 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4178 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4179 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 4180 if (err) {
4181 dev_err(hba->dev, "%s: reset and restore failed\n",
4182 __func__);
4183 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4184 }
4185 /*
4186 * Inform scsi mid-layer that we did reset and allow to handle
4187 * Unit Attention properly.
4188 */
4189 scsi_report_bus_reset(hba->host, 0);
4190 hba->saved_err = 0;
4191 hba->saved_uic_err = 0;
4192 }
9a47ec7c 4193
583fa62d 4194skip_err_handling:
9a47ec7c
YG		 4195 if (!needs_reset) {
4196 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4197 if (hba->saved_err || hba->saved_uic_err)
4198 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4199 __func__, hba->saved_err, hba->saved_uic_err);
4200 }
4201
e8e7f271
SRT		 4202 ufshcd_clear_eh_in_progress(hba);
4203
4204out:
9a47ec7c 4205 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4206 scsi_unblock_requests(hba->host);
1ab27c9c 4207 ufshcd_release(hba);
62694735 4208 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 4209}
4210
4211/**
e8e7f271
SRT		 4212 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4213 * @hba: per-adapter instance
7a3e97b0 4214 */
e8e7f271 4215static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 4216{
4217 u32 reg;
4218
fb7b45f0
DR		 4219 /* PHY layer lane error */
4220 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4221 /* Ignore LINERESET indication, as this is not an error */
4222 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
4223 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK))
4224 /*
4225 * To know whether this error is fatal or not, DB timeout
4226 * must be checked but this error is handled separately.
4227 */
4228 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
4229
e8e7f271
SRT		 4230 /* PA_INIT_ERROR is fatal and needs UIC reset */
4231 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4232 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4233 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 4234 else if (hba->dev_quirks &
4235 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4236 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4237 hba->uic_error |=
4238 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4239 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4240 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4241 }
e8e7f271
SRT		 4242
4243 /* UIC NL/TL/DME errors needs software retry */
4244 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4245 if (reg)
4246 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4247
4248 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4249 if (reg)
4250 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4251
4252 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4253 if (reg)
4254 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4255
4256 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4257 __func__, hba->uic_error);
4258}
4259
4260/**
4261 * ufshcd_check_errors - Check for errors that need s/w attention
4262 * @hba: per-adapter instance
4263 */
4264static void ufshcd_check_errors(struct ufs_hba *hba)
4265{
4266 bool queue_eh_work = false;
4267
7a3e97b0 4268 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4269 queue_eh_work = true;
7a3e97b0
SY		 4270
4271 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 4272 hba->uic_error = 0;
4273 ufshcd_update_uic_error(hba);
4274 if (hba->uic_error)
4275 queue_eh_work = true;
7a3e97b0 4276 }
e8e7f271
SRT		 4277
4278 if (queue_eh_work) {
9a47ec7c
YG		 4279 /*
4280 * update the transfer error masks to sticky bits, let's do this
4281 * irrespective of current ufshcd_state.
4282 */
4283 hba->saved_err |= hba->errors;
4284 hba->saved_uic_err |= hba->uic_error;
4285
e8e7f271
SRT		 4286 /* handle fatal errors only when link is functional */
4287 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4288 /* block commands from scsi mid-layer */
4289 scsi_block_requests(hba->host);
4290
141f8165 4291 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
e8e7f271
SRT		 4292 schedule_work(&hba->eh_work);
4293 }
3441da7d 4294 }
e8e7f271
SRT		 4295 /*
4296 * if (!queue_eh_work) -
4297 * Other errors are either non-fatal where host recovers
4298 * itself without s/w intervention or errors that will be
4299 * handled by the SCSI core layer.
4300 */
7a3e97b0
SY		 4301}
4302
4303/**
4304 * ufshcd_tmc_handler - handle task management function completion
4305 * @hba: per adapter instance
4306 */
4307static void ufshcd_tmc_handler(struct ufs_hba *hba)
4308{
4309 u32 tm_doorbell;
4310
b873a275 4311 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4312 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4313 wake_up(&hba->tm_wq);
7a3e97b0
SY		 4314}
4315
4316/**
4317 * ufshcd_sl_intr - Interrupt service routine
4318 * @hba: per adapter instance
4319 * @intr_status: contains interrupts generated by the controller
4320 */
4321static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4322{
4323 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4324 if (hba->errors)
e8e7f271 4325 ufshcd_check_errors(hba);
7a3e97b0 4326
53b3d9c3
SJ		 4327 if (intr_status & UFSHCD_UIC_MASK)
4328 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 4329
4330 if (intr_status & UTP_TASK_REQ_COMPL)
4331 ufshcd_tmc_handler(hba);
4332
4333 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4334 ufshcd_transfer_req_compl(hba);
4335}
4336
4337/**
4338 * ufshcd_intr - Main interrupt service routine
4339 * @irq: irq number
4340 * @__hba: pointer to adapter instance
4341 *
4342 * Returns IRQ_HANDLED - If interrupt is valid
4343 * IRQ_NONE - If invalid interrupt
4344 */
4345static irqreturn_t ufshcd_intr(int irq, void *__hba)
4346{
d75f7fe4 4347 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 4348 irqreturn_t retval = IRQ_NONE;
4349 struct ufs_hba *hba = __hba;
4350
4351 spin_lock(hba->host->host_lock);
b873a275 4352 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4353 enabled_intr_status =
4354 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4355
d75f7fe4 4356 if (intr_status)
261ea452 4357 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4358
4359 if (enabled_intr_status) {
4360 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 4361 retval = IRQ_HANDLED;
4362 }
4363 spin_unlock(hba->host->host_lock);
4364 return retval;
4365}
4366
e2933132
SRT		 4367static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4368{
4369 int err = 0;
4370 u32 mask = 1 << tag;
4371 unsigned long flags;
4372
4373 if (!test_bit(tag, &hba->outstanding_tasks))
4374 goto out;
4375
4376 spin_lock_irqsave(hba->host->host_lock, flags);
4377 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4378 spin_unlock_irqrestore(hba->host->host_lock, flags);
4379
4380 /* poll for max. 1 sec to clear door bell register by h/w */
4381 err = ufshcd_wait_for_register(hba,
4382 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4383 mask, 0, 1000, 1000, true);
e2933132
SRT		 4384out:
4385 return err;
4386}
4387
7a3e97b0
SY		 4388/**
4389 * ufshcd_issue_tm_cmd - issues task management commands to controller
4390 * @hba: per adapter instance
e2933132
SRT		 4391 * @lun_id: LUN ID to which TM command is sent
4392 * @task_id: task ID to which the TM command is applicable
4393 * @tm_function: task management function opcode
4394 * @tm_response: task management service response return value
7a3e97b0 4395 *
e2933132 4396 * Returns non-zero value on error, zero on success.
7a3e97b0 4397 */
e2933132
SRT		 4398static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4399 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 4400{
4401 struct utp_task_req_desc *task_req_descp;
4402 struct utp_upiu_task_req *task_req_upiup;
4403 struct Scsi_Host *host;
4404 unsigned long flags;
e2933132 4405 int free_slot;
7a3e97b0 4406 int err;
e2933132 4407 int task_tag;
7a3e97b0
SY		 4408
4409 host = hba->host;
4410
e2933132
SRT		 4411 /*
4412 * Get free slot, sleep if slots are unavailable.
4413 * Even though we use wait_event() which sleeps indefinitely,
4414 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4415 */
4416 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4417 ufshcd_hold(hba, false);
7a3e97b0 4418
e2933132 4419 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 4420 task_req_descp = hba->utmrdl_base_addr;
4421 task_req_descp += free_slot;
4422
4423 /* Configure task request descriptor */
4424 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4425 task_req_descp->header.dword_2 =
4426 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4427
4428 /* Configure task request UPIU */
4429 task_req_upiup =
4430 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4431 task_tag = hba->nutrs + free_slot;
7a3e97b0 4432 task_req_upiup->header.dword_0 =
5a0b0cb9 4433 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4434 lun_id, task_tag);
7a3e97b0 4435 task_req_upiup->header.dword_1 =
5a0b0cb9 4436 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 4437 /*
4438 * The host shall provide the same value for LUN field in the basic
4439 * header and for Input Parameter.
4440 */
e2933132
SRT		 4441 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4442 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 4443
d2877be4
KK		 4444 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
4445
7a3e97b0
SY		 4446 /* send command to the controller */
4447 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 4448
4449 /* Make sure descriptors are ready before ringing the task doorbell */
4450 wmb();
4451
b873a275 4452 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 4453 /* Make sure that doorbell is committed immediately */
4454 wmb();
7a3e97b0
SY		 4455
4456 spin_unlock_irqrestore(host->host_lock, flags);
4457
4458 /* wait until the task management command is completed */
e2933132
SRT		 4459 err = wait_event_timeout(hba->tm_wq,
4460 test_bit(free_slot, &hba->tm_condition),
4461 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4462 if (!err) {
e2933132
SRT		 4463 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4464 __func__, tm_function);
4465 if (ufshcd_clear_tm_cmd(hba, free_slot))
4466 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4467 __func__, free_slot);
4468 err = -ETIMEDOUT;
4469 } else {
4470 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4471 }
e2933132 4472
7a3e97b0 4473 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 4474 ufshcd_put_tm_slot(hba, free_slot);
4475 wake_up(&hba->tm_tag_wq);
4476
1ab27c9c 4477 ufshcd_release(hba);
7a3e97b0
SY		 4478 return err;
4479}
4480
4481/**
3441da7d
SRT		 4482 * ufshcd_eh_device_reset_handler - device reset handler registered to
4483 * scsi layer.
7a3e97b0
SY		 4484 * @cmd: SCSI command pointer
4485 *
4486 * Returns SUCCESS/FAILED
4487 */
3441da7d 4488static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 4489{
4490 struct Scsi_Host *host;
4491 struct ufs_hba *hba;
4492 unsigned int tag;
4493 u32 pos;
4494 int err;
e2933132
SRT		 4495 u8 resp = 0xF;
4496 struct ufshcd_lrb *lrbp;
3441da7d 4497 unsigned long flags;
7a3e97b0
SY		 4498
4499 host = cmd->device->host;
4500 hba = shost_priv(host);
4501 tag = cmd->request->tag;
4502
e2933132
SRT		 4503 lrbp = &hba->lrb[tag];
4504 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4505 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 4506 if (!err)
4507 err = resp;
7a3e97b0 4508 goto out;
e2933132 4509 }
7a3e97b0 4510
3441da7d
SRT		 4511 /* clear the commands that were pending for corresponding LUN */
4512 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4513 if (hba->lrb[pos].lun == lrbp->lun) {
4514 err = ufshcd_clear_cmd(hba, pos);
4515 if (err)
4516 break;
7a3e97b0 4517 }
3441da7d
SRT		 4518 }
4519 spin_lock_irqsave(host->host_lock, flags);
4520 ufshcd_transfer_req_compl(hba);
4521 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4522out:
3441da7d
SRT		 4523 if (!err) {
4524 err = SUCCESS;
4525 } else {
4526 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4527 err = FAILED;
4528 }
7a3e97b0
SY		 4529 return err;
4530}
4531
7a3e97b0
SY		 4532/**
4533 * ufshcd_abort - abort a specific command
4534 * @cmd: SCSI command pointer
4535 *
f20810d8
SRT		 4536 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4537 * command, and in host controller by clearing the door-bell register. There can
4538 * be race between controller sending the command to the device while abort is
4539 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4540 * really issued and then try to abort it.
4541 *
7a3e97b0
SY		 4542 * Returns SUCCESS/FAILED
4543 */
4544static int ufshcd_abort(struct scsi_cmnd *cmd)
4545{
4546 struct Scsi_Host *host;
4547 struct ufs_hba *hba;
4548 unsigned long flags;
4549 unsigned int tag;
f20810d8
SRT		 4550 int err = 0;
4551 int poll_cnt;
e2933132
SRT		 4552 u8 resp = 0xF;
4553 struct ufshcd_lrb *lrbp;
e9d501b1 4554 u32 reg;
7a3e97b0
SY		 4555
4556 host = cmd->device->host;
4557 hba = shost_priv(host);
4558 tag = cmd->request->tag;
14497328
YG		 4559 if (!ufshcd_valid_tag(hba, tag)) {
4560 dev_err(hba->dev,
4561 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4562 __func__, tag, cmd, cmd->request);
4563 BUG();
4564 }
7a3e97b0 4565
1ab27c9c 4566 ufshcd_hold(hba, false);
14497328 4567 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4568 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 4569 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4570 dev_err(hba->dev,
4571 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4572 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4573 goto out;
14497328 4574 }
7a3e97b0 4575
e9d501b1
DR		 4576 if (!(reg & (1 << tag))) {
4577 dev_err(hba->dev,
4578 "%s: cmd was completed, but without a notifying intr, tag = %d",
4579 __func__, tag);
4580 }
4581
f20810d8
SRT		 4582 lrbp = &hba->lrb[tag];
4583 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4584 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4585 UFS_QUERY_TASK, &resp);
4586 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4587 /* cmd pending in the device */
4588 break;
4589 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4590 /*
4591 * cmd not pending in the device, check if it is
4592 * in transition.
4593 */
4594 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4595 if (reg & (1 << tag)) {
4596 /* sleep for max. 200us to stabilize */
4597 usleep_range(100, 200);
4598 continue;
4599 }
4600 /* command completed already */
4601 goto out;
4602 } else {
4603 if (!err)
4604 err = resp; /* service response error */
4605 goto out;
4606 }
4607 }
4608
4609 if (!poll_cnt) {
4610 err = -EBUSY;
7a3e97b0
SY		 4611 goto out;
4612 }
7a3e97b0 4613
e2933132
SRT		 4614 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4615 UFS_ABORT_TASK, &resp);
4616 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4617 if (!err)
4618 err = resp; /* service response error */
7a3e97b0 4619 goto out;
e2933132 4620 }
7a3e97b0 4621
f20810d8
SRT		 4622 err = ufshcd_clear_cmd(hba, tag);
4623 if (err)
4624 goto out;
4625
7a3e97b0
SY		 4626 scsi_dma_unmap(cmd);
4627
4628 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4629 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 4630 hba->lrb[tag].cmd = NULL;
4631 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 4632
4633 clear_bit_unlock(tag, &hba->lrb_in_use);
4634 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4635
7a3e97b0 4636out:
f20810d8
SRT		 4637 if (!err) {
4638 err = SUCCESS;
4639 } else {
4640 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4641 err = FAILED;
4642 }
4643
1ab27c9c
ST		 4644 /*
4645 * This ufshcd_release() corresponds to the original scsi cmd that got
4646 * aborted here (as we won't get any IRQ for it).
4647 */
4648 ufshcd_release(hba);
7a3e97b0
SY		 4649 return err;
4650}
4651
3441da7d
SRT		 4652/**
4653 * ufshcd_host_reset_and_restore - reset and restore host controller
4654 * @hba: per-adapter instance
4655 *
4656 * Note that host controller reset may issue DME_RESET to
4657 * local and remote (device) Uni-Pro stack and the attributes
4658 * are reset to default state.
4659 *
4660 * Returns zero on success, non-zero on failure
4661 */
4662static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4663{
4664 int err;
3441da7d
SRT		 4665 unsigned long flags;
4666
4667 /* Reset the host controller */
4668 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4669 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 4670 spin_unlock_irqrestore(hba->host->host_lock, flags);
4671
4672 err = ufshcd_hba_enable(hba);
4673 if (err)
4674 goto out;
4675
4676 /* Establish the link again and restore the device */
1d337ec2
SRT		 4677 err = ufshcd_probe_hba(hba);
4678
4679 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 4680 err = -EIO;
4681out:
4682 if (err)
4683 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4684
4685 return err;
4686}
4687
4688/**
4689 * ufshcd_reset_and_restore - reset and re-initialize host/device
4690 * @hba: per-adapter instance
4691 *
4692 * Reset and recover device, host and re-establish link. This
4693 * is helpful to recover the communication in fatal error conditions.
4694 *
4695 * Returns zero on success, non-zero on failure
4696 */
4697static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4698{
4699 int err = 0;
4700 unsigned long flags;
1d337ec2 4701 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4702
1d337ec2
SRT		 4703 do {
4704 err = ufshcd_host_reset_and_restore(hba);
4705 } while (err && --retries);
3441da7d
SRT		 4706
4707 /*
4708 * After reset the door-bell might be cleared, complete
4709 * outstanding requests in s/w here.
4710 */
4711 spin_lock_irqsave(hba->host->host_lock, flags);
4712 ufshcd_transfer_req_compl(hba);
4713 ufshcd_tmc_handler(hba);
4714 spin_unlock_irqrestore(hba->host->host_lock, flags);
4715
4716 return err;
4717}
4718
4719/**
4720 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4721 * @cmd - SCSI command pointer
4722 *
4723 * Returns SUCCESS/FAILED
4724 */
4725static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4726{
4727 int err;
4728 unsigned long flags;
4729 struct ufs_hba *hba;
4730
4731 hba = shost_priv(cmd->device->host);
4732
1ab27c9c 4733 ufshcd_hold(hba, false);
3441da7d
SRT		 4734 /*
4735 * Check if there is any race with fatal error handling.
4736 * If so, wait for it to complete. Even though fatal error
4737 * handling does reset and restore in some cases, don't assume
4738 * anything out of it. We are just avoiding race here.
4739 */
4740 do {
4741 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4742 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 4743 hba->ufshcd_state == UFSHCD_STATE_RESET))
4744 break;
4745 spin_unlock_irqrestore(hba->host->host_lock, flags);
4746 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4747 flush_work(&hba->eh_work);
3441da7d
SRT		 4748 } while (1);
4749
4750 hba->ufshcd_state = UFSHCD_STATE_RESET;
4751 ufshcd_set_eh_in_progress(hba);
4752 spin_unlock_irqrestore(hba->host->host_lock, flags);
4753
4754 err = ufshcd_reset_and_restore(hba);
4755
4756 spin_lock_irqsave(hba->host->host_lock, flags);
4757 if (!err) {
4758 err = SUCCESS;
4759 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4760 } else {
4761 err = FAILED;
4762 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4763 }
4764 ufshcd_clear_eh_in_progress(hba);
4765 spin_unlock_irqrestore(hba->host->host_lock, flags);
4766
1ab27c9c 4767 ufshcd_release(hba);
3441da7d
SRT		 4768 return err;
4769}
4770
3a4bf06d
YG		 4771/**
4772 * ufshcd_get_max_icc_level - calculate the ICC level
4773 * @sup_curr_uA: max. current supported by the regulator
4774 * @start_scan: row at the desc table to start scan from
4775 * @buff: power descriptor buffer
4776 *
4777 * Returns calculated max ICC level for specific regulator
4778 */
4779static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4780{
4781 int i;
4782 int curr_uA;
4783 u16 data;
4784 u16 unit;
4785
4786 for (i = start_scan; i >= 0; i--) {
4787 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4788 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4789 ATTR_ICC_LVL_UNIT_OFFSET;
4790 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4791 switch (unit) {
4792 case UFSHCD_NANO_AMP:
4793 curr_uA = curr_uA / 1000;
4794 break;
4795 case UFSHCD_MILI_AMP:
4796 curr_uA = curr_uA * 1000;
4797 break;
4798 case UFSHCD_AMP:
4799 curr_uA = curr_uA * 1000 * 1000;
4800 break;
4801 case UFSHCD_MICRO_AMP:
4802 default:
4803 break;
4804 }
4805 if (sup_curr_uA >= curr_uA)
4806 break;
4807 }
4808 if (i < 0) {
4809 i = 0;
4810 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4811 }
4812
4813 return (u32)i;
4814}
4815
4816/**
4817 * ufshcd_calc_icc_level - calculate the max ICC level
4818 * In case regulators are not initialized we'll return 0
4819 * @hba: per-adapter instance
4820 * @desc_buf: power descriptor buffer to extract ICC levels from.
4821 * @len: length of desc_buff
4822 *
4823 * Returns calculated ICC level
4824 */
4825static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4826 u8 *desc_buf, int len)
4827{
4828 u32 icc_level = 0;
4829
4830 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4831 !hba->vreg_info.vccq2) {
4832 dev_err(hba->dev,
4833 "%s: Regulator capability was not set, actvIccLevel=%d",
4834 __func__, icc_level);
4835 goto out;
4836 }
4837
4838 if (hba->vreg_info.vcc)
4839 icc_level = ufshcd_get_max_icc_level(
4840 hba->vreg_info.vcc->max_uA,
4841 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4842 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4843
4844 if (hba->vreg_info.vccq)
4845 icc_level = ufshcd_get_max_icc_level(
4846 hba->vreg_info.vccq->max_uA,
4847 icc_level,
4848 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4849
4850 if (hba->vreg_info.vccq2)
4851 icc_level = ufshcd_get_max_icc_level(
4852 hba->vreg_info.vccq2->max_uA,
4853 icc_level,
4854 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4855out:
4856 return icc_level;
4857}
4858
61e07359
DR		 4859static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
4860{
4861 int ret = 0;
4862 int retries;
4863
4864 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4865 /* write attribute */
4866 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4867 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
4868 if (!ret)
4869 break;
4870
4871 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
4872 }
4873
4874 return ret;
4875}
4876
3a4bf06d
YG		 4877static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4878{
4879 int ret;
4880 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4881 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4882
4883 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4884 if (ret) {
4885 dev_err(hba->dev,
4886 "%s: Failed reading power descriptor.len = %d ret = %d",
4887 __func__, buff_len, ret);
4888 return;
4889 }
4890
4891 hba->init_prefetch_data.icc_level =
4892 ufshcd_find_max_sup_active_icc_level(hba,
4893 desc_buf, buff_len);
4894 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4895 __func__, hba->init_prefetch_data.icc_level);
4896
61e07359
DR		 4897 ret = ufshcd_set_icc_levels_attr(hba,
4898 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 4899
4900 if (ret)
4901 dev_err(hba->dev,
4902 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4903 __func__, hba->init_prefetch_data.icc_level , ret);
4904
4905}
4906
2a8fa600
SJ		 4907/**
4908 * ufshcd_scsi_add_wlus - Adds required W-LUs
4909 * @hba: per-adapter instance
4910 *
4911 * UFS device specification requires the UFS devices to support 4 well known
4912 * logical units:
4913 * "REPORT_LUNS" (address: 01h)
4914 * "UFS Device" (address: 50h)
4915 * "RPMB" (address: 44h)
4916 * "BOOT" (address: 30h)
4917 * UFS device's power management needs to be controlled by "POWER CONDITION"
4918 * field of SSU (START STOP UNIT) command. But this "power condition" field
4919 * will take effect only when its sent to "UFS device" well known logical unit
4920 * hence we require the scsi_device instance to represent this logical unit in
4921 * order for the UFS host driver to send the SSU command for power management.
4922
4923 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4924 * Block) LU so user space process can control this LU. User space may also
4925 * want to have access to BOOT LU.
4926
4927 * This function adds scsi device instances for each of all well known LUs
4928 * (except "REPORT LUNS" LU).
4929 *
4930 * Returns zero on success (all required W-LUs are added successfully),
4931 * non-zero error value on failure (if failed to add any of the required W-LU).
4932 */
4933static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4934{
4935 int ret = 0;
7c48bfd0
AM		 4936 struct scsi_device *sdev_rpmb;
4937 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4938
4939 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4940 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4941 if (IS_ERR(hba->sdev_ufs_device)) {
4942 ret = PTR_ERR(hba->sdev_ufs_device);
4943 hba->sdev_ufs_device = NULL;
4944 goto out;
4945 }
7c48bfd0 4946 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4947
7c48bfd0 4948 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4949 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4950 if (IS_ERR(sdev_boot)) {
4951 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4952 goto remove_sdev_ufs_device;
4953 }
7c48bfd0 4954 scsi_device_put(sdev_boot);
2a8fa600 4955
7c48bfd0 4956 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4957 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4958 if (IS_ERR(sdev_rpmb)) {
4959 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4960 goto remove_sdev_boot;
4961 }
7c48bfd0 4962 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4963 goto out;
4964
4965remove_sdev_boot:
7c48bfd0 4966 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4967remove_sdev_ufs_device:
4968 scsi_remove_device(hba->sdev_ufs_device);
4969out:
4970 return ret;
4971}
4972
c58ab7aa
YG		 4973static int ufs_get_device_info(struct ufs_hba *hba,
4974 struct ufs_device_info *card_data)
4975{
4976 int err;
4977 u8 model_index;
4978 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
4979 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
4980
4981 err = ufshcd_read_device_desc(hba, desc_buf,
4982 QUERY_DESC_DEVICE_MAX_SIZE);
4983 if (err) {
4984 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
4985 __func__, err);
4986 goto out;
4987 }
4988
4989 /*
4990 * getting vendor (manufacturerID) and Bank Index in big endian
4991 * format
4992 */
4993 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
4994 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
4995
4996 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4997
4998 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
4999 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
5000 if (err) {
5001 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
5002 __func__, err);
5003 goto out;
5004 }
5005
5006 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
5007 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
5008 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
5009 MAX_MODEL_LEN));
5010
5011 /* Null terminate the model string */
5012 card_data->model[MAX_MODEL_LEN] = '\0';
5013
5014out:
5015 return err;
5016}
5017
5018void ufs_advertise_fixup_device(struct ufs_hba *hba)
5019{
5020 int err;
5021 struct ufs_dev_fix *f;
5022 struct ufs_device_info card_data;
5023
5024 card_data.wmanufacturerid = 0;
5025
5026 err = ufs_get_device_info(hba, &card_data);
5027 if (err) {
5028 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
5029 __func__, err);
5030 return;
5031 }
5032
5033 for (f = ufs_fixups; f->quirk; f++) {
5034 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
5035 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
5036 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
5037 !strcmp(f->card.model, UFS_ANY_MODEL)))
5038 hba->dev_quirks |= f->quirk;
5039 }
5040}
5041
37113106
YG		 5042/**
5043 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
5044 * @hba: per-adapter instance
5045 *
5046 * PA_TActivate parameter can be tuned manually if UniPro version is less than
5047 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
5048 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
5049 * the hibern8 exit latency.
5050 *
5051 * Returns zero on success, non-zero error value on failure.
5052 */
5053static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
5054{
5055 int ret = 0;
5056 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
5057
5058 ret = ufshcd_dme_peer_get(hba,
5059 UIC_ARG_MIB_SEL(
5060 RX_MIN_ACTIVATETIME_CAPABILITY,
5061 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5062 &peer_rx_min_activatetime);
5063 if (ret)
5064 goto out;
5065
5066 /* make sure proper unit conversion is applied */
5067 tuned_pa_tactivate =
5068 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
5069 / PA_TACTIVATE_TIME_UNIT_US);
5070 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5071 tuned_pa_tactivate);
5072
5073out:
5074 return ret;
5075}
5076
5077/**
5078 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
5079 * @hba: per-adapter instance
5080 *
5081 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
5082 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
5083 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
5084 * This optimal value can help reduce the hibern8 exit latency.
5085 *
5086 * Returns zero on success, non-zero error value on failure.
5087 */
5088static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
5089{
5090 int ret = 0;
5091 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
5092 u32 max_hibern8_time, tuned_pa_hibern8time;
5093
5094 ret = ufshcd_dme_get(hba,
5095 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
5096 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
5097 &local_tx_hibern8_time_cap);
5098 if (ret)
5099 goto out;
5100
5101 ret = ufshcd_dme_peer_get(hba,
5102 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
5103 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
5104 &peer_rx_hibern8_time_cap);
5105 if (ret)
5106 goto out;
5107
5108 max_hibern8_time = max(local_tx_hibern8_time_cap,
5109 peer_rx_hibern8_time_cap);
5110 /* make sure proper unit conversion is applied */
5111 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
5112 / PA_HIBERN8_TIME_UNIT_US);
5113 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
5114 tuned_pa_hibern8time);
5115out:
5116 return ret;
5117}
5118
c6a6db43 5119/**
5120 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
5121 * less than device PA_TACTIVATE time.
5122 * @hba: per-adapter instance
5123 *
5124 * Some UFS devices require host PA_TACTIVATE to be lower than device
5125 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
5126 * for such devices.
5127 *
5128 * Returns zero on success, non-zero error value on failure.
5129 */
5130static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
5131{
5132 int ret = 0;
5133 u32 granularity, peer_granularity;
5134 u32 pa_tactivate, peer_pa_tactivate;
5135 u32 pa_tactivate_us, peer_pa_tactivate_us;
5136 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
5137
5138 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5139 &granularity);
5140 if (ret)
5141 goto out;
5142
5143 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
5144 &peer_granularity);
5145 if (ret)
5146 goto out;
5147
5148 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
5149 (granularity > PA_GRANULARITY_MAX_VAL)) {
5150 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
5151 __func__, granularity);
5152 return -EINVAL;
5153 }
5154
5155 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
5156 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
5157 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
5158 __func__, peer_granularity);
5159 return -EINVAL;
5160 }
5161
5162 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
5163 if (ret)
5164 goto out;
5165
5166 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
5167 &peer_pa_tactivate);
5168 if (ret)
5169 goto out;
5170
5171 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
5172 peer_pa_tactivate_us = peer_pa_tactivate *
5173 gran_to_us_table[peer_granularity - 1];
5174
5175 if (pa_tactivate_us > peer_pa_tactivate_us) {
5176 u32 new_peer_pa_tactivate;
5177
5178 new_peer_pa_tactivate = pa_tactivate_us /
5179 gran_to_us_table[peer_granularity - 1];
5180 new_peer_pa_tactivate++;
5181 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
5182 new_peer_pa_tactivate);
5183 }
5184
5185out:
5186 return ret;
5187}
5188
37113106
YG		 5189static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
5190{
5191 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
5192 ufshcd_tune_pa_tactivate(hba);
5193 ufshcd_tune_pa_hibern8time(hba);
5194 }
5195
5196 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
5197 /* set 1ms timeout for PA_TACTIVATE */
5198 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 5199
5200 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
5201 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 5202}
5203
6ccf44fe 5204/**
1d337ec2
SRT		 5205 * ufshcd_probe_hba - probe hba to detect device and initialize
5206 * @hba: per-adapter instance
5207 *
5208 * Execute link-startup and verify device initialization
6ccf44fe 5209 */
1d337ec2 5210static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 5211{
6ccf44fe
SJ		 5212 int ret;
5213
5214 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 5215 if (ret)
5216 goto out;
5217
5064636c
YG		 5218 ufshcd_init_pwr_info(hba);
5219
afdfff59
YG		 5220 /* set the default level for urgent bkops */
5221 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5222 hba->is_urgent_bkops_lvl_checked = false;
5223
57d104c1
SJ		 5224 /* UniPro link is active now */
5225 ufshcd_set_link_active(hba);
d3e89bac 5226
5a0b0cb9
SRT		 5227 ret = ufshcd_verify_dev_init(hba);
5228 if (ret)
5229 goto out;
68078d5c
DR		 5230
5231 ret = ufshcd_complete_dev_init(hba);
5232 if (ret)
5233 goto out;
5a0b0cb9 5234
c58ab7aa 5235 ufs_advertise_fixup_device(hba);
37113106 5236 ufshcd_tune_unipro_params(hba);
60f01870
YG		 5237
5238 ret = ufshcd_set_vccq_rail_unused(hba,
5239 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5240 if (ret)
5241 goto out;
5242
57d104c1
SJ		 5243 /* UFS device is also active now */
5244 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5245 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 5246 hba->wlun_dev_clr_ua = true;
5247
7eb584db
DR		 5248 if (ufshcd_get_max_pwr_mode(hba)) {
5249 dev_err(hba->dev,
5250 "%s: Failed getting max supported power mode\n",
5251 __func__);
5252 } else {
5253 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 5254 if (ret) {
7eb584db
DR		 5255 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5256 __func__, ret);
8643ae66
DL		 5257 goto out;
5258 }
7eb584db 5259 }
57d104c1 5260
53c12d0e
YG		 5261 /* set the state as operational after switching to desired gear */
5262 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 5263 /*
5264 * If we are in error handling context or in power management callbacks
5265 * context, no need to scan the host
5266 */
5267 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5268 bool flag;
5269
5270 /* clear any previous UFS device information */
5271 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 5272 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5273 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5274 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5275
3a4bf06d
YG		 5276 if (!hba->is_init_prefetch)
5277 ufshcd_init_icc_levels(hba);
5278
2a8fa600
SJ		 5279 /* Add required well known logical units to scsi mid layer */
5280 if (ufshcd_scsi_add_wlus(hba))
5281 goto out;
5282
3441da7d
SRT		 5283 scsi_scan_host(hba->host);
5284 pm_runtime_put_sync(hba->dev);
5285 }
3a4bf06d
YG		 5286
5287 if (!hba->is_init_prefetch)
5288 hba->is_init_prefetch = true;
5289
856b3483 5290 /* Resume devfreq after UFS device is detected */
a508253d 5291 ufshcd_resume_clkscaling(hba);
856b3483 5292
5a0b0cb9 5293out:
1d337ec2
SRT		 5294 /*
5295 * If we failed to initialize the device or the device is not
5296 * present, turn off the power/clocks etc.
5297 */
57d104c1
SJ		 5298 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5299 pm_runtime_put_sync(hba->dev);
1d337ec2 5300 ufshcd_hba_exit(hba);
57d104c1 5301 }
1d337ec2
SRT		 5302
5303 return ret;
5304}
5305
5306/**
5307 * ufshcd_async_scan - asynchronous execution for probing hba
5308 * @data: data pointer to pass to this function
5309 * @cookie: cookie data
5310 */
5311static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5312{
5313 struct ufs_hba *hba = (struct ufs_hba *)data;
5314
5315 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 5316}
5317
f550c65b
YG		 5318static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5319{
5320 unsigned long flags;
5321 struct Scsi_Host *host;
5322 struct ufs_hba *hba;
5323 int index;
5324 bool found = false;
5325
5326 if (!scmd || !scmd->device || !scmd->device->host)
5327 return BLK_EH_NOT_HANDLED;
5328
5329 host = scmd->device->host;
5330 hba = shost_priv(host);
5331 if (!hba)
5332 return BLK_EH_NOT_HANDLED;
5333
5334 spin_lock_irqsave(host->host_lock, flags);
5335
5336 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5337 if (hba->lrb[index].cmd == scmd) {
5338 found = true;
5339 break;
5340 }
5341 }
5342
5343 spin_unlock_irqrestore(host->host_lock, flags);
5344
5345 /*
5346 * Bypass SCSI error handling and reset the block layer timer if this
5347 * SCSI command was not actually dispatched to UFS driver, otherwise
5348 * let SCSI layer handle the error as usual.
5349 */
5350 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5351}
5352
7a3e97b0
SY		 5353static struct scsi_host_template ufshcd_driver_template = {
5354 .module = THIS_MODULE,
5355 .name = UFSHCD,
5356 .proc_name = UFSHCD,
5357 .queuecommand = ufshcd_queuecommand,
5358 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5359 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5360 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5361 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5362 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 5363 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5364 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5365 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 5366 .this_id = -1,
5367 .sg_tablesize = SG_ALL,
5368 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5369 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5370 .max_host_blocked = 1,
c40ecc12 5371 .track_queue_depth = 1,
7a3e97b0
SY		 5372};
5373
57d104c1
SJ		 5374static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5375 int ua)
5376{
7b16a07c 5377 int ret;
57d104c1 5378
7b16a07c
BA		 5379 if (!vreg)
5380 return 0;
57d104c1 5381
7b16a07c
BA		 5382 ret = regulator_set_load(vreg->reg, ua);
5383 if (ret < 0) {
5384 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5385 __func__, vreg->name, ua, ret);
57d104c1
SJ		 5386 }
5387
5388 return ret;
5389}
5390
5391static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5392 struct ufs_vreg *vreg)
5393{
60f01870
YG		 5394 if (!vreg)
5395 return 0;
5396 else if (vreg->unused)
5397 return 0;
5398 else
5399 return ufshcd_config_vreg_load(hba->dev, vreg,
5400 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 5401}
5402
5403static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5404 struct ufs_vreg *vreg)
5405{
60f01870
YG		 5406 if (!vreg)
5407 return 0;
5408 else if (vreg->unused)
5409 return 0;
5410 else
5411 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 5412}
5413
aa497613
SRT		 5414static int ufshcd_config_vreg(struct device *dev,
5415 struct ufs_vreg *vreg, bool on)
5416{
5417 int ret = 0;
5418 struct regulator *reg = vreg->reg;
5419 const char *name = vreg->name;
5420 int min_uV, uA_load;
5421
5422 BUG_ON(!vreg);
5423
5424 if (regulator_count_voltages(reg) > 0) {
5425 min_uV = on ? vreg->min_uV : 0;
5426 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5427 if (ret) {
5428 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5429 __func__, name, ret);
5430 goto out;
5431 }
5432
5433 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 5434 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5435 if (ret)
aa497613 5436 goto out;
aa497613
SRT		 5437 }
5438out:
5439 return ret;
5440}
5441
5442static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5443{
5444 int ret = 0;
5445
60f01870
YG		 5446 if (!vreg)
5447 goto out;
5448 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 5449 goto out;
5450
5451 ret = ufshcd_config_vreg(dev, vreg, true);
5452 if (!ret)
5453 ret = regulator_enable(vreg->reg);
5454
5455 if (!ret)
5456 vreg->enabled = true;
5457 else
5458 dev_err(dev, "%s: %s enable failed, err=%d\n",
5459 __func__, vreg->name, ret);
5460out:
5461 return ret;
5462}
5463
5464static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5465{
5466 int ret = 0;
5467
60f01870
YG		 5468 if (!vreg)
5469 goto out;
5470 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 5471 goto out;
5472
5473 ret = regulator_disable(vreg->reg);
5474
5475 if (!ret) {
5476 /* ignore errors on applying disable config */
5477 ufshcd_config_vreg(dev, vreg, false);
5478 vreg->enabled = false;
5479 } else {
5480 dev_err(dev, "%s: %s disable failed, err=%d\n",
5481 __func__, vreg->name, ret);
5482 }
5483out:
5484 return ret;
5485}
5486
5487static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5488{
5489 int ret = 0;
5490 struct device *dev = hba->dev;
5491 struct ufs_vreg_info *info = &hba->vreg_info;
5492
5493 if (!info)
5494 goto out;
5495
5496 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5497 if (ret)
5498 goto out;
5499
5500 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5501 if (ret)
5502 goto out;
5503
5504 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5505 if (ret)
5506 goto out;
5507
5508out:
5509 if (ret) {
5510 ufshcd_toggle_vreg(dev, info->vccq2, false);
5511 ufshcd_toggle_vreg(dev, info->vccq, false);
5512 ufshcd_toggle_vreg(dev, info->vcc, false);
5513 }
5514 return ret;
5515}
5516
6a771a65
RS		 5517static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5518{
5519 struct ufs_vreg_info *info = &hba->vreg_info;
5520
5521 if (info)
5522 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5523
5524 return 0;
5525}
5526
aa497613
SRT		 5527static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5528{
5529 int ret = 0;
5530
5531 if (!vreg)
5532 goto out;
5533
5534 vreg->reg = devm_regulator_get(dev, vreg->name);
5535 if (IS_ERR(vreg->reg)) {
5536 ret = PTR_ERR(vreg->reg);
5537 dev_err(dev, "%s: %s get failed, err=%d\n",
5538 __func__, vreg->name, ret);
5539 }
5540out:
5541 return ret;
5542}
5543
5544static int ufshcd_init_vreg(struct ufs_hba *hba)
5545{
5546 int ret = 0;
5547 struct device *dev = hba->dev;
5548 struct ufs_vreg_info *info = &hba->vreg_info;
5549
5550 if (!info)
5551 goto out;
5552
5553 ret = ufshcd_get_vreg(dev, info->vcc);
5554 if (ret)
5555 goto out;
5556
5557 ret = ufshcd_get_vreg(dev, info->vccq);
5558 if (ret)
5559 goto out;
5560
5561 ret = ufshcd_get_vreg(dev, info->vccq2);
5562out:
5563 return ret;
5564}
5565
6a771a65
RS		 5566static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5567{
5568 struct ufs_vreg_info *info = &hba->vreg_info;
5569
5570 if (info)
5571 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5572
5573 return 0;
5574}
5575
60f01870
YG		 5576static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5577{
5578 int ret = 0;
5579 struct ufs_vreg_info *info = &hba->vreg_info;
5580
5581 if (!info)
5582 goto out;
5583 else if (!info->vccq)
5584 goto out;
5585
5586 if (unused) {
5587 /* shut off the rail here */
5588 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5589 /*
5590 * Mark this rail as no longer used, so it doesn't get enabled
5591 * later by mistake
5592 */
5593 if (!ret)
5594 info->vccq->unused = true;
5595 } else {
5596 /*
5597 * rail should have been already enabled hence just make sure
5598 * that unused flag is cleared.
5599 */
5600 info->vccq->unused = false;
5601 }
5602out:
5603 return ret;
5604}
5605
57d104c1
SJ		 5606static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5607 bool skip_ref_clk)
c6e79dac
SRT		 5608{
5609 int ret = 0;
5610 struct ufs_clk_info *clki;
5611 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5612 unsigned long flags;
c6e79dac
SRT		 5613
5614 if (!head || list_empty(head))
5615 goto out;
5616
1e879e8f
SJ		 5617 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
5618 if (ret)
5619 return ret;
5620
c6e79dac
SRT		 5621 list_for_each_entry(clki, head, list) {
5622 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 5623 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5624 continue;
5625
c6e79dac
SRT		 5626 if (on && !clki->enabled) {
5627 ret = clk_prepare_enable(clki->clk);
5628 if (ret) {
5629 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5630 __func__, clki->name, ret);
5631 goto out;
5632 }
5633 } else if (!on && clki->enabled) {
5634 clk_disable_unprepare(clki->clk);
5635 }
5636 clki->enabled = on;
5637 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5638 clki->name, on ? "en" : "dis");
5639 }
5640 }
1ab27c9c 5641
1e879e8f
SJ		 5642 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
5643 if (ret)
5644 return ret;
5645
c6e79dac
SRT		 5646out:
5647 if (ret) {
5648 list_for_each_entry(clki, head, list) {
5649 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5650 clk_disable_unprepare(clki->clk);
5651 }
eda910e4 5652 } else if (on) {
1ab27c9c
ST		 5653 spin_lock_irqsave(hba->host->host_lock, flags);
5654 hba->clk_gating.state = CLKS_ON;
5655 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 5656 }
5657 return ret;
5658}
5659
57d104c1
SJ		 5660static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
5661{
5662 return __ufshcd_setup_clocks(hba, on, false);
5663}
5664
c6e79dac
SRT		 5665static int ufshcd_init_clocks(struct ufs_hba *hba)
5666{
5667 int ret = 0;
5668 struct ufs_clk_info *clki;
5669 struct device *dev = hba->dev;
5670 struct list_head *head = &hba->clk_list_head;
5671
5672 if (!head || list_empty(head))
5673 goto out;
5674
5675 list_for_each_entry(clki, head, list) {
5676 if (!clki->name)
5677 continue;
5678
5679 clki->clk = devm_clk_get(dev, clki->name);
5680 if (IS_ERR(clki->clk)) {
5681 ret = PTR_ERR(clki->clk);
5682 dev_err(dev, "%s: %s clk get failed, %d\n",
5683 __func__, clki->name, ret);
5684 goto out;
5685 }
5686
5687 if (clki->max_freq) {
5688 ret = clk_set_rate(clki->clk, clki->max_freq);
5689 if (ret) {
5690 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5691 __func__, clki->name,
5692 clki->max_freq, ret);
5693 goto out;
5694 }
856b3483 5695 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 5696 }
5697 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
5698 clki->name, clk_get_rate(clki->clk));
5699 }
5700out:
5701 return ret;
5702}
5703
5c0c28a8
SRT		 5704static int ufshcd_variant_hba_init(struct ufs_hba *hba)
5705{
5706 int err = 0;
5707
5708 if (!hba->vops)
5709 goto out;
5710
0263bcd0
YG		 5711 err = ufshcd_vops_init(hba);
5712 if (err)
5713 goto out;
5c0c28a8 5714
0263bcd0
YG		 5715 err = ufshcd_vops_setup_regulators(hba, true);
5716 if (err)
5717 goto out_exit;
5c0c28a8
SRT		 5718
5719 goto out;
5720
5c0c28a8 5721out_exit:
0263bcd0 5722 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5723out:
5724 if (err)
5725 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 5726 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 5727 return err;
5728}
5729
5730static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
5731{
5732 if (!hba->vops)
5733 return;
5734
0263bcd0 5735 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 5736
0263bcd0 5737 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5738}
5739
aa497613
SRT		 5740static int ufshcd_hba_init(struct ufs_hba *hba)
5741{
5742 int err;
5743
6a771a65
RS		 5744 /*
5745 * Handle host controller power separately from the UFS device power
5746 * rails as it will help controlling the UFS host controller power
5747 * collapse easily which is different than UFS device power collapse.
5748 * Also, enable the host controller power before we go ahead with rest
5749 * of the initialization here.
5750 */
5751 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 5752 if (err)
5753 goto out;
5754
6a771a65 5755 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 5756 if (err)
5757 goto out;
5758
6a771a65
RS		 5759 err = ufshcd_init_clocks(hba);
5760 if (err)
5761 goto out_disable_hba_vreg;
5762
5763 err = ufshcd_setup_clocks(hba, true);
5764 if (err)
5765 goto out_disable_hba_vreg;
5766
c6e79dac
SRT		 5767 err = ufshcd_init_vreg(hba);
5768 if (err)
5769 goto out_disable_clks;
5770
5771 err = ufshcd_setup_vreg(hba, true);
5772 if (err)
5773 goto out_disable_clks;
5774
aa497613
SRT		 5775 err = ufshcd_variant_hba_init(hba);
5776 if (err)
5777 goto out_disable_vreg;
5778
1d337ec2 5779 hba->is_powered = true;
aa497613
SRT		 5780 goto out;
5781
5782out_disable_vreg:
5783 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 5784out_disable_clks:
5785 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 5786out_disable_hba_vreg:
5787 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 5788out:
5789 return err;
5790}
5791
5792static void ufshcd_hba_exit(struct ufs_hba *hba)
5793{
1d337ec2
SRT		 5794 if (hba->is_powered) {
5795 ufshcd_variant_hba_exit(hba);
5796 ufshcd_setup_vreg(hba, false);
a508253d 5797 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 5798 ufshcd_setup_clocks(hba, false);
5799 ufshcd_setup_hba_vreg(hba, false);
5800 hba->is_powered = false;
5801 }
aa497613
SRT		 5802}
5803
57d104c1
SJ		 5804static int
5805ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
5806{
5807 unsigned char cmd[6] = {REQUEST_SENSE,
5808 0,
5809 0,
5810 0,
dcea0bfb 5811 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 5812 0};
5813 char *buffer;
5814 int ret;
5815
dcea0bfb 5816 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 5817 if (!buffer) {
5818 ret = -ENOMEM;
5819 goto out;
5820 }
5821
5822 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 5823 UFSHCD_REQ_SENSE_SIZE, NULL,
57d104c1
SJ		 5824 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
5825 if (ret)
5826 pr_err("%s: failed with err %d\n", __func__, ret);
5827
5828 kfree(buffer);
5829out:
5830 return ret;
5831}
5832
5833/**
5834 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
5835 * power mode
5836 * @hba: per adapter instance
5837 * @pwr_mode: device power mode to set
5838 *
5839 * Returns 0 if requested power mode is set successfully
5840 * Returns non-zero if failed to set the requested power mode
5841 */
5842static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
5843 enum ufs_dev_pwr_mode pwr_mode)
5844{
5845 unsigned char cmd[6] = { START_STOP };
5846 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 5847 struct scsi_device *sdp;
5848 unsigned long flags;
57d104c1
SJ		 5849 int ret;
5850
7c48bfd0
AM		 5851 spin_lock_irqsave(hba->host->host_lock, flags);
5852 sdp = hba->sdev_ufs_device;
5853 if (sdp) {
5854 ret = scsi_device_get(sdp);
5855 if (!ret && !scsi_device_online(sdp)) {
5856 ret = -ENODEV;
5857 scsi_device_put(sdp);
5858 }
5859 } else {
5860 ret = -ENODEV;
5861 }
5862 spin_unlock_irqrestore(hba->host->host_lock, flags);
5863
5864 if (ret)
5865 return ret;
57d104c1
SJ		 5866
5867 /*
5868 * If scsi commands fail, the scsi mid-layer schedules scsi error-
5869 * handling, which would wait for host to be resumed. Since we know
5870 * we are functional while we are here, skip host resume in error
5871 * handling context.
5872 */
5873 hba->host->eh_noresume = 1;
5874 if (hba->wlun_dev_clr_ua) {
5875 ret = ufshcd_send_request_sense(hba, sdp);
5876 if (ret)
5877 goto out;
5878 /* Unit attention condition is cleared now */
5879 hba->wlun_dev_clr_ua = false;
5880 }
5881
5882 cmd[4] = pwr_mode << 4;
5883
5884 /*
5885 * Current function would be generally called from the power management
5886 * callbacks hence set the REQ_PM flag so that it doesn't resume the
5887 * already suspended childs.
5888 */
5889 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
5890 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
5891 if (ret) {
5892 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 5893 "START_STOP failed for power mode: %d, result %x\n",
5894 pwr_mode, ret);
21045519
HR		 5895 if (driver_byte(ret) & DRIVER_SENSE)
5896 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 5897 }
5898
5899 if (!ret)
5900 hba->curr_dev_pwr_mode = pwr_mode;
5901out:
7c48bfd0 5902 scsi_device_put(sdp);
57d104c1
SJ		 5903 hba->host->eh_noresume = 0;
5904 return ret;
5905}
5906
5907static int ufshcd_link_state_transition(struct ufs_hba *hba,
5908 enum uic_link_state req_link_state,
5909 int check_for_bkops)
5910{
5911 int ret = 0;
5912
5913 if (req_link_state == hba->uic_link_state)
5914 return 0;
5915
5916 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5917 ret = ufshcd_uic_hibern8_enter(hba);
5918 if (!ret)
5919 ufshcd_set_link_hibern8(hba);
5920 else
5921 goto out;
5922 }
5923 /*
5924 * If autobkops is enabled, link can't be turned off because
5925 * turning off the link would also turn off the device.
5926 */
5927 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
5928 (!check_for_bkops || (check_for_bkops &&
5929 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 5930 /*
5931 * Let's make sure that link is in low power mode, we are doing
5932 * this currently by putting the link in Hibern8. Otherway to
5933 * put the link in low power mode is to send the DME end point
5934 * to device and then send the DME reset command to local
5935 * unipro. But putting the link in hibern8 is much faster.
5936 */
5937 ret = ufshcd_uic_hibern8_enter(hba);
5938 if (ret)
5939 goto out;
57d104c1
SJ		 5940 /*
5941 * Change controller state to "reset state" which
5942 * should also put the link in off/reset state
5943 */
596585a2 5944 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 5945 /*
5946 * TODO: Check if we need any delay to make sure that
5947 * controller is reset
5948 */
5949 ufshcd_set_link_off(hba);
5950 }
5951
5952out:
5953 return ret;
5954}
5955
5956static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
5957{
b799fdf7
YG		 5958 /*
5959 * It seems some UFS devices may keep drawing more than sleep current
5960 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
5961 * To avoid this situation, add 2ms delay before putting these UFS
5962 * rails in LPM mode.
5963 */
5964 if (!ufshcd_is_link_active(hba) &&
5965 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
5966 usleep_range(2000, 2100);
5967
57d104c1
SJ		 5968 /*
5969 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
5970 * power.
5971 *
5972 * If UFS device and link is in OFF state, all power supplies (VCC,
5973 * VCCQ, VCCQ2) can be turned off if power on write protect is not
5974 * required. If UFS link is inactive (Hibern8 or OFF state) and device
5975 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
5976 *
5977 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
5978 * in low power state which would save some power.
5979 */
5980 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5981 !hba->dev_info.is_lu_power_on_wp) {
5982 ufshcd_setup_vreg(hba, false);
5983 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5984 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5985 if (!ufshcd_is_link_active(hba)) {
5986 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5987 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
5988 }
5989 }
5990}
5991
5992static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
5993{
5994 int ret = 0;
5995
5996 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5997 !hba->dev_info.is_lu_power_on_wp) {
5998 ret = ufshcd_setup_vreg(hba, true);
5999 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 6000 if (!ret && !ufshcd_is_link_active(hba)) {
6001 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6002 if (ret)
6003 goto vcc_disable;
6004 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6005 if (ret)
6006 goto vccq_lpm;
6007 }
69d72ac8 6008 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 6009 }
6010 goto out;
6011
6012vccq_lpm:
6013 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
6014vcc_disable:
6015 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
6016out:
6017 return ret;
6018}
6019
6020static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
6021{
6022 if (ufshcd_is_link_off(hba))
6023 ufshcd_setup_hba_vreg(hba, false);
6024}
6025
6026static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
6027{
6028 if (ufshcd_is_link_off(hba))
6029 ufshcd_setup_hba_vreg(hba, true);
6030}
6031
7a3e97b0 6032/**
57d104c1 6033 * ufshcd_suspend - helper function for suspend operations
3b1d0580 6034 * @hba: per adapter instance
57d104c1
SJ		 6035 * @pm_op: desired low power operation type
6036 *
6037 * This function will try to put the UFS device and link into low power
6038 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
6039 * (System PM level).
6040 *
6041 * If this function is called during shutdown, it will make sure that
6042 * both UFS device and UFS link is powered off.
7a3e97b0 6043 *
57d104c1
SJ		 6044 * NOTE: UFS device & link must be active before we enter in this function.
6045 *
6046 * Returns 0 for success and non-zero for failure
7a3e97b0 6047 */
57d104c1 6048static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6049{
57d104c1
SJ		 6050 int ret = 0;
6051 enum ufs_pm_level pm_lvl;
6052 enum ufs_dev_pwr_mode req_dev_pwr_mode;
6053 enum uic_link_state req_link_state;
6054
6055 hba->pm_op_in_progress = 1;
6056 if (!ufshcd_is_shutdown_pm(pm_op)) {
6057 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
6058 hba->rpm_lvl : hba->spm_lvl;
6059 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
6060 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
6061 } else {
6062 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
6063 req_link_state = UIC_LINK_OFF_STATE;
6064 }
6065
7a3e97b0 6066 /*
57d104c1
SJ		 6067 * If we can't transition into any of the low power modes
6068 * just gate the clocks.
7a3e97b0 6069 */
1ab27c9c
ST		 6070 ufshcd_hold(hba, false);
6071 hba->clk_gating.is_suspended = true;
6072
d6fcf81a
SJ		 6073 ufshcd_suspend_clkscaling(hba);
6074
57d104c1
SJ		 6075 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
6076 req_link_state == UIC_LINK_ACTIVE_STATE) {
6077 goto disable_clks;
6078 }
7a3e97b0 6079
57d104c1
SJ		 6080 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
6081 (req_link_state == hba->uic_link_state))
d6fcf81a 6082 goto enable_gating;
57d104c1
SJ		 6083
6084 /* UFS device & link must be active before we enter in this function */
6085 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
6086 ret = -EINVAL;
d6fcf81a 6087 goto enable_gating;
57d104c1
SJ		 6088 }
6089
6090 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 6091 if (ufshcd_can_autobkops_during_suspend(hba)) {
6092 /*
6093 * The device is idle with no requests in the queue,
6094 * allow background operations if bkops status shows
6095 * that performance might be impacted.
6096 */
6097 ret = ufshcd_urgent_bkops(hba);
6098 if (ret)
6099 goto enable_gating;
6100 } else {
6101 /* make sure that auto bkops is disabled */
6102 ufshcd_disable_auto_bkops(hba);
6103 }
57d104c1
SJ		 6104 }
6105
6106 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
6107 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
6108 !ufshcd_is_runtime_pm(pm_op))) {
6109 /* ensure that bkops is disabled */
6110 ufshcd_disable_auto_bkops(hba);
6111 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
6112 if (ret)
1ab27c9c 6113 goto enable_gating;
57d104c1
SJ		 6114 }
6115
6116 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
6117 if (ret)
6118 goto set_dev_active;
6119
6120 ufshcd_vreg_set_lpm(hba);
6121
6122disable_clks:
6123 /*
6124 * Call vendor specific suspend callback. As these callbacks may access
6125 * vendor specific host controller register space call them before the
6126 * host clocks are ON.
6127 */
0263bcd0
YG		 6128 ret = ufshcd_vops_suspend(hba, pm_op);
6129 if (ret)
6130 goto set_link_active;
57d104c1 6131
57d104c1
SJ		 6132 if (!ufshcd_is_link_active(hba))
6133 ufshcd_setup_clocks(hba, false);
6134 else
6135 /* If link is active, device ref_clk can't be switched off */
6136 __ufshcd_setup_clocks(hba, false, true);
6137
1ab27c9c 6138 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 6139 /*
6140 * Disable the host irq as host controller as there won't be any
0263bcd0 6141 * host controller transaction expected till resume.
57d104c1
SJ		 6142 */
6143 ufshcd_disable_irq(hba);
6144 /* Put the host controller in low power mode if possible */
6145 ufshcd_hba_vreg_set_lpm(hba);
6146 goto out;
6147
57d104c1 6148set_link_active:
a508253d 6149 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 6150 ufshcd_vreg_set_hpm(hba);
6151 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
6152 ufshcd_set_link_active(hba);
6153 else if (ufshcd_is_link_off(hba))
6154 ufshcd_host_reset_and_restore(hba);
6155set_dev_active:
6156 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
6157 ufshcd_disable_auto_bkops(hba);
1ab27c9c 6158enable_gating:
d6fcf81a 6159 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 6160 hba->clk_gating.is_suspended = false;
6161 ufshcd_release(hba);
57d104c1
SJ		 6162out:
6163 hba->pm_op_in_progress = 0;
6164 return ret;
7a3e97b0
SY		 6165}
6166
6167/**
57d104c1 6168 * ufshcd_resume - helper function for resume operations
3b1d0580 6169 * @hba: per adapter instance
57d104c1 6170 * @pm_op: runtime PM or system PM
7a3e97b0 6171 *
57d104c1
SJ		 6172 * This function basically brings the UFS device, UniPro link and controller
6173 * to active state.
6174 *
6175 * Returns 0 for success and non-zero for failure
7a3e97b0 6176 */
57d104c1 6177static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 6178{
57d104c1
SJ		 6179 int ret;
6180 enum uic_link_state old_link_state;
6181
6182 hba->pm_op_in_progress = 1;
6183 old_link_state = hba->uic_link_state;
6184
6185 ufshcd_hba_vreg_set_hpm(hba);
6186 /* Make sure clocks are enabled before accessing controller */
6187 ret = ufshcd_setup_clocks(hba, true);
6188 if (ret)
6189 goto out;
6190
57d104c1
SJ		 6191 /* enable the host irq as host controller would be active soon */
6192 ret = ufshcd_enable_irq(hba);
6193 if (ret)
6194 goto disable_irq_and_vops_clks;
6195
6196 ret = ufshcd_vreg_set_hpm(hba);
6197 if (ret)
6198 goto disable_irq_and_vops_clks;
6199
7a3e97b0 6200 /*
57d104c1
SJ		 6201 * Call vendor specific resume callback. As these callbacks may access
6202 * vendor specific host controller register space call them when the
6203 * host clocks are ON.
7a3e97b0 6204 */
0263bcd0
YG		 6205 ret = ufshcd_vops_resume(hba, pm_op);
6206 if (ret)
6207 goto disable_vreg;
57d104c1
SJ		 6208
6209 if (ufshcd_is_link_hibern8(hba)) {
6210 ret = ufshcd_uic_hibern8_exit(hba);
6211 if (!ret)
6212 ufshcd_set_link_active(hba);
6213 else
6214 goto vendor_suspend;
6215 } else if (ufshcd_is_link_off(hba)) {
6216 ret = ufshcd_host_reset_and_restore(hba);
6217 /*
6218 * ufshcd_host_reset_and_restore() should have already
6219 * set the link state as active
6220 */
6221 if (ret || !ufshcd_is_link_active(hba))
6222 goto vendor_suspend;
6223 }
6224
6225 if (!ufshcd_is_ufs_dev_active(hba)) {
6226 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6227 if (ret)
6228 goto set_old_link_state;
6229 }
6230
374a246e
SJ		 6231 /*
6232 * If BKOPs operations are urgently needed at this moment then
6233 * keep auto-bkops enabled or else disable it.
6234 */
6235 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 6236 hba->clk_gating.is_suspended = false;
6237
a508253d 6238 ufshcd_resume_clkscaling(hba);
856b3483 6239
1ab27c9c
ST		 6240 /* Schedule clock gating in case of no access to UFS device yet */
6241 ufshcd_release(hba);
57d104c1
SJ		 6242 goto out;
6243
6244set_old_link_state:
6245 ufshcd_link_state_transition(hba, old_link_state, 0);
6246vendor_suspend:
0263bcd0 6247 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 6248disable_vreg:
6249 ufshcd_vreg_set_lpm(hba);
6250disable_irq_and_vops_clks:
6251 ufshcd_disable_irq(hba);
a508253d 6252 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 6253 ufshcd_setup_clocks(hba, false);
6254out:
6255 hba->pm_op_in_progress = 0;
6256 return ret;
6257}
6258
6259/**
6260 * ufshcd_system_suspend - system suspend routine
6261 * @hba: per adapter instance
6262 * @pm_op: runtime PM or system PM
6263 *
6264 * Check the description of ufshcd_suspend() function for more details.
6265 *
6266 * Returns 0 for success and non-zero for failure
6267 */
6268int ufshcd_system_suspend(struct ufs_hba *hba)
6269{
6270 int ret = 0;
6271
6272 if (!hba || !hba->is_powered)
233b594b 6273 return 0;
57d104c1 6274
0b257734 6275 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6276 hba->curr_dev_pwr_mode) &&
6277 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
6278 hba->uic_link_state))
6279 goto out;
57d104c1 6280
0b257734 6281 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 6282 /*
6283 * UFS device and/or UFS link low power states during runtime
6284 * suspend seems to be different than what is expected during
6285 * system suspend. Hence runtime resume the devic & link and
6286 * let the system suspend low power states to take effect.
6287 * TODO: If resume takes longer time, we might have optimize
6288 * it in future by not resuming everything if possible.
6289 */
6290 ret = ufshcd_runtime_resume(hba);
6291 if (ret)
6292 goto out;
6293 }
6294
6295 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6296out:
e785060e
DR		 6297 if (!ret)
6298 hba->is_sys_suspended = true;
57d104c1
SJ		 6299 return ret;
6300}
6301EXPORT_SYMBOL(ufshcd_system_suspend);
6302
6303/**
6304 * ufshcd_system_resume - system resume routine
6305 * @hba: per adapter instance
6306 *
6307 * Returns 0 for success and non-zero for failure
6308 */
7a3e97b0 6309
57d104c1
SJ		 6310int ufshcd_system_resume(struct ufs_hba *hba)
6311{
e3ce73d6
YG		 6312 if (!hba)
6313 return -EINVAL;
6314
6315 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 6316 /*
6317 * Let the runtime resume take care of resuming
6318 * if runtime suspended.
6319 */
6320 return 0;
6321
6322 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 6323}
57d104c1 6324EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6325
57d104c1
SJ		 6326/**
6327 * ufshcd_runtime_suspend - runtime suspend routine
6328 * @hba: per adapter instance
6329 *
6330 * Check the description of ufshcd_suspend() function for more details.
6331 *
6332 * Returns 0 for success and non-zero for failure
6333 */
66ec6d59
SRT		 6334int ufshcd_runtime_suspend(struct ufs_hba *hba)
6335{
e3ce73d6
YG		 6336 if (!hba)
6337 return -EINVAL;
6338
6339 if (!hba->is_powered)
66ec6d59
SRT		 6340 return 0;
6341
57d104c1 6342 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6343}
6344EXPORT_SYMBOL(ufshcd_runtime_suspend);
6345
57d104c1
SJ		 6346/**
6347 * ufshcd_runtime_resume - runtime resume routine
6348 * @hba: per adapter instance
6349 *
6350 * This function basically brings the UFS device, UniPro link and controller
6351 * to active state. Following operations are done in this function:
6352 *
6353 * 1. Turn on all the controller related clocks
6354 * 2. Bring the UniPro link out of Hibernate state
6355 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6356 * to active state.
6357 * 4. If auto-bkops is enabled on the device, disable it.
6358 *
6359 * So following would be the possible power state after this function return
6360 * successfully:
6361 * S1: UFS device in Active state with VCC rail ON
6362 * UniPro link in Active state
6363 * All the UFS/UniPro controller clocks are ON
6364 *
6365 * Returns 0 for success and non-zero for failure
6366 */
66ec6d59
SRT		 6367int ufshcd_runtime_resume(struct ufs_hba *hba)
6368{
e3ce73d6
YG		 6369 if (!hba)
6370 return -EINVAL;
6371
6372 if (!hba->is_powered)
66ec6d59 6373 return 0;
e3ce73d6
YG		 6374
6375 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6376}
6377EXPORT_SYMBOL(ufshcd_runtime_resume);
6378
6379int ufshcd_runtime_idle(struct ufs_hba *hba)
6380{
6381 return 0;
6382}
6383EXPORT_SYMBOL(ufshcd_runtime_idle);
6384
57d104c1
SJ		 6385/**
6386 * ufshcd_shutdown - shutdown routine
6387 * @hba: per adapter instance
6388 *
6389 * This function would power off both UFS device and UFS link.
6390 *
6391 * Returns 0 always to allow force shutdown even in case of errors.
6392 */
6393int ufshcd_shutdown(struct ufs_hba *hba)
6394{
6395 int ret = 0;
6396
6397 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6398 goto out;
6399
6400 if (pm_runtime_suspended(hba->dev)) {
6401 ret = ufshcd_runtime_resume(hba);
6402 if (ret)
6403 goto out;
6404 }
6405
6406 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6407out:
6408 if (ret)
6409 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6410 /* allow force shutdown even in case of errors */
6411 return 0;
6412}
6413EXPORT_SYMBOL(ufshcd_shutdown);
6414
7a3e97b0 6415/**
3b1d0580 6416 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6417 * data structure memory
3b1d0580 6418 * @hba - per adapter instance
7a3e97b0 6419 */
3b1d0580 6420void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6421{
cfdf9c91 6422 scsi_remove_host(hba->host);
7a3e97b0 6423 /* disable interrupts */
2fbd009b 6424 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6425 ufshcd_hba_stop(hba, true);
7a3e97b0 6426
1ab27c9c 6427 ufshcd_exit_clk_gating(hba);
aa497613 6428 ufshcd_hba_exit(hba);
3b1d0580
VH		 6429}
6430EXPORT_SYMBOL_GPL(ufshcd_remove);
6431
47555a5c
YG		 6432/**
6433 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6434 * @hba: pointer to Host Bus Adapter (HBA)
6435 */
6436void ufshcd_dealloc_host(struct ufs_hba *hba)
6437{
6438 scsi_host_put(hba->host);
6439}
6440EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6441
ca3d7bf9
AM		 6442/**
6443 * ufshcd_set_dma_mask - Set dma mask based on the controller
6444 * addressing capability
6445 * @hba: per adapter instance
6446 *
6447 * Returns 0 for success, non-zero for failure
6448 */
6449static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6450{
6451 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6452 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6453 return 0;
6454 }
6455 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6456}
6457
7a3e97b0 6458/**
5c0c28a8 6459 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 6460 * @dev: pointer to device handle
6461 * @hba_handle: driver private handle
7a3e97b0
SY		 6462 * Returns 0 on success, non-zero value on failure
6463 */
5c0c28a8 6464int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 6465{
6466 struct Scsi_Host *host;
6467 struct ufs_hba *hba;
5c0c28a8 6468 int err = 0;
7a3e97b0 6469
3b1d0580
VH		 6470 if (!dev) {
6471 dev_err(dev,
6472 "Invalid memory reference for dev is NULL\n");
6473 err = -ENODEV;
7a3e97b0
SY		 6474 goto out_error;
6475 }
6476
7a3e97b0
SY		 6477 host = scsi_host_alloc(&ufshcd_driver_template,
6478 sizeof(struct ufs_hba));
6479 if (!host) {
3b1d0580 6480 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6481 err = -ENOMEM;
3b1d0580 6482 goto out_error;
7a3e97b0
SY		 6483 }
6484 hba = shost_priv(host);
7a3e97b0 6485 hba->host = host;
3b1d0580 6486 hba->dev = dev;
5c0c28a8
SRT		 6487 *hba_handle = hba;
6488
6489out_error:
6490 return err;
6491}
6492EXPORT_SYMBOL(ufshcd_alloc_host);
6493
856b3483
ST		 6494static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6495{
6496 int ret = 0;
6497 struct ufs_clk_info *clki;
6498 struct list_head *head = &hba->clk_list_head;
6499
6500 if (!head || list_empty(head))
6501 goto out;
6502
f06fcc71
YG		 6503 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
6504 if (ret)
6505 return ret;
6506
856b3483
ST		 6507 list_for_each_entry(clki, head, list) {
6508 if (!IS_ERR_OR_NULL(clki->clk)) {
6509 if (scale_up && clki->max_freq) {
6510 if (clki->curr_freq == clki->max_freq)
6511 continue;
6512 ret = clk_set_rate(clki->clk, clki->max_freq);
6513 if (ret) {
6514 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6515 __func__, clki->name,
6516 clki->max_freq, ret);
6517 break;
6518 }
6519 clki->curr_freq = clki->max_freq;
6520
6521 } else if (!scale_up && clki->min_freq) {
6522 if (clki->curr_freq == clki->min_freq)
6523 continue;
6524 ret = clk_set_rate(clki->clk, clki->min_freq);
6525 if (ret) {
6526 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6527 __func__, clki->name,
6528 clki->min_freq, ret);
6529 break;
6530 }
6531 clki->curr_freq = clki->min_freq;
6532 }
6533 }
6534 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
6535 clki->name, clk_get_rate(clki->clk));
6536 }
f06fcc71
YG		 6537
6538 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
6539
856b3483
ST		 6540out:
6541 return ret;
6542}
6543
6544static int ufshcd_devfreq_target(struct device *dev,
6545 unsigned long *freq, u32 flags)
6546{
6547 int err = 0;
6548 struct ufs_hba *hba = dev_get_drvdata(dev);
30fc33f1
SJ		 6549 bool release_clk_hold = false;
6550 unsigned long irq_flags;
856b3483
ST		 6551
6552 if (!ufshcd_is_clkscaling_enabled(hba))
6553 return -EINVAL;
6554
30fc33f1
SJ		 6555 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6556 if (ufshcd_eh_in_progress(hba)) {
6557 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6558 return 0;
6559 }
6560
6561 if (ufshcd_is_clkgating_allowed(hba) &&
6562 (hba->clk_gating.state != CLKS_ON)) {
6563 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
6564 /* hold the vote until the scaling work is completed */
6565 hba->clk_gating.active_reqs++;
6566 release_clk_hold = true;
6567 hba->clk_gating.state = CLKS_ON;
6568 } else {
6569 /*
6570 * Clock gating work seems to be running in parallel
6571 * hence skip scaling work to avoid deadlock between
6572 * current scaling work and gating work.
6573 */
6574 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6575 return 0;
6576 }
6577 }
6578 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6579
856b3483
ST		 6580 if (*freq == UINT_MAX)
6581 err = ufshcd_scale_clks(hba, true);
6582 else if (*freq == 0)
6583 err = ufshcd_scale_clks(hba, false);
6584
30fc33f1
SJ		 6585 spin_lock_irqsave(hba->host->host_lock, irq_flags);
6586 if (release_clk_hold)
6587 __ufshcd_release(hba);
6588 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
6589
856b3483
ST		 6590 return err;
6591}
6592
6593static int ufshcd_devfreq_get_dev_status(struct device *dev,
6594 struct devfreq_dev_status *stat)
6595{
6596 struct ufs_hba *hba = dev_get_drvdata(dev);
6597 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
6598 unsigned long flags;
6599
6600 if (!ufshcd_is_clkscaling_enabled(hba))
6601 return -EINVAL;
6602
6603 memset(stat, 0, sizeof(*stat));
6604
6605 spin_lock_irqsave(hba->host->host_lock, flags);
6606 if (!scaling->window_start_t)
6607 goto start_window;
6608
6609 if (scaling->is_busy_started)
6610 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
6611 scaling->busy_start_t));
6612
6613 stat->total_time = jiffies_to_usecs((long)jiffies -
6614 (long)scaling->window_start_t);
6615 stat->busy_time = scaling->tot_busy_t;
6616start_window:
6617 scaling->window_start_t = jiffies;
6618 scaling->tot_busy_t = 0;
6619
6620 if (hba->outstanding_reqs) {
6621 scaling->busy_start_t = ktime_get();
6622 scaling->is_busy_started = true;
6623 } else {
6624 scaling->busy_start_t = ktime_set(0, 0);
6625 scaling->is_busy_started = false;
6626 }
6627 spin_unlock_irqrestore(hba->host->host_lock, flags);
6628 return 0;
6629}
6630
6631static struct devfreq_dev_profile ufs_devfreq_profile = {
6632 .polling_ms = 100,
6633 .target = ufshcd_devfreq_target,
6634 .get_dev_status = ufshcd_devfreq_get_dev_status,
6635};
6636
5c0c28a8
SRT		 6637/**
6638 * ufshcd_init - Driver initialization routine
6639 * @hba: per-adapter instance
6640 * @mmio_base: base register address
6641 * @irq: Interrupt line of device
6642 * Returns 0 on success, non-zero value on failure
6643 */
6644int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
6645{
6646 int err;
6647 struct Scsi_Host *host = hba->host;
6648 struct device *dev = hba->dev;
6649
6650 if (!mmio_base) {
6651 dev_err(hba->dev,
6652 "Invalid memory reference for mmio_base is NULL\n");
6653 err = -ENODEV;
6654 goto out_error;
6655 }
6656
3b1d0580
VH		 6657 hba->mmio_base = mmio_base;
6658 hba->irq = irq;
7a3e97b0 6659
aa497613 6660 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 6661 if (err)
6662 goto out_error;
6663
7a3e97b0
SY		 6664 /* Read capabilities registers */
6665 ufshcd_hba_capabilities(hba);
6666
6667 /* Get UFS version supported by the controller */
6668 hba->ufs_version = ufshcd_get_ufs_version(hba);
6669
2fbd009b
SJ		 6670 /* Get Interrupt bit mask per version */
6671 hba->intr_mask = ufshcd_get_intr_mask(hba);
6672
ca3d7bf9
AM		 6673 err = ufshcd_set_dma_mask(hba);
6674 if (err) {
6675 dev_err(hba->dev, "set dma mask failed\n");
6676 goto out_disable;
6677 }
6678
7a3e97b0
SY		 6679 /* Allocate memory for host memory space */
6680 err = ufshcd_memory_alloc(hba);
6681 if (err) {
3b1d0580
VH		 6682 dev_err(hba->dev, "Memory allocation failed\n");
6683 goto out_disable;
7a3e97b0
SY		 6684 }
6685
6686 /* Configure LRB */
6687 ufshcd_host_memory_configure(hba);
6688
6689 host->can_queue = hba->nutrs;
6690 host->cmd_per_lun = hba->nutrs;
6691 host->max_id = UFSHCD_MAX_ID;
0ce147d4 6692 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 6693 host->max_channel = UFSHCD_MAX_CHANNEL;
6694 host->unique_id = host->host_no;
6695 host->max_cmd_len = MAX_CDB_SIZE;
6696
7eb584db
DR		 6697 hba->max_pwr_info.is_valid = false;
6698
7a3e97b0 6699 /* Initailize wait queue for task management */
e2933132
SRT		 6700 init_waitqueue_head(&hba->tm_wq);
6701 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 6702
6703 /* Initialize work queues */
e8e7f271 6704 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 6705 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 6706
6ccf44fe
SJ		 6707 /* Initialize UIC command mutex */
6708 mutex_init(&hba->uic_cmd_mutex);
6709
5a0b0cb9
SRT		 6710 /* Initialize mutex for device management commands */
6711 mutex_init(&hba->dev_cmd.lock);
6712
6713 /* Initialize device management tag acquire wait queue */
6714 init_waitqueue_head(&hba->dev_cmd.tag_wq);
6715
1ab27c9c 6716 ufshcd_init_clk_gating(hba);
199ef13c
YG		 6717
6718 /*
6719 * In order to avoid any spurious interrupt immediately after
6720 * registering UFS controller interrupt handler, clear any pending UFS
6721 * interrupt status and disable all the UFS interrupts.
6722 */
6723 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
6724 REG_INTERRUPT_STATUS);
6725 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
6726 /*
6727 * Make sure that UFS interrupts are disabled and any pending interrupt
6728 * status is cleared before registering UFS interrupt handler.
6729 */
6730 mb();
6731
7a3e97b0 6732 /* IRQ registration */
2953f850 6733 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 6734 if (err) {
3b1d0580 6735 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 6736 goto exit_gating;
57d104c1
SJ		 6737 } else {
6738 hba->is_irq_enabled = true;
7a3e97b0
SY		 6739 }
6740
3b1d0580 6741 err = scsi_add_host(host, hba->dev);
7a3e97b0 6742 if (err) {
3b1d0580 6743 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 6744 goto exit_gating;
7a3e97b0
SY		 6745 }
6746
6ccf44fe
SJ		 6747 /* Host controller enable */
6748 err = ufshcd_hba_enable(hba);
7a3e97b0 6749 if (err) {
6ccf44fe 6750 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 6751 goto out_remove_scsi_host;
7a3e97b0 6752 }
6ccf44fe 6753
856b3483 6754 if (ufshcd_is_clkscaling_enabled(hba)) {
4861ee15 6755 hba->devfreq = devm_devfreq_add_device(dev, &ufs_devfreq_profile,
856b3483
ST		 6756 "simple_ondemand", NULL);
6757 if (IS_ERR(hba->devfreq)) {
6758 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
6759 PTR_ERR(hba->devfreq));
73811c94 6760 err = PTR_ERR(hba->devfreq);
856b3483
ST		 6761 goto out_remove_scsi_host;
6762 }
6763 /* Suspend devfreq until the UFS device is detected */
a508253d 6764 ufshcd_suspend_clkscaling(hba);
856b3483
ST		 6765 }
6766
62694735
SRT		 6767 /* Hold auto suspend until async scan completes */
6768 pm_runtime_get_sync(dev);
6769
57d104c1 6770 /*
7caf489b 6771 * We are assuming that device wasn't put in sleep/power-down
6772 * state exclusively during the boot stage before kernel.
6773 * This assumption helps avoid doing link startup twice during
6774 * ufshcd_probe_hba().
57d104c1 6775 */
7caf489b 6776 ufshcd_set_ufs_dev_active(hba);
57d104c1 6777
6ccf44fe
SJ		 6778 async_schedule(ufshcd_async_scan, hba);
6779
7a3e97b0
SY		 6780 return 0;
6781
3b1d0580
VH		 6782out_remove_scsi_host:
6783 scsi_remove_host(hba->host);
1ab27c9c
ST		 6784exit_gating:
6785 ufshcd_exit_clk_gating(hba);
3b1d0580 6786out_disable:
57d104c1 6787 hba->is_irq_enabled = false;
aa497613 6788 ufshcd_hba_exit(hba);
3b1d0580
VH		 6789out_error:
6790 return err;
6791}
6792EXPORT_SYMBOL_GPL(ufshcd_init);
6793
3b1d0580
VH		 6794MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
6795MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 6796MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 6797MODULE_LICENSE("GPL");
6798MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)