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scsi: libsas: Replace zero-length array with flexible-array
[linux-2.6-block.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
fb276f77 45#include <linux/blk-pm.h>
e0eca63e 46#include "ufshcd.h"
c58ab7aa 47#include "ufs_quirks.h"
53b3d9c3 48#include "unipro.h"
cbb6813e 49#include "ufs-sysfs.h"
df032bf2 50#include "ufs_bsg.h"
3d17b9b5
AD		 51#include <asm/unaligned.h>
52#include <linux/blkdev.h>
7a3e97b0 53
7ff5ab47 54#define CREATE_TRACE_POINTS
55#include <trace/events/ufs.h>
56
2fbd009b
SJ		 57#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
58 UTP_TASK_REQ_COMPL |\
59 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 60/* UIC command timeout, unit: ms */
61#define UIC_CMD_TIMEOUT 500
2fbd009b 62
5a0b0cb9
SRT		 63/* NOP OUT retries waiting for NOP IN response */
64#define NOP_OUT_RETRIES 10
65/* Timeout after 30 msecs if NOP OUT hangs without response */
66#define NOP_OUT_TIMEOUT 30 /* msecs */
67
68078d5c 68/* Query request retries */
10fe5888 69#define QUERY_REQ_RETRIES 3
68078d5c 70/* Query request timeout */
10fe5888 71#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 72
e2933132
SRT		 73/* Task management command timeout */
74#define TM_CMD_TIMEOUT 100 /* msecs */
75
64238fbd
YG		 76/* maximum number of retries for a general UIC command */
77#define UFS_UIC_COMMAND_RETRIES 3
78
1d337ec2
SRT		 79/* maximum number of link-startup retries */
80#define DME_LINKSTARTUP_RETRIES 3
81
87d0b4a6
YG		 82/* Maximum retries for Hibern8 enter */
83#define UIC_HIBERN8_ENTER_RETRIES 3
84
1d337ec2
SRT		 85/* maximum number of reset retries before giving up */
86#define MAX_HOST_RESET_RETRIES 5
87
68078d5c
DR		 88/* Expose the flag value from utp_upiu_query.value */
89#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
90
7d568652
SJ		 91/* Interrupt aggregation default timeout, unit: 40us */
92#define INT_AGGR_DEF_TO 0x02
93
49615ba1
SC		 94/* default delay of autosuspend: 2000 ms */
95#define RPM_AUTOSUSPEND_DELAY_MS 2000
96
09f17791
CG		 97/* Default value of wait time before gating device ref clock */
98#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
99
aa497613
SRT		 100#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
101 ({ \
102 int _ret; \
103 if (_on) \
104 _ret = ufshcd_enable_vreg(_dev, _vreg); \
105 else \
106 _ret = ufshcd_disable_vreg(_dev, _vreg); \
107 _ret; \
108 })
109
ba80917d
TW		 110#define ufshcd_hex_dump(prefix_str, buf, len) do { \
111 size_t __len = (len); \
112 print_hex_dump(KERN_ERR, prefix_str, \
113 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
114 16, 4, buf, __len, false); \
115} while (0)
116
117int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
118 const char *prefix)
119{
d6724756
MG		 120 u32 *regs;
121 size_t pos;
122
123 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
124 return -EINVAL;
ba80917d 125
cddaebaf 126 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 127 if (!regs)
128 return -ENOMEM;
129
d6724756
MG		 130 for (pos = 0; pos < len; pos += 4)
131 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
132
ba80917d
TW		 133 ufshcd_hex_dump(prefix, regs, len);
134 kfree(regs);
135
136 return 0;
137}
138EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 139
7a3e97b0
SY		 140enum {
141 UFSHCD_MAX_CHANNEL = 0,
142 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 143 UFSHCD_CMD_PER_LUN = 32,
144 UFSHCD_CAN_QUEUE = 32,
145};
146
147/* UFSHCD states */
148enum {
7a3e97b0
SY		 149 UFSHCD_STATE_RESET,
150 UFSHCD_STATE_ERROR,
3441da7d 151 UFSHCD_STATE_OPERATIONAL,
141f8165 152 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 153};
154
155/* UFSHCD error handling flags */
156enum {
157 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 158};
159
e8e7f271
SRT		 160/* UFSHCD UIC layer error flags */
161enum {
162 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 163 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
164 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
165 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
166 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
167 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 168};
169
3441da7d 170#define ufshcd_set_eh_in_progress(h) \
9c490d2d 171 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 172#define ufshcd_eh_in_progress(h) \
9c490d2d 173 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 174#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 175 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 176
cbb6813e 177struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 178 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
179 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
180 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
181 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
182 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
183 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
184};
185
186static inline enum ufs_dev_pwr_mode
187ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
188{
189 return ufs_pm_lvl_states[lvl].dev_state;
190}
191
192static inline enum uic_link_state
193ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
194{
195 return ufs_pm_lvl_states[lvl].link_state;
196}
197
0c8f7586 198static inline enum ufs_pm_level
199ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
200 enum uic_link_state link_state)
201{
202 enum ufs_pm_level lvl;
203
204 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
205 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
206 (ufs_pm_lvl_states[lvl].link_state == link_state))
207 return lvl;
208 }
209
210 /* if no match found, return the level 0 */
211 return UFS_PM_LVL_0;
212}
213
56d4a186
SJ		 214static struct ufs_dev_fix ufs_fixups[] = {
215 /* UFS cards deviations table */
216 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
217 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
56d4a186
SJ		 218 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
219 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
56d4a186
SJ		 220 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
221 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
222 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
223 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
224 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
225 UFS_DEVICE_QUIRK_PA_TACTIVATE),
226 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
227 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 228 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
8e4829c6
WL		 230 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
231 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 232
233 END_FIX
234};
235
9333d775 236static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 237static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 238static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 239static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 240static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 241static void ufshcd_hba_exit(struct ufs_hba *hba);
1b9e2141 242static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
1ab27c9c
ST		 243static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
244 bool skip_ref_clk);
245static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
1ab27c9c 246static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 247static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 248static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 249static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
250static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 251static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 252static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 253static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 254static int ufshcd_change_power_mode(struct ufs_hba *hba,
255 struct ufs_pa_layer_attr *pwr_mode);
3d17b9b5
AD		 256static bool ufshcd_wb_sup(struct ufs_hba *hba);
257static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba);
258static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba);
259static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable);
260static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
261static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
262
14497328
YG		 263static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
264{
265 return tag >= 0 && tag < hba->nutrs;
266}
57d104c1 267
5231d38c 268static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 269{
57d104c1 270 if (!hba->is_irq_enabled) {
5231d38c 271 enable_irq(hba->irq);
57d104c1
SJ		 272 hba->is_irq_enabled = true;
273 }
57d104c1
SJ		 274}
275
276static inline void ufshcd_disable_irq(struct ufs_hba *hba)
277{
278 if (hba->is_irq_enabled) {
5231d38c 279 disable_irq(hba->irq);
57d104c1
SJ		 280 hba->is_irq_enabled = false;
281 }
282}
3441da7d 283
3d17b9b5
AD		 284static inline void ufshcd_wb_config(struct ufs_hba *hba)
285{
286 int ret;
287
288 if (!ufshcd_wb_sup(hba))
289 return;
290
291 ret = ufshcd_wb_ctrl(hba, true);
292 if (ret)
293 dev_err(hba->dev, "%s: Enable WB failed: %d\n", __func__, ret);
294 else
295 dev_info(hba->dev, "%s: Write Booster Configured\n", __func__);
296 ret = ufshcd_wb_toggle_flush_during_h8(hba, true);
297 if (ret)
298 dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
299 __func__, ret);
300 ufshcd_wb_toggle_flush(hba, true);
301}
302
38135535
SJ		 303static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
304{
305 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
306 scsi_unblock_requests(hba->host);
307}
308
309static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
310{
311 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
312 scsi_block_requests(hba->host);
313}
314
6667e6d9
OS		 315static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
316 const char *str)
317{
318 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
319
320 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
321}
322
323static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
324 const char *str)
325{
326 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
327
328 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
329}
330
331static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
332 const char *str)
333{
6667e6d9 334 int off = (int)tag - hba->nutrs;
391e388f 335 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 336
391e388f
CH		 337 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
338 &descp->input_param1);
6667e6d9
OS		 339}
340
1a07f2d9
LS		 341static void ufshcd_add_command_trace(struct ufs_hba *hba,
342 unsigned int tag, const char *str)
343{
344 sector_t lba = -1;
345 u8 opcode = 0;
346 u32 intr, doorbell;
e7c3b379 347 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 348 struct scsi_cmnd *cmd = lrbp->cmd;
1a07f2d9
LS		 349 int transfer_len = -1;
350
e7c3b379
OS		 351 if (!trace_ufshcd_command_enabled()) {
352 /* trace UPIU W/O tracing command */
e4d2add7 353 if (cmd)
e7c3b379 354 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 355 return;
e7c3b379 356 }
1a07f2d9 357
e4d2add7 358 if (cmd) { /* data phase exists */
e7c3b379
OS		 359 /* trace UPIU also */
360 ufshcd_add_cmd_upiu_trace(hba, tag, str);
e4d2add7 361 opcode = cmd->cmnd[0];
1a07f2d9
LS		 362 if ((opcode == READ_10) || (opcode == WRITE_10)) {
363 /*
364 * Currently we only fully trace read(10) and write(10)
365 * commands
366 */
e4d2add7
BVA		 367 if (cmd->request && cmd->request->bio)
368 lba = cmd->request->bio->bi_iter.bi_sector;
1a07f2d9
LS		 369 transfer_len = be32_to_cpu(
370 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
371 }
372 }
373
374 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
375 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
376 trace_ufshcd_command(dev_name(hba->dev), str, tag,
377 doorbell, transfer_len, intr, lba, opcode);
378}
379
ff8e20c6
DR		 380static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
381{
382 struct ufs_clk_info *clki;
383 struct list_head *head = &hba->clk_list_head;
384
566ec9ad 385 if (list_empty(head))
ff8e20c6
DR		 386 return;
387
388 list_for_each_entry(clki, head, list) {
389 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
390 clki->max_freq)
391 dev_err(hba->dev, "clk: %s, rate: %u\n",
392 clki->name, clki->curr_freq);
393 }
394}
395
48d5b973
SC		 396static void ufshcd_print_err_hist(struct ufs_hba *hba,
397 struct ufs_err_reg_hist *err_hist,
398 char *err_name)
ff8e20c6
DR		 399{
400 int i;
27752647 401 bool found = false;
ff8e20c6 402
48d5b973
SC		 403 for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
404 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
ff8e20c6 405
645728a6 406 if (err_hist->tstamp[p] == 0)
ff8e20c6 407 continue;
c5397f13 408 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
ff8e20c6 409 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
27752647 410 found = true;
ff8e20c6 411 }
27752647
SC		 412
413 if (!found)
fd1fb4d5 414 dev_err(hba->dev, "No record of %s\n", err_name);
ff8e20c6
DR		 415}
416
66cc820f
DR		 417static void ufshcd_print_host_regs(struct ufs_hba *hba)
418{
ba80917d 419 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 420 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
421 hba->ufs_version, hba->capabilities);
422 dev_err(hba->dev,
423 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
424 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 425 dev_err(hba->dev,
426 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
427 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
428 hba->ufs_stats.hibern8_exit_cnt);
429
48d5b973
SC		 430 ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
431 ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
432 ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
433 ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
434 ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
d3c615bf
SC		 435 ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
436 "auto_hibern8_err");
8808b4e9
SC		 437 ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
438 ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
439 "link_startup_fail");
440 ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
441 ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
442 "suspend_fail");
443 ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
444 ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
445 ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
ff8e20c6
DR		 446
447 ufshcd_print_clk_freqs(hba);
448
7c486d91 449 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 450}
451
452static
453void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
454{
455 struct ufshcd_lrb *lrbp;
7fabb77b 456 int prdt_length;
66cc820f
DR		 457 int tag;
458
459 for_each_set_bit(tag, &bitmap, hba->nutrs) {
460 lrbp = &hba->lrb[tag];
461
ff8e20c6
DR		 462 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
463 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 464 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
465 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 466 dev_err(hba->dev,
467 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
468 tag, (u64)lrbp->utrd_dma_addr);
469
66cc820f
DR		 470 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
471 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 472 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
473 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 474 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
475 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 476 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
477 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 478 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
479 sizeof(struct utp_upiu_rsp));
66cc820f 480
7fabb77b
GB		 481 prdt_length = le16_to_cpu(
482 lrbp->utr_descriptor_ptr->prd_table_length);
483 dev_err(hba->dev,
484 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
485 tag, prdt_length,
486 (u64)lrbp->ucd_prdt_dma_addr);
487
488 if (pr_prdt)
66cc820f 489 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 490 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 491 }
492}
493
494static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
495{
66cc820f
DR		 496 int tag;
497
498 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 499 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
500
66cc820f 501 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 502 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 503 }
504}
505
6ba65588
GB		 506static void ufshcd_print_host_state(struct ufs_hba *hba)
507{
508 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 509 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
510 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 511 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
512 hba->saved_err, hba->saved_uic_err);
513 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
514 hba->curr_dev_pwr_mode, hba->uic_link_state);
515 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
516 hba->pm_op_in_progress, hba->is_sys_suspended);
517 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
518 hba->auto_bkops_enabled, hba->host->host_self_blocked);
519 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
520 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
521 hba->eh_flags, hba->req_abort_count);
522 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
523 hba->capabilities, hba->caps);
524 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
525 hba->dev_quirks);
526}
527
ff8e20c6
DR		 528/**
529 * ufshcd_print_pwr_info - print power params as saved in hba
530 * power info
531 * @hba: per-adapter instance
532 */
533static void ufshcd_print_pwr_info(struct ufs_hba *hba)
534{
535 static const char * const names[] = {
536 "INVALID MODE",
537 "FAST MODE",
538 "SLOW_MODE",
539 "INVALID MODE",
540 "FASTAUTO_MODE",
541 "SLOWAUTO_MODE",
542 "INVALID MODE",
543 };
544
545 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
546 __func__,
547 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
548 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
549 names[hba->pwr_info.pwr_rx],
550 names[hba->pwr_info.pwr_tx],
551 hba->pwr_info.hs_rate);
552}
553
5c955c10
SC		 554void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
555{
556 if (!us)
557 return;
558
559 if (us < 10)
560 udelay(us);
561 else
562 usleep_range(us, us + tolerance);
563}
564EXPORT_SYMBOL_GPL(ufshcd_delay_us);
565
5a0b0cb9
SRT		 566/*
567 * ufshcd_wait_for_register - wait for register value to change
568 * @hba - per-adapter interface
569 * @reg - mmio register offset
570 * @mask - mask to apply to read register value
571 * @val - wait condition
572 * @interval_us - polling interval in microsecs
573 * @timeout_ms - timeout in millisecs
596585a2 574 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 575 *
576 * Returns -ETIMEDOUT on error, zero on success
577 */
596585a2
YG		 578int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
579 u32 val, unsigned long interval_us,
580 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 581{
582 int err = 0;
583 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
584
585 /* ignore bits that we don't intend to wait on */
586 val = val & mask;
587
588 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 589 if (can_sleep)
590 usleep_range(interval_us, interval_us + 50);
591 else
592 udelay(interval_us);
5a0b0cb9
SRT		 593 if (time_after(jiffies, timeout)) {
594 if ((ufshcd_readl(hba, reg) & mask) != val)
595 err = -ETIMEDOUT;
596 break;
597 }
598 }
599
600 return err;
601}
602
2fbd009b
SJ		 603/**
604 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 605 * @hba: Pointer to adapter instance
2fbd009b
SJ		 606 *
607 * Returns interrupt bit mask per version
608 */
609static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
610{
c01848c6
YG		 611 u32 intr_mask = 0;
612
613 switch (hba->ufs_version) {
614 case UFSHCI_VERSION_10:
615 intr_mask = INTERRUPT_MASK_ALL_VER_10;
616 break;
c01848c6
YG		 617 case UFSHCI_VERSION_11:
618 case UFSHCI_VERSION_20:
619 intr_mask = INTERRUPT_MASK_ALL_VER_11;
620 break;
c01848c6
YG		 621 case UFSHCI_VERSION_21:
622 default:
623 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 624 break;
c01848c6
YG		 625 }
626
627 return intr_mask;
2fbd009b
SJ		 628}
629
7a3e97b0
SY		 630/**
631 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 632 * @hba: Pointer to adapter instance
7a3e97b0
SY		 633 *
634 * Returns UFSHCI version supported by the controller
635 */
636static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
637{
0263bcd0
YG		 638 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
639 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 640
b873a275 641 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 642}
643
644/**
645 * ufshcd_is_device_present - Check if any device connected to
646 * the host controller
5c0c28a8 647 * @hba: pointer to adapter instance
7a3e97b0 648 *
c9e6010b 649 * Returns true if device present, false if no device detected
7a3e97b0 650 */
c9e6010b 651static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 652{
5c0c28a8 653 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 654 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 655}
656
657/**
658 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 659 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 660 *
661 * This function is used to get the OCS field from UTRD
662 * Returns the OCS field in the UTRD
663 */
664static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
665{
e8c8e82a 666 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 667}
668
7a3e97b0
SY		 669/**
670 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
671 * @hba: per adapter instance
672 * @pos: position of the bit to be cleared
673 */
674static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
675{
49200199 676 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 677}
678
679/**
680 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
681 * @hba: per adapter instance
682 * @pos: position of the bit to be cleared
683 */
684static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
685{
49200199 686 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 687}
688
a48353f6
YG		 689/**
690 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
691 * @hba: per adapter instance
692 * @tag: position of the bit to be cleared
693 */
694static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
695{
696 __clear_bit(tag, &hba->outstanding_reqs);
697}
698
7a3e97b0
SY		 699/**
700 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
701 * @reg: Register value of host controller status
702 *
703 * Returns integer, 0 on Success and positive value if failed
704 */
705static inline int ufshcd_get_lists_status(u32 reg)
706{
6cf16115 707 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 708}
709
710/**
711 * ufshcd_get_uic_cmd_result - Get the UIC command result
712 * @hba: Pointer to adapter instance
713 *
714 * This function gets the result of UIC command completion
715 * Returns 0 on success, non zero value on error
716 */
717static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
718{
b873a275 719 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 720 MASK_UIC_COMMAND_RESULT;
721}
722
12b4fdb4
SJ		 723/**
724 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
725 * @hba: Pointer to adapter instance
726 *
727 * This function gets UIC command argument3
728 * Returns 0 on success, non zero value on error
729 */
730static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
731{
732 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
733}
734
7a3e97b0 735/**
5a0b0cb9 736 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 737 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 738 */
739static inline int
5a0b0cb9 740ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 741{
5a0b0cb9 742 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 743}
744
745/**
746 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
747 * @ucd_rsp_ptr: pointer to response UPIU
748 *
749 * This function gets the response status and scsi_status from response UPIU
750 * Returns the response result code.
751 */
752static inline int
753ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
754{
755 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
756}
757
1c2623c5
SJ		 758/*
759 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
760 * from response UPIU
761 * @ucd_rsp_ptr: pointer to response UPIU
762 *
763 * Return the data segment length.
764 */
765static inline unsigned int
766ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
767{
768 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
769 MASK_RSP_UPIU_DATA_SEG_LEN;
770}
771
66ec6d59
SRT		 772/**
773 * ufshcd_is_exception_event - Check if the device raised an exception event
774 * @ucd_rsp_ptr: pointer to response UPIU
775 *
776 * The function checks if the device raised an exception event indicated in
777 * the Device Information field of response UPIU.
778 *
779 * Returns true if exception is raised, false otherwise.
780 */
781static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
782{
783 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
784 MASK_RSP_EXCEPTION_EVENT ? true : false;
785}
786
7a3e97b0 787/**
7d568652 788 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 789 * @hba: per adapter instance
7a3e97b0
SY		 790 */
791static inline void
7d568652 792ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 793{
7d568652
SJ		 794 ufshcd_writel(hba, INT_AGGR_ENABLE |
795 INT_AGGR_COUNTER_AND_TIMER_RESET,
796 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
797}
798
799/**
800 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
801 * @hba: per adapter instance
802 * @cnt: Interrupt aggregation counter threshold
803 * @tmout: Interrupt aggregation timeout value
804 */
805static inline void
806ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
807{
808 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
809 INT_AGGR_COUNTER_THLD_VAL(cnt) |
810 INT_AGGR_TIMEOUT_VAL(tmout),
811 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 812}
813
b852190e
YG		 814/**
815 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
816 * @hba: per adapter instance
817 */
818static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
819{
820 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
821}
822
7a3e97b0
SY		 823/**
824 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
825 * When run-stop registers are set to 1, it indicates the
826 * host controller that it can process the requests
827 * @hba: per adapter instance
828 */
829static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
830{
b873a275
SJ		 831 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
832 REG_UTP_TASK_REQ_LIST_RUN_STOP);
833 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
834 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 835}
836
7a3e97b0
SY		 837/**
838 * ufshcd_hba_start - Start controller initialization sequence
839 * @hba: per adapter instance
840 */
841static inline void ufshcd_hba_start(struct ufs_hba *hba)
842{
b873a275 843 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 844}
845
846/**
847 * ufshcd_is_hba_active - Get controller state
848 * @hba: per adapter instance
849 *
c9e6010b 850 * Returns false if controller is active, true otherwise
7a3e97b0 851 */
c9e6010b 852static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 853{
4a8eec2b
TK		 854 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
855 ? false : true;
7a3e97b0
SY		 856}
857
37113106
YG		 858u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
859{
860 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
861 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
862 (hba->ufs_version == UFSHCI_VERSION_11))
863 return UFS_UNIPRO_VER_1_41;
864 else
865 return UFS_UNIPRO_VER_1_6;
866}
867EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
868
869static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
870{
871 /*
872 * If both host and device support UniPro ver1.6 or later, PA layer
873 * parameters tuning happens during link startup itself.
874 *
875 * We can manually tune PA layer parameters if either host or device
876 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
877 * logic simple, we will only do manual tuning if local unipro version
878 * doesn't support ver1.6 or later.
879 */
880 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
881 return true;
882 else
883 return false;
884}
885
394b949f
SJ		 886/**
887 * ufshcd_set_clk_freq - set UFS controller clock frequencies
888 * @hba: per adapter instance
889 * @scale_up: If True, set max possible frequency othewise set low frequency
890 *
891 * Returns 0 if successful
892 * Returns < 0 for any other errors
893 */
894static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 895{
896 int ret = 0;
897 struct ufs_clk_info *clki;
898 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 899
566ec9ad 900 if (list_empty(head))
a3cd5ec5 901 goto out;
902
a3cd5ec5 903 list_for_each_entry(clki, head, list) {
904 if (!IS_ERR_OR_NULL(clki->clk)) {
905 if (scale_up && clki->max_freq) {
906 if (clki->curr_freq == clki->max_freq)
907 continue;
908
a3cd5ec5 909 ret = clk_set_rate(clki->clk, clki->max_freq);
910 if (ret) {
911 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
912 __func__, clki->name,
913 clki->max_freq, ret);
914 break;
915 }
916 trace_ufshcd_clk_scaling(dev_name(hba->dev),
917 "scaled up", clki->name,
918 clki->curr_freq,
919 clki->max_freq);
920
921 clki->curr_freq = clki->max_freq;
922
923 } else if (!scale_up && clki->min_freq) {
924 if (clki->curr_freq == clki->min_freq)
925 continue;
926
a3cd5ec5 927 ret = clk_set_rate(clki->clk, clki->min_freq);
928 if (ret) {
929 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
930 __func__, clki->name,
931 clki->min_freq, ret);
932 break;
933 }
934 trace_ufshcd_clk_scaling(dev_name(hba->dev),
935 "scaled down", clki->name,
936 clki->curr_freq,
937 clki->min_freq);
938 clki->curr_freq = clki->min_freq;
939 }
940 }
941 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
942 clki->name, clk_get_rate(clki->clk));
943 }
944
394b949f
SJ		 945out:
946 return ret;
947}
948
949/**
950 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
951 * @hba: per adapter instance
952 * @scale_up: True if scaling up and false if scaling down
953 *
954 * Returns 0 if successful
955 * Returns < 0 for any other errors
956 */
957static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
958{
959 int ret = 0;
960 ktime_t start = ktime_get();
961
962 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
963 if (ret)
964 goto out;
965
966 ret = ufshcd_set_clk_freq(hba, scale_up);
967 if (ret)
968 goto out;
969
a3cd5ec5 970 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 971 if (ret)
972 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 973
974out:
394b949f 975 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 976 (scale_up ? "up" : "down"),
977 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
978 return ret;
979}
980
981/**
982 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
983 * @hba: per adapter instance
984 * @scale_up: True if scaling up and false if scaling down
985 *
986 * Returns true if scaling is required, false otherwise.
987 */
988static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
989 bool scale_up)
990{
991 struct ufs_clk_info *clki;
992 struct list_head *head = &hba->clk_list_head;
993
566ec9ad 994 if (list_empty(head))
a3cd5ec5 995 return false;
996
997 list_for_each_entry(clki, head, list) {
998 if (!IS_ERR_OR_NULL(clki->clk)) {
999 if (scale_up && clki->max_freq) {
1000 if (clki->curr_freq == clki->max_freq)
1001 continue;
1002 return true;
1003 } else if (!scale_up && clki->min_freq) {
1004 if (clki->curr_freq == clki->min_freq)
1005 continue;
1006 return true;
1007 }
1008 }
1009 }
1010
1011 return false;
1012}
1013
1014static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1015 u64 wait_timeout_us)
1016{
1017 unsigned long flags;
1018 int ret = 0;
1019 u32 tm_doorbell;
1020 u32 tr_doorbell;
1021 bool timeout = false, do_last_check = false;
1022 ktime_t start;
1023
1024 ufshcd_hold(hba, false);
1025 spin_lock_irqsave(hba->host->host_lock, flags);
1026 /*
1027 * Wait for all the outstanding tasks/transfer requests.
1028 * Verify by checking the doorbell registers are clear.
1029 */
1030 start = ktime_get();
1031 do {
1032 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1033 ret = -EBUSY;
1034 goto out;
1035 }
1036
1037 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1038 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1039 if (!tm_doorbell && !tr_doorbell) {
1040 timeout = false;
1041 break;
1042 } else if (do_last_check) {
1043 break;
1044 }
1045
1046 spin_unlock_irqrestore(hba->host->host_lock, flags);
1047 schedule();
1048 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1049 wait_timeout_us) {
1050 timeout = true;
1051 /*
1052 * We might have scheduled out for long time so make
1053 * sure to check if doorbells are cleared by this time
1054 * or not.
1055 */
1056 do_last_check = true;
1057 }
1058 spin_lock_irqsave(hba->host->host_lock, flags);
1059 } while (tm_doorbell || tr_doorbell);
1060
1061 if (timeout) {
1062 dev_err(hba->dev,
1063 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1064 __func__, tm_doorbell, tr_doorbell);
1065 ret = -EBUSY;
1066 }
1067out:
1068 spin_unlock_irqrestore(hba->host->host_lock, flags);
1069 ufshcd_release(hba);
1070 return ret;
1071}
1072
1073/**
1074 * ufshcd_scale_gear - scale up/down UFS gear
1075 * @hba: per adapter instance
1076 * @scale_up: True for scaling up gear and false for scaling down
1077 *
1078 * Returns 0 for success,
1079 * Returns -EBUSY if scaling can't happen at this time
1080 * Returns non-zero for any other errors
1081 */
1082static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1083{
1084 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1085 int ret = 0;
1086 struct ufs_pa_layer_attr new_pwr_info;
1087
1088 if (scale_up) {
1089 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1090 sizeof(struct ufs_pa_layer_attr));
1091 } else {
1092 memcpy(&new_pwr_info, &hba->pwr_info,
1093 sizeof(struct ufs_pa_layer_attr));
1094
1095 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1096 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1097 /* save the current power mode */
1098 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1099 &hba->pwr_info,
1100 sizeof(struct ufs_pa_layer_attr));
1101
1102 /* scale down gear */
1103 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1104 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1105 }
1106 }
1107
1108 /* check if the power mode needs to be changed or not? */
6a9df818 1109 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1110 if (ret)
1111 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1112 __func__, ret,
1113 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1114 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1115
1116 return ret;
1117}
1118
1119static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1120{
1121 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1122 int ret = 0;
1123 /*
1124 * make sure that there are no outstanding requests when
1125 * clock scaling is in progress
1126 */
38135535 1127 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1128 down_write(&hba->clk_scaling_lock);
1129 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1130 ret = -EBUSY;
1131 up_write(&hba->clk_scaling_lock);
38135535 1132 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1133 }
1134
1135 return ret;
1136}
1137
1138static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1139{
1140 up_write(&hba->clk_scaling_lock);
38135535 1141 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5 1142}
1143
1144/**
1145 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1146 * @hba: per adapter instance
1147 * @scale_up: True for scaling up and false for scalin down
1148 *
1149 * Returns 0 for success,
1150 * Returns -EBUSY if scaling can't happen at this time
1151 * Returns non-zero for any other errors
1152 */
1153static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1154{
1155 int ret = 0;
1156
401f1e44 1157 /* let's not get into low power until clock scaling is completed */
1158 ufshcd_hold(hba, false);
1159
a3cd5ec5 1160 ret = ufshcd_clock_scaling_prepare(hba);
1161 if (ret)
394b949f 1162 goto out;
a3cd5ec5 1163
1164 /* scale down the gear before scaling down clocks */
1165 if (!scale_up) {
1166 ret = ufshcd_scale_gear(hba, false);
1167 if (ret)
394b949f 1168 goto out_unprepare;
a3cd5ec5 1169 }
1170
1171 ret = ufshcd_scale_clks(hba, scale_up);
1172 if (ret) {
1173 if (!scale_up)
1174 ufshcd_scale_gear(hba, true);
394b949f 1175 goto out_unprepare;
a3cd5ec5 1176 }
1177
1178 /* scale up the gear after scaling up clocks */
1179 if (scale_up) {
1180 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1181 if (ret) {
a3cd5ec5 1182 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1183 goto out_unprepare;
1184 }
a3cd5ec5 1185 }
1186
3d17b9b5
AD		 1187 /* Enable Write Booster if we have scaled up else disable it */
1188 up_write(&hba->clk_scaling_lock);
1189 ufshcd_wb_ctrl(hba, scale_up);
1190 down_write(&hba->clk_scaling_lock);
1191
394b949f 1192out_unprepare:
a3cd5ec5 1193 ufshcd_clock_scaling_unprepare(hba);
394b949f 1194out:
401f1e44 1195 ufshcd_release(hba);
a3cd5ec5 1196 return ret;
1197}
1198
401f1e44 1199static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1200{
1201 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1202 clk_scaling.suspend_work);
1203 unsigned long irq_flags;
1204
1205 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1206 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1207 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1208 return;
1209 }
1210 hba->clk_scaling.is_suspended = true;
1211 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1212
1213 __ufshcd_suspend_clkscaling(hba);
1214}
1215
1216static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1217{
1218 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1219 clk_scaling.resume_work);
1220 unsigned long irq_flags;
1221
1222 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1223 if (!hba->clk_scaling.is_suspended) {
1224 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1225 return;
1226 }
1227 hba->clk_scaling.is_suspended = false;
1228 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1229
1230 devfreq_resume_device(hba->devfreq);
1231}
1232
a3cd5ec5 1233static int ufshcd_devfreq_target(struct device *dev,
1234 unsigned long *freq, u32 flags)
1235{
1236 int ret = 0;
1237 struct ufs_hba *hba = dev_get_drvdata(dev);
1238 ktime_t start;
401f1e44 1239 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1240 struct list_head *clk_list = &hba->clk_list_head;
1241 struct ufs_clk_info *clki;
a3cd5ec5 1242 unsigned long irq_flags;
1243
1244 if (!ufshcd_is_clkscaling_supported(hba))
1245 return -EINVAL;
1246
91831d33
AD		 1247 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1248 /* Override with the closest supported frequency */
1249 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1250 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1251 if (ufshcd_eh_in_progress(hba)) {
1252 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1253 return 0;
1254 }
1255
401f1e44 1256 if (!hba->clk_scaling.active_reqs)
1257 sched_clk_scaling_suspend_work = true;
1258
092b4558
BA		 1259 if (list_empty(clk_list)) {
1260 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1261 goto out;
1262 }
1263
91831d33 1264 /* Decide based on the rounded-off frequency and update */
092b4558 1265 scale_up = (*freq == clki->max_freq) ? true : false;
91831d33
AD		 1266 if (!scale_up)
1267 *freq = clki->min_freq;
1268 /* Update the frequency */
401f1e44 1269 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1270 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1271 ret = 0;
1272 goto out; /* no state change required */
a3cd5ec5 1273 }
1274 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1275
1276 start = ktime_get();
a3cd5ec5 1277 ret = ufshcd_devfreq_scale(hba, scale_up);
1278
a3cd5ec5 1279 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1280 (scale_up ? "up" : "down"),
1281 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1282
401f1e44 1283out:
1284 if (sched_clk_scaling_suspend_work)
1285 queue_work(hba->clk_scaling.workq,
1286 &hba->clk_scaling.suspend_work);
1287
a3cd5ec5 1288 return ret;
1289}
1290
7252a360
BVA		 1291static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1292{
1293 int *busy = priv;
1294
1295 WARN_ON_ONCE(reserved);
1296 (*busy)++;
1297 return false;
1298}
1299
1300/* Whether or not any tag is in use by a request that is in progress. */
1301static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1302{
1303 struct request_queue *q = hba->cmd_queue;
1304 int busy = 0;
1305
1306 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1307 return busy;
1308}
a3cd5ec5 1309
1310static int ufshcd_devfreq_get_dev_status(struct device *dev,
1311 struct devfreq_dev_status *stat)
1312{
1313 struct ufs_hba *hba = dev_get_drvdata(dev);
1314 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1315 unsigned long flags;
91831d33
AD		 1316 struct list_head *clk_list = &hba->clk_list_head;
1317 struct ufs_clk_info *clki;
a3cd5ec5 1318
1319 if (!ufshcd_is_clkscaling_supported(hba))
1320 return -EINVAL;
1321
1322 memset(stat, 0, sizeof(*stat));
1323
1324 spin_lock_irqsave(hba->host->host_lock, flags);
1325 if (!scaling->window_start_t)
1326 goto start_window;
1327
91831d33
AD		 1328 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1329 /*
1330 * If current frequency is 0, then the ondemand governor considers
1331 * there's no initial frequency set. And it always requests to set
1332 * to max. frequency.
1333 */
1334 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1335 if (scaling->is_busy_started)
1336 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1337 scaling->busy_start_t));
1338
1339 stat->total_time = jiffies_to_usecs((long)jiffies -
1340 (long)scaling->window_start_t);
1341 stat->busy_time = scaling->tot_busy_t;
1342start_window:
1343 scaling->window_start_t = jiffies;
1344 scaling->tot_busy_t = 0;
1345
1346 if (hba->outstanding_reqs) {
1347 scaling->busy_start_t = ktime_get();
1348 scaling->is_busy_started = true;
1349 } else {
1350 scaling->busy_start_t = 0;
1351 scaling->is_busy_started = false;
1352 }
1353 spin_unlock_irqrestore(hba->host->host_lock, flags);
1354 return 0;
1355}
1356
1357static struct devfreq_dev_profile ufs_devfreq_profile = {
1358 .polling_ms = 100,
1359 .target = ufshcd_devfreq_target,
1360 .get_dev_status = ufshcd_devfreq_get_dev_status,
1361};
1362
2c75f9a5
AD		 1363#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1364static struct devfreq_simple_ondemand_data ufs_ondemand_data = {
1365 .upthreshold = 70,
1366 .downdifferential = 5,
1367};
1368
1369static void *gov_data = &ufs_ondemand_data;
1370#else
1371static void *gov_data; /* NULL */
1372#endif
1373
deac444f
BA		 1374static int ufshcd_devfreq_init(struct ufs_hba *hba)
1375{
092b4558
BA		 1376 struct list_head *clk_list = &hba->clk_list_head;
1377 struct ufs_clk_info *clki;
deac444f
BA		 1378 struct devfreq *devfreq;
1379 int ret;
1380
092b4558
BA		 1381 /* Skip devfreq if we don't have any clocks in the list */
1382 if (list_empty(clk_list))
1383 return 0;
1384
1385 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1386 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1387 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1388
2c75f9a5
AD		 1389 ufshcd_vops_config_scaling_param(hba, &ufs_devfreq_profile,
1390 gov_data);
092b4558 1391 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1392 &ufs_devfreq_profile,
1393 DEVFREQ_GOV_SIMPLE_ONDEMAND,
2c75f9a5 1394 gov_data);
deac444f
BA		 1395 if (IS_ERR(devfreq)) {
1396 ret = PTR_ERR(devfreq);
1397 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1398
1399 dev_pm_opp_remove(hba->dev, clki->min_freq);
1400 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1401 return ret;
1402 }
1403
1404 hba->devfreq = devfreq;
1405
1406 return 0;
1407}
1408
092b4558
BA		 1409static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1410{
1411 struct list_head *clk_list = &hba->clk_list_head;
1412 struct ufs_clk_info *clki;
1413
1414 if (!hba->devfreq)
1415 return;
1416
1417 devfreq_remove_device(hba->devfreq);
1418 hba->devfreq = NULL;
1419
1420 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1421 dev_pm_opp_remove(hba->dev, clki->min_freq);
1422 dev_pm_opp_remove(hba->dev, clki->max_freq);
1423}
1424
401f1e44 1425static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1426{
1427 unsigned long flags;
1428
1429 devfreq_suspend_device(hba->devfreq);
1430 spin_lock_irqsave(hba->host->host_lock, flags);
1431 hba->clk_scaling.window_start_t = 0;
1432 spin_unlock_irqrestore(hba->host->host_lock, flags);
1433}
a3cd5ec5 1434
a508253d
GB		 1435static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1436{
401f1e44 1437 unsigned long flags;
1438 bool suspend = false;
1439
fcb0c4b0
ST		 1440 if (!ufshcd_is_clkscaling_supported(hba))
1441 return;
1442
401f1e44 1443 spin_lock_irqsave(hba->host->host_lock, flags);
1444 if (!hba->clk_scaling.is_suspended) {
1445 suspend = true;
1446 hba->clk_scaling.is_suspended = true;
1447 }
1448 spin_unlock_irqrestore(hba->host->host_lock, flags);
1449
1450 if (suspend)
1451 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1452}
1453
1454static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1455{
401f1e44 1456 unsigned long flags;
1457 bool resume = false;
1458
1459 if (!ufshcd_is_clkscaling_supported(hba))
1460 return;
1461
1462 spin_lock_irqsave(hba->host->host_lock, flags);
1463 if (hba->clk_scaling.is_suspended) {
1464 resume = true;
1465 hba->clk_scaling.is_suspended = false;
1466 }
1467 spin_unlock_irqrestore(hba->host->host_lock, flags);
1468
1469 if (resume)
1470 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1471}
1472
1473static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1474 struct device_attribute *attr, char *buf)
1475{
1476 struct ufs_hba *hba = dev_get_drvdata(dev);
1477
1478 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1479}
1480
1481static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1482 struct device_attribute *attr, const char *buf, size_t count)
1483{
1484 struct ufs_hba *hba = dev_get_drvdata(dev);
1485 u32 value;
1486 int err;
1487
1488 if (kstrtou32(buf, 0, &value))
1489 return -EINVAL;
1490
1491 value = !!value;
1492 if (value == hba->clk_scaling.is_allowed)
1493 goto out;
1494
1495 pm_runtime_get_sync(hba->dev);
1496 ufshcd_hold(hba, false);
1497
401f1e44 1498 cancel_work_sync(&hba->clk_scaling.suspend_work);
1499 cancel_work_sync(&hba->clk_scaling.resume_work);
1500
1501 hba->clk_scaling.is_allowed = value;
1502
fcb0c4b0
ST		 1503 if (value) {
1504 ufshcd_resume_clkscaling(hba);
1505 } else {
1506 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1507 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1508 if (err)
1509 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1510 __func__, err);
1511 }
fcb0c4b0
ST		 1512
1513 ufshcd_release(hba);
1514 pm_runtime_put_sync(hba->dev);
1515out:
1516 return count;
a508253d
GB		 1517}
1518
a3cd5ec5 1519static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1520{
1521 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1522 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1523 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1524 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1525 hba->clk_scaling.enable_attr.attr.mode = 0644;
1526 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1527 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1528}
1529
1ab27c9c
ST		 1530static void ufshcd_ungate_work(struct work_struct *work)
1531{
1532 int ret;
1533 unsigned long flags;
1534 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1535 clk_gating.ungate_work);
1536
1537 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1538
1539 spin_lock_irqsave(hba->host->host_lock, flags);
1540 if (hba->clk_gating.state == CLKS_ON) {
1541 spin_unlock_irqrestore(hba->host->host_lock, flags);
1542 goto unblock_reqs;
1543 }
1544
1545 spin_unlock_irqrestore(hba->host->host_lock, flags);
1546 ufshcd_setup_clocks(hba, true);
1547
8b0bbf00
SC		 1548 ufshcd_enable_irq(hba);
1549
1ab27c9c
ST		 1550 /* Exit from hibern8 */
1551 if (ufshcd_can_hibern8_during_gating(hba)) {
1552 /* Prevent gating in this path */
1553 hba->clk_gating.is_suspended = true;
1554 if (ufshcd_is_link_hibern8(hba)) {
1555 ret = ufshcd_uic_hibern8_exit(hba);
1556 if (ret)
1557 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1558 __func__, ret);
1559 else
1560 ufshcd_set_link_active(hba);
1561 }
1562 hba->clk_gating.is_suspended = false;
1563 }
1564unblock_reqs:
38135535 1565 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1566}
1567
1568/**
1569 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1570 * Also, exit from hibern8 mode and set the link as active.
1571 * @hba: per adapter instance
1572 * @async: This indicates whether caller should ungate clocks asynchronously.
1573 */
1574int ufshcd_hold(struct ufs_hba *hba, bool async)
1575{
1576 int rc = 0;
1577 unsigned long flags;
1578
1579 if (!ufshcd_is_clkgating_allowed(hba))
1580 goto out;
1ab27c9c
ST		 1581 spin_lock_irqsave(hba->host->host_lock, flags);
1582 hba->clk_gating.active_reqs++;
1583
53c12d0e
YG		 1584 if (ufshcd_eh_in_progress(hba)) {
1585 spin_unlock_irqrestore(hba->host->host_lock, flags);
1586 return 0;
1587 }
1588
856b3483 1589start:
1ab27c9c
ST		 1590 switch (hba->clk_gating.state) {
1591 case CLKS_ON:
f2a785ac
VG		 1592 /*
1593 * Wait for the ungate work to complete if in progress.
1594 * Though the clocks may be in ON state, the link could
1595 * still be in hibner8 state if hibern8 is allowed
1596 * during clock gating.
1597 * Make sure we exit hibern8 state also in addition to
1598 * clocks being ON.
1599 */
1600 if (ufshcd_can_hibern8_during_gating(hba) &&
1601 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1602 if (async) {
1603 rc = -EAGAIN;
1604 hba->clk_gating.active_reqs--;
1605 break;
1606 }
f2a785ac
VG		 1607 spin_unlock_irqrestore(hba->host->host_lock, flags);
1608 flush_work(&hba->clk_gating.ungate_work);
1609 spin_lock_irqsave(hba->host->host_lock, flags);
1610 goto start;
1611 }
1ab27c9c
ST		 1612 break;
1613 case REQ_CLKS_OFF:
1614 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1615 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1616 trace_ufshcd_clk_gating(dev_name(hba->dev),
1617 hba->clk_gating.state);
1ab27c9c
ST		 1618 break;
1619 }
1620 /*
9c490d2d 1621 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1622 * currently running. Hence, fall through to cancel gating
1623 * work and to enable clocks.
1624 */
30eb2e4c 1625 /* fallthrough */
1ab27c9c 1626 case CLKS_OFF:
38135535 1627 ufshcd_scsi_block_requests(hba);
1ab27c9c 1628 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1629 trace_ufshcd_clk_gating(dev_name(hba->dev),
1630 hba->clk_gating.state);
10e5e375
VV		 1631 queue_work(hba->clk_gating.clk_gating_workq,
1632 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1633 /*
1634 * fall through to check if we should wait for this
1635 * work to be done or not.
1636 */
30eb2e4c 1637 /* fallthrough */
1ab27c9c
ST		 1638 case REQ_CLKS_ON:
1639 if (async) {
1640 rc = -EAGAIN;
1641 hba->clk_gating.active_reqs--;
1642 break;
1643 }
1644
1645 spin_unlock_irqrestore(hba->host->host_lock, flags);
1646 flush_work(&hba->clk_gating.ungate_work);
1647 /* Make sure state is CLKS_ON before returning */
856b3483 1648 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1649 goto start;
1650 default:
1651 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1652 __func__, hba->clk_gating.state);
1653 break;
1654 }
1655 spin_unlock_irqrestore(hba->host->host_lock, flags);
1656out:
1657 return rc;
1658}
6e3fd44d 1659EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1660
1661static void ufshcd_gate_work(struct work_struct *work)
1662{
1663 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1664 clk_gating.gate_work.work);
1665 unsigned long flags;
1666
1667 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1668 /*
1669 * In case you are here to cancel this work the gating state
1670 * would be marked as REQ_CLKS_ON. In this case save time by
1671 * skipping the gating work and exit after changing the clock
1672 * state to CLKS_ON.
1673 */
1674 if (hba->clk_gating.is_suspended ||
18f01374 1675 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1676 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1677 trace_ufshcd_clk_gating(dev_name(hba->dev),
1678 hba->clk_gating.state);
1ab27c9c
ST		 1679 goto rel_lock;
1680 }
1681
1682 if (hba->clk_gating.active_reqs
1683 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1684 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1ab27c9c
ST		 1685 || hba->active_uic_cmd || hba->uic_async_done)
1686 goto rel_lock;
1687
1688 spin_unlock_irqrestore(hba->host->host_lock, flags);
1689
1690 /* put the link into hibern8 mode before turning off clocks */
1691 if (ufshcd_can_hibern8_during_gating(hba)) {
1692 if (ufshcd_uic_hibern8_enter(hba)) {
1693 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1694 trace_ufshcd_clk_gating(dev_name(hba->dev),
1695 hba->clk_gating.state);
1ab27c9c
ST		 1696 goto out;
1697 }
1698 ufshcd_set_link_hibern8(hba);
1699 }
1700
8b0bbf00
SC		 1701 ufshcd_disable_irq(hba);
1702
1ab27c9c
ST		 1703 if (!ufshcd_is_link_active(hba))
1704 ufshcd_setup_clocks(hba, false);
1705 else
1706 /* If link is active, device ref_clk can't be switched off */
1707 __ufshcd_setup_clocks(hba, false, true);
1708
1709 /*
1710 * In case you are here to cancel this work the gating state
1711 * would be marked as REQ_CLKS_ON. In this case keep the state
1712 * as REQ_CLKS_ON which would anyway imply that clocks are off
1713 * and a request to turn them on is pending. By doing this way,
1714 * we keep the state machine in tact and this would ultimately
1715 * prevent from doing cancel work multiple times when there are
1716 * new requests arriving before the current cancel work is done.
1717 */
1718 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1719 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1720 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1721 trace_ufshcd_clk_gating(dev_name(hba->dev),
1722 hba->clk_gating.state);
1723 }
1ab27c9c
ST		 1724rel_lock:
1725 spin_unlock_irqrestore(hba->host->host_lock, flags);
1726out:
1727 return;
1728}
1729
1730/* host lock must be held before calling this variant */
1731static void __ufshcd_release(struct ufs_hba *hba)
1732{
1733 if (!ufshcd_is_clkgating_allowed(hba))
1734 return;
1735
1736 hba->clk_gating.active_reqs--;
1737
1738 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1739 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1740 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
53c12d0e
YG		 1741 || hba->active_uic_cmd || hba->uic_async_done
1742 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1743 return;
1744
1745 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1746 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1747 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1748 &hba->clk_gating.gate_work,
1749 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1750}
1751
1752void ufshcd_release(struct ufs_hba *hba)
1753{
1754 unsigned long flags;
1755
1756 spin_lock_irqsave(hba->host->host_lock, flags);
1757 __ufshcd_release(hba);
1758 spin_unlock_irqrestore(hba->host->host_lock, flags);
1759}
6e3fd44d 1760EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1761
1762static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1763 struct device_attribute *attr, char *buf)
1764{
1765 struct ufs_hba *hba = dev_get_drvdata(dev);
1766
1767 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1768}
1769
1770static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1771 struct device_attribute *attr, const char *buf, size_t count)
1772{
1773 struct ufs_hba *hba = dev_get_drvdata(dev);
1774 unsigned long flags, value;
1775
1776 if (kstrtoul(buf, 0, &value))
1777 return -EINVAL;
1778
1779 spin_lock_irqsave(hba->host->host_lock, flags);
1780 hba->clk_gating.delay_ms = value;
1781 spin_unlock_irqrestore(hba->host->host_lock, flags);
1782 return count;
1783}
1784
b427411a
ST		 1785static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1786 struct device_attribute *attr, char *buf)
1787{
1788 struct ufs_hba *hba = dev_get_drvdata(dev);
1789
1790 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1791}
1792
1793static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1794 struct device_attribute *attr, const char *buf, size_t count)
1795{
1796 struct ufs_hba *hba = dev_get_drvdata(dev);
1797 unsigned long flags;
1798 u32 value;
1799
1800 if (kstrtou32(buf, 0, &value))
1801 return -EINVAL;
1802
1803 value = !!value;
1804 if (value == hba->clk_gating.is_enabled)
1805 goto out;
1806
1807 if (value) {
1808 ufshcd_release(hba);
1809 } else {
1810 spin_lock_irqsave(hba->host->host_lock, flags);
1811 hba->clk_gating.active_reqs++;
1812 spin_unlock_irqrestore(hba->host->host_lock, flags);
1813 }
1814
1815 hba->clk_gating.is_enabled = value;
1816out:
1817 return count;
1818}
1819
eebcc196
VG		 1820static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1821{
1822 char wq_name[sizeof("ufs_clkscaling_00")];
1823
1824 if (!ufshcd_is_clkscaling_supported(hba))
1825 return;
1826
1827 INIT_WORK(&hba->clk_scaling.suspend_work,
1828 ufshcd_clk_scaling_suspend_work);
1829 INIT_WORK(&hba->clk_scaling.resume_work,
1830 ufshcd_clk_scaling_resume_work);
1831
1832 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1833 hba->host->host_no);
1834 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1835
1836 ufshcd_clkscaling_init_sysfs(hba);
1837}
1838
1839static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1840{
1841 if (!ufshcd_is_clkscaling_supported(hba))
1842 return;
1843
1844 destroy_workqueue(hba->clk_scaling.workq);
1845 ufshcd_devfreq_remove(hba);
1846}
1847
1ab27c9c
ST		 1848static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1849{
10e5e375
VV		 1850 char wq_name[sizeof("ufs_clk_gating_00")];
1851
1ab27c9c
ST		 1852 if (!ufshcd_is_clkgating_allowed(hba))
1853 return;
1854
1855 hba->clk_gating.delay_ms = 150;
1856 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1857 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1858
10e5e375
VV		 1859 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1860 hba->host->host_no);
1861 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1862 WQ_MEM_RECLAIM);
1863
b427411a
ST		 1864 hba->clk_gating.is_enabled = true;
1865
1ab27c9c
ST		 1866 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1867 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1868 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1869 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1870 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1871 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1872 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1873
1874 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1875 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1876 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1877 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1878 hba->clk_gating.enable_attr.attr.mode = 0644;
1879 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1880 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1881}
1882
1883static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1884{
1885 if (!ufshcd_is_clkgating_allowed(hba))
1886 return;
1887 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1888 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1889 cancel_work_sync(&hba->clk_gating.ungate_work);
1890 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1891 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1892}
1893
856b3483
ST		 1894/* Must be called with host lock acquired */
1895static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1896{
401f1e44 1897 bool queue_resume_work = false;
1898
fcb0c4b0 1899 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1900 return;
1901
401f1e44 1902 if (!hba->clk_scaling.active_reqs++)
1903 queue_resume_work = true;
1904
1905 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1906 return;
1907
1908 if (queue_resume_work)
1909 queue_work(hba->clk_scaling.workq,
1910 &hba->clk_scaling.resume_work);
1911
1912 if (!hba->clk_scaling.window_start_t) {
1913 hba->clk_scaling.window_start_t = jiffies;
1914 hba->clk_scaling.tot_busy_t = 0;
1915 hba->clk_scaling.is_busy_started = false;
1916 }
1917
856b3483
ST		 1918 if (!hba->clk_scaling.is_busy_started) {
1919 hba->clk_scaling.busy_start_t = ktime_get();
1920 hba->clk_scaling.is_busy_started = true;
1921 }
1922}
1923
1924static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1925{
1926 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1927
fcb0c4b0 1928 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1929 return;
1930
1931 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1932 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1933 scaling->busy_start_t));
8b0e1953 1934 scaling->busy_start_t = 0;
856b3483
ST		 1935 scaling->is_busy_started = false;
1936 }
1937}
7a3e97b0
SY		 1938/**
1939 * ufshcd_send_command - Send SCSI or device management commands
1940 * @hba: per adapter instance
1941 * @task_tag: Task tag of the command
1942 */
1943static inline
1944void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1945{
ff8e20c6 1946 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1947 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
eacf36f5 1948 ufshcd_add_command_trace(hba, task_tag, "send");
856b3483 1949 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1950 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1951 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1952 /* Make sure that doorbell is committed immediately */
1953 wmb();
7a3e97b0
SY		 1954}
1955
1956/**
1957 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1958 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1959 */
1960static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1961{
1962 int len;
1c2623c5
SJ		 1963 if (lrbp->sense_buffer &&
1964 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1965 int len_to_copy;
1966
5a0b0cb9 1967 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 1968 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 1969
09a5a24f
AA		 1970 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1971 len_to_copy);
7a3e97b0
SY		 1972 }
1973}
1974
68078d5c
DR		 1975/**
1976 * ufshcd_copy_query_response() - Copy the Query Response and the data
1977 * descriptor
1978 * @hba: per adapter instance
8aa29f19 1979 * @lrbp: pointer to local reference block
68078d5c
DR		 1980 */
1981static
c6d4a831 1982int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1983{
1984 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1985
68078d5c 1986 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1987
68078d5c 1988 /* Get the descriptor */
1c90836f
AA		 1989 if (hba->dev_cmd.query.descriptor &&
1990 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1991 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1992 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1993 u16 resp_len;
1994 u16 buf_len;
68078d5c
DR		 1995
1996 /* data segment length */
c6d4a831 1997 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1998 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1999 buf_len = be16_to_cpu(
2000 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 2001 if (likely(buf_len >= resp_len)) {
2002 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2003 } else {
2004 dev_warn(hba->dev,
3d4881d1
BH		 2005 "%s: rsp size %d is bigger than buffer size %d",
2006 __func__, resp_len, buf_len);
c6d4a831
DR		 2007 return -EINVAL;
2008 }
68078d5c 2009 }
c6d4a831
DR		 2010
2011 return 0;
68078d5c
DR		 2012}
2013
7a3e97b0
SY		 2014/**
2015 * ufshcd_hba_capabilities - Read controller capabilities
2016 * @hba: per adapter instance
2017 */
2018static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
2019{
b873a275 2020 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 2021
2022 /* nutrs and nutmrs are 0 based values */
2023 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2024 hba->nutmrs =
2025 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2026}
2027
2028/**
6ccf44fe
SJ		 2029 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2030 * to accept UIC commands
7a3e97b0 2031 * @hba: per adapter instance
6ccf44fe
SJ		 2032 * Return true on success, else false
2033 */
2034static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2035{
2036 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2037 return true;
2038 else
2039 return false;
2040}
2041
53b3d9c3
SJ		 2042/**
2043 * ufshcd_get_upmcrs - Get the power mode change request status
2044 * @hba: Pointer to adapter instance
2045 *
2046 * This function gets the UPMCRS field of HCS register
2047 * Returns value of UPMCRS field
2048 */
2049static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2050{
2051 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2052}
2053
6ccf44fe
SJ		 2054/**
2055 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
2056 * @hba: per adapter instance
2057 * @uic_cmd: UIC command
2058 *
2059 * Mutex must be held.
7a3e97b0
SY		 2060 */
2061static inline void
6ccf44fe 2062ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2063{
6ccf44fe
SJ		 2064 WARN_ON(hba->active_uic_cmd);
2065
2066 hba->active_uic_cmd = uic_cmd;
2067
7a3e97b0 2068 /* Write Args */
6ccf44fe
SJ		 2069 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2070 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2071 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 2072
2073 /* Write UIC Cmd */
6ccf44fe 2074 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2075 REG_UIC_COMMAND);
7a3e97b0
SY		 2076}
2077
6ccf44fe
SJ		 2078/**
2079 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2080 * @hba: per adapter instance
8aa29f19 2081 * @uic_cmd: UIC command
6ccf44fe
SJ		 2082 *
2083 * Must be called with mutex held.
2084 * Returns 0 only if success.
2085 */
2086static int
2087ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2088{
2089 int ret;
2090 unsigned long flags;
2091
2092 if (wait_for_completion_timeout(&uic_cmd->done,
2093 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2094 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2095 else
2096 ret = -ETIMEDOUT;
2097
2098 spin_lock_irqsave(hba->host->host_lock, flags);
2099 hba->active_uic_cmd = NULL;
2100 spin_unlock_irqrestore(hba->host->host_lock, flags);
2101
2102 return ret;
2103}
2104
2105/**
2106 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2107 * @hba: per adapter instance
2108 * @uic_cmd: UIC command
d75f7fe4 2109 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2110 *
2111 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2112 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2113 * Returns 0 only if success.
2114 */
2115static int
d75f7fe4
YG		 2116__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2117 bool completion)
6ccf44fe 2118{
6ccf44fe
SJ		 2119 if (!ufshcd_ready_for_uic_cmd(hba)) {
2120 dev_err(hba->dev,
2121 "Controller not ready to accept UIC commands\n");
2122 return -EIO;
2123 }
2124
d75f7fe4
YG		 2125 if (completion)
2126 init_completion(&uic_cmd->done);
6ccf44fe 2127
6ccf44fe 2128 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2129
57d104c1 2130 return 0;
6ccf44fe
SJ		 2131}
2132
2133/**
2134 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2135 * @hba: per adapter instance
2136 * @uic_cmd: UIC command
2137 *
2138 * Returns 0 only if success.
2139 */
e77044c5 2140int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2141{
2142 int ret;
57d104c1 2143 unsigned long flags;
6ccf44fe 2144
1ab27c9c 2145 ufshcd_hold(hba, false);
6ccf44fe 2146 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2147 ufshcd_add_delay_before_dme_cmd(hba);
2148
57d104c1 2149 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2150 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2151 spin_unlock_irqrestore(hba->host->host_lock, flags);
2152 if (!ret)
2153 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2154
6ccf44fe
SJ		 2155 mutex_unlock(&hba->uic_cmd_mutex);
2156
1ab27c9c 2157 ufshcd_release(hba);
6ccf44fe
SJ		 2158 return ret;
2159}
2160
7a3e97b0
SY		 2161/**
2162 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2163 * @hba: per adapter instance
2164 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2165 *
2166 * Returns 0 in case of success, non-zero value in case of failure
2167 */
75b1cc4a 2168static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2169{
2170 struct ufshcd_sg_entry *prd_table;
2171 struct scatterlist *sg;
2172 struct scsi_cmnd *cmd;
2173 int sg_segments;
2174 int i;
2175
2176 cmd = lrbp->cmd;
2177 sg_segments = scsi_dma_map(cmd);
2178 if (sg_segments < 0)
2179 return sg_segments;
2180
2181 if (sg_segments) {
49200199
CH		 2182 lrbp->utr_descriptor_ptr->prd_table_length =
2183 cpu_to_le16((u16)sg_segments);
7a3e97b0
SY		 2184
2185 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2186
2187 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2188 prd_table[i].size =
2189 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2190 prd_table[i].base_addr =
2191 cpu_to_le32(lower_32_bits(sg->dma_address));
2192 prd_table[i].upper_addr =
2193 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2194 prd_table[i].reserved = 0;
7a3e97b0
SY		 2195 }
2196 } else {
2197 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2198 }
2199
2200 return 0;
2201}
2202
2203/**
2fbd009b 2204 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2205 * @hba: per adapter instance
2fbd009b 2206 * @intrs: interrupt bits
7a3e97b0 2207 */
2fbd009b 2208static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2209{
2fbd009b
SJ		 2210 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2211
2212 if (hba->ufs_version == UFSHCI_VERSION_10) {
2213 u32 rw;
2214 rw = set & INTERRUPT_MASK_RW_VER_10;
2215 set = rw | ((set ^ intrs) & intrs);
2216 } else {
2217 set |= intrs;
2218 }
2219
2220 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2221}
2222
2223/**
2224 * ufshcd_disable_intr - disable interrupts
2225 * @hba: per adapter instance
2226 * @intrs: interrupt bits
2227 */
2228static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2229{
2230 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2231
2232 if (hba->ufs_version == UFSHCI_VERSION_10) {
2233 u32 rw;
2234 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2235 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2236 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2237
2238 } else {
2239 set &= ~intrs;
7a3e97b0 2240 }
2fbd009b
SJ		 2241
2242 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2243}
2244
5a0b0cb9
SRT		 2245/**
2246 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2247 * descriptor according to request
2248 * @lrbp: pointer to local reference block
2249 * @upiu_flags: flags required in the header
2250 * @cmd_dir: requests data direction
2251 */
2252static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2253 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2254{
2255 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2256 u32 data_direction;
2257 u32 dword_0;
2258
2259 if (cmd_dir == DMA_FROM_DEVICE) {
2260 data_direction = UTP_DEVICE_TO_HOST;
2261 *upiu_flags = UPIU_CMD_FLAGS_READ;
2262 } else if (cmd_dir == DMA_TO_DEVICE) {
2263 data_direction = UTP_HOST_TO_DEVICE;
2264 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2265 } else {
2266 data_direction = UTP_NO_DATA_TRANSFER;
2267 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2268 }
2269
2270 dword_0 = data_direction | (lrbp->command_type
2271 << UPIU_COMMAND_TYPE_OFFSET);
2272 if (lrbp->intr_cmd)
2273 dword_0 |= UTP_REQ_DESC_INT_CMD;
2274
2275 /* Transfer request descriptor header fields */
2276 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2277 /* dword_1 is reserved, hence it is set to 0 */
2278 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2279 /*
2280 * assigning invalid value for command status. Controller
2281 * updates OCS on command completion, with the command
2282 * status
2283 */
2284 req_desc->header.dword_2 =
2285 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2286 /* dword_3 is reserved, hence it is set to 0 */
2287 req_desc->header.dword_3 = 0;
51047266
YG		 2288
2289 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2290}
2291
2292/**
2293 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2294 * for scsi commands
8aa29f19
BVA		 2295 * @lrbp: local reference block pointer
2296 * @upiu_flags: flags
5a0b0cb9
SRT		 2297 */
2298static
2299void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2300{
1b21b8f0 2301 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2302 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2303 unsigned short cdb_len;
5a0b0cb9
SRT		 2304
2305 /* command descriptor fields */
2306 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2307 UPIU_TRANSACTION_COMMAND, upiu_flags,
2308 lrbp->lun, lrbp->task_tag);
2309 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2310 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2311
2312 /* Total EHS length and Data segment length will be zero */
2313 ucd_req_ptr->header.dword_2 = 0;
2314
1b21b8f0 2315 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2316
1b21b8f0 2317 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2318 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2319 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2320
2321 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2322}
2323
68078d5c
DR		 2324/**
2325 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2326 * for query requsts
2327 * @hba: UFS hba
2328 * @lrbp: local reference block pointer
2329 * @upiu_flags: flags
2330 */
2331static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2332 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2333{
2334 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2335 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2336 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2337
2338 /* Query request header */
2339 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2340 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2341 lrbp->lun, lrbp->task_tag);
2342 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2343 0, query->request.query_func, 0, 0);
2344
6861285c
ZL		 2345 /* Data segment length only need for WRITE_DESC */
2346 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2347 ucd_req_ptr->header.dword_2 =
2348 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2349 else
2350 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2351
2352 /* Copy the Query Request buffer as is */
2353 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2354 QUERY_OSF_SIZE);
68078d5c
DR		 2355
2356 /* Copy the Descriptor */
c6d4a831 2357 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2358 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2359
51047266 2360 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2361}
2362
5a0b0cb9
SRT		 2363static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2364{
2365 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2366
2367 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2368
2369 /* command descriptor fields */
2370 ucd_req_ptr->header.dword_0 =
2371 UPIU_HEADER_DWORD(
2372 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2373 /* clear rest of the fields of basic header */
2374 ucd_req_ptr->header.dword_1 = 0;
2375 ucd_req_ptr->header.dword_2 = 0;
2376
2377 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2378}
2379
7a3e97b0 2380/**
300bb13f
JP		 2381 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2382 * for Device Management Purposes
8aa29f19
BVA		 2383 * @hba: per adapter instance
2384 * @lrbp: pointer to local reference block
7a3e97b0 2385 */
300bb13f 2386static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2387{
7a3e97b0 2388 u32 upiu_flags;
5a0b0cb9 2389 int ret = 0;
7a3e97b0 2390
83dc7e3d 2391 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2392 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2393 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2394 else
2395 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2396
2397 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2398 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2399 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2400 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2401 ufshcd_prepare_utp_nop_upiu(lrbp);
2402 else
2403 ret = -EINVAL;
2404
2405 return ret;
2406}
2407
2408/**
2409 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2410 * for SCSI Purposes
8aa29f19
BVA		 2411 * @hba: per adapter instance
2412 * @lrbp: pointer to local reference block
300bb13f
JP		 2413 */
2414static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2415{
2416 u32 upiu_flags;
2417 int ret = 0;
2418
83dc7e3d 2419 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2420 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2421 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2422 else
2423 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2424
2425 if (likely(lrbp->cmd)) {
2426 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2427 lrbp->cmd->sc_data_direction);
2428 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2429 } else {
2430 ret = -EINVAL;
2431 }
5a0b0cb9
SRT		 2432
2433 return ret;
7a3e97b0
SY		 2434}
2435
2a8fa600
SJ		 2436/**
2437 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2438 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2439 *
2440 * Returns SCSI W-LUN id
2441 */
2442static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2443{
2444 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2445}
2446
4d2b8d40
BVA		 2447static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2448{
2449 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2450 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2451 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2452 i * sizeof(struct utp_transfer_cmd_desc);
2453 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2454 response_upiu);
2455 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2456
2457 lrb->utr_descriptor_ptr = utrdlp + i;
2458 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2459 i * sizeof(struct utp_transfer_req_desc);
2460 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2461 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2462 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2463 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2464 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2465 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2466}
2467
7a3e97b0
SY		 2468/**
2469 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2470 * @host: SCSI host pointer
7a3e97b0 2471 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2472 *
2473 * Returns 0 for success, non-zero in case of failure
2474 */
2475static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2476{
2477 struct ufshcd_lrb *lrbp;
2478 struct ufs_hba *hba;
2479 unsigned long flags;
2480 int tag;
2481 int err = 0;
2482
2483 hba = shost_priv(host);
2484
2485 tag = cmd->request->tag;
14497328
YG		 2486 if (!ufshcd_valid_tag(hba, tag)) {
2487 dev_err(hba->dev,
2488 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2489 __func__, tag, cmd, cmd->request);
2490 BUG();
2491 }
7a3e97b0 2492
a3cd5ec5 2493 if (!down_read_trylock(&hba->clk_scaling_lock))
2494 return SCSI_MLQUEUE_HOST_BUSY;
2495
3441da7d
SRT		 2496 spin_lock_irqsave(hba->host->host_lock, flags);
2497 switch (hba->ufshcd_state) {
2498 case UFSHCD_STATE_OPERATIONAL:
2499 break;
141f8165 2500 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2501 case UFSHCD_STATE_RESET:
7a3e97b0 2502 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2503 goto out_unlock;
2504 case UFSHCD_STATE_ERROR:
2505 set_host_byte(cmd, DID_ERROR);
2506 cmd->scsi_done(cmd);
2507 goto out_unlock;
2508 default:
2509 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2510 __func__, hba->ufshcd_state);
2511 set_host_byte(cmd, DID_BAD_TARGET);
2512 cmd->scsi_done(cmd);
2513 goto out_unlock;
7a3e97b0 2514 }
53c12d0e
YG		 2515
2516 /* if error handling is in progress, don't issue commands */
2517 if (ufshcd_eh_in_progress(hba)) {
2518 set_host_byte(cmd, DID_ERROR);
2519 cmd->scsi_done(cmd);
2520 goto out_unlock;
2521 }
3441da7d 2522 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2523
7fabb77b
GB		 2524 hba->req_abort_count = 0;
2525
1ab27c9c
ST		 2526 err = ufshcd_hold(hba, true);
2527 if (err) {
2528 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2529 goto out;
2530 }
2531 WARN_ON(hba->clk_gating.state != CLKS_ON);
2532
7a3e97b0
SY		 2533 lrbp = &hba->lrb[tag];
2534
5a0b0cb9 2535 WARN_ON(lrbp->cmd);
7a3e97b0 2536 lrbp->cmd = cmd;
09a5a24f 2537 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2538 lrbp->sense_buffer = cmd->sense_buffer;
2539 lrbp->task_tag = tag;
0ce147d4 2540 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2541 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2542 lrbp->req_abort_skip = false;
7a3e97b0 2543
300bb13f
JP		 2544 ufshcd_comp_scsi_upiu(hba, lrbp);
2545
75b1cc4a 2546 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2547 if (err) {
2548 lrbp->cmd = NULL;
17c7d35f 2549 ufshcd_release(hba);
7a3e97b0 2550 goto out;
5a0b0cb9 2551 }
ad1a1b9c
GB		 2552 /* Make sure descriptors are ready before ringing the doorbell */
2553 wmb();
7a3e97b0
SY		 2554
2555 /* issue command to the controller */
2556 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2557 ufshcd_vops_setup_xfer_req(hba, tag, true);
7a3e97b0 2558 ufshcd_send_command(hba, tag);
3441da7d 2559out_unlock:
7a3e97b0
SY		 2560 spin_unlock_irqrestore(hba->host->host_lock, flags);
2561out:
a3cd5ec5 2562 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2563 return err;
2564}
2565
5a0b0cb9
SRT		 2566static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2567 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2568{
2569 lrbp->cmd = NULL;
2570 lrbp->sense_bufflen = 0;
2571 lrbp->sense_buffer = NULL;
2572 lrbp->task_tag = tag;
2573 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2574 lrbp->intr_cmd = true; /* No interrupt aggregation */
2575 hba->dev_cmd.type = cmd_type;
2576
300bb13f 2577 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2578}
2579
2580static int
2581ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2582{
2583 int err = 0;
2584 unsigned long flags;
2585 u32 mask = 1 << tag;
2586
2587 /* clear outstanding transaction before retry */
2588 spin_lock_irqsave(hba->host->host_lock, flags);
2589 ufshcd_utrl_clear(hba, tag);
2590 spin_unlock_irqrestore(hba->host->host_lock, flags);
2591
2592 /*
2593 * wait for for h/w to clear corresponding bit in door-bell.
2594 * max. wait is 1 sec.
2595 */
2596 err = ufshcd_wait_for_register(hba,
2597 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2598 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2599
2600 return err;
2601}
2602
c6d4a831
DR		 2603static int
2604ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2605{
2606 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2607
2608 /* Get the UPIU response */
2609 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2610 UPIU_RSP_CODE_OFFSET;
2611 return query_res->response;
2612}
2613
5a0b0cb9
SRT		 2614/**
2615 * ufshcd_dev_cmd_completion() - handles device management command responses
2616 * @hba: per adapter instance
2617 * @lrbp: pointer to local reference block
2618 */
2619static int
2620ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2621{
2622 int resp;
2623 int err = 0;
2624
ff8e20c6 2625 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2626 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2627
2628 switch (resp) {
2629 case UPIU_TRANSACTION_NOP_IN:
2630 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2631 err = -EINVAL;
2632 dev_err(hba->dev, "%s: unexpected response %x\n",
2633 __func__, resp);
2634 }
2635 break;
68078d5c 2636 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2637 err = ufshcd_check_query_response(hba, lrbp);
2638 if (!err)
2639 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2640 break;
5a0b0cb9
SRT		 2641 case UPIU_TRANSACTION_REJECT_UPIU:
2642 /* TODO: handle Reject UPIU Response */
2643 err = -EPERM;
2644 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2645 __func__);
2646 break;
2647 default:
2648 err = -EINVAL;
2649 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2650 __func__, resp);
2651 break;
2652 }
2653
2654 return err;
2655}
2656
2657static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2658 struct ufshcd_lrb *lrbp, int max_timeout)
2659{
2660 int err = 0;
2661 unsigned long time_left;
2662 unsigned long flags;
2663
2664 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2665 msecs_to_jiffies(max_timeout));
2666
ad1a1b9c
GB		 2667 /* Make sure descriptors are ready before ringing the doorbell */
2668 wmb();
5a0b0cb9
SRT		 2669 spin_lock_irqsave(hba->host->host_lock, flags);
2670 hba->dev_cmd.complete = NULL;
2671 if (likely(time_left)) {
2672 err = ufshcd_get_tr_ocs(lrbp);
2673 if (!err)
2674 err = ufshcd_dev_cmd_completion(hba, lrbp);
2675 }
2676 spin_unlock_irqrestore(hba->host->host_lock, flags);
2677
2678 if (!time_left) {
2679 err = -ETIMEDOUT;
a48353f6
YG		 2680 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2681 __func__, lrbp->task_tag);
5a0b0cb9 2682 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2683 /* successfully cleared the command, retry if needed */
5a0b0cb9 2684 err = -EAGAIN;
a48353f6
YG		 2685 /*
2686 * in case of an error, after clearing the doorbell,
2687 * we also need to clear the outstanding_request
2688 * field in hba
2689 */
2690 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2691 }
2692
2693 return err;
2694}
2695
5a0b0cb9
SRT		 2696/**
2697 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2698 * @hba: UFS hba
2699 * @cmd_type: specifies the type (NOP, Query...)
2700 * @timeout: time in seconds
5a0b0cb9 2701 *
68078d5c
DR		 2702 * NOTE: Since there is only one available tag for device management commands,
2703 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2704 */
2705static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2706 enum dev_cmd_type cmd_type, int timeout)
2707{
7252a360
BVA		 2708 struct request_queue *q = hba->cmd_queue;
2709 struct request *req;
5a0b0cb9
SRT		 2710 struct ufshcd_lrb *lrbp;
2711 int err;
2712 int tag;
2713 struct completion wait;
2714 unsigned long flags;
2715
a3cd5ec5 2716 down_read(&hba->clk_scaling_lock);
2717
5a0b0cb9
SRT		 2718 /*
2719 * Get free slot, sleep if slots are unavailable.
2720 * Even though we use wait_event() which sleeps indefinitely,
2721 * the maximum wait time is bounded by SCSI request timeout.
2722 */
7252a360 2723 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 2724 if (IS_ERR(req)) {
2725 err = PTR_ERR(req);
2726 goto out_unlock;
2727 }
7252a360
BVA		 2728 tag = req->tag;
2729 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5a0b0cb9
SRT		 2730
2731 init_completion(&wait);
2732 lrbp = &hba->lrb[tag];
2733 WARN_ON(lrbp->cmd);
2734 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2735 if (unlikely(err))
2736 goto out_put_tag;
2737
2738 hba->dev_cmd.complete = &wait;
2739
6667e6d9 2740 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2741 /* Make sure descriptors are ready before ringing the doorbell */
2742 wmb();
5a0b0cb9 2743 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2744 ufshcd_vops_setup_xfer_req(hba, tag, false);
5a0b0cb9
SRT		 2745 ufshcd_send_command(hba, tag);
2746 spin_unlock_irqrestore(hba->host->host_lock, flags);
2747
2748 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2749
6667e6d9
OS		 2750 ufshcd_add_query_upiu_trace(hba, tag,
2751 err ? "query_complete_err" : "query_complete");
2752
5a0b0cb9 2753out_put_tag:
7252a360 2754 blk_put_request(req);
bb14dd15 2755out_unlock:
a3cd5ec5 2756 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2757 return err;
2758}
2759
d44a5f98
DR		 2760/**
2761 * ufshcd_init_query() - init the query response and request parameters
2762 * @hba: per-adapter instance
2763 * @request: address of the request pointer to be initialized
2764 * @response: address of the response pointer to be initialized
2765 * @opcode: operation to perform
2766 * @idn: flag idn to access
2767 * @index: LU number to access
2768 * @selector: query/flag/descriptor further identification
2769 */
2770static inline void ufshcd_init_query(struct ufs_hba *hba,
2771 struct ufs_query_req **request, struct ufs_query_res **response,
2772 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2773{
2774 *request = &hba->dev_cmd.query.request;
2775 *response = &hba->dev_cmd.query.response;
2776 memset(*request, 0, sizeof(struct ufs_query_req));
2777 memset(*response, 0, sizeof(struct ufs_query_res));
2778 (*request)->upiu_req.opcode = opcode;
2779 (*request)->upiu_req.idn = idn;
2780 (*request)->upiu_req.index = index;
2781 (*request)->upiu_req.selector = selector;
2782}
2783
dc3c8d3a
YG		 2784static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2785 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2786{
2787 int ret;
2788 int retries;
2789
2790 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2791 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2792 if (ret)
2793 dev_dbg(hba->dev,
2794 "%s: failed with error %d, retries %d\n",
2795 __func__, ret, retries);
2796 else
2797 break;
2798 }
2799
2800 if (ret)
2801 dev_err(hba->dev,
2802 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2803 __func__, opcode, idn, ret, retries);
2804 return ret;
2805}
2806
68078d5c
DR		 2807/**
2808 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2809 * @hba: per-adapter instance
2810 * @opcode: flag query to perform
2811 * @idn: flag idn to access
2812 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2813 *
2814 * Returns 0 for success, non-zero in case of failure
2815 */
dc3c8d3a 2816int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2817 enum flag_idn idn, bool *flag_res)
2818{
d44a5f98
DR		 2819 struct ufs_query_req *request = NULL;
2820 struct ufs_query_res *response = NULL;
2821 int err, index = 0, selector = 0;
e5ad406c 2822 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2823
2824 BUG_ON(!hba);
2825
1ab27c9c 2826 ufshcd_hold(hba, false);
68078d5c 2827 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2828 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2829 selector);
68078d5c
DR		 2830
2831 switch (opcode) {
2832 case UPIU_QUERY_OPCODE_SET_FLAG:
2833 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2834 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2835 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2836 break;
2837 case UPIU_QUERY_OPCODE_READ_FLAG:
2838 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2839 if (!flag_res) {
2840 /* No dummy reads */
2841 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2842 __func__);
2843 err = -EINVAL;
2844 goto out_unlock;
2845 }
2846 break;
2847 default:
2848 dev_err(hba->dev,
2849 "%s: Expected query flag opcode but got = %d\n",
2850 __func__, opcode);
2851 err = -EINVAL;
2852 goto out_unlock;
2853 }
68078d5c 2854
e5ad406c 2855 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2856
2857 if (err) {
2858 dev_err(hba->dev,
2859 "%s: Sending flag query for idn %d failed, err = %d\n",
2860 __func__, idn, err);
2861 goto out_unlock;
2862 }
2863
2864 if (flag_res)
e8c8e82a 2865 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2866 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2867
2868out_unlock:
2869 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2870 ufshcd_release(hba);
68078d5c
DR		 2871 return err;
2872}
2873
66ec6d59
SRT		 2874/**
2875 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2876 * @hba: per-adapter instance
2877 * @opcode: attribute opcode
2878 * @idn: attribute idn to access
2879 * @index: index field
2880 * @selector: selector field
2881 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2882 *
2883 * Returns 0 for success, non-zero in case of failure
2884*/
ec92b59c
SN		 2885int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2886 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2887{
d44a5f98
DR		 2888 struct ufs_query_req *request = NULL;
2889 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2890 int err;
2891
2892 BUG_ON(!hba);
2893
1ab27c9c 2894 ufshcd_hold(hba, false);
66ec6d59
SRT		 2895 if (!attr_val) {
2896 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2897 __func__, opcode);
2898 err = -EINVAL;
2899 goto out;
2900 }
2901
2902 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2903 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2904 selector);
66ec6d59
SRT		 2905
2906 switch (opcode) {
2907 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2908 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2909 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2910 break;
2911 case UPIU_QUERY_OPCODE_READ_ATTR:
2912 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2913 break;
2914 default:
2915 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2916 __func__, opcode);
2917 err = -EINVAL;
2918 goto out_unlock;
2919 }
2920
d44a5f98 2921 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2922
2923 if (err) {
4b761b58
YG		 2924 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2925 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2926 goto out_unlock;
2927 }
2928
e8c8e82a 2929 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2930
2931out_unlock:
2932 mutex_unlock(&hba->dev_cmd.lock);
2933out:
1ab27c9c 2934 ufshcd_release(hba);
66ec6d59
SRT		 2935 return err;
2936}
2937
5e86ae44
YG		 2938/**
2939 * ufshcd_query_attr_retry() - API function for sending query
2940 * attribute with retries
2941 * @hba: per-adapter instance
2942 * @opcode: attribute opcode
2943 * @idn: attribute idn to access
2944 * @index: index field
2945 * @selector: selector field
2946 * @attr_val: the attribute value after the query request
2947 * completes
2948 *
2949 * Returns 0 for success, non-zero in case of failure
2950*/
2951static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2952 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2953 u32 *attr_val)
2954{
2955 int ret = 0;
2956 u32 retries;
2957
68c9fcfd 2958 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 2959 ret = ufshcd_query_attr(hba, opcode, idn, index,
2960 selector, attr_val);
2961 if (ret)
2962 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2963 __func__, ret, retries);
2964 else
2965 break;
2966 }
2967
2968 if (ret)
2969 dev_err(hba->dev,
2970 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2971 __func__, idn, ret, QUERY_REQ_RETRIES);
2972 return ret;
2973}
2974
a70e91b8 2975static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2976 enum query_opcode opcode, enum desc_idn idn, u8 index,
2977 u8 selector, u8 *desc_buf, int *buf_len)
2978{
2979 struct ufs_query_req *request = NULL;
2980 struct ufs_query_res *response = NULL;
2981 int err;
2982
2983 BUG_ON(!hba);
2984
1ab27c9c 2985 ufshcd_hold(hba, false);
d44a5f98
DR		 2986 if (!desc_buf) {
2987 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2988 __func__, opcode);
2989 err = -EINVAL;
2990 goto out;
2991 }
2992
a4b0e8a4 2993 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2994 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2995 __func__, *buf_len);
2996 err = -EINVAL;
2997 goto out;
2998 }
2999
3000 mutex_lock(&hba->dev_cmd.lock);
3001 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3002 selector);
3003 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3004 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3005
3006 switch (opcode) {
3007 case UPIU_QUERY_OPCODE_WRITE_DESC:
3008 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3009 break;
3010 case UPIU_QUERY_OPCODE_READ_DESC:
3011 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3012 break;
3013 default:
3014 dev_err(hba->dev,
3015 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3016 __func__, opcode);
3017 err = -EINVAL;
3018 goto out_unlock;
3019 }
3020
3021 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3022
3023 if (err) {
4b761b58
YG		 3024 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3025 __func__, opcode, idn, index, err);
d44a5f98
DR		 3026 goto out_unlock;
3027 }
3028
ea2aab24 3029 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3030
3031out_unlock:
cfcbae38 3032 hba->dev_cmd.query.descriptor = NULL;
d44a5f98
DR		 3033 mutex_unlock(&hba->dev_cmd.lock);
3034out:
1ab27c9c 3035 ufshcd_release(hba);
d44a5f98
DR		 3036 return err;
3037}
3038
a70e91b8 3039/**
8aa29f19
BVA		 3040 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3041 * @hba: per-adapter instance
3042 * @opcode: attribute opcode
3043 * @idn: attribute idn to access
3044 * @index: index field
3045 * @selector: selector field
3046 * @desc_buf: the buffer that contains the descriptor
3047 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3048 *
3049 * Returns 0 for success, non-zero in case of failure.
3050 * The buf_len parameter will contain, on return, the length parameter
3051 * received on the response.
3052 */
2238d31c
SN		 3053int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3054 enum query_opcode opcode,
3055 enum desc_idn idn, u8 index,
3056 u8 selector,
3057 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3058{
3059 int err;
3060 int retries;
3061
3062 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3063 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3064 selector, desc_buf, buf_len);
3065 if (!err || err == -EINVAL)
3066 break;
3067 }
3068
3069 return err;
3070}
a70e91b8 3071
a4b0e8a4
PM		 3072/**
3073 * ufshcd_read_desc_length - read the specified descriptor length from header
3074 * @hba: Pointer to adapter instance
3075 * @desc_id: descriptor idn value
3076 * @desc_index: descriptor index
3077 * @desc_length: pointer to variable to read the length of descriptor
3078 *
3079 * Return 0 in case of success, non-zero otherwise
3080 */
3081static int ufshcd_read_desc_length(struct ufs_hba *hba,
3082 enum desc_idn desc_id,
3083 int desc_index,
3084 int *desc_length)
3085{
3086 int ret;
3087 u8 header[QUERY_DESC_HDR_SIZE];
3088 int header_len = QUERY_DESC_HDR_SIZE;
3089
3090 if (desc_id >= QUERY_DESC_IDN_MAX)
3091 return -EINVAL;
3092
3093 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3094 desc_id, desc_index, 0, header,
3095 &header_len);
3096
3097 if (ret) {
3098 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3099 __func__, desc_id);
3100 return ret;
3101 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3102 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3103 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3104 desc_id);
3105 ret = -EINVAL;
3106 }
3107
3108 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3109 return ret;
3110
3111}
3112
3113/**
3114 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3115 * @hba: Pointer to adapter instance
3116 * @desc_id: descriptor idn value
3117 * @desc_len: mapped desc length (out)
3118 *
3119 * Return 0 in case of success, non-zero otherwise
3120 */
3121int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3122 enum desc_idn desc_id, int *desc_len)
3123{
3124 switch (desc_id) {
3125 case QUERY_DESC_IDN_DEVICE:
3126 *desc_len = hba->desc_size.dev_desc;
3127 break;
3128 case QUERY_DESC_IDN_POWER:
3129 *desc_len = hba->desc_size.pwr_desc;
3130 break;
3131 case QUERY_DESC_IDN_GEOMETRY:
3132 *desc_len = hba->desc_size.geom_desc;
3133 break;
3134 case QUERY_DESC_IDN_CONFIGURATION:
3135 *desc_len = hba->desc_size.conf_desc;
3136 break;
3137 case QUERY_DESC_IDN_UNIT:
3138 *desc_len = hba->desc_size.unit_desc;
3139 break;
3140 case QUERY_DESC_IDN_INTERCONNECT:
3141 *desc_len = hba->desc_size.interc_desc;
3142 break;
3143 case QUERY_DESC_IDN_STRING:
3144 *desc_len = QUERY_DESC_MAX_SIZE;
3145 break;
c648c2d2
SN		 3146 case QUERY_DESC_IDN_HEALTH:
3147 *desc_len = hba->desc_size.hlth_desc;
3148 break;
a4b0e8a4
PM		 3149 case QUERY_DESC_IDN_RFU_0:
3150 case QUERY_DESC_IDN_RFU_1:
3151 *desc_len = 0;
3152 break;
3153 default:
3154 *desc_len = 0;
3155 return -EINVAL;
3156 }
3157 return 0;
3158}
3159EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3160
da461cec
SJ		 3161/**
3162 * ufshcd_read_desc_param - read the specified descriptor parameter
3163 * @hba: Pointer to adapter instance
3164 * @desc_id: descriptor idn value
3165 * @desc_index: descriptor index
3166 * @param_offset: offset of the parameter to read
3167 * @param_read_buf: pointer to buffer where parameter would be read
3168 * @param_size: sizeof(param_read_buf)
3169 *
3170 * Return 0 in case of success, non-zero otherwise
3171 */
45bced87
SN		 3172int ufshcd_read_desc_param(struct ufs_hba *hba,
3173 enum desc_idn desc_id,
3174 int desc_index,
3175 u8 param_offset,
3176 u8 *param_read_buf,
3177 u8 param_size)
da461cec
SJ		 3178{
3179 int ret;
3180 u8 *desc_buf;
a4b0e8a4 3181 int buff_len;
da461cec
SJ		 3182 bool is_kmalloc = true;
3183
a4b0e8a4
PM		 3184 /* Safety check */
3185 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3186 return -EINVAL;
3187
a4b0e8a4
PM		 3188 /* Get the max length of descriptor from structure filled up at probe
3189 * time.
3190 */
3191 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3192
a4b0e8a4
PM		 3193 /* Sanity checks */
3194 if (ret || !buff_len) {
3195 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3196 __func__);
3197 return ret;
3198 }
3199
3200 /* Check whether we need temp memory */
3201 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3202 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3203 if (!desc_buf)
3204 return -ENOMEM;
a4b0e8a4
PM		 3205 } else {
3206 desc_buf = param_read_buf;
3207 is_kmalloc = false;
da461cec
SJ		 3208 }
3209
a4b0e8a4 3210 /* Request for full descriptor */
a70e91b8 3211 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3212 desc_id, desc_index, 0,
3213 desc_buf, &buff_len);
da461cec 3214
bde44bb6 3215 if (ret) {
3216 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3217 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3218 goto out;
3219 }
3220
bde44bb6 3221 /* Sanity check */
3222 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3223 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3224 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3225 ret = -EINVAL;
3226 goto out;
3227 }
3228
a4b0e8a4
PM		 3229 /* Check wherher we will not copy more data, than available */
3230 if (is_kmalloc && param_size > buff_len)
3231 param_size = buff_len;
bde44bb6 3232
da461cec
SJ		 3233 if (is_kmalloc)
3234 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3235out:
3236 if (is_kmalloc)
3237 kfree(desc_buf);
3238 return ret;
3239}
3240
3241static inline int ufshcd_read_desc(struct ufs_hba *hba,
3242 enum desc_idn desc_id,
3243 int desc_index,
4b828fe1 3244 void *buf,
da461cec
SJ		 3245 u32 size)
3246{
3247 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3248}
3249
b573d484 3250
4b828fe1
TW		 3251/**
3252 * struct uc_string_id - unicode string
3253 *
3254 * @len: size of this descriptor inclusive
3255 * @type: descriptor type
3256 * @uc: unicode string character
3257 */
3258struct uc_string_id {
3259 u8 len;
3260 u8 type;
3261 wchar_t uc[0];
3262} __packed;
3263
3264/* replace non-printable or non-ASCII characters with spaces */
3265static inline char ufshcd_remove_non_printable(u8 ch)
3266{
3267 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3268}
3269
b573d484
YG		 3270/**
3271 * ufshcd_read_string_desc - read string descriptor
3272 * @hba: pointer to adapter instance
3273 * @desc_index: descriptor index
4b828fe1
TW		 3274 * @buf: pointer to buffer where descriptor would be read,
3275 * the caller should free the memory.
b573d484 3276 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3277 * null terminated string.
b573d484 3278 *
4b828fe1
TW		 3279 * Return:
3280 * * string size on success.
3281 * * -ENOMEM: on allocation failure
3282 * * -EINVAL: on a wrong parameter
b573d484 3283 */
4b828fe1
TW		 3284int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3285 u8 **buf, bool ascii)
b573d484 3286{
4b828fe1
TW		 3287 struct uc_string_id *uc_str;
3288 u8 *str;
3289 int ret;
b573d484 3290
4b828fe1
TW		 3291 if (!buf)
3292 return -EINVAL;
b573d484 3293
4b828fe1
TW		 3294 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3295 if (!uc_str)
3296 return -ENOMEM;
b573d484 3297
4b828fe1
TW		 3298 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING,
3299 desc_index, uc_str,
3300 QUERY_DESC_MAX_SIZE);
3301 if (ret < 0) {
3302 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3303 QUERY_REQ_RETRIES, ret);
3304 str = NULL;
3305 goto out;
3306 }
3307
3308 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3309 dev_dbg(hba->dev, "String Desc is of zero length\n");
3310 str = NULL;
3311 ret = 0;
b573d484
YG		 3312 goto out;
3313 }
3314
3315 if (ascii) {
4b828fe1 3316 ssize_t ascii_len;
b573d484 3317 int i;
b573d484 3318 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3319 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3320 str = kzalloc(ascii_len, GFP_KERNEL);
3321 if (!str) {
3322 ret = -ENOMEM;
fcbefc3b 3323 goto out;
b573d484
YG		 3324 }
3325
3326 /*
3327 * the descriptor contains string in UTF16 format
3328 * we need to convert to utf-8 so it can be displayed
3329 */
4b828fe1
TW		 3330 ret = utf16s_to_utf8s(uc_str->uc,
3331 uc_str->len - QUERY_DESC_HDR_SIZE,
3332 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3333
3334 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3335 for (i = 0; i < ret; i++)
3336 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3337
4b828fe1
TW		 3338 str[ret++] = '\0';
3339
3340 } else {
5f57704d 3341 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3342 if (!str) {
3343 ret = -ENOMEM;
3344 goto out;
3345 }
4b828fe1 3346 ret = uc_str->len;
b573d484
YG		 3347 }
3348out:
4b828fe1
TW		 3349 *buf = str;
3350 kfree(uc_str);
3351 return ret;
b573d484 3352}
b573d484 3353
da461cec
SJ		 3354/**
3355 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3356 * @hba: Pointer to adapter instance
3357 * @lun: lun id
3358 * @param_offset: offset of the parameter to read
3359 * @param_read_buf: pointer to buffer where parameter would be read
3360 * @param_size: sizeof(param_read_buf)
3361 *
3362 * Return 0 in case of success, non-zero otherwise
3363 */
3364static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3365 int lun,
3366 enum unit_desc_param param_offset,
3367 u8 *param_read_buf,
3368 u32 param_size)
3369{
3370 /*
3371 * Unit descriptors are only available for general purpose LUs (LUN id
3372 * from 0 to 7) and RPMB Well known LU.
3373 */
1baa8011 3374 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
da461cec
SJ		 3375 return -EOPNOTSUPP;
3376
3377 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3378 param_offset, param_read_buf, param_size);
3379}
3380
09f17791
CG		 3381static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3382{
3383 int err = 0;
3384 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3385
3386 if (hba->dev_info.wspecversion >= 0x300) {
3387 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3388 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3389 &gating_wait);
3390 if (err)
3391 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3392 err, gating_wait);
3393
3394 if (gating_wait == 0) {
3395 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3396 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3397 gating_wait);
3398 }
3399
3400 hba->dev_info.clk_gating_wait_us = gating_wait;
3401 }
3402
3403 return err;
3404}
3405
7a3e97b0
SY		 3406/**
3407 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3408 * @hba: per adapter instance
3409 *
3410 * 1. Allocate DMA memory for Command Descriptor array
3411 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3412 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3413 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3414 * (UTMRDL)
3415 * 4. Allocate memory for local reference block(lrb).
3416 *
3417 * Returns 0 for success, non-zero in case of failure
3418 */
3419static int ufshcd_memory_alloc(struct ufs_hba *hba)
3420{
3421 size_t utmrdl_size, utrdl_size, ucdl_size;
3422
3423 /* Allocate memory for UTP command descriptors */
3424 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3425 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3426 ucdl_size,
3427 &hba->ucdl_dma_addr,
3428 GFP_KERNEL);
7a3e97b0
SY		 3429
3430 /*
3431 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3432 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3433 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3434 * be aligned to 128 bytes as well
3435 */
3436 if (!hba->ucdl_base_addr ||
3437 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3438 dev_err(hba->dev,
7a3e97b0
SY		 3439 "Command Descriptor Memory allocation failed\n");
3440 goto out;
3441 }
3442
3443 /*
3444 * Allocate memory for UTP Transfer descriptors
3445 * UFSHCI requires 1024 byte alignment of UTRD
3446 */
3447 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3448 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3449 utrdl_size,
3450 &hba->utrdl_dma_addr,
3451 GFP_KERNEL);
7a3e97b0
SY		 3452 if (!hba->utrdl_base_addr ||
3453 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3454 dev_err(hba->dev,
7a3e97b0
SY		 3455 "Transfer Descriptor Memory allocation failed\n");
3456 goto out;
3457 }
3458
3459 /*
3460 * Allocate memory for UTP Task Management descriptors
3461 * UFSHCI requires 1024 byte alignment of UTMRD
3462 */
3463 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3464 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3465 utmrdl_size,
3466 &hba->utmrdl_dma_addr,
3467 GFP_KERNEL);
7a3e97b0
SY		 3468 if (!hba->utmrdl_base_addr ||
3469 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3470 dev_err(hba->dev,
7a3e97b0
SY		 3471 "Task Management Descriptor Memory allocation failed\n");
3472 goto out;
3473 }
3474
3475 /* Allocate memory for local reference block */
a86854d0
KC		 3476 hba->lrb = devm_kcalloc(hba->dev,
3477 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3478 GFP_KERNEL);
7a3e97b0 3479 if (!hba->lrb) {
3b1d0580 3480 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3481 goto out;
3482 }
3483 return 0;
3484out:
7a3e97b0
SY		 3485 return -ENOMEM;
3486}
3487
3488/**
3489 * ufshcd_host_memory_configure - configure local reference block with
3490 * memory offsets
3491 * @hba: per adapter instance
3492 *
3493 * Configure Host memory space
3494 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3495 * address.
3496 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3497 * and PRDT offset.
3498 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3499 * into local reference block.
3500 */
3501static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3502{
7a3e97b0
SY		 3503 struct utp_transfer_req_desc *utrdlp;
3504 dma_addr_t cmd_desc_dma_addr;
3505 dma_addr_t cmd_desc_element_addr;
3506 u16 response_offset;
3507 u16 prdt_offset;
3508 int cmd_desc_size;
3509 int i;
3510
3511 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3512
3513 response_offset =
3514 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3515 prdt_offset =
3516 offsetof(struct utp_transfer_cmd_desc, prd_table);
3517
3518 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3519 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3520
3521 for (i = 0; i < hba->nutrs; i++) {
3522 /* Configure UTRD with command descriptor base address */
3523 cmd_desc_element_addr =
3524 (cmd_desc_dma_addr + (cmd_desc_size * i));
3525 utrdlp[i].command_desc_base_addr_lo =
3526 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3527 utrdlp[i].command_desc_base_addr_hi =
3528 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3529
3530 /* Response upiu and prdt offset should be in double words */
49200199
CH		 3531 utrdlp[i].response_upiu_offset =
3532 cpu_to_le16(response_offset >> 2);
3533 utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
3534 utrdlp[i].response_upiu_length =
3535 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0 3536
4d2b8d40 3537 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3538 }
3539}
3540
3541/**
3542 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3543 * @hba: per adapter instance
3544 *
3545 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3546 * in order to initialize the Unipro link startup procedure.
3547 * Once the Unipro links are up, the device connected to the controller
3548 * is detected.
3549 *
3550 * Returns 0 on success, non-zero value on failure
3551 */
3552static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3553{
6ccf44fe
SJ		 3554 struct uic_command uic_cmd = {0};
3555 int ret;
7a3e97b0 3556
6ccf44fe 3557 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3558
6ccf44fe
SJ		 3559 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3560 if (ret)
ff8e20c6 3561 dev_dbg(hba->dev,
6ccf44fe
SJ		 3562 "dme-link-startup: error code %d\n", ret);
3563 return ret;
7a3e97b0
SY		 3564}
3565
cad2e03d
YG		 3566static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3567{
3568 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3569 unsigned long min_sleep_time_us;
3570
3571 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3572 return;
3573
3574 /*
3575 * last_dme_cmd_tstamp will be 0 only for 1st call to
3576 * this function
3577 */
3578 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3579 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3580 } else {
3581 unsigned long delta =
3582 (unsigned long) ktime_to_us(
3583 ktime_sub(ktime_get(),
3584 hba->last_dme_cmd_tstamp));
3585
3586 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3587 min_sleep_time_us =
3588 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3589 else
3590 return; /* no more delay required */
3591 }
3592
3593 /* allow sleep for extra 50us if needed */
3594 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3595}
3596
12b4fdb4
SJ		 3597/**
3598 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3599 * @hba: per adapter instance
3600 * @attr_sel: uic command argument1
3601 * @attr_set: attribute set type as uic command argument2
3602 * @mib_val: setting value as uic command argument3
3603 * @peer: indicate whether peer or local
3604 *
3605 * Returns 0 on success, non-zero value on failure
3606 */
3607int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3608 u8 attr_set, u32 mib_val, u8 peer)
3609{
3610 struct uic_command uic_cmd = {0};
3611 static const char *const action[] = {
3612 "dme-set",
3613 "dme-peer-set"
3614 };
3615 const char *set = action[!!peer];
3616 int ret;
64238fbd 3617 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3618
3619 uic_cmd.command = peer ?
3620 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3621 uic_cmd.argument1 = attr_sel;
3622 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3623 uic_cmd.argument3 = mib_val;
3624
64238fbd
YG		 3625 do {
3626 /* for peer attributes we retry upon failure */
3627 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3628 if (ret)
3629 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3630 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3631 } while (ret && peer && --retries);
3632
f37e9f8c 3633 if (ret)
64238fbd 3634 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3635 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3636 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3637
3638 return ret;
3639}
3640EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3641
3642/**
3643 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3644 * @hba: per adapter instance
3645 * @attr_sel: uic command argument1
3646 * @mib_val: the value of the attribute as returned by the UIC command
3647 * @peer: indicate whether peer or local
3648 *
3649 * Returns 0 on success, non-zero value on failure
3650 */
3651int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3652 u32 *mib_val, u8 peer)
3653{
3654 struct uic_command uic_cmd = {0};
3655 static const char *const action[] = {
3656 "dme-get",
3657 "dme-peer-get"
3658 };
3659 const char *get = action[!!peer];
3660 int ret;
64238fbd 3661 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3662 struct ufs_pa_layer_attr orig_pwr_info;
3663 struct ufs_pa_layer_attr temp_pwr_info;
3664 bool pwr_mode_change = false;
3665
3666 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3667 orig_pwr_info = hba->pwr_info;
3668 temp_pwr_info = orig_pwr_info;
3669
3670 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3671 orig_pwr_info.pwr_rx == FAST_MODE) {
3672 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3673 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3674 pwr_mode_change = true;
3675 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3676 orig_pwr_info.pwr_rx == SLOW_MODE) {
3677 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3678 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3679 pwr_mode_change = true;
3680 }
3681 if (pwr_mode_change) {
3682 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3683 if (ret)
3684 goto out;
3685 }
3686 }
12b4fdb4
SJ		 3687
3688 uic_cmd.command = peer ?
3689 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3690 uic_cmd.argument1 = attr_sel;
3691
64238fbd
YG		 3692 do {
3693 /* for peer attributes we retry upon failure */
3694 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3695 if (ret)
3696 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3697 get, UIC_GET_ATTR_ID(attr_sel), ret);
3698 } while (ret && peer && --retries);
3699
f37e9f8c 3700 if (ret)
64238fbd 3701 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3702 get, UIC_GET_ATTR_ID(attr_sel),
3703 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3704
64238fbd 3705 if (mib_val && !ret)
12b4fdb4 3706 *mib_val = uic_cmd.argument3;
874237f7
YG		 3707
3708 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3709 && pwr_mode_change)
3710 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3711out:
3712 return ret;
3713}
3714EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3715
53b3d9c3 3716/**
57d104c1
SJ		 3717 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3718 * state) and waits for it to take effect.
3719 *
53b3d9c3 3720 * @hba: per adapter instance
57d104c1
SJ		 3721 * @cmd: UIC command to execute
3722 *
3723 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3724 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3725 * and device UniPro link and hence it's final completion would be indicated by
3726 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3727 * addition to normal UIC command completion Status (UCCS). This function only
3728 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3729 *
3730 * Returns 0 on success, non-zero value on failure
3731 */
57d104c1 3732static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3733{
57d104c1 3734 struct completion uic_async_done;
53b3d9c3
SJ		 3735 unsigned long flags;
3736 u8 status;
3737 int ret;
d75f7fe4 3738 bool reenable_intr = false;
53b3d9c3 3739
53b3d9c3 3740 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3741 init_completion(&uic_async_done);
cad2e03d 3742 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3743
3744 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3745 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3746 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3747 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3748 /*
3749 * Make sure UIC command completion interrupt is disabled before
3750 * issuing UIC command.
3751 */
3752 wmb();
3753 reenable_intr = true;
57d104c1 3754 }
d75f7fe4
YG		 3755 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3756 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3757 if (ret) {
3758 dev_err(hba->dev,
3759 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3760 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3761 goto out;
3762 }
3763
57d104c1 3764 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3765 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3766 dev_err(hba->dev,
57d104c1
SJ		 3767 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3768 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3769 ret = -ETIMEDOUT;
3770 goto out;
3771 }
3772
3773 status = ufshcd_get_upmcrs(hba);
3774 if (status != PWR_LOCAL) {
3775 dev_err(hba->dev,
479da360 3776 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3777 cmd->command, status);
53b3d9c3
SJ		 3778 ret = (status != PWR_OK) ? status : -1;
3779 }
3780out:
7942f7b5
VG		 3781 if (ret) {
3782 ufshcd_print_host_state(hba);
3783 ufshcd_print_pwr_info(hba);
3784 ufshcd_print_host_regs(hba);
3785 }
3786
53b3d9c3 3787 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3788 hba->active_uic_cmd = NULL;
57d104c1 3789 hba->uic_async_done = NULL;
d75f7fe4
YG		 3790 if (reenable_intr)
3791 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3792 spin_unlock_irqrestore(hba->host->host_lock, flags);
3793 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3794
53b3d9c3
SJ		 3795 return ret;
3796}
3797
57d104c1
SJ		 3798/**
3799 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3800 * using DME_SET primitives.
3801 * @hba: per adapter instance
3802 * @mode: powr mode value
3803 *
3804 * Returns 0 on success, non-zero value on failure
3805 */
3806static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3807{
3808 struct uic_command uic_cmd = {0};
1ab27c9c 3809 int ret;
57d104c1 3810
c3a2f9ee
YG		 3811 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3812 ret = ufshcd_dme_set(hba,
3813 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3814 if (ret) {
3815 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3816 __func__, ret);
3817 goto out;
3818 }
3819 }
3820
57d104c1
SJ		 3821 uic_cmd.command = UIC_CMD_DME_SET;
3822 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3823 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3824 ufshcd_hold(hba, false);
3825 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3826 ufshcd_release(hba);
57d104c1 3827
c3a2f9ee 3828out:
1ab27c9c 3829 return ret;
57d104c1
SJ		 3830}
3831
087c5efa 3832int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 3833{
3834 int ret;
3835 unsigned long flags;
3836
3837 spin_lock_irqsave(hba->host->host_lock, flags);
3838 hba->ufshcd_state = UFSHCD_STATE_RESET;
3839 ufshcd_set_eh_in_progress(hba);
3840 spin_unlock_irqrestore(hba->host->host_lock, flags);
3841
ebdd1dfd
CG		 3842 /* Reset the attached device */
3843 ufshcd_vops_device_reset(hba);
3844
53c12d0e
YG		 3845 ret = ufshcd_host_reset_and_restore(hba);
3846
3847 spin_lock_irqsave(hba->host->host_lock, flags);
3848 if (ret)
3849 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3850 ufshcd_clear_eh_in_progress(hba);
3851 spin_unlock_irqrestore(hba->host->host_lock, flags);
3852
3853 if (ret)
3854 dev_err(hba->dev, "%s: link recovery failed, err %d",
3855 __func__, ret);
3856
3857 return ret;
3858}
087c5efa 3859EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 3860
87d0b4a6 3861static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3862{
87d0b4a6 3863 int ret;
57d104c1 3864 struct uic_command uic_cmd = {0};
911a0771 3865 ktime_t start = ktime_get();
57d104c1 3866
ee32c909
KK		 3867 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3868
57d104c1 3869 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3870 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3871 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3872 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3873
53c12d0e 3874 if (ret) {
6d303e4b
SJ		 3875 int err;
3876
87d0b4a6
YG		 3877 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3878 __func__, ret);
3879
53c12d0e 3880 /*
6d303e4b
SJ		 3881 * If link recovery fails then return error code returned from
3882 * ufshcd_link_recovery().
3883 * If link recovery succeeds then return -EAGAIN to attempt
3884 * hibern8 enter retry again.
53c12d0e 3885 */
6d303e4b
SJ		 3886 err = ufshcd_link_recovery(hba);
3887 if (err) {
3888 dev_err(hba->dev, "%s: link recovery failed", __func__);
3889 ret = err;
3890 } else {
3891 ret = -EAGAIN;
3892 }
ee32c909
KK		 3893 } else
3894 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3895 POST_CHANGE);
53c12d0e 3896
87d0b4a6
YG		 3897 return ret;
3898}
3899
3900static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3901{
3902 int ret = 0, retries;
57d104c1 3903
87d0b4a6
YG		 3904 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3905 ret = __ufshcd_uic_hibern8_enter(hba);
6d303e4b 3906 if (!ret)
87d0b4a6
YG		 3907 goto out;
3908 }
3909out:
3910 return ret;
57d104c1
SJ		 3911}
3912
9d19bf7a 3913int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 3914{
3915 struct uic_command uic_cmd = {0};
3916 int ret;
911a0771 3917 ktime_t start = ktime_get();
57d104c1 3918
ee32c909
KK		 3919 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3920
57d104c1
SJ		 3921 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3922 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 3923 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3924 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3925
57d104c1 3926 if (ret) {
53c12d0e
YG		 3927 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3928 __func__, ret);
3929 ret = ufshcd_link_recovery(hba);
ff8e20c6 3930 } else {
ee32c909
KK		 3931 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3932 POST_CHANGE);
ff8e20c6
DR		 3933 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3934 hba->ufs_stats.hibern8_exit_cnt++;
3935 }
57d104c1
SJ		 3936
3937 return ret;
3938}
9d19bf7a 3939EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 3940
ba7af5ec
SC		 3941void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
3942{
3943 unsigned long flags;
be7594a4 3944 bool update = false;
ba7af5ec 3945
be7594a4 3946 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 3947 return;
3948
3949 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 3950 if (hba->ahit != ahit) {
3951 hba->ahit = ahit;
3952 update = true;
3953 }
ba7af5ec 3954 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4
CG		 3955
3956 if (update && !pm_runtime_suspended(hba->dev)) {
3957 pm_runtime_get_sync(hba->dev);
3958 ufshcd_hold(hba, false);
3959 ufshcd_auto_hibern8_enable(hba);
3960 ufshcd_release(hba);
3961 pm_runtime_put(hba->dev);
3962 }
ba7af5ec
SC		 3963}
3964EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
3965
71d848b8 3966void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 3967{
3968 unsigned long flags;
3969
ee5f1042 3970 if (!ufshcd_is_auto_hibern8_supported(hba) || !hba->ahit)
ad448378
AH		 3971 return;
3972
3973 spin_lock_irqsave(hba->host->host_lock, flags);
3974 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3975 spin_unlock_irqrestore(hba->host->host_lock, flags);
3976}
3977
5064636c
YG		 3978 /**
3979 * ufshcd_init_pwr_info - setting the POR (power on reset)
3980 * values in hba power info
3981 * @hba: per-adapter instance
3982 */
3983static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3984{
3985 hba->pwr_info.gear_rx = UFS_PWM_G1;
3986 hba->pwr_info.gear_tx = UFS_PWM_G1;
3987 hba->pwr_info.lane_rx = 1;
3988 hba->pwr_info.lane_tx = 1;
3989 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3990 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3991 hba->pwr_info.hs_rate = 0;
3992}
3993
d3e89bac 3994/**
7eb584db
DR		 3995 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3996 * @hba: per-adapter instance
d3e89bac 3997 */
7eb584db 3998static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3999{
7eb584db
DR		 4000 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4001
4002 if (hba->max_pwr_info.is_valid)
4003 return 0;
4004
2349b533 4005 pwr_info->pwr_tx = FAST_MODE;
4006 pwr_info->pwr_rx = FAST_MODE;
7eb584db 4007 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4008
4009 /* Get the connected lane count */
7eb584db
DR		 4010 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4011 &pwr_info->lane_rx);
4012 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4013 &pwr_info->lane_tx);
4014
4015 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4016 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4017 __func__,
4018 pwr_info->lane_rx,
4019 pwr_info->lane_tx);
4020 return -EINVAL;
4021 }
d3e89bac
SJ		 4022
4023 /*
4024 * First, get the maximum gears of HS speed.
4025 * If a zero value, it means there is no HSGEAR capability.
4026 * Then, get the maximum gears of PWM speed.
4027 */
7eb584db
DR		 4028 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4029 if (!pwr_info->gear_rx) {
4030 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4031 &pwr_info->gear_rx);
4032 if (!pwr_info->gear_rx) {
4033 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4034 __func__, pwr_info->gear_rx);
4035 return -EINVAL;
4036 }
2349b533 4037 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4038 }
4039
7eb584db
DR		 4040 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4041 &pwr_info->gear_tx);
4042 if (!pwr_info->gear_tx) {
d3e89bac 4043 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4044 &pwr_info->gear_tx);
4045 if (!pwr_info->gear_tx) {
4046 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4047 __func__, pwr_info->gear_tx);
4048 return -EINVAL;
4049 }
2349b533 4050 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4051 }
4052
4053 hba->max_pwr_info.is_valid = true;
4054 return 0;
4055}
4056
4057static int ufshcd_change_power_mode(struct ufs_hba *hba,
4058 struct ufs_pa_layer_attr *pwr_mode)
4059{
4060 int ret;
4061
4062 /* if already configured to the requested pwr_mode */
4063 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4064 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4065 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4066 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4067 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4068 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4069 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4070 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4071 return 0;
d3e89bac
SJ		 4072 }
4073
4074 /*
4075 * Configure attributes for power mode change with below.
4076 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4077 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4078 * - PA_HSSERIES
4079 */
7eb584db
DR		 4080 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4081 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4082 pwr_mode->lane_rx);
4083 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4084 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4085 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4086 else
4087 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4088
7eb584db
DR		 4089 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4090 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4091 pwr_mode->lane_tx);
4092 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4093 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4094 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4095 else
4096 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4097
7eb584db
DR		 4098 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4099 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4100 pwr_mode->pwr_rx == FAST_MODE ||
4101 pwr_mode->pwr_tx == FAST_MODE)
4102 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4103 pwr_mode->hs_rate);
d3e89bac 4104
08342537
CG		 4105 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4106 DL_FC0ProtectionTimeOutVal_Default);
4107 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4108 DL_TC0ReplayTimeOutVal_Default);
4109 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4110 DL_AFC0ReqTimeOutVal_Default);
4111 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4112 DL_FC1ProtectionTimeOutVal_Default);
4113 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4114 DL_TC1ReplayTimeOutVal_Default);
4115 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4116 DL_AFC1ReqTimeOutVal_Default);
4117
4118 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4119 DL_FC0ProtectionTimeOutVal_Default);
4120 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4121 DL_TC0ReplayTimeOutVal_Default);
4122 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4123 DL_AFC0ReqTimeOutVal_Default);
4124
7eb584db
DR		 4125 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4126 | pwr_mode->pwr_tx);
4127
4128 if (ret) {
d3e89bac 4129 dev_err(hba->dev,
7eb584db
DR		 4130 "%s: power mode change failed %d\n", __func__, ret);
4131 } else {
0263bcd0
YG		 4132 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4133 pwr_mode);
7eb584db
DR		 4134
4135 memcpy(&hba->pwr_info, pwr_mode,
4136 sizeof(struct ufs_pa_layer_attr));
4137 }
4138
4139 return ret;
4140}
4141
4142/**
4143 * ufshcd_config_pwr_mode - configure a new power mode
4144 * @hba: per-adapter instance
4145 * @desired_pwr_mode: desired power configuration
4146 */
0d846e70 4147int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4148 struct ufs_pa_layer_attr *desired_pwr_mode)
4149{
4150 struct ufs_pa_layer_attr final_params = { 0 };
4151 int ret;
4152
0263bcd0
YG		 4153 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4154 desired_pwr_mode, &final_params);
4155
4156 if (ret)
7eb584db
DR		 4157 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4158
4159 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4160
4161 return ret;
4162}
0d846e70 4163EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4164
68078d5c
DR		 4165/**
4166 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4167 * @hba: per-adapter instance
68078d5c
DR		 4168 *
4169 * Set fDeviceInit flag and poll until device toggles it.
4170 */
4171static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4172{
dc3c8d3a
YG		 4173 int i;
4174 int err;
7dfdcc39 4175 bool flag_res = true;
68078d5c 4176
dc3c8d3a
YG		 4177 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4178 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4179 if (err) {
4180 dev_err(hba->dev,
4181 "%s setting fDeviceInit flag failed with error %d\n",
4182 __func__, err);
4183 goto out;
4184 }
4185
dc3c8d3a
YG		 4186 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4187 for (i = 0; i < 1000 && !err && flag_res; i++)
4188 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4189 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4190
68078d5c
DR		 4191 if (err)
4192 dev_err(hba->dev,
4193 "%s reading fDeviceInit flag failed with error %d\n",
4194 __func__, err);
4195 else if (flag_res)
4196 dev_err(hba->dev,
4197 "%s fDeviceInit was not cleared by the device\n",
4198 __func__);
4199
4200out:
4201 return err;
4202}
4203
7a3e97b0
SY		 4204/**
4205 * ufshcd_make_hba_operational - Make UFS controller operational
4206 * @hba: per adapter instance
4207 *
4208 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4209 * 1. Enable required interrupts
4210 * 2. Configure interrupt aggregation
897efe62 4211 * 3. Program UTRL and UTMRL base address
5c0c28a8 4212 * 4. Configure run-stop-registers
7a3e97b0
SY		 4213 *
4214 * Returns 0 on success, non-zero value on failure
4215 */
9d19bf7a 4216int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4217{
4218 int err = 0;
4219 u32 reg;
4220
6ccf44fe
SJ		 4221 /* Enable required interrupts */
4222 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4223
4224 /* Configure interrupt aggregation */
b852190e
YG		 4225 if (ufshcd_is_intr_aggr_allowed(hba))
4226 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4227 else
4228 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4229
4230 /* Configure UTRL and UTMRL base address registers */
4231 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4232 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4233 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4234 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4235 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4236 REG_UTP_TASK_REQ_LIST_BASE_L);
4237 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4238 REG_UTP_TASK_REQ_LIST_BASE_H);
4239
897efe62
YG		 4240 /*
4241 * Make sure base address and interrupt setup are updated before
4242 * enabling the run/stop registers below.
4243 */
4244 wmb();
4245
7a3e97b0
SY		 4246 /*
4247 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4248 */
5c0c28a8 4249 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4250 if (!(ufshcd_get_lists_status(reg))) {
4251 ufshcd_enable_run_stop_reg(hba);
4252 } else {
3b1d0580 4253 dev_err(hba->dev,
7a3e97b0
SY		 4254 "Host controller not ready to process requests");
4255 err = -EIO;
4256 goto out;
4257 }
4258
7a3e97b0
SY		 4259out:
4260 return err;
4261}
9d19bf7a 4262EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4263
596585a2
YG		 4264/**
4265 * ufshcd_hba_stop - Send controller to reset state
4266 * @hba: per adapter instance
4267 * @can_sleep: perform sleep or just spin
4268 */
4269static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4270{
4271 int err;
4272
4273 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4274 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4275 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4276 10, 1, can_sleep);
4277 if (err)
4278 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4279}
4280
7a3e97b0 4281/**
49200199 4282 * ufshcd_hba_enable - initialize the controller
7a3e97b0
SY		 4283 * @hba: per adapter instance
4284 *
4285 * The controller resets itself and controller firmware initialization
4286 * sequence kicks off. When controller is ready it will set
4287 * the Host Controller Enable bit to 1.
4288 *
4289 * Returns 0 on success, non-zero value on failure
4290 */
49200199 4291int ufshcd_hba_enable(struct ufs_hba *hba)
7a3e97b0
SY		 4292{
4293 int retry;
4294
596585a2 4295 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4296 /* change controller state to "reset state" */
596585a2 4297 ufshcd_hba_stop(hba, true);
7a3e97b0 4298
57d104c1
SJ		 4299 /* UniPro link is disabled at this point */
4300 ufshcd_set_link_off(hba);
4301
0263bcd0 4302 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4303
7a3e97b0
SY		 4304 /* start controller initialization sequence */
4305 ufshcd_hba_start(hba);
4306
4307 /*
4308 * To initialize a UFS host controller HCE bit must be set to 1.
4309 * During initialization the HCE bit value changes from 1->0->1.
4310 * When the host controller completes initialization sequence
4311 * it sets the value of HCE bit to 1. The same HCE bit is read back
4312 * to check if the controller has completed initialization sequence.
4313 * So without this delay the value HCE = 1, set in the previous
4314 * instruction might be read back.
4315 * This delay can be changed based on the controller.
4316 */
b9dc8aca 4317 ufshcd_delay_us(hba->hba_enable_delay_us, 100);
7a3e97b0
SY		 4318
4319 /* wait for the host controller to complete initialization */
9fc305ef 4320 retry = 50;
7a3e97b0
SY		 4321 while (ufshcd_is_hba_active(hba)) {
4322 if (retry) {
4323 retry--;
4324 } else {
3b1d0580 4325 dev_err(hba->dev,
7a3e97b0
SY		 4326 "Controller enable failed\n");
4327 return -EIO;
4328 }
9fc305ef 4329 usleep_range(1000, 1100);
7a3e97b0 4330 }
5c0c28a8 4331
1d337ec2 4332 /* enable UIC related interrupts */
57d104c1 4333 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4334
0263bcd0 4335 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4336
7a3e97b0
SY		 4337 return 0;
4338}
9d19bf7a
SC		 4339EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4340
7ca38cf3
YG		 4341static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4342{
ba0320fb 4343 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4344
4345 if (!peer)
4346 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4347 &tx_lanes);
4348 else
4349 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4350 &tx_lanes);
4351 for (i = 0; i < tx_lanes; i++) {
4352 if (!peer)
4353 err = ufshcd_dme_set(hba,
4354 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4355 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4356 0);
4357 else
4358 err = ufshcd_dme_peer_set(hba,
4359 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4360 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4361 0);
4362 if (err) {
4363 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4364 __func__, peer, i, err);
4365 break;
4366 }
4367 }
4368
4369 return err;
4370}
4371
4372static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4373{
4374 return ufshcd_disable_tx_lcc(hba, true);
4375}
4376
a5fe372d
SC		 4377void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4378 u32 reg)
8808b4e9
SC		 4379{
4380 reg_hist->reg[reg_hist->pos] = reg;
4381 reg_hist->tstamp[reg_hist->pos] = ktime_get();
4382 reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4383}
a5fe372d 4384EXPORT_SYMBOL_GPL(ufshcd_update_reg_hist);
8808b4e9 4385
7a3e97b0 4386/**
6ccf44fe 4387 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4388 * @hba: per adapter instance
4389 *
6ccf44fe 4390 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4391 */
6ccf44fe 4392static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4393{
6ccf44fe 4394 int ret;
1d337ec2 4395 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4396 bool link_startup_again = false;
7a3e97b0 4397
7caf489b 4398 /*
4399 * If UFS device isn't active then we will have to issue link startup
4400 * 2 times to make sure the device state move to active.
4401 */
4402 if (!ufshcd_is_ufs_dev_active(hba))
4403 link_startup_again = true;
7a3e97b0 4404
7caf489b 4405link_startup:
1d337ec2 4406 do {
0263bcd0 4407 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4408
1d337ec2 4409 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4410
1d337ec2
SRT		 4411 /* check if device is detected by inter-connect layer */
4412 if (!ret && !ufshcd_is_device_present(hba)) {
8808b4e9
SC		 4413 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4414 0);
1d337ec2
SRT		 4415 dev_err(hba->dev, "%s: Device not present\n", __func__);
4416 ret = -ENXIO;
4417 goto out;
4418 }
6ccf44fe 4419
1d337ec2
SRT		 4420 /*
4421 * DME link lost indication is only received when link is up,
4422 * but we can't be sure if the link is up until link startup
4423 * succeeds. So reset the local Uni-Pro and try again.
4424 */
8808b4e9
SC		 4425 if (ret && ufshcd_hba_enable(hba)) {
4426 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4427 (u32)ret);
1d337ec2 4428 goto out;
8808b4e9 4429 }
1d337ec2
SRT		 4430 } while (ret && retries--);
4431
8808b4e9 4432 if (ret) {
1d337ec2 4433 /* failed to get the link up... retire */
8808b4e9
SC		 4434 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4435 (u32)ret);
5c0c28a8 4436 goto out;
8808b4e9 4437 }
5c0c28a8 4438
7caf489b 4439 if (link_startup_again) {
4440 link_startup_again = false;
4441 retries = DME_LINKSTARTUP_RETRIES;
4442 goto link_startup;
4443 }
4444
d2aebb9b 4445 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4446 ufshcd_init_pwr_info(hba);
4447 ufshcd_print_pwr_info(hba);
4448
7ca38cf3
YG		 4449 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4450 ret = ufshcd_disable_device_tx_lcc(hba);
4451 if (ret)
4452 goto out;
4453 }
4454
5c0c28a8 4455 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4456 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4457 if (ret)
4458 goto out;
7a3e97b0 4459
5c0c28a8 4460 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4461out:
7942f7b5 4462 if (ret) {
6ccf44fe 4463 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4464 ufshcd_print_host_state(hba);
4465 ufshcd_print_pwr_info(hba);
4466 ufshcd_print_host_regs(hba);
4467 }
6ccf44fe 4468 return ret;
7a3e97b0
SY		 4469}
4470
5a0b0cb9
SRT		 4471/**
4472 * ufshcd_verify_dev_init() - Verify device initialization
4473 * @hba: per-adapter instance
4474 *
4475 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4476 * device Transport Protocol (UTP) layer is ready after a reset.
4477 * If the UTP layer at the device side is not initialized, it may
4478 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4479 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4480 */
4481static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4482{
4483 int err = 0;
4484 int retries;
4485
1ab27c9c 4486 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4487 mutex_lock(&hba->dev_cmd.lock);
4488 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4489 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4490 NOP_OUT_TIMEOUT);
4491
4492 if (!err || err == -ETIMEDOUT)
4493 break;
4494
4495 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4496 }
4497 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4498 ufshcd_release(hba);
5a0b0cb9
SRT		 4499
4500 if (err)
4501 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4502 return err;
4503}
4504
0ce147d4
SJ		 4505/**
4506 * ufshcd_set_queue_depth - set lun queue depth
4507 * @sdev: pointer to SCSI device
4508 *
4509 * Read bLUQueueDepth value and activate scsi tagged command
4510 * queueing. For WLUN, queue depth is set to 1. For best-effort
4511 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4512 * value that host can queue.
4513 */
4514static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4515{
4516 int ret = 0;
4517 u8 lun_qdepth;
4518 struct ufs_hba *hba;
4519
4520 hba = shost_priv(sdev->host);
4521
4522 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4523 ret = ufshcd_read_unit_desc_param(hba,
4524 ufshcd_scsi_to_upiu_lun(sdev->lun),
4525 UNIT_DESC_PARAM_LU_Q_DEPTH,
4526 &lun_qdepth,
4527 sizeof(lun_qdepth));
0ce147d4
SJ		 4528
4529 /* Some WLUN doesn't support unit descriptor */
4530 if (ret == -EOPNOTSUPP)
4531 lun_qdepth = 1;
4532 else if (!lun_qdepth)
4533 /* eventually, we can figure out the real queue depth */
4534 lun_qdepth = hba->nutrs;
4535 else
4536 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4537
4538 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4539 __func__, lun_qdepth);
db5ed4df 4540 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4541}
4542
57d104c1
SJ		 4543/*
4544 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4545 * @hba: per-adapter instance
4546 * @lun: UFS device lun id
4547 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4548 *
4549 * Returns 0 in case of success and b_lu_write_protect status would be returned
4550 * @b_lu_write_protect parameter.
4551 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4552 * Returns -EINVAL in case of invalid parameters passed to this function.
4553 */
4554static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4555 u8 lun,
4556 u8 *b_lu_write_protect)
4557{
4558 int ret;
4559
4560 if (!b_lu_write_protect)
4561 ret = -EINVAL;
4562 /*
4563 * According to UFS device spec, RPMB LU can't be write
4564 * protected so skip reading bLUWriteProtect parameter for
4565 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4566 */
1baa8011 4567 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4568 ret = -ENOTSUPP;
4569 else
4570 ret = ufshcd_read_unit_desc_param(hba,
4571 lun,
4572 UNIT_DESC_PARAM_LU_WR_PROTECT,
4573 b_lu_write_protect,
4574 sizeof(*b_lu_write_protect));
4575 return ret;
4576}
4577
4578/**
4579 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4580 * status
4581 * @hba: per-adapter instance
4582 * @sdev: pointer to SCSI device
4583 *
4584 */
4585static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4586 struct scsi_device *sdev)
4587{
4588 if (hba->dev_info.f_power_on_wp_en &&
4589 !hba->dev_info.is_lu_power_on_wp) {
4590 u8 b_lu_write_protect;
4591
4592 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4593 &b_lu_write_protect) &&
4594 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4595 hba->dev_info.is_lu_power_on_wp = true;
4596 }
4597}
4598
7a3e97b0
SY		 4599/**
4600 * ufshcd_slave_alloc - handle initial SCSI device configurations
4601 * @sdev: pointer to SCSI device
4602 *
4603 * Returns success
4604 */
4605static int ufshcd_slave_alloc(struct scsi_device *sdev)
4606{
4607 struct ufs_hba *hba;
4608
4609 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4610
4611 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4612 sdev->use_10_for_ms = 1;
a3a76391
CG		 4613
4614 /* DBD field should be set to 1 in mode sense(10) */
4615 sdev->set_dbd_for_ms = 1;
7a3e97b0 4616
e8e7f271
SRT		 4617 /* allow SCSI layer to restart the device in case of errors */
4618 sdev->allow_restart = 1;
4264fd61 4619
b2a6c522
SRT		 4620 /* REPORT SUPPORTED OPERATION CODES is not supported */
4621 sdev->no_report_opcodes = 1;
4622
84af7e8b
SRT		 4623 /* WRITE_SAME command is not supported */
4624 sdev->no_write_same = 1;
e8e7f271 4625
0ce147d4 4626 ufshcd_set_queue_depth(sdev);
4264fd61 4627
57d104c1
SJ		 4628 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4629
7a3e97b0
SY		 4630 return 0;
4631}
4632
4264fd61
SRT		 4633/**
4634 * ufshcd_change_queue_depth - change queue depth
4635 * @sdev: pointer to SCSI device
4636 * @depth: required depth to set
4264fd61 4637 *
db5ed4df 4638 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4639 */
db5ed4df 4640static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4641{
4642 struct ufs_hba *hba = shost_priv(sdev->host);
4643
4644 if (depth > hba->nutrs)
4645 depth = hba->nutrs;
db5ed4df 4646 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4647}
4648
eeda4749
AM		 4649/**
4650 * ufshcd_slave_configure - adjust SCSI device configurations
4651 * @sdev: pointer to SCSI device
4652 */
4653static int ufshcd_slave_configure(struct scsi_device *sdev)
4654{
49615ba1 4655 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 4656 struct request_queue *q = sdev->request_queue;
4657
4658 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
49615ba1
SC		 4659
4660 if (ufshcd_is_rpm_autosuspend_allowed(hba))
4661 sdev->rpm_autosuspend = 1;
4662
eeda4749
AM		 4663 return 0;
4664}
4665
7a3e97b0
SY		 4666/**
4667 * ufshcd_slave_destroy - remove SCSI device configurations
4668 * @sdev: pointer to SCSI device
4669 */
4670static void ufshcd_slave_destroy(struct scsi_device *sdev)
4671{
4672 struct ufs_hba *hba;
4673
4674 hba = shost_priv(sdev->host);
0ce147d4 4675 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4676 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4677 unsigned long flags;
4678
4679 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4680 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4681 spin_unlock_irqrestore(hba->host->host_lock, flags);
4682 }
7a3e97b0
SY		 4683}
4684
7a3e97b0
SY		 4685/**
4686 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4687 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4688 * @scsi_status: SCSI command status
4689 *
4690 * Returns value base on SCSI command status
4691 */
4692static inline int
4693ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4694{
4695 int result = 0;
4696
4697 switch (scsi_status) {
7a3e97b0 4698 case SAM_STAT_CHECK_CONDITION:
1c2623c5 4699 ufshcd_copy_sense_data(lrbp);
30eb2e4c 4700 /* fallthrough */
1c2623c5 4701 case SAM_STAT_GOOD:
7a3e97b0
SY		 4702 result |= DID_OK << 16 |
4703 COMMAND_COMPLETE << 8 |
1c2623c5 4704 scsi_status;
7a3e97b0
SY		 4705 break;
4706 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4707 case SAM_STAT_BUSY:
7a3e97b0 4708 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4709 ufshcd_copy_sense_data(lrbp);
4710 result |= scsi_status;
7a3e97b0
SY		 4711 break;
4712 default:
4713 result |= DID_ERROR << 16;
4714 break;
4715 } /* end of switch */
4716
4717 return result;
4718}
4719
4720/**
4721 * ufshcd_transfer_rsp_status - Get overall status of the response
4722 * @hba: per adapter instance
8aa29f19 4723 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4724 *
4725 * Returns result of the command to notify SCSI midlayer
4726 */
4727static inline int
4728ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4729{
4730 int result = 0;
4731 int scsi_status;
4732 int ocs;
4733
4734 /* overall command status of utrd */
4735 ocs = ufshcd_get_tr_ocs(lrbp);
4736
4737 switch (ocs) {
4738 case OCS_SUCCESS:
5a0b0cb9 4739 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4740 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4741 switch (result) {
4742 case UPIU_TRANSACTION_RESPONSE:
4743 /*
4744 * get the response UPIU result to extract
4745 * the SCSI command status
4746 */
4747 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4748
4749 /*
4750 * get the result based on SCSI status response
4751 * to notify the SCSI midlayer of the command status
4752 */
4753 scsi_status = result & MASK_SCSI_STATUS;
4754 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4755
f05ac2e5
YG		 4756 /*
4757 * Currently we are only supporting BKOPs exception
4758 * events hence we can ignore BKOPs exception event
4759 * during power management callbacks. BKOPs exception
4760 * event is not expected to be raised in runtime suspend
4761 * callback as it allows the urgent bkops.
4762 * During system suspend, we are anyway forcefully
4763 * disabling the bkops and if urgent bkops is needed
4764 * it will be enabled on system resume. Long term
4765 * solution could be to abort the system suspend if
4766 * UFS device needs urgent BKOPs.
4767 */
4768 if (!hba->pm_op_in_progress &&
2824ec9f
SL		 4769 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4770 schedule_work(&hba->eeh_work)) {
4771 /*
4772 * Prevent suspend once eeh_work is scheduled
4773 * to avoid deadlock between ufshcd_suspend
4774 * and exception event handler.
4775 */
4776 pm_runtime_get_noresume(hba->dev);
4777 }
5a0b0cb9
SRT		 4778 break;
4779 case UPIU_TRANSACTION_REJECT_UPIU:
4780 /* TODO: handle Reject UPIU Response */
4781 result = DID_ERROR << 16;
3b1d0580 4782 dev_err(hba->dev,
5a0b0cb9
SRT		 4783 "Reject UPIU not fully implemented\n");
4784 break;
4785 default:
5a0b0cb9
SRT		 4786 dev_err(hba->dev,
4787 "Unexpected request response code = %x\n",
4788 result);
e0347d89 4789 result = DID_ERROR << 16;
7a3e97b0
SY		 4790 break;
4791 }
7a3e97b0
SY		 4792 break;
4793 case OCS_ABORTED:
4794 result |= DID_ABORT << 16;
4795 break;
e8e7f271
SRT		 4796 case OCS_INVALID_COMMAND_STATUS:
4797 result |= DID_REQUEUE << 16;
4798 break;
7a3e97b0
SY		 4799 case OCS_INVALID_CMD_TABLE_ATTR:
4800 case OCS_INVALID_PRDT_ATTR:
4801 case OCS_MISMATCH_DATA_BUF_SIZE:
4802 case OCS_MISMATCH_RESP_UPIU_SIZE:
4803 case OCS_PEER_COMM_FAILURE:
4804 case OCS_FATAL_ERROR:
4805 default:
4806 result |= DID_ERROR << 16;
3b1d0580 4807 dev_err(hba->dev,
ff8e20c6
DR		 4808 "OCS error from controller = %x for tag %d\n",
4809 ocs, lrbp->task_tag);
4810 ufshcd_print_host_regs(hba);
6ba65588 4811 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4812 break;
4813 } /* end of switch */
4814
2df74b69 4815 if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
66cc820f 4816 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4817 return result;
4818}
4819
6ccf44fe
SJ		 4820/**
4821 * ufshcd_uic_cmd_compl - handle completion of uic command
4822 * @hba: per adapter instance
53b3d9c3 4823 * @intr_status: interrupt status generated by the controller
9333d775
VG		 4824 *
4825 * Returns
4826 * IRQ_HANDLED - If interrupt is valid
4827 * IRQ_NONE - If invalid interrupt
6ccf44fe 4828 */
9333d775 4829static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4830{
9333d775
VG		 4831 irqreturn_t retval = IRQ_NONE;
4832
53b3d9c3 4833 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4834 hba->active_uic_cmd->argument2 |=
4835 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4836 hba->active_uic_cmd->argument3 =
4837 ufshcd_get_dme_attr_val(hba);
6ccf44fe 4838 complete(&hba->active_uic_cmd->done);
9333d775 4839 retval = IRQ_HANDLED;
6ccf44fe 4840 }
53b3d9c3 4841
9333d775 4842 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
57d104c1 4843 complete(hba->uic_async_done);
9333d775
VG		 4844 retval = IRQ_HANDLED;
4845 }
4846 return retval;
6ccf44fe
SJ		 4847}
4848
7a3e97b0 4849/**
9a47ec7c 4850 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4851 * @hba: per adapter instance
9a47ec7c 4852 * @completed_reqs: requests to complete
7a3e97b0 4853 */
9a47ec7c
YG		 4854static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4855 unsigned long completed_reqs)
7a3e97b0 4856{
5a0b0cb9
SRT		 4857 struct ufshcd_lrb *lrbp;
4858 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4859 int result;
4860 int index;
e9d501b1 4861
e9d501b1
DR		 4862 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4863 lrbp = &hba->lrb[index];
4864 cmd = lrbp->cmd;
4865 if (cmd) {
1a07f2d9 4866 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4867 result = ufshcd_transfer_rsp_status(hba, lrbp);
4868 scsi_dma_unmap(cmd);
4869 cmd->result = result;
4870 /* Mark completed command as NULL in LRB */
4871 lrbp->cmd = NULL;
74a527a2 4872 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 4873 /* Do not touch lrbp after scsi done */
4874 cmd->scsi_done(cmd);
1ab27c9c 4875 __ufshcd_release(hba);
300bb13f
JP		 4876 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4877 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
74a527a2 4878 lrbp->compl_time_stamp = ktime_get();
1a07f2d9
LS		 4879 if (hba->dev_cmd.complete) {
4880 ufshcd_add_command_trace(hba, index,
4881 "dev_complete");
e9d501b1 4882 complete(hba->dev_cmd.complete);
1a07f2d9 4883 }
e9d501b1 4884 }
401f1e44 4885 if (ufshcd_is_clkscaling_supported(hba))
4886 hba->clk_scaling.active_reqs--;
e9d501b1 4887 }
7a3e97b0
SY		 4888
4889 /* clear corresponding bits of completed commands */
4890 hba->outstanding_reqs ^= completed_reqs;
4891
856b3483 4892 ufshcd_clk_scaling_update_busy(hba);
7a3e97b0
SY		 4893}
4894
9a47ec7c
YG		 4895/**
4896 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4897 * @hba: per adapter instance
9333d775
VG		 4898 *
4899 * Returns
4900 * IRQ_HANDLED - If interrupt is valid
4901 * IRQ_NONE - If invalid interrupt
9a47ec7c 4902 */
9333d775 4903static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c
YG		 4904{
4905 unsigned long completed_reqs;
4906 u32 tr_doorbell;
4907
4908 /* Resetting interrupt aggregation counters first and reading the
4909 * DOOR_BELL afterward allows us to handle all the completed requests.
4910 * In order to prevent other interrupts starvation the DB is read once
4911 * after reset. The down side of this solution is the possibility of
4912 * false interrupt if device completes another request after resetting
4913 * aggregation and before reading the DB.
4914 */
49200199 4915 if (ufshcd_is_intr_aggr_allowed(hba))
9a47ec7c
YG		 4916 ufshcd_reset_intr_aggr(hba);
4917
4918 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4919 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4920
9333d775
VG		 4921 if (completed_reqs) {
4922 __ufshcd_transfer_req_compl(hba, completed_reqs);
4923 return IRQ_HANDLED;
4924 } else {
4925 return IRQ_NONE;
4926 }
9a47ec7c
YG		 4927}
4928
66ec6d59
SRT		 4929/**
4930 * ufshcd_disable_ee - disable exception event
4931 * @hba: per-adapter instance
4932 * @mask: exception event to disable
4933 *
4934 * Disables exception event in the device so that the EVENT_ALERT
4935 * bit is not set.
4936 *
4937 * Returns zero on success, non-zero error value on failure.
4938 */
4939static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4940{
4941 int err = 0;
4942 u32 val;
4943
4944 if (!(hba->ee_ctrl_mask & mask))
4945 goto out;
4946
4947 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4948 val &= MASK_EE_STATUS;
5e86ae44 4949 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4950 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4951 if (!err)
4952 hba->ee_ctrl_mask &= ~mask;
4953out:
4954 return err;
4955}
4956
4957/**
4958 * ufshcd_enable_ee - enable exception event
4959 * @hba: per-adapter instance
4960 * @mask: exception event to enable
4961 *
4962 * Enable corresponding exception event in the device to allow
4963 * device to alert host in critical scenarios.
4964 *
4965 * Returns zero on success, non-zero error value on failure.
4966 */
4967static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4968{
4969 int err = 0;
4970 u32 val;
4971
4972 if (hba->ee_ctrl_mask & mask)
4973 goto out;
4974
4975 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4976 val &= MASK_EE_STATUS;
5e86ae44 4977 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4978 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4979 if (!err)
4980 hba->ee_ctrl_mask |= mask;
4981out:
4982 return err;
4983}
4984
4985/**
4986 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4987 * @hba: per-adapter instance
4988 *
4989 * Allow device to manage background operations on its own. Enabling
4990 * this might lead to inconsistent latencies during normal data transfers
4991 * as the device is allowed to manage its own way of handling background
4992 * operations.
4993 *
4994 * Returns zero on success, non-zero on failure.
4995 */
4996static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4997{
4998 int err = 0;
4999
5000 if (hba->auto_bkops_enabled)
5001 goto out;
5002
dc3c8d3a 5003 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 5004 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5005 if (err) {
5006 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5007 __func__, err);
5008 goto out;
5009 }
5010
5011 hba->auto_bkops_enabled = true;
7ff5ab47 5012 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5013
5014 /* No need of URGENT_BKOPS exception from the device */
5015 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5016 if (err)
5017 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5018 __func__, err);
5019out:
5020 return err;
5021}
5022
5023/**
5024 * ufshcd_disable_auto_bkops - block device in doing background operations
5025 * @hba: per-adapter instance
5026 *
5027 * Disabling background operations improves command response latency but
5028 * has drawback of device moving into critical state where the device is
5029 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5030 * host is idle so that BKOPS are managed effectively without any negative
5031 * impacts.
5032 *
5033 * Returns zero on success, non-zero on failure.
5034 */
5035static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5036{
5037 int err = 0;
5038
5039 if (!hba->auto_bkops_enabled)
5040 goto out;
5041
5042 /*
5043 * If host assisted BKOPs is to be enabled, make sure
5044 * urgent bkops exception is allowed.
5045 */
5046 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5047 if (err) {
5048 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5049 __func__, err);
5050 goto out;
5051 }
5052
dc3c8d3a 5053 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 5054 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5055 if (err) {
5056 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5057 __func__, err);
5058 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5059 goto out;
5060 }
5061
5062 hba->auto_bkops_enabled = false;
7ff5ab47 5063 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5064 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5065out:
5066 return err;
5067}
5068
5069/**
4e768e76 5070 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5071 * @hba: per adapter instance
5072 *
5073 * After a device reset the device may toggle the BKOPS_EN flag
5074 * to default value. The s/w tracking variables should be updated
4e768e76 5075 * as well. This function would change the auto-bkops state based on
5076 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5077 */
4e768e76 5078static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5079{
4e768e76 5080 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5081 hba->auto_bkops_enabled = false;
5082 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5083 ufshcd_enable_auto_bkops(hba);
5084 } else {
5085 hba->auto_bkops_enabled = true;
5086 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5087 ufshcd_disable_auto_bkops(hba);
5088 }
24366c2a 5089 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5090}
5091
5092static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5093{
5e86ae44 5094 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5095 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5096}
5097
5098/**
57d104c1 5099 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5100 * @hba: per-adapter instance
57d104c1 5101 * @status: bkops_status value
66ec6d59 5102 *
57d104c1
SJ		 5103 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5104 * flag in the device to permit background operations if the device
5105 * bkops_status is greater than or equal to "status" argument passed to
5106 * this function, disable otherwise.
5107 *
5108 * Returns 0 for success, non-zero in case of failure.
5109 *
5110 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5111 * to know whether auto bkops is enabled or disabled after this function
5112 * returns control to it.
66ec6d59 5113 */
57d104c1
SJ		 5114static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5115 enum bkops_status status)
66ec6d59
SRT		 5116{
5117 int err;
57d104c1 5118 u32 curr_status = 0;
66ec6d59 5119
57d104c1 5120 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5121 if (err) {
5122 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5123 __func__, err);
5124 goto out;
57d104c1
SJ		 5125 } else if (curr_status > BKOPS_STATUS_MAX) {
5126 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5127 __func__, curr_status);
5128 err = -EINVAL;
5129 goto out;
66ec6d59
SRT		 5130 }
5131
57d104c1 5132 if (curr_status >= status)
66ec6d59 5133 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5134 else
5135 err = ufshcd_disable_auto_bkops(hba);
24366c2a 5136 hba->urgent_bkops_lvl = curr_status;
66ec6d59
SRT		 5137out:
5138 return err;
5139}
5140
57d104c1
SJ		 5141/**
5142 * ufshcd_urgent_bkops - handle urgent bkops exception event
5143 * @hba: per-adapter instance
5144 *
5145 * Enable fBackgroundOpsEn flag in the device to permit background
5146 * operations.
5147 *
5148 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5149 * and negative error value for any other failure.
5150 */
5151static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5152{
afdfff59 5153 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5154}
5155
66ec6d59
SRT		 5156static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5157{
5e86ae44 5158 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5159 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5160}
5161
afdfff59
YG		 5162static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5163{
5164 int err;
5165 u32 curr_status = 0;
5166
5167 if (hba->is_urgent_bkops_lvl_checked)
5168 goto enable_auto_bkops;
5169
5170 err = ufshcd_get_bkops_status(hba, &curr_status);
5171 if (err) {
5172 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5173 __func__, err);
5174 goto out;
5175 }
5176
5177 /*
5178 * We are seeing that some devices are raising the urgent bkops
5179 * exception events even when BKOPS status doesn't indicate performace
5180 * impacted or critical. Handle these device by determining their urgent
5181 * bkops status at runtime.
5182 */
5183 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5184 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5185 __func__, curr_status);
5186 /* update the current status as the urgent bkops level */
5187 hba->urgent_bkops_lvl = curr_status;
5188 hba->is_urgent_bkops_lvl_checked = true;
5189 }
5190
5191enable_auto_bkops:
5192 err = ufshcd_enable_auto_bkops(hba);
5193out:
5194 if (err < 0)
5195 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5196 __func__, err);
5197}
5198
3d17b9b5
AD		 5199static bool ufshcd_wb_sup(struct ufs_hba *hba)
5200{
5201 return ufshcd_is_wb_allowed(hba);
5202}
5203
5204static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable)
5205{
5206 int ret;
5207 enum query_opcode opcode;
5208
5209 if (!ufshcd_wb_sup(hba))
5210 return 0;
5211
5212 if (!(enable ^ hba->wb_enabled))
5213 return 0;
5214 if (enable)
5215 opcode = UPIU_QUERY_OPCODE_SET_FLAG;
5216 else
5217 opcode = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5218
5219 ret = ufshcd_query_flag_retry(hba, opcode,
5220 QUERY_FLAG_IDN_WB_EN, NULL);
5221 if (ret) {
5222 dev_err(hba->dev, "%s write booster %s failed %d\n",
5223 __func__, enable ? "enable" : "disable", ret);
5224 return ret;
5225 }
5226
5227 hba->wb_enabled = enable;
5228 dev_dbg(hba->dev, "%s write booster %s %d\n",
5229 __func__, enable ? "enable" : "disable", ret);
5230
5231 return ret;
5232}
5233
5234static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5235{
5236 int val;
5237
5238 if (set)
5239 val = UPIU_QUERY_OPCODE_SET_FLAG;
5240 else
5241 val = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5242
5243 return ufshcd_query_flag_retry(hba, val,
5244 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8,
5245 NULL);
5246}
5247
5248static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5249{
5250 if (enable)
5251 ufshcd_wb_buf_flush_enable(hba);
5252 else
5253 ufshcd_wb_buf_flush_disable(hba);
5254
5255}
5256
5257static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba)
5258{
5259 int ret;
5260
5261 if (!ufshcd_wb_sup(hba) || hba->wb_buf_flush_enabled)
5262 return 0;
5263
5264 ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5265 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN, NULL);
5266 if (ret)
5267 dev_err(hba->dev, "%s WB - buf flush enable failed %d\n",
5268 __func__, ret);
5269 else
5270 hba->wb_buf_flush_enabled = true;
5271
5272 dev_dbg(hba->dev, "WB - Flush enabled: %d\n", ret);
5273 return ret;
5274}
5275
5276static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba)
5277{
5278 int ret;
5279
5280 if (!ufshcd_wb_sup(hba) || !hba->wb_buf_flush_enabled)
5281 return 0;
5282
5283 ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5284 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN, NULL);
5285 if (ret) {
5286 dev_warn(hba->dev, "%s: WB - buf flush disable failed %d\n",
5287 __func__, ret);
5288 } else {
5289 hba->wb_buf_flush_enabled = false;
5290 dev_dbg(hba->dev, "WB - Flush disabled: %d\n", ret);
5291 }
5292
5293 return ret;
5294}
5295
5296static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5297 u32 avail_buf)
5298{
5299 u32 cur_buf;
5300 int ret;
5301
5302 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5303 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5304 0, 0, &cur_buf);
5305 if (ret) {
5306 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5307 __func__, ret);
5308 return false;
5309 }
5310
5311 if (!cur_buf) {
5312 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5313 cur_buf);
5314 return false;
5315 }
5316 /* Let it continue to flush when >60% full */
5317 if (avail_buf < UFS_WB_40_PERCENT_BUF_REMAIN)
5318 return true;
5319
5320 return false;
5321}
5322
5323static bool ufshcd_wb_keep_vcc_on(struct ufs_hba *hba)
5324{
5325 int ret;
5326 u32 avail_buf;
5327
5328 if (!ufshcd_wb_sup(hba))
5329 return false;
5330 /*
5331 * The ufs device needs the vcc to be ON to flush.
5332 * With user-space reduction enabled, it's enough to enable flush
5333 * by checking only the available buffer. The threshold
5334 * defined here is > 90% full.
5335 * With user-space preserved enabled, the current-buffer
5336 * should be checked too because the wb buffer size can reduce
5337 * when disk tends to be full. This info is provided by current
5338 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5339 * keeping vcc on when current buffer is empty.
5340 */
5341 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5342 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5343 0, 0, &avail_buf);
5344 if (ret) {
5345 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5346 __func__, ret);
5347 return false;
5348 }
5349
5350 if (!hba->dev_info.b_presrv_uspc_en) {
5351 if (avail_buf <= UFS_WB_10_PERCENT_BUF_REMAIN)
5352 return true;
5353 return false;
5354 }
5355
5356 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5357}
5358
66ec6d59
SRT		 5359/**
5360 * ufshcd_exception_event_handler - handle exceptions raised by device
5361 * @work: pointer to work data
5362 *
5363 * Read bExceptionEventStatus attribute from the device and handle the
5364 * exception event accordingly.
5365 */
5366static void ufshcd_exception_event_handler(struct work_struct *work)
5367{
5368 struct ufs_hba *hba;
5369 int err;
5370 u32 status = 0;
5371 hba = container_of(work, struct ufs_hba, eeh_work);
5372
62694735 5373 pm_runtime_get_sync(hba->dev);
03e1d28e 5374 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5375 err = ufshcd_get_ee_status(hba, &status);
5376 if (err) {
5377 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5378 __func__, err);
5379 goto out;
5380 }
5381
5382 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5383
5384 if (status & MASK_EE_URGENT_BKOPS)
5385 ufshcd_bkops_exception_event_handler(hba);
5386
66ec6d59 5387out:
03e1d28e 5388 ufshcd_scsi_unblock_requests(hba);
2824ec9f
SL		 5389 /*
5390 * pm_runtime_get_noresume is called while scheduling
5391 * eeh_work to avoid suspend racing with exception work.
5392 * Hence decrement usage counter using pm_runtime_put_noidle
5393 * to allow suspend on completion of exception event handler.
5394 */
5395 pm_runtime_put_noidle(hba->dev);
5396 pm_runtime_put(hba->dev);
66ec6d59
SRT		 5397 return;
5398}
5399
9a47ec7c
YG		 5400/* Complete requests that have door-bell cleared */
5401static void ufshcd_complete_requests(struct ufs_hba *hba)
5402{
5403 ufshcd_transfer_req_compl(hba);
5404 ufshcd_tmc_handler(hba);
5405}
5406
583fa62d
YG		 5407/**
5408 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5409 * to recover from the DL NAC errors or not.
5410 * @hba: per-adapter instance
5411 *
5412 * Returns true if error handling is required, false otherwise
5413 */
5414static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5415{
5416 unsigned long flags;
5417 bool err_handling = true;
5418
5419 spin_lock_irqsave(hba->host->host_lock, flags);
5420 /*
5421 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5422 * device fatal error and/or DL NAC & REPLAY timeout errors.
5423 */
5424 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5425 goto out;
5426
5427 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5428 ((hba->saved_err & UIC_ERROR) &&
5429 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5430 goto out;
5431
5432 if ((hba->saved_err & UIC_ERROR) &&
5433 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5434 int err;
5435 /*
5436 * wait for 50ms to see if we can get any other errors or not.
5437 */
5438 spin_unlock_irqrestore(hba->host->host_lock, flags);
5439 msleep(50);
5440 spin_lock_irqsave(hba->host->host_lock, flags);
5441
5442 /*
5443 * now check if we have got any other severe errors other than
5444 * DL NAC error?
5445 */
5446 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5447 ((hba->saved_err & UIC_ERROR) &&
5448 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5449 goto out;
5450
5451 /*
5452 * As DL NAC is the only error received so far, send out NOP
5453 * command to confirm if link is still active or not.
5454 * - If we don't get any response then do error recovery.
5455 * - If we get response then clear the DL NAC error bit.
5456 */
5457
5458 spin_unlock_irqrestore(hba->host->host_lock, flags);
5459 err = ufshcd_verify_dev_init(hba);
5460 spin_lock_irqsave(hba->host->host_lock, flags);
5461
5462 if (err)
5463 goto out;
5464
5465 /* Link seems to be alive hence ignore the DL NAC errors */
5466 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5467 hba->saved_err &= ~UIC_ERROR;
5468 /* clear NAC error */
5469 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5470 if (!hba->saved_uic_err) {
5471 err_handling = false;
5472 goto out;
5473 }
5474 }
5475out:
5476 spin_unlock_irqrestore(hba->host->host_lock, flags);
5477 return err_handling;
5478}
5479
7a3e97b0 5480/**
e8e7f271
SRT		 5481 * ufshcd_err_handler - handle UFS errors that require s/w attention
5482 * @work: pointer to work structure
7a3e97b0 5483 */
e8e7f271 5484static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5485{
5486 struct ufs_hba *hba;
e8e7f271
SRT		 5487 unsigned long flags;
5488 u32 err_xfer = 0;
5489 u32 err_tm = 0;
5490 int err = 0;
5491 int tag;
9a47ec7c 5492 bool needs_reset = false;
e8e7f271
SRT		 5493
5494 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5495
62694735 5496 pm_runtime_get_sync(hba->dev);
1ab27c9c 5497 ufshcd_hold(hba, false);
e8e7f271
SRT		 5498
5499 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5500 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5501 goto out;
e8e7f271
SRT		 5502
5503 hba->ufshcd_state = UFSHCD_STATE_RESET;
5504 ufshcd_set_eh_in_progress(hba);
5505
5506 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5507 ufshcd_complete_requests(hba);
583fa62d
YG		 5508
5509 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5510 bool ret;
5511
5512 spin_unlock_irqrestore(hba->host->host_lock, flags);
5513 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5514 ret = ufshcd_quirk_dl_nac_errors(hba);
5515 spin_lock_irqsave(hba->host->host_lock, flags);
5516 if (!ret)
5517 goto skip_err_handling;
5518 }
9a47ec7c 5519 if ((hba->saved_err & INT_FATAL_ERRORS) ||
82174440 5520 (hba->saved_err & UFSHCD_UIC_HIBERN8_MASK) ||
9a47ec7c
YG		 5521 ((hba->saved_err & UIC_ERROR) &&
5522 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5523 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5524 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5525 needs_reset = true;
e8e7f271 5526
9a47ec7c
YG		 5527 /*
5528 * if host reset is required then skip clearing the pending
2df74b69
CG		 5529 * transfers forcefully because they will get cleared during
5530 * host reset and restore
9a47ec7c
YG		 5531 */
5532 if (needs_reset)
5533 goto skip_pending_xfer_clear;
5534
5535 /* release lock as clear command might sleep */
5536 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5537 /* Clear pending transfer requests */
9a47ec7c
YG		 5538 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5539 if (ufshcd_clear_cmd(hba, tag)) {
5540 err_xfer = true;
5541 goto lock_skip_pending_xfer_clear;
5542 }
5543 }
e8e7f271
SRT		 5544
5545 /* Clear pending task management requests */
9a47ec7c
YG		 5546 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5547 if (ufshcd_clear_tm_cmd(hba, tag)) {
5548 err_tm = true;
5549 goto lock_skip_pending_xfer_clear;
5550 }
5551 }
e8e7f271 5552
9a47ec7c 5553lock_skip_pending_xfer_clear:
e8e7f271 5554 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5555
9a47ec7c
YG		 5556 /* Complete the requests that are cleared by s/w */
5557 ufshcd_complete_requests(hba);
5558
5559 if (err_xfer || err_tm)
5560 needs_reset = true;
5561
5562skip_pending_xfer_clear:
e8e7f271 5563 /* Fatal errors need reset */
9a47ec7c
YG		 5564 if (needs_reset) {
5565 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5566
5567 /*
5568 * ufshcd_reset_and_restore() does the link reinitialization
5569 * which will need atleast one empty doorbell slot to send the
5570 * device management commands (NOP and query commands).
5571 * If there is no slot empty at this moment then free up last
5572 * slot forcefully.
5573 */
5574 if (hba->outstanding_reqs == max_doorbells)
5575 __ufshcd_transfer_req_compl(hba,
5576 (1UL << (hba->nutrs - 1)));
5577
5578 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5579 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5580 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5581 if (err) {
5582 dev_err(hba->dev, "%s: reset and restore failed\n",
5583 __func__);
5584 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5585 }
5586 /*
5587 * Inform scsi mid-layer that we did reset and allow to handle
5588 * Unit Attention properly.
5589 */
5590 scsi_report_bus_reset(hba->host, 0);
5591 hba->saved_err = 0;
5592 hba->saved_uic_err = 0;
5593 }
9a47ec7c 5594
583fa62d 5595skip_err_handling:
9a47ec7c
YG		 5596 if (!needs_reset) {
5597 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5598 if (hba->saved_err || hba->saved_uic_err)
5599 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5600 __func__, hba->saved_err, hba->saved_uic_err);
5601 }
5602
e8e7f271
SRT		 5603 ufshcd_clear_eh_in_progress(hba);
5604
5605out:
9a47ec7c 5606 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5607 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5608 ufshcd_release(hba);
62694735 5609 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5610}
5611
5612/**
e8e7f271
SRT		 5613 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5614 * @hba: per-adapter instance
9333d775
VG		 5615 *
5616 * Returns
5617 * IRQ_HANDLED - If interrupt is valid
5618 * IRQ_NONE - If invalid interrupt
7a3e97b0 5619 */
9333d775 5620static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5621{
5622 u32 reg;
9333d775 5623 irqreturn_t retval = IRQ_NONE;
7a3e97b0 5624
fb7b45f0
DR		 5625 /* PHY layer lane error */
5626 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5627 /* Ignore LINERESET indication, as this is not an error */
5628 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
9333d775 5629 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5630 /*
5631 * To know whether this error is fatal or not, DB timeout
5632 * must be checked but this error is handled separately.
5633 */
5634 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
48d5b973 5635 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
9333d775 5636 retval |= IRQ_HANDLED;
ff8e20c6 5637 }
fb7b45f0 5638
e8e7f271
SRT		 5639 /* PA_INIT_ERROR is fatal and needs UIC reset */
5640 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 5641 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
5642 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5643 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
ff8e20c6 5644
9333d775
VG		 5645 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5646 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5647 else if (hba->dev_quirks &
5648 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5649 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5650 hba->uic_error |=
5651 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5652 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5653 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5654 }
5655 retval |= IRQ_HANDLED;
583fa62d 5656 }
e8e7f271
SRT		 5657
5658 /* UIC NL/TL/DME errors needs software retry */
5659 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 5660 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
5661 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5662 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5663 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 5664 retval |= IRQ_HANDLED;
ff8e20c6 5665 }
e8e7f271
SRT		 5666
5667 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 5668 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
5669 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
48d5b973 5670 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5671 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 5672 retval |= IRQ_HANDLED;
ff8e20c6 5673 }
e8e7f271
SRT		 5674
5675 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 5676 if ((reg & UIC_DME_ERROR) &&
5677 (reg & UIC_DME_ERROR_CODE_MASK)) {
48d5b973 5678 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5679 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 5680 retval |= IRQ_HANDLED;
ff8e20c6 5681 }
e8e7f271
SRT		 5682
5683 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5684 __func__, hba->uic_error);
9333d775 5685 return retval;
e8e7f271
SRT		 5686}
5687
82174440
SC		 5688static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5689 u32 intr_mask)
5690{
5a244e0e
SC		 5691 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5692 !ufshcd_is_auto_hibern8_enabled(hba))
82174440
SC		 5693 return false;
5694
5695 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5696 return false;
5697
5698 if (hba->active_uic_cmd &&
5699 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5700 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5701 return false;
5702
5703 return true;
5704}
5705
e8e7f271
SRT		 5706/**
5707 * ufshcd_check_errors - Check for errors that need s/w attention
5708 * @hba: per-adapter instance
9333d775
VG		 5709 *
5710 * Returns
5711 * IRQ_HANDLED - If interrupt is valid
5712 * IRQ_NONE - If invalid interrupt
e8e7f271 5713 */
9333d775 5714static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
e8e7f271
SRT		 5715{
5716 bool queue_eh_work = false;
9333d775 5717 irqreturn_t retval = IRQ_NONE;
e8e7f271 5718
d3c615bf
SC		 5719 if (hba->errors & INT_FATAL_ERRORS) {
5720 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
e8e7f271 5721 queue_eh_work = true;
d3c615bf 5722 }
7a3e97b0
SY		 5723
5724 if (hba->errors & UIC_ERROR) {
e8e7f271 5725 hba->uic_error = 0;
9333d775 5726 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 5727 if (hba->uic_error)
5728 queue_eh_work = true;
7a3e97b0 5729 }
e8e7f271 5730
82174440
SC		 5731 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
5732 dev_err(hba->dev,
5733 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
5734 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
5735 "Enter" : "Exit",
5736 hba->errors, ufshcd_get_upmcrs(hba));
d3c615bf
SC		 5737 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
5738 hba->errors);
82174440
SC		 5739 queue_eh_work = true;
5740 }
5741
e8e7f271 5742 if (queue_eh_work) {
9a47ec7c
YG		 5743 /*
5744 * update the transfer error masks to sticky bits, let's do this
5745 * irrespective of current ufshcd_state.
5746 */
5747 hba->saved_err |= hba->errors;
5748 hba->saved_uic_err |= hba->uic_error;
5749
e8e7f271
SRT		 5750 /* handle fatal errors only when link is functional */
5751 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5752 /* block commands from scsi mid-layer */
38135535 5753 ufshcd_scsi_block_requests(hba);
e8e7f271 5754
141f8165 5755 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5756
5757 /* dump controller state before resetting */
5758 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5759 bool pr_prdt = !!(hba->saved_err &
5760 SYSTEM_BUS_FATAL_ERROR);
5761
5762 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5763 __func__, hba->saved_err,
5764 hba->saved_uic_err);
5765
5766 ufshcd_print_host_regs(hba);
5767 ufshcd_print_pwr_info(hba);
5768 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5769 ufshcd_print_trs(hba, hba->outstanding_reqs,
5770 pr_prdt);
5771 }
e8e7f271
SRT		 5772 schedule_work(&hba->eh_work);
5773 }
9333d775 5774 retval |= IRQ_HANDLED;
3441da7d 5775 }
e8e7f271
SRT		 5776 /*
5777 * if (!queue_eh_work) -
5778 * Other errors are either non-fatal where host recovers
5779 * itself without s/w intervention or errors that will be
5780 * handled by the SCSI core layer.
5781 */
9333d775 5782 return retval;
7a3e97b0
SY		 5783}
5784
69a6c269
BVA		 5785struct ctm_info {
5786 struct ufs_hba *hba;
5787 unsigned long pending;
5788 unsigned int ncpl;
5789};
5790
5791static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
5792{
5793 struct ctm_info *const ci = priv;
5794 struct completion *c;
5795
5796 WARN_ON_ONCE(reserved);
5797 if (test_bit(req->tag, &ci->pending))
5798 return true;
5799 ci->ncpl++;
5800 c = req->end_io_data;
5801 if (c)
5802 complete(c);
5803 return true;
5804}
5805
7a3e97b0
SY		 5806/**
5807 * ufshcd_tmc_handler - handle task management function completion
5808 * @hba: per adapter instance
9333d775
VG		 5809 *
5810 * Returns
5811 * IRQ_HANDLED - If interrupt is valid
5812 * IRQ_NONE - If invalid interrupt
7a3e97b0 5813 */
9333d775 5814static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 5815{
69a6c269
BVA		 5816 struct request_queue *q = hba->tmf_queue;
5817 struct ctm_info ci = {
5818 .hba = hba,
5819 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
5820 };
7a3e97b0 5821
69a6c269
BVA		 5822 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
5823 return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
7a3e97b0
SY		 5824}
5825
5826/**
5827 * ufshcd_sl_intr - Interrupt service routine
5828 * @hba: per adapter instance
5829 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 5830 *
5831 * Returns
5832 * IRQ_HANDLED - If interrupt is valid
5833 * IRQ_NONE - If invalid interrupt
7a3e97b0 5834 */
9333d775 5835static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 5836{
9333d775
VG		 5837 irqreturn_t retval = IRQ_NONE;
5838
7a3e97b0 5839 hba->errors = UFSHCD_ERROR_MASK & intr_status;
82174440
SC		 5840
5841 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5842 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5843
7a3e97b0 5844 if (hba->errors)
9333d775 5845 retval |= ufshcd_check_errors(hba);
7a3e97b0 5846
53b3d9c3 5847 if (intr_status & UFSHCD_UIC_MASK)
9333d775 5848 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5849
5850 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 5851 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 5852
5853 if (intr_status & UTP_TRANSFER_REQ_COMPL)
9333d775
VG		 5854 retval |= ufshcd_transfer_req_compl(hba);
5855
5856 return retval;
7a3e97b0
SY		 5857}
5858
5859/**
5860 * ufshcd_intr - Main interrupt service routine
5861 * @irq: irq number
5862 * @__hba: pointer to adapter instance
5863 *
9333d775
VG		 5864 * Returns
5865 * IRQ_HANDLED - If interrupt is valid
5866 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 5867 */
5868static irqreturn_t ufshcd_intr(int irq, void *__hba)
5869{
d75f7fe4 5870 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5871 irqreturn_t retval = IRQ_NONE;
5872 struct ufs_hba *hba = __hba;
7f6ba4f1 5873 int retries = hba->nutrs;
7a3e97b0
SY		 5874
5875 spin_lock(hba->host->host_lock);
b873a275 5876 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5877
7f6ba4f1
VG		 5878 /*
5879 * There could be max of hba->nutrs reqs in flight and in worst case
5880 * if the reqs get finished 1 by 1 after the interrupt status is
5881 * read, make sure we handle them by checking the interrupt status
5882 * again in a loop until we process all of the reqs before returning.
5883 */
5884 do {
5885 enabled_intr_status =
5886 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5887 if (intr_status)
5888 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 5889 if (enabled_intr_status)
5890 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 5891
5892 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5893 } while (intr_status && --retries);
d75f7fe4 5894
9333d775
VG		 5895 if (retval == IRQ_NONE) {
5896 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
5897 __func__, intr_status);
5898 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
5899 }
5900
7a3e97b0
SY		 5901 spin_unlock(hba->host->host_lock);
5902 return retval;
5903}
5904
e2933132
SRT		 5905static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5906{
5907 int err = 0;
5908 u32 mask = 1 << tag;
5909 unsigned long flags;
5910
5911 if (!test_bit(tag, &hba->outstanding_tasks))
5912 goto out;
5913
5914 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5915 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5916 spin_unlock_irqrestore(hba->host->host_lock, flags);
5917
5918 /* poll for max. 1 sec to clear door bell register by h/w */
5919 err = ufshcd_wait_for_register(hba,
5920 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5921 mask, 0, 1000, 1000, true);
e2933132
SRT		 5922out:
5923 return err;
5924}
5925
c6049cd9
CH		 5926static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5927 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5928{
69a6c269 5929 struct request_queue *q = hba->tmf_queue;
c6049cd9 5930 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 5931 DECLARE_COMPLETION_ONSTACK(wait);
5932 struct request *req;
7a3e97b0 5933 unsigned long flags;
c6049cd9 5934 int free_slot, task_tag, err;
7a3e97b0 5935
e2933132
SRT		 5936 /*
5937 * Get free slot, sleep if slots are unavailable.
5938 * Even though we use wait_event() which sleeps indefinitely,
5939 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5940 */
69a6c269
BVA		 5941 req = blk_get_request(q, REQ_OP_DRV_OUT, BLK_MQ_REQ_RESERVED);
5942 req->end_io_data = &wait;
5943 free_slot = req->tag;
5944 WARN_ON_ONCE(free_slot < 0 || free_slot >= hba->nutmrs);
1ab27c9c 5945 ufshcd_hold(hba, false);
7a3e97b0 5946
e2933132 5947 spin_lock_irqsave(host->host_lock, flags);
e2933132 5948 task_tag = hba->nutrs + free_slot;
7a3e97b0 5949
c6049cd9
CH		 5950 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5951
5952 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5953 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5954
7a3e97b0
SY		 5955 /* send command to the controller */
5956 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5957
5958 /* Make sure descriptors are ready before ringing the task doorbell */
5959 wmb();
5960
b873a275 5961 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5962 /* Make sure that doorbell is committed immediately */
5963 wmb();
7a3e97b0
SY		 5964
5965 spin_unlock_irqrestore(host->host_lock, flags);
5966
6667e6d9
OS		 5967 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5968
7a3e97b0 5969 /* wait until the task management command is completed */
69a6c269 5970 err = wait_for_completion_io_timeout(&wait,
e2933132 5971 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5972 if (!err) {
69a6c269
BVA		 5973 /*
5974 * Make sure that ufshcd_compl_tm() does not trigger a
5975 * use-after-free.
5976 */
5977 req->end_io_data = NULL;
6667e6d9 5978 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5979 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5980 __func__, tm_function);
5981 if (ufshcd_clear_tm_cmd(hba, free_slot))
5982 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5983 __func__, free_slot);
5984 err = -ETIMEDOUT;
5985 } else {
c6049cd9
CH		 5986 err = 0;
5987 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5988
6667e6d9 5989 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
7a3e97b0 5990 }
e2933132 5991
b557217c
SC		 5992 spin_lock_irqsave(hba->host->host_lock, flags);
5993 __clear_bit(free_slot, &hba->outstanding_tasks);
5994 spin_unlock_irqrestore(hba->host->host_lock, flags);
5995
69a6c269 5996 blk_put_request(req);
e2933132 5997
1ab27c9c 5998 ufshcd_release(hba);
7a3e97b0
SY		 5999 return err;
6000}
6001
c6049cd9
CH		 6002/**
6003 * ufshcd_issue_tm_cmd - issues task management commands to controller
6004 * @hba: per adapter instance
6005 * @lun_id: LUN ID to which TM command is sent
6006 * @task_id: task ID to which the TM command is applicable
6007 * @tm_function: task management function opcode
6008 * @tm_response: task management service response return value
6009 *
6010 * Returns non-zero value on error, zero on success.
6011 */
6012static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6013 u8 tm_function, u8 *tm_response)
6014{
6015 struct utp_task_req_desc treq = { { 0 }, };
6016 int ocs_value, err;
6017
6018 /* Configure task request descriptor */
6019 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6020 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6021
6022 /* Configure task request UPIU */
6023 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6024 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6025 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6026
6027 /*
6028 * The host shall provide the same value for LUN field in the basic
6029 * header and for Input Parameter.
6030 */
6031 treq.input_param1 = cpu_to_be32(lun_id);
6032 treq.input_param2 = cpu_to_be32(task_id);
6033
6034 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6035 if (err == -ETIMEDOUT)
6036 return err;
6037
6038 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6039 if (ocs_value != OCS_SUCCESS)
6040 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6041 __func__, ocs_value);
6042 else if (tm_response)
6043 *tm_response = be32_to_cpu(treq.output_param1) &
6044 MASK_TM_SERVICE_RESP;
6045 return err;
6046}
6047
5e0a86ee
AA		 6048/**
6049 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6050 * @hba: per-adapter instance
6051 * @req_upiu: upiu request
6052 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6053 * @desc_buff: pointer to descriptor buffer, NULL if NA
6054 * @buff_len: descriptor size, 0 if NA
d0e9760d 6055 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6056 * @desc_op: descriptor operation
6057 *
6058 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6059 * Therefore, it "rides" the device management infrastructure: uses its tag and
6060 * tasks work queues.
6061 *
6062 * Since there is only one available tag for device management commands,
6063 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6064 */
6065static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6066 struct utp_upiu_req *req_upiu,
6067 struct utp_upiu_req *rsp_upiu,
6068 u8 *desc_buff, int *buff_len,
7f674c38 6069 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6070 enum query_opcode desc_op)
6071{
7252a360
BVA		 6072 struct request_queue *q = hba->cmd_queue;
6073 struct request *req;
5e0a86ee
AA		 6074 struct ufshcd_lrb *lrbp;
6075 int err = 0;
6076 int tag;
6077 struct completion wait;
6078 unsigned long flags;
6079 u32 upiu_flags;
6080
6081 down_read(&hba->clk_scaling_lock);
6082
7252a360 6083 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 6084 if (IS_ERR(req)) {
6085 err = PTR_ERR(req);
6086 goto out_unlock;
6087 }
7252a360
BVA		 6088 tag = req->tag;
6089 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5e0a86ee
AA		 6090
6091 init_completion(&wait);
6092 lrbp = &hba->lrb[tag];
6093 WARN_ON(lrbp->cmd);
6094
6095 lrbp->cmd = NULL;
6096 lrbp->sense_bufflen = 0;
6097 lrbp->sense_buffer = NULL;
6098 lrbp->task_tag = tag;
6099 lrbp->lun = 0;
6100 lrbp->intr_cmd = true;
6101 hba->dev_cmd.type = cmd_type;
6102
6103 switch (hba->ufs_version) {
6104 case UFSHCI_VERSION_10:
6105 case UFSHCI_VERSION_11:
6106 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6107 break;
6108 default:
6109 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6110 break;
6111 }
6112
6113 /* update the task tag in the request upiu */
6114 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6115
6116 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6117
6118 /* just copy the upiu request as it is */
6119 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6120 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6121 /* The Data Segment Area is optional depending upon the query
6122 * function value. for WRITE DESCRIPTOR, the data segment
6123 * follows right after the tsf.
6124 */
6125 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6126 *buff_len = 0;
6127 }
6128
6129 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6130
6131 hba->dev_cmd.complete = &wait;
6132
6133 /* Make sure descriptors are ready before ringing the doorbell */
6134 wmb();
6135 spin_lock_irqsave(hba->host->host_lock, flags);
6136 ufshcd_send_command(hba, tag);
6137 spin_unlock_irqrestore(hba->host->host_lock, flags);
6138
6139 /*
6140 * ignore the returning value here - ufshcd_check_query_response is
6141 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6142 * read the response directly ignoring all errors.
6143 */
6144 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6145
6146 /* just copy the upiu response as it is */
6147 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6148 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6149 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6150 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6151 MASK_QUERY_DATA_SEG_LEN;
6152
6153 if (*buff_len >= resp_len) {
6154 memcpy(desc_buff, descp, resp_len);
6155 *buff_len = resp_len;
6156 } else {
3d4881d1
BH		 6157 dev_warn(hba->dev,
6158 "%s: rsp size %d is bigger than buffer size %d",
6159 __func__, resp_len, *buff_len);
4bbbe242
AA		 6160 *buff_len = 0;
6161 err = -EINVAL;
6162 }
6163 }
5e0a86ee 6164
7252a360 6165 blk_put_request(req);
bb14dd15 6166out_unlock:
5e0a86ee
AA		 6167 up_read(&hba->clk_scaling_lock);
6168 return err;
6169}
6170
6171/**
6172 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6173 * @hba: per-adapter instance
6174 * @req_upiu: upiu request
6175 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6176 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6177 * @desc_buff: pointer to descriptor buffer, NULL if NA
6178 * @buff_len: descriptor size, 0 if NA
6179 * @desc_op: descriptor operation
6180 *
6181 * Supports UTP Transfer requests (nop and query), and UTP Task
6182 * Management requests.
6183 * It is up to the caller to fill the upiu conent properly, as it will
6184 * be copied without any further input validations.
6185 */
6186int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6187 struct utp_upiu_req *req_upiu,
6188 struct utp_upiu_req *rsp_upiu,
6189 int msgcode,
6190 u8 *desc_buff, int *buff_len,
6191 enum query_opcode desc_op)
6192{
6193 int err;
7f674c38 6194 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee
AA		 6195 struct utp_task_req_desc treq = { { 0 }, };
6196 int ocs_value;
6197 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6198
5e0a86ee
AA		 6199 switch (msgcode) {
6200 case UPIU_TRANSACTION_NOP_OUT:
6201 cmd_type = DEV_CMD_TYPE_NOP;
6202 /* fall through */
6203 case UPIU_TRANSACTION_QUERY_REQ:
6204 ufshcd_hold(hba, false);
6205 mutex_lock(&hba->dev_cmd.lock);
6206 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6207 desc_buff, buff_len,
6208 cmd_type, desc_op);
6209 mutex_unlock(&hba->dev_cmd.lock);
6210 ufshcd_release(hba);
6211
6212 break;
6213 case UPIU_TRANSACTION_TASK_REQ:
6214 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6215 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6216
6217 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
6218
6219 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6220 if (err == -ETIMEDOUT)
6221 break;
6222
6223 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6224 if (ocs_value != OCS_SUCCESS) {
6225 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6226 ocs_value);
6227 break;
6228 }
6229
6230 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
6231
6232 break;
6233 default:
6234 err = -EINVAL;
6235
6236 break;
6237 }
6238
5e0a86ee
AA		 6239 return err;
6240}
6241
7a3e97b0 6242/**
3441da7d
SRT		 6243 * ufshcd_eh_device_reset_handler - device reset handler registered to
6244 * scsi layer.
7a3e97b0
SY		 6245 * @cmd: SCSI command pointer
6246 *
6247 * Returns SUCCESS/FAILED
6248 */
3441da7d 6249static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6250{
6251 struct Scsi_Host *host;
6252 struct ufs_hba *hba;
6253 unsigned int tag;
6254 u32 pos;
6255 int err;
e2933132
SRT		 6256 u8 resp = 0xF;
6257 struct ufshcd_lrb *lrbp;
3441da7d 6258 unsigned long flags;
7a3e97b0
SY		 6259
6260 host = cmd->device->host;
6261 hba = shost_priv(host);
6262 tag = cmd->request->tag;
6263
e2933132
SRT		 6264 lrbp = &hba->lrb[tag];
6265 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
6266 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6267 if (!err)
6268 err = resp;
7a3e97b0 6269 goto out;
e2933132 6270 }
7a3e97b0 6271
3441da7d
SRT		 6272 /* clear the commands that were pending for corresponding LUN */
6273 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6274 if (hba->lrb[pos].lun == lrbp->lun) {
6275 err = ufshcd_clear_cmd(hba, pos);
6276 if (err)
6277 break;
7a3e97b0 6278 }
3441da7d
SRT		 6279 }
6280 spin_lock_irqsave(host->host_lock, flags);
6281 ufshcd_transfer_req_compl(hba);
6282 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 6283
7a3e97b0 6284out:
7fabb77b 6285 hba->req_abort_count = 0;
8808b4e9 6286 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
3441da7d
SRT		 6287 if (!err) {
6288 err = SUCCESS;
6289 } else {
6290 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6291 err = FAILED;
6292 }
7a3e97b0
SY		 6293 return err;
6294}
6295
e0b299e3
GB		 6296static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6297{
6298 struct ufshcd_lrb *lrbp;
6299 int tag;
6300
6301 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6302 lrbp = &hba->lrb[tag];
6303 lrbp->req_abort_skip = true;
6304 }
6305}
6306
7a3e97b0
SY		 6307/**
6308 * ufshcd_abort - abort a specific command
6309 * @cmd: SCSI command pointer
6310 *
f20810d8
SRT		 6311 * Abort the pending command in device by sending UFS_ABORT_TASK task management
6312 * command, and in host controller by clearing the door-bell register. There can
6313 * be race between controller sending the command to the device while abort is
6314 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6315 * really issued and then try to abort it.
6316 *
7a3e97b0
SY		 6317 * Returns SUCCESS/FAILED
6318 */
6319static int ufshcd_abort(struct scsi_cmnd *cmd)
6320{
6321 struct Scsi_Host *host;
6322 struct ufs_hba *hba;
6323 unsigned long flags;
6324 unsigned int tag;
f20810d8
SRT		 6325 int err = 0;
6326 int poll_cnt;
e2933132
SRT		 6327 u8 resp = 0xF;
6328 struct ufshcd_lrb *lrbp;
e9d501b1 6329 u32 reg;
7a3e97b0
SY		 6330
6331 host = cmd->device->host;
6332 hba = shost_priv(host);
6333 tag = cmd->request->tag;
e7d38257 6334 lrbp = &hba->lrb[tag];
14497328
YG		 6335 if (!ufshcd_valid_tag(hba, tag)) {
6336 dev_err(hba->dev,
6337 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6338 __func__, tag, cmd, cmd->request);
6339 BUG();
6340 }
7a3e97b0 6341
e7d38257
DR		 6342 /*
6343 * Task abort to the device W-LUN is illegal. When this command
6344 * will fail, due to spec violation, scsi err handling next step
6345 * will be to send LU reset which, again, is a spec violation.
6346 * To avoid these unnecessary/illegal step we skip to the last error
6347 * handling stage: reset and restore.
6348 */
6349 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6350 return ufshcd_eh_host_reset_handler(cmd);
6351
1ab27c9c 6352 ufshcd_hold(hba, false);
14497328 6353 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 6354 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 6355 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6356 dev_err(hba->dev,
6357 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6358 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 6359 goto out;
14497328 6360 }
7a3e97b0 6361
e9d501b1
DR		 6362 if (!(reg & (1 << tag))) {
6363 dev_err(hba->dev,
6364 "%s: cmd was completed, but without a notifying intr, tag = %d",
6365 __func__, tag);
6366 }
6367
66cc820f
DR		 6368 /* Print Transfer Request of aborted task */
6369 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 6370
7fabb77b
GB		 6371 /*
6372 * Print detailed info about aborted request.
6373 * As more than one request might get aborted at the same time,
6374 * print full information only for the first aborted request in order
6375 * to reduce repeated printouts. For other aborted requests only print
6376 * basic details.
6377 */
6378 scsi_print_command(hba->lrb[tag].cmd);
6379 if (!hba->req_abort_count) {
8808b4e9 6380 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
7fabb77b 6381 ufshcd_print_host_regs(hba);
6ba65588 6382 ufshcd_print_host_state(hba);
7fabb77b
GB		 6383 ufshcd_print_pwr_info(hba);
6384 ufshcd_print_trs(hba, 1 << tag, true);
6385 } else {
6386 ufshcd_print_trs(hba, 1 << tag, false);
6387 }
6388 hba->req_abort_count++;
e0b299e3
GB		 6389
6390 /* Skip task abort in case previous aborts failed and report failure */
6391 if (lrbp->req_abort_skip) {
6392 err = -EIO;
6393 goto out;
6394 }
6395
f20810d8
SRT		 6396 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6397 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6398 UFS_QUERY_TASK, &resp);
6399 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6400 /* cmd pending in the device */
ff8e20c6
DR		 6401 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6402 __func__, tag);
f20810d8
SRT		 6403 break;
6404 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6405 /*
6406 * cmd not pending in the device, check if it is
6407 * in transition.
6408 */
ff8e20c6
DR		 6409 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6410 __func__, tag);
f20810d8
SRT		 6411 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6412 if (reg & (1 << tag)) {
6413 /* sleep for max. 200us to stabilize */
6414 usleep_range(100, 200);
6415 continue;
6416 }
6417 /* command completed already */
ff8e20c6
DR		 6418 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6419 __func__, tag);
f20810d8
SRT		 6420 goto out;
6421 } else {
ff8e20c6
DR		 6422 dev_err(hba->dev,
6423 "%s: no response from device. tag = %d, err %d\n",
6424 __func__, tag, err);
f20810d8
SRT		 6425 if (!err)
6426 err = resp; /* service response error */
6427 goto out;
6428 }
6429 }
6430
6431 if (!poll_cnt) {
6432 err = -EBUSY;
7a3e97b0
SY		 6433 goto out;
6434 }
7a3e97b0 6435
e2933132
SRT		 6436 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6437 UFS_ABORT_TASK, &resp);
6438 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6439 if (!err) {
f20810d8 6440 err = resp; /* service response error */
ff8e20c6
DR		 6441 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6442 __func__, tag, err);
6443 }
7a3e97b0 6444 goto out;
e2933132 6445 }
7a3e97b0 6446
f20810d8 6447 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6448 if (err) {
6449 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6450 __func__, tag, err);
f20810d8 6451 goto out;
ff8e20c6 6452 }
f20810d8 6453
7a3e97b0
SY		 6454 scsi_dma_unmap(cmd);
6455
6456 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6457 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6458 hba->lrb[tag].cmd = NULL;
6459 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9 6460
7a3e97b0 6461out:
f20810d8
SRT		 6462 if (!err) {
6463 err = SUCCESS;
6464 } else {
6465 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6466 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6467 err = FAILED;
6468 }
6469
1ab27c9c
ST		 6470 /*
6471 * This ufshcd_release() corresponds to the original scsi cmd that got
6472 * aborted here (as we won't get any IRQ for it).
6473 */
6474 ufshcd_release(hba);
7a3e97b0
SY		 6475 return err;
6476}
6477
3441da7d
SRT		 6478/**
6479 * ufshcd_host_reset_and_restore - reset and restore host controller
6480 * @hba: per-adapter instance
6481 *
6482 * Note that host controller reset may issue DME_RESET to
6483 * local and remote (device) Uni-Pro stack and the attributes
6484 * are reset to default state.
6485 *
6486 * Returns zero on success, non-zero on failure
6487 */
6488static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6489{
6490 int err;
3441da7d
SRT		 6491 unsigned long flags;
6492
2df74b69
CG		 6493 /*
6494 * Stop the host controller and complete the requests
6495 * cleared by h/w
6496 */
3441da7d 6497 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 6498 ufshcd_hba_stop(hba, false);
2df74b69
CG		 6499 hba->silence_err_logs = true;
6500 ufshcd_complete_requests(hba);
6501 hba->silence_err_logs = false;
3441da7d
SRT		 6502 spin_unlock_irqrestore(hba->host->host_lock, flags);
6503
a3cd5ec5 6504 /* scale up clocks to max frequency before full reinitialization */
394b949f 6505 ufshcd_set_clk_freq(hba, true);
a3cd5ec5 6506
3441da7d
SRT		 6507 err = ufshcd_hba_enable(hba);
6508 if (err)
6509 goto out;
6510
6511 /* Establish the link again and restore the device */
1b9e2141 6512 err = ufshcd_probe_hba(hba, false);
1d337ec2
SRT		 6513
6514 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 6515 err = -EIO;
6516out:
6517 if (err)
6518 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
8808b4e9 6519 ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
3441da7d
SRT		 6520 return err;
6521}
6522
6523/**
6524 * ufshcd_reset_and_restore - reset and re-initialize host/device
6525 * @hba: per-adapter instance
6526 *
6527 * Reset and recover device, host and re-establish link. This
6528 * is helpful to recover the communication in fatal error conditions.
6529 *
6530 * Returns zero on success, non-zero on failure
6531 */
6532static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6533{
6534 int err = 0;
1d337ec2 6535 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6536
1d337ec2 6537 do {
d8d9f793
BA		 6538 /* Reset the attached device */
6539 ufshcd_vops_device_reset(hba);
6540
1d337ec2
SRT		 6541 err = ufshcd_host_reset_and_restore(hba);
6542 } while (err && --retries);
3441da7d 6543
3441da7d
SRT		 6544 return err;
6545}
6546
6547/**
6548 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6549 * @cmd: SCSI command pointer
3441da7d
SRT		 6550 *
6551 * Returns SUCCESS/FAILED
6552 */
6553static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6554{
6555 int err;
6556 unsigned long flags;
6557 struct ufs_hba *hba;
6558
6559 hba = shost_priv(cmd->device->host);
6560
1ab27c9c 6561 ufshcd_hold(hba, false);
3441da7d
SRT		 6562 /*
6563 * Check if there is any race with fatal error handling.
6564 * If so, wait for it to complete. Even though fatal error
6565 * handling does reset and restore in some cases, don't assume
6566 * anything out of it. We are just avoiding race here.
6567 */
6568 do {
6569 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6570 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6571 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6572 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6573 break;
6574 spin_unlock_irqrestore(hba->host->host_lock, flags);
6575 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6576 flush_work(&hba->eh_work);
3441da7d
SRT		 6577 } while (1);
6578
6579 hba->ufshcd_state = UFSHCD_STATE_RESET;
6580 ufshcd_set_eh_in_progress(hba);
6581 spin_unlock_irqrestore(hba->host->host_lock, flags);
6582
6583 err = ufshcd_reset_and_restore(hba);
6584
6585 spin_lock_irqsave(hba->host->host_lock, flags);
6586 if (!err) {
6587 err = SUCCESS;
6588 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6589 } else {
6590 err = FAILED;
6591 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6592 }
6593 ufshcd_clear_eh_in_progress(hba);
6594 spin_unlock_irqrestore(hba->host->host_lock, flags);
6595
1ab27c9c 6596 ufshcd_release(hba);
3441da7d
SRT		 6597 return err;
6598}
6599
3a4bf06d
YG		 6600/**
6601 * ufshcd_get_max_icc_level - calculate the ICC level
6602 * @sup_curr_uA: max. current supported by the regulator
6603 * @start_scan: row at the desc table to start scan from
6604 * @buff: power descriptor buffer
6605 *
6606 * Returns calculated max ICC level for specific regulator
6607 */
6608static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6609{
6610 int i;
6611 int curr_uA;
6612 u16 data;
6613 u16 unit;
6614
6615 for (i = start_scan; i >= 0; i--) {
d79713f9 6616 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6617 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6618 ATTR_ICC_LVL_UNIT_OFFSET;
6619 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6620 switch (unit) {
6621 case UFSHCD_NANO_AMP:
6622 curr_uA = curr_uA / 1000;
6623 break;
6624 case UFSHCD_MILI_AMP:
6625 curr_uA = curr_uA * 1000;
6626 break;
6627 case UFSHCD_AMP:
6628 curr_uA = curr_uA * 1000 * 1000;
6629 break;
6630 case UFSHCD_MICRO_AMP:
6631 default:
6632 break;
6633 }
6634 if (sup_curr_uA >= curr_uA)
6635 break;
6636 }
6637 if (i < 0) {
6638 i = 0;
6639 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6640 }
6641
6642 return (u32)i;
6643}
6644
6645/**
6646 * ufshcd_calc_icc_level - calculate the max ICC level
6647 * In case regulators are not initialized we'll return 0
6648 * @hba: per-adapter instance
6649 * @desc_buf: power descriptor buffer to extract ICC levels from.
6650 * @len: length of desc_buff
6651 *
6652 * Returns calculated ICC level
6653 */
6654static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6655 u8 *desc_buf, int len)
6656{
6657 u32 icc_level = 0;
6658
6659 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6660 !hba->vreg_info.vccq2) {
6661 dev_err(hba->dev,
6662 "%s: Regulator capability was not set, actvIccLevel=%d",
6663 __func__, icc_level);
6664 goto out;
6665 }
6666
0487fff7 6667 if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 6668 icc_level = ufshcd_get_max_icc_level(
6669 hba->vreg_info.vcc->max_uA,
6670 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6671 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6672
0487fff7 6673 if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 6674 icc_level = ufshcd_get_max_icc_level(
6675 hba->vreg_info.vccq->max_uA,
6676 icc_level,
6677 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6678
0487fff7 6679 if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 6680 icc_level = ufshcd_get_max_icc_level(
6681 hba->vreg_info.vccq2->max_uA,
6682 icc_level,
6683 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6684out:
6685 return icc_level;
6686}
6687
e89860f1 6688static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 6689{
6690 int ret;
a4b0e8a4 6691 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a 6692 u8 *desc_buf;
e89860f1 6693 u32 icc_level;
bbe21d7a
KC		 6694
6695 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6696 if (!desc_buf)
6697 return;
3a4bf06d 6698
8c9a51b0
BH		 6699 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0,
6700 desc_buf, buff_len);
3a4bf06d
YG		 6701 if (ret) {
6702 dev_err(hba->dev,
6703 "%s: Failed reading power descriptor.len = %d ret = %d",
6704 __func__, buff_len, ret);
bbe21d7a 6705 goto out;
3a4bf06d
YG		 6706 }
6707
e89860f1
CG		 6708 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
6709 buff_len);
6710 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 6711
dbd34a61 6712 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 6713 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 6714
6715 if (ret)
6716 dev_err(hba->dev,
6717 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 6718 __func__, icc_level, ret);
3a4bf06d 6719
bbe21d7a
KC		 6720out:
6721 kfree(desc_buf);
3a4bf06d
YG		 6722}
6723
fb276f77
CG		 6724static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
6725{
6726 scsi_autopm_get_device(sdev);
6727 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
6728 if (sdev->rpm_autosuspend)
6729 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
6730 RPM_AUTOSUSPEND_DELAY_MS);
6731 scsi_autopm_put_device(sdev);
6732}
6733
2a8fa600
SJ		 6734/**
6735 * ufshcd_scsi_add_wlus - Adds required W-LUs
6736 * @hba: per-adapter instance
6737 *
6738 * UFS device specification requires the UFS devices to support 4 well known
6739 * logical units:
6740 * "REPORT_LUNS" (address: 01h)
6741 * "UFS Device" (address: 50h)
6742 * "RPMB" (address: 44h)
6743 * "BOOT" (address: 30h)
6744 * UFS device's power management needs to be controlled by "POWER CONDITION"
6745 * field of SSU (START STOP UNIT) command. But this "power condition" field
6746 * will take effect only when its sent to "UFS device" well known logical unit
6747 * hence we require the scsi_device instance to represent this logical unit in
6748 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6749 *
2a8fa600
SJ		 6750 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6751 * Block) LU so user space process can control this LU. User space may also
6752 * want to have access to BOOT LU.
8aa29f19 6753 *
2a8fa600
SJ		 6754 * This function adds scsi device instances for each of all well known LUs
6755 * (except "REPORT LUNS" LU).
6756 *
6757 * Returns zero on success (all required W-LUs are added successfully),
6758 * non-zero error value on failure (if failed to add any of the required W-LU).
6759 */
6760static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6761{
6762 int ret = 0;
7c48bfd0
AM		 6763 struct scsi_device *sdev_rpmb;
6764 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6765
6766 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6767 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6768 if (IS_ERR(hba->sdev_ufs_device)) {
6769 ret = PTR_ERR(hba->sdev_ufs_device);
6770 hba->sdev_ufs_device = NULL;
6771 goto out;
6772 }
fb276f77 6773 ufshcd_blk_pm_runtime_init(hba->sdev_ufs_device);
7c48bfd0 6774 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6775
7c48bfd0 6776 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6777 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6778 if (IS_ERR(sdev_rpmb)) {
6779 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6780 goto remove_sdev_ufs_device;
2a8fa600 6781 }
fb276f77 6782 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7c48bfd0 6783 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6784
6785 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6786 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 6787 if (IS_ERR(sdev_boot)) {
3d21fbde 6788 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 6789 } else {
6790 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 6791 scsi_device_put(sdev_boot);
fb276f77 6792 }
2a8fa600
SJ		 6793 goto out;
6794
2a8fa600
SJ		 6795remove_sdev_ufs_device:
6796 scsi_remove_device(hba->sdev_ufs_device);
6797out:
6798 return ret;
6799}
6800
3d17b9b5
AD		 6801static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
6802{
6803 hba->dev_info.d_ext_ufs_feature_sup =
6804 get_unaligned_be32(desc_buf +
6805 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
6806 /*
6807 * WB may be supported but not configured while provisioning.
6808 * The spec says, in dedicated wb buffer mode,
6809 * a max of 1 lun would have wb buffer configured.
6810 * Now only shared buffer mode is supported.
6811 */
6812 hba->dev_info.b_wb_buffer_type =
6813 desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
6814
6815 hba->dev_info.d_wb_alloc_units =
6816 get_unaligned_be32(desc_buf +
6817 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS);
6818 hba->dev_info.b_presrv_uspc_en =
6819 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
6820
6821 if (!((hba->dev_info.d_ext_ufs_feature_sup &
6822 UFS_DEV_WRITE_BOOSTER_SUP) &&
6823 hba->dev_info.b_wb_buffer_type &&
6824 hba->dev_info.d_wb_alloc_units))
6825 hba->caps &= ~UFSHCD_CAP_WB_EN;
6826}
6827
09750066 6828static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 6829{
6830 int err;
bbe21d7a 6831 size_t buff_len;
c58ab7aa 6832 u8 model_index;
bbe21d7a 6833 u8 *desc_buf;
09750066 6834 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 6835
bbe21d7a
KC		 6836 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6837 QUERY_DESC_MAX_SIZE + 1);
6838 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6839 if (!desc_buf) {
6840 err = -ENOMEM;
6841 goto out;
6842 }
c58ab7aa 6843
8c9a51b0
BH		 6844 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, desc_buf,
6845 hba->desc_size.dev_desc);
c58ab7aa
YG		 6846 if (err) {
6847 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6848 __func__, err);
6849 goto out;
6850 }
6851
6852 /*
6853 * getting vendor (manufacturerID) and Bank Index in big endian
6854 * format
6855 */
09750066 6856 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6857 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6858
09f17791
CG		 6859 /* getting Specification Version in big endian format */
6860 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
6861 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
6862
c58ab7aa 6863 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5
AD		 6864
6865 /* Enable WB only for UFS-3.1 */
6866 if (dev_info->wspecversion >= 0x310)
6867 ufshcd_wb_probe(hba, desc_buf);
6868
4b828fe1 6869 err = ufshcd_read_string_desc(hba, model_index,
09750066 6870 &dev_info->model, SD_ASCII_STD);
4b828fe1 6871 if (err < 0) {
c58ab7aa
YG		 6872 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6873 __func__, err);
6874 goto out;
6875 }
6876
4b828fe1
TW		 6877 /*
6878 * ufshcd_read_string_desc returns size of the string
6879 * reset the error value
6880 */
6881 err = 0;
c58ab7aa
YG		 6882
6883out:
bbe21d7a 6884 kfree(desc_buf);
c58ab7aa
YG		 6885 return err;
6886}
6887
09750066 6888static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 6889{
09750066
BH		 6890 struct ufs_dev_info *dev_info = &hba->dev_info;
6891
6892 kfree(dev_info->model);
6893 dev_info->model = NULL;
4b828fe1
TW		 6894}
6895
09750066 6896static void ufs_fixup_device_setup(struct ufs_hba *hba)
c58ab7aa 6897{
c58ab7aa 6898 struct ufs_dev_fix *f;
09750066 6899 struct ufs_dev_info *dev_info = &hba->dev_info;
c58ab7aa
YG		 6900
6901 for (f = ufs_fixups; f->quirk; f++) {
09750066
BH		 6902 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
6903 f->wmanufacturerid == UFS_ANY_VENDOR) &&
6904 ((dev_info->model &&
6905 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
6906 !strcmp(f->model, UFS_ANY_MODEL)))
c58ab7aa
YG		 6907 hba->dev_quirks |= f->quirk;
6908 }
6909}
6910
37113106
YG		 6911/**
6912 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6913 * @hba: per-adapter instance
6914 *
6915 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6916 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6917 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6918 * the hibern8 exit latency.
6919 *
6920 * Returns zero on success, non-zero error value on failure.
6921 */
6922static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6923{
6924 int ret = 0;
6925 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6926
6927 ret = ufshcd_dme_peer_get(hba,
6928 UIC_ARG_MIB_SEL(
6929 RX_MIN_ACTIVATETIME_CAPABILITY,
6930 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6931 &peer_rx_min_activatetime);
6932 if (ret)
6933 goto out;
6934
6935 /* make sure proper unit conversion is applied */
6936 tuned_pa_tactivate =
6937 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6938 / PA_TACTIVATE_TIME_UNIT_US);
6939 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6940 tuned_pa_tactivate);
6941
6942out:
6943 return ret;
6944}
6945
6946/**
6947 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6948 * @hba: per-adapter instance
6949 *
6950 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6951 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6952 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6953 * This optimal value can help reduce the hibern8 exit latency.
6954 *
6955 * Returns zero on success, non-zero error value on failure.
6956 */
6957static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6958{
6959 int ret = 0;
6960 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6961 u32 max_hibern8_time, tuned_pa_hibern8time;
6962
6963 ret = ufshcd_dme_get(hba,
6964 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6965 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6966 &local_tx_hibern8_time_cap);
6967 if (ret)
6968 goto out;
6969
6970 ret = ufshcd_dme_peer_get(hba,
6971 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6972 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6973 &peer_rx_hibern8_time_cap);
6974 if (ret)
6975 goto out;
6976
6977 max_hibern8_time = max(local_tx_hibern8_time_cap,
6978 peer_rx_hibern8_time_cap);
6979 /* make sure proper unit conversion is applied */
6980 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6981 / PA_HIBERN8_TIME_UNIT_US);
6982 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6983 tuned_pa_hibern8time);
6984out:
6985 return ret;
6986}
6987
c6a6db43 6988/**
6989 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6990 * less than device PA_TACTIVATE time.
6991 * @hba: per-adapter instance
6992 *
6993 * Some UFS devices require host PA_TACTIVATE to be lower than device
6994 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6995 * for such devices.
6996 *
6997 * Returns zero on success, non-zero error value on failure.
6998 */
6999static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7000{
7001 int ret = 0;
7002 u32 granularity, peer_granularity;
7003 u32 pa_tactivate, peer_pa_tactivate;
7004 u32 pa_tactivate_us, peer_pa_tactivate_us;
7005 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7006
7007 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7008 &granularity);
7009 if (ret)
7010 goto out;
7011
7012 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7013 &peer_granularity);
7014 if (ret)
7015 goto out;
7016
7017 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7018 (granularity > PA_GRANULARITY_MAX_VAL)) {
7019 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7020 __func__, granularity);
7021 return -EINVAL;
7022 }
7023
7024 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7025 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7026 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7027 __func__, peer_granularity);
7028 return -EINVAL;
7029 }
7030
7031 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7032 if (ret)
7033 goto out;
7034
7035 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7036 &peer_pa_tactivate);
7037 if (ret)
7038 goto out;
7039
7040 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7041 peer_pa_tactivate_us = peer_pa_tactivate *
7042 gran_to_us_table[peer_granularity - 1];
7043
7044 if (pa_tactivate_us > peer_pa_tactivate_us) {
7045 u32 new_peer_pa_tactivate;
7046
7047 new_peer_pa_tactivate = pa_tactivate_us /
7048 gran_to_us_table[peer_granularity - 1];
7049 new_peer_pa_tactivate++;
7050 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7051 new_peer_pa_tactivate);
7052 }
7053
7054out:
7055 return ret;
7056}
7057
09750066 7058static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 7059{
7060 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7061 ufshcd_tune_pa_tactivate(hba);
7062 ufshcd_tune_pa_hibern8time(hba);
7063 }
7064
e91ed9e0
CG		 7065 ufshcd_vops_apply_dev_quirks(hba);
7066
37113106
YG		 7067 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7068 /* set 1ms timeout for PA_TACTIVATE */
7069 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 7070
7071 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7072 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 7073}
7074
ff8e20c6
DR		 7075static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7076{
ff8e20c6
DR		 7077 hba->ufs_stats.hibern8_exit_cnt = 0;
7078 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 7079 hba->req_abort_count = 0;
ff8e20c6
DR		 7080}
7081
a4b0e8a4
PM		 7082static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
7083{
7084 int err;
7085
7086 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
7087 &hba->desc_size.dev_desc);
7088 if (err)
7089 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
7090
7091 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
7092 &hba->desc_size.pwr_desc);
7093 if (err)
7094 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
7095
7096 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
7097 &hba->desc_size.interc_desc);
7098 if (err)
7099 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
7100
7101 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
7102 &hba->desc_size.conf_desc);
7103 if (err)
7104 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
7105
7106 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
7107 &hba->desc_size.unit_desc);
7108 if (err)
7109 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
7110
7111 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
7112 &hba->desc_size.geom_desc);
7113 if (err)
7114 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
059efd84 7115
c648c2d2
SN		 7116 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
7117 &hba->desc_size.hlth_desc);
7118 if (err)
7119 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 7120}
7121
731f0621
BH		 7122static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7123{
7124 int err;
7125 size_t buff_len;
7126 u8 *desc_buf;
7127
7128 buff_len = hba->desc_size.geom_desc;
7129 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7130 if (!desc_buf) {
7131 err = -ENOMEM;
7132 goto out;
7133 }
7134
7135 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_GEOMETRY, 0,
7136 desc_buf, buff_len);
7137 if (err) {
7138 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7139 __func__, err);
7140 goto out;
7141 }
7142
7143 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7144 hba->dev_info.max_lu_supported = 32;
7145 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7146 hba->dev_info.max_lu_supported = 8;
7147
7148out:
7149 kfree(desc_buf);
7150 return err;
7151}
7152
9e1e8a75
SJ		 7153static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7154 {19200000, REF_CLK_FREQ_19_2_MHZ},
7155 {26000000, REF_CLK_FREQ_26_MHZ},
7156 {38400000, REF_CLK_FREQ_38_4_MHZ},
7157 {52000000, REF_CLK_FREQ_52_MHZ},
7158 {0, REF_CLK_FREQ_INVAL},
7159};
7160
7161static enum ufs_ref_clk_freq
7162ufs_get_bref_clk_from_hz(unsigned long freq)
7163{
7164 int i;
7165
7166 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7167 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7168 return ufs_ref_clk_freqs[i].val;
7169
7170 return REF_CLK_FREQ_INVAL;
7171}
7172
7173void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7174{
7175 unsigned long freq;
7176
7177 freq = clk_get_rate(refclk);
7178
7179 hba->dev_ref_clk_freq =
7180 ufs_get_bref_clk_from_hz(freq);
7181
7182 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7183 dev_err(hba->dev,
7184 "invalid ref_clk setting = %ld\n", freq);
7185}
7186
7187static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7188{
7189 int err;
7190 u32 ref_clk;
7191 u32 freq = hba->dev_ref_clk_freq;
7192
7193 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7194 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7195
7196 if (err) {
7197 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7198 err);
7199 goto out;
7200 }
7201
7202 if (ref_clk == freq)
7203 goto out; /* nothing to update */
7204
7205 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7206 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7207
7208 if (err) {
7209 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7210 ufs_ref_clk_freqs[freq].freq_hz);
7211 goto out;
7212 }
7213
7214 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7215 ufs_ref_clk_freqs[freq].freq_hz);
7216
7217out:
7218 return err;
7219}
7220
1b9e2141
BH		 7221static int ufshcd_device_params_init(struct ufs_hba *hba)
7222{
7223 bool flag;
7224 int ret;
7225
731f0621
BH		 7226 /* Clear any previous UFS device information */
7227 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
7228
1b9e2141
BH		 7229 /* Init check for device descriptor sizes */
7230 ufshcd_init_desc_sizes(hba);
7231
731f0621
BH		 7232 /* Init UFS geometry descriptor related parameters */
7233 ret = ufshcd_device_geo_params_init(hba);
7234 if (ret)
7235 goto out;
7236
1b9e2141
BH		 7237 /* Check and apply UFS device quirks */
7238 ret = ufs_get_device_desc(hba);
7239 if (ret) {
7240 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7241 __func__, ret);
7242 goto out;
7243 }
7244
09f17791
CG		 7245 ufshcd_get_ref_clk_gating_wait(hba);
7246
1b9e2141
BH		 7247 ufs_fixup_device_setup(hba);
7248
1b9e2141
BH		 7249 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7250 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
7251 hba->dev_info.f_power_on_wp_en = flag;
7252
2b35b2ad
BH		 7253 /* Probe maximum power mode co-supported by both UFS host and device */
7254 if (ufshcd_get_max_pwr_mode(hba))
7255 dev_err(hba->dev,
7256 "%s: Failed getting max supported power mode\n",
7257 __func__);
1b9e2141
BH		 7258out:
7259 return ret;
7260}
7261
7262/**
7263 * ufshcd_add_lus - probe and add UFS logical units
7264 * @hba: per-adapter instance
7265 */
7266static int ufshcd_add_lus(struct ufs_hba *hba)
7267{
7268 int ret;
7269
1b9e2141
BH		 7270 /* Add required well known logical units to scsi mid layer */
7271 ret = ufshcd_scsi_add_wlus(hba);
7272 if (ret)
7273 goto out;
7274
7275 /* Initialize devfreq after UFS device is detected */
7276 if (ufshcd_is_clkscaling_supported(hba)) {
7277 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7278 &hba->pwr_info,
7279 sizeof(struct ufs_pa_layer_attr));
7280 hba->clk_scaling.saved_pwr_info.is_valid = true;
7281 if (!hba->devfreq) {
7282 ret = ufshcd_devfreq_init(hba);
7283 if (ret)
7284 goto out;
7285 }
7286
7287 hba->clk_scaling.is_allowed = true;
7288 }
7289
7290 ufs_bsg_probe(hba);
7291 scsi_scan_host(hba->host);
7292 pm_runtime_put_sync(hba->dev);
7293
1b9e2141
BH		 7294out:
7295 return ret;
7296}
7297
6ccf44fe 7298/**
1d337ec2
SRT		 7299 * ufshcd_probe_hba - probe hba to detect device and initialize
7300 * @hba: per-adapter instance
1b9e2141 7301 * @async: asynchronous execution or not
1d337ec2
SRT		 7302 *
7303 * Execute link-startup and verify device initialization
6ccf44fe 7304 */
1b9e2141 7305static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
6ccf44fe 7306{
6ccf44fe 7307 int ret;
7ff5ab47 7308 ktime_t start = ktime_get();
6ccf44fe
SJ		 7309
7310 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 7311 if (ret)
7312 goto out;
7313
afdfff59
YG		 7314 /* set the default level for urgent bkops */
7315 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
7316 hba->is_urgent_bkops_lvl_checked = false;
7317
ff8e20c6
DR		 7318 /* Debug counters initialization */
7319 ufshcd_clear_dbg_ufs_stats(hba);
7320
57d104c1
SJ		 7321 /* UniPro link is active now */
7322 ufshcd_set_link_active(hba);
d3e89bac 7323
1b9e2141 7324 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 7325 ret = ufshcd_verify_dev_init(hba);
7326 if (ret)
7327 goto out;
68078d5c 7328
1b9e2141 7329 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 7330 ret = ufshcd_complete_dev_init(hba);
7331 if (ret)
7332 goto out;
5a0b0cb9 7333
1b9e2141
BH		 7334 /*
7335 * Initialize UFS device parameters used by driver, these
7336 * parameters are associated with UFS descriptors.
7337 */
7338 if (async) {
7339 ret = ufshcd_device_params_init(hba);
7340 if (ret)
7341 goto out;
93fdd5ac
TW		 7342 }
7343
09750066 7344 ufshcd_tune_unipro_params(hba);
4b828fe1 7345
57d104c1
SJ		 7346 /* UFS device is also active now */
7347 ufshcd_set_ufs_dev_active(hba);
66ec6d59 7348 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 7349 hba->wlun_dev_clr_ua = true;
7350
2b35b2ad
BH		 7351 /* Gear up to HS gear if supported */
7352 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 7353 /*
7354 * Set the right value to bRefClkFreq before attempting to
7355 * switch to HS gears.
7356 */
7357 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
7358 ufshcd_set_dev_ref_clk(hba);
7eb584db 7359 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 7360 if (ret) {
7eb584db
DR		 7361 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
7362 __func__, ret);
8643ae66
DL		 7363 goto out;
7364 }
6a9df818 7365 ufshcd_print_pwr_info(hba);
7eb584db 7366 }
57d104c1 7367
e89860f1
CG		 7368 /*
7369 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
7370 * and for removable UFS card as well, hence always set the parameter.
7371 * Note: Error handler may issue the device reset hence resetting
7372 * bActiveICCLevel as well so it is always safe to set this here.
7373 */
7374 ufshcd_set_active_icc_lvl(hba);
7375
53c12d0e
YG		 7376 /* set the state as operational after switching to desired gear */
7377 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 7378
3d17b9b5 7379 ufshcd_wb_config(hba);
71d848b8
CG		 7380 /* Enable Auto-Hibernate if configured */
7381 ufshcd_auto_hibern8_enable(hba);
7382
5a0b0cb9 7383out:
1d337ec2 7384
7ff5ab47 7385 trace_ufshcd_init(dev_name(hba->dev), ret,
7386 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7387 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 7388 return ret;
7389}
7390
7391/**
7392 * ufshcd_async_scan - asynchronous execution for probing hba
7393 * @data: data pointer to pass to this function
7394 * @cookie: cookie data
7395 */
7396static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7397{
7398 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 7399 int ret;
1d337ec2 7400
1b9e2141
BH		 7401 /* Initialize hba, detect and initialize UFS device */
7402 ret = ufshcd_probe_hba(hba, true);
7403 if (ret)
7404 goto out;
7405
7406 /* Probe and add UFS logical units */
7407 ret = ufshcd_add_lus(hba);
7408out:
7409 /*
7410 * If we failed to initialize the device or the device is not
7411 * present, turn off the power/clocks etc.
7412 */
7413 if (ret) {
7414 pm_runtime_put_sync(hba->dev);
7415 ufshcd_exit_clk_scaling(hba);
7416 ufshcd_hba_exit(hba);
7417 }
6ccf44fe
SJ		 7418}
7419
d829fc8a
SN		 7420static const struct attribute_group *ufshcd_driver_groups[] = {
7421 &ufs_sysfs_unit_descriptor_group,
ec92b59c 7422 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 7423 NULL,
7424};
7425
7a3e97b0
SY		 7426static struct scsi_host_template ufshcd_driver_template = {
7427 .module = THIS_MODULE,
7428 .name = UFSHCD,
7429 .proc_name = UFSHCD,
7430 .queuecommand = ufshcd_queuecommand,
7431 .slave_alloc = ufshcd_slave_alloc,
eeda4749 7432 .slave_configure = ufshcd_slave_configure,
7a3e97b0 7433 .slave_destroy = ufshcd_slave_destroy,
4264fd61 7434 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 7435 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 7436 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7437 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 7438 .this_id = -1,
7439 .sg_tablesize = SG_ALL,
7440 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7441 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 7442 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 7443 .max_host_blocked = 1,
c40ecc12 7444 .track_queue_depth = 1,
d829fc8a 7445 .sdev_groups = ufshcd_driver_groups,
4af14d11 7446 .dma_boundary = PAGE_SIZE - 1,
49615ba1 7447 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 7448};
7449
57d104c1
SJ		 7450static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7451 int ua)
7452{
7b16a07c 7453 int ret;
57d104c1 7454
7b16a07c
BA		 7455 if (!vreg)
7456 return 0;
57d104c1 7457
0487fff7
SC		 7458 /*
7459 * "set_load" operation shall be required on those regulators
7460 * which specifically configured current limitation. Otherwise
7461 * zero max_uA may cause unexpected behavior when regulator is
7462 * enabled or set as high power mode.
7463 */
7464 if (!vreg->max_uA)
7465 return 0;
7466
7b16a07c
BA		 7467 ret = regulator_set_load(vreg->reg, ua);
7468 if (ret < 0) {
7469 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7470 __func__, vreg->name, ua, ret);
57d104c1
SJ		 7471 }
7472
7473 return ret;
7474}
7475
7476static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7477 struct ufs_vreg *vreg)
7478{
73067981 7479 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 7480}
7481
7482static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7483 struct ufs_vreg *vreg)
7484{
7c7cfdcf
AH		 7485 if (!vreg)
7486 return 0;
7487
73067981 7488 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 7489}
7490
aa497613
SRT		 7491static int ufshcd_config_vreg(struct device *dev,
7492 struct ufs_vreg *vreg, bool on)
7493{
7494 int ret = 0;
72753590
GS		 7495 struct regulator *reg;
7496 const char *name;
aa497613
SRT		 7497 int min_uV, uA_load;
7498
7499 BUG_ON(!vreg);
7500
72753590
GS		 7501 reg = vreg->reg;
7502 name = vreg->name;
7503
aa497613 7504 if (regulator_count_voltages(reg) > 0) {
90d88f47
AD		 7505 uA_load = on ? vreg->max_uA : 0;
7506 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7507 if (ret)
7508 goto out;
7509
3b141e8c
SC		 7510 if (vreg->min_uV && vreg->max_uV) {
7511 min_uV = on ? vreg->min_uV : 0;
7512 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7513 if (ret) {
7514 dev_err(dev,
7515 "%s: %s set voltage failed, err=%d\n",
aa497613 7516 __func__, name, ret);
3b141e8c
SC		 7517 goto out;
7518 }
aa497613 7519 }
aa497613
SRT		 7520 }
7521out:
7522 return ret;
7523}
7524
7525static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7526{
7527 int ret = 0;
7528
73067981 7529 if (!vreg || vreg->enabled)
aa497613
SRT		 7530 goto out;
7531
7532 ret = ufshcd_config_vreg(dev, vreg, true);
7533 if (!ret)
7534 ret = regulator_enable(vreg->reg);
7535
7536 if (!ret)
7537 vreg->enabled = true;
7538 else
7539 dev_err(dev, "%s: %s enable failed, err=%d\n",
7540 __func__, vreg->name, ret);
7541out:
7542 return ret;
7543}
7544
7545static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7546{
7547 int ret = 0;
7548
73067981 7549 if (!vreg || !vreg->enabled)
aa497613
SRT		 7550 goto out;
7551
7552 ret = regulator_disable(vreg->reg);
7553
7554 if (!ret) {
7555 /* ignore errors on applying disable config */
7556 ufshcd_config_vreg(dev, vreg, false);
7557 vreg->enabled = false;
7558 } else {
7559 dev_err(dev, "%s: %s disable failed, err=%d\n",
7560 __func__, vreg->name, ret);
7561 }
7562out:
7563 return ret;
7564}
7565
7566static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7567{
7568 int ret = 0;
7569 struct device *dev = hba->dev;
7570 struct ufs_vreg_info *info = &hba->vreg_info;
7571
aa497613
SRT		 7572 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7573 if (ret)
7574 goto out;
7575
7576 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7577 if (ret)
7578 goto out;
7579
7580 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7581 if (ret)
7582 goto out;
7583
7584out:
7585 if (ret) {
7586 ufshcd_toggle_vreg(dev, info->vccq2, false);
7587 ufshcd_toggle_vreg(dev, info->vccq, false);
7588 ufshcd_toggle_vreg(dev, info->vcc, false);
7589 }
7590 return ret;
7591}
7592
6a771a65
RS		 7593static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7594{
7595 struct ufs_vreg_info *info = &hba->vreg_info;
7596
60b7b823 7597 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 7598}
7599
aa497613
SRT		 7600static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7601{
7602 int ret = 0;
7603
7604 if (!vreg)
7605 goto out;
7606
7607 vreg->reg = devm_regulator_get(dev, vreg->name);
7608 if (IS_ERR(vreg->reg)) {
7609 ret = PTR_ERR(vreg->reg);
7610 dev_err(dev, "%s: %s get failed, err=%d\n",
7611 __func__, vreg->name, ret);
7612 }
7613out:
7614 return ret;
7615}
7616
7617static int ufshcd_init_vreg(struct ufs_hba *hba)
7618{
7619 int ret = 0;
7620 struct device *dev = hba->dev;
7621 struct ufs_vreg_info *info = &hba->vreg_info;
7622
aa497613
SRT		 7623 ret = ufshcd_get_vreg(dev, info->vcc);
7624 if (ret)
7625 goto out;
7626
7627 ret = ufshcd_get_vreg(dev, info->vccq);
7628 if (ret)
7629 goto out;
7630
7631 ret = ufshcd_get_vreg(dev, info->vccq2);
7632out:
7633 return ret;
7634}
7635
6a771a65
RS		 7636static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7637{
7638 struct ufs_vreg_info *info = &hba->vreg_info;
7639
7640 if (info)
7641 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7642
7643 return 0;
7644}
7645
57d104c1
SJ		 7646static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7647 bool skip_ref_clk)
c6e79dac
SRT		 7648{
7649 int ret = 0;
7650 struct ufs_clk_info *clki;
7651 struct list_head *head = &hba->clk_list_head;
1ab27c9c 7652 unsigned long flags;
911a0771 7653 ktime_t start = ktime_get();
7654 bool clk_state_changed = false;
c6e79dac 7655
566ec9ad 7656 if (list_empty(head))
c6e79dac
SRT		 7657 goto out;
7658
38f3242e
CG		 7659 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7660 if (ret)
7661 return ret;
1e879e8f 7662
c6e79dac
SRT		 7663 list_for_each_entry(clki, head, list) {
7664 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7665 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7666 continue;
7667
911a0771 7668 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7669 if (on && !clki->enabled) {
7670 ret = clk_prepare_enable(clki->clk);
7671 if (ret) {
7672 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7673 __func__, clki->name, ret);
7674 goto out;
7675 }
7676 } else if (!on && clki->enabled) {
7677 clk_disable_unprepare(clki->clk);
7678 }
7679 clki->enabled = on;
7680 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7681 clki->name, on ? "en" : "dis");
7682 }
7683 }
1ab27c9c 7684
38f3242e
CG		 7685 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7686 if (ret)
7687 return ret;
1e879e8f 7688
c6e79dac
SRT		 7689out:
7690 if (ret) {
7691 list_for_each_entry(clki, head, list) {
7692 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7693 clk_disable_unprepare(clki->clk);
7694 }
7ff5ab47 7695 } else if (!ret && on) {
1ab27c9c
ST		 7696 spin_lock_irqsave(hba->host->host_lock, flags);
7697 hba->clk_gating.state = CLKS_ON;
7ff5ab47 7698 trace_ufshcd_clk_gating(dev_name(hba->dev),
7699 hba->clk_gating.state);
1ab27c9c 7700 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7701 }
7ff5ab47 7702
911a0771 7703 if (clk_state_changed)
7704 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7705 (on ? "on" : "off"),
7706 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7707 return ret;
7708}
7709
57d104c1
SJ		 7710static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7711{
7712 return __ufshcd_setup_clocks(hba, on, false);
7713}
7714
c6e79dac
SRT		 7715static int ufshcd_init_clocks(struct ufs_hba *hba)
7716{
7717 int ret = 0;
7718 struct ufs_clk_info *clki;
7719 struct device *dev = hba->dev;
7720 struct list_head *head = &hba->clk_list_head;
7721
566ec9ad 7722 if (list_empty(head))
c6e79dac
SRT		 7723 goto out;
7724
7725 list_for_each_entry(clki, head, list) {
7726 if (!clki->name)
7727 continue;
7728
7729 clki->clk = devm_clk_get(dev, clki->name);
7730 if (IS_ERR(clki->clk)) {
7731 ret = PTR_ERR(clki->clk);
7732 dev_err(dev, "%s: %s clk get failed, %d\n",
7733 __func__, clki->name, ret);
7734 goto out;
7735 }
7736
9e1e8a75
SJ		 7737 /*
7738 * Parse device ref clk freq as per device tree "ref_clk".
7739 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
7740 * in ufshcd_alloc_host().
7741 */
7742 if (!strcmp(clki->name, "ref_clk"))
7743 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7744
c6e79dac
SRT		 7745 if (clki->max_freq) {
7746 ret = clk_set_rate(clki->clk, clki->max_freq);
7747 if (ret) {
7748 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7749 __func__, clki->name,
7750 clki->max_freq, ret);
7751 goto out;
7752 }
856b3483 7753 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7754 }
7755 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7756 clki->name, clk_get_rate(clki->clk));
7757 }
7758out:
7759 return ret;
7760}
7761
5c0c28a8
SRT		 7762static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7763{
7764 int err = 0;
7765
7766 if (!hba->vops)
7767 goto out;
7768
0263bcd0
YG		 7769 err = ufshcd_vops_init(hba);
7770 if (err)
7771 goto out;
5c0c28a8 7772
0263bcd0
YG		 7773 err = ufshcd_vops_setup_regulators(hba, true);
7774 if (err)
7775 goto out_exit;
5c0c28a8
SRT		 7776
7777 goto out;
7778
5c0c28a8 7779out_exit:
0263bcd0 7780 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7781out:
7782 if (err)
7783 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7784 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7785 return err;
7786}
7787
7788static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7789{
7790 if (!hba->vops)
7791 return;
7792
0263bcd0 7793 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7794
0263bcd0 7795 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7796}
7797
aa497613
SRT		 7798static int ufshcd_hba_init(struct ufs_hba *hba)
7799{
7800 int err;
7801
6a771a65
RS		 7802 /*
7803 * Handle host controller power separately from the UFS device power
7804 * rails as it will help controlling the UFS host controller power
7805 * collapse easily which is different than UFS device power collapse.
7806 * Also, enable the host controller power before we go ahead with rest
7807 * of the initialization here.
7808 */
7809 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7810 if (err)
7811 goto out;
7812
6a771a65 7813 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7814 if (err)
7815 goto out;
7816
6a771a65
RS		 7817 err = ufshcd_init_clocks(hba);
7818 if (err)
7819 goto out_disable_hba_vreg;
7820
7821 err = ufshcd_setup_clocks(hba, true);
7822 if (err)
7823 goto out_disable_hba_vreg;
7824
c6e79dac
SRT		 7825 err = ufshcd_init_vreg(hba);
7826 if (err)
7827 goto out_disable_clks;
7828
7829 err = ufshcd_setup_vreg(hba, true);
7830 if (err)
7831 goto out_disable_clks;
7832
aa497613
SRT		 7833 err = ufshcd_variant_hba_init(hba);
7834 if (err)
7835 goto out_disable_vreg;
7836
1d337ec2 7837 hba->is_powered = true;
aa497613
SRT		 7838 goto out;
7839
7840out_disable_vreg:
7841 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7842out_disable_clks:
7843 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7844out_disable_hba_vreg:
7845 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7846out:
7847 return err;
7848}
7849
7850static void ufshcd_hba_exit(struct ufs_hba *hba)
7851{
1d337ec2
SRT		 7852 if (hba->is_powered) {
7853 ufshcd_variant_hba_exit(hba);
7854 ufshcd_setup_vreg(hba, false);
a508253d 7855 ufshcd_suspend_clkscaling(hba);
eebcc196 7856 if (ufshcd_is_clkscaling_supported(hba))
0701e49d 7857 if (hba->devfreq)
7858 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7859 ufshcd_setup_clocks(hba, false);
7860 ufshcd_setup_hba_vreg(hba, false);
7861 hba->is_powered = false;
09750066 7862 ufs_put_device_desc(hba);
1d337ec2 7863 }
aa497613
SRT		 7864}
7865
57d104c1
SJ		 7866static int
7867ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7868{
7869 unsigned char cmd[6] = {REQUEST_SENSE,
7870 0,
7871 0,
7872 0,
09a5a24f 7873 UFS_SENSE_SIZE,
57d104c1
SJ		 7874 0};
7875 char *buffer;
7876 int ret;
7877
09a5a24f 7878 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7879 if (!buffer) {
7880 ret = -ENOMEM;
7881 goto out;
7882 }
7883
fcbfffe2 7884 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
09a5a24f 7885 UFS_SENSE_SIZE, NULL, NULL,
fcbfffe2 7886 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7887 if (ret)
7888 pr_err("%s: failed with err %d\n", __func__, ret);
7889
7890 kfree(buffer);
7891out:
7892 return ret;
7893}
7894
7895/**
7896 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7897 * power mode
7898 * @hba: per adapter instance
7899 * @pwr_mode: device power mode to set
7900 *
7901 * Returns 0 if requested power mode is set successfully
7902 * Returns non-zero if failed to set the requested power mode
7903 */
7904static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7905 enum ufs_dev_pwr_mode pwr_mode)
7906{
7907 unsigned char cmd[6] = { START_STOP };
7908 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7909 struct scsi_device *sdp;
7910 unsigned long flags;
57d104c1
SJ		 7911 int ret;
7912
7c48bfd0
AM		 7913 spin_lock_irqsave(hba->host->host_lock, flags);
7914 sdp = hba->sdev_ufs_device;
7915 if (sdp) {
7916 ret = scsi_device_get(sdp);
7917 if (!ret && !scsi_device_online(sdp)) {
7918 ret = -ENODEV;
7919 scsi_device_put(sdp);
7920 }
7921 } else {
7922 ret = -ENODEV;
7923 }
7924 spin_unlock_irqrestore(hba->host->host_lock, flags);
7925
7926 if (ret)
7927 return ret;
57d104c1
SJ		 7928
7929 /*
7930 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7931 * handling, which would wait for host to be resumed. Since we know
7932 * we are functional while we are here, skip host resume in error
7933 * handling context.
7934 */
7935 hba->host->eh_noresume = 1;
7936 if (hba->wlun_dev_clr_ua) {
7937 ret = ufshcd_send_request_sense(hba, sdp);
7938 if (ret)
7939 goto out;
7940 /* Unit attention condition is cleared now */
7941 hba->wlun_dev_clr_ua = false;
7942 }
7943
7944 cmd[4] = pwr_mode << 4;
7945
7946 /*
7947 * Current function would be generally called from the power management
e8064021 7948 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7949 * already suspended childs.
7950 */
fcbfffe2
CH		 7951 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7952 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7953 if (ret) {
7954 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7955 "START_STOP failed for power mode: %d, result %x\n",
7956 pwr_mode, ret);
c65be1a6 7957 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7958 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7959 }
7960
7961 if (!ret)
7962 hba->curr_dev_pwr_mode = pwr_mode;
7963out:
7c48bfd0 7964 scsi_device_put(sdp);
57d104c1
SJ		 7965 hba->host->eh_noresume = 0;
7966 return ret;
7967}
7968
7969static int ufshcd_link_state_transition(struct ufs_hba *hba,
7970 enum uic_link_state req_link_state,
7971 int check_for_bkops)
7972{
7973 int ret = 0;
7974
7975 if (req_link_state == hba->uic_link_state)
7976 return 0;
7977
7978 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7979 ret = ufshcd_uic_hibern8_enter(hba);
7980 if (!ret)
7981 ufshcd_set_link_hibern8(hba);
7982 else
7983 goto out;
7984 }
7985 /*
7986 * If autobkops is enabled, link can't be turned off because
7987 * turning off the link would also turn off the device.
7988 */
7989 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 7990 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 7991 /*
7992 * Let's make sure that link is in low power mode, we are doing
7993 * this currently by putting the link in Hibern8. Otherway to
7994 * put the link in low power mode is to send the DME end point
7995 * to device and then send the DME reset command to local
7996 * unipro. But putting the link in hibern8 is much faster.
7997 */
7998 ret = ufshcd_uic_hibern8_enter(hba);
7999 if (ret)
8000 goto out;
57d104c1
SJ		 8001 /*
8002 * Change controller state to "reset state" which
8003 * should also put the link in off/reset state
8004 */
596585a2 8005 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 8006 /*
8007 * TODO: Check if we need any delay to make sure that
8008 * controller is reset
8009 */
8010 ufshcd_set_link_off(hba);
8011 }
8012
8013out:
8014 return ret;
8015}
8016
8017static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8018{
b799fdf7
YG		 8019 /*
8020 * It seems some UFS devices may keep drawing more than sleep current
8021 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8022 * To avoid this situation, add 2ms delay before putting these UFS
8023 * rails in LPM mode.
8024 */
8025 if (!ufshcd_is_link_active(hba) &&
8026 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8027 usleep_range(2000, 2100);
8028
57d104c1
SJ		 8029 /*
8030 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8031 * power.
8032 *
8033 * If UFS device and link is in OFF state, all power supplies (VCC,
8034 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8035 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8036 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8037 *
8038 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8039 * in low power state which would save some power.
3d17b9b5
AD		 8040 *
8041 * If Write Booster is enabled and the device needs to flush the WB
8042 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 8043 */
8044 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8045 !hba->dev_info.is_lu_power_on_wp) {
8046 ufshcd_setup_vreg(hba, false);
8047 } else if (!ufshcd_is_ufs_dev_active(hba)) {
3d17b9b5
AD		 8048 if (!hba->dev_info.keep_vcc_on)
8049 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
57d104c1
SJ		 8050 if (!ufshcd_is_link_active(hba)) {
8051 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8052 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8053 }
8054 }
8055}
8056
8057static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8058{
8059 int ret = 0;
8060
8061 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8062 !hba->dev_info.is_lu_power_on_wp) {
8063 ret = ufshcd_setup_vreg(hba, true);
8064 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 8065 if (!ret && !ufshcd_is_link_active(hba)) {
8066 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8067 if (ret)
8068 goto vcc_disable;
8069 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8070 if (ret)
8071 goto vccq_lpm;
8072 }
69d72ac8 8073 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 8074 }
8075 goto out;
8076
8077vccq_lpm:
8078 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8079vcc_disable:
8080 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8081out:
8082 return ret;
8083}
8084
8085static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8086{
8087 if (ufshcd_is_link_off(hba))
8088 ufshcd_setup_hba_vreg(hba, false);
8089}
8090
8091static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8092{
8093 if (ufshcd_is_link_off(hba))
8094 ufshcd_setup_hba_vreg(hba, true);
8095}
8096
7a3e97b0 8097/**
57d104c1 8098 * ufshcd_suspend - helper function for suspend operations
3b1d0580 8099 * @hba: per adapter instance
57d104c1
SJ		 8100 * @pm_op: desired low power operation type
8101 *
8102 * This function will try to put the UFS device and link into low power
8103 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
8104 * (System PM level).
8105 *
8106 * If this function is called during shutdown, it will make sure that
8107 * both UFS device and UFS link is powered off.
7a3e97b0 8108 *
57d104c1
SJ		 8109 * NOTE: UFS device & link must be active before we enter in this function.
8110 *
8111 * Returns 0 for success and non-zero for failure
7a3e97b0 8112 */
57d104c1 8113static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8114{
57d104c1
SJ		 8115 int ret = 0;
8116 enum ufs_pm_level pm_lvl;
8117 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8118 enum uic_link_state req_link_state;
8119
8120 hba->pm_op_in_progress = 1;
8121 if (!ufshcd_is_shutdown_pm(pm_op)) {
8122 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
8123 hba->rpm_lvl : hba->spm_lvl;
8124 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8125 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8126 } else {
8127 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8128 req_link_state = UIC_LINK_OFF_STATE;
8129 }
8130
7a3e97b0 8131 /*
57d104c1
SJ		 8132 * If we can't transition into any of the low power modes
8133 * just gate the clocks.
7a3e97b0 8134 */
1ab27c9c
ST		 8135 ufshcd_hold(hba, false);
8136 hba->clk_gating.is_suspended = true;
8137
401f1e44 8138 if (hba->clk_scaling.is_allowed) {
8139 cancel_work_sync(&hba->clk_scaling.suspend_work);
8140 cancel_work_sync(&hba->clk_scaling.resume_work);
8141 ufshcd_suspend_clkscaling(hba);
8142 }
d6fcf81a 8143
57d104c1
SJ		 8144 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8145 req_link_state == UIC_LINK_ACTIVE_STATE) {
8146 goto disable_clks;
8147 }
7a3e97b0 8148
57d104c1
SJ		 8149 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8150 (req_link_state == hba->uic_link_state))
d6fcf81a 8151 goto enable_gating;
57d104c1
SJ		 8152
8153 /* UFS device & link must be active before we enter in this function */
8154 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8155 ret = -EINVAL;
d6fcf81a 8156 goto enable_gating;
57d104c1
SJ		 8157 }
8158
8159 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 8160 if (ufshcd_can_autobkops_during_suspend(hba)) {
8161 /*
8162 * The device is idle with no requests in the queue,
8163 * allow background operations if bkops status shows
8164 * that performance might be impacted.
8165 */
8166 ret = ufshcd_urgent_bkops(hba);
8167 if (ret)
8168 goto enable_gating;
8169 } else {
8170 /* make sure that auto bkops is disabled */
8171 ufshcd_disable_auto_bkops(hba);
8172 }
3d17b9b5
AD		 8173 /*
8174 * With wb enabled, if the bkops is enabled or if the
8175 * configured WB type is 70% full, keep vcc ON
8176 * for the device to flush the wb buffer
8177 */
8178 if ((hba->auto_bkops_enabled && ufshcd_wb_sup(hba)) ||
8179 ufshcd_wb_keep_vcc_on(hba))
8180 hba->dev_info.keep_vcc_on = true;
8181 else
8182 hba->dev_info.keep_vcc_on = false;
8183 } else if (!ufshcd_is_runtime_pm(pm_op)) {
8184 hba->dev_info.keep_vcc_on = false;
57d104c1
SJ		 8185 }
8186
8187 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
3d17b9b5
AD		 8188 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
8189 !ufshcd_is_runtime_pm(pm_op))) {
57d104c1
SJ		 8190 /* ensure that bkops is disabled */
8191 ufshcd_disable_auto_bkops(hba);
8192 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8193 if (ret)
1ab27c9c 8194 goto enable_gating;
57d104c1
SJ		 8195 }
8196
2824ec9f 8197 flush_work(&hba->eeh_work);
57d104c1
SJ		 8198 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
8199 if (ret)
8200 goto set_dev_active;
8201
8202 ufshcd_vreg_set_lpm(hba);
8203
8204disable_clks:
8205 /*
8206 * Call vendor specific suspend callback. As these callbacks may access
8207 * vendor specific host controller register space call them before the
8208 * host clocks are ON.
8209 */
0263bcd0
YG		 8210 ret = ufshcd_vops_suspend(hba, pm_op);
8211 if (ret)
8212 goto set_link_active;
dcb6cec5
SC		 8213 /*
8214 * Disable the host irq as host controller as there won't be any
8215 * host controller transaction expected till resume.
8216 */
8217 ufshcd_disable_irq(hba);
57d104c1 8218
57d104c1
SJ		 8219 if (!ufshcd_is_link_active(hba))
8220 ufshcd_setup_clocks(hba, false);
8221 else
8222 /* If link is active, device ref_clk can't be switched off */
8223 __ufshcd_setup_clocks(hba, false, true);
8224
1ab27c9c 8225 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 8226 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
dcb6cec5 8227
57d104c1
SJ		 8228 /* Put the host controller in low power mode if possible */
8229 ufshcd_hba_vreg_set_lpm(hba);
8230 goto out;
8231
57d104c1 8232set_link_active:
401f1e44 8233 if (hba->clk_scaling.is_allowed)
8234 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 8235 ufshcd_vreg_set_hpm(hba);
8236 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8237 ufshcd_set_link_active(hba);
8238 else if (ufshcd_is_link_off(hba))
8239 ufshcd_host_reset_and_restore(hba);
8240set_dev_active:
8241 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8242 ufshcd_disable_auto_bkops(hba);
1ab27c9c 8243enable_gating:
401f1e44 8244 if (hba->clk_scaling.is_allowed)
8245 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 8246 hba->clk_gating.is_suspended = false;
8247 ufshcd_release(hba);
57d104c1
SJ		 8248out:
8249 hba->pm_op_in_progress = 0;
8808b4e9
SC		 8250 if (ret)
8251 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
57d104c1 8252 return ret;
7a3e97b0
SY		 8253}
8254
8255/**
57d104c1 8256 * ufshcd_resume - helper function for resume operations
3b1d0580 8257 * @hba: per adapter instance
57d104c1 8258 * @pm_op: runtime PM or system PM
7a3e97b0 8259 *
57d104c1
SJ		 8260 * This function basically brings the UFS device, UniPro link and controller
8261 * to active state.
8262 *
8263 * Returns 0 for success and non-zero for failure
7a3e97b0 8264 */
57d104c1 8265static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8266{
57d104c1
SJ		 8267 int ret;
8268 enum uic_link_state old_link_state;
8269
8270 hba->pm_op_in_progress = 1;
8271 old_link_state = hba->uic_link_state;
8272
8273 ufshcd_hba_vreg_set_hpm(hba);
8274 /* Make sure clocks are enabled before accessing controller */
8275 ret = ufshcd_setup_clocks(hba, true);
8276 if (ret)
8277 goto out;
8278
57d104c1 8279 /* enable the host irq as host controller would be active soon */
5231d38c 8280 ufshcd_enable_irq(hba);
57d104c1
SJ		 8281
8282 ret = ufshcd_vreg_set_hpm(hba);
8283 if (ret)
8284 goto disable_irq_and_vops_clks;
8285
7a3e97b0 8286 /*
57d104c1
SJ		 8287 * Call vendor specific resume callback. As these callbacks may access
8288 * vendor specific host controller register space call them when the
8289 * host clocks are ON.
7a3e97b0 8290 */
0263bcd0
YG		 8291 ret = ufshcd_vops_resume(hba, pm_op);
8292 if (ret)
8293 goto disable_vreg;
57d104c1
SJ		 8294
8295 if (ufshcd_is_link_hibern8(hba)) {
8296 ret = ufshcd_uic_hibern8_exit(hba);
8297 if (!ret)
8298 ufshcd_set_link_active(hba);
8299 else
8300 goto vendor_suspend;
8301 } else if (ufshcd_is_link_off(hba)) {
57d104c1 8302 /*
089f5b64
AD		 8303 * A full initialization of the host and the device is
8304 * required since the link was put to off during suspend.
8305 */
8306 ret = ufshcd_reset_and_restore(hba);
8307 /*
8308 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 8309 * set the link state as active
8310 */
8311 if (ret || !ufshcd_is_link_active(hba))
8312 goto vendor_suspend;
8313 }
8314
8315 if (!ufshcd_is_ufs_dev_active(hba)) {
8316 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8317 if (ret)
8318 goto set_old_link_state;
8319 }
8320
4e768e76 8321 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8322 ufshcd_enable_auto_bkops(hba);
8323 else
8324 /*
8325 * If BKOPs operations are urgently needed at this moment then
8326 * keep auto-bkops enabled or else disable it.
8327 */
8328 ufshcd_urgent_bkops(hba);
8329
1ab27c9c
ST		 8330 hba->clk_gating.is_suspended = false;
8331
fcb0c4b0
ST		 8332 if (hba->clk_scaling.is_allowed)
8333 ufshcd_resume_clkscaling(hba);
856b3483 8334
ad448378
AH		 8335 /* Enable Auto-Hibernate if configured */
8336 ufshcd_auto_hibern8_enable(hba);
8337
71d848b8
CG		 8338 /* Schedule clock gating in case of no access to UFS device yet */
8339 ufshcd_release(hba);
8340
57d104c1
SJ		 8341 goto out;
8342
8343set_old_link_state:
8344 ufshcd_link_state_transition(hba, old_link_state, 0);
8345vendor_suspend:
0263bcd0 8346 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 8347disable_vreg:
8348 ufshcd_vreg_set_lpm(hba);
8349disable_irq_and_vops_clks:
8350 ufshcd_disable_irq(hba);
401f1e44 8351 if (hba->clk_scaling.is_allowed)
8352 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 8353 ufshcd_setup_clocks(hba, false);
8354out:
8355 hba->pm_op_in_progress = 0;
8808b4e9
SC		 8356 if (ret)
8357 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
57d104c1
SJ		 8358 return ret;
8359}
8360
8361/**
8362 * ufshcd_system_suspend - system suspend routine
8363 * @hba: per adapter instance
57d104c1
SJ		 8364 *
8365 * Check the description of ufshcd_suspend() function for more details.
8366 *
8367 * Returns 0 for success and non-zero for failure
8368 */
8369int ufshcd_system_suspend(struct ufs_hba *hba)
8370{
8371 int ret = 0;
7ff5ab47 8372 ktime_t start = ktime_get();
57d104c1
SJ		 8373
8374 if (!hba || !hba->is_powered)
233b594b 8375 return 0;
57d104c1 8376
0b257734 8377 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8378 hba->curr_dev_pwr_mode) &&
8379 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8380 hba->uic_link_state))
8381 goto out;
57d104c1 8382
0b257734 8383 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 8384 /*
8385 * UFS device and/or UFS link low power states during runtime
8386 * suspend seems to be different than what is expected during
8387 * system suspend. Hence runtime resume the devic & link and
8388 * let the system suspend low power states to take effect.
8389 * TODO: If resume takes longer time, we might have optimize
8390 * it in future by not resuming everything if possible.
8391 */
8392 ret = ufshcd_runtime_resume(hba);
8393 if (ret)
8394 goto out;
8395 }
8396
8397 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8398out:
7ff5ab47 8399 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8400 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8401 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 8402 if (!ret)
8403 hba->is_sys_suspended = true;
57d104c1
SJ		 8404 return ret;
8405}
8406EXPORT_SYMBOL(ufshcd_system_suspend);
8407
8408/**
8409 * ufshcd_system_resume - system resume routine
8410 * @hba: per adapter instance
8411 *
8412 * Returns 0 for success and non-zero for failure
8413 */
7a3e97b0 8414
57d104c1
SJ		 8415int ufshcd_system_resume(struct ufs_hba *hba)
8416{
7ff5ab47 8417 int ret = 0;
8418 ktime_t start = ktime_get();
8419
e3ce73d6
YG		 8420 if (!hba)
8421 return -EINVAL;
8422
8423 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 8424 /*
8425 * Let the runtime resume take care of resuming
8426 * if runtime suspended.
8427 */
7ff5ab47 8428 goto out;
8429 else
8430 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8431out:
8432 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8433 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8434 hba->curr_dev_pwr_mode, hba->uic_link_state);
ce9e7bce
SC		 8435 if (!ret)
8436 hba->is_sys_suspended = false;
7ff5ab47 8437 return ret;
7a3e97b0 8438}
57d104c1 8439EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 8440
57d104c1
SJ		 8441/**
8442 * ufshcd_runtime_suspend - runtime suspend routine
8443 * @hba: per adapter instance
8444 *
8445 * Check the description of ufshcd_suspend() function for more details.
8446 *
8447 * Returns 0 for success and non-zero for failure
8448 */
66ec6d59
SRT		 8449int ufshcd_runtime_suspend(struct ufs_hba *hba)
8450{
7ff5ab47 8451 int ret = 0;
8452 ktime_t start = ktime_get();
8453
e3ce73d6
YG		 8454 if (!hba)
8455 return -EINVAL;
8456
8457 if (!hba->is_powered)
7ff5ab47 8458 goto out;
8459 else
8460 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8461out:
8462 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8463 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8464 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8465 return ret;
66ec6d59
SRT		 8466}
8467EXPORT_SYMBOL(ufshcd_runtime_suspend);
8468
57d104c1
SJ		 8469/**
8470 * ufshcd_runtime_resume - runtime resume routine
8471 * @hba: per adapter instance
8472 *
8473 * This function basically brings the UFS device, UniPro link and controller
8474 * to active state. Following operations are done in this function:
8475 *
8476 * 1. Turn on all the controller related clocks
8477 * 2. Bring the UniPro link out of Hibernate state
8478 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8479 * to active state.
8480 * 4. If auto-bkops is enabled on the device, disable it.
8481 *
8482 * So following would be the possible power state after this function return
8483 * successfully:
8484 * S1: UFS device in Active state with VCC rail ON
8485 * UniPro link in Active state
8486 * All the UFS/UniPro controller clocks are ON
8487 *
8488 * Returns 0 for success and non-zero for failure
8489 */
66ec6d59
SRT		 8490int ufshcd_runtime_resume(struct ufs_hba *hba)
8491{
7ff5ab47 8492 int ret = 0;
8493 ktime_t start = ktime_get();
8494
e3ce73d6
YG		 8495 if (!hba)
8496 return -EINVAL;
8497
8498 if (!hba->is_powered)
7ff5ab47 8499 goto out;
8500 else
8501 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8502out:
8503 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8504 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8505 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8506 return ret;
66ec6d59
SRT		 8507}
8508EXPORT_SYMBOL(ufshcd_runtime_resume);
8509
8510int ufshcd_runtime_idle(struct ufs_hba *hba)
8511{
8512 return 0;
8513}
8514EXPORT_SYMBOL(ufshcd_runtime_idle);
8515
57d104c1
SJ		 8516/**
8517 * ufshcd_shutdown - shutdown routine
8518 * @hba: per adapter instance
8519 *
8520 * This function would power off both UFS device and UFS link.
8521 *
8522 * Returns 0 always to allow force shutdown even in case of errors.
8523 */
8524int ufshcd_shutdown(struct ufs_hba *hba)
8525{
8526 int ret = 0;
8527
f51913ee
SC		 8528 if (!hba->is_powered)
8529 goto out;
8530
57d104c1
SJ		 8531 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8532 goto out;
8533
8534 if (pm_runtime_suspended(hba->dev)) {
8535 ret = ufshcd_runtime_resume(hba);
8536 if (ret)
8537 goto out;
8538 }
8539
8540 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8541out:
8542 if (ret)
8543 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8544 /* allow force shutdown even in case of errors */
8545 return 0;
8546}
8547EXPORT_SYMBOL(ufshcd_shutdown);
8548
7a3e97b0 8549/**
3b1d0580 8550 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8551 * data structure memory
8aa29f19 8552 * @hba: per adapter instance
7a3e97b0 8553 */
3b1d0580 8554void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8555{
df032bf2 8556 ufs_bsg_remove(hba);
cbb6813e 8557 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 8558 blk_cleanup_queue(hba->tmf_queue);
8559 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360 8560 blk_cleanup_queue(hba->cmd_queue);
cfdf9c91 8561 scsi_remove_host(hba->host);
7a3e97b0 8562 /* disable interrupts */
2fbd009b 8563 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8564 ufshcd_hba_stop(hba, true);
7a3e97b0 8565
eebcc196 8566 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8567 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8568 if (ufshcd_is_clkscaling_supported(hba))
8569 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8570 ufshcd_hba_exit(hba);
3b1d0580
VH		 8571}
8572EXPORT_SYMBOL_GPL(ufshcd_remove);
8573
47555a5c
YG		 8574/**
8575 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8576 * @hba: pointer to Host Bus Adapter (HBA)
8577 */
8578void ufshcd_dealloc_host(struct ufs_hba *hba)
8579{
8580 scsi_host_put(hba->host);
8581}
8582EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8583
ca3d7bf9
AM		 8584/**
8585 * ufshcd_set_dma_mask - Set dma mask based on the controller
8586 * addressing capability
8587 * @hba: per adapter instance
8588 *
8589 * Returns 0 for success, non-zero for failure
8590 */
8591static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8592{
8593 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8594 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8595 return 0;
8596 }
8597 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8598}
8599
7a3e97b0 8600/**
5c0c28a8 8601 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8602 * @dev: pointer to device handle
8603 * @hba_handle: driver private handle
7a3e97b0
SY		 8604 * Returns 0 on success, non-zero value on failure
8605 */
5c0c28a8 8606int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8607{
8608 struct Scsi_Host *host;
8609 struct ufs_hba *hba;
5c0c28a8 8610 int err = 0;
7a3e97b0 8611
3b1d0580
VH		 8612 if (!dev) {
8613 dev_err(dev,
8614 "Invalid memory reference for dev is NULL\n");
8615 err = -ENODEV;
7a3e97b0
SY		 8616 goto out_error;
8617 }
8618
7a3e97b0
SY		 8619 host = scsi_host_alloc(&ufshcd_driver_template,
8620 sizeof(struct ufs_hba));
8621 if (!host) {
3b1d0580 8622 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8623 err = -ENOMEM;
3b1d0580 8624 goto out_error;
7a3e97b0
SY		 8625 }
8626 hba = shost_priv(host);
7a3e97b0 8627 hba->host = host;
3b1d0580 8628 hba->dev = dev;
5c0c28a8 8629 *hba_handle = hba;
9e1e8a75 8630 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
5c0c28a8 8631
566ec9ad
SM		 8632 INIT_LIST_HEAD(&hba->clk_list_head);
8633
5c0c28a8
SRT		 8634out_error:
8635 return err;
8636}
8637EXPORT_SYMBOL(ufshcd_alloc_host);
8638
69a6c269
BVA		 8639/* This function exists because blk_mq_alloc_tag_set() requires this. */
8640static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
8641 const struct blk_mq_queue_data *qd)
8642{
8643 WARN_ON_ONCE(true);
8644 return BLK_STS_NOTSUPP;
8645}
8646
8647static const struct blk_mq_ops ufshcd_tmf_ops = {
8648 .queue_rq = ufshcd_queue_tmf,
8649};
8650
5c0c28a8
SRT		 8651/**
8652 * ufshcd_init - Driver initialization routine
8653 * @hba: per-adapter instance
8654 * @mmio_base: base register address
8655 * @irq: Interrupt line of device
8656 * Returns 0 on success, non-zero value on failure
8657 */
8658int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8659{
8660 int err;
8661 struct Scsi_Host *host = hba->host;
8662 struct device *dev = hba->dev;
8663
8664 if (!mmio_base) {
8665 dev_err(hba->dev,
8666 "Invalid memory reference for mmio_base is NULL\n");
8667 err = -ENODEV;
8668 goto out_error;
8669 }
8670
3b1d0580
VH		 8671 hba->mmio_base = mmio_base;
8672 hba->irq = irq;
b9dc8aca 8673 hba->hba_enable_delay_us = 1000;
7a3e97b0 8674
aa497613 8675 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8676 if (err)
8677 goto out_error;
8678
7a3e97b0
SY		 8679 /* Read capabilities registers */
8680 ufshcd_hba_capabilities(hba);
8681
8682 /* Get UFS version supported by the controller */
8683 hba->ufs_version = ufshcd_get_ufs_version(hba);
8684
c01848c6
YG		 8685 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8686 (hba->ufs_version != UFSHCI_VERSION_11) &&
8687 (hba->ufs_version != UFSHCI_VERSION_20) &&
8688 (hba->ufs_version != UFSHCI_VERSION_21))
8689 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8690 hba->ufs_version);
8691
2fbd009b
SJ		 8692 /* Get Interrupt bit mask per version */
8693 hba->intr_mask = ufshcd_get_intr_mask(hba);
8694
ca3d7bf9
AM		 8695 err = ufshcd_set_dma_mask(hba);
8696 if (err) {
8697 dev_err(hba->dev, "set dma mask failed\n");
8698 goto out_disable;
8699 }
8700
7a3e97b0
SY		 8701 /* Allocate memory for host memory space */
8702 err = ufshcd_memory_alloc(hba);
8703 if (err) {
3b1d0580
VH		 8704 dev_err(hba->dev, "Memory allocation failed\n");
8705 goto out_disable;
7a3e97b0
SY		 8706 }
8707
8708 /* Configure LRB */
8709 ufshcd_host_memory_configure(hba);
8710
8711 host->can_queue = hba->nutrs;
8712 host->cmd_per_lun = hba->nutrs;
8713 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8714 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8715 host->max_channel = UFSHCD_MAX_CHANNEL;
8716 host->unique_id = host->host_no;
a851b2bd 8717 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8718
7eb584db
DR		 8719 hba->max_pwr_info.is_valid = false;
8720
7a3e97b0 8721 /* Initialize work queues */
e8e7f271 8722 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8723 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8724
6ccf44fe
SJ		 8725 /* Initialize UIC command mutex */
8726 mutex_init(&hba->uic_cmd_mutex);
8727
5a0b0cb9
SRT		 8728 /* Initialize mutex for device management commands */
8729 mutex_init(&hba->dev_cmd.lock);
8730
a3cd5ec5 8731 init_rwsem(&hba->clk_scaling_lock);
8732
1ab27c9c 8733 ufshcd_init_clk_gating(hba);
199ef13c 8734
eebcc196
VG		 8735 ufshcd_init_clk_scaling(hba);
8736
199ef13c
YG		 8737 /*
8738 * In order to avoid any spurious interrupt immediately after
8739 * registering UFS controller interrupt handler, clear any pending UFS
8740 * interrupt status and disable all the UFS interrupts.
8741 */
8742 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8743 REG_INTERRUPT_STATUS);
8744 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8745 /*
8746 * Make sure that UFS interrupts are disabled and any pending interrupt
8747 * status is cleared before registering UFS interrupt handler.
8748 */
8749 mb();
8750
7a3e97b0 8751 /* IRQ registration */
2953f850 8752 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8753 if (err) {
3b1d0580 8754 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8755 goto exit_gating;
57d104c1
SJ		 8756 } else {
8757 hba->is_irq_enabled = true;
7a3e97b0
SY		 8758 }
8759
3b1d0580 8760 err = scsi_add_host(host, hba->dev);
7a3e97b0 8761 if (err) {
3b1d0580 8762 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8763 goto exit_gating;
7a3e97b0
SY		 8764 }
8765
7252a360
BVA		 8766 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
8767 if (IS_ERR(hba->cmd_queue)) {
8768 err = PTR_ERR(hba->cmd_queue);
8769 goto out_remove_scsi_host;
8770 }
8771
69a6c269
BVA		 8772 hba->tmf_tag_set = (struct blk_mq_tag_set) {
8773 .nr_hw_queues = 1,
8774 .queue_depth = hba->nutmrs,
8775 .ops = &ufshcd_tmf_ops,
8776 .flags = BLK_MQ_F_NO_SCHED,
8777 };
8778 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
8779 if (err < 0)
8780 goto free_cmd_queue;
8781 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
8782 if (IS_ERR(hba->tmf_queue)) {
8783 err = PTR_ERR(hba->tmf_queue);
8784 goto free_tmf_tag_set;
8785 }
8786
d8d9f793
BA		 8787 /* Reset the attached device */
8788 ufshcd_vops_device_reset(hba);
8789
6ccf44fe
SJ		 8790 /* Host controller enable */
8791 err = ufshcd_hba_enable(hba);
7a3e97b0 8792 if (err) {
6ccf44fe 8793 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8794 ufshcd_print_host_regs(hba);
6ba65588 8795 ufshcd_print_host_state(hba);
69a6c269 8796 goto free_tmf_queue;
7a3e97b0 8797 }
6ccf44fe 8798
0c8f7586 8799 /*
8800 * Set the default power management level for runtime and system PM.
8801 * Default power saving mode is to keep UFS link in Hibern8 state
8802 * and UFS device in sleep state.
8803 */
8804 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8805 UFS_SLEEP_PWR_MODE,
8806 UIC_LINK_HIBERN8_STATE);
8807 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8808 UFS_SLEEP_PWR_MODE,
8809 UIC_LINK_HIBERN8_STATE);
8810
ad448378 8811 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 8812 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 8813 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8814 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8815 }
8816
62694735
SRT		 8817 /* Hold auto suspend until async scan completes */
8818 pm_runtime_get_sync(dev);
38135535 8819 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8820 /*
7caf489b 8821 * We are assuming that device wasn't put in sleep/power-down
8822 * state exclusively during the boot stage before kernel.
8823 * This assumption helps avoid doing link startup twice during
8824 * ufshcd_probe_hba().
57d104c1 8825 */
7caf489b 8826 ufshcd_set_ufs_dev_active(hba);
57d104c1 8827
6ccf44fe 8828 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8829 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8830
7a3e97b0
SY		 8831 return 0;
8832
69a6c269
BVA		 8833free_tmf_queue:
8834 blk_cleanup_queue(hba->tmf_queue);
8835free_tmf_tag_set:
8836 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360
BVA		 8837free_cmd_queue:
8838 blk_cleanup_queue(hba->cmd_queue);
3b1d0580
VH		 8839out_remove_scsi_host:
8840 scsi_remove_host(hba->host);
1ab27c9c 8841exit_gating:
eebcc196 8842 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8843 ufshcd_exit_clk_gating(hba);
3b1d0580 8844out_disable:
57d104c1 8845 hba->is_irq_enabled = false;
aa497613 8846 ufshcd_hba_exit(hba);
3b1d0580
VH		 8847out_error:
8848 return err;
8849}
8850EXPORT_SYMBOL_GPL(ufshcd_init);
8851
3b1d0580
VH		 8852MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8853MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8854MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8855MODULE_LICENSE("GPL");
8856MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Linux 6.x block layer and io_uring tree(s)