Commit | Line | Data |
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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
81c0fc51 | 2 | /* |
54b879b7 | 3 | * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. |
81c0fc51 YG |
4 | */ |
5 | ||
6 | #include <linux/time.h> | |
7 | #include <linux/of.h> | |
8 | #include <linux/platform_device.h> | |
9 | #include <linux/phy/phy.h> | |
12fd5f25 | 10 | #include <linux/reset-controller.h> |
4b9ad0b8 | 11 | |
81c0fc51 | 12 | #include "ufshcd.h" |
47555a5c | 13 | #include "ufshcd-pltfrm.h" |
81c0fc51 YG |
14 | #include "unipro.h" |
15 | #include "ufs-qcom.h" | |
16 | #include "ufshci.h" | |
56d4a186 | 17 | #include "ufs_quirks.h" |
6e3fd44d YG |
18 | #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \ |
19 | (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN) | |
20 | ||
21 | enum { | |
22 | TSTBUS_UAWM, | |
23 | TSTBUS_UARM, | |
24 | TSTBUS_TXUC, | |
25 | TSTBUS_RXUC, | |
26 | TSTBUS_DFC, | |
27 | TSTBUS_TRLUT, | |
28 | TSTBUS_TMRLUT, | |
29 | TSTBUS_OCSC, | |
30 | TSTBUS_UTP_HCI, | |
31 | TSTBUS_COMBINED, | |
32 | TSTBUS_WRAPPER, | |
33 | TSTBUS_UNIPRO, | |
34 | TSTBUS_MAX, | |
35 | }; | |
81c0fc51 YG |
36 | |
37 | static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; | |
38 | ||
81c0fc51 | 39 | static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote); |
6e3fd44d | 40 | static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); |
f06fcc71 YG |
41 | static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, |
42 | u32 clk_cycles); | |
43 | ||
12fd5f25 EG |
44 | static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) |
45 | { | |
46 | return container_of(rcd, struct ufs_qcom_host, rcdev); | |
47 | } | |
48 | ||
eba5ed35 | 49 | static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len, |
ba80917d | 50 | const char *prefix, void *priv) |
eba5ed35 | 51 | { |
ba80917d | 52 | ufshcd_dump_regs(hba, offset, len * 4, prefix); |
eba5ed35 YG |
53 | } |
54 | ||
81c0fc51 YG |
55 | static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes) |
56 | { | |
57 | int err = 0; | |
58 | ||
59 | err = ufshcd_dme_get(hba, | |
60 | UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes); | |
61 | if (err) | |
62 | dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n", | |
63 | __func__, err); | |
64 | ||
65 | return err; | |
66 | } | |
67 | ||
68 | static int ufs_qcom_host_clk_get(struct device *dev, | |
5adaf1e8 | 69 | const char *name, struct clk **clk_out, bool optional) |
81c0fc51 YG |
70 | { |
71 | struct clk *clk; | |
72 | int err = 0; | |
73 | ||
74 | clk = devm_clk_get(dev, name); | |
5adaf1e8 | 75 | if (!IS_ERR(clk)) { |
81c0fc51 | 76 | *clk_out = clk; |
5adaf1e8 VG |
77 | return 0; |
78 | } | |
79 | ||
80 | err = PTR_ERR(clk); | |
81 | ||
82 | if (optional && err == -ENOENT) { | |
83 | *clk_out = NULL; | |
84 | return 0; | |
81c0fc51 YG |
85 | } |
86 | ||
5adaf1e8 VG |
87 | if (err != -EPROBE_DEFER) |
88 | dev_err(dev, "failed to get %s err %d\n", name, err); | |
89 | ||
81c0fc51 YG |
90 | return err; |
91 | } | |
92 | ||
93 | static int ufs_qcom_host_clk_enable(struct device *dev, | |
94 | const char *name, struct clk *clk) | |
95 | { | |
96 | int err = 0; | |
97 | ||
98 | err = clk_prepare_enable(clk); | |
99 | if (err) | |
100 | dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); | |
101 | ||
102 | return err; | |
103 | } | |
104 | ||
105 | static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) | |
106 | { | |
107 | if (!host->is_lane_clks_enabled) | |
108 | return; | |
109 | ||
5adaf1e8 | 110 | clk_disable_unprepare(host->tx_l1_sync_clk); |
81c0fc51 | 111 | clk_disable_unprepare(host->tx_l0_sync_clk); |
5adaf1e8 | 112 | clk_disable_unprepare(host->rx_l1_sync_clk); |
81c0fc51 YG |
113 | clk_disable_unprepare(host->rx_l0_sync_clk); |
114 | ||
115 | host->is_lane_clks_enabled = false; | |
116 | } | |
117 | ||
118 | static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) | |
119 | { | |
120 | int err = 0; | |
121 | struct device *dev = host->hba->dev; | |
122 | ||
123 | if (host->is_lane_clks_enabled) | |
124 | return 0; | |
125 | ||
126 | err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", | |
127 | host->rx_l0_sync_clk); | |
128 | if (err) | |
129 | goto out; | |
130 | ||
131 | err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", | |
132 | host->tx_l0_sync_clk); | |
133 | if (err) | |
134 | goto disable_rx_l0; | |
135 | ||
5adaf1e8 | 136 | err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", |
54b879b7 | 137 | host->rx_l1_sync_clk); |
5adaf1e8 VG |
138 | if (err) |
139 | goto disable_tx_l0; | |
81c0fc51 | 140 | |
5adaf1e8 | 141 | err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", |
54b879b7 | 142 | host->tx_l1_sync_clk); |
5adaf1e8 VG |
143 | if (err) |
144 | goto disable_rx_l1; | |
81c0fc51 YG |
145 | |
146 | host->is_lane_clks_enabled = true; | |
147 | goto out; | |
148 | ||
149 | disable_rx_l1: | |
5adaf1e8 | 150 | clk_disable_unprepare(host->rx_l1_sync_clk); |
81c0fc51 YG |
151 | disable_tx_l0: |
152 | clk_disable_unprepare(host->tx_l0_sync_clk); | |
153 | disable_rx_l0: | |
154 | clk_disable_unprepare(host->rx_l0_sync_clk); | |
155 | out: | |
156 | return err; | |
157 | } | |
158 | ||
159 | static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) | |
160 | { | |
161 | int err = 0; | |
162 | struct device *dev = host->hba->dev; | |
163 | ||
5adaf1e8 VG |
164 | err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", |
165 | &host->rx_l0_sync_clk, false); | |
81c0fc51 YG |
166 | if (err) |
167 | goto out; | |
168 | ||
5adaf1e8 VG |
169 | err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", |
170 | &host->tx_l0_sync_clk, false); | |
81c0fc51 YG |
171 | if (err) |
172 | goto out; | |
173 | ||
54b879b7 YG |
174 | /* In case of single lane per direction, don't read lane1 clocks */ |
175 | if (host->hba->lanes_per_direction > 1) { | |
176 | err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", | |
5adaf1e8 | 177 | &host->rx_l1_sync_clk, false); |
54b879b7 YG |
178 | if (err) |
179 | goto out; | |
f06fcc71 | 180 | |
54b879b7 | 181 | err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", |
5adaf1e8 | 182 | &host->tx_l1_sync_clk, true); |
54b879b7 | 183 | } |
81c0fc51 YG |
184 | out: |
185 | return err; | |
186 | } | |
187 | ||
188 | static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba) | |
189 | { | |
81c0fc51 | 190 | u32 tx_lanes; |
81c0fc51 | 191 | |
1e1e465c | 192 | return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes); |
81c0fc51 YG |
193 | } |
194 | ||
195 | static int ufs_qcom_check_hibern8(struct ufs_hba *hba) | |
196 | { | |
197 | int err; | |
198 | u32 tx_fsm_val = 0; | |
199 | unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); | |
200 | ||
201 | do { | |
202 | err = ufshcd_dme_get(hba, | |
f06fcc71 YG |
203 | UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, |
204 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), | |
205 | &tx_fsm_val); | |
81c0fc51 YG |
206 | if (err || tx_fsm_val == TX_FSM_HIBERN8) |
207 | break; | |
208 | ||
209 | /* sleep for max. 200us */ | |
210 | usleep_range(100, 200); | |
211 | } while (time_before(jiffies, timeout)); | |
212 | ||
213 | /* | |
214 | * we might have scheduled out for long during polling so | |
215 | * check the state again. | |
216 | */ | |
217 | if (time_after(jiffies, timeout)) | |
218 | err = ufshcd_dme_get(hba, | |
f06fcc71 YG |
219 | UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, |
220 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), | |
221 | &tx_fsm_val); | |
81c0fc51 YG |
222 | |
223 | if (err) { | |
224 | dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", | |
225 | __func__, err); | |
226 | } else if (tx_fsm_val != TX_FSM_HIBERN8) { | |
227 | err = tx_fsm_val; | |
228 | dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", | |
229 | __func__, err); | |
230 | } | |
231 | ||
232 | return err; | |
233 | } | |
234 | ||
f06fcc71 YG |
235 | static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) |
236 | { | |
237 | ufshcd_rmwl(host->hba, QUNIPRO_SEL, | |
238 | ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, | |
239 | REG_UFS_CFG1); | |
240 | /* make sure above configuration is applied before we return */ | |
241 | mb(); | |
242 | } | |
243 | ||
81c0fc51 YG |
244 | static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) |
245 | { | |
1ce5898a | 246 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
247 | struct phy *phy = host->generic_phy; |
248 | int ret = 0; | |
81c0fc51 YG |
249 | bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B) |
250 | ? true : false; | |
251 | ||
e9dc42c7 VG |
252 | if (is_rate_B) |
253 | phy_set_mode(phy, PHY_MODE_UFS_HS_B); | |
254 | ||
052553af VG |
255 | /* phy initialization - calibrate the phy */ |
256 | ret = phy_init(phy); | |
81c0fc51 | 257 | if (ret) { |
052553af | 258 | dev_err(hba->dev, "%s: phy init failed, ret = %d\n", |
4b9ad0b8 | 259 | __func__, ret); |
81c0fc51 YG |
260 | goto out; |
261 | } | |
262 | ||
052553af VG |
263 | /* power on phy - start serdes and phy's power and clocks */ |
264 | ret = phy_power_on(phy); | |
81c0fc51 | 265 | if (ret) { |
052553af | 266 | dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", |
81c0fc51 | 267 | __func__, ret); |
052553af | 268 | goto out_disable_phy; |
81c0fc51 YG |
269 | } |
270 | ||
f06fcc71 YG |
271 | ufs_qcom_select_unipro_mode(host); |
272 | ||
052553af VG |
273 | return 0; |
274 | ||
275 | out_disable_phy: | |
052553af | 276 | phy_exit(phy); |
81c0fc51 YG |
277 | out: |
278 | return ret; | |
279 | } | |
280 | ||
281 | /* | |
282 | * The UTP controller has a number of internal clock gating cells (CGCs). | |
283 | * Internal hardware sub-modules within the UTP controller control the CGCs. | |
284 | * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved | |
285 | * in a specific operation, UTP controller CGCs are by default disabled and | |
286 | * this function enables them (after every UFS link startup) to save some power | |
287 | * leakage. | |
288 | */ | |
289 | static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) | |
290 | { | |
291 | ufshcd_writel(hba, | |
292 | ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, | |
293 | REG_UFS_CFG2); | |
294 | ||
295 | /* Ensure that HW clock gating is enabled before next operations */ | |
296 | mb(); | |
297 | } | |
298 | ||
f06fcc71 YG |
299 | static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, |
300 | enum ufs_notify_change_status status) | |
81c0fc51 | 301 | { |
1ce5898a | 302 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
303 | int err = 0; |
304 | ||
305 | switch (status) { | |
306 | case PRE_CHANGE: | |
307 | ufs_qcom_power_up_sequence(hba); | |
308 | /* | |
309 | * The PHY PLL output is the source of tx/rx lane symbol | |
310 | * clocks, hence, enable the lane clocks only after PHY | |
311 | * is initialized. | |
312 | */ | |
313 | err = ufs_qcom_enable_lane_clks(host); | |
314 | break; | |
315 | case POST_CHANGE: | |
316 | /* check if UFS PHY moved from DISABLED to HIBERN8 */ | |
317 | err = ufs_qcom_check_hibern8(hba); | |
318 | ufs_qcom_enable_hw_clk_gating(hba); | |
319 | ||
320 | break; | |
321 | default: | |
322 | dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); | |
323 | err = -EINVAL; | |
324 | break; | |
325 | } | |
326 | return err; | |
327 | } | |
328 | ||
329 | /** | |
f06fcc71 | 330 | * Returns zero for success and non-zero in case of a failure |
81c0fc51 | 331 | */ |
f06fcc71 YG |
332 | static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, |
333 | u32 hs, u32 rate, bool update_link_startup_timer) | |
81c0fc51 | 334 | { |
f06fcc71 | 335 | int ret = 0; |
1ce5898a | 336 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
337 | struct ufs_clk_info *clki; |
338 | u32 core_clk_period_in_ns; | |
339 | u32 tx_clk_cycles_per_us = 0; | |
340 | unsigned long core_clk_rate = 0; | |
341 | u32 core_clk_cycles_per_us = 0; | |
342 | ||
343 | static u32 pwm_fr_table[][2] = { | |
344 | {UFS_PWM_G1, 0x1}, | |
345 | {UFS_PWM_G2, 0x1}, | |
346 | {UFS_PWM_G3, 0x1}, | |
347 | {UFS_PWM_G4, 0x1}, | |
348 | }; | |
349 | ||
350 | static u32 hs_fr_table_rA[][2] = { | |
351 | {UFS_HS_G1, 0x1F}, | |
352 | {UFS_HS_G2, 0x3e}, | |
f06fcc71 | 353 | {UFS_HS_G3, 0x7D}, |
81c0fc51 YG |
354 | }; |
355 | ||
356 | static u32 hs_fr_table_rB[][2] = { | |
357 | {UFS_HS_G1, 0x24}, | |
358 | {UFS_HS_G2, 0x49}, | |
f06fcc71 | 359 | {UFS_HS_G3, 0x92}, |
81c0fc51 YG |
360 | }; |
361 | ||
81c7e06a YG |
362 | /* |
363 | * The Qunipro controller does not use following registers: | |
364 | * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & | |
365 | * UFS_REG_PA_LINK_STARTUP_TIMER | |
366 | * But UTP controller uses SYS1CLK_1US_REG register for Interrupt | |
367 | * Aggregation logic. | |
368 | */ | |
369 | if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) | |
370 | goto out; | |
371 | ||
81c0fc51 YG |
372 | if (gear == 0) { |
373 | dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); | |
374 | goto out_error; | |
375 | } | |
376 | ||
377 | list_for_each_entry(clki, &hba->clk_list_head, list) { | |
378 | if (!strcmp(clki->name, "core_clk")) | |
379 | core_clk_rate = clk_get_rate(clki->clk); | |
380 | } | |
381 | ||
382 | /* If frequency is smaller than 1MHz, set to 1MHz */ | |
383 | if (core_clk_rate < DEFAULT_CLK_RATE_HZ) | |
384 | core_clk_rate = DEFAULT_CLK_RATE_HZ; | |
385 | ||
386 | core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; | |
f06fcc71 YG |
387 | if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { |
388 | ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); | |
389 | /* | |
390 | * make sure above write gets applied before we return from | |
391 | * this function. | |
392 | */ | |
393 | mb(); | |
394 | } | |
395 | ||
396 | if (ufs_qcom_cap_qunipro(host)) | |
397 | goto out; | |
81c0fc51 YG |
398 | |
399 | core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; | |
400 | core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; | |
401 | core_clk_period_in_ns &= MASK_CLK_NS_REG; | |
402 | ||
403 | switch (hs) { | |
404 | case FASTAUTO_MODE: | |
405 | case FAST_MODE: | |
406 | if (rate == PA_HS_MODE_A) { | |
407 | if (gear > ARRAY_SIZE(hs_fr_table_rA)) { | |
408 | dev_err(hba->dev, | |
409 | "%s: index %d exceeds table size %zu\n", | |
410 | __func__, gear, | |
411 | ARRAY_SIZE(hs_fr_table_rA)); | |
412 | goto out_error; | |
413 | } | |
414 | tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; | |
415 | } else if (rate == PA_HS_MODE_B) { | |
416 | if (gear > ARRAY_SIZE(hs_fr_table_rB)) { | |
417 | dev_err(hba->dev, | |
418 | "%s: index %d exceeds table size %zu\n", | |
419 | __func__, gear, | |
420 | ARRAY_SIZE(hs_fr_table_rB)); | |
421 | goto out_error; | |
422 | } | |
423 | tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; | |
424 | } else { | |
425 | dev_err(hba->dev, "%s: invalid rate = %d\n", | |
426 | __func__, rate); | |
427 | goto out_error; | |
428 | } | |
429 | break; | |
430 | case SLOWAUTO_MODE: | |
431 | case SLOW_MODE: | |
432 | if (gear > ARRAY_SIZE(pwm_fr_table)) { | |
433 | dev_err(hba->dev, | |
434 | "%s: index %d exceeds table size %zu\n", | |
435 | __func__, gear, | |
436 | ARRAY_SIZE(pwm_fr_table)); | |
437 | goto out_error; | |
438 | } | |
439 | tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; | |
440 | break; | |
441 | case UNCHANGED: | |
442 | default: | |
443 | dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); | |
444 | goto out_error; | |
445 | } | |
446 | ||
f06fcc71 YG |
447 | if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != |
448 | (core_clk_period_in_ns | tx_clk_cycles_per_us)) { | |
449 | /* this register 2 fields shall be written at once */ | |
450 | ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, | |
451 | REG_UFS_TX_SYMBOL_CLK_NS_US); | |
452 | /* | |
453 | * make sure above write gets applied before we return from | |
454 | * this function. | |
455 | */ | |
456 | mb(); | |
457 | } | |
458 | ||
459 | if (update_link_startup_timer) { | |
460 | ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), | |
461 | REG_UFS_PA_LINK_STARTUP_TIMER); | |
462 | /* | |
463 | * make sure that this configuration is applied before | |
464 | * we return | |
465 | */ | |
466 | mb(); | |
467 | } | |
81c0fc51 YG |
468 | goto out; |
469 | ||
470 | out_error: | |
f06fcc71 | 471 | ret = -EINVAL; |
81c0fc51 | 472 | out: |
f06fcc71 | 473 | return ret; |
81c0fc51 YG |
474 | } |
475 | ||
f06fcc71 YG |
476 | static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, |
477 | enum ufs_notify_change_status status) | |
81c0fc51 | 478 | { |
f06fcc71 YG |
479 | int err = 0; |
480 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
81c0fc51 YG |
481 | |
482 | switch (status) { | |
483 | case PRE_CHANGE: | |
f06fcc71 YG |
484 | if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, |
485 | 0, true)) { | |
81c0fc51 YG |
486 | dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", |
487 | __func__); | |
f06fcc71 YG |
488 | err = -EINVAL; |
489 | goto out; | |
81c0fc51 | 490 | } |
f06fcc71 YG |
491 | |
492 | if (ufs_qcom_cap_qunipro(host)) | |
493 | /* | |
494 | * set unipro core clock cycles to 150 & clear clock | |
495 | * divider | |
496 | */ | |
497 | err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, | |
498 | 150); | |
499 | ||
4b9ad0b8 YG |
500 | /* |
501 | * Some UFS devices (and may be host) have issues if LCC is | |
502 | * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 | |
503 | * before link startup which will make sure that both host | |
504 | * and device TX LCC are disabled once link startup is | |
505 | * completed. | |
506 | */ | |
507 | if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) | |
508 | err = ufshcd_dme_set(hba, | |
509 | UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), | |
510 | 0); | |
511 | ||
81c0fc51 YG |
512 | break; |
513 | case POST_CHANGE: | |
514 | ufs_qcom_link_startup_post_change(hba); | |
515 | break; | |
516 | default: | |
517 | break; | |
518 | } | |
519 | ||
f06fcc71 YG |
520 | out: |
521 | return err; | |
81c0fc51 YG |
522 | } |
523 | ||
524 | static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) | |
525 | { | |
1ce5898a | 526 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
527 | struct phy *phy = host->generic_phy; |
528 | int ret = 0; | |
529 | ||
530 | if (ufs_qcom_is_link_off(hba)) { | |
531 | /* | |
532 | * Disable the tx/rx lane symbol clocks before PHY is | |
533 | * powered down as the PLL source should be disabled | |
534 | * after downstream clocks are disabled. | |
535 | */ | |
536 | ufs_qcom_disable_lane_clks(host); | |
537 | phy_power_off(phy); | |
81c0fc51 | 538 | |
3f6d1767 | 539 | } else if (!ufs_qcom_is_link_active(hba)) { |
f06fcc71 | 540 | ufs_qcom_disable_lane_clks(host); |
f06fcc71 | 541 | } |
81c0fc51 | 542 | |
81c0fc51 YG |
543 | return ret; |
544 | } | |
545 | ||
546 | static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) | |
547 | { | |
1ce5898a | 548 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
549 | struct phy *phy = host->generic_phy; |
550 | int err; | |
551 | ||
3f6d1767 EG |
552 | if (ufs_qcom_is_link_off(hba)) { |
553 | err = phy_power_on(phy); | |
554 | if (err) { | |
555 | dev_err(hba->dev, "%s: failed PHY power on: %d\n", | |
556 | __func__, err); | |
557 | return err; | |
558 | } | |
81c0fc51 | 559 | |
3f6d1767 EG |
560 | err = ufs_qcom_enable_lane_clks(host); |
561 | if (err) | |
562 | return err; | |
f06fcc71 | 563 | |
3f6d1767 EG |
564 | } else if (!ufs_qcom_is_link_active(hba)) { |
565 | err = ufs_qcom_enable_lane_clks(host); | |
566 | if (err) | |
567 | return err; | |
568 | } | |
81c0fc51 | 569 | |
3f6d1767 EG |
570 | hba->is_sys_suspended = false; |
571 | return 0; | |
81c0fc51 YG |
572 | } |
573 | ||
f06fcc71 YG |
574 | #ifdef CONFIG_MSM_BUS_SCALING |
575 | static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host, | |
576 | const char *speed_mode) | |
577 | { | |
578 | struct device *dev = host->hba->dev; | |
579 | struct device_node *np = dev->of_node; | |
580 | int err; | |
581 | const char *key = "qcom,bus-vector-names"; | |
582 | ||
583 | if (!speed_mode) { | |
584 | err = -EINVAL; | |
585 | goto out; | |
586 | } | |
587 | ||
588 | if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN")) | |
589 | err = of_property_match_string(np, key, "MAX"); | |
590 | else | |
591 | err = of_property_match_string(np, key, speed_mode); | |
592 | ||
593 | out: | |
594 | if (err < 0) | |
595 | dev_err(dev, "%s: Invalid %s mode %d\n", | |
596 | __func__, speed_mode, err); | |
597 | return err; | |
598 | } | |
599 | ||
600 | static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result) | |
601 | { | |
602 | int gear = max_t(u32, p->gear_rx, p->gear_tx); | |
603 | int lanes = max_t(u32, p->lane_rx, p->lane_tx); | |
604 | int pwr; | |
605 | ||
606 | /* default to PWM Gear 1, Lane 1 if power mode is not initialized */ | |
607 | if (!gear) | |
608 | gear = 1; | |
609 | ||
610 | if (!lanes) | |
611 | lanes = 1; | |
612 | ||
613 | if (!p->pwr_rx && !p->pwr_tx) { | |
614 | pwr = SLOWAUTO_MODE; | |
615 | snprintf(result, BUS_VECTOR_NAME_LEN, "MIN"); | |
616 | } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE || | |
617 | p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) { | |
618 | pwr = FAST_MODE; | |
619 | snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS", | |
620 | p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes); | |
621 | } else { | |
622 | pwr = SLOW_MODE; | |
623 | snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d", | |
624 | "PWM", gear, lanes); | |
625 | } | |
626 | } | |
627 | ||
628 | static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote) | |
629 | { | |
630 | int err = 0; | |
631 | ||
632 | if (vote != host->bus_vote.curr_vote) { | |
633 | err = msm_bus_scale_client_update_request( | |
634 | host->bus_vote.client_handle, vote); | |
635 | if (err) { | |
636 | dev_err(host->hba->dev, | |
637 | "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n", | |
638 | __func__, host->bus_vote.client_handle, | |
639 | vote, err); | |
640 | goto out; | |
641 | } | |
642 | ||
643 | host->bus_vote.curr_vote = vote; | |
644 | } | |
645 | out: | |
646 | return err; | |
647 | } | |
648 | ||
81c0fc51 YG |
649 | static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host) |
650 | { | |
651 | int vote; | |
652 | int err = 0; | |
653 | char mode[BUS_VECTOR_NAME_LEN]; | |
654 | ||
655 | ufs_qcom_get_speed_mode(&host->dev_req_params, mode); | |
656 | ||
657 | vote = ufs_qcom_get_bus_vote(host, mode); | |
658 | if (vote >= 0) | |
659 | err = ufs_qcom_set_bus_vote(host, vote); | |
660 | else | |
661 | err = vote; | |
662 | ||
663 | if (err) | |
664 | dev_err(host->hba->dev, "%s: failed %d\n", __func__, err); | |
665 | else | |
666 | host->bus_vote.saved_vote = vote; | |
667 | return err; | |
668 | } | |
669 | ||
f06fcc71 YG |
670 | static ssize_t |
671 | show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr, | |
672 | char *buf) | |
673 | { | |
674 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
675 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
676 | ||
677 | return snprintf(buf, PAGE_SIZE, "%u\n", | |
678 | host->bus_vote.is_max_bw_needed); | |
679 | } | |
680 | ||
681 | static ssize_t | |
682 | store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr, | |
683 | const char *buf, size_t count) | |
684 | { | |
685 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
686 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
687 | uint32_t value; | |
688 | ||
689 | if (!kstrtou32(buf, 0, &value)) { | |
690 | host->bus_vote.is_max_bw_needed = !!value; | |
691 | ufs_qcom_update_bus_bw_vote(host); | |
692 | } | |
693 | ||
694 | return count; | |
695 | } | |
696 | ||
697 | static int ufs_qcom_bus_register(struct ufs_qcom_host *host) | |
698 | { | |
699 | int err; | |
700 | struct msm_bus_scale_pdata *bus_pdata; | |
701 | struct device *dev = host->hba->dev; | |
702 | struct platform_device *pdev = to_platform_device(dev); | |
703 | struct device_node *np = dev->of_node; | |
704 | ||
705 | bus_pdata = msm_bus_cl_get_pdata(pdev); | |
706 | if (!bus_pdata) { | |
707 | dev_err(dev, "%s: failed to get bus vectors\n", __func__); | |
708 | err = -ENODATA; | |
709 | goto out; | |
710 | } | |
711 | ||
712 | err = of_property_count_strings(np, "qcom,bus-vector-names"); | |
713 | if (err < 0 || err != bus_pdata->num_usecases) { | |
714 | dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n", | |
715 | __func__, err); | |
716 | goto out; | |
717 | } | |
718 | ||
719 | host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata); | |
720 | if (!host->bus_vote.client_handle) { | |
721 | dev_err(dev, "%s: msm_bus_scale_register_client failed\n", | |
722 | __func__); | |
723 | err = -EFAULT; | |
724 | goto out; | |
725 | } | |
726 | ||
727 | /* cache the vote index for minimum and maximum bandwidth */ | |
728 | host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN"); | |
729 | host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX"); | |
730 | ||
731 | host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw; | |
732 | host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw; | |
733 | sysfs_attr_init(&host->bus_vote.max_bus_bw.attr); | |
734 | host->bus_vote.max_bus_bw.attr.name = "max_bus_bw"; | |
735 | host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR; | |
736 | err = device_create_file(dev, &host->bus_vote.max_bus_bw); | |
737 | out: | |
738 | return err; | |
739 | } | |
740 | #else /* CONFIG_MSM_BUS_SCALING */ | |
741 | static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host) | |
742 | { | |
743 | return 0; | |
744 | } | |
745 | ||
746 | static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote) | |
747 | { | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static int ufs_qcom_bus_register(struct ufs_qcom_host *host) | |
752 | { | |
753 | return 0; | |
754 | } | |
755 | #endif /* CONFIG_MSM_BUS_SCALING */ | |
756 | ||
757 | static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) | |
758 | { | |
759 | if (host->dev_ref_clk_ctrl_mmio && | |
760 | (enable ^ host->is_dev_ref_clk_enabled)) { | |
761 | u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); | |
762 | ||
763 | if (enable) | |
764 | temp |= host->dev_ref_clk_en_mask; | |
765 | else | |
766 | temp &= ~host->dev_ref_clk_en_mask; | |
767 | ||
768 | /* | |
769 | * If we are here to disable this clock it might be immediately | |
770 | * after entering into hibern8 in which case we need to make | |
771 | * sure that device ref_clk is active at least 1us after the | |
772 | * hibern8 enter. | |
773 | */ | |
774 | if (!enable) | |
775 | udelay(1); | |
776 | ||
777 | writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); | |
778 | ||
779 | /* ensure that ref_clk is enabled/disabled before we return */ | |
780 | wmb(); | |
781 | ||
782 | /* | |
783 | * If we call hibern8 exit after this, we need to make sure that | |
784 | * device ref_clk is stable for at least 1us before the hibern8 | |
785 | * exit command. | |
786 | */ | |
787 | if (enable) | |
788 | udelay(1); | |
789 | ||
790 | host->is_dev_ref_clk_enabled = enable; | |
791 | } | |
792 | } | |
793 | ||
81c0fc51 | 794 | static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, |
f06fcc71 | 795 | enum ufs_notify_change_status status, |
81c0fc51 YG |
796 | struct ufs_pa_layer_attr *dev_max_params, |
797 | struct ufs_pa_layer_attr *dev_req_params) | |
798 | { | |
799 | u32 val; | |
1ce5898a | 800 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
e4c0ee3f | 801 | struct ufs_dev_params ufs_qcom_cap; |
81c0fc51 | 802 | int ret = 0; |
81c0fc51 YG |
803 | |
804 | if (!dev_req_params) { | |
805 | pr_err("%s: incoming dev_req_params is NULL\n", __func__); | |
806 | ret = -EINVAL; | |
807 | goto out; | |
808 | } | |
809 | ||
810 | switch (status) { | |
811 | case PRE_CHANGE: | |
812 | ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX; | |
813 | ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX; | |
814 | ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX; | |
815 | ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX; | |
816 | ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX; | |
817 | ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX; | |
818 | ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM; | |
819 | ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM; | |
820 | ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS; | |
821 | ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS; | |
822 | ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; | |
823 | ufs_qcom_cap.desired_working_mode = | |
824 | UFS_QCOM_LIMIT_DESIRED_MODE; | |
825 | ||
f06fcc71 YG |
826 | if (host->hw_ver.major == 0x1) { |
827 | /* | |
828 | * HS-G3 operations may not reliably work on legacy QCOM | |
829 | * UFS host controller hardware even though capability | |
830 | * exchange during link startup phase may end up | |
831 | * negotiating maximum supported gear as G3. | |
832 | * Hence downgrade the maximum supported gear to HS-G2. | |
833 | */ | |
834 | if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) | |
835 | ufs_qcom_cap.hs_tx_gear = UFS_HS_G2; | |
836 | if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) | |
837 | ufs_qcom_cap.hs_rx_gear = UFS_HS_G2; | |
838 | } | |
839 | ||
e4c0ee3f SC |
840 | ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, |
841 | dev_max_params, | |
842 | dev_req_params); | |
81c0fc51 YG |
843 | if (ret) { |
844 | pr_err("%s: failed to determine capabilities\n", | |
845 | __func__); | |
846 | goto out; | |
847 | } | |
848 | ||
f37aabcf YG |
849 | /* enable the device ref clock before changing to HS mode */ |
850 | if (!ufshcd_is_hs_mode(&hba->pwr_info) && | |
851 | ufshcd_is_hs_mode(dev_req_params)) | |
852 | ufs_qcom_dev_ref_clk_ctrl(host, true); | |
81c0fc51 YG |
853 | break; |
854 | case POST_CHANGE: | |
f06fcc71 | 855 | if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, |
81c0fc51 | 856 | dev_req_params->pwr_rx, |
f06fcc71 | 857 | dev_req_params->hs_rate, false)) { |
81c0fc51 YG |
858 | dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", |
859 | __func__); | |
860 | /* | |
861 | * we return error code at the end of the routine, | |
862 | * but continue to configure UFS_PHY_TX_LANE_ENABLE | |
863 | * and bus voting as usual | |
864 | */ | |
865 | ret = -EINVAL; | |
866 | } | |
867 | ||
868 | val = ~(MAX_U32 << dev_req_params->lane_tx); | |
81c0fc51 YG |
869 | |
870 | /* cache the power mode parameters to use internally */ | |
871 | memcpy(&host->dev_req_params, | |
872 | dev_req_params, sizeof(*dev_req_params)); | |
873 | ufs_qcom_update_bus_bw_vote(host); | |
f37aabcf YG |
874 | |
875 | /* disable the device ref clock if entered PWM mode */ | |
876 | if (ufshcd_is_hs_mode(&hba->pwr_info) && | |
877 | !ufshcd_is_hs_mode(dev_req_params)) | |
878 | ufs_qcom_dev_ref_clk_ctrl(host, false); | |
81c0fc51 YG |
879 | break; |
880 | default: | |
881 | ret = -EINVAL; | |
882 | break; | |
883 | } | |
884 | out: | |
885 | return ret; | |
886 | } | |
887 | ||
56d4a186 SJ |
888 | static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) |
889 | { | |
890 | int err; | |
891 | u32 pa_vs_config_reg1; | |
892 | ||
893 | err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), | |
894 | &pa_vs_config_reg1); | |
895 | if (err) | |
896 | goto out; | |
897 | ||
898 | /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ | |
899 | err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), | |
900 | (pa_vs_config_reg1 | (1 << 12))); | |
901 | ||
902 | out: | |
903 | return err; | |
904 | } | |
905 | ||
906 | static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) | |
907 | { | |
908 | int err = 0; | |
909 | ||
910 | if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) | |
911 | err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); | |
912 | ||
913 | return err; | |
914 | } | |
915 | ||
ae977587 YG |
916 | static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) |
917 | { | |
1ce5898a | 918 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
ae977587 YG |
919 | |
920 | if (host->hw_ver.major == 0x1) | |
921 | return UFSHCI_VERSION_11; | |
922 | else | |
923 | return UFSHCI_VERSION_20; | |
924 | } | |
925 | ||
81c0fc51 YG |
926 | /** |
927 | * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks | |
928 | * @hba: host controller instance | |
929 | * | |
930 | * QCOM UFS host controller might have some non standard behaviours (quirks) | |
931 | * than what is specified by UFSHCI specification. Advertise all such | |
932 | * quirks to standard UFS host controller driver so standard takes them into | |
933 | * account. | |
934 | */ | |
935 | static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) | |
936 | { | |
1ce5898a | 937 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 | 938 | |
81c7e06a | 939 | if (host->hw_ver.major == 0x01) { |
8163743e | 940 | hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS |
2c0cc2e2 YG |
941 | | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP |
942 | | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; | |
81c0fc51 | 943 | |
81c7e06a YG |
944 | if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) |
945 | hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; | |
f06fcc71 YG |
946 | |
947 | hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; | |
81c7e06a YG |
948 | } |
949 | ||
69a6fff0 | 950 | if (host->hw_ver.major == 0x2) { |
ae977587 | 951 | hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; |
2f018378 | 952 | |
cad2e03d YG |
953 | if (!ufs_qcom_cap_qunipro(host)) |
954 | /* Legacy UniPro mode still need following quirks */ | |
8163743e | 955 | hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS |
2c0cc2e2 | 956 | | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE |
8163743e | 957 | | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); |
cad2e03d YG |
958 | } |
959 | } | |
960 | ||
961 | static void ufs_qcom_set_caps(struct ufs_hba *hba) | |
962 | { | |
1ce5898a | 963 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
cad2e03d | 964 | |
f06fcc71 YG |
965 | hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; |
966 | hba->caps |= UFSHCD_CAP_CLK_SCALING; | |
967 | hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
81c0fc51 | 968 | |
f06fcc71 YG |
969 | if (host->hw_ver.major >= 0x2) { |
970 | host->caps = UFS_QCOM_CAP_QUNIPRO | | |
971 | UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; | |
81c0fc51 YG |
972 | } |
973 | } | |
974 | ||
f06fcc71 YG |
975 | /** |
976 | * ufs_qcom_setup_clocks - enables/disable clocks | |
977 | * @hba: host controller instance | |
978 | * @on: If true, enable clocks else disable them. | |
1e879e8f | 979 | * @status: PRE_CHANGE or POST_CHANGE notify |
f06fcc71 YG |
980 | * |
981 | * Returns 0 on success, non-zero on failure. | |
982 | */ | |
1e879e8f SJ |
983 | static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, |
984 | enum ufs_notify_change_status status) | |
81c0fc51 | 985 | { |
1ce5898a | 986 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
f06fcc71 | 987 | int err; |
81c0fc51 YG |
988 | int vote = 0; |
989 | ||
990 | /* | |
991 | * In case ufs_qcom_init() is not yet done, simply ignore. | |
992 | * This ufs_qcom_setup_clocks() shall be called from | |
993 | * ufs_qcom_init() after init is done. | |
994 | */ | |
995 | if (!host) | |
996 | return 0; | |
997 | ||
1e879e8f | 998 | if (on && (status == POST_CHANGE)) { |
f37aabcf YG |
999 | /* enable the device ref clock for HS mode*/ |
1000 | if (ufshcd_is_hs_mode(&hba->pwr_info)) | |
1001 | ufs_qcom_dev_ref_clk_ctrl(host, true); | |
81c0fc51 YG |
1002 | vote = host->bus_vote.saved_vote; |
1003 | if (vote == host->bus_vote.min_bw_vote) | |
1004 | ufs_qcom_update_bus_bw_vote(host); | |
f06fcc71 | 1005 | |
1e879e8f | 1006 | } else if (!on && (status == PRE_CHANGE)) { |
feb3d798 | 1007 | if (!ufs_qcom_is_link_active(hba)) { |
81c0fc51 | 1008 | /* disable device ref_clk */ |
f06fcc71 | 1009 | ufs_qcom_dev_ref_clk_ctrl(host, false); |
feb3d798 VG |
1010 | } |
1011 | ||
81c0fc51 YG |
1012 | vote = host->bus_vote.min_bw_vote; |
1013 | } | |
1014 | ||
1015 | err = ufs_qcom_set_bus_vote(host, vote); | |
1016 | if (err) | |
1017 | dev_err(hba->dev, "%s: set bus vote failed %d\n", | |
1018 | __func__, err); | |
1019 | ||
81c0fc51 YG |
1020 | return err; |
1021 | } | |
1022 | ||
12fd5f25 EG |
1023 | static int |
1024 | ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) | |
1025 | { | |
1026 | struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); | |
1027 | ||
1028 | /* Currently this code only knows about a single reset. */ | |
1029 | WARN_ON(id); | |
1030 | ufs_qcom_assert_reset(host->hba); | |
1031 | /* provide 1ms delay to let the reset pulse propagate. */ | |
1032 | usleep_range(1000, 1100); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static int | |
1037 | ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) | |
1038 | { | |
1039 | struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); | |
1040 | ||
1041 | /* Currently this code only knows about a single reset. */ | |
1042 | WARN_ON(id); | |
1043 | ufs_qcom_deassert_reset(host->hba); | |
1044 | ||
1045 | /* | |
1046 | * after reset deassertion, phy will need all ref clocks, | |
1047 | * voltage, current to settle down before starting serdes. | |
1048 | */ | |
1049 | usleep_range(1000, 1100); | |
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | static const struct reset_control_ops ufs_qcom_reset_ops = { | |
1054 | .assert = ufs_qcom_reset_assert, | |
1055 | .deassert = ufs_qcom_reset_deassert, | |
1056 | }; | |
1057 | ||
81c0fc51 YG |
1058 | #define ANDROID_BOOT_DEV_MAX 30 |
1059 | static char android_boot_dev[ANDROID_BOOT_DEV_MAX]; | |
fb819ee8 YG |
1060 | |
1061 | #ifndef MODULE | |
1062 | static int __init get_android_boot_dev(char *str) | |
81c0fc51 YG |
1063 | { |
1064 | strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX); | |
1065 | return 1; | |
1066 | } | |
1067 | __setup("androidboot.bootdevice=", get_android_boot_dev); | |
fb819ee8 | 1068 | #endif |
81c0fc51 YG |
1069 | |
1070 | /** | |
1071 | * ufs_qcom_init - bind phy with controller | |
1072 | * @hba: host controller instance | |
1073 | * | |
1074 | * Binds PHY with controller and powers up PHY enabling clocks | |
1075 | * and regulators. | |
1076 | * | |
1077 | * Returns -EPROBE_DEFER if binding fails, returns negative error | |
1078 | * on phy power up failure and returns zero on success. | |
1079 | */ | |
1080 | static int ufs_qcom_init(struct ufs_hba *hba) | |
1081 | { | |
1082 | int err; | |
1083 | struct device *dev = hba->dev; | |
f06fcc71 | 1084 | struct platform_device *pdev = to_platform_device(dev); |
81c0fc51 | 1085 | struct ufs_qcom_host *host; |
f06fcc71 | 1086 | struct resource *res; |
81c0fc51 YG |
1087 | |
1088 | if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev))) | |
1089 | return -ENODEV; | |
1090 | ||
1091 | host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); | |
1092 | if (!host) { | |
1093 | err = -ENOMEM; | |
1094 | dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); | |
1095 | goto out; | |
1096 | } | |
1097 | ||
f06fcc71 | 1098 | /* Make a two way bind between the qcom host and the hba */ |
81c0fc51 | 1099 | host->hba = hba; |
1ce5898a | 1100 | ufshcd_set_variant(hba, host); |
81c0fc51 | 1101 | |
12fd5f25 EG |
1102 | /* Fire up the reset controller. Failure here is non-fatal. */ |
1103 | host->rcdev.of_node = dev->of_node; | |
1104 | host->rcdev.ops = &ufs_qcom_reset_ops; | |
1105 | host->rcdev.owner = dev->driver->owner; | |
1106 | host->rcdev.nr_resets = 1; | |
1107 | err = devm_reset_controller_register(dev, &host->rcdev); | |
1108 | if (err) { | |
1109 | dev_warn(dev, "Failed to register reset controller\n"); | |
1110 | err = 0; | |
1111 | } | |
1112 | ||
f06fcc71 YG |
1113 | /* |
1114 | * voting/devoting device ref_clk source is time consuming hence | |
1115 | * skip devoting it during aggressive clock gating. This clock | |
1116 | * will still be gated off during runtime suspend. | |
1117 | */ | |
81c0fc51 YG |
1118 | host->generic_phy = devm_phy_get(dev, "ufsphy"); |
1119 | ||
ab436706 YG |
1120 | if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) { |
1121 | /* | |
1122 | * UFS driver might be probed before the phy driver does. | |
1123 | * In that case we would like to return EPROBE_DEFER code. | |
1124 | */ | |
1125 | err = -EPROBE_DEFER; | |
1126 | dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n", | |
1127 | __func__, err); | |
1128 | goto out_variant_clear; | |
1129 | } else if (IS_ERR(host->generic_phy)) { | |
81c0fc51 YG |
1130 | err = PTR_ERR(host->generic_phy); |
1131 | dev_err(dev, "%s: PHY get failed %d\n", __func__, err); | |
a6854dff | 1132 | goto out_variant_clear; |
81c0fc51 YG |
1133 | } |
1134 | ||
1135 | err = ufs_qcom_bus_register(host); | |
1136 | if (err) | |
a6854dff | 1137 | goto out_variant_clear; |
81c0fc51 | 1138 | |
bfdbe8ba YG |
1139 | ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, |
1140 | &host->hw_ver.minor, &host->hw_ver.step); | |
1141 | ||
f06fcc71 YG |
1142 | /* |
1143 | * for newer controllers, device reference clock control bit has | |
1144 | * moved inside UFS controller register address space itself. | |
1145 | */ | |
1146 | if (host->hw_ver.major >= 0x02) { | |
1147 | host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; | |
1148 | host->dev_ref_clk_en_mask = BIT(26); | |
1149 | } else { | |
1150 | /* "dev_ref_clk_ctrl_mem" is optional resource */ | |
1151 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1152 | if (res) { | |
1153 | host->dev_ref_clk_ctrl_mmio = | |
1154 | devm_ioremap_resource(dev, res); | |
1155 | if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) { | |
1156 | dev_warn(dev, | |
1157 | "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n", | |
1158 | __func__, | |
1159 | PTR_ERR(host->dev_ref_clk_ctrl_mmio)); | |
1160 | host->dev_ref_clk_ctrl_mmio = NULL; | |
1161 | } | |
1162 | host->dev_ref_clk_en_mask = BIT(5); | |
1163 | } | |
1164 | } | |
1165 | ||
81c0fc51 YG |
1166 | err = ufs_qcom_init_lane_clks(host); |
1167 | if (err) | |
052553af | 1168 | goto out_variant_clear; |
81c0fc51 | 1169 | |
cad2e03d | 1170 | ufs_qcom_set_caps(hba); |
81c0fc51 YG |
1171 | ufs_qcom_advertise_quirks(hba); |
1172 | ||
1e879e8f | 1173 | ufs_qcom_setup_clocks(hba, true, POST_CHANGE); |
81c0fc51 YG |
1174 | |
1175 | if (hba->dev->id < MAX_UFS_QCOM_HOSTS) | |
1176 | ufs_qcom_hosts[hba->dev->id] = host; | |
1177 | ||
6e3fd44d YG |
1178 | host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN; |
1179 | ufs_qcom_get_default_testbus_cfg(host); | |
1180 | err = ufs_qcom_testbus_config(host); | |
1181 | if (err) { | |
1182 | dev_warn(dev, "%s: failed to configure the testbus %d\n", | |
1183 | __func__, err); | |
1184 | err = 0; | |
1185 | } | |
1186 | ||
81c0fc51 YG |
1187 | goto out; |
1188 | ||
a6854dff | 1189 | out_variant_clear: |
1ce5898a | 1190 | ufshcd_set_variant(hba, NULL); |
81c0fc51 YG |
1191 | out: |
1192 | return err; | |
1193 | } | |
1194 | ||
1195 | static void ufs_qcom_exit(struct ufs_hba *hba) | |
1196 | { | |
1ce5898a | 1197 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 YG |
1198 | |
1199 | ufs_qcom_disable_lane_clks(host); | |
1200 | phy_power_off(host->generic_phy); | |
d7fe6b66 | 1201 | phy_exit(host->generic_phy); |
81c0fc51 YG |
1202 | } |
1203 | ||
f06fcc71 YG |
1204 | static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, |
1205 | u32 clk_cycles) | |
1206 | { | |
1207 | int err; | |
1208 | u32 core_clk_ctrl_reg; | |
1209 | ||
1210 | if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) | |
1211 | return -EINVAL; | |
1212 | ||
1213 | err = ufshcd_dme_get(hba, | |
1214 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), | |
1215 | &core_clk_ctrl_reg); | |
1216 | if (err) | |
1217 | goto out; | |
1218 | ||
1219 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; | |
1220 | core_clk_ctrl_reg |= clk_cycles; | |
1221 | ||
1222 | /* Clear CORE_CLK_DIV_EN */ | |
1223 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; | |
1224 | ||
1225 | err = ufshcd_dme_set(hba, | |
1226 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), | |
1227 | core_clk_ctrl_reg); | |
1228 | out: | |
1229 | return err; | |
1230 | } | |
1231 | ||
1232 | static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) | |
1233 | { | |
1234 | /* nothing to do as of now */ | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) | |
1239 | { | |
1240 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
1241 | ||
1242 | if (!ufs_qcom_cap_qunipro(host)) | |
1243 | return 0; | |
1244 | ||
1245 | /* set unipro core clock cycles to 150 and clear clock divider */ | |
1246 | return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); | |
1247 | } | |
1248 | ||
1249 | static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) | |
1250 | { | |
1251 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
1252 | int err; | |
1253 | u32 core_clk_ctrl_reg; | |
1254 | ||
1255 | if (!ufs_qcom_cap_qunipro(host)) | |
1256 | return 0; | |
1257 | ||
1258 | err = ufshcd_dme_get(hba, | |
1259 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), | |
1260 | &core_clk_ctrl_reg); | |
1261 | ||
1262 | /* make sure CORE_CLK_DIV_EN is cleared */ | |
1263 | if (!err && | |
1264 | (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { | |
1265 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; | |
1266 | err = ufshcd_dme_set(hba, | |
1267 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), | |
1268 | core_clk_ctrl_reg); | |
1269 | } | |
1270 | ||
1271 | return err; | |
1272 | } | |
1273 | ||
1274 | static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) | |
1275 | { | |
1276 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
1277 | ||
1278 | if (!ufs_qcom_cap_qunipro(host)) | |
1279 | return 0; | |
1280 | ||
1281 | /* set unipro core clock cycles to 75 and clear clock divider */ | |
1282 | return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); | |
1283 | } | |
1284 | ||
1285 | static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, | |
1286 | bool scale_up, enum ufs_notify_change_status status) | |
81c0fc51 | 1287 | { |
1ce5898a | 1288 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
81c0fc51 | 1289 | struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; |
f06fcc71 | 1290 | int err = 0; |
81c0fc51 | 1291 | |
f06fcc71 YG |
1292 | if (status == PRE_CHANGE) { |
1293 | if (scale_up) | |
1294 | err = ufs_qcom_clk_scale_up_pre_change(hba); | |
1295 | else | |
1296 | err = ufs_qcom_clk_scale_down_pre_change(hba); | |
1297 | } else { | |
1298 | if (scale_up) | |
1299 | err = ufs_qcom_clk_scale_up_post_change(hba); | |
1300 | else | |
1301 | err = ufs_qcom_clk_scale_down_post_change(hba); | |
1302 | ||
1303 | if (err || !dev_req_params) | |
1304 | goto out; | |
1305 | ||
1306 | ufs_qcom_cfg_timers(hba, | |
1307 | dev_req_params->gear_rx, | |
1308 | dev_req_params->pwr_rx, | |
1309 | dev_req_params->hs_rate, | |
1310 | false); | |
1311 | ufs_qcom_update_bus_bw_vote(host); | |
1312 | } | |
1313 | ||
1314 | out: | |
1315 | return err; | |
6e3fd44d YG |
1316 | } |
1317 | ||
eba5ed35 YG |
1318 | static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, |
1319 | void *priv, void (*print_fn)(struct ufs_hba *hba, | |
ba80917d | 1320 | int offset, int num_regs, const char *str, void *priv)) |
eba5ed35 YG |
1321 | { |
1322 | u32 reg; | |
1323 | struct ufs_qcom_host *host; | |
1324 | ||
1325 | if (unlikely(!hba)) { | |
1326 | pr_err("%s: hba is NULL\n", __func__); | |
1327 | return; | |
1328 | } | |
1329 | if (unlikely(!print_fn)) { | |
1330 | dev_err(hba->dev, "%s: print_fn is NULL\n", __func__); | |
1331 | return; | |
1332 | } | |
1333 | ||
1334 | host = ufshcd_get_variant(hba); | |
1335 | if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN)) | |
1336 | return; | |
1337 | ||
1338 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); | |
1339 | print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv); | |
1340 | ||
1341 | reg = ufshcd_readl(hba, REG_UFS_CFG1); | |
7e014efd | 1342 | reg |= UTP_DBG_RAMS_EN; |
eba5ed35 YG |
1343 | ufshcd_writel(hba, reg, REG_UFS_CFG1); |
1344 | ||
1345 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); | |
1346 | print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv); | |
1347 | ||
1348 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); | |
1349 | print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv); | |
1350 | ||
1351 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); | |
1352 | print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv); | |
1353 | ||
b84ca6e9 | 1354 | /* clear bit 17 - UTP_DBG_RAMS_EN */ |
7e014efd | 1355 | ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); |
eba5ed35 YG |
1356 | |
1357 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); | |
1358 | print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv); | |
1359 | ||
1360 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); | |
1361 | print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv); | |
1362 | ||
1363 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); | |
1364 | print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv); | |
1365 | ||
1366 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); | |
1367 | print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv); | |
1368 | ||
1369 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); | |
1370 | print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv); | |
1371 | ||
1372 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); | |
1373 | print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv); | |
1374 | ||
1375 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); | |
1376 | print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv); | |
1377 | } | |
1378 | ||
1379 | static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) | |
1380 | { | |
9c46b867 VG |
1381 | if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) { |
1382 | ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, | |
1383 | UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); | |
eba5ed35 | 1384 | ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); |
9c46b867 VG |
1385 | } else { |
1386 | ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1); | |
eba5ed35 | 1387 | ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1); |
9c46b867 | 1388 | } |
eba5ed35 YG |
1389 | } |
1390 | ||
6e3fd44d YG |
1391 | static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) |
1392 | { | |
1393 | /* provide a legal default configuration */ | |
9c46b867 VG |
1394 | host->testbus.select_major = TSTBUS_UNIPRO; |
1395 | host->testbus.select_minor = 37; | |
6e3fd44d YG |
1396 | } |
1397 | ||
1398 | static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) | |
1399 | { | |
1400 | if (host->testbus.select_major >= TSTBUS_MAX) { | |
1401 | dev_err(host->hba->dev, | |
1402 | "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", | |
1403 | __func__, host->testbus.select_major); | |
1404 | return false; | |
1405 | } | |
1406 | ||
6e3fd44d YG |
1407 | return true; |
1408 | } | |
1409 | ||
1410 | int ufs_qcom_testbus_config(struct ufs_qcom_host *host) | |
1411 | { | |
1412 | int reg; | |
1413 | int offset; | |
1414 | u32 mask = TEST_BUS_SUB_SEL_MASK; | |
1415 | ||
1416 | if (!host) | |
1417 | return -EINVAL; | |
81c0fc51 | 1418 | |
6e3fd44d YG |
1419 | if (!ufs_qcom_testbus_cfg_is_ok(host)) |
1420 | return -EPERM; | |
1421 | ||
1422 | switch (host->testbus.select_major) { | |
1423 | case TSTBUS_UAWM: | |
1424 | reg = UFS_TEST_BUS_CTRL_0; | |
1425 | offset = 24; | |
1426 | break; | |
1427 | case TSTBUS_UARM: | |
1428 | reg = UFS_TEST_BUS_CTRL_0; | |
1429 | offset = 16; | |
1430 | break; | |
1431 | case TSTBUS_TXUC: | |
1432 | reg = UFS_TEST_BUS_CTRL_0; | |
1433 | offset = 8; | |
1434 | break; | |
1435 | case TSTBUS_RXUC: | |
1436 | reg = UFS_TEST_BUS_CTRL_0; | |
1437 | offset = 0; | |
1438 | break; | |
1439 | case TSTBUS_DFC: | |
1440 | reg = UFS_TEST_BUS_CTRL_1; | |
1441 | offset = 24; | |
1442 | break; | |
1443 | case TSTBUS_TRLUT: | |
1444 | reg = UFS_TEST_BUS_CTRL_1; | |
1445 | offset = 16; | |
1446 | break; | |
1447 | case TSTBUS_TMRLUT: | |
1448 | reg = UFS_TEST_BUS_CTRL_1; | |
1449 | offset = 8; | |
1450 | break; | |
1451 | case TSTBUS_OCSC: | |
1452 | reg = UFS_TEST_BUS_CTRL_1; | |
1453 | offset = 0; | |
1454 | break; | |
1455 | case TSTBUS_WRAPPER: | |
1456 | reg = UFS_TEST_BUS_CTRL_2; | |
1457 | offset = 16; | |
1458 | break; | |
1459 | case TSTBUS_COMBINED: | |
1460 | reg = UFS_TEST_BUS_CTRL_2; | |
1461 | offset = 8; | |
1462 | break; | |
1463 | case TSTBUS_UTP_HCI: | |
1464 | reg = UFS_TEST_BUS_CTRL_2; | |
1465 | offset = 0; | |
1466 | break; | |
1467 | case TSTBUS_UNIPRO: | |
1468 | reg = UFS_UNIPRO_CFG; | |
9c46b867 VG |
1469 | offset = 20; |
1470 | mask = 0xFFF; | |
6e3fd44d YG |
1471 | break; |
1472 | /* | |
1473 | * No need for a default case, since | |
1474 | * ufs_qcom_testbus_cfg_is_ok() checks that the configuration | |
1475 | * is legal | |
1476 | */ | |
1477 | } | |
1478 | mask <<= offset; | |
1479 | ||
1480 | pm_runtime_get_sync(host->hba->dev); | |
1481 | ufshcd_hold(host->hba, false); | |
1482 | ufshcd_rmwl(host->hba, TEST_BUS_SEL, | |
1483 | (u32)host->testbus.select_major << 19, | |
1484 | REG_UFS_CFG1); | |
1485 | ufshcd_rmwl(host->hba, mask, | |
1486 | (u32)host->testbus.select_minor << offset, | |
1487 | reg); | |
eba5ed35 | 1488 | ufs_qcom_enable_test_bus(host); |
9c46b867 VG |
1489 | /* |
1490 | * Make sure the test bus configuration is | |
1491 | * committed before returning. | |
1492 | */ | |
1493 | mb(); | |
6e3fd44d YG |
1494 | ufshcd_release(host->hba); |
1495 | pm_runtime_put_sync(host->hba->dev); | |
1496 | ||
1497 | return 0; | |
81c0fc51 YG |
1498 | } |
1499 | ||
6e3fd44d YG |
1500 | static void ufs_qcom_testbus_read(struct ufs_hba *hba) |
1501 | { | |
ba80917d | 1502 | ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); |
6e3fd44d YG |
1503 | } |
1504 | ||
9c46b867 VG |
1505 | static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba) |
1506 | { | |
1507 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); | |
1508 | u32 *testbus = NULL; | |
1509 | int i, nminor = 256, testbus_len = nminor * sizeof(u32); | |
1510 | ||
1511 | testbus = kmalloc(testbus_len, GFP_KERNEL); | |
1512 | if (!testbus) | |
1513 | return; | |
1514 | ||
1515 | host->testbus.select_major = TSTBUS_UNIPRO; | |
1516 | for (i = 0; i < nminor; i++) { | |
1517 | host->testbus.select_minor = i; | |
1518 | ufs_qcom_testbus_config(host); | |
1519 | testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); | |
1520 | } | |
1521 | print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET, | |
1522 | 16, 4, testbus, testbus_len, false); | |
1523 | kfree(testbus); | |
1524 | } | |
1525 | ||
6e3fd44d YG |
1526 | static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) |
1527 | { | |
ba80917d TW |
1528 | ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, |
1529 | "HCI Vendor Specific Registers "); | |
6e3fd44d | 1530 | |
9c46b867 | 1531 | /* sleep a bit intermittently as we are dumping too much data */ |
eba5ed35 | 1532 | ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper); |
9c46b867 | 1533 | usleep_range(1000, 1100); |
6e3fd44d | 1534 | ufs_qcom_testbus_read(hba); |
9c46b867 VG |
1535 | usleep_range(1000, 1100); |
1536 | ufs_qcom_print_unipro_testbus(hba); | |
1537 | usleep_range(1000, 1100); | |
6e3fd44d | 1538 | } |
eba5ed35 | 1539 | |
81c0fc51 YG |
1540 | /** |
1541 | * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations | |
1542 | * | |
1543 | * The variant operations configure the necessary controller and PHY | |
1544 | * handshake during initialization. | |
1545 | */ | |
47555a5c | 1546 | static struct ufs_hba_variant_ops ufs_hba_qcom_vops = { |
81c0fc51 YG |
1547 | .name = "qcom", |
1548 | .init = ufs_qcom_init, | |
1549 | .exit = ufs_qcom_exit, | |
ae977587 | 1550 | .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, |
81c0fc51 YG |
1551 | .clk_scale_notify = ufs_qcom_clk_scale_notify, |
1552 | .setup_clocks = ufs_qcom_setup_clocks, | |
1553 | .hce_enable_notify = ufs_qcom_hce_enable_notify, | |
1554 | .link_startup_notify = ufs_qcom_link_startup_notify, | |
1555 | .pwr_change_notify = ufs_qcom_pwr_change_notify, | |
56d4a186 | 1556 | .apply_dev_quirks = ufs_qcom_apply_dev_quirks, |
81c0fc51 YG |
1557 | .suspend = ufs_qcom_suspend, |
1558 | .resume = ufs_qcom_resume, | |
6e3fd44d | 1559 | .dbg_register_dump = ufs_qcom_dump_dbg_regs, |
81c0fc51 | 1560 | }; |
fb819ee8 | 1561 | |
47555a5c YG |
1562 | /** |
1563 | * ufs_qcom_probe - probe routine of the driver | |
1564 | * @pdev: pointer to Platform device handle | |
1565 | * | |
1566 | * Return zero for success and non-zero for failure | |
1567 | */ | |
1568 | static int ufs_qcom_probe(struct platform_device *pdev) | |
1569 | { | |
1570 | int err; | |
1571 | struct device *dev = &pdev->dev; | |
1572 | ||
1573 | /* Perform generic probe */ | |
1574 | err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); | |
1575 | if (err) | |
1576 | dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); | |
1577 | ||
1578 | return err; | |
1579 | } | |
1580 | ||
1581 | /** | |
1582 | * ufs_qcom_remove - set driver_data of the device to NULL | |
1583 | * @pdev: pointer to platform device handle | |
1584 | * | |
4b9ad0b8 | 1585 | * Always returns 0 |
47555a5c YG |
1586 | */ |
1587 | static int ufs_qcom_remove(struct platform_device *pdev) | |
1588 | { | |
1589 | struct ufs_hba *hba = platform_get_drvdata(pdev); | |
1590 | ||
1591 | pm_runtime_get_sync(&(pdev)->dev); | |
1592 | ufshcd_remove(hba); | |
1593 | return 0; | |
1594 | } | |
1595 | ||
1596 | static const struct of_device_id ufs_qcom_of_match[] = { | |
1597 | { .compatible = "qcom,ufshc"}, | |
1598 | {}, | |
1599 | }; | |
ab3dabb3 | 1600 | MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); |
47555a5c YG |
1601 | |
1602 | static const struct dev_pm_ops ufs_qcom_pm_ops = { | |
1603 | .suspend = ufshcd_pltfrm_suspend, | |
1604 | .resume = ufshcd_pltfrm_resume, | |
1605 | .runtime_suspend = ufshcd_pltfrm_runtime_suspend, | |
1606 | .runtime_resume = ufshcd_pltfrm_runtime_resume, | |
1607 | .runtime_idle = ufshcd_pltfrm_runtime_idle, | |
1608 | }; | |
1609 | ||
1610 | static struct platform_driver ufs_qcom_pltform = { | |
1611 | .probe = ufs_qcom_probe, | |
1612 | .remove = ufs_qcom_remove, | |
1613 | .shutdown = ufshcd_pltfrm_shutdown, | |
1614 | .driver = { | |
1615 | .name = "ufshcd-qcom", | |
1616 | .pm = &ufs_qcom_pm_ops, | |
1617 | .of_match_table = of_match_ptr(ufs_qcom_of_match), | |
1618 | }, | |
1619 | }; | |
1620 | module_platform_driver(ufs_qcom_pltform); | |
1621 | ||
fb819ee8 | 1622 | MODULE_LICENSE("GPL v2"); |