[linux-block.git] / drivers / scsi / sun_esp.c

// SPDX-License-Identifier: GPL-2.0-only
/* sun_esp.c: ESP front-end for Sparc SBUS systems.
 *
 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/gfp.h>

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME		"sun_esp"
#define PFX DRV_MODULE_NAME	": "
#define DRV_VERSION		"1.100"
#define DRV_MODULE_RELDATE	"August 27, 2008"

#define dma_read32(REG) \
	sbus_readl(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	sbus_writel((VAL), esp->dma_regs + (REG))

/* DVMA chip revisions */
enum dvma_rev {
	dvmarev0,
	dvmaesc1,
	dvmarev1,
	dvmarev2,
	dvmarev3,
	dvmarevplus,
	dvmahme
};

static int esp_sbus_setup_dma(struct esp *esp, struct platform_device *dma_of)
{
	esp->dma = dma_of;

	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
				   resource_size(&dma_of->resource[0]),
				   "espdma");
	if (!esp->dma_regs)
		return -ENOMEM;

	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	case DMA_VERS0:
		esp->dmarev = dvmarev0;
		break;
	case DMA_ESCV1:
		esp->dmarev = dvmaesc1;
		break;
	case DMA_VERS1:
		esp->dmarev = dvmarev1;
		break;
	case DMA_VERS2:
		esp->dmarev = dvmarev2;
		break;
	case DMA_VERHME:
		esp->dmarev = dvmahme;
		break;
	case DMA_VERSPLUS:
		esp->dmarev = dvmarevplus;
		break;
	}

	return 0;

}

static int esp_sbus_map_regs(struct esp *esp, int hme)
{
	struct platform_device *op = to_platform_device(esp->dev);
	struct resource *res;

	/* On HME, two reg sets exist, first is DVMA,
	 * second is ESP registers.
	 */
	if (hme)
		res = &op->resource[1];
	else
		res = &op->resource[0];

	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
	if (!esp->regs)
		return -ENOMEM;

	return 0;
}

static int esp_sbus_map_command_block(struct esp *esp)
{
	esp->command_block = dma_alloc_coherent(esp->dev, 16,
						&esp->command_block_dma,
						GFP_KERNEL);
	if (!esp->command_block)
		return -ENOMEM;
	return 0;
}

static int esp_sbus_register_irq(struct esp *esp)
{
	struct Scsi_Host *host = esp->host;
	struct platform_device *op = to_platform_device(esp->dev);

	host->irq = op->archdata.irqs[0];
	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
}

static void esp_get_scsi_id(struct esp *esp, struct platform_device *espdma)
{
	struct platform_device *op = to_platform_device(esp->dev);
	struct device_node *dp;

	dp = op->dev.of_node;
	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(espdma->dev.of_node,
					     "scsi-initiator-id", 7);

done:
	esp->host->this_id = esp->scsi_id;
	esp->scsi_id_mask = (1 << esp->scsi_id);
}

static void esp_get_differential(struct esp *esp)
{
	struct platform_device *op = to_platform_device(esp->dev);
	struct device_node *dp;

	dp = op->dev.of_node;
	if (of_property_read_bool(dp, "differential"))
		esp->flags |= ESP_FLAG_DIFFERENTIAL;
	else
		esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
}

static void esp_get_clock_params(struct esp *esp)
{
	struct platform_device *op = to_platform_device(esp->dev);
	struct device_node *bus_dp, *dp;
	int fmhz;

	dp = op->dev.of_node;
	bus_dp = dp->parent;

	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	if (fmhz == 0)
		fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);

	esp->cfreq = fmhz;
}

static void esp_get_bursts(struct esp *esp, struct platform_device *dma_of)
{
	struct device_node *dma_dp = dma_of->dev.of_node;
	struct platform_device *op = to_platform_device(esp->dev);
	struct device_node *dp;
	u8 bursts, val;

	dp = op->dev.of_node;
	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	if (bursts == 0xff ||
	    (bursts & DMA_BURST16) == 0 ||
	    (bursts & DMA_BURST32) == 0)
		bursts = (DMA_BURST32 - 1);

	esp->bursts = bursts;
}

static void esp_sbus_get_props(struct esp *esp, struct platform_device *espdma)
{
	esp_get_scsi_id(esp, espdma);
	esp_get_differential(esp);
	esp_get_clock_params(esp);
	esp_get_bursts(esp, espdma);
}

static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	sbus_writeb(val, esp->regs + (reg * 4UL));
}

static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
{
	return sbus_readb(esp->regs + (reg * 4UL));
}

static int sbus_esp_irq_pending(struct esp *esp)
{
	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
		return 1;
	return 0;
}

static void sbus_esp_reset_dma(struct esp *esp)
{
	int can_do_burst16, can_do_burst32, can_do_burst64;
	int can_do_sbus64, lim;
	struct platform_device *op = to_platform_device(esp->dev);
	u32 val;

	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	can_do_burst64 = 0;
	can_do_sbus64 = 0;
	if (sbus_can_dma_64bit())
		can_do_sbus64 = 1;
	if (sbus_can_burst64())
		can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;

	/* Put the DVMA into a known state. */
	if (esp->dmarev != dvmahme) {
		val = dma_read32(DMA_CSR);
		dma_write32(val | DMA_RST_SCSI, DMA_CSR);
		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}
	switch (esp->dmarev) {
	case dvmahme:
		dma_write32(DMA_RESET_FAS366, DMA_CSR);
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
					DMA_SCSI_DISAB | DMA_INT_ENAB);

		esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
					  DMA_BRST_SZ);

		if (can_do_burst64)
			esp->prev_hme_dmacsr |= DMA_BRST64;
		else if (can_do_burst32)
			esp->prev_hme_dmacsr |= DMA_BRST32;

		if (can_do_sbus64) {
			esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
			sbus_set_sbus64(&op->dev, esp->bursts);
		}

		lim = 1000;
		while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
				       "will not clear!\n",
				       esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		dma_write32(0, DMA_ADDR);
		break;

	case dvmarev2:
		if (esp->rev != ESP100) {
			val = dma_read32(DMA_CSR);
			dma_write32(val | DMA_3CLKS, DMA_CSR);
		}
		break;

	case dvmarev3:
		val = dma_read32(DMA_CSR);
		val &= ~DMA_3CLKS;
		val |= DMA_2CLKS;
		if (can_do_burst32) {
			val &= ~DMA_BRST_SZ;
			val |= DMA_BRST32;
		}
		dma_write32(val, DMA_CSR);
		break;

	case dvmaesc1:
		val = dma_read32(DMA_CSR);
		val |= DMA_ADD_ENABLE;
		val &= ~DMA_BCNT_ENAB;
		if (!can_do_burst32 && can_do_burst16) {
			val |= DMA_ESC_BURST;
		} else {
			val &= ~(DMA_ESC_BURST);
		}
		dma_write32(val, DMA_CSR);
		break;

	default:
		break;
	}

	/* Enable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}

static void sbus_esp_dma_drain(struct esp *esp)
{
	u32 csr;
	int lim;

	if (esp->dmarev == dvmahme)
		return;

	csr = dma_read32(DMA_CSR);
	if (!(csr & DMA_FIFO_ISDRAIN))
		return;

	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

	lim = 1000;
	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
			       esp->host->unique_id);
			break;
		}
		udelay(1);
	}
}

static void sbus_esp_dma_invalidate(struct esp *esp)
{
	if (esp->dmarev == dvmahme) {
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
					 (DMA_PARITY_OFF | DMA_2CLKS |
					  DMA_SCSI_DISAB | DMA_INT_ENAB)) &
					~(DMA_ST_WRITE | DMA_ENABLE));

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		/* This is necessary to avoid having the SCSI channel
		 * engine lock up on us.
		 */
		dma_write32(0, DMA_ADDR);
	} else {
		u32 val;
		int lim;

		lim = 1000;
		while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA will not "
				       "invalidate!\n", esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
		val |= DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
		val &= ~DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
	}
}

static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				  u32 dma_count, int write, u8 cmd)
{
	u32 csr;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	if (esp->rev == FASHME) {
		sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
		sbus_esp_write8(esp, 0, FAS_RHI);

		scsi_esp_cmd(esp, cmd);

		csr = esp->prev_hme_dmacsr;
		csr |= DMA_SCSI_DISAB | DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		esp->prev_hme_dmacsr = csr;

		dma_write32(dma_count, DMA_COUNT);
		dma_write32(addr, DMA_ADDR);
		dma_write32(csr, DMA_CSR);
	} else {
		csr = dma_read32(DMA_CSR);
		csr |= DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		dma_write32(csr, DMA_CSR);
		if (esp->dmarev == dvmaesc1) {
			u32 end = PAGE_ALIGN(addr + dma_count + 16U);
			dma_write32(end - addr, DMA_COUNT);
		}
		dma_write32(addr, DMA_ADDR);

		scsi_esp_cmd(esp, cmd);
	}

}

static int sbus_esp_dma_error(struct esp *esp)
{
	u32 csr = dma_read32(DMA_CSR);

	if (csr & DMA_HNDL_ERROR)
		return 1;

	return 0;
}

static const struct esp_driver_ops sbus_esp_ops = {
	.esp_write8	=	sbus_esp_write8,
	.esp_read8	=	sbus_esp_read8,
	.irq_pending	=	sbus_esp_irq_pending,
	.reset_dma	=	sbus_esp_reset_dma,
	.dma_drain	=	sbus_esp_dma_drain,
	.dma_invalidate	=	sbus_esp_dma_invalidate,
	.send_dma_cmd	=	sbus_esp_send_dma_cmd,
	.dma_error	=	sbus_esp_dma_error,
};

static int esp_sbus_probe_one(struct platform_device *op,
			      struct platform_device *espdma, int hme)
{
	const struct scsi_host_template *tpnt = &scsi_esp_template;
	struct Scsi_Host *host;
	struct esp *esp;
	int err;

	host = scsi_host_alloc(tpnt, sizeof(struct esp));

	err = -ENOMEM;
	if (!host)
		goto fail;

	host->max_id = (hme ? 16 : 8);
	esp = shost_priv(host);

	esp->host = host;
	esp->dev = &op->dev;
	esp->ops = &sbus_esp_ops;

	if (hme)
		esp->flags |= ESP_FLAG_WIDE_CAPABLE;

	err = esp_sbus_setup_dma(esp, espdma);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_regs(esp, hme);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_command_block(esp);
	if (err < 0)
		goto fail_unmap_regs;

	err = esp_sbus_register_irq(esp);
	if (err < 0)
		goto fail_unmap_command_block;

	esp_sbus_get_props(esp, espdma);

	/* Before we try to touch the ESP chip, ESC1 dma can
	 * come up with the reset bit set, so make sure that
	 * is clear first.
	 */
	if (esp->dmarev == dvmaesc1) {
		u32 val = dma_read32(DMA_CSR);

		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}

	dev_set_drvdata(&op->dev, esp);

	err = scsi_esp_register(esp);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(host->irq, esp);
fail_unmap_command_block:
	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
fail_unmap_regs:
	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
fail_unlink:
	scsi_host_put(host);
fail:
	return err;
}

static int esp_sbus_probe(struct platform_device *op)
{
	struct device_node *dma_node = NULL;
	struct device_node *dp = op->dev.of_node;
	struct platform_device *dma_of = NULL;
	int hme = 0;
	int ret;

	if (of_node_name_eq(dp->parent, "espdma") ||
	    of_node_name_eq(dp->parent, "dma"))
		dma_node = dp->parent;
	else if (of_node_name_eq(dp, "SUNW,fas")) {
		dma_node = op->dev.of_node;
		hme = 1;
	}
	if (dma_node)
		dma_of = of_find_device_by_node(dma_node);
	if (!dma_of)
		return -ENODEV;

	ret = esp_sbus_probe_one(op, dma_of, hme);
	if (ret)
		put_device(&dma_of->dev);

	return ret;
}

static void esp_sbus_remove(struct platform_device *op)
{
	struct esp *esp = dev_get_drvdata(&op->dev);
	struct platform_device *dma_of = esp->dma;
	unsigned int irq = esp->host->irq;
	bool is_hme;
	u32 val;

	scsi_esp_unregister(esp);

	/* Disable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);

	free_irq(irq, esp);

	is_hme = (esp->dmarev == dvmahme);

	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
		   SBUS_ESP_REG_SIZE);
	of_iounmap(&dma_of->resource[0], esp->dma_regs,
		   resource_size(&dma_of->resource[0]));

	scsi_host_put(esp->host);

	dev_set_drvdata(&op->dev, NULL);

	put_device(&dma_of->dev);
}

static const struct of_device_id esp_match[] = {
	{
		.name = "SUNW,esp",
	},
	{
		.name = "SUNW,fas",
	},
	{
		.name = "esp",
	},
	{},
};
MODULE_DEVICE_TABLE(of, esp_match);

static struct platform_driver esp_sbus_driver = {
	.driver = {
		.name = "esp",
		.of_match_table = esp_match,
	},
	.probe		= esp_sbus_probe,
	.remove_new	= esp_sbus_remove,
};
module_platform_driver(esp_sbus_driver);

MODULE_DESCRIPTION("Sun ESP SCSI driver");
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
cd9ad58d DM	2	/* sun_esp.c: ESP front-end for Sparc SBUS systems.
cd9ad58d DM	3	*
334ae614	4	* Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
cd9ad58d DM	5	*/
	6
	7	#include <linux/kernel.h>
	8	#include <linux/types.h>
6025dfe5	9	#include <linux/delay.h>
cd9ad58d	10	#include <linux/module.h>
27ac792c	11	#include <linux/mm.h>
cd9ad58d	12	#include <linux/init.h>
738f2b7b	13	#include <linux/dma-mapping.h>
05bb5e93	14	#include <linux/of.h>
109a2a48 RH	15	#include <linux/of_platform.h>
109a2a48 RH	16	#include <linux/platform_device.h>
5a0e3ad6	17	#include <linux/gfp.h>
cd9ad58d DM	18
	19	#include <asm/irq.h>
	20	#include <asm/io.h>
	21	#include <asm/dma.h>
	22
cd9ad58d DM	23	#include <scsi/scsi_host.h>
	24
	25	#include "esp_scsi.h"
	26
	27	#define DRV_MODULE_NAME "sun_esp"
	28	#define PFX DRV_MODULE_NAME ": "
05bb5e93 DM	29	#define DRV_VERSION "1.100"
05bb5e93 DM	30	#define DRV_MODULE_RELDATE "August 27, 2008"
cd9ad58d DM	31
	32	#define dma_read32(REG) \
	33	sbus_readl(esp->dma_regs + (REG))
	34	#define dma_write32(VAL, REG) \
	35	sbus_writel((VAL), esp->dma_regs + (REG))
	36
334ae614 DM	37	/* DVMA chip revisions */
	38	enum dvma_rev {
	39	dvmarev0,
	40	dvmaesc1,
	41	dvmarev1,
	42	dvmarev2,
	43	dvmarev3,
	44	dvmarevplus,
	45	dvmahme
	46	};
cd9ad58d	47
6f039790	48	static int esp_sbus_setup_dma(struct esp esp, struct platform_device dma_of)
334ae614 DM	49	{
334ae614 DM	50	esp->dma = dma_of;
cd9ad58d	51
334ae614 DM	52	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
	53	resource_size(&dma_of->resource[0]),
	54	"espdma");
	55	if (!esp->dma_regs)
	56	return -ENOMEM;
cd9ad58d	57
334ae614 DM	58	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	59	case DMA_VERS0:
	60	esp->dmarev = dvmarev0;
	61	break;
	62	case DMA_ESCV1:
	63	esp->dmarev = dvmaesc1;
	64	break;
	65	case DMA_VERS1:
	66	esp->dmarev = dvmarev1;
	67	break;
	68	case DMA_VERS2:
	69	esp->dmarev = dvmarev2;
	70	break;
	71	case DMA_VERHME:
	72	esp->dmarev = dvmahme;
	73	break;
	74	case DMA_VERSPLUS:
	75	esp->dmarev = dvmarevplus;
	76	break;
cd9ad58d	77	}
cd9ad58d DM	78
	79	return 0;
	80
	81	}
	82
6f039790	83	static int esp_sbus_map_regs(struct esp *esp, int hme)
cd9ad58d	84	{
98cda6a2	85	struct platform_device *op = to_platform_device(esp->dev);
cd9ad58d DM	86	struct resource *res;
	87
	88	/* On HME, two reg sets exist, first is DVMA,
	89	* second is ESP registers.
	90	*/
	91	if (hme)
05bb5e93	92	res = &op->resource[1];
cd9ad58d	93	else
05bb5e93	94	res = &op->resource[0];
cd9ad58d	95
05bb5e93	96	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
cd9ad58d DM	97	if (!esp->regs)
	98	return -ENOMEM;
	99
	100	return 0;
	101	}
	102
6f039790	103	static int esp_sbus_map_command_block(struct esp *esp)
cd9ad58d	104	{
98cda6a2	105	esp->command_block = dma_alloc_coherent(esp->dev, 16,
738f2b7b	106	&esp->command_block_dma,
10c0cd38	107	GFP_KERNEL);
cd9ad58d DM	108	if (!esp->command_block)
	109	return -ENOMEM;
	110	return 0;
	111	}
	112
6f039790	113	static int esp_sbus_register_irq(struct esp *esp)
cd9ad58d DM	114	{
cd9ad58d DM	115	struct Scsi_Host *host = esp->host;
98cda6a2	116	struct platform_device *op = to_platform_device(esp->dev);
cd9ad58d	117
1636f8ac	118	host->irq = op->archdata.irqs[0];
cd9ad58d DM	119	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
	120	}
	121
6f039790	122	static void esp_get_scsi_id(struct esp esp, struct platform_device espdma)
cd9ad58d	123	{
98cda6a2	124	struct platform_device *op = to_platform_device(esp->dev);
05bb5e93	125	struct device_node *dp;
cd9ad58d	126
61c7a080	127	dp = op->dev.of_node;
cd9ad58d DM	128	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	129	if (esp->scsi_id != 0xff)
	130	goto done;
	131
	132	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	133	if (esp->scsi_id != 0xff)
	134	goto done;
	135
61c7a080	136	esp->scsi_id = of_getintprop_default(espdma->dev.of_node,
cd9ad58d DM	137	"scsi-initiator-id", 7);
	138
	139	done:
	140	esp->host->this_id = esp->scsi_id;
	141	esp->scsi_id_mask = (1 << esp->scsi_id);
	142	}
	143
6f039790	144	static void esp_get_differential(struct esp *esp)
cd9ad58d	145	{
98cda6a2	146	struct platform_device *op = to_platform_device(esp->dev);
05bb5e93	147	struct device_node *dp;
cd9ad58d	148
61c7a080	149	dp = op->dev.of_node;
06f8e071	150	if (of_property_read_bool(dp, "differential"))
cd9ad58d DM	151	esp->flags \|= ESP_FLAG_DIFFERENTIAL;
	152	else
	153	esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
	154	}
	155
6f039790	156	static void esp_get_clock_params(struct esp *esp)
cd9ad58d	157	{
98cda6a2	158	struct platform_device *op = to_platform_device(esp->dev);
05bb5e93	159	struct device_node bus_dp, dp;
cd9ad58d DM	160	int fmhz;
cd9ad58d DM	161
61c7a080	162	dp = op->dev.of_node;
05bb5e93	163	bus_dp = dp->parent;
cd9ad58d DM	164
	165	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	166	if (fmhz == 0)
05bb5e93	167	fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);
cd9ad58d DM	168
	169	esp->cfreq = fmhz;
	170	}
	171
6f039790	172	static void esp_get_bursts(struct esp esp, struct platform_device dma_of)
cd9ad58d	173	{
61c7a080	174	struct device_node *dma_dp = dma_of->dev.of_node;
98cda6a2	175	struct platform_device *op = to_platform_device(esp->dev);
334ae614 DM	176	struct device_node *dp;
334ae614 DM	177	u8 bursts, val;
cd9ad58d	178
61c7a080	179	dp = op->dev.of_node;
cd9ad58d	180	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
334ae614 DM	181	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	182	if (val != 0xff)
	183	bursts &= val;
cd9ad58d	184
05bb5e93 DM	185	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	186	if (val != 0xff)
	187	bursts &= val;
cd9ad58d DM	188
	189	if (bursts == 0xff \|\|
	190	(bursts & DMA_BURST16) == 0 \|\|
	191	(bursts & DMA_BURST32) == 0)
	192	bursts = (DMA_BURST32 - 1);
	193
	194	esp->bursts = bursts;
	195	}
	196
6f039790	197	static void esp_sbus_get_props(struct esp esp, struct platform_device espdma)
cd9ad58d	198	{
05bb5e93	199	esp_get_scsi_id(esp, espdma);
cd9ad58d DM	200	esp_get_differential(esp);
	201	esp_get_clock_params(esp);
	202	esp_get_bursts(esp, espdma);
	203	}
	204
	205	static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
	206	{
	207	sbus_writeb(val, esp->regs + (reg * 4UL));
	208	}
	209
	210	static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
	211	{
	212	return sbus_readb(esp->regs + (reg * 4UL));
	213	}
	214
cd9ad58d DM	215	static int sbus_esp_irq_pending(struct esp *esp)
	216	{
	217	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR \| DMA_HNDL_ERROR))
	218	return 1;
	219	return 0;
	220	}
	221
	222	static void sbus_esp_reset_dma(struct esp *esp)
	223	{
	224	int can_do_burst16, can_do_burst32, can_do_burst64;
	225	int can_do_sbus64, lim;
98cda6a2	226	struct platform_device *op = to_platform_device(esp->dev);
cd9ad58d DM	227	u32 val;
	228
	229	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	230	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	231	can_do_burst64 = 0;
	232	can_do_sbus64 = 0;
63237eeb	233	if (sbus_can_dma_64bit())
cd9ad58d	234	can_do_sbus64 = 1;
63237eeb	235	if (sbus_can_burst64())
cd9ad58d DM	236	can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
	237
	238	/* Put the DVMA into a known state. */
334ae614	239	if (esp->dmarev != dvmahme) {
cd9ad58d DM	240	val = dma_read32(DMA_CSR);
	241	dma_write32(val \| DMA_RST_SCSI, DMA_CSR);
	242	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	243	}
334ae614	244	switch (esp->dmarev) {
cd9ad58d DM	245	case dvmahme:
	246	dma_write32(DMA_RESET_FAS366, DMA_CSR);
	247	dma_write32(DMA_RST_SCSI, DMA_CSR);
	248
	249	esp->prev_hme_dmacsr = (DMA_PARITY_OFF \| DMA_2CLKS \|
	250	DMA_SCSI_DISAB \| DMA_INT_ENAB);
	251
	252	esp->prev_hme_dmacsr &= ~(DMA_ENABLE \| DMA_ST_WRITE \|
	253	DMA_BRST_SZ);
	254
	255	if (can_do_burst64)
	256	esp->prev_hme_dmacsr \|= DMA_BRST64;
	257	else if (can_do_burst32)
	258	esp->prev_hme_dmacsr \|= DMA_BRST32;
	259
	260	if (can_do_sbus64) {
	261	esp->prev_hme_dmacsr \|= DMA_SCSI_SBUS64;
05bb5e93	262	sbus_set_sbus64(&op->dev, esp->bursts);
cd9ad58d DM	263	}
	264
	265	lim = 1000;
	266	while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
	267	if (--lim == 0) {
	268	printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
	269	"will not clear!\n",
	270	esp->host->unique_id);
	271	break;
	272	}
	273	udelay(1);
	274	}
	275
	276	dma_write32(0, DMA_CSR);
	277	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	278
	279	dma_write32(0, DMA_ADDR);
	280	break;
	281
	282	case dvmarev2:
	283	if (esp->rev != ESP100) {
	284	val = dma_read32(DMA_CSR);
	285	dma_write32(val \| DMA_3CLKS, DMA_CSR);
	286	}
	287	break;
	288
	289	case dvmarev3:
	290	val = dma_read32(DMA_CSR);
	291	val &= ~DMA_3CLKS;
	292	val \|= DMA_2CLKS;
	293	if (can_do_burst32) {
	294	val &= ~DMA_BRST_SZ;
	295	val \|= DMA_BRST32;
	296	}
	297	dma_write32(val, DMA_CSR);
	298	break;
	299
	300	case dvmaesc1:
	301	val = dma_read32(DMA_CSR);
	302	val \|= DMA_ADD_ENABLE;
	303	val &= ~DMA_BCNT_ENAB;
	304	if (!can_do_burst32 && can_do_burst16) {
	305	val \|= DMA_ESC_BURST;
	306	} else {
	307	val &= ~(DMA_ESC_BURST);
	308	}
	309	dma_write32(val, DMA_CSR);
	310	break;
	311
	312	default:
	313	break;
	314	}
	315
	316	/* Enable interrupts. */
	317	val = dma_read32(DMA_CSR);
	318	dma_write32(val \| DMA_INT_ENAB, DMA_CSR);
	319	}
	320
	321	static void sbus_esp_dma_drain(struct esp *esp)
	322	{
	323	u32 csr;
	324	int lim;
	325
334ae614	326	if (esp->dmarev == dvmahme)
cd9ad58d DM	327	return;
	328
	329	csr = dma_read32(DMA_CSR);
	330	if (!(csr & DMA_FIFO_ISDRAIN))
	331	return;
	332
334ae614	333	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
cd9ad58d DM	334	dma_write32(csr \| DMA_FIFO_STDRAIN, DMA_CSR);
	335
	336	lim = 1000;
	337	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
	338	if (--lim == 0) {
	339	printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
	340	esp->host->unique_id);
	341	break;
	342	}
	343	udelay(1);
	344	}
	345	}
	346
	347	static void sbus_esp_dma_invalidate(struct esp *esp)
	348	{
334ae614	349	if (esp->dmarev == dvmahme) {
cd9ad58d DM	350	dma_write32(DMA_RST_SCSI, DMA_CSR);
	351
	352	esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr \|
	353	(DMA_PARITY_OFF \| DMA_2CLKS \|
	354	DMA_SCSI_DISAB \| DMA_INT_ENAB)) &
	355	~(DMA_ST_WRITE \| DMA_ENABLE));
	356
	357	dma_write32(0, DMA_CSR);
	358	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	359
	360	/* This is necessary to avoid having the SCSI channel
	361	* engine lock up on us.
	362	*/
	363	dma_write32(0, DMA_ADDR);
	364	} else {
	365	u32 val;
	366	int lim;
	367
	368	lim = 1000;
	369	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
	370	if (--lim == 0) {
	371	printk(KERN_ALERT PFX "esp%d: DMA will not "
	372	"invalidate!\n", esp->host->unique_id);
	373	break;
	374	}
	375	udelay(1);
	376	}
	377
	378	val &= ~(DMA_ENABLE \| DMA_ST_WRITE \| DMA_BCNT_ENAB);
	379	val \|= DMA_FIFO_INV;
	380	dma_write32(val, DMA_CSR);
	381	val &= ~DMA_FIFO_INV;
	382	dma_write32(val, DMA_CSR);
	383	}
	384	}
	385
	386	static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
	387	u32 dma_count, int write, u8 cmd)
	388	{
	389	u32 csr;
	390
	391	BUG_ON(!(cmd & ESP_CMD_DMA));
	392
	393	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	394	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	395	if (esp->rev == FASHME) {
	396	sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
	397	sbus_esp_write8(esp, 0, FAS_RHI);
	398
	399	scsi_esp_cmd(esp, cmd);
	400
	401	csr = esp->prev_hme_dmacsr;
	402	csr \|= DMA_SCSI_DISAB \| DMA_ENABLE;
	403	if (write)
	404	csr \|= DMA_ST_WRITE;
	405	else
	406	csr &= ~DMA_ST_WRITE;
	407	esp->prev_hme_dmacsr = csr;
	408
	409	dma_write32(dma_count, DMA_COUNT);
	410	dma_write32(addr, DMA_ADDR);
	411	dma_write32(csr, DMA_CSR);
	412	} else {
	413	csr = dma_read32(DMA_CSR);
414	csr \|= DMA_ENABLE;
415	if (write)
416	csr \|= DMA_ST_WRITE;
417	else
418	csr &= ~DMA_ST_WRITE;
419	dma_write32(csr, DMA_CSR);
334ae614	420	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	421	u32 end = PAGE_ALIGN(addr + dma_count + 16U);
	422	dma_write32(end - addr, DMA_COUNT);
	423	}
	424	dma_write32(addr, DMA_ADDR);
	425
	426	scsi_esp_cmd(esp, cmd);
	427	}
	428
	429	}
	430
	431	static int sbus_esp_dma_error(struct esp *esp)
	432	{
	433	u32 csr = dma_read32(DMA_CSR);
	434
	435	if (csr & DMA_HNDL_ERROR)
	436	return 1;
	437
	438	return 0;
	439	}
	440
	441	static const struct esp_driver_ops sbus_esp_ops = {
	442	.esp_write8 = sbus_esp_write8,
	443	.esp_read8 = sbus_esp_read8,
cd9ad58d DM	444	.irq_pending = sbus_esp_irq_pending,
	445	.reset_dma = sbus_esp_reset_dma,
	446	.dma_drain = sbus_esp_dma_drain,
	447	.dma_invalidate = sbus_esp_dma_invalidate,
	448	.send_dma_cmd = sbus_esp_send_dma_cmd,
	449	.dma_error = sbus_esp_dma_error,
	450	};
	451
6f039790 GKH	452	static int esp_sbus_probe_one(struct platform_device *op,
6f039790 GKH	453	struct platform_device *espdma, int hme)
cd9ad58d	454	{
3b465a14	455	const struct scsi_host_template *tpnt = &scsi_esp_template;
cd9ad58d DM	456	struct Scsi_Host *host;
	457	struct esp *esp;
	458	int err;
	459
	460	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	461
	462	err = -ENOMEM;
	463	if (!host)
	464	goto fail;
	465
	466	host->max_id = (hme ? 16 : 8);
2b14ec78	467	esp = shost_priv(host);
cd9ad58d DM	468
cd9ad58d DM	469	esp->host = host;
98cda6a2	470	esp->dev = &op->dev;
cd9ad58d DM	471	esp->ops = &sbus_esp_ops;
	472
	473	if (hme)
	474	esp->flags \|= ESP_FLAG_WIDE_CAPABLE;
	475
334ae614	476	err = esp_sbus_setup_dma(esp, espdma);
cd9ad58d DM	477	if (err < 0)
	478	goto fail_unlink;
	479
	480	err = esp_sbus_map_regs(esp, hme);
	481	if (err < 0)
	482	goto fail_unlink;
	483
	484	err = esp_sbus_map_command_block(esp);
	485	if (err < 0)
	486	goto fail_unmap_regs;
	487
	488	err = esp_sbus_register_irq(esp);
	489	if (err < 0)
	490	goto fail_unmap_command_block;
	491
	492	esp_sbus_get_props(esp, espdma);
	493
	494	/* Before we try to touch the ESP chip, ESC1 dma can
	495	* come up with the reset bit set, so make sure that
	496	* is clear first.
	497	*/
334ae614	498	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	499	u32 val = dma_read32(DMA_CSR);
	500
	501	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	502	}
	503
05bb5e93	504	dev_set_drvdata(&op->dev, esp);
cd9ad58d	505
44b1b4d2	506	err = scsi_esp_register(esp);
cd9ad58d DM	507	if (err)
	508	goto fail_free_irq;
	509
	510	return 0;
	511
	512	fail_free_irq:
	513	free_irq(host->irq, esp);
	514	fail_unmap_command_block:
05bb5e93	515	dma_free_coherent(&op->dev, 16,
738f2b7b DM	516	esp->command_block,
738f2b7b DM	517	esp->command_block_dma);
cd9ad58d	518	fail_unmap_regs:
05bb5e93	519	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
cd9ad58d DM	520	fail_unlink:
	521	scsi_host_put(host);
	522	fail:
	523	return err;
	524	}
	525
6f039790	526	static int esp_sbus_probe(struct platform_device *op)
cd9ad58d	527	{
334ae614	528	struct device_node *dma_node = NULL;
61c7a080	529	struct device_node *dp = op->dev.of_node;
2dc11581	530	struct platform_device *dma_of = NULL;
cd9ad58d	531	int hme = 0;
f62f9ffd	532	int ret;
cd9ad58d	533
4b668103 RH	534	if (of_node_name_eq(dp->parent, "espdma") \|\|
4b668103 RH	535	of_node_name_eq(dp->parent, "dma"))
334ae614	536	dma_node = dp->parent;
4b668103	537	else if (of_node_name_eq(dp, "SUNW,fas")) {
61c7a080	538	dma_node = op->dev.of_node;
cd9ad58d DM	539	hme = 1;
cd9ad58d DM	540	}
334ae614 DM	541	if (dma_node)
	542	dma_of = of_find_device_by_node(dma_node);
	543	if (!dma_of)
	544	return -ENODEV;
cd9ad58d	545
f62f9ffd JH	546	ret = esp_sbus_probe_one(op, dma_of, hme);
	547	if (ret)
	548	put_device(&dma_of->dev);
	549
	550	return ret;
cd9ad58d DM	551	}
cd9ad58d DM	552
6ff482ee	553	static void esp_sbus_remove(struct platform_device *op)
cd9ad58d	554	{
05bb5e93	555	struct esp *esp = dev_get_drvdata(&op->dev);
2dc11581	556	struct platform_device *dma_of = esp->dma;
cd9ad58d	557	unsigned int irq = esp->host->irq;
05bb5e93	558	bool is_hme;
cd9ad58d DM	559	u32 val;
	560
	561	scsi_esp_unregister(esp);
	562
	563	/* Disable interrupts. */
	564	val = dma_read32(DMA_CSR);
	565	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
	566
	567	free_irq(irq, esp);
05bb5e93 DM	568
	569	is_hme = (esp->dmarev == dvmahme);
	570
	571	dma_free_coherent(&op->dev, 16,
738f2b7b DM	572	esp->command_block,
738f2b7b DM	573	esp->command_block_dma);
05bb5e93 DM	574	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
05bb5e93 DM	575	SBUS_ESP_REG_SIZE);
334ae614 DM	576	of_iounmap(&dma_of->resource[0], esp->dma_regs,
334ae614 DM	577	resource_size(&dma_of->resource[0]));
cd9ad58d DM	578
	579	scsi_host_put(esp->host);
	580
05bb5e93 DM	581	dev_set_drvdata(&op->dev, NULL);
05bb5e93 DM	582
f62f9ffd	583	put_device(&dma_of->dev);
cd9ad58d DM	584	}
cd9ad58d DM	585
fd098316	586	static const struct of_device_id esp_match[] = {
cd9ad58d DM	587	{
	588	.name = "SUNW,esp",
	589	},
	590	{
	591	.name = "SUNW,fas",
	592	},
	593	{
	594	.name = "esp",
	595	},
	596	{},
	597	};
	598	MODULE_DEVICE_TABLE(of, esp_match);
	599
4ebb24f7	600	static struct platform_driver esp_sbus_driver = {
4018294b GL	601	.driver = {
4018294b GL	602	.name = "esp",
4018294b GL	603	.of_match_table = esp_match,
4018294b GL	604	},
cd9ad58d	605	.probe = esp_sbus_probe,
6ff482ee	606	.remove_new = esp_sbus_remove,
cd9ad58d	607	};
ea0dc200	608	module_platform_driver(esp_sbus_driver);
cd9ad58d DM	609
cd9ad58d DM	610	MODULE_DESCRIPTION("Sun ESP SCSI driver");
6a57a219	611	MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
cd9ad58d DM	612	MODULE_LICENSE("GPL");
cd9ad58d DM	613	MODULE_VERSION(DRV_VERSION);