[linux-2.6-block.git] / drivers / scsi / sun3x_esp.c

// SPDX-License-Identifier: GPL-2.0-only
/* sun3x_esp.c: ESP front-end for Sun3x systems.
 *
 * Copyright (C) 2007,2008 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
 */

#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/sun3x.h>
#include <asm/dma.h>
#include <asm/dvma.h>

/* DMA controller reg offsets */
#define DMA_CSR		0x00UL	/* rw  DMA control/status register    0x00   */
#define DMA_ADDR        0x04UL	/* rw  DMA transfer address register  0x04   */
#define DMA_COUNT       0x08UL	/* rw  DMA transfer count register    0x08   */
#define DMA_TEST        0x0cUL	/* rw  DMA test/debug register        0x0c   */

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME		"sun3x_esp"
#define PFX DRV_MODULE_NAME	": "
#define DRV_VERSION		"1.000"
#define DRV_MODULE_RELDATE	"Nov 1, 2007"

/*
 * m68k always assumes readl/writel operate on little endian
 * mmio space; this is wrong at least for Sun3x, so we
 * need to workaround this until a proper way is found
 */
#if 0
#define dma_read32(REG) \
	readl(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	writel((VAL), esp->dma_regs + (REG))
#else
#define dma_read32(REG) \
	*(volatile u32 *)(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
#endif

static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	writeb(val, esp->regs + (reg * 4UL));
}

static u8 sun3x_esp_read8(struct esp *esp, unsigned long reg)
{
	return readb(esp->regs + (reg * 4UL));
}

static int sun3x_esp_irq_pending(struct esp *esp)
{
	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
		return 1;
	return 0;
}

static void sun3x_esp_reset_dma(struct esp *esp)
{
	u32 val;

	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_RST_SCSI, DMA_CSR);
	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);

	/* Enable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}

static void sun3x_esp_dma_drain(struct esp *esp)
{
	u32 csr;
	int lim;

	csr = dma_read32(DMA_CSR);
	if (!(csr & DMA_FIFO_ISDRAIN))
		return;

	dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

	lim = 1000;
	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
			       esp->host->unique_id);
			break;
		}
		udelay(1);
	}
}

static void sun3x_esp_dma_invalidate(struct esp *esp)
{
	u32 val;
	int lim;

	lim = 1000;
	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not "
			       "invalidate!\n", esp->host->unique_id);
			break;
		}
		udelay(1);
	}

	val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
	val |= DMA_FIFO_INV;
	dma_write32(val, DMA_CSR);
	val &= ~DMA_FIFO_INV;
	dma_write32(val, DMA_CSR);
}

static void sun3x_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				  u32 dma_count, int write, u8 cmd)
{
	u32 csr;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	sun3x_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	sun3x_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	csr = dma_read32(DMA_CSR);
	csr |= DMA_ENABLE;
	if (write)
		csr |= DMA_ST_WRITE;
	else
		csr &= ~DMA_ST_WRITE;
	dma_write32(csr, DMA_CSR);
	dma_write32(addr, DMA_ADDR);

	scsi_esp_cmd(esp, cmd);
}

static int sun3x_esp_dma_error(struct esp *esp)
{
	u32 csr = dma_read32(DMA_CSR);

	if (csr & DMA_HNDL_ERROR)
		return 1;

	return 0;
}

static const struct esp_driver_ops sun3x_esp_ops = {
	.esp_write8	=	sun3x_esp_write8,
	.esp_read8	=	sun3x_esp_read8,
	.irq_pending	=	sun3x_esp_irq_pending,
	.reset_dma	=	sun3x_esp_reset_dma,
	.dma_drain	=	sun3x_esp_dma_drain,
	.dma_invalidate	=	sun3x_esp_dma_invalidate,
	.send_dma_cmd	=	sun3x_esp_send_dma_cmd,
	.dma_error	=	sun3x_esp_dma_error,
};

static int esp_sun3x_probe(struct platform_device *dev)
{
	struct scsi_host_template *tpnt = &scsi_esp_template;
	struct Scsi_Host *host;
	struct esp *esp;
	struct resource *res;
	int err = -ENOMEM;

	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	if (!host)
		goto fail;

	host->max_id = 8;
	esp = shost_priv(host);

	esp->host = host;
	esp->dev = &dev->dev;
	esp->ops = &sun3x_esp_ops;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res || !res->start)
		goto fail_unlink;

	esp->regs = ioremap_nocache(res->start, 0x20);
	if (!esp->regs)
		goto fail_unmap_regs;

	res = platform_get_resource(dev, IORESOURCE_MEM, 1);
	if (!res || !res->start)
		goto fail_unmap_regs;

	esp->dma_regs = ioremap_nocache(res->start, 0x10);

	esp->command_block = dma_alloc_coherent(esp->dev, 16,
						&esp->command_block_dma,
						GFP_KERNEL);
	if (!esp->command_block)
		goto fail_unmap_regs_dma;

	host->irq = platform_get_irq(dev, 0);
	err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED,
			  "SUN3X ESP", esp);
	if (err < 0)
		goto fail_unmap_command_block;

	esp->scsi_id = 7;
	esp->host->this_id = esp->scsi_id;
	esp->scsi_id_mask = (1 << esp->scsi_id);
	esp->cfreq = 20000000;

	dev_set_drvdata(&dev->dev, esp);

	err = scsi_esp_register(esp);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(host->irq, esp);
fail_unmap_command_block:
	dma_free_coherent(esp->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
fail_unmap_regs_dma:
	iounmap(esp->dma_regs);
fail_unmap_regs:
	iounmap(esp->regs);
fail_unlink:
	scsi_host_put(host);
fail:
	return err;
}

static int esp_sun3x_remove(struct platform_device *dev)
{
	struct esp *esp = dev_get_drvdata(&dev->dev);
	unsigned int irq = esp->host->irq;
	u32 val;

	scsi_esp_unregister(esp);

	/* Disable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);

	free_irq(irq, esp);
	dma_free_coherent(esp->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);

	scsi_host_put(esp->host);

	return 0;
}

static struct platform_driver esp_sun3x_driver = {
	.probe          = esp_sun3x_probe,
	.remove         = esp_sun3x_remove,
	.driver = {
		.name   = "sun3x_esp",
	},
};

static int __init sun3x_esp_init(void)
{
	return platform_driver_register(&esp_sun3x_driver);
}

static void __exit sun3x_esp_exit(void)
{
	platform_driver_unregister(&esp_sun3x_driver);
}

MODULE_DESCRIPTION("Sun3x ESP SCSI driver");
MODULE_AUTHOR("Thomas Bogendoerfer (tsbogend@alpha.franken.de)");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

module_init(sun3x_esp_init);
module_exit(sun3x_esp_exit);
MODULE_ALIAS("platform:sun3x_esp");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
0bb67f18	2	/* sun3x_esp.c: ESP front-end for Sun3x systems.
1da177e4	3	*
0bb67f18	4	* Copyright (C) 2007,2008 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
1da177e4 LT	5	*/
	6
	7	#include <linux/kernel.h>
5a0e3ad6	8	#include <linux/gfp.h>
1da177e4	9	#include <linux/types.h>
1da177e4	10	#include <linux/delay.h>
0bb67f18 TB	11	#include <linux/module.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/dma-mapping.h>
1da177e4	15	#include <linux/interrupt.h>
2584cf83	16	#include <linux/io.h>
1da177e4	17
1da177e4	18	#include <asm/sun3x.h>
0bb67f18	19	#include <asm/dma.h>
1da177e4	20	#include <asm/dvma.h>
1da177e4	21
0bb67f18 TB	22	/* DMA controller reg offsets */
	23	#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
	24	#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
	25	#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
	26	#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
1da177e4	27
0bb67f18	28	#include <scsi/scsi_host.h>
1da177e4	29
0bb67f18	30	#include "esp_scsi.h"
1da177e4	31
0bb67f18 TB	32	#define DRV_MODULE_NAME "sun3x_esp"
	33	#define PFX DRV_MODULE_NAME ": "
	34	#define DRV_VERSION "1.000"
	35	#define DRV_MODULE_RELDATE "Nov 1, 2007"
1da177e4	36
0bb67f18 TB	37	/*
	38	* m68k always assumes readl/writel operate on little endian
	39	* mmio space; this is wrong at least for Sun3x, so we
	40	* need to workaround this until a proper way is found
	41	*/
	42	#if 0
	43	#define dma_read32(REG) \
	44	readl(esp->dma_regs + (REG))
	45	#define dma_write32(VAL, REG) \
	46	writel((VAL), esp->dma_regs + (REG))
	47	#else
	48	#define dma_read32(REG) \
	49	(volatile u32 )(esp->dma_regs + (REG))
	50	#define dma_write32(VAL, REG) \
	51	do { (volatile u32 )(esp->dma_regs + (REG)) = (VAL); } while (0)
	52	#endif
	53
	54	static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg)
	55	{
	56	writeb(val, esp->regs + (reg * 4UL));
1da177e4 LT	57	}
1da177e4 LT	58
0bb67f18	59	static u8 sun3x_esp_read8(struct esp *esp, unsigned long reg)
1da177e4	60	{
0bb67f18	61	return readb(esp->regs + (reg * 4UL));
1da177e4	62	}
0bb67f18	63
0bb67f18	64	static int sun3x_esp_irq_pending(struct esp *esp)
1da177e4	65	{
0bb67f18 TB	66	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR \| DMA_HNDL_ERROR))
	67	return 1;
	68	return 0;
	69	}
1da177e4	70
0bb67f18 TB	71	static void sun3x_esp_reset_dma(struct esp *esp)
	72	{
	73	u32 val;
1da177e4	74
0bb67f18 TB	75	val = dma_read32(DMA_CSR);
	76	dma_write32(val \| DMA_RST_SCSI, DMA_CSR);
	77	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
1da177e4	78
0bb67f18 TB	79	/* Enable interrupts. */
	80	val = dma_read32(DMA_CSR);
	81	dma_write32(val \| DMA_INT_ENAB, DMA_CSR);
1da177e4 LT	82	}
1da177e4 LT	83
0bb67f18	84	static void sun3x_esp_dma_drain(struct esp *esp)
1da177e4	85	{
0bb67f18 TB	86	u32 csr;
0bb67f18 TB	87	int lim;
1da177e4	88
0bb67f18 TB	89	csr = dma_read32(DMA_CSR);
	90	if (!(csr & DMA_FIFO_ISDRAIN))
	91	return;
1da177e4	92
0bb67f18	93	dma_write32(csr \| DMA_FIFO_STDRAIN, DMA_CSR);
1da177e4	94
0bb67f18 TB	95	lim = 1000;
	96	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
	97	if (--lim == 0) {
	98	printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
	99	esp->host->unique_id);
	100	break;
	101	}
	102	udelay(1);
	103	}
1da177e4 LT	104	}
1da177e4 LT	105
0bb67f18	106	static void sun3x_esp_dma_invalidate(struct esp *esp)
1da177e4	107	{
0bb67f18 TB	108	u32 val;
	109	int lim;
	110
	111	lim = 1000;
	112	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
	113	if (--lim == 0) {
	114	printk(KERN_ALERT PFX "esp%d: DMA will not "
	115	"invalidate!\n", esp->host->unique_id);
	116	break;
	117	}
	118	udelay(1);
	119	}
1da177e4	120
0bb67f18 TB	121	val &= ~(DMA_ENABLE \| DMA_ST_WRITE \| DMA_BCNT_ENAB);
	122	val \|= DMA_FIFO_INV;
	123	dma_write32(val, DMA_CSR);
	124	val &= ~DMA_FIFO_INV;
	125	dma_write32(val, DMA_CSR);
1da177e4 LT	126	}
1da177e4 LT	127
0bb67f18 TB	128	static void sun3x_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
0bb67f18 TB	129	u32 dma_count, int write, u8 cmd)
1da177e4	130	{
0bb67f18 TB	131	u32 csr;
	132
	133	BUG_ON(!(cmd & ESP_CMD_DMA));
	134
	135	sun3x_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	136	sun3x_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	137	csr = dma_read32(DMA_CSR);
	138	csr \|= DMA_ENABLE;
	139	if (write)
	140	csr \|= DMA_ST_WRITE;
	141	else
	142	csr &= ~DMA_ST_WRITE;
	143	dma_write32(csr, DMA_CSR);
	144	dma_write32(addr, DMA_ADDR);
	145
	146	scsi_esp_cmd(esp, cmd);
1da177e4 LT	147	}
1da177e4 LT	148
0bb67f18	149	static int sun3x_esp_dma_error(struct esp *esp)
1da177e4	150	{
0bb67f18	151	u32 csr = dma_read32(DMA_CSR);
1da177e4	152
0bb67f18 TB	153	if (csr & DMA_HNDL_ERROR)
	154	return 1;
	155
	156	return 0;
1da177e4 LT	157	}
1da177e4 LT	158
0bb67f18 TB	159	static const struct esp_driver_ops sun3x_esp_ops = {
	160	.esp_write8 = sun3x_esp_write8,
	161	.esp_read8 = sun3x_esp_read8,
0bb67f18 TB	162	.irq_pending = sun3x_esp_irq_pending,
	163	.reset_dma = sun3x_esp_reset_dma,
	164	.dma_drain = sun3x_esp_dma_drain,
	165	.dma_invalidate = sun3x_esp_dma_invalidate,
	166	.send_dma_cmd = sun3x_esp_send_dma_cmd,
	167	.dma_error = sun3x_esp_dma_error,
	168	};
	169
6f039790	170	static int esp_sun3x_probe(struct platform_device *dev)
1da177e4	171	{
0bb67f18 TB	172	struct scsi_host_template *tpnt = &scsi_esp_template;
	173	struct Scsi_Host *host;
	174	struct esp *esp;
	175	struct resource *res;
	176	int err = -ENOMEM;
1da177e4	177
0bb67f18 TB	178	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	179	if (!host)
	180	goto fail;
1da177e4	181
0bb67f18 TB	182	host->max_id = 8;
0bb67f18 TB	183	esp = shost_priv(host);
1da177e4	184
0bb67f18	185	esp->host = host;
e32ec657	186	esp->dev = &dev->dev;
0bb67f18	187	esp->ops = &sun3x_esp_ops;
1da177e4	188
0bb67f18	189	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3fe68cc1	190	if (!res \|\| !res->start)
0bb67f18	191	goto fail_unlink;
1da177e4	192
0bb67f18 TB	193	esp->regs = ioremap_nocache(res->start, 0x20);
	194	if (!esp->regs)
	195	goto fail_unmap_regs;
1da177e4	196
0bb67f18	197	res = platform_get_resource(dev, IORESOURCE_MEM, 1);
3fe68cc1	198	if (!res \|\| !res->start)
0bb67f18	199	goto fail_unmap_regs;
1da177e4	200
0bb67f18	201	esp->dma_regs = ioremap_nocache(res->start, 0x10);
1da177e4	202
0bb67f18 TB	203	esp->command_block = dma_alloc_coherent(esp->dev, 16,
	204	&esp->command_block_dma,
	205	GFP_KERNEL);
	206	if (!esp->command_block)
	207	goto fail_unmap_regs_dma;
1da177e4	208
0bb67f18 TB	209	host->irq = platform_get_irq(dev, 0);
	210	err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED,
	211	"SUN3X ESP", esp);
	212	if (err < 0)
	213	goto fail_unmap_command_block;
1da177e4	214
0bb67f18 TB	215	esp->scsi_id = 7;
	216	esp->host->this_id = esp->scsi_id;
	217	esp->scsi_id_mask = (1 << esp->scsi_id);
	218	esp->cfreq = 20000000;
1da177e4	219
0bb67f18 TB	220	dev_set_drvdata(&dev->dev, esp);
0bb67f18 TB	221
44b1b4d2	222	err = scsi_esp_register(esp);
0bb67f18 TB	223	if (err)
	224	goto fail_free_irq;
	225
	226	return 0;
	227
	228	fail_free_irq:
	229	free_irq(host->irq, esp);
	230	fail_unmap_command_block:
	231	dma_free_coherent(esp->dev, 16,
	232	esp->command_block,
	233	esp->command_block_dma);
	234	fail_unmap_regs_dma:
	235	iounmap(esp->dma_regs);
	236	fail_unmap_regs:
	237	iounmap(esp->regs);
	238	fail_unlink:
	239	scsi_host_put(host);
	240	fail:
	241	return err;
1da177e4 LT	242	}
1da177e4 LT	243
6f039790	244	static int esp_sun3x_remove(struct platform_device *dev)
1da177e4	245	{
0bb67f18 TB	246	struct esp *esp = dev_get_drvdata(&dev->dev);
	247	unsigned int irq = esp->host->irq;
	248	u32 val;
1da177e4	249
0bb67f18	250	scsi_esp_unregister(esp);
1da177e4	251
0bb67f18 TB	252	/* Disable interrupts. */
	253	val = dma_read32(DMA_CSR);
	254	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
1da177e4	255
0bb67f18 TB	256	free_irq(irq, esp);
	257	dma_free_coherent(esp->dev, 16,
	258	esp->command_block,
	259	esp->command_block_dma);
1da177e4	260
0bb67f18	261	scsi_host_put(esp->host);
1da177e4	262
0bb67f18	263	return 0;
1da177e4 LT	264	}
1da177e4 LT	265
0bb67f18 TB	266	static struct platform_driver esp_sun3x_driver = {
0bb67f18 TB	267	.probe = esp_sun3x_probe,
6f039790	268	.remove = esp_sun3x_remove,
0bb67f18 TB	269	.driver = {
	270	.name = "sun3x_esp",
	271	},
1da177e4 LT	272	};
1da177e4 LT	273
0bb67f18 TB	274	static int __init sun3x_esp_init(void)
	275	{
	276	return platform_driver_register(&esp_sun3x_driver);
	277	}
1da177e4	278
0bb67f18 TB	279	static void __exit sun3x_esp_exit(void)
	280	{
	281	platform_driver_unregister(&esp_sun3x_driver);
	282	}
1da177e4	283
0bb67f18 TB	284	MODULE_DESCRIPTION("Sun3x ESP SCSI driver");
0bb67f18 TB	285	MODULE_AUTHOR("Thomas Bogendoerfer (tsbogend@alpha.franken.de)");
1da177e4	286	MODULE_LICENSE("GPL");
0bb67f18 TB	287	MODULE_VERSION(DRV_VERSION);
	288
	289	module_init(sun3x_esp_init);
	290	module_exit(sun3x_esp_exit);
ecc1241e	291	MODULE_ALIAS("platform:sun3x_esp");