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1da177e4 LT |
1 | /* |
2 | * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl) | |
3 | * | |
4 | * Sun3 DMA additions by Sam Creasey (sammy@sammy.net) | |
5 | * | |
6 | * Adapted from mac_scsinew.h: | |
7 | */ | |
8 | /* | |
9 | * Cumana Generic NCR5380 driver defines | |
10 | * | |
11 | * Copyright 1993, Drew Eckhardt | |
12 | * Visionary Computing | |
13 | * (Unix and Linux consulting and custom programming) | |
14 | * drew@colorado.edu | |
15 | * +1 (303) 440-4894 | |
16 | * | |
17 | * ALPHA RELEASE 1. | |
18 | * | |
19 | * For more information, please consult | |
20 | * | |
21 | * NCR 5380 Family | |
22 | * SCSI Protocol Controller | |
23 | * Databook | |
24 | * | |
25 | * NCR Microelectronics | |
26 | * 1635 Aeroplaza Drive | |
27 | * Colorado Springs, CO 80916 | |
28 | * 1+ (719) 578-3400 | |
29 | * 1+ (800) 334-5454 | |
30 | */ | |
31 | ||
9f6620a3 FT |
32 | #ifndef SUN3_SCSI_H |
33 | #define SUN3_SCSI_H | |
1da177e4 LT |
34 | |
35 | #define SUN3SCSI_PUBLIC_RELEASE 1 | |
36 | ||
37 | /* | |
38 | * Int: level 2 autovector | |
39 | * IO: type 1, base 0x00140000, 5 bits phys space: A<4..0> | |
40 | */ | |
41 | #define IRQ_SUN3_SCSI 2 | |
42 | #define IOBASE_SUN3_SCSI 0x00140000 | |
43 | ||
44 | #define IOBASE_SUN3_VMESCSI 0xff200000 | |
45 | ||
811c9366 | 46 | static int sun3scsi_abort(struct scsi_cmnd *); |
d0be4a7d | 47 | static int sun3scsi_detect (struct scsi_host_template *); |
1da177e4 | 48 | static const char *sun3scsi_info (struct Scsi_Host *); |
811c9366 | 49 | static int sun3scsi_bus_reset(struct scsi_cmnd *); |
f281233d | 50 | static int sun3scsi_queue_command(struct Scsi_Host *, struct scsi_cmnd *); |
1da177e4 LT |
51 | static int sun3scsi_release (struct Scsi_Host *); |
52 | ||
53 | #ifndef CMD_PER_LUN | |
54 | #define CMD_PER_LUN 2 | |
55 | #endif | |
56 | ||
57 | #ifndef CAN_QUEUE | |
58 | #define CAN_QUEUE 16 | |
59 | #endif | |
60 | ||
61 | #ifndef SG_TABLESIZE | |
62 | #define SG_TABLESIZE SG_NONE | |
63 | #endif | |
64 | ||
65 | #ifndef MAX_TAGS | |
66 | #define MAX_TAGS 32 | |
67 | #endif | |
68 | ||
69 | #ifndef USE_TAGGED_QUEUING | |
70 | #define USE_TAGGED_QUEUING 1 | |
71 | #endif | |
72 | ||
73 | #include <scsi/scsicam.h> | |
74 | ||
75 | #ifdef SUN3_SCSI_VME | |
76 | #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI" | |
77 | #else | |
78 | #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI" | |
79 | #endif | |
80 | ||
1da177e4 LT |
81 | #define NCR5380_implementation_fields \ |
82 | int port, ctrl | |
83 | ||
84 | #define NCR5380_local_declare() \ | |
85 | struct Scsi_Host *_instance | |
86 | ||
87 | #define NCR5380_setup(instance) \ | |
88 | _instance = instance | |
89 | ||
90 | #define NCR5380_read(reg) sun3scsi_read(reg) | |
91 | #define NCR5380_write(reg, value) sun3scsi_write(reg, value) | |
92 | ||
93 | #define NCR5380_intr sun3scsi_intr | |
94 | #define NCR5380_queue_command sun3scsi_queue_command | |
95 | #define NCR5380_bus_reset sun3scsi_bus_reset | |
96 | #define NCR5380_abort sun3scsi_abort | |
9dcc26cf | 97 | #define NCR5380_show_info sun3scsi_show_info |
1da177e4 LT |
98 | #define NCR5380_dma_xfer_len(i, cmd, phase) \ |
99 | sun3scsi_dma_xfer_len(cmd->SCp.this_residual,cmd,((phase) & SR_IO) ? 0 : 1) | |
100 | ||
101 | #define NCR5380_dma_write_setup(instance, data, count) sun3scsi_dma_setup(data, count, 1) | |
102 | #define NCR5380_dma_read_setup(instance, data, count) sun3scsi_dma_setup(data, count, 0) | |
103 | #define NCR5380_dma_residual sun3scsi_dma_residual | |
104 | ||
1da177e4 LT |
105 | /* additional registers - mainly DMA control regs */ |
106 | /* these start at regbase + 8 -- directly after the NCR regs */ | |
107 | struct sun3_dma_regs { | |
108 | unsigned short dma_addr_hi; /* vme only */ | |
109 | unsigned short dma_addr_lo; /* vme only */ | |
110 | unsigned short dma_count_hi; /* vme only */ | |
111 | unsigned short dma_count_lo; /* vme only */ | |
112 | unsigned short udc_data; /* udc dma data reg (obio only) */ | |
113 | unsigned short udc_addr; /* uda dma addr reg (obio only) */ | |
114 | unsigned short fifo_data; /* fifo data reg, holds extra byte on | |
115 | odd dma reads */ | |
116 | unsigned short fifo_count; | |
117 | unsigned short csr; /* control/status reg */ | |
118 | unsigned short bpack_hi; /* vme only */ | |
119 | unsigned short bpack_lo; /* vme only */ | |
120 | unsigned short ivect; /* vme only */ | |
121 | unsigned short fifo_count_hi; /* vme only */ | |
122 | }; | |
123 | ||
124 | /* ucd chip specific regs - live in dvma space */ | |
125 | struct sun3_udc_regs { | |
126 | unsigned short rsel; /* select regs to load */ | |
127 | unsigned short addr_hi; /* high word of addr */ | |
128 | unsigned short addr_lo; /* low word */ | |
129 | unsigned short count; /* words to be xfer'd */ | |
130 | unsigned short mode_hi; /* high word of channel mode */ | |
131 | unsigned short mode_lo; /* low word of channel mode */ | |
132 | }; | |
133 | ||
134 | /* addresses of the udc registers */ | |
135 | #define UDC_MODE 0x38 | |
136 | #define UDC_CSR 0x2e /* command/status */ | |
137 | #define UDC_CHN_HI 0x26 /* chain high word */ | |
138 | #define UDC_CHN_LO 0x22 /* chain lo word */ | |
139 | #define UDC_CURA_HI 0x1a /* cur reg A high */ | |
140 | #define UDC_CURA_LO 0x0a /* cur reg A low */ | |
141 | #define UDC_CURB_HI 0x12 /* cur reg B high */ | |
142 | #define UDC_CURB_LO 0x02 /* cur reg B low */ | |
143 | #define UDC_MODE_HI 0x56 /* mode reg high */ | |
144 | #define UDC_MODE_LO 0x52 /* mode reg low */ | |
145 | #define UDC_COUNT 0x32 /* words to xfer */ | |
146 | ||
147 | /* some udc commands */ | |
148 | #define UDC_RESET 0 | |
149 | #define UDC_CHN_START 0xa0 /* start chain */ | |
150 | #define UDC_INT_ENABLE 0x32 /* channel 1 int on */ | |
151 | ||
152 | /* udc mode words */ | |
153 | #define UDC_MODE_HIWORD 0x40 | |
154 | #define UDC_MODE_LSEND 0xc2 | |
155 | #define UDC_MODE_LRECV 0xd2 | |
156 | ||
157 | /* udc reg selections */ | |
158 | #define UDC_RSEL_SEND 0x282 | |
159 | #define UDC_RSEL_RECV 0x182 | |
160 | ||
161 | /* bits in csr reg */ | |
162 | #define CSR_DMA_ACTIVE 0x8000 | |
163 | #define CSR_DMA_CONFLICT 0x4000 | |
164 | #define CSR_DMA_BUSERR 0x2000 | |
165 | ||
166 | #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */ | |
167 | #define CSR_SDB_INT 0x200 /* sbc interrupt pending */ | |
168 | #define CSR_DMA_INT 0x100 /* dma interrupt pending */ | |
169 | ||
170 | #define CSR_LEFT 0xc0 | |
171 | #define CSR_LEFT_3 0xc0 | |
172 | #define CSR_LEFT_2 0x80 | |
173 | #define CSR_LEFT_1 0x40 | |
174 | #define CSR_PACK_ENABLE 0x20 | |
175 | ||
176 | #define CSR_DMA_ENABLE 0x10 | |
177 | ||
178 | #define CSR_SEND 0x8 /* 1 = send 0 = recv */ | |
179 | #define CSR_FIFO 0x2 /* reset fifo */ | |
180 | #define CSR_INTR 0x4 /* interrupt enable */ | |
181 | #define CSR_SCSI 0x1 | |
182 | ||
183 | #define VME_DATA24 0x3d00 | |
184 | ||
9f6620a3 | 185 | #endif /* SUN3_SCSI_H */ |
1da177e4 | 186 |