Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl) | |
4 | * | |
5 | * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net) | |
6 | * | |
757f5bad FT |
7 | * VME support added by Sam Creasey |
8 | * | |
9 | * TODO: modify this driver to support multiple Sun3 SCSI VME boards | |
10 | * | |
1da177e4 LT |
11 | * Adapted from mac_scsinew.c: |
12 | */ | |
13 | /* | |
14 | * Generic Macintosh NCR5380 driver | |
15 | * | |
16 | * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov> | |
17 | * | |
18 | * derived in part from: | |
19 | */ | |
20 | /* | |
21 | * Generic Generic NCR5380 driver | |
22 | * | |
23 | * Copyright 1995, Russell King | |
1da177e4 LT |
24 | */ |
25 | ||
1da177e4 | 26 | #include <linux/types.h> |
1da177e4 | 27 | #include <linux/delay.h> |
1da177e4 | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | #include <linux/ioport.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/blkdev.h> | |
0d31f875 | 32 | #include <linux/platform_device.h> |
1da177e4 LT |
33 | |
34 | #include <asm/io.h> | |
1da177e4 | 35 | #include <asm/dvma.h> |
1da177e4 | 36 | |
1da177e4 | 37 | #include <scsi/scsi_host.h> |
1da177e4 | 38 | |
8dad0c51 FT |
39 | /* minimum number of bytes to do dma on */ |
40 | #define DMA_MIN_SIZE 129 | |
1da177e4 | 41 | |
e63449c4 FT |
42 | /* Definitions for the core NCR5380 driver. */ |
43 | ||
2231ef87 FT |
44 | #define NCR5380_implementation_fields /* none */ |
45 | ||
61e1ce58 FT |
46 | #define NCR5380_read(reg) in_8(hostdata->io + (reg)) |
47 | #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value) | |
2231ef87 FT |
48 | |
49 | #define NCR5380_queue_command sun3scsi_queue_command | |
12e5fc66 | 50 | #define NCR5380_host_reset sun3scsi_host_reset |
2231ef87 | 51 | #define NCR5380_abort sun3scsi_abort |
2231ef87 FT |
52 | #define NCR5380_info sun3scsi_info |
53 | ||
4a98f896 FT |
54 | #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len |
55 | #define NCR5380_dma_recv_setup sun3scsi_dma_count | |
56 | #define NCR5380_dma_send_setup sun3scsi_dma_count | |
57 | #define NCR5380_dma_residual sun3scsi_dma_residual | |
2231ef87 FT |
58 | |
59 | #include "NCR5380.h" | |
60 | ||
14d739f6 FT |
61 | /* dma regs start at regbase + 8, directly after the NCR regs */ |
62 | struct sun3_dma_regs { | |
63 | unsigned short dma_addr_hi; /* vme only */ | |
64 | unsigned short dma_addr_lo; /* vme only */ | |
65 | unsigned short dma_count_hi; /* vme only */ | |
66 | unsigned short dma_count_lo; /* vme only */ | |
67 | unsigned short udc_data; /* udc dma data reg (obio only) */ | |
68 | unsigned short udc_addr; /* uda dma addr reg (obio only) */ | |
69 | unsigned short fifo_data; /* fifo data reg, | |
70 | * holds extra byte on odd dma reads | |
71 | */ | |
72 | unsigned short fifo_count; | |
73 | unsigned short csr; /* control/status reg */ | |
74 | unsigned short bpack_hi; /* vme only */ | |
75 | unsigned short bpack_lo; /* vme only */ | |
76 | unsigned short ivect; /* vme only */ | |
77 | unsigned short fifo_count_hi; /* vme only */ | |
78 | }; | |
79 | ||
80 | /* ucd chip specific regs - live in dvma space */ | |
81 | struct sun3_udc_regs { | |
82 | unsigned short rsel; /* select regs to load */ | |
83 | unsigned short addr_hi; /* high word of addr */ | |
84 | unsigned short addr_lo; /* low word */ | |
85 | unsigned short count; /* words to be xfer'd */ | |
86 | unsigned short mode_hi; /* high word of channel mode */ | |
87 | unsigned short mode_lo; /* low word of channel mode */ | |
88 | }; | |
89 | ||
90 | /* addresses of the udc registers */ | |
91 | #define UDC_MODE 0x38 | |
92 | #define UDC_CSR 0x2e /* command/status */ | |
93 | #define UDC_CHN_HI 0x26 /* chain high word */ | |
94 | #define UDC_CHN_LO 0x22 /* chain lo word */ | |
95 | #define UDC_CURA_HI 0x1a /* cur reg A high */ | |
96 | #define UDC_CURA_LO 0x0a /* cur reg A low */ | |
97 | #define UDC_CURB_HI 0x12 /* cur reg B high */ | |
98 | #define UDC_CURB_LO 0x02 /* cur reg B low */ | |
99 | #define UDC_MODE_HI 0x56 /* mode reg high */ | |
100 | #define UDC_MODE_LO 0x52 /* mode reg low */ | |
101 | #define UDC_COUNT 0x32 /* words to xfer */ | |
102 | ||
103 | /* some udc commands */ | |
104 | #define UDC_RESET 0 | |
105 | #define UDC_CHN_START 0xa0 /* start chain */ | |
106 | #define UDC_INT_ENABLE 0x32 /* channel 1 int on */ | |
107 | ||
108 | /* udc mode words */ | |
109 | #define UDC_MODE_HIWORD 0x40 | |
110 | #define UDC_MODE_LSEND 0xc2 | |
111 | #define UDC_MODE_LRECV 0xd2 | |
112 | ||
113 | /* udc reg selections */ | |
114 | #define UDC_RSEL_SEND 0x282 | |
115 | #define UDC_RSEL_RECV 0x182 | |
116 | ||
117 | /* bits in csr reg */ | |
118 | #define CSR_DMA_ACTIVE 0x8000 | |
119 | #define CSR_DMA_CONFLICT 0x4000 | |
120 | #define CSR_DMA_BUSERR 0x2000 | |
121 | ||
122 | #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */ | |
123 | #define CSR_SDB_INT 0x200 /* sbc interrupt pending */ | |
124 | #define CSR_DMA_INT 0x100 /* dma interrupt pending */ | |
125 | ||
126 | #define CSR_LEFT 0xc0 | |
127 | #define CSR_LEFT_3 0xc0 | |
128 | #define CSR_LEFT_2 0x80 | |
129 | #define CSR_LEFT_1 0x40 | |
130 | #define CSR_PACK_ENABLE 0x20 | |
131 | ||
132 | #define CSR_DMA_ENABLE 0x10 | |
133 | ||
134 | #define CSR_SEND 0x8 /* 1 = send 0 = recv */ | |
135 | #define CSR_FIFO 0x2 /* reset fifo */ | |
136 | #define CSR_INTR 0x4 /* interrupt enable */ | |
137 | #define CSR_SCSI 0x1 | |
138 | ||
139 | #define VME_DATA24 0x3d00 | |
2231ef87 FT |
140 | |
141 | extern int sun3_map_test(unsigned long, char *); | |
142 | ||
1da177e4 LT |
143 | static int setup_can_queue = -1; |
144 | module_param(setup_can_queue, int, 0); | |
145 | static int setup_cmd_per_lun = -1; | |
146 | module_param(setup_cmd_per_lun, int, 0); | |
147 | static int setup_sg_tablesize = -1; | |
148 | module_param(setup_sg_tablesize, int, 0); | |
1da177e4 LT |
149 | static int setup_hostid = -1; |
150 | module_param(setup_hostid, int, 0); | |
151 | ||
1da177e4 LT |
152 | /* ms to wait after hitting dma regs */ |
153 | #define SUN3_DMA_DELAY 10 | |
154 | ||
155 | /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */ | |
156 | #define SUN3_DVMA_BUFSIZE 0xe000 | |
157 | ||
2231ef87 | 158 | static struct scsi_cmnd *sun3_dma_setup_done; |
1da177e4 | 159 | static volatile struct sun3_dma_regs *dregs; |
0d31f875 | 160 | static struct sun3_udc_regs *udc_regs; |
d5f7e65d FT |
161 | static unsigned char *sun3_dma_orig_addr; |
162 | static unsigned long sun3_dma_orig_count; | |
163 | static int sun3_dma_active; | |
164 | static unsigned long last_residual; | |
1da177e4 | 165 | |
757f5bad | 166 | #ifndef SUN3_SCSI_VME |
1da177e4 LT |
167 | /* dma controller register access functions */ |
168 | ||
169 | static inline unsigned short sun3_udc_read(unsigned char reg) | |
170 | { | |
171 | unsigned short ret; | |
172 | ||
173 | dregs->udc_addr = UDC_CSR; | |
174 | udelay(SUN3_DMA_DELAY); | |
175 | ret = dregs->udc_data; | |
176 | udelay(SUN3_DMA_DELAY); | |
177 | ||
178 | return ret; | |
179 | } | |
180 | ||
181 | static inline void sun3_udc_write(unsigned short val, unsigned char reg) | |
182 | { | |
183 | dregs->udc_addr = reg; | |
184 | udelay(SUN3_DMA_DELAY); | |
185 | dregs->udc_data = val; | |
186 | udelay(SUN3_DMA_DELAY); | |
187 | } | |
757f5bad | 188 | #endif |
1da177e4 | 189 | |
1da177e4 LT |
190 | // safe bits for the CSR |
191 | #define CSR_GOOD 0x060f | |
192 | ||
cd46140a | 193 | static irqreturn_t scsi_sun3_intr(int irq, void *dev) |
1da177e4 | 194 | { |
cd46140a | 195 | struct Scsi_Host *instance = dev; |
1da177e4 LT |
196 | unsigned short csr = dregs->csr; |
197 | int handled = 0; | |
198 | ||
757f5bad FT |
199 | #ifdef SUN3_SCSI_VME |
200 | dregs->csr &= ~CSR_DMA_ENABLE; | |
201 | #endif | |
202 | ||
1da177e4 | 203 | if(csr & ~CSR_GOOD) { |
cd46140a FT |
204 | if (csr & CSR_DMA_BUSERR) |
205 | shost_printk(KERN_ERR, instance, "bus error in DMA\n"); | |
206 | if (csr & CSR_DMA_CONFLICT) | |
207 | shost_printk(KERN_ERR, instance, "DMA conflict\n"); | |
1da177e4 LT |
208 | handled = 1; |
209 | } | |
210 | ||
211 | if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { | |
cd46140a | 212 | NCR5380_intr(irq, dev); |
1da177e4 LT |
213 | handled = 1; |
214 | } | |
215 | ||
216 | return IRQ_RETVAL(handled); | |
217 | } | |
218 | ||
1da177e4 | 219 | /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */ |
4a98f896 FT |
220 | static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata, |
221 | unsigned char *data, int count, int write_flag) | |
1da177e4 | 222 | { |
1da177e4 LT |
223 | void *addr; |
224 | ||
225 | if(sun3_dma_orig_addr != NULL) | |
226 | dvma_unmap(sun3_dma_orig_addr); | |
227 | ||
757f5bad FT |
228 | #ifdef SUN3_SCSI_VME |
229 | addr = (void *)dvma_map_vme((unsigned long) data, count); | |
230 | #else | |
1da177e4 | 231 | addr = (void *)dvma_map((unsigned long) data, count); |
757f5bad | 232 | #endif |
1da177e4 LT |
233 | |
234 | sun3_dma_orig_addr = addr; | |
235 | sun3_dma_orig_count = count; | |
757f5bad FT |
236 | |
237 | #ifndef SUN3_SCSI_VME | |
1da177e4 LT |
238 | dregs->fifo_count = 0; |
239 | sun3_udc_write(UDC_RESET, UDC_CSR); | |
240 | ||
241 | /* reset fifo */ | |
242 | dregs->csr &= ~CSR_FIFO; | |
243 | dregs->csr |= CSR_FIFO; | |
757f5bad | 244 | #endif |
1da177e4 LT |
245 | |
246 | /* set direction */ | |
247 | if(write_flag) | |
248 | dregs->csr |= CSR_SEND; | |
249 | else | |
250 | dregs->csr &= ~CSR_SEND; | |
251 | ||
757f5bad FT |
252 | #ifdef SUN3_SCSI_VME |
253 | dregs->csr |= CSR_PACK_ENABLE; | |
254 | ||
255 | dregs->dma_addr_hi = ((unsigned long)addr >> 16); | |
256 | dregs->dma_addr_lo = ((unsigned long)addr & 0xffff); | |
257 | ||
258 | dregs->dma_count_hi = 0; | |
259 | dregs->dma_count_lo = 0; | |
260 | dregs->fifo_count_hi = 0; | |
261 | dregs->fifo_count = 0; | |
262 | #else | |
1da177e4 LT |
263 | /* byte count for fifo */ |
264 | dregs->fifo_count = count; | |
265 | ||
266 | sun3_udc_write(UDC_RESET, UDC_CSR); | |
267 | ||
268 | /* reset fifo */ | |
269 | dregs->csr &= ~CSR_FIFO; | |
270 | dregs->csr |= CSR_FIFO; | |
271 | ||
272 | if(dregs->fifo_count != count) { | |
4a98f896 FT |
273 | shost_printk(KERN_ERR, hostdata->host, |
274 | "FIFO mismatch %04x not %04x\n", | |
cd46140a | 275 | dregs->fifo_count, (unsigned int) count); |
4a98f896 | 276 | NCR5380_dprint(NDEBUG_DMA, hostdata->host); |
1da177e4 LT |
277 | } |
278 | ||
279 | /* setup udc */ | |
1da177e4 LT |
280 | udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8); |
281 | udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff); | |
1da177e4 LT |
282 | udc_regs->count = count/2; /* count in words */ |
283 | udc_regs->mode_hi = UDC_MODE_HIWORD; | |
284 | if(write_flag) { | |
285 | if(count & 1) | |
286 | udc_regs->count++; | |
287 | udc_regs->mode_lo = UDC_MODE_LSEND; | |
288 | udc_regs->rsel = UDC_RSEL_SEND; | |
289 | } else { | |
290 | udc_regs->mode_lo = UDC_MODE_LRECV; | |
291 | udc_regs->rsel = UDC_RSEL_RECV; | |
292 | } | |
293 | ||
294 | /* announce location of regs block */ | |
295 | sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8), | |
296 | UDC_CHN_HI); | |
297 | ||
298 | sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO); | |
299 | ||
300 | /* set dma master on */ | |
301 | sun3_udc_write(0xd, UDC_MODE); | |
302 | ||
303 | /* interrupt enable */ | |
304 | sun3_udc_write(UDC_INT_ENABLE, UDC_CSR); | |
757f5bad | 305 | #endif |
1da177e4 LT |
306 | |
307 | return count; | |
308 | ||
309 | } | |
310 | ||
4a98f896 FT |
311 | static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata, |
312 | unsigned char *data, int count) | |
313 | { | |
314 | return count; | |
315 | } | |
316 | ||
317 | static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata, | |
318 | unsigned char *data, int count) | |
319 | { | |
320 | return sun3scsi_dma_setup(hostdata, data, count, 0); | |
321 | } | |
322 | ||
323 | static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata, | |
324 | unsigned char *data, int count) | |
325 | { | |
326 | return sun3scsi_dma_setup(hostdata, data, count, 1); | |
327 | } | |
328 | ||
329 | static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata) | |
1da177e4 LT |
330 | { |
331 | return last_residual; | |
332 | } | |
333 | ||
4a98f896 FT |
334 | static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata, |
335 | struct scsi_cmnd *cmd) | |
1da177e4 | 336 | { |
4a98f896 FT |
337 | int wanted_len = cmd->SCp.this_residual; |
338 | ||
57292b58 | 339 | if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request)) |
1da177e4 | 340 | return 0; |
e63449c4 FT |
341 | |
342 | return wanted_len; | |
1da177e4 LT |
343 | } |
344 | ||
345 | static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data) | |
346 | { | |
757f5bad FT |
347 | #ifdef SUN3_SCSI_VME |
348 | unsigned short csr; | |
349 | ||
350 | csr = dregs->csr; | |
351 | ||
352 | dregs->dma_count_hi = (sun3_dma_orig_count >> 16); | |
353 | dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff); | |
1da177e4 | 354 | |
757f5bad FT |
355 | dregs->fifo_count_hi = (sun3_dma_orig_count >> 16); |
356 | dregs->fifo_count = (sun3_dma_orig_count & 0xffff); | |
357 | ||
358 | /* if(!(csr & CSR_DMA_ENABLE)) | |
359 | * dregs->csr |= CSR_DMA_ENABLE; | |
360 | */ | |
361 | #else | |
1da177e4 | 362 | sun3_udc_write(UDC_CHN_START, UDC_CSR); |
757f5bad | 363 | #endif |
1da177e4 LT |
364 | |
365 | return 0; | |
366 | } | |
367 | ||
368 | /* clean up after our dma is done */ | |
369 | static int sun3scsi_dma_finish(int write_flag) | |
370 | { | |
757f5bad | 371 | unsigned short __maybe_unused count; |
1da177e4 LT |
372 | unsigned short fifo; |
373 | int ret = 0; | |
374 | ||
375 | sun3_dma_active = 0; | |
757f5bad FT |
376 | |
377 | #ifdef SUN3_SCSI_VME | |
378 | dregs->csr &= ~CSR_DMA_ENABLE; | |
379 | ||
380 | fifo = dregs->fifo_count; | |
381 | if (write_flag) { | |
382 | if ((fifo > 0) && (fifo < sun3_dma_orig_count)) | |
383 | fifo++; | |
384 | } | |
385 | ||
386 | last_residual = fifo; | |
387 | /* empty bytes from the fifo which didn't make it */ | |
388 | if ((!write_flag) && (dregs->csr & CSR_LEFT)) { | |
389 | unsigned char *vaddr; | |
390 | ||
391 | vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr); | |
392 | ||
393 | vaddr += (sun3_dma_orig_count - fifo); | |
394 | vaddr--; | |
395 | ||
396 | switch (dregs->csr & CSR_LEFT) { | |
397 | case CSR_LEFT_3: | |
398 | *vaddr = (dregs->bpack_lo & 0xff00) >> 8; | |
399 | vaddr--; | |
400 | ||
401 | case CSR_LEFT_2: | |
402 | *vaddr = (dregs->bpack_hi & 0x00ff); | |
403 | vaddr--; | |
404 | ||
405 | case CSR_LEFT_1: | |
406 | *vaddr = (dregs->bpack_hi & 0xff00) >> 8; | |
407 | break; | |
408 | } | |
409 | } | |
410 | #else | |
1da177e4 LT |
411 | // check to empty the fifo on a read |
412 | if(!write_flag) { | |
413 | int tmo = 20000; /* .2 sec */ | |
414 | ||
415 | while(1) { | |
416 | if(dregs->csr & CSR_FIFO_EMPTY) | |
417 | break; | |
418 | ||
419 | if(--tmo <= 0) { | |
420 | printk("sun3scsi: fifo failed to empty!\n"); | |
421 | return 1; | |
422 | } | |
423 | udelay(10); | |
424 | } | |
425 | } | |
1da177e4 | 426 | |
cd46140a FT |
427 | dregs->udc_addr = 0x32; |
428 | udelay(SUN3_DMA_DELAY); | |
429 | count = 2 * dregs->udc_data; | |
430 | udelay(SUN3_DMA_DELAY); | |
1da177e4 LT |
431 | |
432 | fifo = dregs->fifo_count; | |
433 | last_residual = fifo; | |
434 | ||
435 | /* empty bytes from the fifo which didn't make it */ | |
436 | if((!write_flag) && (count - fifo) == 2) { | |
437 | unsigned short data; | |
438 | unsigned char *vaddr; | |
439 | ||
440 | data = dregs->fifo_data; | |
441 | vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr); | |
442 | ||
443 | vaddr += (sun3_dma_orig_count - fifo); | |
444 | ||
445 | vaddr[-2] = (data & 0xff00) >> 8; | |
446 | vaddr[-1] = (data & 0xff); | |
447 | } | |
757f5bad | 448 | #endif |
1da177e4 LT |
449 | |
450 | dvma_unmap(sun3_dma_orig_addr); | |
451 | sun3_dma_orig_addr = NULL; | |
757f5bad FT |
452 | |
453 | #ifdef SUN3_SCSI_VME | |
454 | dregs->dma_addr_hi = 0; | |
455 | dregs->dma_addr_lo = 0; | |
456 | dregs->dma_count_hi = 0; | |
457 | dregs->dma_count_lo = 0; | |
458 | ||
459 | dregs->fifo_count = 0; | |
460 | dregs->fifo_count_hi = 0; | |
461 | ||
462 | dregs->csr &= ~CSR_SEND; | |
463 | /* dregs->csr |= CSR_DMA_ENABLE; */ | |
464 | #else | |
1da177e4 LT |
465 | sun3_udc_write(UDC_RESET, UDC_CSR); |
466 | dregs->fifo_count = 0; | |
467 | dregs->csr &= ~CSR_SEND; | |
468 | ||
469 | /* reset fifo */ | |
470 | dregs->csr &= ~CSR_FIFO; | |
471 | dregs->csr |= CSR_FIFO; | |
757f5bad | 472 | #endif |
1da177e4 LT |
473 | |
474 | sun3_dma_setup_done = NULL; | |
475 | ||
476 | return ret; | |
477 | ||
478 | } | |
479 | ||
e9db3198 | 480 | #include "NCR5380.c" |
1da177e4 | 481 | |
0d31f875 FT |
482 | #ifdef SUN3_SCSI_VME |
483 | #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI" | |
484 | #define DRV_MODULE_NAME "sun3_scsi_vme" | |
485 | #else | |
486 | #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI" | |
487 | #define DRV_MODULE_NAME "sun3_scsi" | |
488 | #endif | |
489 | ||
490 | #define PFX DRV_MODULE_NAME ": " | |
491 | ||
492 | static struct scsi_host_template sun3_scsi_template = { | |
493 | .module = THIS_MODULE, | |
494 | .proc_name = DRV_MODULE_NAME, | |
1da177e4 | 495 | .name = SUN3_SCSI_NAME, |
1da177e4 LT |
496 | .info = sun3scsi_info, |
497 | .queuecommand = sun3scsi_queue_command, | |
aa2e2cb1 | 498 | .eh_abort_handler = sun3scsi_abort, |
12e5fc66 | 499 | .eh_host_reset_handler = sun3scsi_host_reset, |
d572f65f | 500 | .can_queue = 16, |
1da177e4 | 501 | .this_id = 7, |
d572f65f FT |
502 | .sg_tablesize = SG_NONE, |
503 | .cmd_per_lun = 2, | |
4af14d11 | 504 | .dma_boundary = PAGE_SIZE - 1, |
32b26a10 | 505 | .cmd_size = NCR5380_CMD_SIZE, |
1da177e4 LT |
506 | }; |
507 | ||
0d31f875 FT |
508 | static int __init sun3_scsi_probe(struct platform_device *pdev) |
509 | { | |
510 | struct Scsi_Host *instance; | |
820682b1 | 511 | struct NCR5380_hostdata *hostdata; |
0d31f875 FT |
512 | int error; |
513 | struct resource *irq, *mem; | |
61e1ce58 | 514 | void __iomem *ioaddr; |
ca513fc9 | 515 | int host_flags = 0; |
0d31f875 FT |
516 | #ifdef SUN3_SCSI_VME |
517 | int i; | |
518 | #endif | |
519 | ||
520 | if (setup_can_queue > 0) | |
521 | sun3_scsi_template.can_queue = setup_can_queue; | |
522 | if (setup_cmd_per_lun > 0) | |
523 | sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun; | |
524 | if (setup_sg_tablesize >= 0) | |
525 | sun3_scsi_template.sg_tablesize = setup_sg_tablesize; | |
526 | if (setup_hostid >= 0) | |
527 | sun3_scsi_template.this_id = setup_hostid & 7; | |
528 | ||
0d31f875 FT |
529 | #ifdef SUN3_SCSI_VME |
530 | ioaddr = NULL; | |
531 | for (i = 0; i < 2; i++) { | |
532 | unsigned char x; | |
533 | ||
534 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, i); | |
535 | mem = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
536 | if (!irq || !mem) | |
537 | break; | |
538 | ||
539 | ioaddr = sun3_ioremap(mem->start, resource_size(mem), | |
540 | SUN3_PAGE_TYPE_VME16); | |
541 | dregs = (struct sun3_dma_regs *)(ioaddr + 8); | |
542 | ||
543 | if (sun3_map_test((unsigned long)dregs, &x)) { | |
544 | unsigned short oldcsr; | |
545 | ||
546 | oldcsr = dregs->csr; | |
547 | dregs->csr = 0; | |
548 | udelay(SUN3_DMA_DELAY); | |
549 | if (dregs->csr == 0x1400) | |
550 | break; | |
551 | ||
552 | dregs->csr = oldcsr; | |
553 | } | |
554 | ||
555 | iounmap(ioaddr); | |
556 | ioaddr = NULL; | |
557 | } | |
558 | if (!ioaddr) | |
559 | return -ENODEV; | |
560 | #else | |
561 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
562 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
563 | if (!irq || !mem) | |
564 | return -ENODEV; | |
565 | ||
566 | ioaddr = ioremap(mem->start, resource_size(mem)); | |
567 | dregs = (struct sun3_dma_regs *)(ioaddr + 8); | |
568 | ||
569 | udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)); | |
570 | if (!udc_regs) { | |
571 | pr_err(PFX "couldn't allocate DVMA memory!\n"); | |
572 | iounmap(ioaddr); | |
573 | return -ENOMEM; | |
574 | } | |
575 | #endif | |
576 | ||
0d31f875 FT |
577 | instance = scsi_host_alloc(&sun3_scsi_template, |
578 | sizeof(struct NCR5380_hostdata)); | |
579 | if (!instance) { | |
580 | error = -ENOMEM; | |
581 | goto fail_alloc; | |
582 | } | |
0d31f875 | 583 | |
0d31f875 FT |
584 | instance->irq = irq->start; |
585 | ||
820682b1 | 586 | hostdata = shost_priv(instance); |
61e1ce58 FT |
587 | hostdata->base = mem->start; |
588 | hostdata->io = ioaddr; | |
820682b1 | 589 | |
0ad0eff9 FT |
590 | error = NCR5380_init(instance, host_flags); |
591 | if (error) | |
592 | goto fail_init; | |
0d31f875 FT |
593 | |
594 | error = request_irq(instance->irq, scsi_sun3_intr, 0, | |
595 | "NCR5380", instance); | |
596 | if (error) { | |
0d31f875 FT |
597 | pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n", |
598 | instance->host_no, instance->irq); | |
599 | goto fail_irq; | |
0d31f875 FT |
600 | } |
601 | ||
602 | dregs->csr = 0; | |
603 | udelay(SUN3_DMA_DELAY); | |
604 | dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; | |
605 | udelay(SUN3_DMA_DELAY); | |
606 | dregs->fifo_count = 0; | |
607 | #ifdef SUN3_SCSI_VME | |
608 | dregs->fifo_count_hi = 0; | |
609 | dregs->dma_addr_hi = 0; | |
610 | dregs->dma_addr_lo = 0; | |
611 | dregs->dma_count_hi = 0; | |
612 | dregs->dma_count_lo = 0; | |
613 | ||
614 | dregs->ivect = VME_DATA24 | (instance->irq & 0xff); | |
615 | #endif | |
616 | ||
9c3f0e2b | 617 | NCR5380_maybe_reset_bus(instance); |
0d31f875 FT |
618 | |
619 | error = scsi_add_host(instance, NULL); | |
620 | if (error) | |
621 | goto fail_host; | |
622 | ||
623 | platform_set_drvdata(pdev, instance); | |
624 | ||
625 | scsi_scan_host(instance); | |
626 | return 0; | |
627 | ||
628 | fail_host: | |
e4dec680 | 629 | free_irq(instance->irq, instance); |
0d31f875 FT |
630 | fail_irq: |
631 | NCR5380_exit(instance); | |
0ad0eff9 | 632 | fail_init: |
0d31f875 FT |
633 | scsi_host_put(instance); |
634 | fail_alloc: | |
635 | if (udc_regs) | |
636 | dvma_free(udc_regs); | |
61e1ce58 | 637 | iounmap(ioaddr); |
0d31f875 FT |
638 | return error; |
639 | } | |
640 | ||
641 | static int __exit sun3_scsi_remove(struct platform_device *pdev) | |
642 | { | |
643 | struct Scsi_Host *instance = platform_get_drvdata(pdev); | |
61e1ce58 FT |
644 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
645 | void __iomem *ioaddr = hostdata->io; | |
0d31f875 FT |
646 | |
647 | scsi_remove_host(instance); | |
e4dec680 | 648 | free_irq(instance->irq, instance); |
0d31f875 FT |
649 | NCR5380_exit(instance); |
650 | scsi_host_put(instance); | |
651 | if (udc_regs) | |
652 | dvma_free(udc_regs); | |
61e1ce58 | 653 | iounmap(ioaddr); |
0d31f875 FT |
654 | return 0; |
655 | } | |
656 | ||
657 | static struct platform_driver sun3_scsi_driver = { | |
658 | .remove = __exit_p(sun3_scsi_remove), | |
659 | .driver = { | |
660 | .name = DRV_MODULE_NAME, | |
0d31f875 FT |
661 | }, |
662 | }; | |
1da177e4 | 663 | |
0d31f875 | 664 | module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe); |
1da177e4 | 665 | |
0d31f875 | 666 | MODULE_ALIAS("platform:" DRV_MODULE_NAME); |
1da177e4 | 667 | MODULE_LICENSE("GPL"); |