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scsi: always assign block layer tags if enabled
[linux-2.6-block.git] / drivers / scsi / stex.c
CommitLineData
5a25ba16
JG		 1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
bd5cd9cd 4 * Copyright (C) 2005-2009 Promise Technology Inc.
5a25ba16
JG		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
5a25ba16
JG		 14 */
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
5a0e3ad6 20#include <linux/slab.h>
5a25ba16
JG		 21#include <linux/time.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/byteorder.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_host.h>
cf355883 35#include <scsi/scsi_tcq.h>
c25da0af 36#include <scsi/scsi_dbg.h>
11002fbc 37#include <scsi/scsi_eh.h>
5a25ba16
JG		 38
39#define DRV_NAME "stex"
cce9c8ae 40#define ST_DRIVER_VERSION "4.6.0000.4"
05b4460b
EL		 41#define ST_VER_MAJOR 4
42#define ST_VER_MINOR 6
43#define ST_OEM 0
cce9c8ae 44#define ST_BUILD_VER 4
5a25ba16
JG		 45
46enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
69cb4875 59 YIOA_STATUS = 0x00,
0f3f6ee6
EL		 60 YH2I_INT = 0x20,
61 YINT_EN = 0x34,
62 YI2H_INT = 0x9c,
63 YI2H_INT_C = 0xa0,
64 YH2I_REQ = 0xc0,
65 YH2I_REQ_HI = 0xc4,
66
5a25ba16 67 /* MU register value */
9eb46d2a
EL		 68 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
69 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
70 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
71 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
72 MU_INBOUND_DOORBELL_RESET = (1 << 4),
73
74 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
75 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
76 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
77 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
78 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
79 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
5a25ba16
JG		 80
81 /* MU status code */
82 MU_STATE_STARTING = 1,
9eb46d2a
EL		 83 MU_STATE_STARTED = 2,
84 MU_STATE_RESETTING = 3,
85 MU_STATE_FAILED = 4,
5a25ba16 86
76fbf96f 87 MU_MAX_DELAY = 120,
5a25ba16 88 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
529e7a62 89 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
76fbf96f 90 MU_HARD_RESET_WAIT = 30000,
5a25ba16
JG		 91 HMU_PARTNER_TYPE = 2,
92
93 /* firmware returned values */
94 SRB_STATUS_SUCCESS = 0x01,
95 SRB_STATUS_ERROR = 0x04,
96 SRB_STATUS_BUSY = 0x05,
97 SRB_STATUS_INVALID_REQUEST = 0x06,
98 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
99 SRB_SEE_SENSE = 0x80,
100
101 /* task attribute */
102 TASK_ATTRIBUTE_SIMPLE = 0x0,
103 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
104 TASK_ATTRIBUTE_ORDERED = 0x2,
105 TASK_ATTRIBUTE_ACA = 0x4,
106
0f3f6ee6
EL		 107 SS_STS_NORMAL = 0x80000000,
108 SS_STS_DONE = 0x40000000,
109 SS_STS_HANDSHAKE = 0x20000000,
110
111 SS_HEAD_HANDSHAKE = 0x80,
112
69cb4875
EL		 113 SS_H2I_INT_RESET = 0x100,
114
9eb46d2a
EL		 115 SS_I2H_REQUEST_RESET = 0x2000,
116
69cb4875
EL		 117 SS_MU_OPERATIONAL = 0x80000000,
118
7cfe99a5 119 STEX_CDB_LENGTH = 16,
5a25ba16 120 STATUS_VAR_LEN = 128,
5a25ba16
JG		 121
122 /* sg flags */
123 SG_CF_EOT = 0x80, /* end of table */
124 SG_CF_64B = 0x40, /* 64 bit item */
125 SG_CF_HOST = 0x20, /* sg in host memory */
7cfe99a5
ELP		 126 MSG_DATA_DIR_ND = 0,
127 MSG_DATA_DIR_IN = 1,
128 MSG_DATA_DIR_OUT = 2,
5a25ba16 129
5a25ba16
JG		 130 st_shasta = 0,
131 st_vsc = 1,
591a3a5f
EL		 132 st_yosemite = 2,
133 st_seq = 3,
0f3f6ee6 134 st_yel = 4,
5a25ba16
JG		 135
136 PASSTHRU_REQ_TYPE = 0x00000001,
137 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
7cfe99a5 138 ST_INTERNAL_TIMEOUT = 180,
5a25ba16 139
fb4f66be
EL		 140 ST_TO_CMD = 0,
141 ST_FROM_CMD = 1,
142
5a25ba16 143 /* vendor specific commands of Promise */
fb4f66be
EL		 144 MGT_CMD = 0xd8,
145 SINBAND_MGT_CMD = 0xd9,
5a25ba16
JG		 146 ARRAY_CMD = 0xe0,
147 CONTROLLER_CMD = 0xe1,
148 DEBUGGING_CMD = 0xe2,
149 PASSTHRU_CMD = 0xe3,
150
151 PASSTHRU_GET_ADAPTER = 0x05,
152 PASSTHRU_GET_DRVVER = 0x10,
fb4f66be
EL		 153
154 CTLR_CONFIG_CMD = 0x03,
155 CTLR_SHUTDOWN = 0x0d,
156
5a25ba16
JG		 157 CTLR_POWER_STATE_CHANGE = 0x0e,
158 CTLR_POWER_SAVING = 0x01,
159
160 PASSTHRU_SIGNATURE = 0x4e415041,
fb4f66be 161 MGT_CMD_SIGNATURE = 0xba,
5a25ba16
JG		 162
163 INQUIRY_EVPD = 0x01,
94e9108b
EL		 164
165 ST_ADDITIONAL_MEM = 0x200000,
cbacfb5f 166 ST_ADDITIONAL_MEM_MIN = 0x80000,
5a25ba16
JG		 167};
168
169struct st_sgitem {
170 u8 ctrl; /* SG_CF_xxx */
171 u8 reserved[3];
172 __le32 count;
f1498161 173 __le64 addr;
5a25ba16
JG		 174};
175
0f3f6ee6
EL		 176struct st_ss_sgitem {
177 __le32 addr;
178 __le32 addr_hi;
179 __le32 count;
180};
181
5a25ba16
JG		 182struct st_sgtable {
183 __le16 sg_count;
184 __le16 max_sg_count;
185 __le32 sz_in_byte;
5a25ba16
JG		 186};
187
0f3f6ee6
EL		 188struct st_msg_header {
189 __le64 handle;
190 u8 flag;
191 u8 channel;
192 __le16 timeout;
193 u32 reserved;
194};
195
5a25ba16 196struct handshake_frame {
f1498161 197 __le64 rb_phy; /* request payload queue physical address */
5a25ba16
JG		 198 __le16 req_sz; /* size of each request payload */
199 __le16 req_cnt; /* count of reqs the buffer can hold */
200 __le16 status_sz; /* size of each status payload */
201 __le16 status_cnt; /* count of status the buffer can hold */
f1498161 202 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
5a25ba16
JG		 203 u8 partner_type; /* who sends this frame */
204 u8 reserved0[7];
205 __le32 partner_ver_major;
206 __le32 partner_ver_minor;
207 __le32 partner_ver_oem;
208 __le32 partner_ver_build;
94e9108b
EL		 209 __le32 extra_offset; /* NEW */
210 __le32 extra_size; /* NEW */
0f3f6ee6
EL		 211 __le32 scratch_size;
212 u32 reserved1;
5a25ba16
JG		 213};
214
215struct req_msg {
216 __le16 tag;
217 u8 lun;
218 u8 target;
219 u8 task_attr;
220 u8 task_manage;
7cfe99a5 221 u8 data_dir;
f903d7b7 222 u8 payload_sz; /* payload size in 4-byte, not used */
5a25ba16 223 u8 cdb[STEX_CDB_LENGTH];
591a3a5f 224 u32 variable[0];
5a25ba16
JG		 225};
226
227struct status_msg {
228 __le16 tag;
229 u8 lun;
230 u8 target;
231 u8 srb_status;
232 u8 scsi_status;
233 u8 reserved;
234 u8 payload_sz; /* payload size in 4-byte */
235 u8 variable[STATUS_VAR_LEN];
236};
237
238struct ver_info {
239 u32 major;
240 u32 minor;
241 u32 oem;
242 u32 build;
243 u32 reserved[2];
244};
245
246struct st_frame {
247 u32 base[6];
248 u32 rom_addr;
249
250 struct ver_info drv_ver;
251 struct ver_info bios_ver;
252
253 u32 bus;
254 u32 slot;
255 u32 irq_level;
256 u32 irq_vec;
257 u32 id;
258 u32 subid;
259
260 u32 dimm_size;
261 u8 dimm_type;
262 u8 reserved[3];
263
264 u32 channel;
265 u32 reserved1;
266};
267
268struct st_drvver {
269 u32 major;
270 u32 minor;
271 u32 oem;
272 u32 build;
273 u32 signature[2];
274 u8 console_id;
275 u8 host_no;
276 u8 reserved0[2];
277 u32 reserved[3];
278};
279
5a25ba16
JG		 280struct st_ccb {
281 struct req_msg *req;
282 struct scsi_cmnd *cmd;
283
284 void *sense_buffer;
285 unsigned int sense_bufflen;
286 int sg_count;
287
288 u32 req_type;
289 u8 srb_status;
290 u8 scsi_status;
f1498161 291 u8 reserved[2];
5a25ba16
JG		 292};
293
294struct st_hba {
295 void __iomem *mmio_base; /* iomapped PCI memory space */
296 void *dma_mem;
297 dma_addr_t dma_handle;
94e9108b 298 size_t dma_size;
5a25ba16
JG		 299
300 struct Scsi_Host *host;
301 struct pci_dev *pdev;
302
0f3f6ee6
EL		 303 struct req_msg * (*alloc_rq) (struct st_hba *);
304 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
305 void (*send) (struct st_hba *, struct req_msg *, u16);
306
5a25ba16
JG		 307 u32 req_head;
308 u32 req_tail;
309 u32 status_head;
310 u32 status_tail;
311
312 struct status_msg *status_buffer;
313 void *copy_buffer; /* temp buffer for driver-handled commands */
591a3a5f 314 struct st_ccb *ccb;
5a25ba16 315 struct st_ccb *wait_ccb;
0f3f6ee6 316 __le32 *scratch;
5a25ba16 317
9eb46d2a
EL		 318 char work_q_name[20];
319 struct workqueue_struct *work_q;
320 struct work_struct reset_work;
321 wait_queue_head_t reset_waitq;
5a25ba16 322 unsigned int mu_status;
5a25ba16 323 unsigned int cardtype;
99946f81
EL		 324 int msi_enabled;
325 int out_req_cnt;
591a3a5f
EL		 326 u32 extra_offset;
327 u16 rq_count;
328 u16 rq_size;
329 u16 sts_count;
330};
331
332struct st_card_info {
0f3f6ee6
EL		 333 struct req_msg * (*alloc_rq) (struct st_hba *);
334 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
335 void (*send) (struct st_hba *, struct req_msg *, u16);
591a3a5f
EL		 336 unsigned int max_id;
337 unsigned int max_lun;
338 unsigned int max_channel;
339 u16 rq_count;
340 u16 rq_size;
341 u16 sts_count;
5a25ba16
JG		 342};
343
99946f81
EL		 344static int msi;
345module_param(msi, int, 0);
346MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
347
5a25ba16
JG		 348static const char console_inq_page[] =
349{
350 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
351 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
352 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
353 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
354 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
355 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
356 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
357 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
358};
359
360MODULE_AUTHOR("Ed Lin");
361MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
362MODULE_LICENSE("GPL");
363MODULE_VERSION(ST_DRIVER_VERSION);
364
f1498161 365static void stex_gettime(__le64 *time)
5a25ba16
JG		 366{
367 struct timeval tv;
5a25ba16 368
7cfe99a5 369 do_gettimeofday(&tv);
f1498161 370 *time = cpu_to_le64(tv.tv_sec);
5a25ba16
JG		 371}
372
5a25ba16
JG		 373static struct status_msg *stex_get_status(struct st_hba *hba)
374{
f1498161 375 struct status_msg *status = hba->status_buffer + hba->status_tail;
5a25ba16
JG		 376
377 ++hba->status_tail;
591a3a5f 378 hba->status_tail %= hba->sts_count+1;
5a25ba16
JG		 379
380 return status;
381}
382
5a25ba16
JG		 383static void stex_invalid_field(struct scsi_cmnd *cmd,
384 void (*done)(struct scsi_cmnd *))
385{
11002fbc
FT		 386 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
387
7cfe99a5 388 /* "Invalid field in cdb" */
11002fbc
FT		 389 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
390 0x0);
5a25ba16
JG		 391 done(cmd);
392}
393
394static struct req_msg *stex_alloc_req(struct st_hba *hba)
395{
591a3a5f 396 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
5a25ba16
JG		 397
398 ++hba->req_head;
591a3a5f 399 hba->req_head %= hba->rq_count+1;
5a25ba16
JG		 400
401 return req;
402}
403
0f3f6ee6
EL		 404static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
405{
406 return (struct req_msg *)(hba->dma_mem +
407 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
408}
409
5a25ba16
JG		 410static int stex_map_sg(struct st_hba *hba,
411 struct req_msg *req, struct st_ccb *ccb)
412{
5a25ba16 413 struct scsi_cmnd *cmd;
d5587d5d 414 struct scatterlist *sg;
5a25ba16 415 struct st_sgtable *dst;
f1498161 416 struct st_sgitem *table;
d5587d5d 417 int i, nseg;
5a25ba16
JG		 418
419 cmd = ccb->cmd;
d5587d5d 420 nseg = scsi_dma_map(cmd);
f1498161 421 BUG_ON(nseg < 0);
d5587d5d 422 if (nseg) {
f1498161
EL		 423 dst = (struct st_sgtable *)req->variable;
424
d5587d5d
FT		 425 ccb->sg_count = nseg;
426 dst->sg_count = cpu_to_le16((u16)nseg);
f1498161
EL		 427 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
428 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
5a25ba16 429
f1498161 430 table = (struct st_sgitem *)(dst + 1);
d5587d5d 431 scsi_for_each_sg(cmd, sg, nseg, i) {
f1498161
EL		 432 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
433 table[i].addr = cpu_to_le64(sg_dma_address(sg));
434 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
5a25ba16 435 }
f1498161 436 table[--i].ctrl |= SG_CF_EOT;
5a25ba16
JG		 437 }
438
f1498161 439 return nseg;
5a25ba16
JG		 440}
441
0f3f6ee6
EL		 442static int stex_ss_map_sg(struct st_hba *hba,
443 struct req_msg *req, struct st_ccb *ccb)
444{
445 struct scsi_cmnd *cmd;
446 struct scatterlist *sg;
447 struct st_sgtable *dst;
448 struct st_ss_sgitem *table;
449 int i, nseg;
450
451 cmd = ccb->cmd;
452 nseg = scsi_dma_map(cmd);
453 BUG_ON(nseg < 0);
454 if (nseg) {
455 dst = (struct st_sgtable *)req->variable;
456
457 ccb->sg_count = nseg;
458 dst->sg_count = cpu_to_le16((u16)nseg);
459 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
460 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
461
462 table = (struct st_ss_sgitem *)(dst + 1);
463 scsi_for_each_sg(cmd, sg, nseg, i) {
464 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
465 table[i].addr =
466 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
467 table[i].addr_hi =
468 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
469 }
470 }
471
472 return nseg;
473}
474
5a25ba16
JG		 475static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
476{
477 struct st_frame *p;
478 size_t count = sizeof(struct st_frame);
479
480 p = hba->copy_buffer;
f1498161 481 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
5a25ba16
JG		 482 memset(p->base, 0, sizeof(u32)*6);
483 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
484 p->rom_addr = 0;
485
486 p->drv_ver.major = ST_VER_MAJOR;
487 p->drv_ver.minor = ST_VER_MINOR;
488 p->drv_ver.oem = ST_OEM;
489 p->drv_ver.build = ST_BUILD_VER;
490
491 p->bus = hba->pdev->bus->number;
492 p->slot = hba->pdev->devfn;
493 p->irq_level = 0;
494 p->irq_vec = hba->pdev->irq;
495 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
496 p->subid =
497 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
498
f1498161 499 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
5a25ba16
JG		 500}
501
502static void
503stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
504{
505 req->tag = cpu_to_le16(tag);
5a25ba16
JG		 506
507 hba->ccb[tag].req = req;
508 hba->out_req_cnt++;
509
510 writel(hba->req_head, hba->mmio_base + IMR0);
511 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
512 readl(hba->mmio_base + IDBL); /* flush */
513}
514
0f3f6ee6
EL		 515static void
516stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
517{
518 struct scsi_cmnd *cmd;
519 struct st_msg_header *msg_h;
520 dma_addr_t addr;
521
522 req->tag = cpu_to_le16(tag);
523
524 hba->ccb[tag].req = req;
525 hba->out_req_cnt++;
526
527 cmd = hba->ccb[tag].cmd;
528 msg_h = (struct st_msg_header *)req - 1;
529 if (likely(cmd)) {
530 msg_h->channel = (u8)cmd->device->channel;
531 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
532 }
533 addr = hba->dma_handle + hba->req_head * hba->rq_size;
534 addr += (hba->ccb[tag].sg_count+4)/11;
535 msg_h->handle = cpu_to_le64(addr);
536
537 ++hba->req_head;
538 hba->req_head %= hba->rq_count+1;
539
540 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
541 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
542 writel(addr, hba->mmio_base + YH2I_REQ);
543 readl(hba->mmio_base + YH2I_REQ); /* flush */
544}
545
cf355883
EL		 546static int
547stex_slave_alloc(struct scsi_device *sdev)
548{
549 /* Cheat: usually extracted from Inquiry data */
550 sdev->tagged_supported = 1;
551
2ecb204d 552 scsi_adjust_queue_depth(sdev, 0, sdev->host->can_queue);
cf355883
EL		 553
554 return 0;
555}
556
5a25ba16
JG		 557static int
558stex_slave_config(struct scsi_device *sdev)
559{
560 sdev->use_10_for_rw = 1;
561 sdev->use_10_for_ms = 1;
dc5c49bf 562 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
cf355883
EL		 563 sdev->tagged_supported = 1;
564
5a25ba16
JG		 565 return 0;
566}
567
5a25ba16 568static int
f281233d 569stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
5a25ba16
JG		 570{
571 struct st_hba *hba;
572 struct Scsi_Host *host;
f1498161 573 unsigned int id, lun;
5a25ba16
JG		 574 struct req_msg *req;
575 u16 tag;
7cfe99a5 576
5a25ba16
JG		 577 host = cmd->device->host;
578 id = cmd->device->id;
e0b2e597 579 lun = cmd->device->lun;
5a25ba16
JG		 580 hba = (struct st_hba *) &host->hostdata[0];
581
9eb46d2a
EL		 582 if (unlikely(hba->mu_status == MU_STATE_RESETTING))
583 return SCSI_MLQUEUE_HOST_BUSY;
584
5a25ba16
JG		 585 switch (cmd->cmnd[0]) {
586 case MODE_SENSE_10:
587 {
588 static char ms10_caching_page[12] =
589 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
590 unsigned char page;
7cfe99a5 591
5a25ba16
JG		 592 page = cmd->cmnd[2] & 0x3f;
593 if (page == 0x8 || page == 0x3f) {
31fe47d4
FT		 594 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
595 sizeof(ms10_caching_page));
5a25ba16
JG		 596 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
597 done(cmd);
598 } else
599 stex_invalid_field(cmd, done);
600 return 0;
601 }
e0b2e597
EL		 602 case REPORT_LUNS:
603 /*
604 * The shasta firmware does not report actual luns in the
605 * target, so fail the command to force sequential lun scan.
606 * Also, the console device does not support this command.
607 */
608 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
609 stex_invalid_field(cmd, done);
610 return 0;
611 }
612 break;
d116a7bc
EL		 613 case TEST_UNIT_READY:
614 if (id == host->max_id - 1) {
615 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
616 done(cmd);
617 return 0;
618 }
619 break;
5a25ba16 620 case INQUIRY:
91e6ecad
EL		 621 if (lun >= host->max_lun) {
622 cmd->result = DID_NO_CONNECT << 16;
623 done(cmd);
624 return 0;
625 }
e0b2e597 626 if (id != host->max_id - 1)
5a25ba16 627 break;
0f3f6ee6
EL		 628 if (!lun && !cmd->device->channel &&
629 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
31fe47d4
FT		 630 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
631 sizeof(console_inq_page));
5a25ba16
JG		 632 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
633 done(cmd);
634 } else
635 stex_invalid_field(cmd, done);
636 return 0;
637 case PASSTHRU_CMD:
638 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
639 struct st_drvver ver;
26106e3c 640 size_t cp_len = sizeof(ver);
7cfe99a5 641
5a25ba16
JG		 642 ver.major = ST_VER_MAJOR;
643 ver.minor = ST_VER_MINOR;
644 ver.oem = ST_OEM;
645 ver.build = ST_BUILD_VER;
646 ver.signature[0] = PASSTHRU_SIGNATURE;
e0b2e597 647 ver.console_id = host->max_id - 1;
5a25ba16 648 ver.host_no = hba->host->host_no;
31fe47d4 649 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
26106e3c 650 cmd->result = sizeof(ver) == cp_len ?
5a25ba16
JG		 651 DID_OK << 16 | COMMAND_COMPLETE << 8 :
652 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
653 done(cmd);
654 return 0;
655 }
656 default:
657 break;
658 }
659
660 cmd->scsi_done = done;
661
cf355883
EL		 662 tag = cmd->request->tag;
663
664 if (unlikely(tag >= host->can_queue))
5a25ba16
JG		 665 return SCSI_MLQUEUE_HOST_BUSY;
666
0f3f6ee6 667 req = hba->alloc_rq(hba);
fb4f66be 668
e0b2e597
EL		 669 req->lun = lun;
670 req->target = id;
5a25ba16
JG		 671
672 /* cdb */
673 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
674
7cfe99a5
ELP		 675 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
676 req->data_dir = MSG_DATA_DIR_IN;
677 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
678 req->data_dir = MSG_DATA_DIR_OUT;
679 else
680 req->data_dir = MSG_DATA_DIR_ND;
681
5a25ba16
JG		 682 hba->ccb[tag].cmd = cmd;
683 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
684 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
5a25ba16 685
0f3f6ee6
EL		 686 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
687 hba->ccb[tag].sg_count = 0;
688 memset(&req->variable[0], 0, 8);
689 }
5a25ba16 690
0f3f6ee6 691 hba->send(hba, req, tag);
5a25ba16
JG		 692 return 0;
693}
694
f281233d
JG		 695static DEF_SCSI_QCMD(stex_queuecommand)
696
5a25ba16
JG		 697static void stex_scsi_done(struct st_ccb *ccb)
698{
699 struct scsi_cmnd *cmd = ccb->cmd;
700 int result;
701
f1498161 702 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
5a25ba16
JG		 703 result = ccb->scsi_status;
704 switch (ccb->scsi_status) {
705 case SAM_STAT_GOOD:
706 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
707 break;
708 case SAM_STAT_CHECK_CONDITION:
709 result |= DRIVER_SENSE << 24;
710 break;
711 case SAM_STAT_BUSY:
712 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
713 break;
714 default:
715 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
716 break;
717 }
718 }
719 else if (ccb->srb_status & SRB_SEE_SENSE)
720 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
721 else switch (ccb->srb_status) {
722 case SRB_STATUS_SELECTION_TIMEOUT:
723 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
724 break;
725 case SRB_STATUS_BUSY:
726 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
727 break;
728 case SRB_STATUS_INVALID_REQUEST:
729 case SRB_STATUS_ERROR:
730 default:
731 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
732 break;
733 }
734
735 cmd->result = result;
736 cmd->scsi_done(cmd);
737}
738
739static void stex_copy_data(struct st_ccb *ccb,
740 struct status_msg *resp, unsigned int variable)
741{
5a25ba16
JG		 742 if (resp->scsi_status != SAM_STAT_GOOD) {
743 if (ccb->sense_buffer != NULL)
744 memcpy(ccb->sense_buffer, resp->variable,
745 min(variable, ccb->sense_bufflen));
746 return;
747 }
748
749 if (ccb->cmd == NULL)
750 return;
f1498161 751 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
fb4f66be
EL		 752}
753
f1498161 754static void stex_check_cmd(struct st_hba *hba,
fb4f66be
EL		 755 struct st_ccb *ccb, struct status_msg *resp)
756{
fb4f66be 757 if (ccb->cmd->cmnd[0] == MGT_CMD &&
f1498161 758 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
968a5763
EL		 759 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
760 le32_to_cpu(*(__le32 *)&resp->variable[0]));
5a25ba16
JG		 761}
762
763static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
764{
765 void __iomem *base = hba->mmio_base;
766 struct status_msg *resp;
767 struct st_ccb *ccb;
768 unsigned int size;
769 u16 tag;
770
f1498161 771 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
5a25ba16
JG		 772 return;
773
774 /* status payloads */
775 hba->status_head = readl(base + OMR1);
591a3a5f 776 if (unlikely(hba->status_head > hba->sts_count)) {
5a25ba16
JG		 777 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
778 pci_name(hba->pdev));
779 return;
780 }
781
fb4f66be
EL		 782 /*
783 * it's not a valid status payload if:
784 * 1. there are no pending requests(e.g. during init stage)
785 * 2. there are some pending requests, but the controller is in
786 * reset status, and its type is not st_yosemite
787 * firmware of st_yosemite in reset status will return pending requests
788 * to driver, so we allow it to pass
789 */
790 if (unlikely(hba->out_req_cnt <= 0 ||
791 (hba->mu_status == MU_STATE_RESETTING &&
792 hba->cardtype != st_yosemite))) {
5a25ba16
JG		 793 hba->status_tail = hba->status_head;
794 goto update_status;
795 }
796
797 while (hba->status_tail != hba->status_head) {
798 resp = stex_get_status(hba);
799 tag = le16_to_cpu(resp->tag);
cf355883 800 if (unlikely(tag >= hba->host->can_queue)) {
5a25ba16
JG		 801 printk(KERN_WARNING DRV_NAME
802 "(%s): invalid tag\n", pci_name(hba->pdev));
803 continue;
804 }
5a25ba16 805
f1498161 806 hba->out_req_cnt--;
5a25ba16 807 ccb = &hba->ccb[tag];
f1498161 808 if (unlikely(hba->wait_ccb == ccb))
5a25ba16
JG		 809 hba->wait_ccb = NULL;
810 if (unlikely(ccb->req == NULL)) {
811 printk(KERN_WARNING DRV_NAME
812 "(%s): lagging req\n", pci_name(hba->pdev));
5a25ba16
JG		 813 continue;
814 }
815
816 size = resp->payload_sz * sizeof(u32); /* payload size */
817 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
818 size > sizeof(*resp))) {
819 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
820 pci_name(hba->pdev));
821 } else {
822 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
823 if (size)
824 stex_copy_data(ccb, resp, size);
825 }
826
dd48ebf7 827 ccb->req = NULL;
5a25ba16
JG		 828 ccb->srb_status = resp->srb_status;
829 ccb->scsi_status = resp->scsi_status;
830
cf355883 831 if (likely(ccb->cmd != NULL)) {
fb4f66be 832 if (hba->cardtype == st_yosemite)
f1498161 833 stex_check_cmd(hba, ccb, resp);
fb4f66be 834
cf355883
EL		 835 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
836 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
837 stex_controller_info(hba, ccb);
fb4f66be 838
d5587d5d 839 scsi_dma_unmap(ccb->cmd);
cf355883 840 stex_scsi_done(ccb);
f1498161 841 } else
5a25ba16 842 ccb->req_type = 0;
5a25ba16
JG		 843 }
844
845update_status:
846 writel(hba->status_head, base + IMR1);
847 readl(base + IMR1); /* flush */
848}
849
7d12e780 850static irqreturn_t stex_intr(int irq, void *__hba)
5a25ba16
JG		 851{
852 struct st_hba *hba = __hba;
853 void __iomem *base = hba->mmio_base;
854 u32 data;
855 unsigned long flags;
5a25ba16
JG		 856
857 spin_lock_irqsave(hba->host->host_lock, flags);
858
859 data = readl(base + ODBL);
860
861 if (data && data != 0xffffffff) {
862 /* clear the interrupt */
863 writel(data, base + ODBL);
864 readl(base + ODBL); /* flush */
865 stex_mu_intr(hba, data);
9eb46d2a
EL		 866 spin_unlock_irqrestore(hba->host->host_lock, flags);
867 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
868 hba->cardtype == st_shasta))
869 queue_work(hba->work_q, &hba->reset_work);
870 return IRQ_HANDLED;
5a25ba16
JG		 871 }
872
873 spin_unlock_irqrestore(hba->host->host_lock, flags);
874
9eb46d2a 875 return IRQ_NONE;
5a25ba16
JG		 876}
877
0f3f6ee6
EL		 878static void stex_ss_mu_intr(struct st_hba *hba)
879{
880 struct status_msg *resp;
881 struct st_ccb *ccb;
882 __le32 *scratch;
883 unsigned int size;
884 int count = 0;
885 u32 value;
886 u16 tag;
887
888 if (unlikely(hba->out_req_cnt <= 0 ||
889 hba->mu_status == MU_STATE_RESETTING))
890 return;
891
892 while (count < hba->sts_count) {
893 scratch = hba->scratch + hba->status_tail;
894 value = le32_to_cpu(*scratch);
895 if (unlikely(!(value & SS_STS_NORMAL)))
896 return;
897
898 resp = hba->status_buffer + hba->status_tail;
899 *scratch = 0;
900 ++count;
901 ++hba->status_tail;
902 hba->status_tail %= hba->sts_count+1;
903
904 tag = (u16)value;
905 if (unlikely(tag >= hba->host->can_queue)) {
906 printk(KERN_WARNING DRV_NAME
69cb4875 907 "(%s): invalid tag\n", pci_name(hba->pdev));
0f3f6ee6
EL		 908 continue;
909 }
910
911 hba->out_req_cnt--;
912 ccb = &hba->ccb[tag];
913 if (unlikely(hba->wait_ccb == ccb))
914 hba->wait_ccb = NULL;
915 if (unlikely(ccb->req == NULL)) {
916 printk(KERN_WARNING DRV_NAME
917 "(%s): lagging req\n", pci_name(hba->pdev));
918 continue;
919 }
920
921 ccb->req = NULL;
922 if (likely(value & SS_STS_DONE)) { /* normal case */
923 ccb->srb_status = SRB_STATUS_SUCCESS;
924 ccb->scsi_status = SAM_STAT_GOOD;
925 } else {
926 ccb->srb_status = resp->srb_status;
927 ccb->scsi_status = resp->scsi_status;
928 size = resp->payload_sz * sizeof(u32);
929 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
930 size > sizeof(*resp))) {
931 printk(KERN_WARNING DRV_NAME
932 "(%s): bad status size\n",
933 pci_name(hba->pdev));
934 } else {
935 size -= sizeof(*resp) - STATUS_VAR_LEN;
936 if (size)
937 stex_copy_data(ccb, resp, size);
938 }
939 if (likely(ccb->cmd != NULL))
940 stex_check_cmd(hba, ccb, resp);
941 }
942
943 if (likely(ccb->cmd != NULL)) {
944 scsi_dma_unmap(ccb->cmd);
945 stex_scsi_done(ccb);
946 } else
947 ccb->req_type = 0;
948 }
949}
950
951static irqreturn_t stex_ss_intr(int irq, void *__hba)
952{
953 struct st_hba *hba = __hba;
954 void __iomem *base = hba->mmio_base;
955 u32 data;
956 unsigned long flags;
0f3f6ee6
EL		 957
958 spin_lock_irqsave(hba->host->host_lock, flags);
959
960 data = readl(base + YI2H_INT);
961 if (data && data != 0xffffffff) {
962 /* clear the interrupt */
963 writel(data, base + YI2H_INT_C);
964 stex_ss_mu_intr(hba);
9eb46d2a
EL		 965 spin_unlock_irqrestore(hba->host->host_lock, flags);
966 if (unlikely(data & SS_I2H_REQUEST_RESET))
967 queue_work(hba->work_q, &hba->reset_work);
968 return IRQ_HANDLED;
0f3f6ee6
EL		 969 }
970
971 spin_unlock_irqrestore(hba->host->host_lock, flags);
972
9eb46d2a 973 return IRQ_NONE;
0f3f6ee6
EL		 974}
975
976static int stex_common_handshake(struct st_hba *hba)
5a25ba16
JG		 977{
978 void __iomem *base = hba->mmio_base;
979 struct handshake_frame *h;
980 dma_addr_t status_phys;
529e7a62 981 u32 data;
76fbf96f 982 unsigned long before;
5a25ba16
JG		 983
984 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
985 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
986 readl(base + IDBL);
76fbf96f
EL		 987 before = jiffies;
988 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
989 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
990 printk(KERN_ERR DRV_NAME
991 "(%s): no handshake signature\n",
992 pci_name(hba->pdev));
993 return -1;
994 }
5a25ba16
JG		 995 rmb();
996 msleep(1);
997 }
5a25ba16
JG		 998 }
999
1000 udelay(10);
1001
529e7a62
EL		 1002 data = readl(base + OMR1);
1003 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1004 data &= 0x0000ffff;
f1498161 1005 if (hba->host->can_queue > data) {
529e7a62 1006 hba->host->can_queue = data;
f1498161
EL		 1007 hba->host->cmd_per_lun = data;
1008 }
529e7a62
EL		 1009 }
1010
f1498161
EL		 1011 h = (struct handshake_frame *)hba->status_buffer;
1012 h->rb_phy = cpu_to_le64(hba->dma_handle);
591a3a5f
EL		 1013 h->req_sz = cpu_to_le16(hba->rq_size);
1014 h->req_cnt = cpu_to_le16(hba->rq_count+1);
5a25ba16 1015 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
591a3a5f 1016 h->status_cnt = cpu_to_le16(hba->sts_count+1);
5a25ba16
JG		 1017 stex_gettime(&h->hosttime);
1018 h->partner_type = HMU_PARTNER_TYPE;
591a3a5f
EL		 1019 if (hba->extra_offset) {
1020 h->extra_offset = cpu_to_le32(hba->extra_offset);
cbacfb5f 1021 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
94e9108b
EL		 1022 } else
1023 h->extra_offset = h->extra_size = 0;
5a25ba16 1024
591a3a5f 1025 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
5a25ba16
JG		 1026 writel(status_phys, base + IMR0);
1027 readl(base + IMR0);
1028 writel((status_phys >> 16) >> 16, base + IMR1);
1029 readl(base + IMR1);
1030
1031 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1032 readl(base + OMR0);
1033 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1034 readl(base + IDBL); /* flush */
1035
1036 udelay(10);
76fbf96f
EL		 1037 before = jiffies;
1038 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1039 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1040 printk(KERN_ERR DRV_NAME
1041 "(%s): no signature after handshake frame\n",
1042 pci_name(hba->pdev));
1043 return -1;
1044 }
5a25ba16
JG		 1045 rmb();
1046 msleep(1);
1047 }
1048
5a25ba16
JG		 1049 writel(0, base + IMR0);
1050 readl(base + IMR0);
1051 writel(0, base + OMR0);
1052 readl(base + OMR0);
1053 writel(0, base + IMR1);
1054 readl(base + IMR1);
1055 writel(0, base + OMR1);
1056 readl(base + OMR1); /* flush */
5a25ba16
JG		 1057 return 0;
1058}
1059
0f3f6ee6
EL		 1060static int stex_ss_handshake(struct st_hba *hba)
1061{
1062 void __iomem *base = hba->mmio_base;
1063 struct st_msg_header *msg_h;
1064 struct handshake_frame *h;
69cb4875 1065 __le32 *scratch;
9eb46d2a 1066 u32 data, scratch_size;
0f3f6ee6
EL		 1067 unsigned long before;
1068 int ret = 0;
1069
69cb4875
EL		 1070 before = jiffies;
1071 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1072 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1073 printk(KERN_ERR DRV_NAME
1074 "(%s): firmware not operational\n",
1075 pci_name(hba->pdev));
1076 return -1;
1077 }
1078 msleep(1);
1079 }
1080
1081 msg_h = (struct st_msg_header *)hba->dma_mem;
0f3f6ee6
EL		 1082 msg_h->handle = cpu_to_le64(hba->dma_handle);
1083 msg_h->flag = SS_HEAD_HANDSHAKE;
1084
69cb4875 1085 h = (struct handshake_frame *)(msg_h + 1);
0f3f6ee6
EL		 1086 h->rb_phy = cpu_to_le64(hba->dma_handle);
1087 h->req_sz = cpu_to_le16(hba->rq_size);
1088 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1089 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1090 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1091 stex_gettime(&h->hosttime);
1092 h->partner_type = HMU_PARTNER_TYPE;
1093 h->extra_offset = h->extra_size = 0;
9eb46d2a
EL		 1094 scratch_size = (hba->sts_count+1)*sizeof(u32);
1095 h->scratch_size = cpu_to_le32(scratch_size);
0f3f6ee6
EL		 1096
1097 data = readl(base + YINT_EN);
1098 data &= ~4;
1099 writel(data, base + YINT_EN);
1100 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
9eb46d2a 1101 readl(base + YH2I_REQ_HI);
0f3f6ee6 1102 writel(hba->dma_handle, base + YH2I_REQ);
9eb46d2a 1103 readl(base + YH2I_REQ); /* flush */
0f3f6ee6
EL		 1104
1105 scratch = hba->scratch;
1106 before = jiffies;
1107 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1108 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1109 printk(KERN_ERR DRV_NAME
1110 "(%s): no signature after handshake frame\n",
1111 pci_name(hba->pdev));
1112 ret = -1;
1113 break;
1114 }
1115 rmb();
1116 msleep(1);
1117 }
1118
9eb46d2a 1119 memset(scratch, 0, scratch_size);
0f3f6ee6
EL		 1120 msg_h->flag = 0;
1121 return ret;
1122}
1123
1124static int stex_handshake(struct st_hba *hba)
1125{
1126 int err;
1127 unsigned long flags;
9eb46d2a 1128 unsigned int mu_status;
0f3f6ee6
EL		 1129
1130 err = (hba->cardtype == st_yel) ?
1131 stex_ss_handshake(hba) : stex_common_handshake(hba);
9eb46d2a
EL		 1132 spin_lock_irqsave(hba->host->host_lock, flags);
1133 mu_status = hba->mu_status;
0f3f6ee6 1134 if (err == 0) {
0f3f6ee6
EL		 1135 hba->req_head = 0;
1136 hba->req_tail = 0;
1137 hba->status_head = 0;
1138 hba->status_tail = 0;
1139 hba->out_req_cnt = 0;
1140 hba->mu_status = MU_STATE_STARTED;
9eb46d2a
EL		 1141 } else
1142 hba->mu_status = MU_STATE_FAILED;
1143 if (mu_status == MU_STATE_RESETTING)
1144 wake_up_all(&hba->reset_waitq);
1145 spin_unlock_irqrestore(hba->host->host_lock, flags);
0f3f6ee6
EL		 1146 return err;
1147}
1148
5a25ba16
JG		 1149static int stex_abort(struct scsi_cmnd *cmd)
1150{
1151 struct Scsi_Host *host = cmd->device->host;
1152 struct st_hba *hba = (struct st_hba *)host->hostdata;
cf355883 1153 u16 tag = cmd->request->tag;
5a25ba16
JG		 1154 void __iomem *base;
1155 u32 data;
1156 int result = SUCCESS;
1157 unsigned long flags;
c25da0af 1158
1fa6b5fb 1159 scmd_printk(KERN_INFO, cmd, "aborting command\n");
c25da0af 1160
5a25ba16
JG		 1161 base = hba->mmio_base;
1162 spin_lock_irqsave(host->host_lock, flags);
9eb46d2a
EL		 1163 if (tag < host->can_queue &&
1164 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
cf355883 1165 hba->wait_ccb = &hba->ccb[tag];
9eb46d2a
EL		 1166 else
1167 goto out;
5a25ba16 1168
0f3f6ee6
EL		 1169 if (hba->cardtype == st_yel) {
1170 data = readl(base + YI2H_INT);
1171 if (data == 0 || data == 0xffffffff)
1172 goto fail_out;
5a25ba16 1173
0f3f6ee6
EL		 1174 writel(data, base + YI2H_INT_C);
1175 stex_ss_mu_intr(hba);
1176 } else {
1177 data = readl(base + ODBL);
1178 if (data == 0 || data == 0xffffffff)
1179 goto fail_out;
5a25ba16 1180
0f3f6ee6
EL		 1181 writel(data, base + ODBL);
1182 readl(base + ODBL); /* flush */
5a25ba16 1183
0f3f6ee6
EL		 1184 stex_mu_intr(hba, data);
1185 }
5a25ba16
JG		 1186 if (hba->wait_ccb == NULL) {
1187 printk(KERN_WARNING DRV_NAME
1188 "(%s): lost interrupt\n", pci_name(hba->pdev));
1189 goto out;
1190 }
1191
1192fail_out:
d5587d5d 1193 scsi_dma_unmap(cmd);
5a25ba16
JG		 1194 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1195 hba->wait_ccb = NULL;
1196 result = FAILED;
1197out:
1198 spin_unlock_irqrestore(host->host_lock, flags);
1199 return result;
1200}
1201
1202static void stex_hard_reset(struct st_hba *hba)
1203{
1204 struct pci_bus *bus;
1205 int i;
1206 u16 pci_cmd;
1207 u8 pci_bctl;
1208
1209 for (i = 0; i < 16; i++)
1210 pci_read_config_dword(hba->pdev, i * 4,
1211 &hba->pdev->saved_config_space[i]);
1212
1213 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1214 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1215 bus = hba->pdev->bus;
1216 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1217 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1218 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
69f4a513
EL		 1219
1220 /*
1221 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1222 * require more time to finish bus reset. Use 100 ms here for safety
1223 */
1224 msleep(100);
5a25ba16
JG		 1225 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1226 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1227
76fbf96f 1228 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
5a25ba16 1229 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
47c4f997 1230 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
5a25ba16
JG		 1231 break;
1232 msleep(1);
1233 }
1234
1235 ssleep(5);
1236 for (i = 0; i < 16; i++)
1237 pci_write_config_dword(hba->pdev, i * 4,
1238 hba->pdev->saved_config_space[i]);
1239}
1240
9eb46d2a
EL		 1241static int stex_yos_reset(struct st_hba *hba)
1242{
1243 void __iomem *base;
1244 unsigned long flags, before;
1245 int ret = 0;
1246
1247 base = hba->mmio_base;
1248 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1249 readl(base + IDBL); /* flush */
1250 before = jiffies;
1251 while (hba->out_req_cnt > 0) {
1252 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1253 printk(KERN_WARNING DRV_NAME
1254 "(%s): reset timeout\n", pci_name(hba->pdev));
1255 ret = -1;
1256 break;
1257 }
1258 msleep(1);
1259 }
1260
1261 spin_lock_irqsave(hba->host->host_lock, flags);
1262 if (ret == -1)
1263 hba->mu_status = MU_STATE_FAILED;
1264 else
1265 hba->mu_status = MU_STATE_STARTED;
1266 wake_up_all(&hba->reset_waitq);
1267 spin_unlock_irqrestore(hba->host->host_lock, flags);
1268
1269 return ret;
1270}
1271
69cb4875
EL		 1272static void stex_ss_reset(struct st_hba *hba)
1273{
1274 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1275 readl(hba->mmio_base + YH2I_INT);
1276 ssleep(5);
1277}
1278
9eb46d2a 1279static int stex_do_reset(struct st_hba *hba)
5a25ba16 1280{
9eb46d2a
EL		 1281 struct st_ccb *ccb;
1282 unsigned long flags;
1283 unsigned int mu_status = MU_STATE_RESETTING;
1284 u16 tag;
7cfe99a5 1285
9eb46d2a
EL		 1286 spin_lock_irqsave(hba->host->host_lock, flags);
1287 if (hba->mu_status == MU_STATE_STARTING) {
1288 spin_unlock_irqrestore(hba->host->host_lock, flags);
1289 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1290 pci_name(hba->pdev));
1291 return 0;
1292 }
1293 while (hba->mu_status == MU_STATE_RESETTING) {
1294 spin_unlock_irqrestore(hba->host->host_lock, flags);
1295 wait_event_timeout(hba->reset_waitq,
1296 hba->mu_status != MU_STATE_RESETTING,
1297 MU_MAX_DELAY * HZ);
1298 spin_lock_irqsave(hba->host->host_lock, flags);
1299 mu_status = hba->mu_status;
1300 }
5a25ba16 1301
9eb46d2a
EL		 1302 if (mu_status != MU_STATE_RESETTING) {
1303 spin_unlock_irqrestore(hba->host->host_lock, flags);
1304 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1305 }
c25da0af 1306
5a25ba16 1307 hba->mu_status = MU_STATE_RESETTING;
9eb46d2a
EL		 1308 spin_unlock_irqrestore(hba->host->host_lock, flags);
1309
1310 if (hba->cardtype == st_yosemite)
1311 return stex_yos_reset(hba);
5a25ba16
JG		 1312
1313 if (hba->cardtype == st_shasta)
1314 stex_hard_reset(hba);
69cb4875
EL		 1315 else if (hba->cardtype == st_yel)
1316 stex_ss_reset(hba);
5a25ba16 1317
9eb46d2a
EL		 1318 spin_lock_irqsave(hba->host->host_lock, flags);
1319 for (tag = 0; tag < hba->host->can_queue; tag++) {
1320 ccb = &hba->ccb[tag];
1321 if (ccb->req == NULL)
1322 continue;
1323 ccb->req = NULL;
1324 if (ccb->cmd) {
1325 scsi_dma_unmap(ccb->cmd);
1326 ccb->cmd->result = DID_RESET << 16;
1327 ccb->cmd->scsi_done(ccb->cmd);
1328 ccb->cmd = NULL;
fb4f66be 1329 }
5a25ba16 1330 }
9eb46d2a 1331 spin_unlock_irqrestore(hba->host->host_lock, flags);
5a25ba16 1332
9eb46d2a
EL		 1333 if (stex_handshake(hba) == 0)
1334 return 0;
fb4f66be 1335
9eb46d2a
EL		 1336 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1337 pci_name(hba->pdev));
1338 return -1;
1339}
1340
1341static int stex_reset(struct scsi_cmnd *cmd)
1342{
1343 struct st_hba *hba;
1344
1345 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1346
1fa6b5fb
HR		 1347 shost_printk(KERN_INFO, cmd->device->host,
1348 "resetting host\n");
9eb46d2a
EL		 1349
1350 return stex_do_reset(hba) ? FAILED : SUCCESS;
1351}
1352
1353static void stex_reset_work(struct work_struct *work)
1354{
1355 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1356
1357 stex_do_reset(hba);
5a25ba16
JG		 1358}
1359
1360static int stex_biosparam(struct scsi_device *sdev,
1361 struct block_device *bdev, sector_t capacity, int geom[])
1362{
b4b8bed1 1363 int heads = 255, sectors = 63;
5a25ba16
JG		 1364
1365 if (capacity < 0x200000) {
1366 heads = 64;
1367 sectors = 32;
1368 }
1369
b4b8bed1 1370 sector_div(capacity, heads * sectors);
5a25ba16
JG		 1371
1372 geom[0] = heads;
1373 geom[1] = sectors;
b4b8bed1 1374 geom[2] = capacity;
5a25ba16
JG		 1375
1376 return 0;
1377}
1378
1379static struct scsi_host_template driver_template = {
1380 .module = THIS_MODULE,
1381 .name = DRV_NAME,
1382 .proc_name = DRV_NAME,
1383 .bios_param = stex_biosparam,
1384 .queuecommand = stex_queuecommand,
cf355883 1385 .slave_alloc = stex_slave_alloc,
5a25ba16 1386 .slave_configure = stex_slave_config,
5a25ba16
JG		 1387 .eh_abort_handler = stex_abort,
1388 .eh_host_reset_handler = stex_reset,
5a25ba16 1389 .this_id = -1,
2ecb204d 1390 .use_blk_tags = 1,
591a3a5f
EL		 1391};
1392
1393static struct pci_device_id stex_pci_tbl[] = {
1394 /* st_shasta */
1395 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1396 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1397 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1398 st_shasta }, /* SuperTrak EX12350 */
1399 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1400 st_shasta }, /* SuperTrak EX4350 */
1401 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1402 st_shasta }, /* SuperTrak EX24350 */
1403
1404 /* st_vsc */
1405 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1406
1407 /* st_yosemite */
0f3f6ee6 1408 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
591a3a5f
EL		 1409
1410 /* st_seq */
1411 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
0f3f6ee6
EL		 1412
1413 /* st_yel */
1414 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1415 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
591a3a5f
EL		 1416 { } /* terminate list */
1417};
1418
1419static struct st_card_info stex_card_info[] = {
1420 /* st_shasta */
1421 {
1422 .max_id = 17,
1423 .max_lun = 8,
1424 .max_channel = 0,
1425 .rq_count = 32,
1426 .rq_size = 1048,
1427 .sts_count = 32,
0f3f6ee6
EL		 1428 .alloc_rq = stex_alloc_req,
1429 .map_sg = stex_map_sg,
1430 .send = stex_send_cmd,
591a3a5f
EL		 1431 },
1432
1433 /* st_vsc */
1434 {
1435 .max_id = 129,
1436 .max_lun = 1,
1437 .max_channel = 0,
1438 .rq_count = 32,
1439 .rq_size = 1048,
1440 .sts_count = 32,
0f3f6ee6
EL		 1441 .alloc_rq = stex_alloc_req,
1442 .map_sg = stex_map_sg,
1443 .send = stex_send_cmd,
591a3a5f
EL		 1444 },
1445
1446 /* st_yosemite */
1447 {
1448 .max_id = 2,
1449 .max_lun = 256,
1450 .max_channel = 0,
1451 .rq_count = 256,
1452 .rq_size = 1048,
1453 .sts_count = 256,
0f3f6ee6
EL		 1454 .alloc_rq = stex_alloc_req,
1455 .map_sg = stex_map_sg,
1456 .send = stex_send_cmd,
591a3a5f
EL		 1457 },
1458
1459 /* st_seq */
1460 {
1461 .max_id = 129,
1462 .max_lun = 1,
1463 .max_channel = 0,
1464 .rq_count = 32,
1465 .rq_size = 1048,
1466 .sts_count = 32,
0f3f6ee6
EL		 1467 .alloc_rq = stex_alloc_req,
1468 .map_sg = stex_map_sg,
1469 .send = stex_send_cmd,
1470 },
1471
1472 /* st_yel */
1473 {
1474 .max_id = 129,
1475 .max_lun = 256,
1476 .max_channel = 3,
1477 .rq_count = 801,
1478 .rq_size = 512,
1479 .sts_count = 801,
1480 .alloc_rq = stex_ss_alloc_req,
1481 .map_sg = stex_ss_map_sg,
1482 .send = stex_ss_send_cmd,
591a3a5f 1483 },
5a25ba16
JG		 1484};
1485
1486static int stex_set_dma_mask(struct pci_dev * pdev)
1487{
1488 int ret;
7cfe99a5 1489
cce9c8ae
EL		 1490 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1491 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
5a25ba16 1492 return 0;
284901a9 1493 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16 1494 if (!ret)
284901a9 1495 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16
JG		 1496 return ret;
1497}
1498
99946f81
EL		 1499static int stex_request_irq(struct st_hba *hba)
1500{
1501 struct pci_dev *pdev = hba->pdev;
1502 int status;
1503
1504 if (msi) {
1505 status = pci_enable_msi(pdev);
1506 if (status != 0)
1507 printk(KERN_ERR DRV_NAME
1508 "(%s): error %d setting up MSI\n",
1509 pci_name(pdev), status);
1510 else
1511 hba->msi_enabled = 1;
1512 } else
1513 hba->msi_enabled = 0;
1514
0f3f6ee6
EL		 1515 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1516 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
99946f81
EL		 1517
1518 if (status != 0) {
1519 if (hba->msi_enabled)
1520 pci_disable_msi(pdev);
1521 }
1522 return status;
1523}
1524
1525static void stex_free_irq(struct st_hba *hba)
1526{
1527 struct pci_dev *pdev = hba->pdev;
1528
1529 free_irq(pdev->irq, hba);
1530 if (hba->msi_enabled)
1531 pci_disable_msi(pdev);
1532}
1533
6f039790 1534static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
5a25ba16
JG		 1535{
1536 struct st_hba *hba;
1537 struct Scsi_Host *host;
591a3a5f 1538 const struct st_card_info *ci = NULL;
0f3f6ee6 1539 u32 sts_offset, cp_offset, scratch_offset;
5a25ba16
JG		 1540 int err;
1541
1542 err = pci_enable_device(pdev);
1543 if (err)
1544 return err;
1545
1546 pci_set_master(pdev);
1547
1548 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1549
1550 if (!host) {
1551 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1552 pci_name(pdev));
1553 err = -ENOMEM;
1554 goto out_disable;
1555 }
1556
1557 hba = (struct st_hba *)host->hostdata;
1558 memset(hba, 0, sizeof(struct st_hba));
1559
1560 err = pci_request_regions(pdev, DRV_NAME);
1561 if (err < 0) {
1562 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1563 pci_name(pdev));
1564 goto out_scsi_host_put;
1565 }
1566
25729a7f 1567 hba->mmio_base = pci_ioremap_bar(pdev, 0);
5a25ba16
JG		 1568 if ( !hba->mmio_base) {
1569 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1570 pci_name(pdev));
1571 err = -ENOMEM;
1572 goto out_release_regions;
1573 }
1574
1575 err = stex_set_dma_mask(pdev);
1576 if (err) {
1577 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1578 pci_name(pdev));
1579 goto out_iounmap;
1580 }
1581
94e9108b 1582 hba->cardtype = (unsigned int) id->driver_data;
591a3a5f 1583 ci = &stex_card_info[hba->cardtype];
0f3f6ee6
EL		 1584 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1585 if (hba->cardtype == st_yel)
1586 sts_offset += (ci->sts_count+1) * sizeof(u32);
591a3a5f
EL		 1587 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1588 hba->dma_size = cp_offset + sizeof(struct st_frame);
1589 if (hba->cardtype == st_seq ||
1590 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1591 hba->extra_offset = hba->dma_size;
1592 hba->dma_size += ST_ADDITIONAL_MEM;
1593 }
5a25ba16 1594 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
94e9108b 1595 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
5a25ba16 1596 if (!hba->dma_mem) {
cbacfb5f
EL		 1597 /* Retry minimum coherent mapping for st_seq and st_vsc */
1598 if (hba->cardtype == st_seq ||
1599 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1600 printk(KERN_WARNING DRV_NAME
1601 "(%s): allocating min buffer for controller\n",
1602 pci_name(pdev));
1603 hba->dma_size = hba->extra_offset
1604 + ST_ADDITIONAL_MEM_MIN;
1605 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1606 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1607 }
1608
1609 if (!hba->dma_mem) {
1610 err = -ENOMEM;
1611 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1612 pci_name(pdev));
1613 goto out_iounmap;
1614 }
5a25ba16
JG		 1615 }
1616
591a3a5f
EL		 1617 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1618 if (!hba->ccb) {
1619 err = -ENOMEM;
1620 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1621 pci_name(pdev));
1622 goto out_pci_free;
1623 }
1624
0f3f6ee6
EL		 1625 if (hba->cardtype == st_yel)
1626 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
591a3a5f
EL		 1627 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1628 hba->copy_buffer = hba->dma_mem + cp_offset;
1629 hba->rq_count = ci->rq_count;
1630 hba->rq_size = ci->rq_size;
1631 hba->sts_count = ci->sts_count;
0f3f6ee6
EL		 1632 hba->alloc_rq = ci->alloc_rq;
1633 hba->map_sg = ci->map_sg;
1634 hba->send = ci->send;
5a25ba16
JG		 1635 hba->mu_status = MU_STATE_STARTING;
1636
0f3f6ee6
EL		 1637 if (hba->cardtype == st_yel)
1638 host->sg_tablesize = 38;
1639 else
1640 host->sg_tablesize = 32;
591a3a5f
EL		 1641 host->can_queue = ci->rq_count;
1642 host->cmd_per_lun = ci->rq_count;
1643 host->max_id = ci->max_id;
1644 host->max_lun = ci->max_lun;
1645 host->max_channel = ci->max_channel;
5a25ba16
JG		 1646 host->unique_id = host->host_no;
1647 host->max_cmd_len = STEX_CDB_LENGTH;
1648
1649 hba->host = host;
1650 hba->pdev = pdev;
9eb46d2a
EL		 1651 init_waitqueue_head(&hba->reset_waitq);
1652
1653 snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1654 "stex_wq_%d", host->host_no);
1655 hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1656 if (!hba->work_q) {
1657 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1658 pci_name(pdev));
1659 err = -ENOMEM;
1660 goto out_ccb_free;
1661 }
1662 INIT_WORK(&hba->reset_work, stex_reset_work);
5a25ba16 1663
99946f81 1664 err = stex_request_irq(hba);
5a25ba16
JG		 1665 if (err) {
1666 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1667 pci_name(pdev));
9eb46d2a 1668 goto out_free_wq;
5a25ba16
JG		 1669 }
1670
1671 err = stex_handshake(hba);
1672 if (err)
1673 goto out_free_irq;
1674
529e7a62 1675 err = scsi_init_shared_tag_map(host, host->can_queue);
deb81d80 1676 if (err) {
cf355883
EL		 1677 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1678 pci_name(pdev));
1679 goto out_free_irq;
1680 }
1681
5a25ba16
JG		 1682 pci_set_drvdata(pdev, hba);
1683
1684 err = scsi_add_host(host, &pdev->dev);
1685 if (err) {
1686 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1687 pci_name(pdev));
1688 goto out_free_irq;
1689 }
1690
1691 scsi_scan_host(host);
1692
1693 return 0;
1694
1695out_free_irq:
99946f81 1696 stex_free_irq(hba);
9eb46d2a
EL		 1697out_free_wq:
1698 destroy_workqueue(hba->work_q);
591a3a5f
EL		 1699out_ccb_free:
1700 kfree(hba->ccb);
5a25ba16 1701out_pci_free:
94e9108b 1702 dma_free_coherent(&pdev->dev, hba->dma_size,
5a25ba16
JG		 1703 hba->dma_mem, hba->dma_handle);
1704out_iounmap:
1705 iounmap(hba->mmio_base);
1706out_release_regions:
1707 pci_release_regions(pdev);
1708out_scsi_host_put:
1709 scsi_host_put(host);
1710out_disable:
1711 pci_disable_device(pdev);
1712
1713 return err;
1714}
1715
1716static void stex_hba_stop(struct st_hba *hba)
1717{
1718 struct req_msg *req;
0f3f6ee6 1719 struct st_msg_header *msg_h;
5a25ba16
JG		 1720 unsigned long flags;
1721 unsigned long before;
cf355883 1722 u16 tag = 0;
5a25ba16
JG		 1723
1724 spin_lock_irqsave(hba->host->host_lock, flags);
0f3f6ee6
EL		 1725 req = hba->alloc_rq(hba);
1726 if (hba->cardtype == st_yel) {
1727 msg_h = (struct st_msg_header *)req - 1;
1728 memset(msg_h, 0, hba->rq_size);
1729 } else
1730 memset(req, 0, hba->rq_size);
5a25ba16 1731
0f3f6ee6 1732 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
fb4f66be
EL		 1733 req->cdb[0] = MGT_CMD;
1734 req->cdb[1] = MGT_CMD_SIGNATURE;
1735 req->cdb[2] = CTLR_CONFIG_CMD;
1736 req->cdb[3] = CTLR_SHUTDOWN;
1737 } else {
1738 req->cdb[0] = CONTROLLER_CMD;
1739 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1740 req->cdb[2] = CTLR_POWER_SAVING;
1741 }
5a25ba16
JG		 1742
1743 hba->ccb[tag].cmd = NULL;
1744 hba->ccb[tag].sg_count = 0;
1745 hba->ccb[tag].sense_bufflen = 0;
1746 hba->ccb[tag].sense_buffer = NULL;
f1498161 1747 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
5a25ba16 1748
0f3f6ee6 1749 hba->send(hba, req, tag);
5a25ba16
JG		 1750 spin_unlock_irqrestore(hba->host->host_lock, flags);
1751
cf355883
EL		 1752 before = jiffies;
1753 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
f1498161
EL		 1754 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1755 hba->ccb[tag].req_type = 0;
cf355883 1756 return;
f1498161
EL		 1757 }
1758 msleep(1);
cf355883 1759 }
5a25ba16
JG		 1760}
1761
1762static void stex_hba_free(struct st_hba *hba)
1763{
99946f81 1764 stex_free_irq(hba);
5a25ba16 1765
9eb46d2a
EL		 1766 destroy_workqueue(hba->work_q);
1767
5a25ba16
JG		 1768 iounmap(hba->mmio_base);
1769
1770 pci_release_regions(hba->pdev);
1771
591a3a5f
EL		 1772 kfree(hba->ccb);
1773
94e9108b 1774 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
5a25ba16
JG		 1775 hba->dma_mem, hba->dma_handle);
1776}
1777
1778static void stex_remove(struct pci_dev *pdev)
1779{
1780 struct st_hba *hba = pci_get_drvdata(pdev);
1781
1782 scsi_remove_host(hba->host);
1783
5a25ba16
JG		 1784 stex_hba_stop(hba);
1785
1786 stex_hba_free(hba);
1787
1788 scsi_host_put(hba->host);
1789
1790 pci_disable_device(pdev);
1791}
1792
1793static void stex_shutdown(struct pci_dev *pdev)
1794{
1795 struct st_hba *hba = pci_get_drvdata(pdev);
1796
1797 stex_hba_stop(hba);
1798}
1799
5a25ba16
JG		 1800MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1801
1802static struct pci_driver stex_pci_driver = {
1803 .name = DRV_NAME,
1804 .id_table = stex_pci_tbl,
1805 .probe = stex_probe,
6f039790 1806 .remove = stex_remove,
5a25ba16
JG		 1807 .shutdown = stex_shutdown,
1808};
1809
1810static int __init stex_init(void)
1811{
1812 printk(KERN_INFO DRV_NAME
1813 ": Promise SuperTrak EX Driver version: %s\n",
1814 ST_DRIVER_VERSION);
1815
1816 return pci_register_driver(&stex_pci_driver);
1817}
1818
1819static void __exit stex_exit(void)
1820{
1821 pci_unregister_driver(&stex_pci_driver);
1822}
1823
1824module_init(stex_init);
1825module_exit(stex_exit);
Linux 6.x block layer and io_uring tree(s)