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stex: Support to Pegasus series.
[linux-block.git] / drivers / scsi / stex.c
CommitLineData
5a25ba16
JG		 1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
1ec364e6 4 * Copyright (C) 2005-2015 Promise Technology Inc.
5a25ba16
JG		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
5a25ba16
JG		 14 */
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
5a0e3ad6 20#include <linux/slab.h>
5a25ba16
JG		 21#include <linux/time.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/spinlock.h>
0da39687 28#include <linux/ktime.h>
5a25ba16
JG		 29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/byteorder.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_host.h>
cf355883 36#include <scsi/scsi_tcq.h>
c25da0af 37#include <scsi/scsi_dbg.h>
11002fbc 38#include <scsi/scsi_eh.h>
5a25ba16
JG		 39
40#define DRV_NAME "stex"
1ec364e6
C		 41#define ST_DRIVER_VERSION "5.00.0000.01"
42#define ST_VER_MAJOR 5
43#define ST_VER_MINOR 00
44#define ST_OEM 0000
45#define ST_BUILD_VER 01
5a25ba16
JG		 46
47enum {
48 /* MU register offset */
49 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
50 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
51 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
52 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
53 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
54 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
55 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
56 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
57 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
58 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
59
69cb4875 60 YIOA_STATUS = 0x00,
0f3f6ee6
EL		 61 YH2I_INT = 0x20,
62 YINT_EN = 0x34,
63 YI2H_INT = 0x9c,
64 YI2H_INT_C = 0xa0,
65 YH2I_REQ = 0xc0,
66 YH2I_REQ_HI = 0xc4,
67
5a25ba16 68 /* MU register value */
9eb46d2a
EL		 69 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
70 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
71 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
72 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
73 MU_INBOUND_DOORBELL_RESET = (1 << 4),
74
75 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
76 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
77 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
78 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
79 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
80 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
5a25ba16
JG		 81
82 /* MU status code */
83 MU_STATE_STARTING = 1,
9eb46d2a
EL		 84 MU_STATE_STARTED = 2,
85 MU_STATE_RESETTING = 3,
86 MU_STATE_FAILED = 4,
5a25ba16 87
76fbf96f 88 MU_MAX_DELAY = 120,
5a25ba16 89 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
529e7a62 90 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
76fbf96f 91 MU_HARD_RESET_WAIT = 30000,
5a25ba16
JG		 92 HMU_PARTNER_TYPE = 2,
93
94 /* firmware returned values */
95 SRB_STATUS_SUCCESS = 0x01,
96 SRB_STATUS_ERROR = 0x04,
97 SRB_STATUS_BUSY = 0x05,
98 SRB_STATUS_INVALID_REQUEST = 0x06,
99 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
100 SRB_SEE_SENSE = 0x80,
101
102 /* task attribute */
103 TASK_ATTRIBUTE_SIMPLE = 0x0,
104 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
105 TASK_ATTRIBUTE_ORDERED = 0x2,
106 TASK_ATTRIBUTE_ACA = 0x4,
107
0f3f6ee6
EL		 108 SS_STS_NORMAL = 0x80000000,
109 SS_STS_DONE = 0x40000000,
110 SS_STS_HANDSHAKE = 0x20000000,
111
112 SS_HEAD_HANDSHAKE = 0x80,
113
69cb4875
EL		 114 SS_H2I_INT_RESET = 0x100,
115
9eb46d2a
EL		 116 SS_I2H_REQUEST_RESET = 0x2000,
117
69cb4875
EL		 118 SS_MU_OPERATIONAL = 0x80000000,
119
7cfe99a5 120 STEX_CDB_LENGTH = 16,
5a25ba16 121 STATUS_VAR_LEN = 128,
5a25ba16
JG		 122
123 /* sg flags */
124 SG_CF_EOT = 0x80, /* end of table */
125 SG_CF_64B = 0x40, /* 64 bit item */
126 SG_CF_HOST = 0x20, /* sg in host memory */
7cfe99a5
ELP		 127 MSG_DATA_DIR_ND = 0,
128 MSG_DATA_DIR_IN = 1,
129 MSG_DATA_DIR_OUT = 2,
5a25ba16 130
5a25ba16
JG		 131 st_shasta = 0,
132 st_vsc = 1,
591a3a5f
EL		 133 st_yosemite = 2,
134 st_seq = 3,
0f3f6ee6 135 st_yel = 4,
5a25ba16
JG		 136
137 PASSTHRU_REQ_TYPE = 0x00000001,
138 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
7cfe99a5 139 ST_INTERNAL_TIMEOUT = 180,
5a25ba16 140
fb4f66be
EL		 141 ST_TO_CMD = 0,
142 ST_FROM_CMD = 1,
143
5a25ba16 144 /* vendor specific commands of Promise */
fb4f66be
EL		 145 MGT_CMD = 0xd8,
146 SINBAND_MGT_CMD = 0xd9,
5a25ba16
JG		 147 ARRAY_CMD = 0xe0,
148 CONTROLLER_CMD = 0xe1,
149 DEBUGGING_CMD = 0xe2,
150 PASSTHRU_CMD = 0xe3,
151
152 PASSTHRU_GET_ADAPTER = 0x05,
153 PASSTHRU_GET_DRVVER = 0x10,
fb4f66be
EL		 154
155 CTLR_CONFIG_CMD = 0x03,
156 CTLR_SHUTDOWN = 0x0d,
157
5a25ba16
JG		 158 CTLR_POWER_STATE_CHANGE = 0x0e,
159 CTLR_POWER_SAVING = 0x01,
160
161 PASSTHRU_SIGNATURE = 0x4e415041,
fb4f66be 162 MGT_CMD_SIGNATURE = 0xba,
5a25ba16
JG		 163
164 INQUIRY_EVPD = 0x01,
94e9108b
EL		 165
166 ST_ADDITIONAL_MEM = 0x200000,
cbacfb5f 167 ST_ADDITIONAL_MEM_MIN = 0x80000,
5a25ba16
JG		 168};
169
170struct st_sgitem {
171 u8 ctrl; /* SG_CF_xxx */
172 u8 reserved[3];
173 __le32 count;
f1498161 174 __le64 addr;
5a25ba16
JG		 175};
176
0f3f6ee6
EL		 177struct st_ss_sgitem {
178 __le32 addr;
179 __le32 addr_hi;
180 __le32 count;
181};
182
5a25ba16
JG		 183struct st_sgtable {
184 __le16 sg_count;
185 __le16 max_sg_count;
186 __le32 sz_in_byte;
5a25ba16
JG		 187};
188
0f3f6ee6
EL		 189struct st_msg_header {
190 __le64 handle;
191 u8 flag;
192 u8 channel;
193 __le16 timeout;
194 u32 reserved;
195};
196
5a25ba16 197struct handshake_frame {
f1498161 198 __le64 rb_phy; /* request payload queue physical address */
5a25ba16
JG		 199 __le16 req_sz; /* size of each request payload */
200 __le16 req_cnt; /* count of reqs the buffer can hold */
201 __le16 status_sz; /* size of each status payload */
202 __le16 status_cnt; /* count of status the buffer can hold */
f1498161 203 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
5a25ba16
JG		 204 u8 partner_type; /* who sends this frame */
205 u8 reserved0[7];
206 __le32 partner_ver_major;
207 __le32 partner_ver_minor;
208 __le32 partner_ver_oem;
209 __le32 partner_ver_build;
94e9108b
EL		 210 __le32 extra_offset; /* NEW */
211 __le32 extra_size; /* NEW */
0f3f6ee6
EL		 212 __le32 scratch_size;
213 u32 reserved1;
5a25ba16
JG		 214};
215
216struct req_msg {
217 __le16 tag;
218 u8 lun;
219 u8 target;
220 u8 task_attr;
221 u8 task_manage;
7cfe99a5 222 u8 data_dir;
f903d7b7 223 u8 payload_sz; /* payload size in 4-byte, not used */
5a25ba16 224 u8 cdb[STEX_CDB_LENGTH];
591a3a5f 225 u32 variable[0];
5a25ba16
JG		 226};
227
228struct status_msg {
229 __le16 tag;
230 u8 lun;
231 u8 target;
232 u8 srb_status;
233 u8 scsi_status;
234 u8 reserved;
235 u8 payload_sz; /* payload size in 4-byte */
236 u8 variable[STATUS_VAR_LEN];
237};
238
239struct ver_info {
240 u32 major;
241 u32 minor;
242 u32 oem;
243 u32 build;
244 u32 reserved[2];
245};
246
247struct st_frame {
248 u32 base[6];
249 u32 rom_addr;
250
251 struct ver_info drv_ver;
252 struct ver_info bios_ver;
253
254 u32 bus;
255 u32 slot;
256 u32 irq_level;
257 u32 irq_vec;
258 u32 id;
259 u32 subid;
260
261 u32 dimm_size;
262 u8 dimm_type;
263 u8 reserved[3];
264
265 u32 channel;
266 u32 reserved1;
267};
268
269struct st_drvver {
270 u32 major;
271 u32 minor;
272 u32 oem;
273 u32 build;
274 u32 signature[2];
275 u8 console_id;
276 u8 host_no;
277 u8 reserved0[2];
278 u32 reserved[3];
279};
280
5a25ba16
JG		 281struct st_ccb {
282 struct req_msg *req;
283 struct scsi_cmnd *cmd;
284
285 void *sense_buffer;
286 unsigned int sense_bufflen;
287 int sg_count;
288
289 u32 req_type;
290 u8 srb_status;
291 u8 scsi_status;
f1498161 292 u8 reserved[2];
5a25ba16
JG		 293};
294
295struct st_hba {
296 void __iomem *mmio_base; /* iomapped PCI memory space */
297 void *dma_mem;
298 dma_addr_t dma_handle;
94e9108b 299 size_t dma_size;
5a25ba16
JG		 300
301 struct Scsi_Host *host;
302 struct pci_dev *pdev;
303
0f3f6ee6
EL		 304 struct req_msg * (*alloc_rq) (struct st_hba *);
305 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
306 void (*send) (struct st_hba *, struct req_msg *, u16);
307
5a25ba16
JG		 308 u32 req_head;
309 u32 req_tail;
310 u32 status_head;
311 u32 status_tail;
312
313 struct status_msg *status_buffer;
314 void *copy_buffer; /* temp buffer for driver-handled commands */
591a3a5f 315 struct st_ccb *ccb;
5a25ba16 316 struct st_ccb *wait_ccb;
0f3f6ee6 317 __le32 *scratch;
5a25ba16 318
9eb46d2a
EL		 319 char work_q_name[20];
320 struct workqueue_struct *work_q;
321 struct work_struct reset_work;
322 wait_queue_head_t reset_waitq;
5a25ba16 323 unsigned int mu_status;
5a25ba16 324 unsigned int cardtype;
99946f81
EL		 325 int msi_enabled;
326 int out_req_cnt;
591a3a5f
EL		 327 u32 extra_offset;
328 u16 rq_count;
329 u16 rq_size;
330 u16 sts_count;
1ec364e6 331 u8 supports_pm;
591a3a5f
EL		 332};
333
334struct st_card_info {
0f3f6ee6
EL		 335 struct req_msg * (*alloc_rq) (struct st_hba *);
336 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
337 void (*send) (struct st_hba *, struct req_msg *, u16);
591a3a5f
EL		 338 unsigned int max_id;
339 unsigned int max_lun;
340 unsigned int max_channel;
341 u16 rq_count;
342 u16 rq_size;
343 u16 sts_count;
5a25ba16
JG		 344};
345
99946f81
EL		 346static int msi;
347module_param(msi, int, 0);
348MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
349
5a25ba16
JG		 350static const char console_inq_page[] =
351{
352 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
353 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
354 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
355 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
356 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
357 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
358 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
359 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
360};
361
362MODULE_AUTHOR("Ed Lin");
363MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
364MODULE_LICENSE("GPL");
365MODULE_VERSION(ST_DRIVER_VERSION);
366
5a25ba16
JG		 367static struct status_msg *stex_get_status(struct st_hba *hba)
368{
f1498161 369 struct status_msg *status = hba->status_buffer + hba->status_tail;
5a25ba16
JG		 370
371 ++hba->status_tail;
591a3a5f 372 hba->status_tail %= hba->sts_count+1;
5a25ba16
JG		 373
374 return status;
375}
376
5a25ba16
JG		 377static void stex_invalid_field(struct scsi_cmnd *cmd,
378 void (*done)(struct scsi_cmnd *))
379{
11002fbc
FT		 380 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
381
7cfe99a5 382 /* "Invalid field in cdb" */
11002fbc
FT		 383 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
384 0x0);
5a25ba16
JG		 385 done(cmd);
386}
387
388static struct req_msg *stex_alloc_req(struct st_hba *hba)
389{
591a3a5f 390 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
5a25ba16
JG		 391
392 ++hba->req_head;
591a3a5f 393 hba->req_head %= hba->rq_count+1;
5a25ba16
JG		 394
395 return req;
396}
397
0f3f6ee6
EL		 398static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
399{
400 return (struct req_msg *)(hba->dma_mem +
401 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
402}
403
5a25ba16
JG		 404static int stex_map_sg(struct st_hba *hba,
405 struct req_msg *req, struct st_ccb *ccb)
406{
5a25ba16 407 struct scsi_cmnd *cmd;
d5587d5d 408 struct scatterlist *sg;
5a25ba16 409 struct st_sgtable *dst;
f1498161 410 struct st_sgitem *table;
d5587d5d 411 int i, nseg;
5a25ba16
JG		 412
413 cmd = ccb->cmd;
d5587d5d 414 nseg = scsi_dma_map(cmd);
f1498161 415 BUG_ON(nseg < 0);
d5587d5d 416 if (nseg) {
f1498161
EL		 417 dst = (struct st_sgtable *)req->variable;
418
d5587d5d
FT		 419 ccb->sg_count = nseg;
420 dst->sg_count = cpu_to_le16((u16)nseg);
f1498161
EL		 421 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
422 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
5a25ba16 423
f1498161 424 table = (struct st_sgitem *)(dst + 1);
d5587d5d 425 scsi_for_each_sg(cmd, sg, nseg, i) {
f1498161
EL		 426 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
427 table[i].addr = cpu_to_le64(sg_dma_address(sg));
428 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
5a25ba16 429 }
f1498161 430 table[--i].ctrl |= SG_CF_EOT;
5a25ba16
JG		 431 }
432
f1498161 433 return nseg;
5a25ba16
JG		 434}
435
0f3f6ee6
EL		 436static int stex_ss_map_sg(struct st_hba *hba,
437 struct req_msg *req, struct st_ccb *ccb)
438{
439 struct scsi_cmnd *cmd;
440 struct scatterlist *sg;
441 struct st_sgtable *dst;
442 struct st_ss_sgitem *table;
443 int i, nseg;
444
445 cmd = ccb->cmd;
446 nseg = scsi_dma_map(cmd);
447 BUG_ON(nseg < 0);
448 if (nseg) {
449 dst = (struct st_sgtable *)req->variable;
450
451 ccb->sg_count = nseg;
452 dst->sg_count = cpu_to_le16((u16)nseg);
453 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
454 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
455
456 table = (struct st_ss_sgitem *)(dst + 1);
457 scsi_for_each_sg(cmd, sg, nseg, i) {
458 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
459 table[i].addr =
460 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
461 table[i].addr_hi =
462 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
463 }
464 }
465
466 return nseg;
467}
468
5a25ba16
JG		 469static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
470{
471 struct st_frame *p;
472 size_t count = sizeof(struct st_frame);
473
474 p = hba->copy_buffer;
f1498161 475 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
5a25ba16
JG		 476 memset(p->base, 0, sizeof(u32)*6);
477 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
478 p->rom_addr = 0;
479
480 p->drv_ver.major = ST_VER_MAJOR;
481 p->drv_ver.minor = ST_VER_MINOR;
482 p->drv_ver.oem = ST_OEM;
483 p->drv_ver.build = ST_BUILD_VER;
484
485 p->bus = hba->pdev->bus->number;
486 p->slot = hba->pdev->devfn;
487 p->irq_level = 0;
488 p->irq_vec = hba->pdev->irq;
489 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
490 p->subid =
491 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
492
f1498161 493 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
5a25ba16
JG		 494}
495
496static void
497stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
498{
499 req->tag = cpu_to_le16(tag);
5a25ba16
JG		 500
501 hba->ccb[tag].req = req;
502 hba->out_req_cnt++;
503
504 writel(hba->req_head, hba->mmio_base + IMR0);
505 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
506 readl(hba->mmio_base + IDBL); /* flush */
507}
508
0f3f6ee6
EL		 509static void
510stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
511{
512 struct scsi_cmnd *cmd;
513 struct st_msg_header *msg_h;
514 dma_addr_t addr;
515
516 req->tag = cpu_to_le16(tag);
517
518 hba->ccb[tag].req = req;
519 hba->out_req_cnt++;
520
521 cmd = hba->ccb[tag].cmd;
522 msg_h = (struct st_msg_header *)req - 1;
523 if (likely(cmd)) {
524 msg_h->channel = (u8)cmd->device->channel;
525 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
526 }
527 addr = hba->dma_handle + hba->req_head * hba->rq_size;
528 addr += (hba->ccb[tag].sg_count+4)/11;
529 msg_h->handle = cpu_to_le64(addr);
530
531 ++hba->req_head;
532 hba->req_head %= hba->rq_count+1;
533
534 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
535 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
536 writel(addr, hba->mmio_base + YH2I_REQ);
537 readl(hba->mmio_base + YH2I_REQ); /* flush */
538}
539
5a25ba16
JG		 540static int
541stex_slave_config(struct scsi_device *sdev)
542{
543 sdev->use_10_for_rw = 1;
544 sdev->use_10_for_ms = 1;
dc5c49bf 545 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
cf355883 546
5a25ba16
JG		 547 return 0;
548}
549
5a25ba16 550static int
f281233d 551stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
5a25ba16
JG		 552{
553 struct st_hba *hba;
554 struct Scsi_Host *host;
f1498161 555 unsigned int id, lun;
5a25ba16
JG		 556 struct req_msg *req;
557 u16 tag;
7cfe99a5 558
5a25ba16
JG		 559 host = cmd->device->host;
560 id = cmd->device->id;
e0b2e597 561 lun = cmd->device->lun;
5a25ba16
JG		 562 hba = (struct st_hba *) &host->hostdata[0];
563
9eb46d2a
EL		 564 if (unlikely(hba->mu_status == MU_STATE_RESETTING))
565 return SCSI_MLQUEUE_HOST_BUSY;
566
5a25ba16
JG		 567 switch (cmd->cmnd[0]) {
568 case MODE_SENSE_10:
569 {
570 static char ms10_caching_page[12] =
571 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
572 unsigned char page;
7cfe99a5 573
5a25ba16
JG		 574 page = cmd->cmnd[2] & 0x3f;
575 if (page == 0x8 || page == 0x3f) {
31fe47d4
FT		 576 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
577 sizeof(ms10_caching_page));
5a25ba16
JG		 578 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
579 done(cmd);
580 } else
581 stex_invalid_field(cmd, done);
582 return 0;
583 }
e0b2e597
EL		 584 case REPORT_LUNS:
585 /*
586 * The shasta firmware does not report actual luns in the
587 * target, so fail the command to force sequential lun scan.
588 * Also, the console device does not support this command.
589 */
590 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
591 stex_invalid_field(cmd, done);
592 return 0;
593 }
594 break;
d116a7bc
EL		 595 case TEST_UNIT_READY:
596 if (id == host->max_id - 1) {
597 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
598 done(cmd);
599 return 0;
600 }
601 break;
5a25ba16 602 case INQUIRY:
91e6ecad
EL		 603 if (lun >= host->max_lun) {
604 cmd->result = DID_NO_CONNECT << 16;
605 done(cmd);
606 return 0;
607 }
e0b2e597 608 if (id != host->max_id - 1)
5a25ba16 609 break;
0f3f6ee6
EL		 610 if (!lun && !cmd->device->channel &&
611 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
31fe47d4
FT		 612 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
613 sizeof(console_inq_page));
5a25ba16
JG		 614 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
615 done(cmd);
616 } else
617 stex_invalid_field(cmd, done);
618 return 0;
619 case PASSTHRU_CMD:
620 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
621 struct st_drvver ver;
26106e3c 622 size_t cp_len = sizeof(ver);
7cfe99a5 623
5a25ba16
JG		 624 ver.major = ST_VER_MAJOR;
625 ver.minor = ST_VER_MINOR;
626 ver.oem = ST_OEM;
627 ver.build = ST_BUILD_VER;
628 ver.signature[0] = PASSTHRU_SIGNATURE;
e0b2e597 629 ver.console_id = host->max_id - 1;
5a25ba16 630 ver.host_no = hba->host->host_no;
31fe47d4 631 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
26106e3c 632 cmd->result = sizeof(ver) == cp_len ?
5a25ba16
JG		 633 DID_OK << 16 | COMMAND_COMPLETE << 8 :
634 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
635 done(cmd);
636 return 0;
637 }
638 default:
639 break;
640 }
641
642 cmd->scsi_done = done;
643
cf355883
EL		 644 tag = cmd->request->tag;
645
646 if (unlikely(tag >= host->can_queue))
5a25ba16
JG		 647 return SCSI_MLQUEUE_HOST_BUSY;
648
0f3f6ee6 649 req = hba->alloc_rq(hba);
fb4f66be 650
e0b2e597
EL		 651 req->lun = lun;
652 req->target = id;
5a25ba16
JG		 653
654 /* cdb */
655 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
656
7cfe99a5
ELP		 657 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
658 req->data_dir = MSG_DATA_DIR_IN;
659 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
660 req->data_dir = MSG_DATA_DIR_OUT;
661 else
662 req->data_dir = MSG_DATA_DIR_ND;
663
5a25ba16
JG		 664 hba->ccb[tag].cmd = cmd;
665 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
666 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
5a25ba16 667
0f3f6ee6
EL		 668 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
669 hba->ccb[tag].sg_count = 0;
670 memset(&req->variable[0], 0, 8);
671 }
5a25ba16 672
0f3f6ee6 673 hba->send(hba, req, tag);
5a25ba16
JG		 674 return 0;
675}
676
f281233d
JG		 677static DEF_SCSI_QCMD(stex_queuecommand)
678
5a25ba16
JG		 679static void stex_scsi_done(struct st_ccb *ccb)
680{
681 struct scsi_cmnd *cmd = ccb->cmd;
682 int result;
683
f1498161 684 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
5a25ba16
JG		 685 result = ccb->scsi_status;
686 switch (ccb->scsi_status) {
687 case SAM_STAT_GOOD:
688 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
689 break;
690 case SAM_STAT_CHECK_CONDITION:
691 result |= DRIVER_SENSE << 24;
692 break;
693 case SAM_STAT_BUSY:
694 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
695 break;
696 default:
697 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
698 break;
699 }
700 }
701 else if (ccb->srb_status & SRB_SEE_SENSE)
702 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
703 else switch (ccb->srb_status) {
704 case SRB_STATUS_SELECTION_TIMEOUT:
705 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
706 break;
707 case SRB_STATUS_BUSY:
708 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
709 break;
710 case SRB_STATUS_INVALID_REQUEST:
711 case SRB_STATUS_ERROR:
712 default:
713 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
714 break;
715 }
716
717 cmd->result = result;
718 cmd->scsi_done(cmd);
719}
720
721static void stex_copy_data(struct st_ccb *ccb,
722 struct status_msg *resp, unsigned int variable)
723{
5a25ba16
JG		 724 if (resp->scsi_status != SAM_STAT_GOOD) {
725 if (ccb->sense_buffer != NULL)
726 memcpy(ccb->sense_buffer, resp->variable,
727 min(variable, ccb->sense_bufflen));
728 return;
729 }
730
731 if (ccb->cmd == NULL)
732 return;
f1498161 733 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
fb4f66be
EL		 734}
735
f1498161 736static void stex_check_cmd(struct st_hba *hba,
fb4f66be
EL		 737 struct st_ccb *ccb, struct status_msg *resp)
738{
fb4f66be 739 if (ccb->cmd->cmnd[0] == MGT_CMD &&
f1498161 740 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
968a5763
EL		 741 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
742 le32_to_cpu(*(__le32 *)&resp->variable[0]));
5a25ba16
JG		 743}
744
745static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
746{
747 void __iomem *base = hba->mmio_base;
748 struct status_msg *resp;
749 struct st_ccb *ccb;
750 unsigned int size;
751 u16 tag;
752
f1498161 753 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
5a25ba16
JG		 754 return;
755
756 /* status payloads */
757 hba->status_head = readl(base + OMR1);
591a3a5f 758 if (unlikely(hba->status_head > hba->sts_count)) {
5a25ba16
JG		 759 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
760 pci_name(hba->pdev));
761 return;
762 }
763
fb4f66be
EL		 764 /*
765 * it's not a valid status payload if:
766 * 1. there are no pending requests(e.g. during init stage)
767 * 2. there are some pending requests, but the controller is in
768 * reset status, and its type is not st_yosemite
769 * firmware of st_yosemite in reset status will return pending requests
770 * to driver, so we allow it to pass
771 */
772 if (unlikely(hba->out_req_cnt <= 0 ||
773 (hba->mu_status == MU_STATE_RESETTING &&
774 hba->cardtype != st_yosemite))) {
5a25ba16
JG		 775 hba->status_tail = hba->status_head;
776 goto update_status;
777 }
778
779 while (hba->status_tail != hba->status_head) {
780 resp = stex_get_status(hba);
781 tag = le16_to_cpu(resp->tag);
cf355883 782 if (unlikely(tag >= hba->host->can_queue)) {
5a25ba16
JG		 783 printk(KERN_WARNING DRV_NAME
784 "(%s): invalid tag\n", pci_name(hba->pdev));
785 continue;
786 }
5a25ba16 787
f1498161 788 hba->out_req_cnt--;
5a25ba16 789 ccb = &hba->ccb[tag];
f1498161 790 if (unlikely(hba->wait_ccb == ccb))
5a25ba16
JG		 791 hba->wait_ccb = NULL;
792 if (unlikely(ccb->req == NULL)) {
793 printk(KERN_WARNING DRV_NAME
794 "(%s): lagging req\n", pci_name(hba->pdev));
5a25ba16
JG		 795 continue;
796 }
797
798 size = resp->payload_sz * sizeof(u32); /* payload size */
799 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
800 size > sizeof(*resp))) {
801 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
802 pci_name(hba->pdev));
803 } else {
804 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
805 if (size)
806 stex_copy_data(ccb, resp, size);
807 }
808
dd48ebf7 809 ccb->req = NULL;
5a25ba16
JG		 810 ccb->srb_status = resp->srb_status;
811 ccb->scsi_status = resp->scsi_status;
812
cf355883 813 if (likely(ccb->cmd != NULL)) {
fb4f66be 814 if (hba->cardtype == st_yosemite)
f1498161 815 stex_check_cmd(hba, ccb, resp);
fb4f66be 816
cf355883
EL		 817 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
818 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
819 stex_controller_info(hba, ccb);
fb4f66be 820
d5587d5d 821 scsi_dma_unmap(ccb->cmd);
cf355883 822 stex_scsi_done(ccb);
f1498161 823 } else
5a25ba16 824 ccb->req_type = 0;
5a25ba16
JG		 825 }
826
827update_status:
828 writel(hba->status_head, base + IMR1);
829 readl(base + IMR1); /* flush */
830}
831
7d12e780 832static irqreturn_t stex_intr(int irq, void *__hba)
5a25ba16
JG		 833{
834 struct st_hba *hba = __hba;
835 void __iomem *base = hba->mmio_base;
836 u32 data;
837 unsigned long flags;
5a25ba16
JG		 838
839 spin_lock_irqsave(hba->host->host_lock, flags);
840
841 data = readl(base + ODBL);
842
843 if (data && data != 0xffffffff) {
844 /* clear the interrupt */
845 writel(data, base + ODBL);
846 readl(base + ODBL); /* flush */
847 stex_mu_intr(hba, data);
9eb46d2a
EL		 848 spin_unlock_irqrestore(hba->host->host_lock, flags);
849 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
850 hba->cardtype == st_shasta))
851 queue_work(hba->work_q, &hba->reset_work);
852 return IRQ_HANDLED;
5a25ba16
JG		 853 }
854
855 spin_unlock_irqrestore(hba->host->host_lock, flags);
856
9eb46d2a 857 return IRQ_NONE;
5a25ba16
JG		 858}
859
0f3f6ee6
EL		 860static void stex_ss_mu_intr(struct st_hba *hba)
861{
862 struct status_msg *resp;
863 struct st_ccb *ccb;
864 __le32 *scratch;
865 unsigned int size;
866 int count = 0;
867 u32 value;
868 u16 tag;
869
870 if (unlikely(hba->out_req_cnt <= 0 ||
871 hba->mu_status == MU_STATE_RESETTING))
872 return;
873
874 while (count < hba->sts_count) {
875 scratch = hba->scratch + hba->status_tail;
876 value = le32_to_cpu(*scratch);
877 if (unlikely(!(value & SS_STS_NORMAL)))
878 return;
879
880 resp = hba->status_buffer + hba->status_tail;
881 *scratch = 0;
882 ++count;
883 ++hba->status_tail;
884 hba->status_tail %= hba->sts_count+1;
885
886 tag = (u16)value;
887 if (unlikely(tag >= hba->host->can_queue)) {
888 printk(KERN_WARNING DRV_NAME
69cb4875 889 "(%s): invalid tag\n", pci_name(hba->pdev));
0f3f6ee6
EL		 890 continue;
891 }
892
893 hba->out_req_cnt--;
894 ccb = &hba->ccb[tag];
895 if (unlikely(hba->wait_ccb == ccb))
896 hba->wait_ccb = NULL;
897 if (unlikely(ccb->req == NULL)) {
898 printk(KERN_WARNING DRV_NAME
899 "(%s): lagging req\n", pci_name(hba->pdev));
900 continue;
901 }
902
903 ccb->req = NULL;
904 if (likely(value & SS_STS_DONE)) { /* normal case */
905 ccb->srb_status = SRB_STATUS_SUCCESS;
906 ccb->scsi_status = SAM_STAT_GOOD;
907 } else {
908 ccb->srb_status = resp->srb_status;
909 ccb->scsi_status = resp->scsi_status;
910 size = resp->payload_sz * sizeof(u32);
911 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
912 size > sizeof(*resp))) {
913 printk(KERN_WARNING DRV_NAME
914 "(%s): bad status size\n",
915 pci_name(hba->pdev));
916 } else {
917 size -= sizeof(*resp) - STATUS_VAR_LEN;
918 if (size)
919 stex_copy_data(ccb, resp, size);
920 }
921 if (likely(ccb->cmd != NULL))
922 stex_check_cmd(hba, ccb, resp);
923 }
924
925 if (likely(ccb->cmd != NULL)) {
926 scsi_dma_unmap(ccb->cmd);
927 stex_scsi_done(ccb);
928 } else
929 ccb->req_type = 0;
930 }
931}
932
933static irqreturn_t stex_ss_intr(int irq, void *__hba)
934{
935 struct st_hba *hba = __hba;
936 void __iomem *base = hba->mmio_base;
937 u32 data;
938 unsigned long flags;
0f3f6ee6
EL		 939
940 spin_lock_irqsave(hba->host->host_lock, flags);
941
942 data = readl(base + YI2H_INT);
943 if (data && data != 0xffffffff) {
944 /* clear the interrupt */
945 writel(data, base + YI2H_INT_C);
946 stex_ss_mu_intr(hba);
9eb46d2a
EL		 947 spin_unlock_irqrestore(hba->host->host_lock, flags);
948 if (unlikely(data & SS_I2H_REQUEST_RESET))
949 queue_work(hba->work_q, &hba->reset_work);
950 return IRQ_HANDLED;
0f3f6ee6
EL		 951 }
952
953 spin_unlock_irqrestore(hba->host->host_lock, flags);
954
9eb46d2a 955 return IRQ_NONE;
0f3f6ee6
EL		 956}
957
958static int stex_common_handshake(struct st_hba *hba)
5a25ba16
JG		 959{
960 void __iomem *base = hba->mmio_base;
961 struct handshake_frame *h;
962 dma_addr_t status_phys;
529e7a62 963 u32 data;
76fbf96f 964 unsigned long before;
5a25ba16
JG		 965
966 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
967 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
968 readl(base + IDBL);
76fbf96f
EL		 969 before = jiffies;
970 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
971 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
972 printk(KERN_ERR DRV_NAME
973 "(%s): no handshake signature\n",
974 pci_name(hba->pdev));
975 return -1;
976 }
5a25ba16
JG		 977 rmb();
978 msleep(1);
979 }
5a25ba16
JG		 980 }
981
982 udelay(10);
983
529e7a62
EL		 984 data = readl(base + OMR1);
985 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
986 data &= 0x0000ffff;
f1498161 987 if (hba->host->can_queue > data) {
529e7a62 988 hba->host->can_queue = data;
f1498161
EL		 989 hba->host->cmd_per_lun = data;
990 }
529e7a62
EL		 991 }
992
f1498161
EL		 993 h = (struct handshake_frame *)hba->status_buffer;
994 h->rb_phy = cpu_to_le64(hba->dma_handle);
591a3a5f
EL		 995 h->req_sz = cpu_to_le16(hba->rq_size);
996 h->req_cnt = cpu_to_le16(hba->rq_count+1);
5a25ba16 997 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
591a3a5f 998 h->status_cnt = cpu_to_le16(hba->sts_count+1);
0da39687 999 h->hosttime = cpu_to_le64(ktime_get_real_seconds());
5a25ba16 1000 h->partner_type = HMU_PARTNER_TYPE;
591a3a5f
EL		 1001 if (hba->extra_offset) {
1002 h->extra_offset = cpu_to_le32(hba->extra_offset);
cbacfb5f 1003 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
94e9108b
EL		 1004 } else
1005 h->extra_offset = h->extra_size = 0;
5a25ba16 1006
591a3a5f 1007 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
5a25ba16
JG		 1008 writel(status_phys, base + IMR0);
1009 readl(base + IMR0);
1010 writel((status_phys >> 16) >> 16, base + IMR1);
1011 readl(base + IMR1);
1012
1013 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1014 readl(base + OMR0);
1015 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1016 readl(base + IDBL); /* flush */
1017
1018 udelay(10);
76fbf96f
EL		 1019 before = jiffies;
1020 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1021 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1022 printk(KERN_ERR DRV_NAME
1023 "(%s): no signature after handshake frame\n",
1024 pci_name(hba->pdev));
1025 return -1;
1026 }
5a25ba16
JG		 1027 rmb();
1028 msleep(1);
1029 }
1030
5a25ba16
JG		 1031 writel(0, base + IMR0);
1032 readl(base + IMR0);
1033 writel(0, base + OMR0);
1034 readl(base + OMR0);
1035 writel(0, base + IMR1);
1036 readl(base + IMR1);
1037 writel(0, base + OMR1);
1038 readl(base + OMR1); /* flush */
5a25ba16
JG		 1039 return 0;
1040}
1041
0f3f6ee6
EL		 1042static int stex_ss_handshake(struct st_hba *hba)
1043{
1044 void __iomem *base = hba->mmio_base;
1045 struct st_msg_header *msg_h;
1046 struct handshake_frame *h;
69cb4875 1047 __le32 *scratch;
9eb46d2a 1048 u32 data, scratch_size;
0f3f6ee6
EL		 1049 unsigned long before;
1050 int ret = 0;
1051
69cb4875
EL		 1052 before = jiffies;
1053 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1054 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1055 printk(KERN_ERR DRV_NAME
1056 "(%s): firmware not operational\n",
1057 pci_name(hba->pdev));
1058 return -1;
1059 }
1060 msleep(1);
1061 }
1062
1063 msg_h = (struct st_msg_header *)hba->dma_mem;
0f3f6ee6
EL		 1064 msg_h->handle = cpu_to_le64(hba->dma_handle);
1065 msg_h->flag = SS_HEAD_HANDSHAKE;
1066
69cb4875 1067 h = (struct handshake_frame *)(msg_h + 1);
0f3f6ee6
EL		 1068 h->rb_phy = cpu_to_le64(hba->dma_handle);
1069 h->req_sz = cpu_to_le16(hba->rq_size);
1070 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1071 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1072 h->status_cnt = cpu_to_le16(hba->sts_count+1);
0da39687 1073 h->hosttime = cpu_to_le64(ktime_get_real_seconds());
0f3f6ee6
EL		 1074 h->partner_type = HMU_PARTNER_TYPE;
1075 h->extra_offset = h->extra_size = 0;
9eb46d2a
EL		 1076 scratch_size = (hba->sts_count+1)*sizeof(u32);
1077 h->scratch_size = cpu_to_le32(scratch_size);
0f3f6ee6
EL		 1078
1079 data = readl(base + YINT_EN);
1080 data &= ~4;
1081 writel(data, base + YINT_EN);
1082 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
9eb46d2a 1083 readl(base + YH2I_REQ_HI);
0f3f6ee6 1084 writel(hba->dma_handle, base + YH2I_REQ);
9eb46d2a 1085 readl(base + YH2I_REQ); /* flush */
0f3f6ee6
EL		 1086
1087 scratch = hba->scratch;
1088 before = jiffies;
1089 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1090 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1091 printk(KERN_ERR DRV_NAME
1092 "(%s): no signature after handshake frame\n",
1093 pci_name(hba->pdev));
1094 ret = -1;
1095 break;
1096 }
1097 rmb();
1098 msleep(1);
1099 }
1100
9eb46d2a 1101 memset(scratch, 0, scratch_size);
0f3f6ee6
EL		 1102 msg_h->flag = 0;
1103 return ret;
1104}
1105
1106static int stex_handshake(struct st_hba *hba)
1107{
1108 int err;
1109 unsigned long flags;
9eb46d2a 1110 unsigned int mu_status;
0f3f6ee6
EL		 1111
1112 err = (hba->cardtype == st_yel) ?
1113 stex_ss_handshake(hba) : stex_common_handshake(hba);
9eb46d2a
EL		 1114 spin_lock_irqsave(hba->host->host_lock, flags);
1115 mu_status = hba->mu_status;
0f3f6ee6 1116 if (err == 0) {
0f3f6ee6
EL		 1117 hba->req_head = 0;
1118 hba->req_tail = 0;
1119 hba->status_head = 0;
1120 hba->status_tail = 0;
1121 hba->out_req_cnt = 0;
1122 hba->mu_status = MU_STATE_STARTED;
9eb46d2a
EL		 1123 } else
1124 hba->mu_status = MU_STATE_FAILED;
1125 if (mu_status == MU_STATE_RESETTING)
1126 wake_up_all(&hba->reset_waitq);
1127 spin_unlock_irqrestore(hba->host->host_lock, flags);
0f3f6ee6
EL		 1128 return err;
1129}
1130
5a25ba16
JG		 1131static int stex_abort(struct scsi_cmnd *cmd)
1132{
1133 struct Scsi_Host *host = cmd->device->host;
1134 struct st_hba *hba = (struct st_hba *)host->hostdata;
cf355883 1135 u16 tag = cmd->request->tag;
5a25ba16
JG		 1136 void __iomem *base;
1137 u32 data;
1138 int result = SUCCESS;
1139 unsigned long flags;
c25da0af 1140
1fa6b5fb 1141 scmd_printk(KERN_INFO, cmd, "aborting command\n");
c25da0af 1142
5a25ba16
JG		 1143 base = hba->mmio_base;
1144 spin_lock_irqsave(host->host_lock, flags);
9eb46d2a
EL		 1145 if (tag < host->can_queue &&
1146 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
cf355883 1147 hba->wait_ccb = &hba->ccb[tag];
9eb46d2a
EL		 1148 else
1149 goto out;
5a25ba16 1150
0f3f6ee6
EL		 1151 if (hba->cardtype == st_yel) {
1152 data = readl(base + YI2H_INT);
1153 if (data == 0 || data == 0xffffffff)
1154 goto fail_out;
5a25ba16 1155
0f3f6ee6
EL		 1156 writel(data, base + YI2H_INT_C);
1157 stex_ss_mu_intr(hba);
1158 } else {
1159 data = readl(base + ODBL);
1160 if (data == 0 || data == 0xffffffff)
1161 goto fail_out;
5a25ba16 1162
0f3f6ee6
EL		 1163 writel(data, base + ODBL);
1164 readl(base + ODBL); /* flush */
5a25ba16 1165
0f3f6ee6
EL		 1166 stex_mu_intr(hba, data);
1167 }
5a25ba16
JG		 1168 if (hba->wait_ccb == NULL) {
1169 printk(KERN_WARNING DRV_NAME
1170 "(%s): lost interrupt\n", pci_name(hba->pdev));
1171 goto out;
1172 }
1173
1174fail_out:
d5587d5d 1175 scsi_dma_unmap(cmd);
5a25ba16
JG		 1176 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1177 hba->wait_ccb = NULL;
1178 result = FAILED;
1179out:
1180 spin_unlock_irqrestore(host->host_lock, flags);
1181 return result;
1182}
1183
1184static void stex_hard_reset(struct st_hba *hba)
1185{
1186 struct pci_bus *bus;
1187 int i;
1188 u16 pci_cmd;
1189 u8 pci_bctl;
1190
1191 for (i = 0; i < 16; i++)
1192 pci_read_config_dword(hba->pdev, i * 4,
1193 &hba->pdev->saved_config_space[i]);
1194
1195 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1196 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1197 bus = hba->pdev->bus;
1198 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1199 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1200 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
69f4a513
EL		 1201
1202 /*
1203 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1204 * require more time to finish bus reset. Use 100 ms here for safety
1205 */
1206 msleep(100);
5a25ba16
JG		 1207 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1208 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1209
76fbf96f 1210 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
5a25ba16 1211 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
47c4f997 1212 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
5a25ba16
JG		 1213 break;
1214 msleep(1);
1215 }
1216
1217 ssleep(5);
1218 for (i = 0; i < 16; i++)
1219 pci_write_config_dword(hba->pdev, i * 4,
1220 hba->pdev->saved_config_space[i]);
1221}
1222
9eb46d2a
EL		 1223static int stex_yos_reset(struct st_hba *hba)
1224{
1225 void __iomem *base;
1226 unsigned long flags, before;
1227 int ret = 0;
1228
1229 base = hba->mmio_base;
1230 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1231 readl(base + IDBL); /* flush */
1232 before = jiffies;
1233 while (hba->out_req_cnt > 0) {
1234 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1235 printk(KERN_WARNING DRV_NAME
1236 "(%s): reset timeout\n", pci_name(hba->pdev));
1237 ret = -1;
1238 break;
1239 }
1240 msleep(1);
1241 }
1242
1243 spin_lock_irqsave(hba->host->host_lock, flags);
1244 if (ret == -1)
1245 hba->mu_status = MU_STATE_FAILED;
1246 else
1247 hba->mu_status = MU_STATE_STARTED;
1248 wake_up_all(&hba->reset_waitq);
1249 spin_unlock_irqrestore(hba->host->host_lock, flags);
1250
1251 return ret;
1252}
1253
69cb4875
EL		 1254static void stex_ss_reset(struct st_hba *hba)
1255{
1256 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1257 readl(hba->mmio_base + YH2I_INT);
1258 ssleep(5);
1259}
1260
9eb46d2a 1261static int stex_do_reset(struct st_hba *hba)
5a25ba16 1262{
9eb46d2a
EL		 1263 struct st_ccb *ccb;
1264 unsigned long flags;
1265 unsigned int mu_status = MU_STATE_RESETTING;
1266 u16 tag;
7cfe99a5 1267
9eb46d2a
EL		 1268 spin_lock_irqsave(hba->host->host_lock, flags);
1269 if (hba->mu_status == MU_STATE_STARTING) {
1270 spin_unlock_irqrestore(hba->host->host_lock, flags);
1271 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1272 pci_name(hba->pdev));
1273 return 0;
1274 }
1275 while (hba->mu_status == MU_STATE_RESETTING) {
1276 spin_unlock_irqrestore(hba->host->host_lock, flags);
1277 wait_event_timeout(hba->reset_waitq,
1278 hba->mu_status != MU_STATE_RESETTING,
1279 MU_MAX_DELAY * HZ);
1280 spin_lock_irqsave(hba->host->host_lock, flags);
1281 mu_status = hba->mu_status;
1282 }
5a25ba16 1283
9eb46d2a
EL		 1284 if (mu_status != MU_STATE_RESETTING) {
1285 spin_unlock_irqrestore(hba->host->host_lock, flags);
1286 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1287 }
c25da0af 1288
5a25ba16 1289 hba->mu_status = MU_STATE_RESETTING;
9eb46d2a
EL		 1290 spin_unlock_irqrestore(hba->host->host_lock, flags);
1291
1292 if (hba->cardtype == st_yosemite)
1293 return stex_yos_reset(hba);
5a25ba16
JG		 1294
1295 if (hba->cardtype == st_shasta)
1296 stex_hard_reset(hba);
69cb4875
EL		 1297 else if (hba->cardtype == st_yel)
1298 stex_ss_reset(hba);
5a25ba16 1299
9eb46d2a
EL		 1300 spin_lock_irqsave(hba->host->host_lock, flags);
1301 for (tag = 0; tag < hba->host->can_queue; tag++) {
1302 ccb = &hba->ccb[tag];
1303 if (ccb->req == NULL)
1304 continue;
1305 ccb->req = NULL;
1306 if (ccb->cmd) {
1307 scsi_dma_unmap(ccb->cmd);
1308 ccb->cmd->result = DID_RESET << 16;
1309 ccb->cmd->scsi_done(ccb->cmd);
1310 ccb->cmd = NULL;
fb4f66be 1311 }
5a25ba16 1312 }
9eb46d2a 1313 spin_unlock_irqrestore(hba->host->host_lock, flags);
5a25ba16 1314
9eb46d2a
EL		 1315 if (stex_handshake(hba) == 0)
1316 return 0;
fb4f66be 1317
9eb46d2a
EL		 1318 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1319 pci_name(hba->pdev));
1320 return -1;
1321}
1322
1323static int stex_reset(struct scsi_cmnd *cmd)
1324{
1325 struct st_hba *hba;
1326
1327 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1328
1fa6b5fb
HR		 1329 shost_printk(KERN_INFO, cmd->device->host,
1330 "resetting host\n");
9eb46d2a
EL		 1331
1332 return stex_do_reset(hba) ? FAILED : SUCCESS;
1333}
1334
1335static void stex_reset_work(struct work_struct *work)
1336{
1337 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1338
1339 stex_do_reset(hba);
5a25ba16
JG		 1340}
1341
1342static int stex_biosparam(struct scsi_device *sdev,
1343 struct block_device *bdev, sector_t capacity, int geom[])
1344{
b4b8bed1 1345 int heads = 255, sectors = 63;
5a25ba16
JG		 1346
1347 if (capacity < 0x200000) {
1348 heads = 64;
1349 sectors = 32;
1350 }
1351
b4b8bed1 1352 sector_div(capacity, heads * sectors);
5a25ba16
JG		 1353
1354 geom[0] = heads;
1355 geom[1] = sectors;
b4b8bed1 1356 geom[2] = capacity;
5a25ba16
JG		 1357
1358 return 0;
1359}
1360
1361static struct scsi_host_template driver_template = {
1362 .module = THIS_MODULE,
1363 .name = DRV_NAME,
1364 .proc_name = DRV_NAME,
1365 .bios_param = stex_biosparam,
1366 .queuecommand = stex_queuecommand,
1367 .slave_configure = stex_slave_config,
5a25ba16
JG		 1368 .eh_abort_handler = stex_abort,
1369 .eh_host_reset_handler = stex_reset,
5a25ba16 1370 .this_id = -1,
591a3a5f
EL		 1371};
1372
1373static struct pci_device_id stex_pci_tbl[] = {
1374 /* st_shasta */
1375 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1376 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1377 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1378 st_shasta }, /* SuperTrak EX12350 */
1379 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1380 st_shasta }, /* SuperTrak EX4350 */
1381 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1382 st_shasta }, /* SuperTrak EX24350 */
1383
1384 /* st_vsc */
1385 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1386
1387 /* st_yosemite */
0f3f6ee6 1388 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
591a3a5f
EL		 1389
1390 /* st_seq */
1391 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
0f3f6ee6
EL		 1392
1393 /* st_yel */
1394 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1395 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
591a3a5f
EL		 1396 { } /* terminate list */
1397};
1398
1399static struct st_card_info stex_card_info[] = {
1400 /* st_shasta */
1401 {
1402 .max_id = 17,
1403 .max_lun = 8,
1404 .max_channel = 0,
1405 .rq_count = 32,
1406 .rq_size = 1048,
1407 .sts_count = 32,
0f3f6ee6
EL		 1408 .alloc_rq = stex_alloc_req,
1409 .map_sg = stex_map_sg,
1410 .send = stex_send_cmd,
591a3a5f
EL		 1411 },
1412
1413 /* st_vsc */
1414 {
1415 .max_id = 129,
1416 .max_lun = 1,
1417 .max_channel = 0,
1418 .rq_count = 32,
1419 .rq_size = 1048,
1420 .sts_count = 32,
0f3f6ee6
EL		 1421 .alloc_rq = stex_alloc_req,
1422 .map_sg = stex_map_sg,
1423 .send = stex_send_cmd,
591a3a5f
EL		 1424 },
1425
1426 /* st_yosemite */
1427 {
1428 .max_id = 2,
1429 .max_lun = 256,
1430 .max_channel = 0,
1431 .rq_count = 256,
1432 .rq_size = 1048,
1433 .sts_count = 256,
0f3f6ee6
EL		 1434 .alloc_rq = stex_alloc_req,
1435 .map_sg = stex_map_sg,
1436 .send = stex_send_cmd,
591a3a5f
EL		 1437 },
1438
1439 /* st_seq */
1440 {
1441 .max_id = 129,
1442 .max_lun = 1,
1443 .max_channel = 0,
1444 .rq_count = 32,
1445 .rq_size = 1048,
1446 .sts_count = 32,
0f3f6ee6
EL		 1447 .alloc_rq = stex_alloc_req,
1448 .map_sg = stex_map_sg,
1449 .send = stex_send_cmd,
1450 },
1451
1452 /* st_yel */
1453 {
1454 .max_id = 129,
1455 .max_lun = 256,
1456 .max_channel = 3,
1457 .rq_count = 801,
1458 .rq_size = 512,
1459 .sts_count = 801,
1460 .alloc_rq = stex_ss_alloc_req,
1461 .map_sg = stex_ss_map_sg,
1462 .send = stex_ss_send_cmd,
591a3a5f 1463 },
5a25ba16
JG		 1464};
1465
1466static int stex_set_dma_mask(struct pci_dev * pdev)
1467{
1468 int ret;
7cfe99a5 1469
cce9c8ae
EL		 1470 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1471 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
5a25ba16 1472 return 0;
284901a9 1473 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16 1474 if (!ret)
284901a9 1475 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16
JG		 1476 return ret;
1477}
1478
99946f81
EL		 1479static int stex_request_irq(struct st_hba *hba)
1480{
1481 struct pci_dev *pdev = hba->pdev;
1482 int status;
1483
1484 if (msi) {
1485 status = pci_enable_msi(pdev);
1486 if (status != 0)
1487 printk(KERN_ERR DRV_NAME
1488 "(%s): error %d setting up MSI\n",
1489 pci_name(pdev), status);
1490 else
1491 hba->msi_enabled = 1;
1492 } else
1493 hba->msi_enabled = 0;
1494
0f3f6ee6
EL		 1495 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1496 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
99946f81
EL		 1497
1498 if (status != 0) {
1499 if (hba->msi_enabled)
1500 pci_disable_msi(pdev);
1501 }
1502 return status;
1503}
1504
1505static void stex_free_irq(struct st_hba *hba)
1506{
1507 struct pci_dev *pdev = hba->pdev;
1508
1509 free_irq(pdev->irq, hba);
1510 if (hba->msi_enabled)
1511 pci_disable_msi(pdev);
1512}
1513
6f039790 1514static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
5a25ba16
JG		 1515{
1516 struct st_hba *hba;
1517 struct Scsi_Host *host;
591a3a5f 1518 const struct st_card_info *ci = NULL;
0f3f6ee6 1519 u32 sts_offset, cp_offset, scratch_offset;
5a25ba16
JG		 1520 int err;
1521
1522 err = pci_enable_device(pdev);
1523 if (err)
1524 return err;
1525
1526 pci_set_master(pdev);
1527
1528 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1529
1530 if (!host) {
1531 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1532 pci_name(pdev));
1533 err = -ENOMEM;
1534 goto out_disable;
1535 }
1536
1537 hba = (struct st_hba *)host->hostdata;
1538 memset(hba, 0, sizeof(struct st_hba));
1539
1540 err = pci_request_regions(pdev, DRV_NAME);
1541 if (err < 0) {
1542 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1543 pci_name(pdev));
1544 goto out_scsi_host_put;
1545 }
1546
25729a7f 1547 hba->mmio_base = pci_ioremap_bar(pdev, 0);
5a25ba16
JG		 1548 if ( !hba->mmio_base) {
1549 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1550 pci_name(pdev));
1551 err = -ENOMEM;
1552 goto out_release_regions;
1553 }
1554
1555 err = stex_set_dma_mask(pdev);
1556 if (err) {
1557 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1558 pci_name(pdev));
1559 goto out_iounmap;
1560 }
1561
94e9108b 1562 hba->cardtype = (unsigned int) id->driver_data;
591a3a5f 1563 ci = &stex_card_info[hba->cardtype];
1ec364e6
C		 1564 switch (id->subdevice) {
1565 case 0x4221:
1566 case 0x4222:
1567 case 0x4223:
1568 case 0x4224:
1569 case 0x4225:
1570 case 0x4226:
1571 case 0x4227:
1572 case 0x4261:
1573 case 0x4262:
1574 case 0x4263:
1575 case 0x4264:
1576 case 0x4265:
1577 break;
1578 default:
1579 if (hba->cardtype == st_yel)
1580 hba->supports_pm = 1;
1581 }
1582
0f3f6ee6
EL		 1583 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1584 if (hba->cardtype == st_yel)
1585 sts_offset += (ci->sts_count+1) * sizeof(u32);
591a3a5f
EL		 1586 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1587 hba->dma_size = cp_offset + sizeof(struct st_frame);
1588 if (hba->cardtype == st_seq ||
1589 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1590 hba->extra_offset = hba->dma_size;
1591 hba->dma_size += ST_ADDITIONAL_MEM;
1592 }
5a25ba16 1593 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
94e9108b 1594 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
5a25ba16 1595 if (!hba->dma_mem) {
cbacfb5f
EL		 1596 /* Retry minimum coherent mapping for st_seq and st_vsc */
1597 if (hba->cardtype == st_seq ||
1598 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1599 printk(KERN_WARNING DRV_NAME
1600 "(%s): allocating min buffer for controller\n",
1601 pci_name(pdev));
1602 hba->dma_size = hba->extra_offset
1603 + ST_ADDITIONAL_MEM_MIN;
1604 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1605 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1606 }
1607
1608 if (!hba->dma_mem) {
1609 err = -ENOMEM;
1610 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1611 pci_name(pdev));
1612 goto out_iounmap;
1613 }
5a25ba16
JG		 1614 }
1615
591a3a5f
EL		 1616 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1617 if (!hba->ccb) {
1618 err = -ENOMEM;
1619 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1620 pci_name(pdev));
1621 goto out_pci_free;
1622 }
1623
0f3f6ee6
EL		 1624 if (hba->cardtype == st_yel)
1625 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
591a3a5f
EL		 1626 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1627 hba->copy_buffer = hba->dma_mem + cp_offset;
1628 hba->rq_count = ci->rq_count;
1629 hba->rq_size = ci->rq_size;
1630 hba->sts_count = ci->sts_count;
0f3f6ee6
EL		 1631 hba->alloc_rq = ci->alloc_rq;
1632 hba->map_sg = ci->map_sg;
1633 hba->send = ci->send;
5a25ba16
JG		 1634 hba->mu_status = MU_STATE_STARTING;
1635
0f3f6ee6
EL		 1636 if (hba->cardtype == st_yel)
1637 host->sg_tablesize = 38;
1638 else
1639 host->sg_tablesize = 32;
591a3a5f
EL		 1640 host->can_queue = ci->rq_count;
1641 host->cmd_per_lun = ci->rq_count;
1642 host->max_id = ci->max_id;
1643 host->max_lun = ci->max_lun;
1644 host->max_channel = ci->max_channel;
5a25ba16
JG		 1645 host->unique_id = host->host_no;
1646 host->max_cmd_len = STEX_CDB_LENGTH;
1647
1648 hba->host = host;
1649 hba->pdev = pdev;
9eb46d2a
EL		 1650 init_waitqueue_head(&hba->reset_waitq);
1651
1652 snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1653 "stex_wq_%d", host->host_no);
1654 hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1655 if (!hba->work_q) {
1656 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1657 pci_name(pdev));
1658 err = -ENOMEM;
1659 goto out_ccb_free;
1660 }
1661 INIT_WORK(&hba->reset_work, stex_reset_work);
5a25ba16 1662
99946f81 1663 err = stex_request_irq(hba);
5a25ba16
JG		 1664 if (err) {
1665 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1666 pci_name(pdev));
9eb46d2a 1667 goto out_free_wq;
5a25ba16
JG		 1668 }
1669
1670 err = stex_handshake(hba);
1671 if (err)
1672 goto out_free_irq;
1673
1674 pci_set_drvdata(pdev, hba);
1675
1676 err = scsi_add_host(host, &pdev->dev);
1677 if (err) {
1678 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1679 pci_name(pdev));
1680 goto out_free_irq;
1681 }
1682
1683 scsi_scan_host(host);
1684
1685 return 0;
1686
1687out_free_irq:
99946f81 1688 stex_free_irq(hba);
9eb46d2a
EL		 1689out_free_wq:
1690 destroy_workqueue(hba->work_q);
591a3a5f
EL		 1691out_ccb_free:
1692 kfree(hba->ccb);
5a25ba16 1693out_pci_free:
94e9108b 1694 dma_free_coherent(&pdev->dev, hba->dma_size,
5a25ba16
JG		 1695 hba->dma_mem, hba->dma_handle);
1696out_iounmap:
1697 iounmap(hba->mmio_base);
1698out_release_regions:
1699 pci_release_regions(pdev);
1700out_scsi_host_put:
1701 scsi_host_put(host);
1702out_disable:
1703 pci_disable_device(pdev);
1704
1705 return err;
1706}
1707
1708static void stex_hba_stop(struct st_hba *hba)
1709{
1710 struct req_msg *req;
0f3f6ee6 1711 struct st_msg_header *msg_h;
5a25ba16
JG		 1712 unsigned long flags;
1713 unsigned long before;
cf355883 1714 u16 tag = 0;
5a25ba16
JG		 1715
1716 spin_lock_irqsave(hba->host->host_lock, flags);
0f3f6ee6
EL		 1717 req = hba->alloc_rq(hba);
1718 if (hba->cardtype == st_yel) {
1719 msg_h = (struct st_msg_header *)req - 1;
1720 memset(msg_h, 0, hba->rq_size);
1721 } else
1722 memset(req, 0, hba->rq_size);
5a25ba16 1723
0f3f6ee6 1724 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
fb4f66be
EL		 1725 req->cdb[0] = MGT_CMD;
1726 req->cdb[1] = MGT_CMD_SIGNATURE;
1727 req->cdb[2] = CTLR_CONFIG_CMD;
1728 req->cdb[3] = CTLR_SHUTDOWN;
1729 } else {
1730 req->cdb[0] = CONTROLLER_CMD;
1731 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1732 req->cdb[2] = CTLR_POWER_SAVING;
1733 }
5a25ba16
JG		 1734
1735 hba->ccb[tag].cmd = NULL;
1736 hba->ccb[tag].sg_count = 0;
1737 hba->ccb[tag].sense_bufflen = 0;
1738 hba->ccb[tag].sense_buffer = NULL;
f1498161 1739 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
5a25ba16 1740
0f3f6ee6 1741 hba->send(hba, req, tag);
5a25ba16
JG		 1742 spin_unlock_irqrestore(hba->host->host_lock, flags);
1743
cf355883
EL		 1744 before = jiffies;
1745 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
f1498161
EL		 1746 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1747 hba->ccb[tag].req_type = 0;
cf355883 1748 return;
f1498161
EL		 1749 }
1750 msleep(1);
cf355883 1751 }
5a25ba16
JG		 1752}
1753
1754static void stex_hba_free(struct st_hba *hba)
1755{
99946f81 1756 stex_free_irq(hba);
5a25ba16 1757
9eb46d2a
EL		 1758 destroy_workqueue(hba->work_q);
1759
5a25ba16
JG		 1760 iounmap(hba->mmio_base);
1761
1762 pci_release_regions(hba->pdev);
1763
591a3a5f
EL		 1764 kfree(hba->ccb);
1765
94e9108b 1766 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
5a25ba16
JG		 1767 hba->dma_mem, hba->dma_handle);
1768}
1769
1770static void stex_remove(struct pci_dev *pdev)
1771{
1772 struct st_hba *hba = pci_get_drvdata(pdev);
1773
1774 scsi_remove_host(hba->host);
1775
5a25ba16
JG		 1776 stex_hba_stop(hba);
1777
1778 stex_hba_free(hba);
1779
1780 scsi_host_put(hba->host);
1781
1782 pci_disable_device(pdev);
1783}
1784
1785static void stex_shutdown(struct pci_dev *pdev)
1786{
1787 struct st_hba *hba = pci_get_drvdata(pdev);
1788
1789 stex_hba_stop(hba);
1790}
1791
5a25ba16
JG		 1792MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1793
1794static struct pci_driver stex_pci_driver = {
1795 .name = DRV_NAME,
1796 .id_table = stex_pci_tbl,
1797 .probe = stex_probe,
6f039790 1798 .remove = stex_remove,
5a25ba16
JG		 1799 .shutdown = stex_shutdown,
1800};
1801
1802static int __init stex_init(void)
1803{
1804 printk(KERN_INFO DRV_NAME
1805 ": Promise SuperTrak EX Driver version: %s\n",
1806 ST_DRIVER_VERSION);
1807
1808 return pci_register_driver(&stex_pci_driver);
1809}
1810
1811static void __exit stex_exit(void)
1812{
1813 pci_unregister_driver(&stex_pci_driver);
1814}
1815
1816module_init(stex_init);
1817module_exit(stex_exit);
Linux 6.x block layer and io_uring tree(s)