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1da177e4 LT |
1 | /* |
2 | * sata_nv.c - NVIDIA nForce SATA | |
3 | * | |
4 | * Copyright 2004 NVIDIA Corp. All rights reserved. | |
5 | * Copyright 2004 Andrew Chew | |
6 | * | |
aa7e16d6 JG |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
1da177e4 | 21 | * |
af36d7f0 JG |
22 | * |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
25 | * | |
26 | * No hardware documentation available outside of NVIDIA. | |
27 | * This driver programs the NVIDIA SATA controller in a similar | |
28 | * fashion as with other PCI IDE BMDMA controllers, with a few | |
29 | * NV-specific details such as register offsets, SATA phy location, | |
30 | * hotplug info, etc. | |
31 | * | |
b887030a AC |
32 | * 0.10 |
33 | * - Fixed spurious interrupts issue seen with the Maxtor 6H500F0 500GB | |
34 | * drive. Also made the check_hotplug() callbacks return whether there | |
35 | * was a hotplug interrupt or not. This was not the source of the | |
36 | * spurious interrupts, but is the right thing to do anyway. | |
37 | * | |
e710245b AC |
38 | * 0.09 |
39 | * - Fixed bug introduced by 0.08's MCP51 and MCP55 support. | |
af36d7f0 | 40 | * |
541134cf DD |
41 | * 0.08 |
42 | * - Added support for MCP51 and MCP55. | |
43 | * | |
44 | * 0.07 | |
45 | * - Added support for RAID class code. | |
46 | * | |
1da177e4 LT |
47 | * 0.06 |
48 | * - Added generic SATA support by using a pci_device_id that filters on | |
49 | * the IDE storage class code. | |
50 | * | |
51 | * 0.03 | |
52 | * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using | |
53 | * mmio_base, which is only set for the CK804/MCP04 case. | |
54 | * | |
55 | * 0.02 | |
56 | * - Added support for CK804 SATA controller. | |
57 | * | |
58 | * 0.01 | |
59 | * - Initial revision. | |
60 | */ | |
61 | ||
62 | #include <linux/config.h> | |
63 | #include <linux/kernel.h> | |
64 | #include <linux/module.h> | |
65 | #include <linux/pci.h> | |
66 | #include <linux/init.h> | |
67 | #include <linux/blkdev.h> | |
68 | #include <linux/delay.h> | |
69 | #include <linux/interrupt.h> | |
a9524a76 | 70 | #include <linux/device.h> |
1da177e4 LT |
71 | #include <scsi/scsi_host.h> |
72 | #include <linux/libata.h> | |
73 | ||
74 | #define DRV_NAME "sata_nv" | |
541134cf | 75 | #define DRV_VERSION "0.8" |
1da177e4 LT |
76 | |
77 | #define NV_PORTS 2 | |
78 | #define NV_PIO_MASK 0x1f | |
79 | #define NV_MWDMA_MASK 0x07 | |
80 | #define NV_UDMA_MASK 0x7f | |
81 | #define NV_PORT0_SCR_REG_OFFSET 0x00 | |
82 | #define NV_PORT1_SCR_REG_OFFSET 0x40 | |
83 | ||
84 | #define NV_INT_STATUS 0x10 | |
85 | #define NV_INT_STATUS_CK804 0x440 | |
86 | #define NV_INT_STATUS_PDEV_INT 0x01 | |
87 | #define NV_INT_STATUS_PDEV_PM 0x02 | |
88 | #define NV_INT_STATUS_PDEV_ADDED 0x04 | |
89 | #define NV_INT_STATUS_PDEV_REMOVED 0x08 | |
90 | #define NV_INT_STATUS_SDEV_INT 0x10 | |
91 | #define NV_INT_STATUS_SDEV_PM 0x20 | |
92 | #define NV_INT_STATUS_SDEV_ADDED 0x40 | |
93 | #define NV_INT_STATUS_SDEV_REMOVED 0x80 | |
94 | #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \ | |
95 | NV_INT_STATUS_PDEV_REMOVED) | |
96 | #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \ | |
97 | NV_INT_STATUS_SDEV_REMOVED) | |
98 | #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \ | |
99 | NV_INT_STATUS_SDEV_HOTPLUG) | |
100 | ||
101 | #define NV_INT_ENABLE 0x11 | |
102 | #define NV_INT_ENABLE_CK804 0x441 | |
103 | #define NV_INT_ENABLE_PDEV_MASK 0x01 | |
104 | #define NV_INT_ENABLE_PDEV_PM 0x02 | |
105 | #define NV_INT_ENABLE_PDEV_ADDED 0x04 | |
106 | #define NV_INT_ENABLE_PDEV_REMOVED 0x08 | |
107 | #define NV_INT_ENABLE_SDEV_MASK 0x10 | |
108 | #define NV_INT_ENABLE_SDEV_PM 0x20 | |
109 | #define NV_INT_ENABLE_SDEV_ADDED 0x40 | |
110 | #define NV_INT_ENABLE_SDEV_REMOVED 0x80 | |
111 | #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \ | |
112 | NV_INT_ENABLE_PDEV_REMOVED) | |
113 | #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \ | |
114 | NV_INT_ENABLE_SDEV_REMOVED) | |
115 | #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \ | |
116 | NV_INT_ENABLE_SDEV_HOTPLUG) | |
117 | ||
118 | #define NV_INT_CONFIG 0x12 | |
119 | #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI | |
120 | ||
121 | // For PCI config register 20 | |
122 | #define NV_MCP_SATA_CFG_20 0x50 | |
123 | #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04 | |
124 | ||
125 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
126 | static irqreturn_t nv_interrupt (int irq, void *dev_instance, | |
127 | struct pt_regs *regs); | |
128 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
129 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
130 | static void nv_host_stop (struct ata_host_set *host_set); | |
131 | static void nv_enable_hotplug(struct ata_probe_ent *probe_ent); | |
132 | static void nv_disable_hotplug(struct ata_host_set *host_set); | |
b887030a | 133 | static int nv_check_hotplug(struct ata_host_set *host_set); |
1da177e4 LT |
134 | static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent); |
135 | static void nv_disable_hotplug_ck804(struct ata_host_set *host_set); | |
b887030a | 136 | static int nv_check_hotplug_ck804(struct ata_host_set *host_set); |
1da177e4 LT |
137 | |
138 | enum nv_host_type | |
139 | { | |
140 | GENERIC, | |
141 | NFORCE2, | |
142 | NFORCE3, | |
e710245b | 143 | CK804 |
1da177e4 LT |
144 | }; |
145 | ||
3b7d697d | 146 | static const struct pci_device_id nv_pci_tbl[] = { |
1da177e4 LT |
147 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, |
148 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 }, | |
149 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, | |
150 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 }, | |
151 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, | |
152 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 }, | |
153 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA, | |
154 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
155 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2, | |
156 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
157 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA, | |
158 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
159 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2, | |
160 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
541134cf | 161 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA, |
e710245b | 162 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
541134cf | 163 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2, |
e710245b | 164 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
541134cf | 165 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA, |
e710245b | 166 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
e86ee668 | 167 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2, |
e710245b | 168 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
1da177e4 LT |
169 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
170 | PCI_ANY_ID, PCI_ANY_ID, | |
171 | PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC }, | |
541134cf DD |
172 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
173 | PCI_ANY_ID, PCI_ANY_ID, | |
174 | PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC }, | |
1da177e4 LT |
175 | { 0, } /* terminate list */ |
176 | }; | |
177 | ||
178 | #define NV_HOST_FLAGS_SCR_MMIO 0x00000001 | |
179 | ||
180 | struct nv_host_desc | |
181 | { | |
182 | enum nv_host_type host_type; | |
183 | void (*enable_hotplug)(struct ata_probe_ent *probe_ent); | |
184 | void (*disable_hotplug)(struct ata_host_set *host_set); | |
b887030a | 185 | int (*check_hotplug)(struct ata_host_set *host_set); |
1da177e4 LT |
186 | |
187 | }; | |
188 | static struct nv_host_desc nv_device_tbl[] = { | |
189 | { | |
190 | .host_type = GENERIC, | |
191 | .enable_hotplug = NULL, | |
192 | .disable_hotplug= NULL, | |
193 | .check_hotplug = NULL, | |
194 | }, | |
195 | { | |
196 | .host_type = NFORCE2, | |
197 | .enable_hotplug = nv_enable_hotplug, | |
198 | .disable_hotplug= nv_disable_hotplug, | |
199 | .check_hotplug = nv_check_hotplug, | |
200 | }, | |
201 | { | |
202 | .host_type = NFORCE3, | |
203 | .enable_hotplug = nv_enable_hotplug, | |
204 | .disable_hotplug= nv_disable_hotplug, | |
205 | .check_hotplug = nv_check_hotplug, | |
206 | }, | |
207 | { .host_type = CK804, | |
208 | .enable_hotplug = nv_enable_hotplug_ck804, | |
209 | .disable_hotplug= nv_disable_hotplug_ck804, | |
210 | .check_hotplug = nv_check_hotplug_ck804, | |
211 | }, | |
212 | }; | |
213 | ||
214 | struct nv_host | |
215 | { | |
216 | struct nv_host_desc *host_desc; | |
217 | unsigned long host_flags; | |
218 | }; | |
219 | ||
220 | static struct pci_driver nv_pci_driver = { | |
221 | .name = DRV_NAME, | |
222 | .id_table = nv_pci_tbl, | |
223 | .probe = nv_init_one, | |
224 | .remove = ata_pci_remove_one, | |
225 | }; | |
226 | ||
193515d5 | 227 | static struct scsi_host_template nv_sht = { |
1da177e4 LT |
228 | .module = THIS_MODULE, |
229 | .name = DRV_NAME, | |
230 | .ioctl = ata_scsi_ioctl, | |
231 | .queuecommand = ata_scsi_queuecmd, | |
232 | .eh_strategy_handler = ata_scsi_error, | |
233 | .can_queue = ATA_DEF_QUEUE, | |
234 | .this_id = ATA_SHT_THIS_ID, | |
235 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
236 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
237 | .emulated = ATA_SHT_EMULATED, | |
238 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
239 | .proc_name = DRV_NAME, | |
240 | .dma_boundary = ATA_DMA_BOUNDARY, | |
241 | .slave_configure = ata_scsi_slave_config, | |
242 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
243 | }; |
244 | ||
057ace5e | 245 | static const struct ata_port_operations nv_ops = { |
1da177e4 LT |
246 | .port_disable = ata_port_disable, |
247 | .tf_load = ata_tf_load, | |
248 | .tf_read = ata_tf_read, | |
249 | .exec_command = ata_exec_command, | |
250 | .check_status = ata_check_status, | |
251 | .dev_select = ata_std_dev_select, | |
252 | .phy_reset = sata_phy_reset, | |
253 | .bmdma_setup = ata_bmdma_setup, | |
254 | .bmdma_start = ata_bmdma_start, | |
255 | .bmdma_stop = ata_bmdma_stop, | |
256 | .bmdma_status = ata_bmdma_status, | |
257 | .qc_prep = ata_qc_prep, | |
258 | .qc_issue = ata_qc_issue_prot, | |
259 | .eng_timeout = ata_eng_timeout, | |
260 | .irq_handler = nv_interrupt, | |
261 | .irq_clear = ata_bmdma_irq_clear, | |
262 | .scr_read = nv_scr_read, | |
263 | .scr_write = nv_scr_write, | |
264 | .port_start = ata_port_start, | |
265 | .port_stop = ata_port_stop, | |
266 | .host_stop = nv_host_stop, | |
267 | }; | |
268 | ||
269 | /* FIXME: The hardware provides the necessary SATA PHY controls | |
270 | * to support ATA_FLAG_SATA_RESET. However, it is currently | |
271 | * necessary to disable that flag, to solve misdetection problems. | |
272 | * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info. | |
273 | * | |
274 | * This problem really needs to be investigated further. But in the | |
275 | * meantime, we avoid ATA_FLAG_SATA_RESET to get people working. | |
276 | */ | |
277 | static struct ata_port_info nv_port_info = { | |
278 | .sht = &nv_sht, | |
279 | .host_flags = ATA_FLAG_SATA | | |
280 | /* ATA_FLAG_SATA_RESET | */ | |
281 | ATA_FLAG_SRST | | |
282 | ATA_FLAG_NO_LEGACY, | |
283 | .pio_mask = NV_PIO_MASK, | |
284 | .mwdma_mask = NV_MWDMA_MASK, | |
285 | .udma_mask = NV_UDMA_MASK, | |
286 | .port_ops = &nv_ops, | |
287 | }; | |
288 | ||
289 | MODULE_AUTHOR("NVIDIA"); | |
290 | MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); | |
291 | MODULE_LICENSE("GPL"); | |
292 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); | |
293 | MODULE_VERSION(DRV_VERSION); | |
294 | ||
295 | static irqreturn_t nv_interrupt (int irq, void *dev_instance, | |
296 | struct pt_regs *regs) | |
297 | { | |
298 | struct ata_host_set *host_set = dev_instance; | |
299 | struct nv_host *host = host_set->private_data; | |
300 | unsigned int i; | |
301 | unsigned int handled = 0; | |
302 | unsigned long flags; | |
303 | ||
304 | spin_lock_irqsave(&host_set->lock, flags); | |
305 | ||
306 | for (i = 0; i < host_set->n_ports; i++) { | |
307 | struct ata_port *ap; | |
308 | ||
309 | ap = host_set->ports[i]; | |
c1389503 TH |
310 | if (ap && |
311 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
312 | struct ata_queued_cmd *qc; |
313 | ||
314 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
315 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
316 | handled += ata_host_intr(ap, qc); | |
b887030a AC |
317 | else |
318 | // No request pending? Clear interrupt status | |
319 | // anyway, in case there's one pending. | |
320 | ap->ops->check_status(ap); | |
1da177e4 LT |
321 | } |
322 | ||
323 | } | |
324 | ||
325 | if (host->host_desc->check_hotplug) | |
b887030a | 326 | handled += host->host_desc->check_hotplug(host_set); |
1da177e4 LT |
327 | |
328 | spin_unlock_irqrestore(&host_set->lock, flags); | |
329 | ||
330 | return IRQ_RETVAL(handled); | |
331 | } | |
332 | ||
333 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
334 | { | |
335 | struct ata_host_set *host_set = ap->host_set; | |
336 | struct nv_host *host = host_set->private_data; | |
337 | ||
338 | if (sc_reg > SCR_CONTROL) | |
339 | return 0xffffffffU; | |
340 | ||
341 | if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) | |
9ee0c0a2 | 342 | return readl((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
343 | else |
344 | return inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
345 | } | |
346 | ||
347 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
348 | { | |
349 | struct ata_host_set *host_set = ap->host_set; | |
350 | struct nv_host *host = host_set->private_data; | |
351 | ||
352 | if (sc_reg > SCR_CONTROL) | |
353 | return; | |
354 | ||
355 | if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) | |
9ee0c0a2 | 356 | writel(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
357 | else |
358 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); | |
359 | } | |
360 | ||
361 | static void nv_host_stop (struct ata_host_set *host_set) | |
362 | { | |
363 | struct nv_host *host = host_set->private_data; | |
374b1873 | 364 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
1da177e4 LT |
365 | |
366 | // Disable hotplug event interrupts. | |
367 | if (host->host_desc->disable_hotplug) | |
368 | host->host_desc->disable_hotplug(host_set); | |
369 | ||
370 | kfree(host); | |
aa8f0dc6 | 371 | |
374b1873 JG |
372 | if (host_set->mmio_base) |
373 | pci_iounmap(pdev, host_set->mmio_base); | |
1da177e4 LT |
374 | } |
375 | ||
376 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
377 | { | |
378 | static int printed_version = 0; | |
379 | struct nv_host *host; | |
380 | struct ata_port_info *ppi; | |
381 | struct ata_probe_ent *probe_ent; | |
382 | int pci_dev_busy = 0; | |
383 | int rc; | |
384 | u32 bar; | |
385 | ||
386 | // Make sure this is a SATA controller by counting the number of bars | |
387 | // (NVIDIA SATA controllers will always have six bars). Otherwise, | |
388 | // it's an IDE controller and we ignore it. | |
389 | for (bar=0; bar<6; bar++) | |
390 | if (pci_resource_start(pdev, bar) == 0) | |
391 | return -ENODEV; | |
392 | ||
393 | if (!printed_version++) | |
a9524a76 | 394 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
395 | |
396 | rc = pci_enable_device(pdev); | |
397 | if (rc) | |
398 | goto err_out; | |
399 | ||
400 | rc = pci_request_regions(pdev, DRV_NAME); | |
401 | if (rc) { | |
402 | pci_dev_busy = 1; | |
403 | goto err_out_disable; | |
404 | } | |
405 | ||
406 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
407 | if (rc) | |
408 | goto err_out_regions; | |
409 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
410 | if (rc) | |
411 | goto err_out_regions; | |
412 | ||
413 | rc = -ENOMEM; | |
414 | ||
415 | ppi = &nv_port_info; | |
47a86593 | 416 | probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
1da177e4 LT |
417 | if (!probe_ent) |
418 | goto err_out_regions; | |
419 | ||
420 | host = kmalloc(sizeof(struct nv_host), GFP_KERNEL); | |
421 | if (!host) | |
422 | goto err_out_free_ent; | |
423 | ||
424 | memset(host, 0, sizeof(struct nv_host)); | |
425 | host->host_desc = &nv_device_tbl[ent->driver_data]; | |
426 | ||
427 | probe_ent->private_data = host; | |
428 | ||
429 | if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM) | |
430 | host->host_flags |= NV_HOST_FLAGS_SCR_MMIO; | |
431 | ||
432 | if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) { | |
433 | unsigned long base; | |
434 | ||
374b1873 | 435 | probe_ent->mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
436 | if (probe_ent->mmio_base == NULL) { |
437 | rc = -EIO; | |
438 | goto err_out_free_host; | |
439 | } | |
440 | ||
441 | base = (unsigned long)probe_ent->mmio_base; | |
442 | ||
443 | probe_ent->port[0].scr_addr = | |
444 | base + NV_PORT0_SCR_REG_OFFSET; | |
445 | probe_ent->port[1].scr_addr = | |
446 | base + NV_PORT1_SCR_REG_OFFSET; | |
447 | } else { | |
448 | ||
449 | probe_ent->port[0].scr_addr = | |
450 | pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET; | |
451 | probe_ent->port[1].scr_addr = | |
452 | pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET; | |
453 | } | |
454 | ||
455 | pci_set_master(pdev); | |
456 | ||
457 | rc = ata_device_add(probe_ent); | |
458 | if (rc != NV_PORTS) | |
459 | goto err_out_iounmap; | |
460 | ||
461 | // Enable hotplug event interrupts. | |
462 | if (host->host_desc->enable_hotplug) | |
463 | host->host_desc->enable_hotplug(probe_ent); | |
464 | ||
465 | kfree(probe_ent); | |
466 | ||
467 | return 0; | |
468 | ||
469 | err_out_iounmap: | |
470 | if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) | |
374b1873 | 471 | pci_iounmap(pdev, probe_ent->mmio_base); |
1da177e4 LT |
472 | err_out_free_host: |
473 | kfree(host); | |
474 | err_out_free_ent: | |
475 | kfree(probe_ent); | |
476 | err_out_regions: | |
477 | pci_release_regions(pdev); | |
478 | err_out_disable: | |
479 | if (!pci_dev_busy) | |
480 | pci_disable_device(pdev); | |
481 | err_out: | |
482 | return rc; | |
483 | } | |
484 | ||
485 | static void nv_enable_hotplug(struct ata_probe_ent *probe_ent) | |
486 | { | |
487 | u8 intr_mask; | |
488 | ||
489 | outb(NV_INT_STATUS_HOTPLUG, | |
490 | probe_ent->port[0].scr_addr + NV_INT_STATUS); | |
491 | ||
492 | intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE); | |
493 | intr_mask |= NV_INT_ENABLE_HOTPLUG; | |
494 | ||
495 | outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE); | |
496 | } | |
497 | ||
498 | static void nv_disable_hotplug(struct ata_host_set *host_set) | |
499 | { | |
500 | u8 intr_mask; | |
501 | ||
502 | intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE); | |
503 | ||
504 | intr_mask &= ~(NV_INT_ENABLE_HOTPLUG); | |
505 | ||
506 | outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE); | |
507 | } | |
508 | ||
b887030a | 509 | static int nv_check_hotplug(struct ata_host_set *host_set) |
1da177e4 LT |
510 | { |
511 | u8 intr_status; | |
512 | ||
513 | intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); | |
514 | ||
515 | // Clear interrupt status. | |
516 | outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); | |
517 | ||
518 | if (intr_status & NV_INT_STATUS_HOTPLUG) { | |
519 | if (intr_status & NV_INT_STATUS_PDEV_ADDED) | |
520 | printk(KERN_WARNING "nv_sata: " | |
521 | "Primary device added\n"); | |
522 | ||
523 | if (intr_status & NV_INT_STATUS_PDEV_REMOVED) | |
524 | printk(KERN_WARNING "nv_sata: " | |
525 | "Primary device removed\n"); | |
526 | ||
527 | if (intr_status & NV_INT_STATUS_SDEV_ADDED) | |
528 | printk(KERN_WARNING "nv_sata: " | |
529 | "Secondary device added\n"); | |
530 | ||
531 | if (intr_status & NV_INT_STATUS_SDEV_REMOVED) | |
532 | printk(KERN_WARNING "nv_sata: " | |
533 | "Secondary device removed\n"); | |
b887030a AC |
534 | |
535 | return 1; | |
1da177e4 | 536 | } |
b887030a AC |
537 | |
538 | return 0; | |
1da177e4 LT |
539 | } |
540 | ||
541 | static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent) | |
542 | { | |
543 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
544 | u8 intr_mask; | |
545 | u8 regval; | |
546 | ||
547 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
548 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
549 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
550 | ||
551 | writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804); | |
552 | ||
553 | intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804); | |
554 | intr_mask |= NV_INT_ENABLE_HOTPLUG; | |
555 | ||
556 | writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804); | |
557 | } | |
558 | ||
559 | static void nv_disable_hotplug_ck804(struct ata_host_set *host_set) | |
560 | { | |
561 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | |
562 | u8 intr_mask; | |
563 | u8 regval; | |
564 | ||
565 | intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804); | |
566 | ||
567 | intr_mask &= ~(NV_INT_ENABLE_HOTPLUG); | |
568 | ||
569 | writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804); | |
570 | ||
571 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
572 | regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
573 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
574 | } | |
575 | ||
b887030a | 576 | static int nv_check_hotplug_ck804(struct ata_host_set *host_set) |
1da177e4 LT |
577 | { |
578 | u8 intr_status; | |
579 | ||
580 | intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804); | |
581 | ||
582 | // Clear interrupt status. | |
583 | writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804); | |
584 | ||
585 | if (intr_status & NV_INT_STATUS_HOTPLUG) { | |
586 | if (intr_status & NV_INT_STATUS_PDEV_ADDED) | |
587 | printk(KERN_WARNING "nv_sata: " | |
588 | "Primary device added\n"); | |
589 | ||
590 | if (intr_status & NV_INT_STATUS_PDEV_REMOVED) | |
591 | printk(KERN_WARNING "nv_sata: " | |
592 | "Primary device removed\n"); | |
593 | ||
594 | if (intr_status & NV_INT_STATUS_SDEV_ADDED) | |
595 | printk(KERN_WARNING "nv_sata: " | |
596 | "Secondary device added\n"); | |
597 | ||
598 | if (intr_status & NV_INT_STATUS_SDEV_REMOVED) | |
599 | printk(KERN_WARNING "nv_sata: " | |
600 | "Secondary device removed\n"); | |
b887030a AC |
601 | |
602 | return 1; | |
1da177e4 | 603 | } |
b887030a AC |
604 | |
605 | return 0; | |
1da177e4 LT |
606 | } |
607 | ||
608 | static int __init nv_init(void) | |
609 | { | |
610 | return pci_module_init(&nv_pci_driver); | |
611 | } | |
612 | ||
613 | static void __exit nv_exit(void) | |
614 | { | |
615 | pci_unregister_driver(&nv_pci_driver); | |
616 | } | |
617 | ||
618 | module_init(nv_init); | |
619 | module_exit(nv_exit); |