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qla4xxx: Added new opcodes for 84XX Minidump template
[linux-2.6-block.git] / drivers / scsi / qla4xxx / ql4_nx.c
CommitLineData
f4f5df23
VC		 1/*
2 * QLogic iSCSI HBA Driver
4a4f51e9 3 * Copyright (c) 2003-2013 QLogic Corporation
f4f5df23
VC		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7#include <linux/delay.h>
a6751ccb 8#include <linux/io.h>
f4f5df23 9#include <linux/pci.h>
068237c8 10#include <linux/ratelimit.h>
f4f5df23
VC		 11#include "ql4_def.h"
12#include "ql4_glbl.h"
6e7b4292 13#include "ql4_inline.h"
f4f5df23 14
797a796a
HM		 15#include <asm-generic/io-64-nonatomic-lo-hi.h>
16
b1829789 17#define TIMEOUT_100_MS 100
f4f5df23
VC		 18#define MASK(n) DMA_BIT_MASK(n)
19#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
20#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
21#define MS_WIN(addr) (addr & 0x0ffc0000)
22#define QLA82XX_PCI_MN_2M (0)
23#define QLA82XX_PCI_MS_2M (0x80000)
24#define QLA82XX_PCI_OCM0_2M (0xc0000)
25#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
26#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
27
28/* CRB window related */
29#define CRB_BLK(off) ((off >> 20) & 0x3f)
30#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
31#define CRB_WINDOW_2M (0x130060)
7664a1fd 32#define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
f4f5df23
VC		 33 ((off) & 0xf0000))
34#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
35#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
36#define CRB_INDIRECT_2M (0x1e0000UL)
37
38static inline void __iomem *
39qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
40{
41 if ((off < ha->first_page_group_end) &&
42 (off >= ha->first_page_group_start))
43 return (void __iomem *)(ha->nx_pcibase + off);
44
45 return NULL;
46}
47
48#define MAX_CRB_XFORM 60
49static unsigned long crb_addr_xform[MAX_CRB_XFORM];
50static int qla4_8xxx_crb_table_initialized;
51
52#define qla4_8xxx_crb_addr_transform(name) \
53 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
54 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
55static void
f8086f4f 56qla4_82xx_crb_addr_transform_setup(void)
f4f5df23
VC		 57{
58 qla4_8xxx_crb_addr_transform(XDMA);
59 qla4_8xxx_crb_addr_transform(TIMR);
60 qla4_8xxx_crb_addr_transform(SRE);
61 qla4_8xxx_crb_addr_transform(SQN3);
62 qla4_8xxx_crb_addr_transform(SQN2);
63 qla4_8xxx_crb_addr_transform(SQN1);
64 qla4_8xxx_crb_addr_transform(SQN0);
65 qla4_8xxx_crb_addr_transform(SQS3);
66 qla4_8xxx_crb_addr_transform(SQS2);
67 qla4_8xxx_crb_addr_transform(SQS1);
68 qla4_8xxx_crb_addr_transform(SQS0);
69 qla4_8xxx_crb_addr_transform(RPMX7);
70 qla4_8xxx_crb_addr_transform(RPMX6);
71 qla4_8xxx_crb_addr_transform(RPMX5);
72 qla4_8xxx_crb_addr_transform(RPMX4);
73 qla4_8xxx_crb_addr_transform(RPMX3);
74 qla4_8xxx_crb_addr_transform(RPMX2);
75 qla4_8xxx_crb_addr_transform(RPMX1);
76 qla4_8xxx_crb_addr_transform(RPMX0);
77 qla4_8xxx_crb_addr_transform(ROMUSB);
78 qla4_8xxx_crb_addr_transform(SN);
79 qla4_8xxx_crb_addr_transform(QMN);
80 qla4_8xxx_crb_addr_transform(QMS);
81 qla4_8xxx_crb_addr_transform(PGNI);
82 qla4_8xxx_crb_addr_transform(PGND);
83 qla4_8xxx_crb_addr_transform(PGN3);
84 qla4_8xxx_crb_addr_transform(PGN2);
85 qla4_8xxx_crb_addr_transform(PGN1);
86 qla4_8xxx_crb_addr_transform(PGN0);
87 qla4_8xxx_crb_addr_transform(PGSI);
88 qla4_8xxx_crb_addr_transform(PGSD);
89 qla4_8xxx_crb_addr_transform(PGS3);
90 qla4_8xxx_crb_addr_transform(PGS2);
91 qla4_8xxx_crb_addr_transform(PGS1);
92 qla4_8xxx_crb_addr_transform(PGS0);
93 qla4_8xxx_crb_addr_transform(PS);
94 qla4_8xxx_crb_addr_transform(PH);
95 qla4_8xxx_crb_addr_transform(NIU);
96 qla4_8xxx_crb_addr_transform(I2Q);
97 qla4_8xxx_crb_addr_transform(EG);
98 qla4_8xxx_crb_addr_transform(MN);
99 qla4_8xxx_crb_addr_transform(MS);
100 qla4_8xxx_crb_addr_transform(CAS2);
101 qla4_8xxx_crb_addr_transform(CAS1);
102 qla4_8xxx_crb_addr_transform(CAS0);
103 qla4_8xxx_crb_addr_transform(CAM);
104 qla4_8xxx_crb_addr_transform(C2C1);
105 qla4_8xxx_crb_addr_transform(C2C0);
106 qla4_8xxx_crb_addr_transform(SMB);
107 qla4_8xxx_crb_addr_transform(OCM0);
108 qla4_8xxx_crb_addr_transform(I2C0);
109
110 qla4_8xxx_crb_table_initialized = 1;
111}
112
113static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
114 {{{0, 0, 0, 0} } }, /* 0: PCI */
115 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
116 {1, 0x0110000, 0x0120000, 0x130000},
117 {1, 0x0120000, 0x0122000, 0x124000},
118 {1, 0x0130000, 0x0132000, 0x126000},
119 {1, 0x0140000, 0x0142000, 0x128000},
120 {1, 0x0150000, 0x0152000, 0x12a000},
121 {1, 0x0160000, 0x0170000, 0x110000},
122 {1, 0x0170000, 0x0172000, 0x12e000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x01e0000, 0x01e0800, 0x122000},
130 {0, 0x0000000, 0x0000000, 0x000000} } },
131 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
132 {{{0, 0, 0, 0} } }, /* 3: */
133 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
134 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
135 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
136 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
137 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {1, 0x08f0000, 0x08f2000, 0x172000} } },
153 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {1, 0x09f0000, 0x09f2000, 0x176000} } },
169 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
185 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {0, 0x0000000, 0x0000000, 0x000000},
199 {0, 0x0000000, 0x0000000, 0x000000},
200 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
201 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
202 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
203 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
204 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
205 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
206 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
207 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
208 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
209 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
210 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
211 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
212 {{{0, 0, 0, 0} } }, /* 23: */
213 {{{0, 0, 0, 0} } }, /* 24: */
214 {{{0, 0, 0, 0} } }, /* 25: */
215 {{{0, 0, 0, 0} } }, /* 26: */
216 {{{0, 0, 0, 0} } }, /* 27: */
217 {{{0, 0, 0, 0} } }, /* 28: */
218 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
219 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
220 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
221 {{{0} } }, /* 32: PCI */
222 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
223 {1, 0x2110000, 0x2120000, 0x130000},
224 {1, 0x2120000, 0x2122000, 0x124000},
225 {1, 0x2130000, 0x2132000, 0x126000},
226 {1, 0x2140000, 0x2142000, 0x128000},
227 {1, 0x2150000, 0x2152000, 0x12a000},
228 {1, 0x2160000, 0x2170000, 0x110000},
229 {1, 0x2170000, 0x2172000, 0x12e000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000},
236 {0, 0x0000000, 0x0000000, 0x000000},
237 {0, 0x0000000, 0x0000000, 0x000000} } },
238 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
239 {{{0} } }, /* 35: */
240 {{{0} } }, /* 36: */
241 {{{0} } }, /* 37: */
242 {{{0} } }, /* 38: */
243 {{{0} } }, /* 39: */
244 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
245 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
246 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
247 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
248 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
249 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
250 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
251 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
252 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
253 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
254 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
255 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
256 {{{0} } }, /* 52: */
257 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
258 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
259 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
260 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
261 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
262 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
263 {{{0} } }, /* 59: I2C0 */
264 {{{0} } }, /* 60: I2C1 */
265 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
266 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
267 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
268};
269
270/*
271 * top 12 bits of crb internal address (hub, agent)
272 */
7664a1fd 273static unsigned qla4_82xx_crb_hub_agt[64] = {
f4f5df23
VC		 274 0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
278 0,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
304 0,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
306 0,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
309 0,
310 0,
311 0,
312 0,
313 0,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
315 0,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
326 0,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
331 0,
332 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
334 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
335 0,
336 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
337 0,
338};
339
340/* Device states */
341static char *qdev_state[] = {
342 "Unknown",
343 "Cold",
344 "Initializing",
345 "Ready",
346 "Need Reset",
347 "Need Quiescent",
348 "Failed",
349 "Quiescent",
350};
351
352/*
353 * In: 'off' is offset from CRB space in 128M pci map
354 * Out: 'off' is 2M pci map addr
355 * side effect: lock crb window
356 */
357static void
f8086f4f 358qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
f4f5df23
VC		 359{
360 u32 win_read;
361
362 ha->crb_win = CRB_HI(*off);
363 writel(ha->crb_win,
364 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
365
366 /* Read back value to make sure write has gone through before trying
367 * to use it. */
368 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
369 if (win_read != ha->crb_win) {
370 DEBUG2(ql4_printk(KERN_INFO, ha,
371 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
372 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
373 }
374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
375}
376
377void
f8086f4f 378qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
f4f5df23
VC		 379{
380 unsigned long flags = 0;
381 int rv;
382
f8086f4f 383 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
f4f5df23
VC		 384
385 BUG_ON(rv == -1);
386
387 if (rv == 1) {
388 write_lock_irqsave(&ha->hw_lock, flags);
f8086f4f
VC		 389 qla4_82xx_crb_win_lock(ha);
390 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
f4f5df23
VC		 391 }
392
393 writel(data, (void __iomem *)off);
394
395 if (rv == 1) {
f8086f4f 396 qla4_82xx_crb_win_unlock(ha);
f4f5df23
VC		 397 write_unlock_irqrestore(&ha->hw_lock, flags);
398 }
399}
400
33693c7a 401uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
f4f5df23
VC		 402{
403 unsigned long flags = 0;
404 int rv;
405 u32 data;
406
f8086f4f 407 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
f4f5df23
VC		 408
409 BUG_ON(rv == -1);
410
411 if (rv == 1) {
412 write_lock_irqsave(&ha->hw_lock, flags);
f8086f4f
VC		 413 qla4_82xx_crb_win_lock(ha);
414 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
f4f5df23
VC		 415 }
416 data = readl((void __iomem *)off);
417
418 if (rv == 1) {
f8086f4f 419 qla4_82xx_crb_win_unlock(ha);
f4f5df23
VC		 420 write_unlock_irqrestore(&ha->hw_lock, flags);
421 }
422 return data;
423}
424
068237c8 425/* Minidump related functions */
33693c7a 426int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
068237c8 427{
33693c7a
VC		 428 uint32_t win_read, off_value;
429 int rval = QLA_SUCCESS;
068237c8
TP		 430
431 off_value = off & 0xFFFF0000;
432 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
433
33693c7a
VC		 434 /*
435 * Read back value to make sure write has gone through before trying
068237c8
TP		 436 * to use it.
437 */
438 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
439 if (win_read != off_value) {
440 DEBUG2(ql4_printk(KERN_INFO, ha,
441 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
33693c7a
VC		 442 __func__, off_value, win_read, off));
443 rval = QLA_ERROR;
444 } else {
445 off_value = off & 0x0000FFFF;
446 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
447 ha->nx_pcibase));
068237c8 448 }
33693c7a
VC		 449 return rval;
450}
068237c8 451
33693c7a
VC		 452int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
453{
454 uint32_t win_read, off_value;
455 int rval = QLA_SUCCESS;
068237c8 456
33693c7a
VC		 457 off_value = off & 0xFFFF0000;
458 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
068237c8 459
33693c7a
VC		 460 /* Read back value to make sure write has gone through before trying
461 * to use it.
462 */
463 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
464 if (win_read != off_value) {
465 DEBUG2(ql4_printk(KERN_INFO, ha,
466 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
467 __func__, off_value, win_read, off));
468 rval = QLA_ERROR;
469 } else {
470 off_value = off & 0x0000FFFF;
068237c8
TP		 471 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
472 ha->nx_pcibase));
33693c7a 473 }
068237c8
TP		 474 return rval;
475}
476
f4f5df23
VC		 477#define CRB_WIN_LOCK_TIMEOUT 100000000
478
f8086f4f 479int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 480{
481 int i;
482 int done = 0, timeout = 0;
483
484 while (!done) {
485 /* acquire semaphore3 from PCI HW block */
f8086f4f 486 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
f4f5df23
VC		 487 if (done == 1)
488 break;
489 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
490 return -1;
491
492 timeout++;
493
494 /* Yield CPU */
495 if (!in_interrupt())
496 schedule();
497 else {
498 for (i = 0; i < 20; i++)
499 cpu_relax(); /*This a nop instr on i386*/
500 }
501 }
f8086f4f 502 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
f4f5df23
VC		 503 return 0;
504}
505
f8086f4f 506void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
f4f5df23 507{
f8086f4f 508 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
f4f5df23
VC		 509}
510
511#define IDC_LOCK_TIMEOUT 100000000
512
513/**
f8086f4f 514 * qla4_82xx_idc_lock - hw_lock
f4f5df23
VC		 515 * @ha: pointer to adapter structure
516 *
517 * General purpose lock used to synchronize access to
518 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
519 **/
f8086f4f 520int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 521{
522 int i;
523 int done = 0, timeout = 0;
524
525 while (!done) {
526 /* acquire semaphore5 from PCI HW block */
f8086f4f 527 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
f4f5df23
VC		 528 if (done == 1)
529 break;
530 if (timeout >= IDC_LOCK_TIMEOUT)
531 return -1;
532
533 timeout++;
534
535 /* Yield CPU */
536 if (!in_interrupt())
537 schedule();
538 else {
539 for (i = 0; i < 20; i++)
540 cpu_relax(); /*This a nop instr on i386*/
541 }
542 }
543 return 0;
544}
545
f8086f4f 546void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
f4f5df23 547{
f8086f4f 548 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
f4f5df23
VC		 549}
550
551int
f8086f4f 552qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
f4f5df23
VC		 553{
554 struct crb_128M_2M_sub_block_map *m;
555
556 if (*off >= QLA82XX_CRB_MAX)
557 return -1;
558
559 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
560 *off = (*off - QLA82XX_PCI_CAMQM) +
561 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
562 return 0;
563 }
564
565 if (*off < QLA82XX_PCI_CRBSPACE)
566 return -1;
567
568 *off -= QLA82XX_PCI_CRBSPACE;
569 /*
570 * Try direct map
571 */
572
573 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
574
575 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
576 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
577 return 0;
578 }
579
580 /*
581 * Not in direct map, use crb window
582 */
583 return 1;
584}
585
f4f5df23
VC		 586/*
587* check memory access boundary.
588* used by test agent. support ddr access only for now
589*/
590static unsigned long
f8086f4f 591qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
f4f5df23
VC		 592 unsigned long long addr, int size)
593{
de8c72da
VC		 594 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
595 QLA8XXX_ADDR_DDR_NET_MAX) ||
596 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
597 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
f4f5df23
VC		 598 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
599 return 0;
600 }
601 return 1;
602}
603
7664a1fd 604static int qla4_82xx_pci_set_window_warning_count;
f4f5df23
VC		 605
606static unsigned long
f8086f4f 607qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
f4f5df23
VC		 608{
609 int window;
610 u32 win_read;
611
de8c72da
VC		 612 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
613 QLA8XXX_ADDR_DDR_NET_MAX)) {
f4f5df23
VC		 614 /* DDR network side */
615 window = MN_WIN(addr);
616 ha->ddr_mn_window = window;
f8086f4f 617 qla4_82xx_wr_32(ha, ha->mn_win_crb |
f4f5df23 618 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 619 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
f4f5df23
VC		 620 QLA82XX_PCI_CRBSPACE);
621 if ((win_read << 17) != window) {
622 ql4_printk(KERN_WARNING, ha,
623 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
624 __func__, window, win_read);
625 }
626 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
de8c72da
VC		 627 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
628 QLA8XXX_ADDR_OCM0_MAX)) {
f4f5df23
VC		 629 unsigned int temp1;
630 /* if bits 19:18&17:11 are on */
631 if ((addr & 0x00ff800) == 0xff800) {
632 printk("%s: QM access not handled.\n", __func__);
633 addr = -1UL;
634 }
635
636 window = OCM_WIN(addr);
637 ha->ddr_mn_window = window;
f8086f4f 638 qla4_82xx_wr_32(ha, ha->mn_win_crb |
f4f5df23 639 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 640 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
f4f5df23
VC		 641 QLA82XX_PCI_CRBSPACE);
642 temp1 = ((window & 0x1FF) << 7) |
643 ((window & 0x0FFFE0000) >> 17);
644 if (win_read != temp1) {
645 printk("%s: Written OCMwin (0x%x) != Read"
646 " OCMwin (0x%x)\n", __func__, temp1, win_read);
647 }
648 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
649
de8c72da 650 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
f4f5df23
VC		 651 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
652 /* QDR network side */
653 window = MS_WIN(addr);
654 ha->qdr_sn_window = window;
f8086f4f 655 qla4_82xx_wr_32(ha, ha->ms_win_crb |
f4f5df23 656 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 657 win_read = qla4_82xx_rd_32(ha,
f4f5df23
VC		 658 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
659 if (win_read != window) {
660 printk("%s: Written MSwin (0x%x) != Read "
661 "MSwin (0x%x)\n", __func__, window, win_read);
662 }
663 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
664
665 } else {
666 /*
667 * peg gdb frequently accesses memory that doesn't exist,
668 * this limits the chit chat so debugging isn't slowed down.
669 */
7664a1fd
VC		 670 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
671 (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
f4f5df23
VC		 672 printk("%s: Warning:%s Unknown address range!\n",
673 __func__, DRIVER_NAME);
674 }
675 addr = -1UL;
676 }
677 return addr;
678}
679
680/* check if address is in the same windows as the previous access */
f8086f4f 681static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
f4f5df23
VC		 682 unsigned long long addr)
683{
684 int window;
685 unsigned long long qdr_max;
686
687 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
688
de8c72da
VC		 689 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
690 QLA8XXX_ADDR_DDR_NET_MAX)) {
f4f5df23
VC		 691 /* DDR network side */
692 BUG(); /* MN access can not come here */
de8c72da
VC		 693 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
694 QLA8XXX_ADDR_OCM0_MAX)) {
f4f5df23 695 return 1;
de8c72da
VC		 696 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
697 QLA8XXX_ADDR_OCM1_MAX)) {
f4f5df23 698 return 1;
de8c72da 699 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
f4f5df23
VC		 700 qdr_max)) {
701 /* QDR network side */
de8c72da 702 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
f4f5df23
VC		 703 if (ha->qdr_sn_window == window)
704 return 1;
705 }
706
707 return 0;
708}
709
f8086f4f 710static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
f4f5df23
VC		 711 u64 off, void *data, int size)
712{
713 unsigned long flags;
714 void __iomem *addr;
715 int ret = 0;
716 u64 start;
717 void __iomem *mem_ptr = NULL;
718 unsigned long mem_base;
719 unsigned long mem_page;
720
721 write_lock_irqsave(&ha->hw_lock, flags);
722
723 /*
724 * If attempting to access unknown address or straddle hw windows,
725 * do not access.
726 */
f8086f4f 727 start = qla4_82xx_pci_set_window(ha, off);
f4f5df23 728 if ((start == -1UL) ||
f8086f4f 729 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
f4f5df23
VC		 730 write_unlock_irqrestore(&ha->hw_lock, flags);
731 printk(KERN_ERR"%s out of bound pci memory access. "
732 "offset is 0x%llx\n", DRIVER_NAME, off);
733 return -1;
734 }
735
736 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
737 if (!addr) {
738 write_unlock_irqrestore(&ha->hw_lock, flags);
739 mem_base = pci_resource_start(ha->pdev, 0);
740 mem_page = start & PAGE_MASK;
741 /* Map two pages whenever user tries to access addresses in two
742 consecutive pages.
743 */
744 if (mem_page != ((start + size - 1) & PAGE_MASK))
745 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
746 else
747 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
748
749 if (mem_ptr == NULL) {
750 *(u8 *)data = 0;
751 return -1;
752 }
753 addr = mem_ptr;
754 addr += start & (PAGE_SIZE - 1);
755 write_lock_irqsave(&ha->hw_lock, flags);
756 }
757
758 switch (size) {
759 case 1:
760 *(u8 *)data = readb(addr);
761 break;
762 case 2:
763 *(u16 *)data = readw(addr);
764 break;
765 case 4:
766 *(u32 *)data = readl(addr);
767 break;
768 case 8:
769 *(u64 *)data = readq(addr);
770 break;
771 default:
772 ret = -1;
773 break;
774 }
775 write_unlock_irqrestore(&ha->hw_lock, flags);
776
777 if (mem_ptr)
778 iounmap(mem_ptr);
779 return ret;
780}
781
782static int
f8086f4f 783qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
f4f5df23
VC		 784 void *data, int size)
785{
786 unsigned long flags;
787 void __iomem *addr;
788 int ret = 0;
789 u64 start;
790 void __iomem *mem_ptr = NULL;
791 unsigned long mem_base;
792 unsigned long mem_page;
793
794 write_lock_irqsave(&ha->hw_lock, flags);
795
796 /*
797 * If attempting to access unknown address or straddle hw windows,
798 * do not access.
799 */
f8086f4f 800 start = qla4_82xx_pci_set_window(ha, off);
f4f5df23 801 if ((start == -1UL) ||
f8086f4f 802 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
f4f5df23
VC		 803 write_unlock_irqrestore(&ha->hw_lock, flags);
804 printk(KERN_ERR"%s out of bound pci memory access. "
805 "offset is 0x%llx\n", DRIVER_NAME, off);
806 return -1;
807 }
808
809 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
810 if (!addr) {
811 write_unlock_irqrestore(&ha->hw_lock, flags);
812 mem_base = pci_resource_start(ha->pdev, 0);
813 mem_page = start & PAGE_MASK;
814 /* Map two pages whenever user tries to access addresses in two
815 consecutive pages.
816 */
817 if (mem_page != ((start + size - 1) & PAGE_MASK))
818 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
819 else
820 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
821 if (mem_ptr == NULL)
822 return -1;
823
824 addr = mem_ptr;
825 addr += start & (PAGE_SIZE - 1);
826 write_lock_irqsave(&ha->hw_lock, flags);
827 }
828
829 switch (size) {
830 case 1:
831 writeb(*(u8 *)data, addr);
832 break;
833 case 2:
834 writew(*(u16 *)data, addr);
835 break;
836 case 4:
837 writel(*(u32 *)data, addr);
838 break;
839 case 8:
840 writeq(*(u64 *)data, addr);
841 break;
842 default:
843 ret = -1;
844 break;
845 }
846 write_unlock_irqrestore(&ha->hw_lock, flags);
847 if (mem_ptr)
848 iounmap(mem_ptr);
849 return ret;
850}
851
852#define MTU_FUDGE_FACTOR 100
853
854static unsigned long
f8086f4f 855qla4_82xx_decode_crb_addr(unsigned long addr)
f4f5df23
VC		 856{
857 int i;
858 unsigned long base_addr, offset, pci_base;
859
860 if (!qla4_8xxx_crb_table_initialized)
f8086f4f 861 qla4_82xx_crb_addr_transform_setup();
f4f5df23
VC		 862
863 pci_base = ADDR_ERROR;
864 base_addr = addr & 0xfff00000;
865 offset = addr & 0x000fffff;
866
867 for (i = 0; i < MAX_CRB_XFORM; i++) {
868 if (crb_addr_xform[i] == base_addr) {
869 pci_base = i << 20;
870 break;
871 }
872 }
873 if (pci_base == ADDR_ERROR)
874 return pci_base;
875 else
876 return pci_base + offset;
877}
878
879static long rom_max_timeout = 100;
7664a1fd 880static long qla4_82xx_rom_lock_timeout = 100;
f4f5df23
VC		 881
882static int
f8086f4f 883qla4_82xx_rom_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 884{
885 int i;
886 int done = 0, timeout = 0;
887
888 while (!done) {
889 /* acquire semaphore2 from PCI HW block */
890
f8086f4f 891 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
f4f5df23
VC		 892 if (done == 1)
893 break;
7664a1fd 894 if (timeout >= qla4_82xx_rom_lock_timeout)
f4f5df23
VC		 895 return -1;
896
897 timeout++;
898
899 /* Yield CPU */
900 if (!in_interrupt())
901 schedule();
902 else {
903 for (i = 0; i < 20; i++)
904 cpu_relax(); /*This a nop instr on i386*/
905 }
906 }
f8086f4f 907 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
f4f5df23
VC		 908 return 0;
909}
910
911static void
f8086f4f 912qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
f4f5df23 913{
f8086f4f 914 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
f4f5df23
VC		 915}
916
917static int
f8086f4f 918qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
f4f5df23
VC		 919{
920 long timeout = 0;
921 long done = 0 ;
922
923 while (done == 0) {
f8086f4f 924 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
f4f5df23
VC		 925 done &= 2;
926 timeout++;
927 if (timeout >= rom_max_timeout) {
928 printk("%s: Timeout reached waiting for rom done",
929 DRIVER_NAME);
930 return -1;
931 }
932 }
933 return 0;
934}
935
936static int
f8086f4f 937qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
f4f5df23 938{
f8086f4f
VC		 939 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
940 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
941 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
942 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
943 if (qla4_82xx_wait_rom_done(ha)) {
f4f5df23
VC		 944 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
945 return -1;
946 }
947 /* reset abyte_cnt and dummy_byte_cnt */
f8086f4f 948 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
f4f5df23 949 udelay(10);
f8086f4f 950 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
f4f5df23 951
f8086f4f 952 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
f4f5df23
VC		 953 return 0;
954}
955
956static int
f8086f4f 957qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
f4f5df23
VC		 958{
959 int ret, loops = 0;
960
f8086f4f 961 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
f4f5df23
VC		 962 udelay(100);
963 loops++;
964 }
965 if (loops >= 50000) {
f8086f4f
VC		 966 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
967 DRIVER_NAME);
f4f5df23
VC		 968 return -1;
969 }
f8086f4f
VC		 970 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
971 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 972 return ret;
973}
974
975/**
976 * This routine does CRB initialize sequence
977 * to put the ISP into operational state
978 **/
979static int
f8086f4f 980qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
f4f5df23
VC		 981{
982 int addr, val;
983 int i ;
984 struct crb_addr_pair *buf;
985 unsigned long off;
986 unsigned offset, n;
987
988 struct crb_addr_pair {
989 long addr;
990 long data;
991 };
992
993 /* Halt all the indiviual PEGs and other blocks of the ISP */
f8086f4f 994 qla4_82xx_rom_lock(ha);
a1fc26ba 995
cb74428e 996 /* disable all I2Q */
f8086f4f
VC		 997 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
998 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
999 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1001 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1002 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
cb74428e
VC		 1003
1004 /* disable all niu interrupts */
f8086f4f 1005 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
a1fc26ba 1006 /* disable xge rx/tx */
f8086f4f 1007 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
a1fc26ba 1008 /* disable xg1 rx/tx */
f8086f4f 1009 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
cb74428e 1010 /* disable sideband mac */
f8086f4f 1011 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
cb74428e 1012 /* disable ap0 mac */
f8086f4f 1013 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
cb74428e 1014 /* disable ap1 mac */
f8086f4f 1015 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
a1fc26ba
SN		 1016
1017 /* halt sre */
f8086f4f
VC		 1018 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1019 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
a1fc26ba
SN		 1020
1021 /* halt epg */
f8086f4f 1022 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
a1fc26ba
SN		 1023
1024 /* halt timers */
f8086f4f
VC		 1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1026 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1027 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1028 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1029 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1030 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
a1fc26ba
SN		 1031
1032 /* halt pegs */
f8086f4f
VC		 1033 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1034 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1035 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1036 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1037 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
cb74428e 1038 msleep(5);
a1fc26ba
SN		 1039
1040 /* big hammer */
f4f5df23
VC		 1041 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1042 /* don't reset CAM block on reset */
f8086f4f 1043 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
f4f5df23 1044 else
f8086f4f 1045 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
f4f5df23 1046
f8086f4f 1047 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 1048
1049 /* Read the signature value from the flash.
1050 * Offset 0: Contain signature (0xcafecafe)
1051 * Offset 4: Offset and number of addr/value pairs
1052 * that present in CRB initialize sequence
1053 */
f8086f4f
VC		 1054 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1055 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
f4f5df23
VC		 1056 ql4_printk(KERN_WARNING, ha,
1057 "[ERROR] Reading crb_init area: n: %08x\n", n);
1058 return -1;
1059 }
1060
1061 /* Offset in flash = lower 16 bits
1062 * Number of enteries = upper 16 bits
1063 */
1064 offset = n & 0xffffU;
1065 n = (n >> 16) & 0xffffU;
1066
1067 /* number of addr/value pair should not exceed 1024 enteries */
1068 if (n >= 1024) {
1069 ql4_printk(KERN_WARNING, ha,
1070 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1071 DRIVER_NAME, __func__, n);
1072 return -1;
1073 }
1074
1075 ql4_printk(KERN_INFO, ha,
1076 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1077
1078 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1079 if (buf == NULL) {
1080 ql4_printk(KERN_WARNING, ha,
1081 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1082 return -1;
1083 }
1084
1085 for (i = 0; i < n; i++) {
f8086f4f
VC		 1086 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1087 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
f4f5df23
VC		 1088 0) {
1089 kfree(buf);
1090 return -1;
1091 }
1092
1093 buf[i].addr = addr;
1094 buf[i].data = val;
1095 }
1096
1097 for (i = 0; i < n; i++) {
1098 /* Translate internal CRB initialization
1099 * address to PCI bus address
1100 */
f8086f4f 1101 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
f4f5df23
VC		 1102 QLA82XX_PCI_CRBSPACE;
1103 /* Not all CRB addr/value pair to be written,
1104 * some of them are skipped
1105 */
1106
1107 /* skip if LS bit is set*/
1108 if (off & 0x1) {
1109 DEBUG2(ql4_printk(KERN_WARNING, ha,
1110 "Skip CRB init replay for offset = 0x%lx\n", off));
1111 continue;
1112 }
1113
1114 /* skipping cold reboot MAGIC */
1115 if (off == QLA82XX_CAM_RAM(0x1fc))
1116 continue;
1117
1118 /* do not reset PCI */
1119 if (off == (ROMUSB_GLB + 0xbc))
1120 continue;
1121
1122 /* skip core clock, so that firmware can increase the clock */
1123 if (off == (ROMUSB_GLB + 0xc8))
1124 continue;
1125
1126 /* skip the function enable register */
1127 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1128 continue;
1129
1130 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1131 continue;
1132
1133 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1134 continue;
1135
1136 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1137 continue;
1138
1139 if (off == ADDR_ERROR) {
1140 ql4_printk(KERN_WARNING, ha,
1141 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1142 DRIVER_NAME, buf[i].addr);
1143 continue;
1144 }
1145
f8086f4f 1146 qla4_82xx_wr_32(ha, off, buf[i].data);
f4f5df23
VC		 1147
1148 /* ISP requires much bigger delay to settle down,
1149 * else crb_window returns 0xffffffff
1150 */
1151 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1152 msleep(1000);
1153
1154 /* ISP requires millisec delay between
1155 * successive CRB register updation
1156 */
1157 msleep(1);
1158 }
1159
1160 kfree(buf);
1161
1162 /* Resetting the data and instruction cache */
f8086f4f
VC		 1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1164 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1165 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
f4f5df23
VC		 1166
1167 /* Clear all protocol processing engines */
f8086f4f
VC		 1168 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1169 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1170 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1171 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1172 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1173 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1174 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1175 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
f4f5df23
VC		 1176
1177 return 0;
1178}
1179
f4f5df23 1180static int
f8086f4f 1181qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23 1182{
4cd83cbe 1183 int i, rval = 0;
f4f5df23
VC		 1184 long size = 0;
1185 long flashaddr, memaddr;
1186 u64 data;
1187 u32 high, low;
1188
1189 flashaddr = memaddr = ha->hw.flt_region_bootload;
4cd83cbe 1190 size = (image_start - flashaddr) / 8;
f4f5df23
VC		 1191
1192 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1193 ha->host_no, __func__, flashaddr, image_start));
1194
1195 for (i = 0; i < size; i++) {
f8086f4f
VC		 1196 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1197 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
f4f5df23 1198 (int *)&high))) {
4cd83cbe
LC		 1199 rval = -1;
1200 goto exit_load_from_flash;
f4f5df23
VC		 1201 }
1202 data = ((u64)high << 32) | low ;
f8086f4f 1203 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
4cd83cbe
LC		 1204 if (rval)
1205 goto exit_load_from_flash;
1206
f4f5df23
VC		 1207 flashaddr += 8;
1208 memaddr += 8;
1209
4cd83cbe 1210 if (i % 0x1000 == 0)
f4f5df23
VC		 1211 msleep(1);
1212
1213 }
1214
1215 udelay(100);
1216
1217 read_lock(&ha->hw_lock);
f8086f4f
VC		 1218 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1219 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
f4f5df23
VC		 1220 read_unlock(&ha->hw_lock);
1221
4cd83cbe
LC		 1222exit_load_from_flash:
1223 return rval;
f4f5df23
VC		 1224}
1225
f8086f4f 1226static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23
VC		 1227{
1228 u32 rst;
1229
f8086f4f
VC		 1230 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1231 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
f4f5df23
VC		 1232 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1233 __func__);
1234 return QLA_ERROR;
1235 }
1236
1237 udelay(500);
1238
1239 /* at this point, QM is in reset. This could be a problem if there are
1240 * incoming d* transition queue messages. QM/PCIE could wedge.
1241 * To get around this, QM is brought out of reset.
1242 */
1243
f8086f4f 1244 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
f4f5df23
VC		 1245 /* unreset qm */
1246 rst &= ~(1 << 28);
f8086f4f 1247 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
f4f5df23 1248
f8086f4f 1249 if (qla4_82xx_load_from_flash(ha, image_start)) {
f4f5df23
VC		 1250 printk("%s: Error trying to load fw from flash!\n", __func__);
1251 return QLA_ERROR;
1252 }
1253
1254 return QLA_SUCCESS;
1255}
1256
1257int
f8086f4f 1258qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
f4f5df23
VC		 1259 u64 off, void *data, int size)
1260{
1261 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1262 int shift_amount;
1263 uint32_t temp;
1264 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1265
1266 /*
1267 * If not MN, go check for MS or invalid.
1268 */
1269
de8c72da 1270 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
f4f5df23
VC		 1271 mem_crb = QLA82XX_CRB_QDR_NET;
1272 else {
1273 mem_crb = QLA82XX_CRB_DDR_NET;
f8086f4f
VC		 1274 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1275 return qla4_82xx_pci_mem_read_direct(ha,
f4f5df23
VC		 1276 off, data, size);
1277 }
1278
1279
1280 off8 = off & 0xfffffff0;
1281 off0[0] = off & 0xf;
1282 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1283 shift_amount = 4;
1284
1285 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1286 off0[1] = 0;
1287 sz[1] = size - sz[0];
1288
1289 for (i = 0; i < loop; i++) {
1290 temp = off8 + (i << shift_amount);
f8086f4f 1291 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
f4f5df23 1292 temp = 0;
f8086f4f 1293 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
f4f5df23 1294 temp = MIU_TA_CTL_ENABLE;
f8086f4f 1295 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
c38fa3ab 1296 temp = MIU_TA_CTL_START_ENABLE;
f8086f4f 1297 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
f4f5df23
VC		 1298
1299 for (j = 0; j < MAX_CTL_CHECK; j++) {
f8086f4f 1300 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
f4f5df23
VC		 1301 if ((temp & MIU_TA_CTL_BUSY) == 0)
1302 break;
1303 }
1304
1305 if (j >= MAX_CTL_CHECK) {
068237c8
TP		 1306 printk_ratelimited(KERN_ERR
1307 "%s: failed to read through agent\n",
1308 __func__);
f4f5df23
VC		 1309 break;
1310 }
1311
1312 start = off0[i] >> 2;
1313 end = (off0[i] + sz[i] - 1) >> 2;
1314 for (k = start; k <= end; k++) {
f8086f4f 1315 temp = qla4_82xx_rd_32(ha,
f4f5df23
VC		 1316 mem_crb + MIU_TEST_AGT_RDDATA(k));
1317 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1318 }
1319 }
1320
1321 if (j >= MAX_CTL_CHECK)
1322 return -1;
1323
1324 if ((off0[0] & 7) == 0) {
1325 val = word[0];
1326 } else {
1327 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1328 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1329 }
1330
1331 switch (size) {
1332 case 1:
1333 *(uint8_t *)data = val;
1334 break;
1335 case 2:
1336 *(uint16_t *)data = val;
1337 break;
1338 case 4:
1339 *(uint32_t *)data = val;
1340 break;
1341 case 8:
1342 *(uint64_t *)data = val;
1343 break;
1344 }
1345 return 0;
1346}
1347
1348int
f8086f4f 1349qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
f4f5df23
VC		 1350 u64 off, void *data, int size)
1351{
1352 int i, j, ret = 0, loop, sz[2], off0;
1353 int scale, shift_amount, startword;
1354 uint32_t temp;
1355 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1356
1357 /*
1358 * If not MN, go check for MS or invalid.
1359 */
de8c72da 1360 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
f4f5df23
VC		 1361 mem_crb = QLA82XX_CRB_QDR_NET;
1362 else {
1363 mem_crb = QLA82XX_CRB_DDR_NET;
f8086f4f
VC		 1364 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1365 return qla4_82xx_pci_mem_write_direct(ha,
f4f5df23
VC		 1366 off, data, size);
1367 }
1368
1369 off0 = off & 0x7;
1370 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1371 sz[1] = size - sz[0];
1372
1373 off8 = off & 0xfffffff0;
1374 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1375 shift_amount = 4;
1376 scale = 2;
1377 startword = (off & 0xf)/8;
1378
1379 for (i = 0; i < loop; i++) {
f8086f4f 1380 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
f4f5df23
VC		 1381 (i << shift_amount), &word[i * scale], 8))
1382 return -1;
1383 }
1384
1385 switch (size) {
1386 case 1:
1387 tmpw = *((uint8_t *)data);
1388 break;
1389 case 2:
1390 tmpw = *((uint16_t *)data);
1391 break;
1392 case 4:
1393 tmpw = *((uint32_t *)data);
1394 break;
1395 case 8:
1396 default:
1397 tmpw = *((uint64_t *)data);
1398 break;
1399 }
1400
1401 if (sz[0] == 8)
1402 word[startword] = tmpw;
1403 else {
1404 word[startword] &=
1405 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1406 word[startword] |= tmpw << (off0 * 8);
1407 }
1408
1409 if (sz[1] != 0) {
1410 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1411 word[startword+1] |= tmpw >> (sz[0] * 8);
1412 }
1413
1414 for (i = 0; i < loop; i++) {
1415 temp = off8 + (i << shift_amount);
f8086f4f 1416 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
f4f5df23 1417 temp = 0;
f8086f4f 1418 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
f4f5df23 1419 temp = word[i * scale] & 0xffffffff;
f8086f4f 1420 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
f4f5df23 1421 temp = (word[i * scale] >> 32) & 0xffffffff;
f8086f4f 1422 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
f4f5df23 1423 temp = word[i*scale + 1] & 0xffffffff;
f8086f4f 1424 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
f4f5df23
VC		 1425 temp);
1426 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
f8086f4f 1427 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
f4f5df23
VC		 1428 temp);
1429
c38fa3ab 1430 temp = MIU_TA_CTL_WRITE_ENABLE;
f8086f4f 1431 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
c38fa3ab 1432 temp = MIU_TA_CTL_WRITE_START;
f8086f4f 1433 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
f4f5df23
VC		 1434
1435 for (j = 0; j < MAX_CTL_CHECK; j++) {
f8086f4f 1436 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
f4f5df23
VC		 1437 if ((temp & MIU_TA_CTL_BUSY) == 0)
1438 break;
1439 }
1440
1441 if (j >= MAX_CTL_CHECK) {
1442 if (printk_ratelimit())
1443 ql4_printk(KERN_ERR, ha,
068237c8
TP		 1444 "%s: failed to read through agent\n",
1445 __func__);
f4f5df23
VC		 1446 ret = -1;
1447 break;
1448 }
1449 }
1450
1451 return ret;
1452}
1453
f8086f4f 1454static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
f4f5df23
VC		 1455{
1456 u32 val = 0;
1457 int retries = 60;
1458
1459 if (!pegtune_val) {
1460 do {
f8086f4f 1461 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
f4f5df23
VC		 1462 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1463 (val == PHAN_INITIALIZE_ACK))
1464 return 0;
1465 set_current_state(TASK_UNINTERRUPTIBLE);
1466 schedule_timeout(500);
1467
1468 } while (--retries);
1469
f4f5df23 1470 if (!retries) {
f8086f4f 1471 pegtune_val = qla4_82xx_rd_32(ha,
f4f5df23
VC		 1472 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1473 printk(KERN_WARNING "%s: init failed, "
1474 "pegtune_val = %x\n", __func__, pegtune_val);
1475 return -1;
1476 }
1477 }
1478 return 0;
1479}
1480
f8086f4f 1481static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
f4f5df23
VC		 1482{
1483 uint32_t state = 0;
1484 int loops = 0;
1485
1486 /* Window 1 call */
1487 read_lock(&ha->hw_lock);
f8086f4f 1488 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
f4f5df23
VC		 1489 read_unlock(&ha->hw_lock);
1490
1491 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1492 udelay(100);
1493 /* Window 1 call */
1494 read_lock(&ha->hw_lock);
f8086f4f 1495 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
f4f5df23
VC		 1496 read_unlock(&ha->hw_lock);
1497
1498 loops++;
1499 }
1500
1501 if (loops >= 30000) {
1502 DEBUG2(ql4_printk(KERN_INFO, ha,
1503 "Receive Peg initialization not complete: 0x%x.\n", state));
1504 return QLA_ERROR;
1505 }
1506
1507 return QLA_SUCCESS;
1508}
1509
626115cd 1510void
f4f5df23
VC		 1511qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1512{
1513 uint32_t drv_active;
1514
33693c7a 1515 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
6e7b4292
VC		 1516
1517 /*
b37ca418 1518 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1519 * shift 1 by func_num to set a bit for the function.
1520 * For ISP8022, drv_active has 4 bits per function
1521 */
b37ca418 1522 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1523 drv_active |= (1 << ha->func_num);
1524 else
1525 drv_active |= (1 << (ha->func_num * 4));
1526
068237c8
TP		 1527 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1528 __func__, ha->host_no, drv_active);
33693c7a 1529 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
f4f5df23
VC		 1530}
1531
1532void
1533qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1534{
1535 uint32_t drv_active;
1536
33693c7a 1537 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
6e7b4292
VC		 1538
1539 /*
b37ca418 1540 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1541 * shift 1 by func_num to set a bit for the function.
1542 * For ISP8022, drv_active has 4 bits per function
1543 */
b37ca418 1544 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1545 drv_active &= ~(1 << (ha->func_num));
1546 else
1547 drv_active &= ~(1 << (ha->func_num * 4));
1548
068237c8
TP		 1549 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1550 __func__, ha->host_no, drv_active);
33693c7a 1551 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
f4f5df23
VC		 1552}
1553
33693c7a 1554inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
f4f5df23 1555{
2232be0d 1556 uint32_t drv_state, drv_active;
f4f5df23
VC		 1557 int rval;
1558
33693c7a
VC		 1559 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1560 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
6e7b4292
VC		 1561
1562 /*
b37ca418 1563 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1564 * shift 1 by func_num to set a bit for the function.
1565 * For ISP8022, drv_active has 4 bits per function
1566 */
b37ca418 1567 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1568 rval = drv_state & (1 << ha->func_num);
1569 else
1570 rval = drv_state & (1 << (ha->func_num * 4));
1571
2232be0d
LC		 1572 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1573 rval = 1;
1574
f4f5df23
VC		 1575 return rval;
1576}
1577
6e7b4292 1578void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
f4f5df23
VC		 1579{
1580 uint32_t drv_state;
1581
33693c7a 1582 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
6e7b4292
VC		 1583
1584 /*
b37ca418 1585 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1586 * shift 1 by func_num to set a bit for the function.
1587 * For ISP8022, drv_active has 4 bits per function
1588 */
b37ca418 1589 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1590 drv_state |= (1 << ha->func_num);
1591 else
1592 drv_state |= (1 << (ha->func_num * 4));
1593
068237c8
TP		 1594 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1595 __func__, ha->host_no, drv_state);
33693c7a 1596 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
f4f5df23
VC		 1597}
1598
6e7b4292 1599void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
f4f5df23
VC		 1600{
1601 uint32_t drv_state;
1602
33693c7a 1603 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
6e7b4292
VC		 1604
1605 /*
b37ca418 1606 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1607 * shift 1 by func_num to set a bit for the function.
1608 * For ISP8022, drv_active has 4 bits per function
1609 */
b37ca418 1610 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1611 drv_state &= ~(1 << ha->func_num);
1612 else
1613 drv_state &= ~(1 << (ha->func_num * 4));
1614
068237c8
TP		 1615 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1616 __func__, ha->host_no, drv_state);
33693c7a 1617 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
f4f5df23
VC		 1618}
1619
1620static inline void
1621qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1622{
1623 uint32_t qsnt_state;
1624
33693c7a 1625 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
6e7b4292
VC		 1626
1627 /*
b37ca418 1628 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
6e7b4292
VC		 1629 * shift 1 by func_num to set a bit for the function.
1630 * For ISP8022, drv_active has 4 bits per function.
1631 */
b37ca418 1632 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 1633 qsnt_state |= (1 << ha->func_num);
1634 else
1635 qsnt_state |= (2 << (ha->func_num * 4));
1636
33693c7a 1637 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
f4f5df23
VC		 1638}
1639
1640
1641static int
f8086f4f 1642qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23 1643{
f4f5df23
VC		 1644 uint16_t lnk;
1645
1646 /* scrub dma mask expansion register */
f8086f4f 1647 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
f4f5df23
VC		 1648
1649 /* Overwrite stale initialization register values */
f8086f4f
VC		 1650 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1651 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1652 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1653 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
f4f5df23 1654
f8086f4f 1655 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
f4f5df23
VC		 1656 printk("%s: Error trying to start fw!\n", __func__);
1657 return QLA_ERROR;
1658 }
1659
1660 /* Handshake with the card before we register the devices. */
f8086f4f 1661 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
f4f5df23
VC		 1662 printk("%s: Error during card handshake!\n", __func__);
1663 return QLA_ERROR;
1664 }
1665
1666 /* Negotiated Link width */
5548bfd0 1667 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
f4f5df23
VC		 1668 ha->link_width = (lnk >> 4) & 0x3f;
1669
1670 /* Synchronize with Receive peg */
f8086f4f 1671 return qla4_82xx_rcvpeg_ready(ha);
f4f5df23
VC		 1672}
1673
33693c7a 1674int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
f4f5df23
VC		 1675{
1676 int rval = QLA_ERROR;
1677
1678 /*
1679 * FW Load priority:
1680 * 1) Operational firmware residing in flash.
1681 * 2) Fail
1682 */
1683
1684 ql4_printk(KERN_INFO, ha,
1685 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1686 rval = qla4_8xxx_get_flash_info(ha);
1687 if (rval != QLA_SUCCESS)
1688 return rval;
1689
1690 ql4_printk(KERN_INFO, ha,
1691 "FW: Attempting to load firmware from flash...\n");
f8086f4f 1692 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
f4f5df23 1693
f581a3f7
VC		 1694 if (rval != QLA_SUCCESS) {
1695 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1696 " FAILED...\n");
1697 return rval;
1698 }
f4f5df23
VC		 1699
1700 return rval;
1701}
1702
33693c7a 1703void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
b25ee66f 1704{
f8086f4f 1705 if (qla4_82xx_rom_lock(ha)) {
b25ee66f
SS		 1706 /* Someone else is holding the lock. */
1707 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1708 }
1709
1710 /*
1711 * Either we got the lock, or someone
1712 * else died while holding it.
1713 * In either case, unlock.
1714 */
f8086f4f 1715 qla4_82xx_rom_unlock(ha);
b25ee66f
SS		 1716}
1717
b1829789
TP		 1718static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
1719 uint32_t addr1, uint32_t mask)
1720{
1721 unsigned long timeout;
1722 uint32_t rval = QLA_SUCCESS;
1723 uint32_t temp;
1724
1725 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1726 do {
1727 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
1728 if ((temp & mask) != 0)
1729 break;
1730
1731 if (time_after_eq(jiffies, timeout)) {
1732 ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
1733 return QLA_ERROR;
1734 }
1735 } while (1);
1736
1737 return rval;
1738}
1739
1740uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
1741 uint32_t addr3, uint32_t mask, uint32_t addr,
1742 uint32_t *data_ptr)
1743{
1744 int rval = QLA_SUCCESS;
1745 uint32_t temp;
1746 uint32_t data;
1747
1748 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1749 if (rval)
1750 goto exit_ipmdio_rd_reg;
1751
1752 temp = (0x40000000 | addr);
1753 ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
1754
1755 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1756 if (rval)
1757 goto exit_ipmdio_rd_reg;
1758
1759 ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
1760 *data_ptr = data;
1761
1762exit_ipmdio_rd_reg:
1763 return rval;
1764}
1765
1766
1767static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
1768 uint32_t addr1,
1769 uint32_t addr2,
1770 uint32_t addr3,
1771 uint32_t mask)
1772{
1773 unsigned long timeout;
1774 uint32_t temp;
1775 uint32_t rval = QLA_SUCCESS;
1776
1777 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1778 do {
1779 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
1780 if ((temp & 0x1) != 1)
1781 break;
1782 if (time_after_eq(jiffies, timeout)) {
1783 ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
1784 return QLA_ERROR;
1785 }
1786 } while (1);
1787
1788 return rval;
1789}
1790
1791static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
1792 uint32_t addr1, uint32_t addr3,
1793 uint32_t mask, uint32_t addr,
1794 uint32_t value)
1795{
1796 int rval = QLA_SUCCESS;
1797
1798 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1799 if (rval)
1800 goto exit_ipmdio_wr_reg;
1801
1802 ha->isp_ops->wr_reg_indirect(ha, addr3, value);
1803 ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
1804
1805 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1806 if (rval)
1807 goto exit_ipmdio_wr_reg;
1808
1809exit_ipmdio_wr_reg:
1810 return rval;
1811}
1812
068237c8 1813static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
7664a1fd 1814 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1815 uint32_t **d_ptr)
1816{
1817 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
7664a1fd 1818 struct qla8xxx_minidump_entry_crb *crb_hdr;
068237c8
TP		 1819 uint32_t *data_ptr = *d_ptr;
1820
1821 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1822 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
068237c8
TP		 1823 r_addr = crb_hdr->addr;
1824 r_stride = crb_hdr->crb_strd.addr_stride;
1825 loop_cnt = crb_hdr->op_count;
1826
1827 for (i = 0; i < loop_cnt; i++) {
33693c7a 1828 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 1829 *data_ptr++ = cpu_to_le32(r_addr);
1830 *data_ptr++ = cpu_to_le32(r_value);
1831 r_addr += r_stride;
1832 }
1833 *d_ptr = data_ptr;
1834}
1835
41f79bde
SV		 1836static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1837{
1838 int rval = QLA_SUCCESS;
1839 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1840 uint64_t dma_base_addr = 0;
1841 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1842
1843 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1844 ha->fw_dump_tmplt_hdr;
1845 dma_eng_num =
1846 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1847 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1848 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1849
1850 /* Read the pex-dma's command-status-and-control register. */
1851 rval = ha->isp_ops->rd_reg_indirect(ha,
1852 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1853 &cmd_sts_and_cntrl);
1854
1855 if (rval)
1856 return QLA_ERROR;
1857
1858 /* Check if requested pex-dma engine is available. */
1859 if (cmd_sts_and_cntrl & BIT_31)
1860 return QLA_SUCCESS;
1861 else
1862 return QLA_ERROR;
1863}
1864
1865static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1866 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1867{
1868 int rval = QLA_SUCCESS, wait = 0;
1869 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1870 uint64_t dma_base_addr = 0;
1871 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1872
1873 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1874 ha->fw_dump_tmplt_hdr;
1875 dma_eng_num =
1876 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1877 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1878 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1879
1880 rval = ha->isp_ops->wr_reg_indirect(ha,
1881 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1882 m_hdr->desc_card_addr);
1883 if (rval)
1884 goto error_exit;
1885
1886 rval = ha->isp_ops->wr_reg_indirect(ha,
1887 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1888 if (rval)
1889 goto error_exit;
1890
1891 rval = ha->isp_ops->wr_reg_indirect(ha,
1892 dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
1893 m_hdr->start_dma_cmd);
1894 if (rval)
1895 goto error_exit;
1896
1897 /* Wait for dma operation to complete. */
1898 for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
1899 rval = ha->isp_ops->rd_reg_indirect(ha,
1900 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1901 &cmd_sts_and_cntrl);
1902 if (rval)
1903 goto error_exit;
1904
1905 if ((cmd_sts_and_cntrl & BIT_1) == 0)
1906 break;
1907 else
1908 udelay(10);
1909 }
1910
1911 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
1912 if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
1913 rval = QLA_ERROR;
1914 goto error_exit;
1915 }
1916
1917error_exit:
1918 return rval;
1919}
1920
1921static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1922 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1923 uint32_t **d_ptr)
1924{
1925 int rval = QLA_SUCCESS;
1926 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
1927 uint32_t size, read_size;
1928 uint8_t *data_ptr = (uint8_t *)*d_ptr;
1929 void *rdmem_buffer = NULL;
1930 dma_addr_t rdmem_dma;
1931 struct qla4_83xx_pex_dma_descriptor dma_desc;
1932
1933 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1934
1935 rval = qla4_83xx_check_dma_engine_state(ha);
1936 if (rval != QLA_SUCCESS) {
1937 DEBUG2(ql4_printk(KERN_INFO, ha,
1938 "%s: DMA engine not available. Fallback to rdmem-read.\n",
1939 __func__));
1940 return QLA_ERROR;
1941 }
1942
1943 m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
1944 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
1945 QLA83XX_PEX_DMA_READ_SIZE,
1946 &rdmem_dma, GFP_KERNEL);
1947 if (!rdmem_buffer) {
1948 DEBUG2(ql4_printk(KERN_INFO, ha,
1949 "%s: Unable to allocate rdmem dma buffer\n",
1950 __func__));
1951 return QLA_ERROR;
1952 }
1953
1954 /* Prepare pex-dma descriptor to be written to MS memory. */
1955 /* dma-desc-cmd layout:
1956 * 0-3: dma-desc-cmd 0-3
1957 * 4-7: pcid function number
1958 * 8-15: dma-desc-cmd 8-15
1959 */
1960 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
1961 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
1962 dma_desc.dma_bus_addr = rdmem_dma;
1963
1964 size = 0;
1965 read_size = 0;
1966 /*
1967 * Perform rdmem operation using pex-dma.
1968 * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
1969 */
1970 while (read_size < m_hdr->read_data_size) {
1971 if (m_hdr->read_data_size - read_size >=
1972 QLA83XX_PEX_DMA_READ_SIZE)
1973 size = QLA83XX_PEX_DMA_READ_SIZE;
1974 else {
1975 size = (m_hdr->read_data_size - read_size);
1976
1977 if (rdmem_buffer)
1978 dma_free_coherent(&ha->pdev->dev,
1979 QLA83XX_PEX_DMA_READ_SIZE,
1980 rdmem_buffer, rdmem_dma);
1981
1982 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
1983 &rdmem_dma,
1984 GFP_KERNEL);
1985 if (!rdmem_buffer) {
1986 DEBUG2(ql4_printk(KERN_INFO, ha,
1987 "%s: Unable to allocate rdmem dma buffer\n",
1988 __func__));
1989 return QLA_ERROR;
1990 }
1991 dma_desc.dma_bus_addr = rdmem_dma;
1992 }
1993
1994 dma_desc.src_addr = m_hdr->read_addr + read_size;
1995 dma_desc.cmd.read_data_size = size;
1996
1997 /* Prepare: Write pex-dma descriptor to MS memory. */
1998 rval = qla4_83xx_ms_mem_write_128b(ha,
1999 (uint64_t)m_hdr->desc_card_addr,
2000 (uint32_t *)&dma_desc,
2001 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
2002 if (rval == -1) {
2003 ql4_printk(KERN_INFO, ha,
2004 "%s: Error writing rdmem-dma-init to MS !!!\n",
2005 __func__);
2006 goto error_exit;
2007 }
2008
2009 DEBUG2(ql4_printk(KERN_INFO, ha,
2010 "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
2011 __func__, size));
2012 /* Execute: Start pex-dma operation. */
2013 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
2014 if (rval != QLA_SUCCESS) {
2015 DEBUG2(ql4_printk(KERN_INFO, ha,
2016 "scsi(%ld): start-pex-dma failed rval=0x%x\n",
2017 ha->host_no, rval));
2018 goto error_exit;
2019 }
2020
2021 memcpy(data_ptr, rdmem_buffer, size);
2022 data_ptr += size;
2023 read_size += size;
2024 }
2025
2026 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2027
2028 *d_ptr = (uint32_t *)data_ptr;
2029
2030error_exit:
2031 if (rdmem_buffer)
2032 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
2033 rdmem_dma);
2034
2035 return rval;
2036}
2037
068237c8 2038static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
7664a1fd 2039 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2040 uint32_t **d_ptr)
2041{
2042 uint32_t addr, r_addr, c_addr, t_r_addr;
2043 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2044 unsigned long p_wait, w_time, p_mask;
2045 uint32_t c_value_w, c_value_r;
7664a1fd 2046 struct qla8xxx_minidump_entry_cache *cache_hdr;
068237c8
TP		 2047 int rval = QLA_ERROR;
2048 uint32_t *data_ptr = *d_ptr;
2049
2050 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2051 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
068237c8
TP		 2052
2053 loop_count = cache_hdr->op_count;
2054 r_addr = cache_hdr->read_addr;
2055 c_addr = cache_hdr->control_addr;
2056 c_value_w = cache_hdr->cache_ctrl.write_value;
2057
2058 t_r_addr = cache_hdr->tag_reg_addr;
2059 t_value = cache_hdr->addr_ctrl.init_tag_value;
2060 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2061 p_wait = cache_hdr->cache_ctrl.poll_wait;
2062 p_mask = cache_hdr->cache_ctrl.poll_mask;
2063
2064 for (i = 0; i < loop_count; i++) {
33693c7a 2065 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
068237c8
TP		 2066
2067 if (c_value_w)
33693c7a 2068 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
068237c8
TP		 2069
2070 if (p_mask) {
2071 w_time = jiffies + p_wait;
2072 do {
33693c7a
VC		 2073 ha->isp_ops->rd_reg_indirect(ha, c_addr,
2074 &c_value_r);
068237c8
TP		 2075 if ((c_value_r & p_mask) == 0) {
2076 break;
2077 } else if (time_after_eq(jiffies, w_time)) {
2078 /* capturing dump failed */
2079 return rval;
2080 }
2081 } while (1);
2082 }
2083
2084 addr = r_addr;
2085 for (k = 0; k < r_cnt; k++) {
33693c7a 2086 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
068237c8
TP		 2087 *data_ptr++ = cpu_to_le32(r_value);
2088 addr += cache_hdr->read_ctrl.read_addr_stride;
2089 }
2090
2091 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2092 }
2093 *d_ptr = data_ptr;
2094 return QLA_SUCCESS;
2095}
2096
2097static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
7664a1fd 2098 struct qla8xxx_minidump_entry_hdr *entry_hdr)
068237c8 2099{
7664a1fd 2100 struct qla8xxx_minidump_entry_crb *crb_entry;
068237c8
TP		 2101 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2102 uint32_t crb_addr;
2103 unsigned long wtime;
2104 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2105 int i;
2106
2107 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2108 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2109 ha->fw_dump_tmplt_hdr;
7664a1fd 2110 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
068237c8
TP		 2111
2112 crb_addr = crb_entry->addr;
2113 for (i = 0; i < crb_entry->op_count; i++) {
2114 opcode = crb_entry->crb_ctrl.opcode;
de8c72da 2115 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
33693c7a
VC		 2116 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2117 crb_entry->value_1);
de8c72da 2118 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
068237c8 2119 }
de8c72da 2120 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
33693c7a
VC		 2121 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2122 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
de8c72da 2123 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
068237c8 2124 }
de8c72da 2125 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
33693c7a 2126 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8 2127 read_value &= crb_entry->value_2;
de8c72da
VC		 2128 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2129 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
068237c8 2130 read_value |= crb_entry->value_3;
de8c72da 2131 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
068237c8 2132 }
33693c7a 2133 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
068237c8 2134 }
de8c72da 2135 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
33693c7a 2136 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8 2137 read_value |= crb_entry->value_3;
33693c7a 2138 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
de8c72da 2139 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
068237c8 2140 }
de8c72da 2141 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
068237c8
TP		 2142 poll_time = crb_entry->crb_strd.poll_timeout;
2143 wtime = jiffies + poll_time;
33693c7a 2144 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8
TP		 2145
2146 do {
2147 if ((read_value & crb_entry->value_2) ==
33693c7a 2148 crb_entry->value_1) {
068237c8 2149 break;
33693c7a 2150 } else if (time_after_eq(jiffies, wtime)) {
068237c8
TP		 2151 /* capturing dump failed */
2152 rval = QLA_ERROR;
2153 break;
33693c7a
VC		 2154 } else {
2155 ha->isp_ops->rd_reg_indirect(ha,
2156 crb_addr, &read_value);
2157 }
068237c8 2158 } while (1);
de8c72da 2159 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
068237c8
TP		 2160 }
2161
de8c72da 2162 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
068237c8
TP		 2163 if (crb_entry->crb_strd.state_index_a) {
2164 index = crb_entry->crb_strd.state_index_a;
2165 addr = tmplt_hdr->saved_state_array[index];
2166 } else {
2167 addr = crb_addr;
2168 }
2169
33693c7a 2170 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
068237c8
TP		 2171 index = crb_entry->crb_ctrl.state_index_v;
2172 tmplt_hdr->saved_state_array[index] = read_value;
de8c72da 2173 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
068237c8
TP		 2174 }
2175
de8c72da 2176 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
068237c8
TP		 2177 if (crb_entry->crb_strd.state_index_a) {
2178 index = crb_entry->crb_strd.state_index_a;
2179 addr = tmplt_hdr->saved_state_array[index];
2180 } else {
2181 addr = crb_addr;
2182 }
2183
2184 if (crb_entry->crb_ctrl.state_index_v) {
2185 index = crb_entry->crb_ctrl.state_index_v;
2186 read_value =
2187 tmplt_hdr->saved_state_array[index];
2188 } else {
2189 read_value = crb_entry->value_1;
2190 }
2191
33693c7a 2192 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
de8c72da 2193 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
068237c8
TP		 2194 }
2195
de8c72da 2196 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
068237c8
TP		 2197 index = crb_entry->crb_ctrl.state_index_v;
2198 read_value = tmplt_hdr->saved_state_array[index];
2199 read_value <<= crb_entry->crb_ctrl.shl;
2200 read_value >>= crb_entry->crb_ctrl.shr;
2201 if (crb_entry->value_2)
2202 read_value &= crb_entry->value_2;
2203 read_value |= crb_entry->value_3;
2204 read_value += crb_entry->value_1;
2205 tmplt_hdr->saved_state_array[index] = read_value;
de8c72da 2206 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
068237c8
TP		 2207 }
2208 crb_addr += crb_entry->crb_strd.addr_stride;
2209 }
2210 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2211 return rval;
2212}
2213
2214static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
7664a1fd 2215 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2216 uint32_t **d_ptr)
2217{
2218 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
7664a1fd 2219 struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
068237c8
TP		 2220 uint32_t *data_ptr = *d_ptr;
2221
2222 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2223 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
068237c8
TP		 2224 r_addr = ocm_hdr->read_addr;
2225 r_stride = ocm_hdr->read_addr_stride;
2226 loop_cnt = ocm_hdr->op_count;
2227
2228 DEBUG2(ql4_printk(KERN_INFO, ha,
2229 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2230 __func__, r_addr, r_stride, loop_cnt));
2231
2232 for (i = 0; i < loop_cnt; i++) {
2233 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2234 *data_ptr++ = cpu_to_le32(r_value);
2235 r_addr += r_stride;
2236 }
2237 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
26fdf922 2238 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
068237c8
TP		 2239 *d_ptr = data_ptr;
2240}
2241
2242static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
7664a1fd 2243 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2244 uint32_t **d_ptr)
2245{
2246 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
7664a1fd 2247 struct qla8xxx_minidump_entry_mux *mux_hdr;
068237c8
TP		 2248 uint32_t *data_ptr = *d_ptr;
2249
2250 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2251 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
068237c8
TP		 2252 r_addr = mux_hdr->read_addr;
2253 s_addr = mux_hdr->select_addr;
2254 s_stride = mux_hdr->select_value_stride;
2255 s_value = mux_hdr->select_value;
2256 loop_cnt = mux_hdr->op_count;
2257
2258 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 2259 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2260 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 2261 *data_ptr++ = cpu_to_le32(s_value);
2262 *data_ptr++ = cpu_to_le32(r_value);
2263 s_value += s_stride;
2264 }
2265 *d_ptr = data_ptr;
2266}
2267
2268static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
7664a1fd 2269 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2270 uint32_t **d_ptr)
2271{
2272 uint32_t addr, r_addr, c_addr, t_r_addr;
2273 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2274 uint32_t c_value_w;
7664a1fd 2275 struct qla8xxx_minidump_entry_cache *cache_hdr;
068237c8
TP		 2276 uint32_t *data_ptr = *d_ptr;
2277
7664a1fd 2278 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
068237c8
TP		 2279 loop_count = cache_hdr->op_count;
2280 r_addr = cache_hdr->read_addr;
2281 c_addr = cache_hdr->control_addr;
2282 c_value_w = cache_hdr->cache_ctrl.write_value;
2283
2284 t_r_addr = cache_hdr->tag_reg_addr;
2285 t_value = cache_hdr->addr_ctrl.init_tag_value;
2286 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2287
2288 for (i = 0; i < loop_count; i++) {
33693c7a
VC		 2289 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2290 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
068237c8
TP		 2291 addr = r_addr;
2292 for (k = 0; k < r_cnt; k++) {
33693c7a 2293 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
068237c8
TP		 2294 *data_ptr++ = cpu_to_le32(r_value);
2295 addr += cache_hdr->read_ctrl.read_addr_stride;
2296 }
2297 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2298 }
2299 *d_ptr = data_ptr;
2300}
2301
2302static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
7664a1fd 2303 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2304 uint32_t **d_ptr)
2305{
2306 uint32_t s_addr, r_addr;
2307 uint32_t r_stride, r_value, r_cnt, qid = 0;
2308 uint32_t i, k, loop_cnt;
7664a1fd 2309 struct qla8xxx_minidump_entry_queue *q_hdr;
068237c8
TP		 2310 uint32_t *data_ptr = *d_ptr;
2311
2312 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2313 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
068237c8
TP		 2314 s_addr = q_hdr->select_addr;
2315 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2316 r_stride = q_hdr->rd_strd.read_addr_stride;
2317 loop_cnt = q_hdr->op_count;
2318
2319 for (i = 0; i < loop_cnt; i++) {
33693c7a 2320 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
068237c8
TP		 2321 r_addr = q_hdr->read_addr;
2322 for (k = 0; k < r_cnt; k++) {
33693c7a 2323 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 2324 *data_ptr++ = cpu_to_le32(r_value);
2325 r_addr += r_stride;
2326 }
2327 qid += q_hdr->q_strd.queue_id_stride;
2328 }
2329 *d_ptr = data_ptr;
2330}
2331
2332#define MD_DIRECT_ROM_WINDOW 0x42110030
2333#define MD_DIRECT_ROM_READ_BASE 0x42150000
2334
f8086f4f 2335static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
7664a1fd 2336 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2337 uint32_t **d_ptr)
2338{
2339 uint32_t r_addr, r_value;
2340 uint32_t i, loop_cnt;
7664a1fd 2341 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
068237c8
TP		 2342 uint32_t *data_ptr = *d_ptr;
2343
2344 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2345 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
068237c8
TP		 2346 r_addr = rom_hdr->read_addr;
2347 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2348
2349 DEBUG2(ql4_printk(KERN_INFO, ha,
2350 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2351 __func__, r_addr, loop_cnt));
2352
2353 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 2354 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2355 (r_addr & 0xFFFF0000));
2356 ha->isp_ops->rd_reg_indirect(ha,
2357 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2358 &r_value);
068237c8
TP		 2359 *data_ptr++ = cpu_to_le32(r_value);
2360 r_addr += sizeof(uint32_t);
2361 }
2362 *d_ptr = data_ptr;
2363}
2364
2365#define MD_MIU_TEST_AGT_CTRL 0x41000090
2366#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
2367#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
2368
41f79bde 2369static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
7664a1fd 2370 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2371 uint32_t **d_ptr)
2372{
2373 uint32_t r_addr, r_value, r_data;
2374 uint32_t i, j, loop_cnt;
7664a1fd 2375 struct qla8xxx_minidump_entry_rdmem *m_hdr;
068237c8
TP		 2376 unsigned long flags;
2377 uint32_t *data_ptr = *d_ptr;
2378
2379 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2380 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
068237c8
TP		 2381 r_addr = m_hdr->read_addr;
2382 loop_cnt = m_hdr->read_data_size/16;
2383
2384 DEBUG2(ql4_printk(KERN_INFO, ha,
2385 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2386 __func__, r_addr, m_hdr->read_data_size));
2387
2388 if (r_addr & 0xf) {
2389 DEBUG2(ql4_printk(KERN_INFO, ha,
cf2fbdd2 2390 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
068237c8
TP		 2391 __func__, r_addr));
2392 return QLA_ERROR;
2393 }
2394
2395 if (m_hdr->read_data_size % 16) {
2396 DEBUG2(ql4_printk(KERN_INFO, ha,
2397 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2398 __func__, m_hdr->read_data_size));
2399 return QLA_ERROR;
2400 }
2401
2402 DEBUG2(ql4_printk(KERN_INFO, ha,
2403 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2404 __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2405
2406 write_lock_irqsave(&ha->hw_lock, flags);
2407 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 2408 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2409 r_addr);
068237c8 2410 r_value = 0;
33693c7a
VC		 2411 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2412 r_value);
068237c8 2413 r_value = MIU_TA_CTL_ENABLE;
33693c7a 2414 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
c38fa3ab 2415 r_value = MIU_TA_CTL_START_ENABLE;
33693c7a 2416 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
068237c8
TP		 2417
2418 for (j = 0; j < MAX_CTL_CHECK; j++) {
33693c7a
VC		 2419 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2420 &r_value);
068237c8
TP		 2421 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2422 break;
2423 }
2424
2425 if (j >= MAX_CTL_CHECK) {
2426 printk_ratelimited(KERN_ERR
2427 "%s: failed to read through agent\n",
2428 __func__);
2429 write_unlock_irqrestore(&ha->hw_lock, flags);
2430 return QLA_SUCCESS;
2431 }
2432
2433 for (j = 0; j < 4; j++) {
33693c7a
VC		 2434 ha->isp_ops->rd_reg_indirect(ha,
2435 MD_MIU_TEST_AGT_RDDATA[j],
2436 &r_data);
068237c8
TP		 2437 *data_ptr++ = cpu_to_le32(r_data);
2438 }
2439
2440 r_addr += 16;
2441 }
2442 write_unlock_irqrestore(&ha->hw_lock, flags);
2443
2444 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2445 __func__, (loop_cnt * 16)));
2446
2447 *d_ptr = data_ptr;
2448 return QLA_SUCCESS;
2449}
2450
41f79bde
SV		 2451static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2452 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2453 uint32_t **d_ptr)
2454{
2455 uint32_t *data_ptr = *d_ptr;
2456 int rval = QLA_SUCCESS;
2457
2458 if (is_qla8032(ha) || is_qla8042(ha)) {
2459 rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr,
2460 &data_ptr);
2461 if (rval != QLA_SUCCESS) {
2462 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2463 &data_ptr);
2464 }
2465 } else {
2466 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2467 &data_ptr);
2468 }
2469 *d_ptr = data_ptr;
2470 return rval;
2471}
2472
5e9bcec7 2473static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
7664a1fd 2474 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2475 int index)
2476{
de8c72da 2477 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
068237c8
TP		 2478 DEBUG2(ql4_printk(KERN_INFO, ha,
2479 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2480 ha->host_no, index, entry_hdr->entry_type,
2481 entry_hdr->d_ctrl.entry_capture_mask));
58e2bbe9
TP		 2482 /* If driver encounters a new entry type that it cannot process,
2483 * it should just skip the entry and adjust the total buffer size by
2484 * from subtracting the skipped bytes from it
2485 */
2486 ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
068237c8
TP		 2487}
2488
6e7b4292
VC		 2489/* ISP83xx functions to process new minidump entries... */
2490static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2491 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2492 uint32_t **d_ptr)
2493{
2494 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2495 uint16_t s_stride, i;
2496 uint32_t *data_ptr = *d_ptr;
2497 uint32_t rval = QLA_SUCCESS;
2498 struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2499
2500 pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2501 s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2502 r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2503 s_value = le32_to_cpu(pollrd_hdr->select_value);
2504 s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2505
2506 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2507 poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2508
2509 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2510 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2511 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2512 while (1) {
2513 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2514
2515 if ((r_value & poll_mask) != 0) {
2516 break;
2517 } else {
2518 msleep(1);
2519 if (--poll_wait == 0) {
2520 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2521 __func__);
2522 rval = QLA_ERROR;
2523 goto exit_process_pollrd;
2524 }
2525 }
2526 }
2527 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2528 *data_ptr++ = cpu_to_le32(s_value);
2529 *data_ptr++ = cpu_to_le32(r_value);
2530 s_value += s_stride;
2531 }
2532
2533 *d_ptr = data_ptr;
2534
2535exit_process_pollrd:
2536 return rval;
2537}
2538
b1829789
TP		 2539static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
2540 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2541 uint32_t **d_ptr)
2542{
2543 int loop_cnt;
2544 uint32_t addr1, addr2, value, data, temp, wrval;
2545 uint8_t stride, stride2;
2546 uint16_t count;
2547 uint32_t poll, mask, data_size, modify_mask;
2548 uint32_t wait_count = 0;
2549 uint32_t *data_ptr = *d_ptr;
2550 struct qla8044_minidump_entry_rddfe *rddfe;
2551 uint32_t rval = QLA_SUCCESS;
2552
2553 rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
2554 addr1 = le32_to_cpu(rddfe->addr_1);
2555 value = le32_to_cpu(rddfe->value);
2556 stride = le32_to_cpu(rddfe->stride);
2557 stride2 = le32_to_cpu(rddfe->stride2);
2558 count = le32_to_cpu(rddfe->count);
2559
2560 poll = le32_to_cpu(rddfe->poll);
2561 mask = le32_to_cpu(rddfe->mask);
2562 modify_mask = le32_to_cpu(rddfe->modify_mask);
2563 data_size = le32_to_cpu(rddfe->data_size);
2564
2565 addr2 = addr1 + stride;
2566
2567 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
2568 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
2569
2570 wait_count = 0;
2571 while (wait_count < poll) {
2572 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2573 if ((temp & mask) != 0)
2574 break;
2575 wait_count++;
2576 }
2577
2578 if (wait_count == poll) {
2579 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2580 rval = QLA_ERROR;
2581 goto exit_process_rddfe;
2582 } else {
2583 ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
2584 temp = temp & modify_mask;
2585 temp = (temp | ((loop_cnt << 16) | loop_cnt));
2586 wrval = ((temp << 16) | temp);
2587
2588 ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
2589 ha->isp_ops->wr_reg_indirect(ha, addr1, value);
2590
2591 wait_count = 0;
2592 while (wait_count < poll) {
2593 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2594 if ((temp & mask) != 0)
2595 break;
2596 wait_count++;
2597 }
2598 if (wait_count == poll) {
2599 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2600 __func__);
2601 rval = QLA_ERROR;
2602 goto exit_process_rddfe;
2603 }
2604
2605 ha->isp_ops->wr_reg_indirect(ha, addr1,
2606 ((0x40000000 | value) +
2607 stride2));
2608 wait_count = 0;
2609 while (wait_count < poll) {
2610 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2611 if ((temp & mask) != 0)
2612 break;
2613 wait_count++;
2614 }
2615
2616 if (wait_count == poll) {
2617 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2618 __func__);
2619 rval = QLA_ERROR;
2620 goto exit_process_rddfe;
2621 }
2622
2623 ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
2624
2625 *data_ptr++ = cpu_to_le32(wrval);
2626 *data_ptr++ = cpu_to_le32(data);
2627 }
2628 }
2629
2630 *d_ptr = data_ptr;
2631exit_process_rddfe:
2632 return rval;
2633}
2634
2635static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
2636 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2637 uint32_t **d_ptr)
2638{
2639 int rval = QLA_SUCCESS;
2640 uint32_t addr1, addr2, value1, value2, data, selval;
2641 uint8_t stride1, stride2;
2642 uint32_t addr3, addr4, addr5, addr6, addr7;
2643 uint16_t count, loop_cnt;
2644 uint32_t poll, mask;
2645 uint32_t *data_ptr = *d_ptr;
2646 struct qla8044_minidump_entry_rdmdio *rdmdio;
2647
2648 rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
2649 addr1 = le32_to_cpu(rdmdio->addr_1);
2650 addr2 = le32_to_cpu(rdmdio->addr_2);
2651 value1 = le32_to_cpu(rdmdio->value_1);
2652 stride1 = le32_to_cpu(rdmdio->stride_1);
2653 stride2 = le32_to_cpu(rdmdio->stride_2);
2654 count = le32_to_cpu(rdmdio->count);
2655
2656 poll = le32_to_cpu(rdmdio->poll);
2657 mask = le32_to_cpu(rdmdio->mask);
2658 value2 = le32_to_cpu(rdmdio->value_2);
2659
2660 addr3 = addr1 + stride1;
2661
2662 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
2663 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2664 addr3, mask);
2665 if (rval)
2666 goto exit_process_rdmdio;
2667
2668 addr4 = addr2 - stride1;
2669 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
2670 value2);
2671 if (rval)
2672 goto exit_process_rdmdio;
2673
2674 addr5 = addr2 - (2 * stride1);
2675 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
2676 value1);
2677 if (rval)
2678 goto exit_process_rdmdio;
2679
2680 addr6 = addr2 - (3 * stride1);
2681 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
2682 addr6, 0x2);
2683 if (rval)
2684 goto exit_process_rdmdio;
2685
2686 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2687 addr3, mask);
2688 if (rval)
2689 goto exit_process_rdmdio;
2690
2691 addr7 = addr2 - (4 * stride1);
2692 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
2693 mask, addr7, &data);
2694 if (rval)
2695 goto exit_process_rdmdio;
2696
2697 selval = (value2 << 18) | (value1 << 2) | 2;
2698
2699 stride2 = le32_to_cpu(rdmdio->stride_2);
2700 *data_ptr++ = cpu_to_le32(selval);
2701 *data_ptr++ = cpu_to_le32(data);
2702
2703 value1 = value1 + stride2;
2704 *d_ptr = data_ptr;
2705 }
2706
2707exit_process_rdmdio:
2708 return rval;
2709}
2710
2711static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
2712 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2713 uint32_t **d_ptr)
2714{
2715 uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
2716 struct qla8044_minidump_entry_pollwr *pollwr_hdr;
2717 uint32_t wait_count = 0;
2718 uint32_t rval = QLA_SUCCESS;
2719
2720 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
2721 addr1 = le32_to_cpu(pollwr_hdr->addr_1);
2722 addr2 = le32_to_cpu(pollwr_hdr->addr_2);
2723 value1 = le32_to_cpu(pollwr_hdr->value_1);
2724 value2 = le32_to_cpu(pollwr_hdr->value_2);
2725
2726 poll = le32_to_cpu(pollwr_hdr->poll);
2727 mask = le32_to_cpu(pollwr_hdr->mask);
2728
2729 while (wait_count < poll) {
2730 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2731
2732 if ((r_value & poll) != 0)
2733 break;
2734
2735 wait_count++;
2736 }
2737
2738 if (wait_count == poll) {
2739 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2740 rval = QLA_ERROR;
2741 goto exit_process_pollwr;
2742 }
2743
2744 ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
2745 ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
2746
2747 wait_count = 0;
2748 while (wait_count < poll) {
2749 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2750
2751 if ((r_value & poll) != 0)
2752 break;
2753 wait_count++;
2754 }
2755
2756exit_process_pollwr:
2757 return rval;
2758}
2759
6e7b4292
VC		 2760static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2761 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2762 uint32_t **d_ptr)
2763{
2764 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2765 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2766 struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2767 uint32_t *data_ptr = *d_ptr;
2768
2769 rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2770 sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2771 sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2772 sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2773 sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2774 sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2775 read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2776
2777 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2778 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2779 t_sel_val = sel_val1 & sel_val_mask;
2780 *data_ptr++ = cpu_to_le32(t_sel_val);
2781
2782 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2783 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2784
2785 *data_ptr++ = cpu_to_le32(data);
2786
2787 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2788 t_sel_val = sel_val2 & sel_val_mask;
2789 *data_ptr++ = cpu_to_le32(t_sel_val);
2790
2791 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2792 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2793
2794 *data_ptr++ = cpu_to_le32(data);
2795
2796 sel_val1 += rdmux2_hdr->select_value_stride;
2797 sel_val2 += rdmux2_hdr->select_value_stride;
2798 }
2799
2800 *d_ptr = data_ptr;
2801}
2802
2803static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2804 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2805 uint32_t **d_ptr)
2806{
2807 uint32_t poll_wait, poll_mask, r_value, data;
2808 uint32_t addr_1, addr_2, value_1, value_2;
2809 uint32_t *data_ptr = *d_ptr;
2810 uint32_t rval = QLA_SUCCESS;
2811 struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2812
2813 poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2814 addr_1 = le32_to_cpu(poll_hdr->addr_1);
2815 addr_2 = le32_to_cpu(poll_hdr->addr_2);
2816 value_1 = le32_to_cpu(poll_hdr->value_1);
2817 value_2 = le32_to_cpu(poll_hdr->value_2);
2818 poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2819
2820 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2821
2822 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2823 while (1) {
2824 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2825
2826 if ((r_value & poll_mask) != 0) {
2827 break;
2828 } else {
2829 msleep(1);
2830 if (--poll_wait == 0) {
2831 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2832 __func__);
2833 rval = QLA_ERROR;
2834 goto exit_process_pollrdmwr;
2835 }
2836 }
2837 }
2838
2839 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2840 data &= le32_to_cpu(poll_hdr->modify_mask);
2841 ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2842 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2843
2844 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2845 while (1) {
2846 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2847
2848 if ((r_value & poll_mask) != 0) {
2849 break;
2850 } else {
2851 msleep(1);
2852 if (--poll_wait == 0) {
2853 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2854 __func__);
2855 rval = QLA_ERROR;
2856 goto exit_process_pollrdmwr;
2857 }
2858 }
2859 }
2860
2861 *data_ptr++ = cpu_to_le32(addr_2);
2862 *data_ptr++ = cpu_to_le32(data);
2863 *d_ptr = data_ptr;
2864
2865exit_process_pollrdmwr:
2866 return rval;
2867}
2868
2869static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2870 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2871 uint32_t **d_ptr)
2872{
2873 uint32_t fl_addr, u32_count, rval;
2874 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2875 uint32_t *data_ptr = *d_ptr;
2876
2877 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2878 fl_addr = le32_to_cpu(rom_hdr->read_addr);
2879 u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2880
2881 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2882 __func__, fl_addr, u32_count));
2883
2884 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2885 (u8 *)(data_ptr), u32_count);
2886
2887 if (rval == QLA_ERROR) {
2888 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2889 __func__, u32_count);
2890 goto exit_process_rdrom;
2891 }
2892
2893 data_ptr += u32_count;
2894 *d_ptr = data_ptr;
2895
2896exit_process_rdrom:
2897 return rval;
2898}
2899
068237c8 2900/**
f8086f4f 2901 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
068237c8
TP		 2902 * @ha: pointer to adapter structure
2903 **/
2904static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2905{
2906 int num_entry_hdr = 0;
7664a1fd 2907 struct qla8xxx_minidump_entry_hdr *entry_hdr;
068237c8
TP		 2908 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2909 uint32_t *data_ptr;
2910 uint32_t data_collected = 0;
2911 int i, rval = QLA_ERROR;
2912 uint64_t now;
2913 uint32_t timestamp;
2914
58e2bbe9 2915 ha->fw_dump_skip_size = 0;
068237c8
TP		 2916 if (!ha->fw_dump) {
2917 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2918 __func__, ha->host_no);
2919 return rval;
2920 }
2921
2922 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2923 ha->fw_dump_tmplt_hdr;
2924 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2925 ha->fw_dump_tmplt_size);
2926 data_collected += ha->fw_dump_tmplt_size;
2927
2928 num_entry_hdr = tmplt_hdr->num_of_entries;
2929 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2930 __func__, data_ptr);
2931 ql4_printk(KERN_INFO, ha,
2932 "[%s]: no of entry headers in Template: 0x%x\n",
2933 __func__, num_entry_hdr);
2934 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2935 __func__, ha->fw_dump_capture_mask);
2936 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2937 __func__, ha->fw_dump_size, ha->fw_dump_size);
2938
2939 /* Update current timestamp before taking dump */
2940 now = get_jiffies_64();
2941 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2942 tmplt_hdr->driver_timestamp = timestamp;
2943
7664a1fd 2944 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
068237c8
TP		 2945 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2946 tmplt_hdr->first_entry_offset);
2947
b37ca418 2948 if (is_qla8032(ha) || is_qla8042(ha))
6e7b4292
VC		 2949 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2950 tmplt_hdr->ocm_window_reg[ha->func_num];
2951
068237c8
TP		 2952 /* Walk through the entry headers - validate/perform required action */
2953 for (i = 0; i < num_entry_hdr; i++) {
4812d070 2954 if (data_collected > ha->fw_dump_size) {
068237c8
TP		 2955 ql4_printk(KERN_INFO, ha,
2956 "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2957 data_collected, ha->fw_dump_size);
2958 return rval;
2959 }
2960
2961 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2962 ha->fw_dump_capture_mask)) {
2963 entry_hdr->d_ctrl.driver_flags |=
de8c72da 2964 QLA8XXX_DBG_SKIPPED_FLAG;
068237c8
TP		 2965 goto skip_nxt_entry;
2966 }
2967
2968 DEBUG2(ql4_printk(KERN_INFO, ha,
2969 "Data collected: [0x%x], Dump size left:[0x%x]\n",
2970 data_collected,
2971 (ha->fw_dump_size - data_collected)));
2972
2973 /* Decode the entry type and take required action to capture
2974 * debug data
2975 */
2976 switch (entry_hdr->entry_type) {
de8c72da 2977 case QLA8XXX_RDEND:
5e9bcec7 2978 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8 2979 break;
de8c72da 2980 case QLA8XXX_CNTRL:
068237c8
TP		 2981 rval = qla4_8xxx_minidump_process_control(ha,
2982 entry_hdr);
2983 if (rval != QLA_SUCCESS) {
5e9bcec7 2984 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2985 goto md_failed;
2986 }
2987 break;
de8c72da 2988 case QLA8XXX_RDCRB:
068237c8
TP		 2989 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2990 &data_ptr);
2991 break;
de8c72da 2992 case QLA8XXX_RDMEM:
068237c8
TP		 2993 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2994 &data_ptr);
2995 if (rval != QLA_SUCCESS) {
5e9bcec7 2996 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2997 goto md_failed;
2998 }
2999 break;
de8c72da
VC		 3000 case QLA8XXX_BOARD:
3001 case QLA8XXX_RDROM:
6e7b4292
VC		 3002 if (is_qla8022(ha)) {
3003 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
3004 &data_ptr);
b37ca418 3005 } else if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3006 rval = qla4_83xx_minidump_process_rdrom(ha,
3007 entry_hdr,
3008 &data_ptr);
3009 if (rval != QLA_SUCCESS)
3010 qla4_8xxx_mark_entry_skipped(ha,
3011 entry_hdr,
3012 i);
3013 }
068237c8 3014 break;
de8c72da
VC		 3015 case QLA8XXX_L2DTG:
3016 case QLA8XXX_L2ITG:
3017 case QLA8XXX_L2DAT:
3018 case QLA8XXX_L2INS:
068237c8
TP		 3019 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
3020 &data_ptr);
3021 if (rval != QLA_SUCCESS) {
5e9bcec7 3022 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 3023 goto md_failed;
3024 }
3025 break;
6e7b4292
VC		 3026 case QLA8XXX_L1DTG:
3027 case QLA8XXX_L1ITG:
de8c72da
VC		 3028 case QLA8XXX_L1DAT:
3029 case QLA8XXX_L1INS:
068237c8
TP		 3030 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
3031 &data_ptr);
3032 break;
de8c72da 3033 case QLA8XXX_RDOCM:
068237c8
TP		 3034 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
3035 &data_ptr);
3036 break;
de8c72da 3037 case QLA8XXX_RDMUX:
068237c8
TP		 3038 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
3039 &data_ptr);
3040 break;
de8c72da 3041 case QLA8XXX_QUEUE:
068237c8
TP		 3042 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
3043 &data_ptr);
3044 break;
6e7b4292 3045 case QLA83XX_POLLRD:
b37ca418 3046 if (is_qla8022(ha)) {
6e7b4292
VC		 3047 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3048 break;
3049 }
3050 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
3051 &data_ptr);
3052 if (rval != QLA_SUCCESS)
3053 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3054 break;
3055 case QLA83XX_RDMUX2:
b37ca418 3056 if (is_qla8022(ha)) {
6e7b4292
VC		 3057 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3058 break;
3059 }
3060 qla83xx_minidump_process_rdmux2(ha, entry_hdr,
3061 &data_ptr);
3062 break;
3063 case QLA83XX_POLLRDMWR:
b37ca418 3064 if (is_qla8022(ha)) {
6e7b4292
VC		 3065 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3066 break;
3067 }
3068 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
3069 &data_ptr);
3070 if (rval != QLA_SUCCESS)
3071 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3072 break;
b1829789
TP		 3073 case QLA8044_RDDFE:
3074 rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
3075 &data_ptr);
3076 if (rval != QLA_SUCCESS)
3077 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3078 break;
3079 case QLA8044_RDMDIO:
3080 rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
3081 &data_ptr);
3082 if (rval != QLA_SUCCESS)
3083 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3084 break;
3085 case QLA8044_POLLWR:
3086 rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
3087 &data_ptr);
3088 if (rval != QLA_SUCCESS)
3089 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3090 break;
de8c72da 3091 case QLA8XXX_RDNOP:
068237c8 3092 default:
5e9bcec7 3093 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 3094 break;
3095 }
3096
4812d070 3097 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
068237c8
TP		 3098skip_nxt_entry:
3099 /* next entry in the template */
7664a1fd 3100 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
068237c8
TP		 3101 (((uint8_t *)entry_hdr) +
3102 entry_hdr->entry_size);
3103 }
3104
58e2bbe9 3105 if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
068237c8
TP		 3106 ql4_printk(KERN_INFO, ha,
3107 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
3108 data_collected, ha->fw_dump_size);
35a9c2ab 3109 rval = QLA_ERROR;
068237c8
TP		 3110 goto md_failed;
3111 }
3112
3113 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
3114 __func__, i));
3115md_failed:
3116 return rval;
3117}
3118
3119/**
3120 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
3121 * @ha: pointer to adapter structure
3122 **/
3123static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
3124{
3125 char event_string[40];
3126 char *envp[] = { event_string, NULL };
3127
3128 switch (code) {
3129 case QL4_UEVENT_CODE_FW_DUMP:
3130 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3131 ha->host_no);
3132 break;
3133 default:
3134 /*do nothing*/
3135 break;
3136 }
3137
3138 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
3139}
3140
6e7b4292 3141void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
aec07cae
VC		 3142{
3143 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
3144 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
3145 if (!qla4_8xxx_collect_md_data(ha)) {
3146 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
3147 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
3148 } else {
3149 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
3150 __func__);
3151 }
3152 }
3153}
3154
f4f5df23
VC		 3155/**
3156 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
3157 * @ha: pointer to adapter structure
3158 *
3159 * Note: IDC lock must be held upon entry
3160 **/
6e7b4292 3161int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
f4f5df23 3162{
b25ee66f 3163 int rval = QLA_ERROR;
32436aaa 3164 int i;
80645dc0 3165 uint32_t old_count, count;
4ebbb5cf 3166 int need_reset = 0;
f4f5df23 3167
33693c7a 3168 need_reset = ha->isp_ops->need_reset(ha);
b25ee66f
SS		 3169
3170 if (need_reset) {
3171 /* We are trying to perform a recovery here. */
4ebbb5cf 3172 if (test_bit(AF_FW_RECOVERY, &ha->flags))
33693c7a 3173 ha->isp_ops->rom_lock_recovery(ha);
b25ee66f 3174 } else {
4ebbb5cf
VC		 3175 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
3176 for (i = 0; i < 10; i++) {
3177 msleep(200);
3178 count = qla4_8xxx_rd_direct(ha,
3179 QLA8XXX_PEG_ALIVE_COUNTER);
3180 if (count != old_count) {
3181 rval = QLA_SUCCESS;
3182 goto dev_ready;
3183 }
b25ee66f 3184 }
4ebbb5cf 3185 ha->isp_ops->rom_lock_recovery(ha);
f4f5df23
VC		 3186 }
3187
f4f5df23
VC		 3188 /* set to DEV_INITIALIZING */
3189 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
33693c7a
VC		 3190 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3191 QLA8XXX_DEV_INITIALIZING);
f4f5df23 3192
33693c7a 3193 ha->isp_ops->idc_unlock(ha);
6e7b4292
VC		 3194
3195 if (is_qla8022(ha))
3196 qla4_8xxx_get_minidump(ha);
3197
33693c7a
VC		 3198 rval = ha->isp_ops->restart_firmware(ha);
3199 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 3200
3201 if (rval != QLA_SUCCESS) {
3202 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3203 qla4_8xxx_clear_drv_active(ha);
33693c7a
VC		 3204 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3205 QLA8XXX_DEV_FAILED);
f4f5df23
VC		 3206 return rval;
3207 }
3208
3209dev_ready:
3210 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
33693c7a 3211 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
f4f5df23 3212
b25ee66f 3213 return rval;
f4f5df23
VC		 3214}
3215
3216/**
f8086f4f 3217 * qla4_82xx_need_reset_handler - Code to start reset sequence
f4f5df23
VC		 3218 * @ha: pointer to adapter structure
3219 *
3220 * Note: IDC lock must be held upon entry
3221 **/
3222static void
f8086f4f 3223qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
f4f5df23
VC		 3224{
3225 uint32_t dev_state, drv_state, drv_active;
068237c8 3226 uint32_t active_mask = 0xFFFFFFFF;
f4f5df23
VC		 3227 unsigned long reset_timeout;
3228
3229 ql4_printk(KERN_INFO, ha,
3230 "Performing ISP error recovery\n");
3231
3232 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
f8086f4f 3233 qla4_82xx_idc_unlock(ha);
f4f5df23 3234 ha->isp_ops->disable_intrs(ha);
f8086f4f 3235 qla4_82xx_idc_lock(ha);
f4f5df23
VC		 3236 }
3237
de8c72da 3238 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
068237c8
TP		 3239 DEBUG2(ql4_printk(KERN_INFO, ha,
3240 "%s(%ld): reset acknowledged\n",
3241 __func__, ha->host_no));
3242 qla4_8xxx_set_rst_ready(ha);
3243 } else {
3244 active_mask = (~(1 << (ha->func_num * 4)));
3245 }
f4f5df23
VC		 3246
3247 /* wait for 10 seconds for reset ack from all functions */
3248 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3249
f8086f4f
VC		 3250 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3251 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
f4f5df23
VC		 3252
3253 ql4_printk(KERN_INFO, ha,
3254 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3255 __func__, ha->host_no, drv_state, drv_active);
3256
068237c8 3257 while (drv_state != (drv_active & active_mask)) {
f4f5df23 3258 if (time_after_eq(jiffies, reset_timeout)) {
068237c8
TP		 3259 ql4_printk(KERN_INFO, ha,
3260 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
3261 DRIVER_NAME, drv_state, drv_active);
f4f5df23
VC		 3262 break;
3263 }
3264
068237c8
TP		 3265 /*
3266 * When reset_owner times out, check which functions
3267 * acked/did not ack
3268 */
de8c72da 3269 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
068237c8
TP		 3270 ql4_printk(KERN_INFO, ha,
3271 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3272 __func__, ha->host_no, drv_state,
3273 drv_active);
3274 }
f8086f4f 3275 qla4_82xx_idc_unlock(ha);
f4f5df23 3276 msleep(1000);
f8086f4f 3277 qla4_82xx_idc_lock(ha);
f4f5df23 3278
f8086f4f
VC		 3279 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3280 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
f4f5df23
VC		 3281 }
3282
068237c8 3283 /* Clear RESET OWNER as we are not going to use it any further */
de8c72da 3284 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
068237c8 3285
f8086f4f 3286 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
068237c8
TP		 3287 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
3288 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
f4f5df23
VC		 3289
3290 /* Force to DEV_COLD unless someone else is starting a reset */
de8c72da 3291 if (dev_state != QLA8XXX_DEV_INITIALIZING) {
f4f5df23 3292 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
de8c72da 3293 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
068237c8 3294 qla4_8xxx_set_rst_ready(ha);
f4f5df23
VC		 3295 }
3296}
3297
3298/**
3299 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
3300 * @ha: pointer to adapter structure
3301 **/
3302void
3303qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
3304{
33693c7a 3305 ha->isp_ops->idc_lock(ha);
f4f5df23 3306 qla4_8xxx_set_qsnt_ready(ha);
33693c7a 3307 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 3308}
3309
83dbdf6f
VC		 3310static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
3311{
3312 int idc_ver;
3313 uint32_t drv_active;
3314
3315 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3316 if (drv_active == (1 << (ha->func_num * 4))) {
3317 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3318 QLA82XX_IDC_VERSION);
3319 ql4_printk(KERN_INFO, ha,
3320 "%s: IDC version updated to %d\n", __func__,
3321 QLA82XX_IDC_VERSION);
3322 } else {
3323 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3324 if (QLA82XX_IDC_VERSION != idc_ver) {
3325 ql4_printk(KERN_INFO, ha,
3326 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3327 __func__, QLA82XX_IDC_VERSION, idc_ver);
3328 }
3329 }
3330}
3331
6e7b4292 3332static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
83dbdf6f 3333{
6e7b4292
VC		 3334 int idc_ver;
3335 uint32_t drv_active;
3336 int rval = QLA_SUCCESS;
3337
3338 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3339 if (drv_active == (1 << ha->func_num)) {
3340 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3341 idc_ver &= (~0xFF);
3342 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3343 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3344 ql4_printk(KERN_INFO, ha,
3345 "%s: IDC version updated to %d\n", __func__,
ecca5120 3346 idc_ver);
6e7b4292
VC		 3347 } else {
3348 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3349 idc_ver &= 0xFF;
3350 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3351 ql4_printk(KERN_INFO, ha,
3352 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3353 __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3354 idc_ver);
3355 rval = QLA_ERROR;
3356 goto exit_set_idc_ver;
3357 }
3358 }
3359
3360 /* Update IDC_MINOR_VERSION */
3361 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3362 idc_ver &= ~(0x03 << (ha->func_num * 2));
3363 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3364 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3365
3366exit_set_idc_ver:
3367 return rval;
3368}
3369
39c95826 3370int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
6e7b4292
VC		 3371{
3372 uint32_t drv_active;
3373 int rval = QLA_SUCCESS;
3374
3375 if (test_bit(AF_INIT_DONE, &ha->flags))
3376 goto exit_update_idc_reg;
3377
3378 ha->isp_ops->idc_lock(ha);
3379 qla4_8xxx_set_drv_active(ha);
3380
3381 /*
3382 * If we are the first driver to load and
3383 * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3384 */
b37ca418 3385 if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3386 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3387 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3388 qla4_83xx_clear_idc_dontreset(ha);
3389 }
3390
3391 if (is_qla8022(ha)) {
83dbdf6f 3392 qla4_82xx_set_idc_ver(ha);
b37ca418 3393 } else if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3394 rval = qla4_83xx_set_idc_ver(ha);
3395 if (rval == QLA_ERROR)
3396 qla4_8xxx_clear_drv_active(ha);
83dbdf6f 3397 }
6e7b4292
VC		 3398
3399 ha->isp_ops->idc_unlock(ha);
3400
3401exit_update_idc_reg:
3402 return rval;
f4f5df23
VC		 3403}
3404
3405/**
3406 * qla4_8xxx_device_state_handler - Adapter state machine
3407 * @ha: pointer to host adapter structure.
3408 *
3409 * Note: IDC lock must be UNLOCKED upon entry
3410 **/
3411int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3412{
3413 uint32_t dev_state;
3414 int rval = QLA_SUCCESS;
3415 unsigned long dev_init_timeout;
3416
6e7b4292
VC		 3417 rval = qla4_8xxx_update_idc_reg(ha);
3418 if (rval == QLA_ERROR)
3419 goto exit_state_handler;
f4f5df23 3420
33693c7a 3421 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
068237c8
TP		 3422 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3423 dev_state, dev_state < MAX_STATES ?
3424 qdev_state[dev_state] : "Unknown"));
f4f5df23
VC		 3425
3426 /* wait for 30 seconds for device to go ready */
3427 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3428
33693c7a 3429 ha->isp_ops->idc_lock(ha);
f4f5df23 3430 while (1) {
f4f5df23
VC		 3431
3432 if (time_after_eq(jiffies, dev_init_timeout)) {
068237c8
TP		 3433 ql4_printk(KERN_WARNING, ha,
3434 "%s: Device Init Failed 0x%x = %s\n",
3435 DRIVER_NAME,
3436 dev_state, dev_state < MAX_STATES ?
3437 qdev_state[dev_state] : "Unknown");
33693c7a
VC		 3438 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3439 QLA8XXX_DEV_FAILED);
f4f5df23
VC		 3440 }
3441
33693c7a 3442 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
068237c8
TP		 3443 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3444 dev_state, dev_state < MAX_STATES ?
3445 qdev_state[dev_state] : "Unknown");
f4f5df23
VC		 3446
3447 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3448 switch (dev_state) {
de8c72da 3449 case QLA8XXX_DEV_READY:
f4f5df23 3450 goto exit;
de8c72da 3451 case QLA8XXX_DEV_COLD:
f4f5df23 3452 rval = qla4_8xxx_device_bootstrap(ha);
f4f5df23 3453 goto exit;
de8c72da 3454 case QLA8XXX_DEV_INITIALIZING:
33693c7a 3455 ha->isp_ops->idc_unlock(ha);
f4f5df23 3456 msleep(1000);
33693c7a 3457 ha->isp_ops->idc_lock(ha);
f4f5df23 3458 break;
de8c72da 3459 case QLA8XXX_DEV_NEED_RESET:
6e7b4292 3460 /*
b37ca418
VC		 3461 * For ISP8324 and ISP8042, if NEED_RESET is set by any
3462 * driver, it should be honored, irrespective of
3463 * IDC_CTRL DONTRESET_BIT0
6e7b4292 3464 */
b37ca418 3465 if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3466 qla4_83xx_need_reset_handler(ha);
3467 } else if (is_qla8022(ha)) {
3468 if (!ql4xdontresethba) {
3469 qla4_82xx_need_reset_handler(ha);
3470 /* Update timeout value after need
3471 * reset handler */
3472 dev_init_timeout = jiffies +
3473 (ha->nx_dev_init_timeout * HZ);
3474 } else {
3475 ha->isp_ops->idc_unlock(ha);
3476 msleep(1000);
3477 ha->isp_ops->idc_lock(ha);
3478 }
f4f5df23 3479 }
f4f5df23 3480 break;
de8c72da 3481 case QLA8XXX_DEV_NEED_QUIESCENT:
f4f5df23
VC		 3482 /* idc locked/unlocked in handler */
3483 qla4_8xxx_need_qsnt_handler(ha);
e3f37d16 3484 break;
de8c72da 3485 case QLA8XXX_DEV_QUIESCENT:
33693c7a 3486 ha->isp_ops->idc_unlock(ha);
f4f5df23 3487 msleep(1000);
33693c7a 3488 ha->isp_ops->idc_lock(ha);
f4f5df23 3489 break;
de8c72da 3490 case QLA8XXX_DEV_FAILED:
33693c7a 3491 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 3492 qla4xxx_dead_adapter_cleanup(ha);
3493 rval = QLA_ERROR;
33693c7a 3494 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 3495 goto exit;
3496 default:
33693c7a 3497 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 3498 qla4xxx_dead_adapter_cleanup(ha);
3499 rval = QLA_ERROR;
33693c7a 3500 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 3501 goto exit;
3502 }
3503 }
3504exit:
33693c7a 3505 ha->isp_ops->idc_unlock(ha);
6e7b4292 3506exit_state_handler:
f4f5df23
VC		 3507 return rval;
3508}
3509
3510int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3511{
3512 int retval;
78764999
SR		 3513
3514 /* clear the interrupt */
b37ca418 3515 if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3516 writel(0, &ha->qla4_83xx_reg->risc_intr);
3517 readl(&ha->qla4_83xx_reg->risc_intr);
3518 } else if (is_qla8022(ha)) {
3519 writel(0, &ha->qla4_82xx_reg->host_int);
3520 readl(&ha->qla4_82xx_reg->host_int);
3521 }
78764999 3522
f4f5df23
VC		 3523 retval = qla4_8xxx_device_state_handler(ha);
3524
1b3d399c
TP		 3525 /* Initialize request and response queues. */
3526 if (retval == QLA_SUCCESS)
3527 qla4xxx_init_rings(ha);
3528
137257da 3529 if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
f4f5df23 3530 retval = qla4xxx_request_irqs(ha);
f581a3f7 3531
f4f5df23
VC		 3532 return retval;
3533}
3534
3535/*****************************************************************************/
3536/* Flash Manipulation Routines */
3537/*****************************************************************************/
3538
3539#define OPTROM_BURST_SIZE 0x1000
3540#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3541
3542#define FARX_DATA_FLAG BIT_31
3543#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
3544#define FARX_ACCESS_FLASH_DATA 0x7FF00000
3545
3546static inline uint32_t
3547flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3548{
3549 return hw->flash_conf_off | faddr;
3550}
3551
3552static inline uint32_t
3553flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3554{
3555 return hw->flash_data_off | faddr;
3556}
3557
3558static uint32_t *
f8086f4f 3559qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
f4f5df23
VC		 3560 uint32_t faddr, uint32_t length)
3561{
3562 uint32_t i;
3563 uint32_t val;
3564 int loops = 0;
f8086f4f 3565 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
f4f5df23
VC		 3566 udelay(100);
3567 cond_resched();
3568 loops++;
3569 }
3570 if (loops >= 50000) {
3571 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3572 return dwptr;
3573 }
3574
3575 /* Dword reads to flash. */
3576 for (i = 0; i < length/4; i++, faddr += 4) {
f8086f4f 3577 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
f4f5df23
VC		 3578 ql4_printk(KERN_WARNING, ha,
3579 "Do ROM fast read failed\n");
3580 goto done_read;
3581 }
3582 dwptr[i] = __constant_cpu_to_le32(val);
3583 }
3584
3585done_read:
f8086f4f 3586 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 3587 return dwptr;
3588}
3589
3590/**
3591 * Address and length are byte address
3592 **/
3593static uint8_t *
f8086f4f 3594qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
f4f5df23
VC		 3595 uint32_t offset, uint32_t length)
3596{
f8086f4f 3597 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
f4f5df23
VC		 3598 return buf;
3599}
3600
3601static int
3602qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3603{
3604 const char *loc, *locations[] = { "DEF", "PCI" };
3605
3606 /*
3607 * FLT-location structure resides after the last PCI region.
3608 */
3609
3610 /* Begin with sane defaults. */
3611 loc = locations[0];
3612 *start = FA_FLASH_LAYOUT_ADDR_82;
3613
3614 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3615 return QLA_SUCCESS;
3616}
3617
3618static void
3619qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3620{
3621 const char *loc, *locations[] = { "DEF", "FLT" };
3622 uint16_t *wptr;
3623 uint16_t cnt, chksum;
6e7b4292 3624 uint32_t start, status;
f4f5df23
VC		 3625 struct qla_flt_header *flt;
3626 struct qla_flt_region *region;
3627 struct ql82xx_hw_data *hw = &ha->hw;
3628
3629 hw->flt_region_flt = flt_addr;
3630 wptr = (uint16_t *)ha->request_ring;
3631 flt = (struct qla_flt_header *)ha->request_ring;
3632 region = (struct qla_flt_region *)&flt[1];
6e7b4292
VC		 3633
3634 if (is_qla8022(ha)) {
3635 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3636 flt_addr << 2, OPTROM_BURST_SIZE);
b37ca418 3637 } else if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3638 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3639 (uint8_t *)ha->request_ring,
3640 0x400);
3641 if (status != QLA_SUCCESS)
3642 goto no_flash_data;
3643 }
3644
f4f5df23
VC		 3645 if (*wptr == __constant_cpu_to_le16(0xffff))
3646 goto no_flash_data;
3647 if (flt->version != __constant_cpu_to_le16(1)) {
3648 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3649 "version=0x%x length=0x%x checksum=0x%x.\n",
3650 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3651 le16_to_cpu(flt->checksum)));
3652 goto no_flash_data;
3653 }
3654
3655 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3656 for (chksum = 0; cnt; cnt--)
3657 chksum += le16_to_cpu(*wptr++);
3658 if (chksum) {
3659 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3660 "version=0x%x length=0x%x checksum=0x%x.\n",
3661 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3662 chksum));
3663 goto no_flash_data;
3664 }
3665
3666 loc = locations[1];
3667 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3668 for ( ; cnt; cnt--, region++) {
3669 /* Store addresses as DWORD offsets. */
3670 start = le32_to_cpu(region->start) >> 2;
3671
3672 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3673 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3674 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3675
3676 switch (le32_to_cpu(region->code) & 0xff) {
3677 case FLT_REG_FDT:
3678 hw->flt_region_fdt = start;
3679 break;
3680 case FLT_REG_BOOT_CODE_82:
3681 hw->flt_region_boot = start;
3682 break;
3683 case FLT_REG_FW_82:
93823956 3684 case FLT_REG_FW_82_1:
f4f5df23
VC		 3685 hw->flt_region_fw = start;
3686 break;
3687 case FLT_REG_BOOTLOAD_82:
3688 hw->flt_region_bootload = start;
3689 break;
2a991c21
MR		 3690 case FLT_REG_ISCSI_PARAM:
3691 hw->flt_iscsi_param = start;
3692 break;
4549415a
LC		 3693 case FLT_REG_ISCSI_CHAP:
3694 hw->flt_region_chap = start;
3695 hw->flt_chap_size = le32_to_cpu(region->size);
3696 break;
1e9e2be3
AC		 3697 case FLT_REG_ISCSI_DDB:
3698 hw->flt_region_ddb = start;
3699 hw->flt_ddb_size = le32_to_cpu(region->size);
3700 break;
f4f5df23
VC		 3701 }
3702 }
3703 goto done;
3704
3705no_flash_data:
3706 /* Use hardcoded defaults. */
3707 loc = locations[0];
3708
3709 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
3710 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
3711 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3712 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
9a16f65b 3713 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
4549415a 3714 hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
1e9e2be3
AC		 3715 hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
3716 hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
4549415a 3717
f4f5df23 3718done:
9a16f65b 3719 DEBUG2(ql4_printk(KERN_INFO, ha,
1e9e2be3 3720 "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
9a16f65b
VC		 3721 loc, hw->flt_region_flt, hw->flt_region_fdt,
3722 hw->flt_region_boot, hw->flt_region_bootload,
1e9e2be3
AC		 3723 hw->flt_region_fw, hw->flt_region_chap,
3724 hw->flt_chap_size, hw->flt_region_ddb,
3725 hw->flt_ddb_size));
f4f5df23
VC		 3726}
3727
3728static void
f8086f4f 3729qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
f4f5df23
VC		 3730{
3731#define FLASH_BLK_SIZE_4K 0x1000
3732#define FLASH_BLK_SIZE_32K 0x8000
3733#define FLASH_BLK_SIZE_64K 0x10000
3734 const char *loc, *locations[] = { "MID", "FDT" };
3735 uint16_t cnt, chksum;
3736 uint16_t *wptr;
3737 struct qla_fdt_layout *fdt;
3c3e2108
VC		 3738 uint16_t mid = 0;
3739 uint16_t fid = 0;
f4f5df23
VC		 3740 struct ql82xx_hw_data *hw = &ha->hw;
3741
3742 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3743 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3744
3745 wptr = (uint16_t *)ha->request_ring;
3746 fdt = (struct qla_fdt_layout *)ha->request_ring;
f8086f4f 3747 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
f4f5df23
VC		 3748 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3749
3750 if (*wptr == __constant_cpu_to_le16(0xffff))
3751 goto no_flash_data;
3752
3753 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3754 fdt->sig[3] != 'D')
3755 goto no_flash_data;
3756
3757 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3758 cnt++)
3759 chksum += le16_to_cpu(*wptr++);
3760
3761 if (chksum) {
3762 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3763 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3764 le16_to_cpu(fdt->version)));
3765 goto no_flash_data;
3766 }
3767
3768 loc = locations[1];
3769 mid = le16_to_cpu(fdt->man_id);
3770 fid = le16_to_cpu(fdt->id);
3771 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3772 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3773 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3774
3775 if (fdt->unprotect_sec_cmd) {
3776 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3777 fdt->unprotect_sec_cmd);
3778 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3779 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3780 flash_conf_addr(hw, 0x0336);
3781 }
3782 goto done;
3783
3784no_flash_data:
3785 loc = locations[0];
3786 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3787done:
3788 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3789 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3790 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3791 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3792 hw->fdt_block_size));
3793}
3794
3795static void
f8086f4f 3796qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
f4f5df23
VC		 3797{
3798#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
3799 uint32_t *wptr;
3800
3801 if (!is_qla8022(ha))
3802 return;
3803 wptr = (uint32_t *)ha->request_ring;
f8086f4f 3804 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
f4f5df23
VC		 3805 QLA82XX_IDC_PARAM_ADDR , 8);
3806
3807 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3808 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3809 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3810 } else {
3811 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3812 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3813 }
3814
3815 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3816 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3817 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3818 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3819 return;
3820}
3821
33693c7a
VC		 3822void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3823 int in_count)
3824{
3825 int i;
3826
3827 /* Load all mailbox registers, except mailbox 0. */
3828 for (i = 1; i < in_count; i++)
3829 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3830
3831 /* Wakeup firmware */
3832 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3833 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3834 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3835 readl(&ha->qla4_82xx_reg->hint);
3836}
3837
3838void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3839{
3840 int intr_status;
3841
3842 intr_status = readl(&ha->qla4_82xx_reg->host_int);
3843 if (intr_status & ISRX_82XX_RISC_INT) {
3844 ha->mbox_status_count = out_count;
3845 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3846 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3847
3848 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3849 test_bit(AF_INTx_ENABLED, &ha->flags))
3850 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3851 0xfbff);
3852 }
f4f5df23
VC		 3853}
3854
3855int
3856qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3857{
3858 int ret;
3859 uint32_t flt_addr;
3860
3861 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3862 if (ret != QLA_SUCCESS)
3863 return ret;
3864
3865 qla4_8xxx_get_flt_info(ha, flt_addr);
6e7b4292
VC		 3866 if (is_qla8022(ha)) {
3867 qla4_82xx_get_fdt_info(ha);
3868 qla4_82xx_get_idc_param(ha);
b37ca418 3869 } else if (is_qla8032(ha) || is_qla8042(ha)) {
6e7b4292
VC		 3870 qla4_83xx_get_idc_param(ha);
3871 }
f4f5df23
VC		 3872
3873 return QLA_SUCCESS;
3874}
3875
3876/**
3877 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3878 * @ha: pointer to host adapter structure.
3879 *
3880 * Remarks:
3881 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3882 * not be available after successful return. Driver must cleanup potential
3883 * outstanding I/O's after calling this funcion.
3884 **/
3885int
3886qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3887{
3888 int status;
3889 uint32_t mbox_cmd[MBOX_REG_COUNT];
3890 uint32_t mbox_sts[MBOX_REG_COUNT];
3891
3892 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3893 memset(&mbox_sts, 0, sizeof(mbox_sts));
3894
3895 mbox_cmd[0] = MBOX_CMD_STOP_FW;
3896 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3897 &mbox_cmd[0], &mbox_sts[0]);
3898
3899 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3900 __func__, status));
3901 return status;
3902}
3903
3904/**
f8086f4f 3905 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
f4f5df23
VC		 3906 * @ha: pointer to host adapter structure.
3907 **/
3908int
f8086f4f 3909qla4_82xx_isp_reset(struct scsi_qla_host *ha)
f4f5df23
VC		 3910{
3911 int rval;
3912 uint32_t dev_state;
3913
f8086f4f
VC		 3914 qla4_82xx_idc_lock(ha);
3915 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
f4f5df23 3916
de8c72da 3917 if (dev_state == QLA8XXX_DEV_READY) {
f4f5df23 3918 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
f8086f4f 3919 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
de8c72da
VC		 3920 QLA8XXX_DEV_NEED_RESET);
3921 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
f4f5df23
VC		 3922 } else
3923 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
3924
f8086f4f 3925 qla4_82xx_idc_unlock(ha);
f4f5df23
VC		 3926
3927 rval = qla4_8xxx_device_state_handler(ha);
3928
f8086f4f 3929 qla4_82xx_idc_lock(ha);
f4f5df23 3930 qla4_8xxx_clear_rst_ready(ha);
f8086f4f 3931 qla4_82xx_idc_unlock(ha);
f4f5df23 3932
068237c8 3933 if (rval == QLA_SUCCESS) {
f8086f4f 3934 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
21033639 3935 clear_bit(AF_FW_RECOVERY, &ha->flags);
068237c8 3936 }
21033639 3937
f4f5df23
VC		 3938 return rval;
3939}
3940
3941/**
3942 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
3943 * @ha: pointer to host adapter structure.
3944 *
3945 **/
3946int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
3947{
3948 uint32_t mbox_cmd[MBOX_REG_COUNT];
3949 uint32_t mbox_sts[MBOX_REG_COUNT];
3950 struct mbx_sys_info *sys_info;
3951 dma_addr_t sys_info_dma;
3952 int status = QLA_ERROR;
3953
3954 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3955 &sys_info_dma, GFP_KERNEL);
3956 if (sys_info == NULL) {
3957 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3958 ha->host_no, __func__));
3959 return status;
3960 }
3961
3962 memset(sys_info, 0, sizeof(*sys_info));
3963 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3964 memset(&mbox_sts, 0, sizeof(mbox_sts));
3965
3966 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3967 mbox_cmd[1] = LSDW(sys_info_dma);
3968 mbox_cmd[2] = MSDW(sys_info_dma);
3969 mbox_cmd[4] = sizeof(*sys_info);
3970
3971 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3972 &mbox_sts[0]) != QLA_SUCCESS) {
3973 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3974 ha->host_no, __func__));
3975 goto exit_validate_mac82;
3976 }
3977
2ccdf0dc 3978 /* Make sure we receive the minimum required data to cache internally */
b37ca418 3979 if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
e19dd66f 3980 offsetof(struct mbx_sys_info, reserved)) {
f4f5df23
VC		 3981 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3982 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3983 goto exit_validate_mac82;
f4f5df23
VC		 3984 }
3985
3986 /* Save M.A.C. address & serial_number */
2a991c21 3987 ha->port_num = sys_info->port_num;
f4f5df23
VC		 3988 memcpy(ha->my_mac, &sys_info->mac_addr[0],
3989 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3990 memcpy(ha->serial_number, &sys_info->serial_number,
3991 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
91ec7cec
VC		 3992 memcpy(ha->model_name, &sys_info->board_id_str,
3993 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3994 ha->phy_port_cnt = sys_info->phys_port_cnt;
3995 ha->phy_port_num = sys_info->port_num;
3996 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
f4f5df23
VC		 3997
3998 DEBUG2(printk("scsi%ld: %s: "
3999 "mac %02x:%02x:%02x:%02x:%02x:%02x "
4000 "serial %s\n", ha->host_no, __func__,
4001 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
4002 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
4003 ha->serial_number));
4004
4005 status = QLA_SUCCESS;
4006
4007exit_validate_mac82:
4008 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
4009 sys_info_dma);
4010 return status;
4011}
4012
4013/* Interrupt handling helpers. */
4014
5c19b92a 4015int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
f4f5df23
VC		 4016{
4017 uint32_t mbox_cmd[MBOX_REG_COUNT];
4018 uint32_t mbox_sts[MBOX_REG_COUNT];
4019
4020 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4021
4022 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4023 memset(&mbox_sts, 0, sizeof(mbox_sts));
4024 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4025 mbox_cmd[1] = INTR_ENABLE;
4026 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4027 &mbox_sts[0]) != QLA_SUCCESS) {
4028 DEBUG2(ql4_printk(KERN_INFO, ha,
4029 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4030 __func__, mbox_sts[0]));
4031 return QLA_ERROR;
4032 }
4033 return QLA_SUCCESS;
4034}
4035
5c19b92a 4036int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
f4f5df23
VC		 4037{
4038 uint32_t mbox_cmd[MBOX_REG_COUNT];
4039 uint32_t mbox_sts[MBOX_REG_COUNT];
4040
4041 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4042
4043 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4044 memset(&mbox_sts, 0, sizeof(mbox_sts));
4045 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4046 mbox_cmd[1] = INTR_DISABLE;
4047 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4048 &mbox_sts[0]) != QLA_SUCCESS) {
4049 DEBUG2(ql4_printk(KERN_INFO, ha,
4050 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4051 __func__, mbox_sts[0]));
4052 return QLA_ERROR;
4053 }
4054
4055 return QLA_SUCCESS;
4056}
4057
4058void
f8086f4f 4059qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
f4f5df23 4060{
5c19b92a 4061 qla4_8xxx_intr_enable(ha);
f4f5df23
VC		 4062
4063 spin_lock_irq(&ha->hardware_lock);
4064 /* BIT 10 - reset */
f8086f4f 4065 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
f4f5df23
VC		 4066 spin_unlock_irq(&ha->hardware_lock);
4067 set_bit(AF_INTERRUPTS_ON, &ha->flags);
4068}
4069
4070void
f8086f4f 4071qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
f4f5df23 4072{
5fa8b573 4073 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
5c19b92a 4074 qla4_8xxx_intr_disable(ha);
f4f5df23
VC		 4075
4076 spin_lock_irq(&ha->hardware_lock);
4077 /* BIT 10 - set */
f8086f4f 4078 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
f4f5df23 4079 spin_unlock_irq(&ha->hardware_lock);
f4f5df23
VC		 4080}
4081
4082struct ql4_init_msix_entry {
4083 uint16_t entry;
4084 uint16_t index;
4085 const char *name;
4086 irq_handler_t handler;
4087};
4088
4089static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
4090 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
4091 "qla4xxx (default)",
4092 (irq_handler_t)qla4_8xxx_default_intr_handler },
4093 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
4094 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
4095};
4096
4097void
4098qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
4099{
4100 int i;
4101 struct ql4_msix_entry *qentry;
4102
4103 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
4104 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
4105 if (qentry->have_irq) {
4106 free_irq(qentry->msix_vector, ha);
4107 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
4108 __func__, qla4_8xxx_msix_entries[i].name));
4109 }
4110 }
4111 pci_disable_msix(ha->pdev);
4112 clear_bit(AF_MSIX_ENABLED, &ha->flags);
4113}
4114
4115int
4116qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
4117{
4118 int i, ret;
4119 struct msix_entry entries[QLA_MSIX_ENTRIES];
4120 struct ql4_msix_entry *qentry;
4121
4122 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
4123 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
4124
4125 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
4126 if (ret) {
4127 ql4_printk(KERN_WARNING, ha,
4128 "MSI-X: Failed to enable support -- %d/%d\n",
4129 QLA_MSIX_ENTRIES, ret);
4130 goto msix_out;
4131 }
4132 set_bit(AF_MSIX_ENABLED, &ha->flags);
4133
4134 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
4135 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
4136 qentry->msix_vector = entries[i].vector;
4137 qentry->msix_entry = entries[i].entry;
4138 qentry->have_irq = 0;
4139 ret = request_irq(qentry->msix_vector,
4140 qla4_8xxx_msix_entries[i].handler, 0,
4141 qla4_8xxx_msix_entries[i].name, ha);
4142 if (ret) {
4143 ql4_printk(KERN_WARNING, ha,
4144 "MSI-X: Unable to register handler -- %x/%d.\n",
4145 qla4_8xxx_msix_entries[i].index, ret);
4146 qla4_8xxx_disable_msix(ha);
4147 goto msix_out;
4148 }
4149 qentry->have_irq = 1;
4150 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
4151 __func__, qla4_8xxx_msix_entries[i].name));
4152 }
4153msix_out:
4154 return ret;
4155}
37418cc6
NJ		 4156
4157int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
4158{
4159 int status = QLA_SUCCESS;
4160
4161 /* Dont retry adapter initialization if IRQ allocation failed */
4162 if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
4163 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
4164 __func__);
4165 status = QLA_ERROR;
4166 goto exit_init_adapter_failure;
4167 }
4168
4169 /* Since interrupts are registered in start_firmware for
4170 * 8xxx, release them here if initialize_adapter fails
4171 * and retry adapter initialization */
4172 qla4xxx_free_irqs(ha);
4173
4174exit_init_adapter_failure:
4175 return status;
4176}
Linux 6.x block layer and io_uring tree(s)