projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla4xxx: Added new function qla4_8xxx_get_minidump
[linux-2.6-block.git] / drivers / scsi / qla4xxx / ql4_nx.c
CommitLineData
f4f5df23
VC		 1/*
2 * QLogic iSCSI HBA Driver
7d01d069 3 * Copyright (c) 2003-2010 QLogic Corporation
f4f5df23
VC		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7#include <linux/delay.h>
a6751ccb 8#include <linux/io.h>
f4f5df23 9#include <linux/pci.h>
068237c8 10#include <linux/ratelimit.h>
f4f5df23
VC		 11#include "ql4_def.h"
12#include "ql4_glbl.h"
13
797a796a
HM		 14#include <asm-generic/io-64-nonatomic-lo-hi.h>
15
f4f5df23
VC		 16#define MASK(n) DMA_BIT_MASK(n)
17#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
18#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
19#define MS_WIN(addr) (addr & 0x0ffc0000)
20#define QLA82XX_PCI_MN_2M (0)
21#define QLA82XX_PCI_MS_2M (0x80000)
22#define QLA82XX_PCI_OCM0_2M (0xc0000)
23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25
26/* CRB window related */
27#define CRB_BLK(off) ((off >> 20) & 0x3f)
28#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
29#define CRB_WINDOW_2M (0x130060)
7664a1fd 30#define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
f4f5df23
VC		 31 ((off) & 0xf0000))
32#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
34#define CRB_INDIRECT_2M (0x1e0000UL)
35
36static inline void __iomem *
37qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
38{
39 if ((off < ha->first_page_group_end) &&
40 (off >= ha->first_page_group_start))
41 return (void __iomem *)(ha->nx_pcibase + off);
42
43 return NULL;
44}
45
46#define MAX_CRB_XFORM 60
47static unsigned long crb_addr_xform[MAX_CRB_XFORM];
48static int qla4_8xxx_crb_table_initialized;
49
50#define qla4_8xxx_crb_addr_transform(name) \
51 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
52 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
53static void
f8086f4f 54qla4_82xx_crb_addr_transform_setup(void)
f4f5df23
VC		 55{
56 qla4_8xxx_crb_addr_transform(XDMA);
57 qla4_8xxx_crb_addr_transform(TIMR);
58 qla4_8xxx_crb_addr_transform(SRE);
59 qla4_8xxx_crb_addr_transform(SQN3);
60 qla4_8xxx_crb_addr_transform(SQN2);
61 qla4_8xxx_crb_addr_transform(SQN1);
62 qla4_8xxx_crb_addr_transform(SQN0);
63 qla4_8xxx_crb_addr_transform(SQS3);
64 qla4_8xxx_crb_addr_transform(SQS2);
65 qla4_8xxx_crb_addr_transform(SQS1);
66 qla4_8xxx_crb_addr_transform(SQS0);
67 qla4_8xxx_crb_addr_transform(RPMX7);
68 qla4_8xxx_crb_addr_transform(RPMX6);
69 qla4_8xxx_crb_addr_transform(RPMX5);
70 qla4_8xxx_crb_addr_transform(RPMX4);
71 qla4_8xxx_crb_addr_transform(RPMX3);
72 qla4_8xxx_crb_addr_transform(RPMX2);
73 qla4_8xxx_crb_addr_transform(RPMX1);
74 qla4_8xxx_crb_addr_transform(RPMX0);
75 qla4_8xxx_crb_addr_transform(ROMUSB);
76 qla4_8xxx_crb_addr_transform(SN);
77 qla4_8xxx_crb_addr_transform(QMN);
78 qla4_8xxx_crb_addr_transform(QMS);
79 qla4_8xxx_crb_addr_transform(PGNI);
80 qla4_8xxx_crb_addr_transform(PGND);
81 qla4_8xxx_crb_addr_transform(PGN3);
82 qla4_8xxx_crb_addr_transform(PGN2);
83 qla4_8xxx_crb_addr_transform(PGN1);
84 qla4_8xxx_crb_addr_transform(PGN0);
85 qla4_8xxx_crb_addr_transform(PGSI);
86 qla4_8xxx_crb_addr_transform(PGSD);
87 qla4_8xxx_crb_addr_transform(PGS3);
88 qla4_8xxx_crb_addr_transform(PGS2);
89 qla4_8xxx_crb_addr_transform(PGS1);
90 qla4_8xxx_crb_addr_transform(PGS0);
91 qla4_8xxx_crb_addr_transform(PS);
92 qla4_8xxx_crb_addr_transform(PH);
93 qla4_8xxx_crb_addr_transform(NIU);
94 qla4_8xxx_crb_addr_transform(I2Q);
95 qla4_8xxx_crb_addr_transform(EG);
96 qla4_8xxx_crb_addr_transform(MN);
97 qla4_8xxx_crb_addr_transform(MS);
98 qla4_8xxx_crb_addr_transform(CAS2);
99 qla4_8xxx_crb_addr_transform(CAS1);
100 qla4_8xxx_crb_addr_transform(CAS0);
101 qla4_8xxx_crb_addr_transform(CAM);
102 qla4_8xxx_crb_addr_transform(C2C1);
103 qla4_8xxx_crb_addr_transform(C2C0);
104 qla4_8xxx_crb_addr_transform(SMB);
105 qla4_8xxx_crb_addr_transform(OCM0);
106 qla4_8xxx_crb_addr_transform(I2C0);
107
108 qla4_8xxx_crb_table_initialized = 1;
109}
110
111static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
112 {{{0, 0, 0, 0} } }, /* 0: PCI */
113 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
114 {1, 0x0110000, 0x0120000, 0x130000},
115 {1, 0x0120000, 0x0122000, 0x124000},
116 {1, 0x0130000, 0x0132000, 0x126000},
117 {1, 0x0140000, 0x0142000, 0x128000},
118 {1, 0x0150000, 0x0152000, 0x12a000},
119 {1, 0x0160000, 0x0170000, 0x110000},
120 {1, 0x0170000, 0x0172000, 0x12e000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x01e0000, 0x01e0800, 0x122000},
128 {0, 0x0000000, 0x0000000, 0x000000} } },
129 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
130 {{{0, 0, 0, 0} } }, /* 3: */
131 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
132 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
133 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
134 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
135 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {1, 0x08f0000, 0x08f2000, 0x172000} } },
151 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {1, 0x09f0000, 0x09f2000, 0x176000} } },
167 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
183 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
199 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
200 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
201 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
202 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
203 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
204 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
205 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
206 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
207 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
208 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
209 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
210 {{{0, 0, 0, 0} } }, /* 23: */
211 {{{0, 0, 0, 0} } }, /* 24: */
212 {{{0, 0, 0, 0} } }, /* 25: */
213 {{{0, 0, 0, 0} } }, /* 26: */
214 {{{0, 0, 0, 0} } }, /* 27: */
215 {{{0, 0, 0, 0} } }, /* 28: */
216 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
217 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
218 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
219 {{{0} } }, /* 32: PCI */
220 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
221 {1, 0x2110000, 0x2120000, 0x130000},
222 {1, 0x2120000, 0x2122000, 0x124000},
223 {1, 0x2130000, 0x2132000, 0x126000},
224 {1, 0x2140000, 0x2142000, 0x128000},
225 {1, 0x2150000, 0x2152000, 0x12a000},
226 {1, 0x2160000, 0x2170000, 0x110000},
227 {1, 0x2170000, 0x2172000, 0x12e000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000} } },
236 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
237 {{{0} } }, /* 35: */
238 {{{0} } }, /* 36: */
239 {{{0} } }, /* 37: */
240 {{{0} } }, /* 38: */
241 {{{0} } }, /* 39: */
242 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
243 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
244 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
245 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
246 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
247 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
248 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
249 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
250 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
251 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
252 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
253 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
254 {{{0} } }, /* 52: */
255 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
256 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
257 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
258 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
259 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
260 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
261 {{{0} } }, /* 59: I2C0 */
262 {{{0} } }, /* 60: I2C1 */
263 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
264 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
265 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
266};
267
268/*
269 * top 12 bits of crb internal address (hub, agent)
270 */
7664a1fd 271static unsigned qla4_82xx_crb_hub_agt[64] = {
f4f5df23
VC		 272 0,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
276 0,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
299 0,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
301 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
302 0,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
304 0,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
307 0,
308 0,
309 0,
310 0,
311 0,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
313 0,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
324 0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
329 0,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
333 0,
334 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
335 0,
336};
337
338/* Device states */
339static char *qdev_state[] = {
340 "Unknown",
341 "Cold",
342 "Initializing",
343 "Ready",
344 "Need Reset",
345 "Need Quiescent",
346 "Failed",
347 "Quiescent",
348};
349
350/*
351 * In: 'off' is offset from CRB space in 128M pci map
352 * Out: 'off' is 2M pci map addr
353 * side effect: lock crb window
354 */
355static void
f8086f4f 356qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
f4f5df23
VC		 357{
358 u32 win_read;
359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363
364 /* Read back value to make sure write has gone through before trying
365 * to use it. */
366 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
367 if (win_read != ha->crb_win) {
368 DEBUG2(ql4_printk(KERN_INFO, ha,
369 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
370 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
371 }
372 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
373}
374
375void
f8086f4f 376qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
f4f5df23
VC		 377{
378 unsigned long flags = 0;
379 int rv;
380
f8086f4f 381 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
f4f5df23
VC		 382
383 BUG_ON(rv == -1);
384
385 if (rv == 1) {
386 write_lock_irqsave(&ha->hw_lock, flags);
f8086f4f
VC		 387 qla4_82xx_crb_win_lock(ha);
388 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
f4f5df23
VC		 389 }
390
391 writel(data, (void __iomem *)off);
392
393 if (rv == 1) {
f8086f4f 394 qla4_82xx_crb_win_unlock(ha);
f4f5df23
VC		 395 write_unlock_irqrestore(&ha->hw_lock, flags);
396 }
397}
398
33693c7a 399uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
f4f5df23
VC		 400{
401 unsigned long flags = 0;
402 int rv;
403 u32 data;
404
f8086f4f 405 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
f4f5df23
VC		 406
407 BUG_ON(rv == -1);
408
409 if (rv == 1) {
410 write_lock_irqsave(&ha->hw_lock, flags);
f8086f4f
VC		 411 qla4_82xx_crb_win_lock(ha);
412 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
f4f5df23
VC		 413 }
414 data = readl((void __iomem *)off);
415
416 if (rv == 1) {
f8086f4f 417 qla4_82xx_crb_win_unlock(ha);
f4f5df23
VC		 418 write_unlock_irqrestore(&ha->hw_lock, flags);
419 }
420 return data;
421}
422
068237c8 423/* Minidump related functions */
33693c7a 424int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
068237c8 425{
33693c7a
VC		 426 uint32_t win_read, off_value;
427 int rval = QLA_SUCCESS;
068237c8
TP		 428
429 off_value = off & 0xFFFF0000;
430 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
431
33693c7a
VC		 432 /*
433 * Read back value to make sure write has gone through before trying
068237c8
TP		 434 * to use it.
435 */
436 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
437 if (win_read != off_value) {
438 DEBUG2(ql4_printk(KERN_INFO, ha,
439 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
33693c7a
VC		 440 __func__, off_value, win_read, off));
441 rval = QLA_ERROR;
442 } else {
443 off_value = off & 0x0000FFFF;
444 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
445 ha->nx_pcibase));
068237c8 446 }
33693c7a
VC		 447 return rval;
448}
449
450int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
451{
452 uint32_t win_read, off_value;
453 int rval = QLA_SUCCESS;
068237c8 454
33693c7a
VC		 455 off_value = off & 0xFFFF0000;
456 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
068237c8 457
33693c7a
VC		 458 /* Read back value to make sure write has gone through before trying
459 * to use it.
460 */
461 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
462 if (win_read != off_value) {
463 DEBUG2(ql4_printk(KERN_INFO, ha,
464 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
465 __func__, off_value, win_read, off));
466 rval = QLA_ERROR;
467 } else {
468 off_value = off & 0x0000FFFF;
068237c8
TP		 469 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
470 ha->nx_pcibase));
33693c7a 471 }
068237c8
TP		 472 return rval;
473}
474
f4f5df23
VC		 475#define CRB_WIN_LOCK_TIMEOUT 100000000
476
f8086f4f 477int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 478{
479 int i;
480 int done = 0, timeout = 0;
481
482 while (!done) {
483 /* acquire semaphore3 from PCI HW block */
f8086f4f 484 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
f4f5df23
VC		 485 if (done == 1)
486 break;
487 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
488 return -1;
489
490 timeout++;
491
492 /* Yield CPU */
493 if (!in_interrupt())
494 schedule();
495 else {
496 for (i = 0; i < 20; i++)
497 cpu_relax(); /*This a nop instr on i386*/
498 }
499 }
f8086f4f 500 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
f4f5df23
VC		 501 return 0;
502}
503
f8086f4f 504void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
f4f5df23 505{
f8086f4f 506 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
f4f5df23
VC		 507}
508
509#define IDC_LOCK_TIMEOUT 100000000
510
511/**
f8086f4f 512 * qla4_82xx_idc_lock - hw_lock
f4f5df23
VC		 513 * @ha: pointer to adapter structure
514 *
515 * General purpose lock used to synchronize access to
516 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
517 **/
f8086f4f 518int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 519{
520 int i;
521 int done = 0, timeout = 0;
522
523 while (!done) {
524 /* acquire semaphore5 from PCI HW block */
f8086f4f 525 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
f4f5df23
VC		 526 if (done == 1)
527 break;
528 if (timeout >= IDC_LOCK_TIMEOUT)
529 return -1;
530
531 timeout++;
532
533 /* Yield CPU */
534 if (!in_interrupt())
535 schedule();
536 else {
537 for (i = 0; i < 20; i++)
538 cpu_relax(); /*This a nop instr on i386*/
539 }
540 }
541 return 0;
542}
543
f8086f4f 544void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
f4f5df23 545{
f8086f4f 546 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
f4f5df23
VC		 547}
548
549int
f8086f4f 550qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
f4f5df23
VC		 551{
552 struct crb_128M_2M_sub_block_map *m;
553
554 if (*off >= QLA82XX_CRB_MAX)
555 return -1;
556
557 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
558 *off = (*off - QLA82XX_PCI_CAMQM) +
559 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
560 return 0;
561 }
562
563 if (*off < QLA82XX_PCI_CRBSPACE)
564 return -1;
565
566 *off -= QLA82XX_PCI_CRBSPACE;
567 /*
568 * Try direct map
569 */
570
571 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
572
573 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
574 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
575 return 0;
576 }
577
578 /*
579 * Not in direct map, use crb window
580 */
581 return 1;
582}
583
f4f5df23
VC		 584/*
585* check memory access boundary.
586* used by test agent. support ddr access only for now
587*/
588static unsigned long
f8086f4f 589qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
f4f5df23
VC		 590 unsigned long long addr, int size)
591{
de8c72da
VC		 592 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
593 QLA8XXX_ADDR_DDR_NET_MAX) ||
594 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
595 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
f4f5df23
VC		 596 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
597 return 0;
598 }
599 return 1;
600}
601
7664a1fd 602static int qla4_82xx_pci_set_window_warning_count;
f4f5df23
VC		 603
604static unsigned long
f8086f4f 605qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
f4f5df23
VC		 606{
607 int window;
608 u32 win_read;
609
de8c72da
VC		 610 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
611 QLA8XXX_ADDR_DDR_NET_MAX)) {
f4f5df23
VC		 612 /* DDR network side */
613 window = MN_WIN(addr);
614 ha->ddr_mn_window = window;
f8086f4f 615 qla4_82xx_wr_32(ha, ha->mn_win_crb |
f4f5df23 616 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 617 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
f4f5df23
VC		 618 QLA82XX_PCI_CRBSPACE);
619 if ((win_read << 17) != window) {
620 ql4_printk(KERN_WARNING, ha,
621 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
622 __func__, window, win_read);
623 }
624 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
de8c72da
VC		 625 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
626 QLA8XXX_ADDR_OCM0_MAX)) {
f4f5df23
VC		 627 unsigned int temp1;
628 /* if bits 19:18&17:11 are on */
629 if ((addr & 0x00ff800) == 0xff800) {
630 printk("%s: QM access not handled.\n", __func__);
631 addr = -1UL;
632 }
633
634 window = OCM_WIN(addr);
635 ha->ddr_mn_window = window;
f8086f4f 636 qla4_82xx_wr_32(ha, ha->mn_win_crb |
f4f5df23 637 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 638 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
f4f5df23
VC		 639 QLA82XX_PCI_CRBSPACE);
640 temp1 = ((window & 0x1FF) << 7) |
641 ((window & 0x0FFFE0000) >> 17);
642 if (win_read != temp1) {
643 printk("%s: Written OCMwin (0x%x) != Read"
644 " OCMwin (0x%x)\n", __func__, temp1, win_read);
645 }
646 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
647
de8c72da 648 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
f4f5df23
VC		 649 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
650 /* QDR network side */
651 window = MS_WIN(addr);
652 ha->qdr_sn_window = window;
f8086f4f 653 qla4_82xx_wr_32(ha, ha->ms_win_crb |
f4f5df23 654 QLA82XX_PCI_CRBSPACE, window);
f8086f4f 655 win_read = qla4_82xx_rd_32(ha,
f4f5df23
VC		 656 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
657 if (win_read != window) {
658 printk("%s: Written MSwin (0x%x) != Read "
659 "MSwin (0x%x)\n", __func__, window, win_read);
660 }
661 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
662
663 } else {
664 /*
665 * peg gdb frequently accesses memory that doesn't exist,
666 * this limits the chit chat so debugging isn't slowed down.
667 */
7664a1fd
VC		 668 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
669 (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
f4f5df23
VC		 670 printk("%s: Warning:%s Unknown address range!\n",
671 __func__, DRIVER_NAME);
672 }
673 addr = -1UL;
674 }
675 return addr;
676}
677
678/* check if address is in the same windows as the previous access */
f8086f4f 679static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
f4f5df23
VC		 680 unsigned long long addr)
681{
682 int window;
683 unsigned long long qdr_max;
684
685 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
686
de8c72da
VC		 687 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
688 QLA8XXX_ADDR_DDR_NET_MAX)) {
f4f5df23
VC		 689 /* DDR network side */
690 BUG(); /* MN access can not come here */
de8c72da
VC		 691 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
692 QLA8XXX_ADDR_OCM0_MAX)) {
f4f5df23 693 return 1;
de8c72da
VC		 694 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
695 QLA8XXX_ADDR_OCM1_MAX)) {
f4f5df23 696 return 1;
de8c72da 697 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
f4f5df23
VC		 698 qdr_max)) {
699 /* QDR network side */
de8c72da 700 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
f4f5df23
VC		 701 if (ha->qdr_sn_window == window)
702 return 1;
703 }
704
705 return 0;
706}
707
f8086f4f 708static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
f4f5df23
VC		 709 u64 off, void *data, int size)
710{
711 unsigned long flags;
712 void __iomem *addr;
713 int ret = 0;
714 u64 start;
715 void __iomem *mem_ptr = NULL;
716 unsigned long mem_base;
717 unsigned long mem_page;
718
719 write_lock_irqsave(&ha->hw_lock, flags);
720
721 /*
722 * If attempting to access unknown address or straddle hw windows,
723 * do not access.
724 */
f8086f4f 725 start = qla4_82xx_pci_set_window(ha, off);
f4f5df23 726 if ((start == -1UL) ||
f8086f4f 727 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
f4f5df23
VC		 728 write_unlock_irqrestore(&ha->hw_lock, flags);
729 printk(KERN_ERR"%s out of bound pci memory access. "
730 "offset is 0x%llx\n", DRIVER_NAME, off);
731 return -1;
732 }
733
734 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
735 if (!addr) {
736 write_unlock_irqrestore(&ha->hw_lock, flags);
737 mem_base = pci_resource_start(ha->pdev, 0);
738 mem_page = start & PAGE_MASK;
739 /* Map two pages whenever user tries to access addresses in two
740 consecutive pages.
741 */
742 if (mem_page != ((start + size - 1) & PAGE_MASK))
743 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
744 else
745 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
746
747 if (mem_ptr == NULL) {
748 *(u8 *)data = 0;
749 return -1;
750 }
751 addr = mem_ptr;
752 addr += start & (PAGE_SIZE - 1);
753 write_lock_irqsave(&ha->hw_lock, flags);
754 }
755
756 switch (size) {
757 case 1:
758 *(u8 *)data = readb(addr);
759 break;
760 case 2:
761 *(u16 *)data = readw(addr);
762 break;
763 case 4:
764 *(u32 *)data = readl(addr);
765 break;
766 case 8:
767 *(u64 *)data = readq(addr);
768 break;
769 default:
770 ret = -1;
771 break;
772 }
773 write_unlock_irqrestore(&ha->hw_lock, flags);
774
775 if (mem_ptr)
776 iounmap(mem_ptr);
777 return ret;
778}
779
780static int
f8086f4f 781qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
f4f5df23
VC		 782 void *data, int size)
783{
784 unsigned long flags;
785 void __iomem *addr;
786 int ret = 0;
787 u64 start;
788 void __iomem *mem_ptr = NULL;
789 unsigned long mem_base;
790 unsigned long mem_page;
791
792 write_lock_irqsave(&ha->hw_lock, flags);
793
794 /*
795 * If attempting to access unknown address or straddle hw windows,
796 * do not access.
797 */
f8086f4f 798 start = qla4_82xx_pci_set_window(ha, off);
f4f5df23 799 if ((start == -1UL) ||
f8086f4f 800 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
f4f5df23
VC		 801 write_unlock_irqrestore(&ha->hw_lock, flags);
802 printk(KERN_ERR"%s out of bound pci memory access. "
803 "offset is 0x%llx\n", DRIVER_NAME, off);
804 return -1;
805 }
806
807 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
808 if (!addr) {
809 write_unlock_irqrestore(&ha->hw_lock, flags);
810 mem_base = pci_resource_start(ha->pdev, 0);
811 mem_page = start & PAGE_MASK;
812 /* Map two pages whenever user tries to access addresses in two
813 consecutive pages.
814 */
815 if (mem_page != ((start + size - 1) & PAGE_MASK))
816 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
817 else
818 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
819 if (mem_ptr == NULL)
820 return -1;
821
822 addr = mem_ptr;
823 addr += start & (PAGE_SIZE - 1);
824 write_lock_irqsave(&ha->hw_lock, flags);
825 }
826
827 switch (size) {
828 case 1:
829 writeb(*(u8 *)data, addr);
830 break;
831 case 2:
832 writew(*(u16 *)data, addr);
833 break;
834 case 4:
835 writel(*(u32 *)data, addr);
836 break;
837 case 8:
838 writeq(*(u64 *)data, addr);
839 break;
840 default:
841 ret = -1;
842 break;
843 }
844 write_unlock_irqrestore(&ha->hw_lock, flags);
845 if (mem_ptr)
846 iounmap(mem_ptr);
847 return ret;
848}
849
850#define MTU_FUDGE_FACTOR 100
851
852static unsigned long
f8086f4f 853qla4_82xx_decode_crb_addr(unsigned long addr)
f4f5df23
VC		 854{
855 int i;
856 unsigned long base_addr, offset, pci_base;
857
858 if (!qla4_8xxx_crb_table_initialized)
f8086f4f 859 qla4_82xx_crb_addr_transform_setup();
f4f5df23
VC		 860
861 pci_base = ADDR_ERROR;
862 base_addr = addr & 0xfff00000;
863 offset = addr & 0x000fffff;
864
865 for (i = 0; i < MAX_CRB_XFORM; i++) {
866 if (crb_addr_xform[i] == base_addr) {
867 pci_base = i << 20;
868 break;
869 }
870 }
871 if (pci_base == ADDR_ERROR)
872 return pci_base;
873 else
874 return pci_base + offset;
875}
876
877static long rom_max_timeout = 100;
7664a1fd 878static long qla4_82xx_rom_lock_timeout = 100;
f4f5df23
VC		 879
880static int
f8086f4f 881qla4_82xx_rom_lock(struct scsi_qla_host *ha)
f4f5df23
VC		 882{
883 int i;
884 int done = 0, timeout = 0;
885
886 while (!done) {
887 /* acquire semaphore2 from PCI HW block */
888
f8086f4f 889 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
f4f5df23
VC		 890 if (done == 1)
891 break;
7664a1fd 892 if (timeout >= qla4_82xx_rom_lock_timeout)
f4f5df23
VC		 893 return -1;
894
895 timeout++;
896
897 /* Yield CPU */
898 if (!in_interrupt())
899 schedule();
900 else {
901 for (i = 0; i < 20; i++)
902 cpu_relax(); /*This a nop instr on i386*/
903 }
904 }
f8086f4f 905 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
f4f5df23
VC		 906 return 0;
907}
908
909static void
f8086f4f 910qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
f4f5df23 911{
f8086f4f 912 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
f4f5df23
VC		 913}
914
915static int
f8086f4f 916qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
f4f5df23
VC		 917{
918 long timeout = 0;
919 long done = 0 ;
920
921 while (done == 0) {
f8086f4f 922 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
f4f5df23
VC		 923 done &= 2;
924 timeout++;
925 if (timeout >= rom_max_timeout) {
926 printk("%s: Timeout reached waiting for rom done",
927 DRIVER_NAME);
928 return -1;
929 }
930 }
931 return 0;
932}
933
934static int
f8086f4f 935qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
f4f5df23 936{
f8086f4f
VC		 937 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
939 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
940 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
941 if (qla4_82xx_wait_rom_done(ha)) {
f4f5df23
VC		 942 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
943 return -1;
944 }
945 /* reset abyte_cnt and dummy_byte_cnt */
f8086f4f 946 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
f4f5df23 947 udelay(10);
f8086f4f 948 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
f4f5df23 949
f8086f4f 950 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
f4f5df23
VC		 951 return 0;
952}
953
954static int
f8086f4f 955qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
f4f5df23
VC		 956{
957 int ret, loops = 0;
958
f8086f4f 959 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
f4f5df23
VC		 960 udelay(100);
961 loops++;
962 }
963 if (loops >= 50000) {
f8086f4f
VC		 964 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
965 DRIVER_NAME);
f4f5df23
VC		 966 return -1;
967 }
f8086f4f
VC		 968 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
969 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 970 return ret;
971}
972
973/**
974 * This routine does CRB initialize sequence
975 * to put the ISP into operational state
976 **/
977static int
f8086f4f 978qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
f4f5df23
VC		 979{
980 int addr, val;
981 int i ;
982 struct crb_addr_pair *buf;
983 unsigned long off;
984 unsigned offset, n;
985
986 struct crb_addr_pair {
987 long addr;
988 long data;
989 };
990
991 /* Halt all the indiviual PEGs and other blocks of the ISP */
f8086f4f 992 qla4_82xx_rom_lock(ha);
a1fc26ba 993
cb74428e 994 /* disable all I2Q */
f8086f4f
VC		 995 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
996 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
997 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
998 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
999 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
cb74428e
VC		 1001
1002 /* disable all niu interrupts */
f8086f4f 1003 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
a1fc26ba 1004 /* disable xge rx/tx */
f8086f4f 1005 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
a1fc26ba 1006 /* disable xg1 rx/tx */
f8086f4f 1007 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
cb74428e 1008 /* disable sideband mac */
f8086f4f 1009 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
cb74428e 1010 /* disable ap0 mac */
f8086f4f 1011 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
cb74428e 1012 /* disable ap1 mac */
f8086f4f 1013 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
a1fc26ba
SN		 1014
1015 /* halt sre */
f8086f4f
VC		 1016 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1017 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
a1fc26ba
SN		 1018
1019 /* halt epg */
f8086f4f 1020 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
a1fc26ba
SN		 1021
1022 /* halt timers */
f8086f4f
VC		 1023 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1024 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1026 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1027 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1028 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
a1fc26ba
SN		 1029
1030 /* halt pegs */
f8086f4f
VC		 1031 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1032 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1033 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1034 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1035 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
cb74428e 1036 msleep(5);
a1fc26ba
SN		 1037
1038 /* big hammer */
f4f5df23
VC		 1039 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1040 /* don't reset CAM block on reset */
f8086f4f 1041 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
f4f5df23 1042 else
f8086f4f 1043 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
f4f5df23 1044
f8086f4f 1045 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 1046
1047 /* Read the signature value from the flash.
1048 * Offset 0: Contain signature (0xcafecafe)
1049 * Offset 4: Offset and number of addr/value pairs
1050 * that present in CRB initialize sequence
1051 */
f8086f4f
VC		 1052 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1053 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
f4f5df23
VC		 1054 ql4_printk(KERN_WARNING, ha,
1055 "[ERROR] Reading crb_init area: n: %08x\n", n);
1056 return -1;
1057 }
1058
1059 /* Offset in flash = lower 16 bits
1060 * Number of enteries = upper 16 bits
1061 */
1062 offset = n & 0xffffU;
1063 n = (n >> 16) & 0xffffU;
1064
1065 /* number of addr/value pair should not exceed 1024 enteries */
1066 if (n >= 1024) {
1067 ql4_printk(KERN_WARNING, ha,
1068 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1069 DRIVER_NAME, __func__, n);
1070 return -1;
1071 }
1072
1073 ql4_printk(KERN_INFO, ha,
1074 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1075
1076 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1077 if (buf == NULL) {
1078 ql4_printk(KERN_WARNING, ha,
1079 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1080 return -1;
1081 }
1082
1083 for (i = 0; i < n; i++) {
f8086f4f
VC		 1084 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1085 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
f4f5df23
VC		 1086 0) {
1087 kfree(buf);
1088 return -1;
1089 }
1090
1091 buf[i].addr = addr;
1092 buf[i].data = val;
1093 }
1094
1095 for (i = 0; i < n; i++) {
1096 /* Translate internal CRB initialization
1097 * address to PCI bus address
1098 */
f8086f4f 1099 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
f4f5df23
VC		 1100 QLA82XX_PCI_CRBSPACE;
1101 /* Not all CRB addr/value pair to be written,
1102 * some of them are skipped
1103 */
1104
1105 /* skip if LS bit is set*/
1106 if (off & 0x1) {
1107 DEBUG2(ql4_printk(KERN_WARNING, ha,
1108 "Skip CRB init replay for offset = 0x%lx\n", off));
1109 continue;
1110 }
1111
1112 /* skipping cold reboot MAGIC */
1113 if (off == QLA82XX_CAM_RAM(0x1fc))
1114 continue;
1115
1116 /* do not reset PCI */
1117 if (off == (ROMUSB_GLB + 0xbc))
1118 continue;
1119
1120 /* skip core clock, so that firmware can increase the clock */
1121 if (off == (ROMUSB_GLB + 0xc8))
1122 continue;
1123
1124 /* skip the function enable register */
1125 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1126 continue;
1127
1128 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1129 continue;
1130
1131 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1132 continue;
1133
1134 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1135 continue;
1136
1137 if (off == ADDR_ERROR) {
1138 ql4_printk(KERN_WARNING, ha,
1139 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1140 DRIVER_NAME, buf[i].addr);
1141 continue;
1142 }
1143
f8086f4f 1144 qla4_82xx_wr_32(ha, off, buf[i].data);
f4f5df23
VC		 1145
1146 /* ISP requires much bigger delay to settle down,
1147 * else crb_window returns 0xffffffff
1148 */
1149 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1150 msleep(1000);
1151
1152 /* ISP requires millisec delay between
1153 * successive CRB register updation
1154 */
1155 msleep(1);
1156 }
1157
1158 kfree(buf);
1159
1160 /* Resetting the data and instruction cache */
f8086f4f
VC		 1161 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1162 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
f4f5df23
VC		 1164
1165 /* Clear all protocol processing engines */
f8086f4f
VC		 1166 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1167 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1168 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1169 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1170 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1171 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1172 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1173 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
f4f5df23
VC		 1174
1175 return 0;
1176}
1177
f4f5df23 1178static int
f8086f4f 1179qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23 1180{
4cd83cbe 1181 int i, rval = 0;
f4f5df23
VC		 1182 long size = 0;
1183 long flashaddr, memaddr;
1184 u64 data;
1185 u32 high, low;
1186
1187 flashaddr = memaddr = ha->hw.flt_region_bootload;
4cd83cbe 1188 size = (image_start - flashaddr) / 8;
f4f5df23
VC		 1189
1190 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1191 ha->host_no, __func__, flashaddr, image_start));
1192
1193 for (i = 0; i < size; i++) {
f8086f4f
VC		 1194 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1195 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
f4f5df23 1196 (int *)&high))) {
4cd83cbe
LC		 1197 rval = -1;
1198 goto exit_load_from_flash;
f4f5df23
VC		 1199 }
1200 data = ((u64)high << 32) | low ;
f8086f4f 1201 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
4cd83cbe
LC		 1202 if (rval)
1203 goto exit_load_from_flash;
1204
f4f5df23
VC		 1205 flashaddr += 8;
1206 memaddr += 8;
1207
4cd83cbe 1208 if (i % 0x1000 == 0)
f4f5df23
VC		 1209 msleep(1);
1210
1211 }
1212
1213 udelay(100);
1214
1215 read_lock(&ha->hw_lock);
f8086f4f
VC		 1216 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1217 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
f4f5df23
VC		 1218 read_unlock(&ha->hw_lock);
1219
4cd83cbe
LC		 1220exit_load_from_flash:
1221 return rval;
f4f5df23
VC		 1222}
1223
f8086f4f 1224static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23
VC		 1225{
1226 u32 rst;
1227
f8086f4f
VC		 1228 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1229 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
f4f5df23
VC		 1230 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1231 __func__);
1232 return QLA_ERROR;
1233 }
1234
1235 udelay(500);
1236
1237 /* at this point, QM is in reset. This could be a problem if there are
1238 * incoming d* transition queue messages. QM/PCIE could wedge.
1239 * To get around this, QM is brought out of reset.
1240 */
1241
f8086f4f 1242 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
f4f5df23
VC		 1243 /* unreset qm */
1244 rst &= ~(1 << 28);
f8086f4f 1245 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
f4f5df23 1246
f8086f4f 1247 if (qla4_82xx_load_from_flash(ha, image_start)) {
f4f5df23
VC		 1248 printk("%s: Error trying to load fw from flash!\n", __func__);
1249 return QLA_ERROR;
1250 }
1251
1252 return QLA_SUCCESS;
1253}
1254
1255int
f8086f4f 1256qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
f4f5df23
VC		 1257 u64 off, void *data, int size)
1258{
1259 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1260 int shift_amount;
1261 uint32_t temp;
1262 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1263
1264 /*
1265 * If not MN, go check for MS or invalid.
1266 */
1267
de8c72da 1268 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
f4f5df23
VC		 1269 mem_crb = QLA82XX_CRB_QDR_NET;
1270 else {
1271 mem_crb = QLA82XX_CRB_DDR_NET;
f8086f4f
VC		 1272 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1273 return qla4_82xx_pci_mem_read_direct(ha,
f4f5df23
VC		 1274 off, data, size);
1275 }
1276
1277
1278 off8 = off & 0xfffffff0;
1279 off0[0] = off & 0xf;
1280 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1281 shift_amount = 4;
1282
1283 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1284 off0[1] = 0;
1285 sz[1] = size - sz[0];
1286
1287 for (i = 0; i < loop; i++) {
1288 temp = off8 + (i << shift_amount);
f8086f4f 1289 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
f4f5df23 1290 temp = 0;
f8086f4f 1291 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
f4f5df23 1292 temp = MIU_TA_CTL_ENABLE;
f8086f4f 1293 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
c38fa3ab 1294 temp = MIU_TA_CTL_START_ENABLE;
f8086f4f 1295 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
f4f5df23
VC		 1296
1297 for (j = 0; j < MAX_CTL_CHECK; j++) {
f8086f4f 1298 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
f4f5df23
VC		 1299 if ((temp & MIU_TA_CTL_BUSY) == 0)
1300 break;
1301 }
1302
1303 if (j >= MAX_CTL_CHECK) {
068237c8
TP		 1304 printk_ratelimited(KERN_ERR
1305 "%s: failed to read through agent\n",
1306 __func__);
f4f5df23
VC		 1307 break;
1308 }
1309
1310 start = off0[i] >> 2;
1311 end = (off0[i] + sz[i] - 1) >> 2;
1312 for (k = start; k <= end; k++) {
f8086f4f 1313 temp = qla4_82xx_rd_32(ha,
f4f5df23
VC		 1314 mem_crb + MIU_TEST_AGT_RDDATA(k));
1315 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1316 }
1317 }
1318
1319 if (j >= MAX_CTL_CHECK)
1320 return -1;
1321
1322 if ((off0[0] & 7) == 0) {
1323 val = word[0];
1324 } else {
1325 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1326 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1327 }
1328
1329 switch (size) {
1330 case 1:
1331 *(uint8_t *)data = val;
1332 break;
1333 case 2:
1334 *(uint16_t *)data = val;
1335 break;
1336 case 4:
1337 *(uint32_t *)data = val;
1338 break;
1339 case 8:
1340 *(uint64_t *)data = val;
1341 break;
1342 }
1343 return 0;
1344}
1345
1346int
f8086f4f 1347qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
f4f5df23
VC		 1348 u64 off, void *data, int size)
1349{
1350 int i, j, ret = 0, loop, sz[2], off0;
1351 int scale, shift_amount, startword;
1352 uint32_t temp;
1353 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1354
1355 /*
1356 * If not MN, go check for MS or invalid.
1357 */
de8c72da 1358 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
f4f5df23
VC		 1359 mem_crb = QLA82XX_CRB_QDR_NET;
1360 else {
1361 mem_crb = QLA82XX_CRB_DDR_NET;
f8086f4f
VC		 1362 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1363 return qla4_82xx_pci_mem_write_direct(ha,
f4f5df23
VC		 1364 off, data, size);
1365 }
1366
1367 off0 = off & 0x7;
1368 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1369 sz[1] = size - sz[0];
1370
1371 off8 = off & 0xfffffff0;
1372 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1373 shift_amount = 4;
1374 scale = 2;
1375 startword = (off & 0xf)/8;
1376
1377 for (i = 0; i < loop; i++) {
f8086f4f 1378 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
f4f5df23
VC		 1379 (i << shift_amount), &word[i * scale], 8))
1380 return -1;
1381 }
1382
1383 switch (size) {
1384 case 1:
1385 tmpw = *((uint8_t *)data);
1386 break;
1387 case 2:
1388 tmpw = *((uint16_t *)data);
1389 break;
1390 case 4:
1391 tmpw = *((uint32_t *)data);
1392 break;
1393 case 8:
1394 default:
1395 tmpw = *((uint64_t *)data);
1396 break;
1397 }
1398
1399 if (sz[0] == 8)
1400 word[startword] = tmpw;
1401 else {
1402 word[startword] &=
1403 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1404 word[startword] |= tmpw << (off0 * 8);
1405 }
1406
1407 if (sz[1] != 0) {
1408 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1409 word[startword+1] |= tmpw >> (sz[0] * 8);
1410 }
1411
1412 for (i = 0; i < loop; i++) {
1413 temp = off8 + (i << shift_amount);
f8086f4f 1414 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
f4f5df23 1415 temp = 0;
f8086f4f 1416 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
f4f5df23 1417 temp = word[i * scale] & 0xffffffff;
f8086f4f 1418 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
f4f5df23 1419 temp = (word[i * scale] >> 32) & 0xffffffff;
f8086f4f 1420 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
f4f5df23 1421 temp = word[i*scale + 1] & 0xffffffff;
f8086f4f 1422 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
f4f5df23
VC		 1423 temp);
1424 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
f8086f4f 1425 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
f4f5df23
VC		 1426 temp);
1427
c38fa3ab 1428 temp = MIU_TA_CTL_WRITE_ENABLE;
f8086f4f 1429 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
c38fa3ab 1430 temp = MIU_TA_CTL_WRITE_START;
f8086f4f 1431 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
f4f5df23
VC		 1432
1433 for (j = 0; j < MAX_CTL_CHECK; j++) {
f8086f4f 1434 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
f4f5df23
VC		 1435 if ((temp & MIU_TA_CTL_BUSY) == 0)
1436 break;
1437 }
1438
1439 if (j >= MAX_CTL_CHECK) {
1440 if (printk_ratelimit())
1441 ql4_printk(KERN_ERR, ha,
068237c8
TP		 1442 "%s: failed to read through agent\n",
1443 __func__);
f4f5df23
VC		 1444 ret = -1;
1445 break;
1446 }
1447 }
1448
1449 return ret;
1450}
1451
f8086f4f 1452static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
f4f5df23
VC		 1453{
1454 u32 val = 0;
1455 int retries = 60;
1456
1457 if (!pegtune_val) {
1458 do {
f8086f4f 1459 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
f4f5df23
VC		 1460 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1461 (val == PHAN_INITIALIZE_ACK))
1462 return 0;
1463 set_current_state(TASK_UNINTERRUPTIBLE);
1464 schedule_timeout(500);
1465
1466 } while (--retries);
1467
f4f5df23 1468 if (!retries) {
f8086f4f 1469 pegtune_val = qla4_82xx_rd_32(ha,
f4f5df23
VC		 1470 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1471 printk(KERN_WARNING "%s: init failed, "
1472 "pegtune_val = %x\n", __func__, pegtune_val);
1473 return -1;
1474 }
1475 }
1476 return 0;
1477}
1478
f8086f4f 1479static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
f4f5df23
VC		 1480{
1481 uint32_t state = 0;
1482 int loops = 0;
1483
1484 /* Window 1 call */
1485 read_lock(&ha->hw_lock);
f8086f4f 1486 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
f4f5df23
VC		 1487 read_unlock(&ha->hw_lock);
1488
1489 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1490 udelay(100);
1491 /* Window 1 call */
1492 read_lock(&ha->hw_lock);
f8086f4f 1493 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
f4f5df23
VC		 1494 read_unlock(&ha->hw_lock);
1495
1496 loops++;
1497 }
1498
1499 if (loops >= 30000) {
1500 DEBUG2(ql4_printk(KERN_INFO, ha,
1501 "Receive Peg initialization not complete: 0x%x.\n", state));
1502 return QLA_ERROR;
1503 }
1504
1505 return QLA_SUCCESS;
1506}
1507
626115cd 1508void
f4f5df23
VC		 1509qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1510{
1511 uint32_t drv_active;
1512
33693c7a 1513 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
f4f5df23 1514 drv_active |= (1 << (ha->func_num * 4));
068237c8
TP		 1515 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1516 __func__, ha->host_no, drv_active);
33693c7a 1517 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
f4f5df23
VC		 1518}
1519
1520void
1521qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1522{
1523 uint32_t drv_active;
1524
33693c7a 1525 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
f4f5df23 1526 drv_active &= ~(1 << (ha->func_num * 4));
068237c8
TP		 1527 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1528 __func__, ha->host_no, drv_active);
33693c7a 1529 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
f4f5df23
VC		 1530}
1531
33693c7a 1532inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
f4f5df23 1533{
2232be0d 1534 uint32_t drv_state, drv_active;
f4f5df23
VC		 1535 int rval;
1536
33693c7a
VC		 1537 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1538 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
f4f5df23 1539 rval = drv_state & (1 << (ha->func_num * 4));
2232be0d
LC		 1540 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1541 rval = 1;
1542
f4f5df23
VC		 1543 return rval;
1544}
1545
1546static inline void
1547qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1548{
1549 uint32_t drv_state;
1550
33693c7a 1551 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
f4f5df23 1552 drv_state |= (1 << (ha->func_num * 4));
068237c8
TP		 1553 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1554 __func__, ha->host_no, drv_state);
33693c7a 1555 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
f4f5df23
VC		 1556}
1557
1558static inline void
1559qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1560{
1561 uint32_t drv_state;
1562
33693c7a 1563 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
f4f5df23 1564 drv_state &= ~(1 << (ha->func_num * 4));
068237c8
TP		 1565 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1566 __func__, ha->host_no, drv_state);
33693c7a 1567 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
f4f5df23
VC		 1568}
1569
1570static inline void
1571qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1572{
1573 uint32_t qsnt_state;
1574
33693c7a 1575 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
f4f5df23 1576 qsnt_state |= (2 << (ha->func_num * 4));
33693c7a 1577 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
f4f5df23
VC		 1578}
1579
1580
1581static int
f8086f4f 1582qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
f4f5df23
VC		 1583{
1584 int pcie_cap;
1585 uint16_t lnk;
1586
1587 /* scrub dma mask expansion register */
f8086f4f 1588 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
f4f5df23
VC		 1589
1590 /* Overwrite stale initialization register values */
f8086f4f
VC		 1591 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1592 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1593 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1594 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
f4f5df23 1595
f8086f4f 1596 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
f4f5df23
VC		 1597 printk("%s: Error trying to start fw!\n", __func__);
1598 return QLA_ERROR;
1599 }
1600
1601 /* Handshake with the card before we register the devices. */
f8086f4f 1602 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
f4f5df23
VC		 1603 printk("%s: Error during card handshake!\n", __func__);
1604 return QLA_ERROR;
1605 }
1606
1607 /* Negotiated Link width */
983bfb5b 1608 pcie_cap = pci_pcie_cap(ha->pdev);
f4f5df23
VC		 1609 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1610 ha->link_width = (lnk >> 4) & 0x3f;
1611
1612 /* Synchronize with Receive peg */
f8086f4f 1613 return qla4_82xx_rcvpeg_ready(ha);
f4f5df23
VC		 1614}
1615
33693c7a 1616int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
f4f5df23
VC		 1617{
1618 int rval = QLA_ERROR;
1619
1620 /*
1621 * FW Load priority:
1622 * 1) Operational firmware residing in flash.
1623 * 2) Fail
1624 */
1625
1626 ql4_printk(KERN_INFO, ha,
1627 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1628 rval = qla4_8xxx_get_flash_info(ha);
1629 if (rval != QLA_SUCCESS)
1630 return rval;
1631
1632 ql4_printk(KERN_INFO, ha,
1633 "FW: Attempting to load firmware from flash...\n");
f8086f4f 1634 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
f4f5df23 1635
f581a3f7
VC		 1636 if (rval != QLA_SUCCESS) {
1637 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1638 " FAILED...\n");
1639 return rval;
1640 }
f4f5df23
VC		 1641
1642 return rval;
1643}
1644
33693c7a 1645void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
b25ee66f 1646{
f8086f4f 1647 if (qla4_82xx_rom_lock(ha)) {
b25ee66f
SS		 1648 /* Someone else is holding the lock. */
1649 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1650 }
1651
1652 /*
1653 * Either we got the lock, or someone
1654 * else died while holding it.
1655 * In either case, unlock.
1656 */
f8086f4f 1657 qla4_82xx_rom_unlock(ha);
b25ee66f
SS		 1658}
1659
068237c8 1660static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
7664a1fd 1661 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1662 uint32_t **d_ptr)
1663{
1664 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
7664a1fd 1665 struct qla8xxx_minidump_entry_crb *crb_hdr;
068237c8
TP		 1666 uint32_t *data_ptr = *d_ptr;
1667
1668 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1669 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
068237c8
TP		 1670 r_addr = crb_hdr->addr;
1671 r_stride = crb_hdr->crb_strd.addr_stride;
1672 loop_cnt = crb_hdr->op_count;
1673
1674 for (i = 0; i < loop_cnt; i++) {
33693c7a 1675 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 1676 *data_ptr++ = cpu_to_le32(r_addr);
1677 *data_ptr++ = cpu_to_le32(r_value);
1678 r_addr += r_stride;
1679 }
1680 *d_ptr = data_ptr;
1681}
1682
1683static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
7664a1fd 1684 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1685 uint32_t **d_ptr)
1686{
1687 uint32_t addr, r_addr, c_addr, t_r_addr;
1688 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1689 unsigned long p_wait, w_time, p_mask;
1690 uint32_t c_value_w, c_value_r;
7664a1fd 1691 struct qla8xxx_minidump_entry_cache *cache_hdr;
068237c8
TP		 1692 int rval = QLA_ERROR;
1693 uint32_t *data_ptr = *d_ptr;
1694
1695 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1696 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
068237c8
TP		 1697
1698 loop_count = cache_hdr->op_count;
1699 r_addr = cache_hdr->read_addr;
1700 c_addr = cache_hdr->control_addr;
1701 c_value_w = cache_hdr->cache_ctrl.write_value;
1702
1703 t_r_addr = cache_hdr->tag_reg_addr;
1704 t_value = cache_hdr->addr_ctrl.init_tag_value;
1705 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1706 p_wait = cache_hdr->cache_ctrl.poll_wait;
1707 p_mask = cache_hdr->cache_ctrl.poll_mask;
1708
1709 for (i = 0; i < loop_count; i++) {
33693c7a 1710 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
068237c8
TP		 1711
1712 if (c_value_w)
33693c7a 1713 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
068237c8
TP		 1714
1715 if (p_mask) {
1716 w_time = jiffies + p_wait;
1717 do {
33693c7a
VC		 1718 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1719 &c_value_r);
068237c8
TP		 1720 if ((c_value_r & p_mask) == 0) {
1721 break;
1722 } else if (time_after_eq(jiffies, w_time)) {
1723 /* capturing dump failed */
1724 return rval;
1725 }
1726 } while (1);
1727 }
1728
1729 addr = r_addr;
1730 for (k = 0; k < r_cnt; k++) {
33693c7a 1731 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
068237c8
TP		 1732 *data_ptr++ = cpu_to_le32(r_value);
1733 addr += cache_hdr->read_ctrl.read_addr_stride;
1734 }
1735
1736 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1737 }
1738 *d_ptr = data_ptr;
1739 return QLA_SUCCESS;
1740}
1741
1742static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
7664a1fd 1743 struct qla8xxx_minidump_entry_hdr *entry_hdr)
068237c8 1744{
7664a1fd 1745 struct qla8xxx_minidump_entry_crb *crb_entry;
068237c8
TP		 1746 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
1747 uint32_t crb_addr;
1748 unsigned long wtime;
1749 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
1750 int i;
1751
1752 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1753 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1754 ha->fw_dump_tmplt_hdr;
7664a1fd 1755 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
068237c8
TP		 1756
1757 crb_addr = crb_entry->addr;
1758 for (i = 0; i < crb_entry->op_count; i++) {
1759 opcode = crb_entry->crb_ctrl.opcode;
de8c72da 1760 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
33693c7a
VC		 1761 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
1762 crb_entry->value_1);
de8c72da 1763 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
068237c8 1764 }
de8c72da 1765 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
33693c7a
VC		 1766 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1767 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
de8c72da 1768 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
068237c8 1769 }
de8c72da 1770 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
33693c7a 1771 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8 1772 read_value &= crb_entry->value_2;
de8c72da
VC		 1773 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
1774 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
068237c8 1775 read_value |= crb_entry->value_3;
de8c72da 1776 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
068237c8 1777 }
33693c7a 1778 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
068237c8 1779 }
de8c72da 1780 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
33693c7a 1781 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8 1782 read_value |= crb_entry->value_3;
33693c7a 1783 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
de8c72da 1784 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
068237c8 1785 }
de8c72da 1786 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
068237c8
TP		 1787 poll_time = crb_entry->crb_strd.poll_timeout;
1788 wtime = jiffies + poll_time;
33693c7a 1789 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
068237c8
TP		 1790
1791 do {
1792 if ((read_value & crb_entry->value_2) ==
33693c7a 1793 crb_entry->value_1) {
068237c8 1794 break;
33693c7a 1795 } else if (time_after_eq(jiffies, wtime)) {
068237c8
TP		 1796 /* capturing dump failed */
1797 rval = QLA_ERROR;
1798 break;
33693c7a
VC		 1799 } else {
1800 ha->isp_ops->rd_reg_indirect(ha,
1801 crb_addr, &read_value);
1802 }
068237c8 1803 } while (1);
de8c72da 1804 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
068237c8
TP		 1805 }
1806
de8c72da 1807 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
068237c8
TP		 1808 if (crb_entry->crb_strd.state_index_a) {
1809 index = crb_entry->crb_strd.state_index_a;
1810 addr = tmplt_hdr->saved_state_array[index];
1811 } else {
1812 addr = crb_addr;
1813 }
1814
33693c7a 1815 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
068237c8
TP		 1816 index = crb_entry->crb_ctrl.state_index_v;
1817 tmplt_hdr->saved_state_array[index] = read_value;
de8c72da 1818 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
068237c8
TP		 1819 }
1820
de8c72da 1821 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
068237c8
TP		 1822 if (crb_entry->crb_strd.state_index_a) {
1823 index = crb_entry->crb_strd.state_index_a;
1824 addr = tmplt_hdr->saved_state_array[index];
1825 } else {
1826 addr = crb_addr;
1827 }
1828
1829 if (crb_entry->crb_ctrl.state_index_v) {
1830 index = crb_entry->crb_ctrl.state_index_v;
1831 read_value =
1832 tmplt_hdr->saved_state_array[index];
1833 } else {
1834 read_value = crb_entry->value_1;
1835 }
1836
33693c7a 1837 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
de8c72da 1838 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
068237c8
TP		 1839 }
1840
de8c72da 1841 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
068237c8
TP		 1842 index = crb_entry->crb_ctrl.state_index_v;
1843 read_value = tmplt_hdr->saved_state_array[index];
1844 read_value <<= crb_entry->crb_ctrl.shl;
1845 read_value >>= crb_entry->crb_ctrl.shr;
1846 if (crb_entry->value_2)
1847 read_value &= crb_entry->value_2;
1848 read_value |= crb_entry->value_3;
1849 read_value += crb_entry->value_1;
1850 tmplt_hdr->saved_state_array[index] = read_value;
de8c72da 1851 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
068237c8
TP		 1852 }
1853 crb_addr += crb_entry->crb_strd.addr_stride;
1854 }
1855 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1856 return rval;
1857}
1858
1859static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
7664a1fd 1860 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1861 uint32_t **d_ptr)
1862{
1863 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
7664a1fd 1864 struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
068237c8
TP		 1865 uint32_t *data_ptr = *d_ptr;
1866
1867 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1868 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
068237c8
TP		 1869 r_addr = ocm_hdr->read_addr;
1870 r_stride = ocm_hdr->read_addr_stride;
1871 loop_cnt = ocm_hdr->op_count;
1872
1873 DEBUG2(ql4_printk(KERN_INFO, ha,
1874 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
1875 __func__, r_addr, r_stride, loop_cnt));
1876
1877 for (i = 0; i < loop_cnt; i++) {
1878 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1879 *data_ptr++ = cpu_to_le32(r_value);
1880 r_addr += r_stride;
1881 }
1882 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
26fdf922 1883 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
068237c8
TP		 1884 *d_ptr = data_ptr;
1885}
1886
1887static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
7664a1fd 1888 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1889 uint32_t **d_ptr)
1890{
1891 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
7664a1fd 1892 struct qla8xxx_minidump_entry_mux *mux_hdr;
068237c8
TP		 1893 uint32_t *data_ptr = *d_ptr;
1894
1895 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1896 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
068237c8
TP		 1897 r_addr = mux_hdr->read_addr;
1898 s_addr = mux_hdr->select_addr;
1899 s_stride = mux_hdr->select_value_stride;
1900 s_value = mux_hdr->select_value;
1901 loop_cnt = mux_hdr->op_count;
1902
1903 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 1904 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
1905 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 1906 *data_ptr++ = cpu_to_le32(s_value);
1907 *data_ptr++ = cpu_to_le32(r_value);
1908 s_value += s_stride;
1909 }
1910 *d_ptr = data_ptr;
1911}
1912
1913static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
7664a1fd 1914 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1915 uint32_t **d_ptr)
1916{
1917 uint32_t addr, r_addr, c_addr, t_r_addr;
1918 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1919 uint32_t c_value_w;
7664a1fd 1920 struct qla8xxx_minidump_entry_cache *cache_hdr;
068237c8
TP		 1921 uint32_t *data_ptr = *d_ptr;
1922
7664a1fd 1923 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
068237c8
TP		 1924 loop_count = cache_hdr->op_count;
1925 r_addr = cache_hdr->read_addr;
1926 c_addr = cache_hdr->control_addr;
1927 c_value_w = cache_hdr->cache_ctrl.write_value;
1928
1929 t_r_addr = cache_hdr->tag_reg_addr;
1930 t_value = cache_hdr->addr_ctrl.init_tag_value;
1931 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1932
1933 for (i = 0; i < loop_count; i++) {
33693c7a
VC		 1934 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1935 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
068237c8
TP		 1936 addr = r_addr;
1937 for (k = 0; k < r_cnt; k++) {
33693c7a 1938 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
068237c8
TP		 1939 *data_ptr++ = cpu_to_le32(r_value);
1940 addr += cache_hdr->read_ctrl.read_addr_stride;
1941 }
1942 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1943 }
1944 *d_ptr = data_ptr;
1945}
1946
1947static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
7664a1fd 1948 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1949 uint32_t **d_ptr)
1950{
1951 uint32_t s_addr, r_addr;
1952 uint32_t r_stride, r_value, r_cnt, qid = 0;
1953 uint32_t i, k, loop_cnt;
7664a1fd 1954 struct qla8xxx_minidump_entry_queue *q_hdr;
068237c8
TP		 1955 uint32_t *data_ptr = *d_ptr;
1956
1957 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1958 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
068237c8
TP		 1959 s_addr = q_hdr->select_addr;
1960 r_cnt = q_hdr->rd_strd.read_addr_cnt;
1961 r_stride = q_hdr->rd_strd.read_addr_stride;
1962 loop_cnt = q_hdr->op_count;
1963
1964 for (i = 0; i < loop_cnt; i++) {
33693c7a 1965 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
068237c8
TP		 1966 r_addr = q_hdr->read_addr;
1967 for (k = 0; k < r_cnt; k++) {
33693c7a 1968 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
068237c8
TP		 1969 *data_ptr++ = cpu_to_le32(r_value);
1970 r_addr += r_stride;
1971 }
1972 qid += q_hdr->q_strd.queue_id_stride;
1973 }
1974 *d_ptr = data_ptr;
1975}
1976
1977#define MD_DIRECT_ROM_WINDOW 0x42110030
1978#define MD_DIRECT_ROM_READ_BASE 0x42150000
1979
f8086f4f 1980static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
7664a1fd 1981 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 1982 uint32_t **d_ptr)
1983{
1984 uint32_t r_addr, r_value;
1985 uint32_t i, loop_cnt;
7664a1fd 1986 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
068237c8
TP		 1987 uint32_t *data_ptr = *d_ptr;
1988
1989 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 1990 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
068237c8
TP		 1991 r_addr = rom_hdr->read_addr;
1992 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
1993
1994 DEBUG2(ql4_printk(KERN_INFO, ha,
1995 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
1996 __func__, r_addr, loop_cnt));
1997
1998 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 1999 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2000 (r_addr & 0xFFFF0000));
2001 ha->isp_ops->rd_reg_indirect(ha,
2002 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2003 &r_value);
068237c8
TP		 2004 *data_ptr++ = cpu_to_le32(r_value);
2005 r_addr += sizeof(uint32_t);
2006 }
2007 *d_ptr = data_ptr;
2008}
2009
2010#define MD_MIU_TEST_AGT_CTRL 0x41000090
2011#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
2012#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
2013
2014static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
7664a1fd 2015 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2016 uint32_t **d_ptr)
2017{
2018 uint32_t r_addr, r_value, r_data;
2019 uint32_t i, j, loop_cnt;
7664a1fd 2020 struct qla8xxx_minidump_entry_rdmem *m_hdr;
068237c8
TP		 2021 unsigned long flags;
2022 uint32_t *data_ptr = *d_ptr;
2023
2024 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
7664a1fd 2025 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
068237c8
TP		 2026 r_addr = m_hdr->read_addr;
2027 loop_cnt = m_hdr->read_data_size/16;
2028
2029 DEBUG2(ql4_printk(KERN_INFO, ha,
2030 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2031 __func__, r_addr, m_hdr->read_data_size));
2032
2033 if (r_addr & 0xf) {
2034 DEBUG2(ql4_printk(KERN_INFO, ha,
2035 "[%s]: Read addr 0x%x not 16 bytes alligned\n",
2036 __func__, r_addr));
2037 return QLA_ERROR;
2038 }
2039
2040 if (m_hdr->read_data_size % 16) {
2041 DEBUG2(ql4_printk(KERN_INFO, ha,
2042 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2043 __func__, m_hdr->read_data_size));
2044 return QLA_ERROR;
2045 }
2046
2047 DEBUG2(ql4_printk(KERN_INFO, ha,
2048 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2049 __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2050
2051 write_lock_irqsave(&ha->hw_lock, flags);
2052 for (i = 0; i < loop_cnt; i++) {
33693c7a
VC		 2053 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2054 r_addr);
068237c8 2055 r_value = 0;
33693c7a
VC		 2056 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2057 r_value);
068237c8 2058 r_value = MIU_TA_CTL_ENABLE;
33693c7a 2059 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
c38fa3ab 2060 r_value = MIU_TA_CTL_START_ENABLE;
33693c7a 2061 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
068237c8
TP		 2062
2063 for (j = 0; j < MAX_CTL_CHECK; j++) {
33693c7a
VC		 2064 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2065 &r_value);
068237c8
TP		 2066 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2067 break;
2068 }
2069
2070 if (j >= MAX_CTL_CHECK) {
2071 printk_ratelimited(KERN_ERR
2072 "%s: failed to read through agent\n",
2073 __func__);
2074 write_unlock_irqrestore(&ha->hw_lock, flags);
2075 return QLA_SUCCESS;
2076 }
2077
2078 for (j = 0; j < 4; j++) {
33693c7a
VC		 2079 ha->isp_ops->rd_reg_indirect(ha,
2080 MD_MIU_TEST_AGT_RDDATA[j],
2081 &r_data);
068237c8
TP		 2082 *data_ptr++ = cpu_to_le32(r_data);
2083 }
2084
2085 r_addr += 16;
2086 }
2087 write_unlock_irqrestore(&ha->hw_lock, flags);
2088
2089 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2090 __func__, (loop_cnt * 16)));
2091
2092 *d_ptr = data_ptr;
2093 return QLA_SUCCESS;
2094}
2095
5e9bcec7 2096static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
7664a1fd 2097 struct qla8xxx_minidump_entry_hdr *entry_hdr,
068237c8
TP		 2098 int index)
2099{
de8c72da 2100 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
068237c8
TP		 2101 DEBUG2(ql4_printk(KERN_INFO, ha,
2102 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2103 ha->host_no, index, entry_hdr->entry_type,
2104 entry_hdr->d_ctrl.entry_capture_mask));
2105}
2106
2107/**
f8086f4f 2108 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
068237c8
TP		 2109 * @ha: pointer to adapter structure
2110 **/
2111static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2112{
2113 int num_entry_hdr = 0;
7664a1fd 2114 struct qla8xxx_minidump_entry_hdr *entry_hdr;
068237c8
TP		 2115 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2116 uint32_t *data_ptr;
2117 uint32_t data_collected = 0;
2118 int i, rval = QLA_ERROR;
2119 uint64_t now;
2120 uint32_t timestamp;
2121
2122 if (!ha->fw_dump) {
2123 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2124 __func__, ha->host_no);
2125 return rval;
2126 }
2127
2128 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2129 ha->fw_dump_tmplt_hdr;
2130 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2131 ha->fw_dump_tmplt_size);
2132 data_collected += ha->fw_dump_tmplt_size;
2133
2134 num_entry_hdr = tmplt_hdr->num_of_entries;
2135 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2136 __func__, data_ptr);
2137 ql4_printk(KERN_INFO, ha,
2138 "[%s]: no of entry headers in Template: 0x%x\n",
2139 __func__, num_entry_hdr);
2140 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2141 __func__, ha->fw_dump_capture_mask);
2142 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2143 __func__, ha->fw_dump_size, ha->fw_dump_size);
2144
2145 /* Update current timestamp before taking dump */
2146 now = get_jiffies_64();
2147 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2148 tmplt_hdr->driver_timestamp = timestamp;
2149
7664a1fd 2150 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
068237c8
TP		 2151 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2152 tmplt_hdr->first_entry_offset);
2153
2154 /* Walk through the entry headers - validate/perform required action */
2155 for (i = 0; i < num_entry_hdr; i++) {
2156 if (data_collected >= ha->fw_dump_size) {
2157 ql4_printk(KERN_INFO, ha,
2158 "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2159 data_collected, ha->fw_dump_size);
2160 return rval;
2161 }
2162
2163 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2164 ha->fw_dump_capture_mask)) {
2165 entry_hdr->d_ctrl.driver_flags |=
de8c72da 2166 QLA8XXX_DBG_SKIPPED_FLAG;
068237c8
TP		 2167 goto skip_nxt_entry;
2168 }
2169
2170 DEBUG2(ql4_printk(KERN_INFO, ha,
2171 "Data collected: [0x%x], Dump size left:[0x%x]\n",
2172 data_collected,
2173 (ha->fw_dump_size - data_collected)));
2174
2175 /* Decode the entry type and take required action to capture
2176 * debug data
2177 */
2178 switch (entry_hdr->entry_type) {
de8c72da 2179 case QLA8XXX_RDEND:
5e9bcec7 2180 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8 2181 break;
de8c72da 2182 case QLA8XXX_CNTRL:
068237c8
TP		 2183 rval = qla4_8xxx_minidump_process_control(ha,
2184 entry_hdr);
2185 if (rval != QLA_SUCCESS) {
5e9bcec7 2186 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2187 goto md_failed;
2188 }
2189 break;
de8c72da 2190 case QLA8XXX_RDCRB:
068237c8
TP		 2191 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2192 &data_ptr);
2193 break;
de8c72da 2194 case QLA8XXX_RDMEM:
068237c8
TP		 2195 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2196 &data_ptr);
2197 if (rval != QLA_SUCCESS) {
5e9bcec7 2198 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2199 goto md_failed;
2200 }
2201 break;
de8c72da
VC		 2202 case QLA8XXX_BOARD:
2203 case QLA8XXX_RDROM:
f8086f4f 2204 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
068237c8
TP		 2205 &data_ptr);
2206 break;
de8c72da
VC		 2207 case QLA8XXX_L2DTG:
2208 case QLA8XXX_L2ITG:
2209 case QLA8XXX_L2DAT:
2210 case QLA8XXX_L2INS:
068237c8
TP		 2211 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2212 &data_ptr);
2213 if (rval != QLA_SUCCESS) {
5e9bcec7 2214 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2215 goto md_failed;
2216 }
2217 break;
de8c72da
VC		 2218 case QLA8XXX_L1DAT:
2219 case QLA8XXX_L1INS:
068237c8
TP		 2220 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2221 &data_ptr);
2222 break;
de8c72da 2223 case QLA8XXX_RDOCM:
068237c8
TP		 2224 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2225 &data_ptr);
2226 break;
de8c72da 2227 case QLA8XXX_RDMUX:
068237c8
TP		 2228 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2229 &data_ptr);
2230 break;
de8c72da 2231 case QLA8XXX_QUEUE:
068237c8
TP		 2232 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2233 &data_ptr);
2234 break;
de8c72da 2235 case QLA8XXX_RDNOP:
068237c8 2236 default:
5e9bcec7 2237 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
068237c8
TP		 2238 break;
2239 }
2240
2241 data_collected = (uint8_t *)data_ptr -
2242 ((uint8_t *)((uint8_t *)ha->fw_dump +
2243 ha->fw_dump_tmplt_size));
2244skip_nxt_entry:
2245 /* next entry in the template */
7664a1fd 2246 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
068237c8
TP		 2247 (((uint8_t *)entry_hdr) +
2248 entry_hdr->entry_size);
2249 }
2250
2251 if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) {
2252 ql4_printk(KERN_INFO, ha,
2253 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2254 data_collected, ha->fw_dump_size);
2255 goto md_failed;
2256 }
2257
2258 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2259 __func__, i));
2260md_failed:
2261 return rval;
2262}
2263
2264/**
2265 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2266 * @ha: pointer to adapter structure
2267 **/
2268static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2269{
2270 char event_string[40];
2271 char *envp[] = { event_string, NULL };
2272
2273 switch (code) {
2274 case QL4_UEVENT_CODE_FW_DUMP:
2275 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2276 ha->host_no);
2277 break;
2278 default:
2279 /*do nothing*/
2280 break;
2281 }
2282
2283 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2284}
2285
aec07cae
VC		 2286static void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
2287{
2288 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2289 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2290 if (!qla4_8xxx_collect_md_data(ha)) {
2291 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2292 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
2293 } else {
2294 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
2295 __func__);
2296 }
2297 }
2298}
2299
f4f5df23
VC		 2300/**
2301 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2302 * @ha: pointer to adapter structure
2303 *
2304 * Note: IDC lock must be held upon entry
2305 **/
2306static int
2307qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2308{
b25ee66f
SS		 2309 int rval = QLA_ERROR;
2310 int i, timeout;
f4f5df23 2311 uint32_t old_count, count;
b25ee66f 2312 int need_reset = 0, peg_stuck = 1;
f4f5df23 2313
33693c7a
VC		 2314 need_reset = ha->isp_ops->need_reset(ha);
2315 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
f4f5df23
VC		 2316
2317 for (i = 0; i < 10; i++) {
2318 timeout = msleep_interruptible(200);
2319 if (timeout) {
33693c7a
VC		 2320 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2321 QLA8XXX_DEV_FAILED);
b25ee66f 2322 return rval;
f4f5df23
VC		 2323 }
2324
33693c7a 2325 count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
f4f5df23 2326 if (count != old_count)
b25ee66f
SS		 2327 peg_stuck = 0;
2328 }
2329
2330 if (need_reset) {
2331 /* We are trying to perform a recovery here. */
2332 if (peg_stuck)
33693c7a 2333 ha->isp_ops->rom_lock_recovery(ha);
b25ee66f
SS		 2334 goto dev_initialize;
2335 } else {
2336 /* Start of day for this ha context. */
2337 if (peg_stuck) {
2338 /* Either we are the first or recovery in progress. */
33693c7a 2339 ha->isp_ops->rom_lock_recovery(ha);
b25ee66f
SS		 2340 goto dev_initialize;
2341 } else {
2342 /* Firmware already running. */
2343 rval = QLA_SUCCESS;
f4f5df23 2344 goto dev_ready;
b25ee66f 2345 }
f4f5df23
VC		 2346 }
2347
2348dev_initialize:
2349 /* set to DEV_INITIALIZING */
2350 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
33693c7a
VC		 2351 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2352 QLA8XXX_DEV_INITIALIZING);
f4f5df23 2353
33693c7a 2354 ha->isp_ops->idc_unlock(ha);
aec07cae 2355 qla4_8xxx_get_minidump(ha);
33693c7a
VC		 2356 rval = ha->isp_ops->restart_firmware(ha);
2357 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 2358
2359 if (rval != QLA_SUCCESS) {
2360 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2361 qla4_8xxx_clear_drv_active(ha);
33693c7a
VC		 2362 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2363 QLA8XXX_DEV_FAILED);
f4f5df23
VC		 2364 return rval;
2365 }
2366
2367dev_ready:
2368 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
33693c7a 2369 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
f4f5df23 2370
b25ee66f 2371 return rval;
f4f5df23
VC		 2372}
2373
2374/**
f8086f4f 2375 * qla4_82xx_need_reset_handler - Code to start reset sequence
f4f5df23
VC		 2376 * @ha: pointer to adapter structure
2377 *
2378 * Note: IDC lock must be held upon entry
2379 **/
2380static void
f8086f4f 2381qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
f4f5df23
VC		 2382{
2383 uint32_t dev_state, drv_state, drv_active;
068237c8 2384 uint32_t active_mask = 0xFFFFFFFF;
f4f5df23
VC		 2385 unsigned long reset_timeout;
2386
2387 ql4_printk(KERN_INFO, ha,
2388 "Performing ISP error recovery\n");
2389
2390 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
f8086f4f 2391 qla4_82xx_idc_unlock(ha);
f4f5df23 2392 ha->isp_ops->disable_intrs(ha);
f8086f4f 2393 qla4_82xx_idc_lock(ha);
f4f5df23
VC		 2394 }
2395
de8c72da 2396 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
068237c8
TP		 2397 DEBUG2(ql4_printk(KERN_INFO, ha,
2398 "%s(%ld): reset acknowledged\n",
2399 __func__, ha->host_no));
2400 qla4_8xxx_set_rst_ready(ha);
2401 } else {
2402 active_mask = (~(1 << (ha->func_num * 4)));
2403 }
f4f5df23
VC		 2404
2405 /* wait for 10 seconds for reset ack from all functions */
2406 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2407
f8086f4f
VC		 2408 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2409 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
f4f5df23
VC		 2410
2411 ql4_printk(KERN_INFO, ha,
2412 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2413 __func__, ha->host_no, drv_state, drv_active);
2414
068237c8 2415 while (drv_state != (drv_active & active_mask)) {
f4f5df23 2416 if (time_after_eq(jiffies, reset_timeout)) {
068237c8
TP		 2417 ql4_printk(KERN_INFO, ha,
2418 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2419 DRIVER_NAME, drv_state, drv_active);
f4f5df23
VC		 2420 break;
2421 }
2422
068237c8
TP		 2423 /*
2424 * When reset_owner times out, check which functions
2425 * acked/did not ack
2426 */
de8c72da 2427 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
068237c8
TP		 2428 ql4_printk(KERN_INFO, ha,
2429 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2430 __func__, ha->host_no, drv_state,
2431 drv_active);
2432 }
f8086f4f 2433 qla4_82xx_idc_unlock(ha);
f4f5df23 2434 msleep(1000);
f8086f4f 2435 qla4_82xx_idc_lock(ha);
f4f5df23 2436
f8086f4f
VC		 2437 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2438 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
f4f5df23
VC		 2439 }
2440
068237c8 2441 /* Clear RESET OWNER as we are not going to use it any further */
de8c72da 2442 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
068237c8 2443
f8086f4f 2444 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
068237c8
TP		 2445 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2446 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
f4f5df23
VC		 2447
2448 /* Force to DEV_COLD unless someone else is starting a reset */
de8c72da 2449 if (dev_state != QLA8XXX_DEV_INITIALIZING) {
f4f5df23 2450 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
de8c72da 2451 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
068237c8 2452 qla4_8xxx_set_rst_ready(ha);
f4f5df23
VC		 2453 }
2454}
2455
2456/**
2457 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2458 * @ha: pointer to adapter structure
2459 **/
2460void
2461qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2462{
33693c7a 2463 ha->isp_ops->idc_lock(ha);
f4f5df23 2464 qla4_8xxx_set_qsnt_ready(ha);
33693c7a 2465 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 2466}
2467
83dbdf6f
VC		 2468static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
2469{
2470 int idc_ver;
2471 uint32_t drv_active;
2472
2473 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2474 if (drv_active == (1 << (ha->func_num * 4))) {
2475 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
2476 QLA82XX_IDC_VERSION);
2477 ql4_printk(KERN_INFO, ha,
2478 "%s: IDC version updated to %d\n", __func__,
2479 QLA82XX_IDC_VERSION);
2480 } else {
2481 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2482 if (QLA82XX_IDC_VERSION != idc_ver) {
2483 ql4_printk(KERN_INFO, ha,
2484 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2485 __func__, QLA82XX_IDC_VERSION, idc_ver);
2486 }
2487 }
2488}
2489
2490static void qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
2491{
2492 if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2493 ha->isp_ops->idc_lock(ha);
2494 qla4_8xxx_set_drv_active(ha);
2495 qla4_82xx_set_idc_ver(ha);
2496 ha->isp_ops->idc_unlock(ha);
2497 }
2498}
2499
f4f5df23
VC		 2500/**
2501 * qla4_8xxx_device_state_handler - Adapter state machine
2502 * @ha: pointer to host adapter structure.
2503 *
2504 * Note: IDC lock must be UNLOCKED upon entry
2505 **/
2506int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2507{
2508 uint32_t dev_state;
2509 int rval = QLA_SUCCESS;
2510 unsigned long dev_init_timeout;
2511
83dbdf6f 2512 qla4_8xxx_update_idc_reg(ha);
f4f5df23 2513
33693c7a 2514 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
068237c8
TP		 2515 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2516 dev_state, dev_state < MAX_STATES ?
2517 qdev_state[dev_state] : "Unknown"));
f4f5df23
VC		 2518
2519 /* wait for 30 seconds for device to go ready */
2520 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2521
33693c7a 2522 ha->isp_ops->idc_lock(ha);
f4f5df23 2523 while (1) {
f4f5df23
VC		 2524
2525 if (time_after_eq(jiffies, dev_init_timeout)) {
068237c8
TP		 2526 ql4_printk(KERN_WARNING, ha,
2527 "%s: Device Init Failed 0x%x = %s\n",
2528 DRIVER_NAME,
2529 dev_state, dev_state < MAX_STATES ?
2530 qdev_state[dev_state] : "Unknown");
33693c7a
VC		 2531 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2532 QLA8XXX_DEV_FAILED);
f4f5df23
VC		 2533 }
2534
33693c7a 2535 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
068237c8
TP		 2536 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2537 dev_state, dev_state < MAX_STATES ?
2538 qdev_state[dev_state] : "Unknown");
f4f5df23
VC		 2539
2540 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2541 switch (dev_state) {
de8c72da 2542 case QLA8XXX_DEV_READY:
f4f5df23 2543 goto exit;
de8c72da 2544 case QLA8XXX_DEV_COLD:
f4f5df23 2545 rval = qla4_8xxx_device_bootstrap(ha);
f4f5df23 2546 goto exit;
de8c72da 2547 case QLA8XXX_DEV_INITIALIZING:
33693c7a 2548 ha->isp_ops->idc_unlock(ha);
f4f5df23 2549 msleep(1000);
33693c7a 2550 ha->isp_ops->idc_lock(ha);
f4f5df23 2551 break;
de8c72da 2552 case QLA8XXX_DEV_NEED_RESET:
f4f5df23 2553 if (!ql4xdontresethba) {
f8086f4f 2554 qla4_82xx_need_reset_handler(ha);
f4f5df23
VC		 2555 /* Update timeout value after need
2556 * reset handler */
2557 dev_init_timeout = jiffies +
2558 (ha->nx_dev_init_timeout * HZ);
9acf7533 2559 } else {
33693c7a 2560 ha->isp_ops->idc_unlock(ha);
9acf7533 2561 msleep(1000);
33693c7a 2562 ha->isp_ops->idc_lock(ha);
f4f5df23 2563 }
f4f5df23 2564 break;
de8c72da 2565 case QLA8XXX_DEV_NEED_QUIESCENT:
f4f5df23
VC		 2566 /* idc locked/unlocked in handler */
2567 qla4_8xxx_need_qsnt_handler(ha);
e3f37d16 2568 break;
de8c72da 2569 case QLA8XXX_DEV_QUIESCENT:
33693c7a 2570 ha->isp_ops->idc_unlock(ha);
f4f5df23 2571 msleep(1000);
33693c7a 2572 ha->isp_ops->idc_lock(ha);
f4f5df23 2573 break;
de8c72da 2574 case QLA8XXX_DEV_FAILED:
33693c7a 2575 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 2576 qla4xxx_dead_adapter_cleanup(ha);
2577 rval = QLA_ERROR;
33693c7a 2578 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 2579 goto exit;
2580 default:
33693c7a 2581 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 2582 qla4xxx_dead_adapter_cleanup(ha);
2583 rval = QLA_ERROR;
33693c7a 2584 ha->isp_ops->idc_lock(ha);
f4f5df23
VC		 2585 goto exit;
2586 }
2587 }
2588exit:
33693c7a 2589 ha->isp_ops->idc_unlock(ha);
f4f5df23
VC		 2590 return rval;
2591}
2592
2593int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2594{
2595 int retval;
78764999
SR		 2596
2597 /* clear the interrupt */
7664a1fd
VC		 2598 writel(0, &ha->qla4_82xx_reg->host_int);
2599 readl(&ha->qla4_82xx_reg->host_int);
78764999 2600
f4f5df23
VC		 2601 retval = qla4_8xxx_device_state_handler(ha);
2602
f581a3f7 2603 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
f4f5df23 2604 retval = qla4xxx_request_irqs(ha);
f581a3f7 2605
f4f5df23
VC		 2606 return retval;
2607}
2608
2609/*****************************************************************************/
2610/* Flash Manipulation Routines */
2611/*****************************************************************************/
2612
2613#define OPTROM_BURST_SIZE 0x1000
2614#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
2615
2616#define FARX_DATA_FLAG BIT_31
2617#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
2618#define FARX_ACCESS_FLASH_DATA 0x7FF00000
2619
2620static inline uint32_t
2621flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2622{
2623 return hw->flash_conf_off | faddr;
2624}
2625
2626static inline uint32_t
2627flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2628{
2629 return hw->flash_data_off | faddr;
2630}
2631
2632static uint32_t *
f8086f4f 2633qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
f4f5df23
VC		 2634 uint32_t faddr, uint32_t length)
2635{
2636 uint32_t i;
2637 uint32_t val;
2638 int loops = 0;
f8086f4f 2639 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
f4f5df23
VC		 2640 udelay(100);
2641 cond_resched();
2642 loops++;
2643 }
2644 if (loops >= 50000) {
2645 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
2646 return dwptr;
2647 }
2648
2649 /* Dword reads to flash. */
2650 for (i = 0; i < length/4; i++, faddr += 4) {
f8086f4f 2651 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
f4f5df23
VC		 2652 ql4_printk(KERN_WARNING, ha,
2653 "Do ROM fast read failed\n");
2654 goto done_read;
2655 }
2656 dwptr[i] = __constant_cpu_to_le32(val);
2657 }
2658
2659done_read:
f8086f4f 2660 qla4_82xx_rom_unlock(ha);
f4f5df23
VC		 2661 return dwptr;
2662}
2663
2664/**
2665 * Address and length are byte address
2666 **/
2667static uint8_t *
f8086f4f 2668qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
f4f5df23
VC		 2669 uint32_t offset, uint32_t length)
2670{
f8086f4f 2671 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
f4f5df23
VC		 2672 return buf;
2673}
2674
2675static int
2676qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
2677{
2678 const char *loc, *locations[] = { "DEF", "PCI" };
2679
2680 /*
2681 * FLT-location structure resides after the last PCI region.
2682 */
2683
2684 /* Begin with sane defaults. */
2685 loc = locations[0];
2686 *start = FA_FLASH_LAYOUT_ADDR_82;
2687
2688 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
2689 return QLA_SUCCESS;
2690}
2691
2692static void
2693qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
2694{
2695 const char *loc, *locations[] = { "DEF", "FLT" };
2696 uint16_t *wptr;
2697 uint16_t cnt, chksum;
2698 uint32_t start;
2699 struct qla_flt_header *flt;
2700 struct qla_flt_region *region;
2701 struct ql82xx_hw_data *hw = &ha->hw;
2702
2703 hw->flt_region_flt = flt_addr;
2704 wptr = (uint16_t *)ha->request_ring;
2705 flt = (struct qla_flt_header *)ha->request_ring;
2706 region = (struct qla_flt_region *)&flt[1];
f8086f4f 2707 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
f4f5df23
VC		 2708 flt_addr << 2, OPTROM_BURST_SIZE);
2709 if (*wptr == __constant_cpu_to_le16(0xffff))
2710 goto no_flash_data;
2711 if (flt->version != __constant_cpu_to_le16(1)) {
2712 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
2713 "version=0x%x length=0x%x checksum=0x%x.\n",
2714 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2715 le16_to_cpu(flt->checksum)));
2716 goto no_flash_data;
2717 }
2718
2719 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
2720 for (chksum = 0; cnt; cnt--)
2721 chksum += le16_to_cpu(*wptr++);
2722 if (chksum) {
2723 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
2724 "version=0x%x length=0x%x checksum=0x%x.\n",
2725 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2726 chksum));
2727 goto no_flash_data;
2728 }
2729
2730 loc = locations[1];
2731 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2732 for ( ; cnt; cnt--, region++) {
2733 /* Store addresses as DWORD offsets. */
2734 start = le32_to_cpu(region->start) >> 2;
2735
2736 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
2737 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
2738 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
2739
2740 switch (le32_to_cpu(region->code) & 0xff) {
2741 case FLT_REG_FDT:
2742 hw->flt_region_fdt = start;
2743 break;
2744 case FLT_REG_BOOT_CODE_82:
2745 hw->flt_region_boot = start;
2746 break;
2747 case FLT_REG_FW_82:
93823956 2748 case FLT_REG_FW_82_1:
f4f5df23
VC		 2749 hw->flt_region_fw = start;
2750 break;
2751 case FLT_REG_BOOTLOAD_82:
2752 hw->flt_region_bootload = start;
2753 break;
2a991c21
MR		 2754 case FLT_REG_ISCSI_PARAM:
2755 hw->flt_iscsi_param = start;
2756 break;
4549415a
LC		 2757 case FLT_REG_ISCSI_CHAP:
2758 hw->flt_region_chap = start;
2759 hw->flt_chap_size = le32_to_cpu(region->size);
2760 break;
f4f5df23
VC		 2761 }
2762 }
2763 goto done;
2764
2765no_flash_data:
2766 /* Use hardcoded defaults. */
2767 loc = locations[0];
2768
2769 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
2770 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
2771 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2772 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
4549415a
LC		 2773 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP;
2774 hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
2775
f4f5df23
VC		 2776done:
2777 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2778 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2779 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2780 hw->flt_region_fw));
2781}
2782
2783static void
f8086f4f 2784qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
f4f5df23
VC		 2785{
2786#define FLASH_BLK_SIZE_4K 0x1000
2787#define FLASH_BLK_SIZE_32K 0x8000
2788#define FLASH_BLK_SIZE_64K 0x10000
2789 const char *loc, *locations[] = { "MID", "FDT" };
2790 uint16_t cnt, chksum;
2791 uint16_t *wptr;
2792 struct qla_fdt_layout *fdt;
3c3e2108
VC		 2793 uint16_t mid = 0;
2794 uint16_t fid = 0;
f4f5df23
VC		 2795 struct ql82xx_hw_data *hw = &ha->hw;
2796
2797 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2798 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2799
2800 wptr = (uint16_t *)ha->request_ring;
2801 fdt = (struct qla_fdt_layout *)ha->request_ring;
f8086f4f 2802 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
f4f5df23
VC		 2803 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2804
2805 if (*wptr == __constant_cpu_to_le16(0xffff))
2806 goto no_flash_data;
2807
2808 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2809 fdt->sig[3] != 'D')
2810 goto no_flash_data;
2811
2812 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2813 cnt++)
2814 chksum += le16_to_cpu(*wptr++);
2815
2816 if (chksum) {
2817 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2818 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2819 le16_to_cpu(fdt->version)));
2820 goto no_flash_data;
2821 }
2822
2823 loc = locations[1];
2824 mid = le16_to_cpu(fdt->man_id);
2825 fid = le16_to_cpu(fdt->id);
2826 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2827 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2828 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2829
2830 if (fdt->unprotect_sec_cmd) {
2831 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2832 fdt->unprotect_sec_cmd);
2833 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2834 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2835 flash_conf_addr(hw, 0x0336);
2836 }
2837 goto done;
2838
2839no_flash_data:
2840 loc = locations[0];
2841 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2842done:
2843 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2844 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2845 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2846 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2847 hw->fdt_block_size));
2848}
2849
2850static void
f8086f4f 2851qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
f4f5df23
VC		 2852{
2853#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2854 uint32_t *wptr;
2855
2856 if (!is_qla8022(ha))
2857 return;
2858 wptr = (uint32_t *)ha->request_ring;
f8086f4f 2859 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
f4f5df23
VC		 2860 QLA82XX_IDC_PARAM_ADDR , 8);
2861
2862 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2863 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2864 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2865 } else {
2866 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2867 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2868 }
2869
2870 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2871 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2872 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2873 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2874 return;
33693c7a
VC		 2875}
2876
2877void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
2878 int in_count)
2879{
2880 int i;
2881
2882 /* Load all mailbox registers, except mailbox 0. */
2883 for (i = 1; i < in_count; i++)
2884 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
2885
2886 /* Wakeup firmware */
2887 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
2888 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
2889 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
2890 readl(&ha->qla4_82xx_reg->hint);
2891}
2892
2893void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
2894{
2895 int intr_status;
2896
2897 intr_status = readl(&ha->qla4_82xx_reg->host_int);
2898 if (intr_status & ISRX_82XX_RISC_INT) {
2899 ha->mbox_status_count = out_count;
2900 intr_status = readl(&ha->qla4_82xx_reg->host_status);
2901 ha->isp_ops->interrupt_service_routine(ha, intr_status);
2902
2903 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
2904 test_bit(AF_INTx_ENABLED, &ha->flags))
2905 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
2906 0xfbff);
2907 }
f4f5df23
VC		 2908}
2909
2910int
2911qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2912{
2913 int ret;
2914 uint32_t flt_addr;
2915
2916 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2917 if (ret != QLA_SUCCESS)
2918 return ret;
2919
2920 qla4_8xxx_get_flt_info(ha, flt_addr);
f8086f4f
VC		 2921 qla4_82xx_get_fdt_info(ha);
2922 qla4_82xx_get_idc_param(ha);
f4f5df23
VC		 2923
2924 return QLA_SUCCESS;
2925}
2926
2927/**
2928 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2929 * @ha: pointer to host adapter structure.
2930 *
2931 * Remarks:
2932 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2933 * not be available after successful return. Driver must cleanup potential
2934 * outstanding I/O's after calling this funcion.
2935 **/
2936int
2937qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2938{
2939 int status;
2940 uint32_t mbox_cmd[MBOX_REG_COUNT];
2941 uint32_t mbox_sts[MBOX_REG_COUNT];
2942
2943 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2944 memset(&mbox_sts, 0, sizeof(mbox_sts));
2945
2946 mbox_cmd[0] = MBOX_CMD_STOP_FW;
2947 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2948 &mbox_cmd[0], &mbox_sts[0]);
2949
2950 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2951 __func__, status));
2952 return status;
2953}
2954
2955/**
f8086f4f 2956 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
f4f5df23
VC		 2957 * @ha: pointer to host adapter structure.
2958 **/
2959int
f8086f4f 2960qla4_82xx_isp_reset(struct scsi_qla_host *ha)
f4f5df23
VC		 2961{
2962 int rval;
2963 uint32_t dev_state;
2964
f8086f4f
VC		 2965 qla4_82xx_idc_lock(ha);
2966 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
f4f5df23 2967
de8c72da 2968 if (dev_state == QLA8XXX_DEV_READY) {
f4f5df23 2969 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
f8086f4f 2970 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
de8c72da
VC		 2971 QLA8XXX_DEV_NEED_RESET);
2972 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
f4f5df23
VC		 2973 } else
2974 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2975
f8086f4f 2976 qla4_82xx_idc_unlock(ha);
f4f5df23
VC		 2977
2978 rval = qla4_8xxx_device_state_handler(ha);
2979
f8086f4f 2980 qla4_82xx_idc_lock(ha);
f4f5df23 2981 qla4_8xxx_clear_rst_ready(ha);
f8086f4f 2982 qla4_82xx_idc_unlock(ha);
f4f5df23 2983
068237c8 2984 if (rval == QLA_SUCCESS) {
f8086f4f 2985 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
21033639 2986 clear_bit(AF_FW_RECOVERY, &ha->flags);
068237c8 2987 }
21033639 2988
f4f5df23
VC		 2989 return rval;
2990}
2991
2992/**
2993 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2994 * @ha: pointer to host adapter structure.
2995 *
2996 **/
2997int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2998{
2999 uint32_t mbox_cmd[MBOX_REG_COUNT];
3000 uint32_t mbox_sts[MBOX_REG_COUNT];
3001 struct mbx_sys_info *sys_info;
3002 dma_addr_t sys_info_dma;
3003 int status = QLA_ERROR;
3004
3005 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3006 &sys_info_dma, GFP_KERNEL);
3007 if (sys_info == NULL) {
3008 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3009 ha->host_no, __func__));
3010 return status;
3011 }
3012
3013 memset(sys_info, 0, sizeof(*sys_info));
3014 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3015 memset(&mbox_sts, 0, sizeof(mbox_sts));
3016
3017 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3018 mbox_cmd[1] = LSDW(sys_info_dma);
3019 mbox_cmd[2] = MSDW(sys_info_dma);
3020 mbox_cmd[4] = sizeof(*sys_info);
3021
3022 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3023 &mbox_sts[0]) != QLA_SUCCESS) {
3024 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3025 ha->host_no, __func__));
3026 goto exit_validate_mac82;
3027 }
3028
2ccdf0dc
VC		 3029 /* Make sure we receive the minimum required data to cache internally */
3030 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
f4f5df23
VC		 3031 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3032 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3033 goto exit_validate_mac82;
3034
3035 }
3036
3037 /* Save M.A.C. address & serial_number */
2a991c21 3038 ha->port_num = sys_info->port_num;
f4f5df23
VC		 3039 memcpy(ha->my_mac, &sys_info->mac_addr[0],
3040 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3041 memcpy(ha->serial_number, &sys_info->serial_number,
3042 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
91ec7cec
VC		 3043 memcpy(ha->model_name, &sys_info->board_id_str,
3044 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3045 ha->phy_port_cnt = sys_info->phys_port_cnt;
3046 ha->phy_port_num = sys_info->port_num;
3047 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
f4f5df23
VC		 3048
3049 DEBUG2(printk("scsi%ld: %s: "
3050 "mac %02x:%02x:%02x:%02x:%02x:%02x "
3051 "serial %s\n", ha->host_no, __func__,
3052 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
3053 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
3054 ha->serial_number));
3055
3056 status = QLA_SUCCESS;
3057
3058exit_validate_mac82:
3059 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
3060 sys_info_dma);
3061 return status;
3062}
3063
3064/* Interrupt handling helpers. */
3065
3066static int
3067qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
3068{
3069 uint32_t mbox_cmd[MBOX_REG_COUNT];
3070 uint32_t mbox_sts[MBOX_REG_COUNT];
3071
3072 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3073
3074 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3075 memset(&mbox_sts, 0, sizeof(mbox_sts));
3076 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3077 mbox_cmd[1] = INTR_ENABLE;
3078 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3079 &mbox_sts[0]) != QLA_SUCCESS) {
3080 DEBUG2(ql4_printk(KERN_INFO, ha,
3081 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3082 __func__, mbox_sts[0]));
3083 return QLA_ERROR;
3084 }
3085 return QLA_SUCCESS;
3086}
3087
3088static int
3089qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3090{
3091 uint32_t mbox_cmd[MBOX_REG_COUNT];
3092 uint32_t mbox_sts[MBOX_REG_COUNT];
3093
3094 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3095
3096 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3097 memset(&mbox_sts, 0, sizeof(mbox_sts));
3098 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3099 mbox_cmd[1] = INTR_DISABLE;
3100 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3101 &mbox_sts[0]) != QLA_SUCCESS) {
3102 DEBUG2(ql4_printk(KERN_INFO, ha,
3103 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3104 __func__, mbox_sts[0]));
3105 return QLA_ERROR;
3106 }
3107
3108 return QLA_SUCCESS;
3109}
3110
3111void
f8086f4f 3112qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
f4f5df23
VC		 3113{
3114 qla4_8xxx_mbx_intr_enable(ha);
3115
3116 spin_lock_irq(&ha->hardware_lock);
3117 /* BIT 10 - reset */
f8086f4f 3118 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
f4f5df23
VC		 3119 spin_unlock_irq(&ha->hardware_lock);
3120 set_bit(AF_INTERRUPTS_ON, &ha->flags);
3121}
3122
3123void
f8086f4f 3124qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
f4f5df23 3125{
5fa8b573 3126 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
f4f5df23
VC		 3127 qla4_8xxx_mbx_intr_disable(ha);
3128
3129 spin_lock_irq(&ha->hardware_lock);
3130 /* BIT 10 - set */
f8086f4f 3131 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
f4f5df23 3132 spin_unlock_irq(&ha->hardware_lock);
f4f5df23
VC		 3133}
3134
3135struct ql4_init_msix_entry {
3136 uint16_t entry;
3137 uint16_t index;
3138 const char *name;
3139 irq_handler_t handler;
3140};
3141
3142static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3143 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3144 "qla4xxx (default)",
3145 (irq_handler_t)qla4_8xxx_default_intr_handler },
3146 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3147 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3148};
3149
3150void
3151qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3152{
3153 int i;
3154 struct ql4_msix_entry *qentry;
3155
3156 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3157 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3158 if (qentry->have_irq) {
3159 free_irq(qentry->msix_vector, ha);
3160 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3161 __func__, qla4_8xxx_msix_entries[i].name));
3162 }
3163 }
3164 pci_disable_msix(ha->pdev);
3165 clear_bit(AF_MSIX_ENABLED, &ha->flags);
3166}
3167
3168int
3169qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3170{
3171 int i, ret;
3172 struct msix_entry entries[QLA_MSIX_ENTRIES];
3173 struct ql4_msix_entry *qentry;
3174
3175 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3176 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3177
3178 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3179 if (ret) {
3180 ql4_printk(KERN_WARNING, ha,
3181 "MSI-X: Failed to enable support -- %d/%d\n",
3182 QLA_MSIX_ENTRIES, ret);
3183 goto msix_out;
3184 }
3185 set_bit(AF_MSIX_ENABLED, &ha->flags);
3186
3187 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3188 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3189 qentry->msix_vector = entries[i].vector;
3190 qentry->msix_entry = entries[i].entry;
3191 qentry->have_irq = 0;
3192 ret = request_irq(qentry->msix_vector,
3193 qla4_8xxx_msix_entries[i].handler, 0,
3194 qla4_8xxx_msix_entries[i].name, ha);
3195 if (ret) {
3196 ql4_printk(KERN_WARNING, ha,
3197 "MSI-X: Unable to register handler -- %x/%d.\n",
3198 qla4_8xxx_msix_entries[i].index, ret);
3199 qla4_8xxx_disable_msix(ha);
3200 goto msix_out;
3201 }
3202 qentry->have_irq = 1;
3203 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3204 __func__, qla4_8xxx_msix_entries[i].name));
3205 }
3206msix_out:
3207 return ret;
3208}
Linux 6.x block layer and io_uring tree(s)