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f4f5df23 VC |
1 | /* |
2 | * QLogic iSCSI HBA Driver | |
4a4f51e9 | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
f4f5df23 VC |
4 | * |
5 | * See LICENSE.qla4xxx for copyright and licensing details. | |
6 | */ | |
7 | #include <linux/delay.h> | |
a6751ccb | 8 | #include <linux/io.h> |
f4f5df23 | 9 | #include <linux/pci.h> |
068237c8 | 10 | #include <linux/ratelimit.h> |
f4f5df23 VC |
11 | #include "ql4_def.h" |
12 | #include "ql4_glbl.h" | |
6e7b4292 | 13 | #include "ql4_inline.h" |
f4f5df23 | 14 | |
2f8e2c87 | 15 | #include <linux/io-64-nonatomic-lo-hi.h> |
797a796a | 16 | |
b1829789 | 17 | #define TIMEOUT_100_MS 100 |
f4f5df23 VC |
18 | #define MASK(n) DMA_BIT_MASK(n) |
19 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
20 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
21 | #define MS_WIN(addr) (addr & 0x0ffc0000) | |
22 | #define QLA82XX_PCI_MN_2M (0) | |
23 | #define QLA82XX_PCI_MS_2M (0x80000) | |
24 | #define QLA82XX_PCI_OCM0_2M (0xc0000) | |
25 | #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) | |
26 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
27 | ||
28 | /* CRB window related */ | |
29 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
30 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
31 | #define CRB_WINDOW_2M (0x130060) | |
7664a1fd | 32 | #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ |
f4f5df23 VC |
33 | ((off) & 0xf0000)) |
34 | #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) | |
35 | #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) | |
36 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
37 | ||
38 | static inline void __iomem * | |
39 | qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) | |
40 | { | |
41 | if ((off < ha->first_page_group_end) && | |
42 | (off >= ha->first_page_group_start)) | |
43 | return (void __iomem *)(ha->nx_pcibase + off); | |
44 | ||
45 | return NULL; | |
46 | } | |
47 | ||
bb83e59d BVA |
48 | static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, |
49 | 0x410000AC, 0x410000B8, 0x410000BC }; | |
f4f5df23 VC |
50 | #define MAX_CRB_XFORM 60 |
51 | static unsigned long crb_addr_xform[MAX_CRB_XFORM]; | |
52 | static int qla4_8xxx_crb_table_initialized; | |
53 | ||
54 | #define qla4_8xxx_crb_addr_transform(name) \ | |
55 | (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ | |
56 | QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) | |
57 | static void | |
f8086f4f | 58 | qla4_82xx_crb_addr_transform_setup(void) |
f4f5df23 VC |
59 | { |
60 | qla4_8xxx_crb_addr_transform(XDMA); | |
61 | qla4_8xxx_crb_addr_transform(TIMR); | |
62 | qla4_8xxx_crb_addr_transform(SRE); | |
63 | qla4_8xxx_crb_addr_transform(SQN3); | |
64 | qla4_8xxx_crb_addr_transform(SQN2); | |
65 | qla4_8xxx_crb_addr_transform(SQN1); | |
66 | qla4_8xxx_crb_addr_transform(SQN0); | |
67 | qla4_8xxx_crb_addr_transform(SQS3); | |
68 | qla4_8xxx_crb_addr_transform(SQS2); | |
69 | qla4_8xxx_crb_addr_transform(SQS1); | |
70 | qla4_8xxx_crb_addr_transform(SQS0); | |
71 | qla4_8xxx_crb_addr_transform(RPMX7); | |
72 | qla4_8xxx_crb_addr_transform(RPMX6); | |
73 | qla4_8xxx_crb_addr_transform(RPMX5); | |
74 | qla4_8xxx_crb_addr_transform(RPMX4); | |
75 | qla4_8xxx_crb_addr_transform(RPMX3); | |
76 | qla4_8xxx_crb_addr_transform(RPMX2); | |
77 | qla4_8xxx_crb_addr_transform(RPMX1); | |
78 | qla4_8xxx_crb_addr_transform(RPMX0); | |
79 | qla4_8xxx_crb_addr_transform(ROMUSB); | |
80 | qla4_8xxx_crb_addr_transform(SN); | |
81 | qla4_8xxx_crb_addr_transform(QMN); | |
82 | qla4_8xxx_crb_addr_transform(QMS); | |
83 | qla4_8xxx_crb_addr_transform(PGNI); | |
84 | qla4_8xxx_crb_addr_transform(PGND); | |
85 | qla4_8xxx_crb_addr_transform(PGN3); | |
86 | qla4_8xxx_crb_addr_transform(PGN2); | |
87 | qla4_8xxx_crb_addr_transform(PGN1); | |
88 | qla4_8xxx_crb_addr_transform(PGN0); | |
89 | qla4_8xxx_crb_addr_transform(PGSI); | |
90 | qla4_8xxx_crb_addr_transform(PGSD); | |
91 | qla4_8xxx_crb_addr_transform(PGS3); | |
92 | qla4_8xxx_crb_addr_transform(PGS2); | |
93 | qla4_8xxx_crb_addr_transform(PGS1); | |
94 | qla4_8xxx_crb_addr_transform(PGS0); | |
95 | qla4_8xxx_crb_addr_transform(PS); | |
96 | qla4_8xxx_crb_addr_transform(PH); | |
97 | qla4_8xxx_crb_addr_transform(NIU); | |
98 | qla4_8xxx_crb_addr_transform(I2Q); | |
99 | qla4_8xxx_crb_addr_transform(EG); | |
100 | qla4_8xxx_crb_addr_transform(MN); | |
101 | qla4_8xxx_crb_addr_transform(MS); | |
102 | qla4_8xxx_crb_addr_transform(CAS2); | |
103 | qla4_8xxx_crb_addr_transform(CAS1); | |
104 | qla4_8xxx_crb_addr_transform(CAS0); | |
105 | qla4_8xxx_crb_addr_transform(CAM); | |
106 | qla4_8xxx_crb_addr_transform(C2C1); | |
107 | qla4_8xxx_crb_addr_transform(C2C0); | |
108 | qla4_8xxx_crb_addr_transform(SMB); | |
109 | qla4_8xxx_crb_addr_transform(OCM0); | |
110 | qla4_8xxx_crb_addr_transform(I2C0); | |
111 | ||
112 | qla4_8xxx_crb_table_initialized = 1; | |
113 | } | |
114 | ||
115 | static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { | |
116 | {{{0, 0, 0, 0} } }, /* 0: PCI */ | |
117 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ | |
118 | {1, 0x0110000, 0x0120000, 0x130000}, | |
119 | {1, 0x0120000, 0x0122000, 0x124000}, | |
120 | {1, 0x0130000, 0x0132000, 0x126000}, | |
121 | {1, 0x0140000, 0x0142000, 0x128000}, | |
122 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
123 | {1, 0x0160000, 0x0170000, 0x110000}, | |
124 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {0, 0x0000000, 0x0000000, 0x000000}, | |
128 | {0, 0x0000000, 0x0000000, 0x000000}, | |
129 | {0, 0x0000000, 0x0000000, 0x000000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
132 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
133 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ | |
134 | {{{0, 0, 0, 0} } }, /* 3: */ | |
135 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ | |
136 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ | |
137 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ | |
138 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ | |
139 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {0, 0x0000000, 0x0000000, 0x000000}, | |
144 | {0, 0x0000000, 0x0000000, 0x000000}, | |
145 | {0, 0x0000000, 0x0000000, 0x000000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {0, 0x0000000, 0x0000000, 0x000000}, | |
148 | {0, 0x0000000, 0x0000000, 0x000000}, | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {0, 0x0000000, 0x0000000, 0x000000}, | |
151 | {0, 0x0000000, 0x0000000, 0x000000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
155 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {0, 0x0000000, 0x0000000, 0x000000}, | |
160 | {0, 0x0000000, 0x0000000, 0x000000}, | |
161 | {0, 0x0000000, 0x0000000, 0x000000}, | |
162 | {0, 0x0000000, 0x0000000, 0x000000}, | |
163 | {0, 0x0000000, 0x0000000, 0x000000}, | |
164 | {0, 0x0000000, 0x0000000, 0x000000}, | |
165 | {0, 0x0000000, 0x0000000, 0x000000}, | |
166 | {0, 0x0000000, 0x0000000, 0x000000}, | |
167 | {0, 0x0000000, 0x0000000, 0x000000}, | |
168 | {0, 0x0000000, 0x0000000, 0x000000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
171 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {0, 0x0000000, 0x0000000, 0x000000}, | |
176 | {0, 0x0000000, 0x0000000, 0x000000}, | |
177 | {0, 0x0000000, 0x0000000, 0x000000}, | |
178 | {0, 0x0000000, 0x0000000, 0x000000}, | |
179 | {0, 0x0000000, 0x0000000, 0x000000}, | |
180 | {0, 0x0000000, 0x0000000, 0x000000}, | |
181 | {0, 0x0000000, 0x0000000, 0x000000}, | |
182 | {0, 0x0000000, 0x0000000, 0x000000}, | |
183 | {0, 0x0000000, 0x0000000, 0x000000}, | |
184 | {0, 0x0000000, 0x0000000, 0x000000}, | |
185 | {0, 0x0000000, 0x0000000, 0x000000}, | |
186 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
187 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ | |
188 | {0, 0x0000000, 0x0000000, 0x000000}, | |
189 | {0, 0x0000000, 0x0000000, 0x000000}, | |
190 | {0, 0x0000000, 0x0000000, 0x000000}, | |
191 | {0, 0x0000000, 0x0000000, 0x000000}, | |
192 | {0, 0x0000000, 0x0000000, 0x000000}, | |
193 | {0, 0x0000000, 0x0000000, 0x000000}, | |
194 | {0, 0x0000000, 0x0000000, 0x000000}, | |
195 | {0, 0x0000000, 0x0000000, 0x000000}, | |
196 | {0, 0x0000000, 0x0000000, 0x000000}, | |
197 | {0, 0x0000000, 0x0000000, 0x000000}, | |
198 | {0, 0x0000000, 0x0000000, 0x000000}, | |
199 | {0, 0x0000000, 0x0000000, 0x000000}, | |
200 | {0, 0x0000000, 0x0000000, 0x000000}, | |
201 | {0, 0x0000000, 0x0000000, 0x000000}, | |
202 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
203 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ | |
204 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ | |
205 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ | |
206 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ | |
207 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ | |
208 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ | |
209 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ | |
210 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ | |
211 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ | |
212 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ | |
213 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ | |
214 | {{{0, 0, 0, 0} } }, /* 23: */ | |
215 | {{{0, 0, 0, 0} } }, /* 24: */ | |
216 | {{{0, 0, 0, 0} } }, /* 25: */ | |
217 | {{{0, 0, 0, 0} } }, /* 26: */ | |
218 | {{{0, 0, 0, 0} } }, /* 27: */ | |
219 | {{{0, 0, 0, 0} } }, /* 28: */ | |
220 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ | |
221 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ | |
222 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ | |
223 | {{{0} } }, /* 32: PCI */ | |
224 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ | |
225 | {1, 0x2110000, 0x2120000, 0x130000}, | |
226 | {1, 0x2120000, 0x2122000, 0x124000}, | |
227 | {1, 0x2130000, 0x2132000, 0x126000}, | |
228 | {1, 0x2140000, 0x2142000, 0x128000}, | |
229 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
230 | {1, 0x2160000, 0x2170000, 0x110000}, | |
231 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
232 | {0, 0x0000000, 0x0000000, 0x000000}, | |
233 | {0, 0x0000000, 0x0000000, 0x000000}, | |
234 | {0, 0x0000000, 0x0000000, 0x000000}, | |
235 | {0, 0x0000000, 0x0000000, 0x000000}, | |
236 | {0, 0x0000000, 0x0000000, 0x000000}, | |
237 | {0, 0x0000000, 0x0000000, 0x000000}, | |
238 | {0, 0x0000000, 0x0000000, 0x000000}, | |
239 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
240 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ | |
241 | {{{0} } }, /* 35: */ | |
242 | {{{0} } }, /* 36: */ | |
243 | {{{0} } }, /* 37: */ | |
244 | {{{0} } }, /* 38: */ | |
245 | {{{0} } }, /* 39: */ | |
246 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ | |
247 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ | |
248 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ | |
249 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ | |
250 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ | |
251 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ | |
252 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ | |
253 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ | |
254 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ | |
255 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ | |
256 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ | |
257 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ | |
258 | {{{0} } }, /* 52: */ | |
259 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ | |
260 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ | |
261 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ | |
262 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ | |
263 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ | |
264 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ | |
265 | {{{0} } }, /* 59: I2C0 */ | |
266 | {{{0} } }, /* 60: I2C1 */ | |
267 | {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ | |
268 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ | |
269 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ | |
270 | }; | |
271 | ||
272 | /* | |
273 | * top 12 bits of crb internal address (hub, agent) | |
274 | */ | |
7664a1fd | 275 | static unsigned qla4_82xx_crb_hub_agt[64] = { |
f4f5df23 VC |
276 | 0, |
277 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
278 | QLA82XX_HW_CRB_HUB_AGT_ADR_MN, | |
279 | QLA82XX_HW_CRB_HUB_AGT_ADR_MS, | |
280 | 0, | |
281 | QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, | |
282 | QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, | |
283 | QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, | |
284 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, | |
285 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, | |
286 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, | |
287 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, | |
288 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
289 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
290 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
291 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, | |
292 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
293 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, | |
294 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, | |
295 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, | |
296 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, | |
297 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, | |
298 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, | |
299 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, | |
300 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, | |
301 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, | |
302 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, | |
303 | 0, | |
304 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, | |
305 | QLA82XX_HW_CRB_HUB_AGT_ADR_SN, | |
306 | 0, | |
307 | QLA82XX_HW_CRB_HUB_AGT_ADR_EG, | |
308 | 0, | |
309 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
310 | QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, | |
311 | 0, | |
312 | 0, | |
313 | 0, | |
314 | 0, | |
315 | 0, | |
316 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
317 | 0, | |
318 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, | |
319 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, | |
320 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, | |
321 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, | |
322 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, | |
323 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, | |
324 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, | |
325 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
326 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
327 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
328 | 0, | |
329 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, | |
330 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, | |
331 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, | |
332 | QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, | |
333 | 0, | |
334 | QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, | |
335 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, | |
336 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, | |
337 | 0, | |
338 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, | |
339 | 0, | |
340 | }; | |
341 | ||
342 | /* Device states */ | |
343 | static char *qdev_state[] = { | |
344 | "Unknown", | |
345 | "Cold", | |
346 | "Initializing", | |
347 | "Ready", | |
348 | "Need Reset", | |
349 | "Need Quiescent", | |
350 | "Failed", | |
351 | "Quiescent", | |
352 | }; | |
353 | ||
354 | /* | |
355 | * In: 'off' is offset from CRB space in 128M pci map | |
356 | * Out: 'off' is 2M pci map addr | |
357 | * side effect: lock crb window | |
358 | */ | |
359 | static void | |
f8086f4f | 360 | qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) |
f4f5df23 VC |
361 | { |
362 | u32 win_read; | |
363 | ||
364 | ha->crb_win = CRB_HI(*off); | |
365 | writel(ha->crb_win, | |
366 | (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
367 | ||
368 | /* Read back value to make sure write has gone through before trying | |
369 | * to use it. */ | |
370 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
371 | if (win_read != ha->crb_win) { | |
372 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
373 | "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," | |
374 | " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); | |
375 | } | |
376 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; | |
377 | } | |
378 | ||
379 | void | |
f8086f4f | 380 | qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) |
f4f5df23 VC |
381 | { |
382 | unsigned long flags = 0; | |
383 | int rv; | |
384 | ||
f8086f4f | 385 | rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); |
f4f5df23 VC |
386 | |
387 | BUG_ON(rv == -1); | |
388 | ||
389 | if (rv == 1) { | |
390 | write_lock_irqsave(&ha->hw_lock, flags); | |
f8086f4f VC |
391 | qla4_82xx_crb_win_lock(ha); |
392 | qla4_82xx_pci_set_crbwindow_2M(ha, &off); | |
f4f5df23 VC |
393 | } |
394 | ||
395 | writel(data, (void __iomem *)off); | |
396 | ||
397 | if (rv == 1) { | |
f8086f4f | 398 | qla4_82xx_crb_win_unlock(ha); |
f4f5df23 VC |
399 | write_unlock_irqrestore(&ha->hw_lock, flags); |
400 | } | |
401 | } | |
402 | ||
33693c7a | 403 | uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) |
f4f5df23 VC |
404 | { |
405 | unsigned long flags = 0; | |
406 | int rv; | |
407 | u32 data; | |
408 | ||
f8086f4f | 409 | rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); |
f4f5df23 VC |
410 | |
411 | BUG_ON(rv == -1); | |
412 | ||
413 | if (rv == 1) { | |
414 | write_lock_irqsave(&ha->hw_lock, flags); | |
f8086f4f VC |
415 | qla4_82xx_crb_win_lock(ha); |
416 | qla4_82xx_pci_set_crbwindow_2M(ha, &off); | |
f4f5df23 VC |
417 | } |
418 | data = readl((void __iomem *)off); | |
419 | ||
420 | if (rv == 1) { | |
f8086f4f | 421 | qla4_82xx_crb_win_unlock(ha); |
f4f5df23 VC |
422 | write_unlock_irqrestore(&ha->hw_lock, flags); |
423 | } | |
424 | return data; | |
425 | } | |
426 | ||
068237c8 | 427 | /* Minidump related functions */ |
33693c7a | 428 | int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) |
068237c8 | 429 | { |
33693c7a VC |
430 | uint32_t win_read, off_value; |
431 | int rval = QLA_SUCCESS; | |
068237c8 TP |
432 | |
433 | off_value = off & 0xFFFF0000; | |
434 | writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
435 | ||
33693c7a VC |
436 | /* |
437 | * Read back value to make sure write has gone through before trying | |
068237c8 TP |
438 | * to use it. |
439 | */ | |
440 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
441 | if (win_read != off_value) { | |
442 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
443 | "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", | |
33693c7a VC |
444 | __func__, off_value, win_read, off)); |
445 | rval = QLA_ERROR; | |
446 | } else { | |
447 | off_value = off & 0x0000FFFF; | |
448 | *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + | |
449 | ha->nx_pcibase)); | |
068237c8 | 450 | } |
33693c7a VC |
451 | return rval; |
452 | } | |
068237c8 | 453 | |
33693c7a VC |
454 | int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) |
455 | { | |
456 | uint32_t win_read, off_value; | |
457 | int rval = QLA_SUCCESS; | |
068237c8 | 458 | |
33693c7a VC |
459 | off_value = off & 0xFFFF0000; |
460 | writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
068237c8 | 461 | |
33693c7a VC |
462 | /* Read back value to make sure write has gone through before trying |
463 | * to use it. | |
464 | */ | |
465 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
466 | if (win_read != off_value) { | |
467 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
468 | "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", | |
469 | __func__, off_value, win_read, off)); | |
470 | rval = QLA_ERROR; | |
471 | } else { | |
472 | off_value = off & 0x0000FFFF; | |
068237c8 TP |
473 | writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + |
474 | ha->nx_pcibase)); | |
33693c7a | 475 | } |
068237c8 TP |
476 | return rval; |
477 | } | |
478 | ||
f4f5df23 VC |
479 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
480 | ||
f8086f4f | 481 | int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) |
f4f5df23 VC |
482 | { |
483 | int i; | |
484 | int done = 0, timeout = 0; | |
485 | ||
486 | while (!done) { | |
487 | /* acquire semaphore3 from PCI HW block */ | |
f8086f4f | 488 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); |
f4f5df23 VC |
489 | if (done == 1) |
490 | break; | |
491 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) | |
492 | return -1; | |
493 | ||
494 | timeout++; | |
495 | ||
496 | /* Yield CPU */ | |
497 | if (!in_interrupt()) | |
498 | schedule(); | |
499 | else { | |
500 | for (i = 0; i < 20; i++) | |
501 | cpu_relax(); /*This a nop instr on i386*/ | |
502 | } | |
503 | } | |
f8086f4f | 504 | qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); |
f4f5df23 VC |
505 | return 0; |
506 | } | |
507 | ||
f8086f4f | 508 | void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) |
f4f5df23 | 509 | { |
f8086f4f | 510 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); |
f4f5df23 VC |
511 | } |
512 | ||
513 | #define IDC_LOCK_TIMEOUT 100000000 | |
514 | ||
515 | /** | |
f8086f4f | 516 | * qla4_82xx_idc_lock - hw_lock |
f4f5df23 VC |
517 | * @ha: pointer to adapter structure |
518 | * | |
519 | * General purpose lock used to synchronize access to | |
520 | * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. | |
521 | **/ | |
f8086f4f | 522 | int qla4_82xx_idc_lock(struct scsi_qla_host *ha) |
f4f5df23 VC |
523 | { |
524 | int i; | |
525 | int done = 0, timeout = 0; | |
526 | ||
527 | while (!done) { | |
528 | /* acquire semaphore5 from PCI HW block */ | |
f8086f4f | 529 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); |
f4f5df23 VC |
530 | if (done == 1) |
531 | break; | |
532 | if (timeout >= IDC_LOCK_TIMEOUT) | |
533 | return -1; | |
534 | ||
535 | timeout++; | |
536 | ||
537 | /* Yield CPU */ | |
538 | if (!in_interrupt()) | |
539 | schedule(); | |
540 | else { | |
541 | for (i = 0; i < 20; i++) | |
542 | cpu_relax(); /*This a nop instr on i386*/ | |
543 | } | |
544 | } | |
545 | return 0; | |
546 | } | |
547 | ||
f8086f4f | 548 | void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) |
f4f5df23 | 549 | { |
f8086f4f | 550 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); |
f4f5df23 VC |
551 | } |
552 | ||
553 | int | |
f8086f4f | 554 | qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) |
f4f5df23 VC |
555 | { |
556 | struct crb_128M_2M_sub_block_map *m; | |
557 | ||
558 | if (*off >= QLA82XX_CRB_MAX) | |
559 | return -1; | |
560 | ||
561 | if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { | |
562 | *off = (*off - QLA82XX_PCI_CAMQM) + | |
563 | QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; | |
564 | return 0; | |
565 | } | |
566 | ||
567 | if (*off < QLA82XX_PCI_CRBSPACE) | |
568 | return -1; | |
569 | ||
570 | *off -= QLA82XX_PCI_CRBSPACE; | |
571 | /* | |
572 | * Try direct map | |
573 | */ | |
574 | ||
575 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; | |
576 | ||
577 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { | |
578 | *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; | |
579 | return 0; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Not in direct map, use crb window | |
584 | */ | |
585 | return 1; | |
586 | } | |
587 | ||
f4f5df23 VC |
588 | /* |
589 | * check memory access boundary. | |
590 | * used by test agent. support ddr access only for now | |
591 | */ | |
592 | static unsigned long | |
f8086f4f | 593 | qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, |
f4f5df23 VC |
594 | unsigned long long addr, int size) |
595 | { | |
de8c72da VC |
596 | if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
597 | QLA8XXX_ADDR_DDR_NET_MAX) || | |
598 | !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, | |
599 | QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || | |
f4f5df23 VC |
600 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
601 | return 0; | |
602 | } | |
603 | return 1; | |
604 | } | |
605 | ||
7664a1fd | 606 | static int qla4_82xx_pci_set_window_warning_count; |
f4f5df23 VC |
607 | |
608 | static unsigned long | |
f8086f4f | 609 | qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) |
f4f5df23 VC |
610 | { |
611 | int window; | |
612 | u32 win_read; | |
613 | ||
de8c72da VC |
614 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
615 | QLA8XXX_ADDR_DDR_NET_MAX)) { | |
f4f5df23 VC |
616 | /* DDR network side */ |
617 | window = MN_WIN(addr); | |
618 | ha->ddr_mn_window = window; | |
f8086f4f | 619 | qla4_82xx_wr_32(ha, ha->mn_win_crb | |
f4f5df23 | 620 | QLA82XX_PCI_CRBSPACE, window); |
f8086f4f | 621 | win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | |
f4f5df23 VC |
622 | QLA82XX_PCI_CRBSPACE); |
623 | if ((win_read << 17) != window) { | |
624 | ql4_printk(KERN_WARNING, ha, | |
625 | "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", | |
626 | __func__, window, win_read); | |
627 | } | |
628 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; | |
de8c72da VC |
629 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
630 | QLA8XXX_ADDR_OCM0_MAX)) { | |
f4f5df23 VC |
631 | unsigned int temp1; |
632 | /* if bits 19:18&17:11 are on */ | |
633 | if ((addr & 0x00ff800) == 0xff800) { | |
634 | printk("%s: QM access not handled.\n", __func__); | |
635 | addr = -1UL; | |
636 | } | |
637 | ||
638 | window = OCM_WIN(addr); | |
639 | ha->ddr_mn_window = window; | |
f8086f4f | 640 | qla4_82xx_wr_32(ha, ha->mn_win_crb | |
f4f5df23 | 641 | QLA82XX_PCI_CRBSPACE, window); |
f8086f4f | 642 | win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | |
f4f5df23 VC |
643 | QLA82XX_PCI_CRBSPACE); |
644 | temp1 = ((window & 0x1FF) << 7) | | |
645 | ((window & 0x0FFFE0000) >> 17); | |
646 | if (win_read != temp1) { | |
647 | printk("%s: Written OCMwin (0x%x) != Read" | |
648 | " OCMwin (0x%x)\n", __func__, temp1, win_read); | |
649 | } | |
650 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; | |
651 | ||
de8c72da | 652 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
f4f5df23 VC |
653 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { |
654 | /* QDR network side */ | |
655 | window = MS_WIN(addr); | |
656 | ha->qdr_sn_window = window; | |
f8086f4f | 657 | qla4_82xx_wr_32(ha, ha->ms_win_crb | |
f4f5df23 | 658 | QLA82XX_PCI_CRBSPACE, window); |
f8086f4f | 659 | win_read = qla4_82xx_rd_32(ha, |
f4f5df23 VC |
660 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); |
661 | if (win_read != window) { | |
662 | printk("%s: Written MSwin (0x%x) != Read " | |
663 | "MSwin (0x%x)\n", __func__, window, win_read); | |
664 | } | |
665 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; | |
666 | ||
667 | } else { | |
668 | /* | |
669 | * peg gdb frequently accesses memory that doesn't exist, | |
670 | * this limits the chit chat so debugging isn't slowed down. | |
671 | */ | |
7664a1fd VC |
672 | if ((qla4_82xx_pci_set_window_warning_count++ < 8) || |
673 | (qla4_82xx_pci_set_window_warning_count%64 == 0)) { | |
f4f5df23 VC |
674 | printk("%s: Warning:%s Unknown address range!\n", |
675 | __func__, DRIVER_NAME); | |
676 | } | |
677 | addr = -1UL; | |
678 | } | |
679 | return addr; | |
680 | } | |
681 | ||
682 | /* check if address is in the same windows as the previous access */ | |
f8086f4f | 683 | static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, |
f4f5df23 VC |
684 | unsigned long long addr) |
685 | { | |
686 | int window; | |
687 | unsigned long long qdr_max; | |
688 | ||
689 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; | |
690 | ||
de8c72da VC |
691 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
692 | QLA8XXX_ADDR_DDR_NET_MAX)) { | |
f4f5df23 VC |
693 | /* DDR network side */ |
694 | BUG(); /* MN access can not come here */ | |
de8c72da VC |
695 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
696 | QLA8XXX_ADDR_OCM0_MAX)) { | |
f4f5df23 | 697 | return 1; |
de8c72da VC |
698 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, |
699 | QLA8XXX_ADDR_OCM1_MAX)) { | |
f4f5df23 | 700 | return 1; |
de8c72da | 701 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
f4f5df23 VC |
702 | qdr_max)) { |
703 | /* QDR network side */ | |
de8c72da | 704 | window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; |
f4f5df23 VC |
705 | if (ha->qdr_sn_window == window) |
706 | return 1; | |
707 | } | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
f8086f4f | 712 | static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, |
f4f5df23 VC |
713 | u64 off, void *data, int size) |
714 | { | |
715 | unsigned long flags; | |
716 | void __iomem *addr; | |
717 | int ret = 0; | |
718 | u64 start; | |
719 | void __iomem *mem_ptr = NULL; | |
720 | unsigned long mem_base; | |
721 | unsigned long mem_page; | |
722 | ||
723 | write_lock_irqsave(&ha->hw_lock, flags); | |
724 | ||
725 | /* | |
726 | * If attempting to access unknown address or straddle hw windows, | |
727 | * do not access. | |
728 | */ | |
f8086f4f | 729 | start = qla4_82xx_pci_set_window(ha, off); |
f4f5df23 | 730 | if ((start == -1UL) || |
f8086f4f | 731 | (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { |
f4f5df23 VC |
732 | write_unlock_irqrestore(&ha->hw_lock, flags); |
733 | printk(KERN_ERR"%s out of bound pci memory access. " | |
734 | "offset is 0x%llx\n", DRIVER_NAME, off); | |
735 | return -1; | |
736 | } | |
737 | ||
738 | addr = qla4_8xxx_pci_base_offsetfset(ha, start); | |
739 | if (!addr) { | |
740 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
741 | mem_base = pci_resource_start(ha->pdev, 0); | |
742 | mem_page = start & PAGE_MASK; | |
743 | /* Map two pages whenever user tries to access addresses in two | |
744 | consecutive pages. | |
745 | */ | |
746 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
747 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); | |
748 | else | |
749 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
750 | ||
751 | if (mem_ptr == NULL) { | |
752 | *(u8 *)data = 0; | |
753 | return -1; | |
754 | } | |
755 | addr = mem_ptr; | |
756 | addr += start & (PAGE_SIZE - 1); | |
757 | write_lock_irqsave(&ha->hw_lock, flags); | |
758 | } | |
759 | ||
760 | switch (size) { | |
761 | case 1: | |
762 | *(u8 *)data = readb(addr); | |
763 | break; | |
764 | case 2: | |
765 | *(u16 *)data = readw(addr); | |
766 | break; | |
767 | case 4: | |
768 | *(u32 *)data = readl(addr); | |
769 | break; | |
770 | case 8: | |
771 | *(u64 *)data = readq(addr); | |
772 | break; | |
773 | default: | |
774 | ret = -1; | |
775 | break; | |
776 | } | |
777 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
778 | ||
779 | if (mem_ptr) | |
780 | iounmap(mem_ptr); | |
781 | return ret; | |
782 | } | |
783 | ||
784 | static int | |
f8086f4f | 785 | qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, |
f4f5df23 VC |
786 | void *data, int size) |
787 | { | |
788 | unsigned long flags; | |
789 | void __iomem *addr; | |
790 | int ret = 0; | |
791 | u64 start; | |
792 | void __iomem *mem_ptr = NULL; | |
793 | unsigned long mem_base; | |
794 | unsigned long mem_page; | |
795 | ||
796 | write_lock_irqsave(&ha->hw_lock, flags); | |
797 | ||
798 | /* | |
799 | * If attempting to access unknown address or straddle hw windows, | |
800 | * do not access. | |
801 | */ | |
f8086f4f | 802 | start = qla4_82xx_pci_set_window(ha, off); |
f4f5df23 | 803 | if ((start == -1UL) || |
f8086f4f | 804 | (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { |
f4f5df23 VC |
805 | write_unlock_irqrestore(&ha->hw_lock, flags); |
806 | printk(KERN_ERR"%s out of bound pci memory access. " | |
807 | "offset is 0x%llx\n", DRIVER_NAME, off); | |
808 | return -1; | |
809 | } | |
810 | ||
811 | addr = qla4_8xxx_pci_base_offsetfset(ha, start); | |
812 | if (!addr) { | |
813 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
814 | mem_base = pci_resource_start(ha->pdev, 0); | |
815 | mem_page = start & PAGE_MASK; | |
816 | /* Map two pages whenever user tries to access addresses in two | |
817 | consecutive pages. | |
818 | */ | |
819 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
820 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); | |
821 | else | |
822 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
823 | if (mem_ptr == NULL) | |
824 | return -1; | |
825 | ||
826 | addr = mem_ptr; | |
827 | addr += start & (PAGE_SIZE - 1); | |
828 | write_lock_irqsave(&ha->hw_lock, flags); | |
829 | } | |
830 | ||
831 | switch (size) { | |
832 | case 1: | |
833 | writeb(*(u8 *)data, addr); | |
834 | break; | |
835 | case 2: | |
836 | writew(*(u16 *)data, addr); | |
837 | break; | |
838 | case 4: | |
839 | writel(*(u32 *)data, addr); | |
840 | break; | |
841 | case 8: | |
842 | writeq(*(u64 *)data, addr); | |
843 | break; | |
844 | default: | |
845 | ret = -1; | |
846 | break; | |
847 | } | |
848 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
849 | if (mem_ptr) | |
850 | iounmap(mem_ptr); | |
851 | return ret; | |
852 | } | |
853 | ||
854 | #define MTU_FUDGE_FACTOR 100 | |
855 | ||
856 | static unsigned long | |
f8086f4f | 857 | qla4_82xx_decode_crb_addr(unsigned long addr) |
f4f5df23 VC |
858 | { |
859 | int i; | |
860 | unsigned long base_addr, offset, pci_base; | |
861 | ||
862 | if (!qla4_8xxx_crb_table_initialized) | |
f8086f4f | 863 | qla4_82xx_crb_addr_transform_setup(); |
f4f5df23 VC |
864 | |
865 | pci_base = ADDR_ERROR; | |
866 | base_addr = addr & 0xfff00000; | |
867 | offset = addr & 0x000fffff; | |
868 | ||
869 | for (i = 0; i < MAX_CRB_XFORM; i++) { | |
870 | if (crb_addr_xform[i] == base_addr) { | |
871 | pci_base = i << 20; | |
872 | break; | |
873 | } | |
874 | } | |
875 | if (pci_base == ADDR_ERROR) | |
876 | return pci_base; | |
877 | else | |
878 | return pci_base + offset; | |
879 | } | |
880 | ||
881 | static long rom_max_timeout = 100; | |
7664a1fd | 882 | static long qla4_82xx_rom_lock_timeout = 100; |
f4f5df23 VC |
883 | |
884 | static int | |
f8086f4f | 885 | qla4_82xx_rom_lock(struct scsi_qla_host *ha) |
f4f5df23 VC |
886 | { |
887 | int i; | |
888 | int done = 0, timeout = 0; | |
889 | ||
890 | while (!done) { | |
891 | /* acquire semaphore2 from PCI HW block */ | |
892 | ||
f8086f4f | 893 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); |
f4f5df23 VC |
894 | if (done == 1) |
895 | break; | |
7664a1fd | 896 | if (timeout >= qla4_82xx_rom_lock_timeout) |
f4f5df23 VC |
897 | return -1; |
898 | ||
899 | timeout++; | |
900 | ||
901 | /* Yield CPU */ | |
902 | if (!in_interrupt()) | |
903 | schedule(); | |
904 | else { | |
905 | for (i = 0; i < 20; i++) | |
906 | cpu_relax(); /*This a nop instr on i386*/ | |
907 | } | |
908 | } | |
f8086f4f | 909 | qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); |
f4f5df23 VC |
910 | return 0; |
911 | } | |
912 | ||
913 | static void | |
f8086f4f | 914 | qla4_82xx_rom_unlock(struct scsi_qla_host *ha) |
f4f5df23 | 915 | { |
f8086f4f | 916 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); |
f4f5df23 VC |
917 | } |
918 | ||
919 | static int | |
f8086f4f | 920 | qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) |
f4f5df23 VC |
921 | { |
922 | long timeout = 0; | |
923 | long done = 0 ; | |
924 | ||
925 | while (done == 0) { | |
f8086f4f | 926 | done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); |
f4f5df23 VC |
927 | done &= 2; |
928 | timeout++; | |
929 | if (timeout >= rom_max_timeout) { | |
930 | printk("%s: Timeout reached waiting for rom done", | |
931 | DRIVER_NAME); | |
932 | return -1; | |
933 | } | |
934 | } | |
935 | return 0; | |
936 | } | |
937 | ||
938 | static int | |
f8086f4f | 939 | qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) |
f4f5df23 | 940 | { |
f8086f4f VC |
941 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); |
942 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
943 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
944 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
945 | if (qla4_82xx_wait_rom_done(ha)) { | |
f4f5df23 VC |
946 | printk("%s: Error waiting for rom done\n", DRIVER_NAME); |
947 | return -1; | |
948 | } | |
949 | /* reset abyte_cnt and dummy_byte_cnt */ | |
f8086f4f | 950 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
f4f5df23 | 951 | udelay(10); |
f8086f4f | 952 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); |
f4f5df23 | 953 | |
f8086f4f | 954 | *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); |
f4f5df23 VC |
955 | return 0; |
956 | } | |
957 | ||
958 | static int | |
f8086f4f | 959 | qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) |
f4f5df23 VC |
960 | { |
961 | int ret, loops = 0; | |
962 | ||
f8086f4f | 963 | while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { |
f4f5df23 VC |
964 | udelay(100); |
965 | loops++; | |
966 | } | |
967 | if (loops >= 50000) { | |
f8086f4f VC |
968 | ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", |
969 | DRIVER_NAME); | |
f4f5df23 VC |
970 | return -1; |
971 | } | |
f8086f4f VC |
972 | ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); |
973 | qla4_82xx_rom_unlock(ha); | |
f4f5df23 VC |
974 | return ret; |
975 | } | |
976 | ||
977 | /** | |
978 | * This routine does CRB initialize sequence | |
979 | * to put the ISP into operational state | |
980 | **/ | |
981 | static int | |
f8086f4f | 982 | qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) |
f4f5df23 VC |
983 | { |
984 | int addr, val; | |
985 | int i ; | |
986 | struct crb_addr_pair *buf; | |
987 | unsigned long off; | |
988 | unsigned offset, n; | |
989 | ||
990 | struct crb_addr_pair { | |
991 | long addr; | |
992 | long data; | |
993 | }; | |
994 | ||
995 | /* Halt all the indiviual PEGs and other blocks of the ISP */ | |
f8086f4f | 996 | qla4_82xx_rom_lock(ha); |
a1fc26ba | 997 | |
cb74428e | 998 | /* disable all I2Q */ |
f8086f4f VC |
999 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); |
1000 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); | |
1001 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); | |
1002 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); | |
1003 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); | |
1004 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); | |
cb74428e VC |
1005 | |
1006 | /* disable all niu interrupts */ | |
f8086f4f | 1007 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); |
a1fc26ba | 1008 | /* disable xge rx/tx */ |
f8086f4f | 1009 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); |
a1fc26ba | 1010 | /* disable xg1 rx/tx */ |
f8086f4f | 1011 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); |
cb74428e | 1012 | /* disable sideband mac */ |
f8086f4f | 1013 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); |
cb74428e | 1014 | /* disable ap0 mac */ |
f8086f4f | 1015 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); |
cb74428e | 1016 | /* disable ap1 mac */ |
f8086f4f | 1017 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); |
a1fc26ba SN |
1018 | |
1019 | /* halt sre */ | |
f8086f4f VC |
1020 | val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); |
1021 | qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); | |
a1fc26ba SN |
1022 | |
1023 | /* halt epg */ | |
f8086f4f | 1024 | qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); |
a1fc26ba SN |
1025 | |
1026 | /* halt timers */ | |
f8086f4f VC |
1027 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); |
1028 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); | |
1029 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); | |
1030 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); | |
1031 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); | |
1032 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); | |
a1fc26ba SN |
1033 | |
1034 | /* halt pegs */ | |
f8086f4f VC |
1035 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); |
1036 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); | |
1037 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); | |
1038 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); | |
1039 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); | |
cb74428e | 1040 | msleep(5); |
a1fc26ba SN |
1041 | |
1042 | /* big hammer */ | |
f4f5df23 VC |
1043 | if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) |
1044 | /* don't reset CAM block on reset */ | |
f8086f4f | 1045 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); |
f4f5df23 | 1046 | else |
f8086f4f | 1047 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); |
f4f5df23 | 1048 | |
f8086f4f | 1049 | qla4_82xx_rom_unlock(ha); |
f4f5df23 VC |
1050 | |
1051 | /* Read the signature value from the flash. | |
1052 | * Offset 0: Contain signature (0xcafecafe) | |
1053 | * Offset 4: Offset and number of addr/value pairs | |
1054 | * that present in CRB initialize sequence | |
1055 | */ | |
f8086f4f VC |
1056 | if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || |
1057 | qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { | |
f4f5df23 VC |
1058 | ql4_printk(KERN_WARNING, ha, |
1059 | "[ERROR] Reading crb_init area: n: %08x\n", n); | |
1060 | return -1; | |
1061 | } | |
1062 | ||
1063 | /* Offset in flash = lower 16 bits | |
1064 | * Number of enteries = upper 16 bits | |
1065 | */ | |
1066 | offset = n & 0xffffU; | |
1067 | n = (n >> 16) & 0xffffU; | |
1068 | ||
1069 | /* number of addr/value pair should not exceed 1024 enteries */ | |
1070 | if (n >= 1024) { | |
1071 | ql4_printk(KERN_WARNING, ha, | |
1072 | "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", | |
1073 | DRIVER_NAME, __func__, n); | |
1074 | return -1; | |
1075 | } | |
1076 | ||
1077 | ql4_printk(KERN_INFO, ha, | |
1078 | "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); | |
1079 | ||
6da2ec56 | 1080 | buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
f4f5df23 VC |
1081 | if (buf == NULL) { |
1082 | ql4_printk(KERN_WARNING, ha, | |
1083 | "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); | |
1084 | return -1; | |
1085 | } | |
1086 | ||
1087 | for (i = 0; i < n; i++) { | |
f8086f4f VC |
1088 | if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || |
1089 | qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != | |
f4f5df23 VC |
1090 | 0) { |
1091 | kfree(buf); | |
1092 | return -1; | |
1093 | } | |
1094 | ||
1095 | buf[i].addr = addr; | |
1096 | buf[i].data = val; | |
1097 | } | |
1098 | ||
1099 | for (i = 0; i < n; i++) { | |
1100 | /* Translate internal CRB initialization | |
1101 | * address to PCI bus address | |
1102 | */ | |
f8086f4f | 1103 | off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + |
f4f5df23 VC |
1104 | QLA82XX_PCI_CRBSPACE; |
1105 | /* Not all CRB addr/value pair to be written, | |
1106 | * some of them are skipped | |
1107 | */ | |
1108 | ||
1109 | /* skip if LS bit is set*/ | |
1110 | if (off & 0x1) { | |
1111 | DEBUG2(ql4_printk(KERN_WARNING, ha, | |
1112 | "Skip CRB init replay for offset = 0x%lx\n", off)); | |
1113 | continue; | |
1114 | } | |
1115 | ||
1116 | /* skipping cold reboot MAGIC */ | |
1117 | if (off == QLA82XX_CAM_RAM(0x1fc)) | |
1118 | continue; | |
1119 | ||
1120 | /* do not reset PCI */ | |
1121 | if (off == (ROMUSB_GLB + 0xbc)) | |
1122 | continue; | |
1123 | ||
1124 | /* skip core clock, so that firmware can increase the clock */ | |
1125 | if (off == (ROMUSB_GLB + 0xc8)) | |
1126 | continue; | |
1127 | ||
1128 | /* skip the function enable register */ | |
1129 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
1130 | continue; | |
1131 | ||
1132 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) | |
1133 | continue; | |
1134 | ||
1135 | if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) | |
1136 | continue; | |
1137 | ||
1138 | if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) | |
1139 | continue; | |
1140 | ||
1141 | if (off == ADDR_ERROR) { | |
1142 | ql4_printk(KERN_WARNING, ha, | |
1143 | "%s: [ERROR] Unknown addr: 0x%08lx\n", | |
1144 | DRIVER_NAME, buf[i].addr); | |
1145 | continue; | |
1146 | } | |
1147 | ||
f8086f4f | 1148 | qla4_82xx_wr_32(ha, off, buf[i].data); |
f4f5df23 VC |
1149 | |
1150 | /* ISP requires much bigger delay to settle down, | |
1151 | * else crb_window returns 0xffffffff | |
1152 | */ | |
1153 | if (off == QLA82XX_ROMUSB_GLB_SW_RESET) | |
1154 | msleep(1000); | |
1155 | ||
1156 | /* ISP requires millisec delay between | |
1157 | * successive CRB register updation | |
1158 | */ | |
1159 | msleep(1); | |
1160 | } | |
1161 | ||
1162 | kfree(buf); | |
1163 | ||
1164 | /* Resetting the data and instruction cache */ | |
f8086f4f VC |
1165 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); |
1166 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); | |
1167 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); | |
f4f5df23 VC |
1168 | |
1169 | /* Clear all protocol processing engines */ | |
f8086f4f VC |
1170 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); |
1171 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); | |
1172 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); | |
1173 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); | |
1174 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); | |
1175 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); | |
1176 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); | |
1177 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); | |
f4f5df23 VC |
1178 | |
1179 | return 0; | |
1180 | } | |
1181 | ||
dd3b854e VC |
1182 | /** |
1183 | * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory | |
1184 | * @ha: Pointer to adapter structure | |
1185 | * @addr: Flash address to write to | |
1186 | * @data: Data to be written | |
1187 | * @count: word_count to be written | |
1188 | * | |
1189 | * Return: On success return QLA_SUCCESS | |
1190 | * On error return QLA_ERROR | |
1191 | **/ | |
1192 | int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, | |
1193 | uint32_t *data, uint32_t count) | |
1194 | { | |
1195 | int i, j; | |
1196 | uint32_t agt_ctrl; | |
1197 | unsigned long flags; | |
1198 | int ret_val = QLA_SUCCESS; | |
1199 | ||
1200 | /* Only 128-bit aligned access */ | |
1201 | if (addr & 0xF) { | |
1202 | ret_val = QLA_ERROR; | |
1203 | goto exit_ms_mem_write; | |
1204 | } | |
1205 | ||
1206 | write_lock_irqsave(&ha->hw_lock, flags); | |
1207 | ||
1208 | /* Write address */ | |
1209 | ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); | |
1210 | if (ret_val == QLA_ERROR) { | |
1211 | ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", | |
1212 | __func__); | |
1213 | goto exit_ms_mem_write_unlock; | |
1214 | } | |
1215 | ||
1216 | for (i = 0; i < count; i++, addr += 16) { | |
1217 | if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, | |
1218 | QLA8XXX_ADDR_QDR_NET_MAX)) || | |
1219 | (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, | |
1220 | QLA8XXX_ADDR_DDR_NET_MAX)))) { | |
1221 | ret_val = QLA_ERROR; | |
1222 | goto exit_ms_mem_write_unlock; | |
1223 | } | |
1224 | ||
1225 | ret_val = ha->isp_ops->wr_reg_indirect(ha, | |
1226 | MD_MIU_TEST_AGT_ADDR_LO, | |
1227 | addr); | |
1228 | /* Write data */ | |
1229 | ret_val |= ha->isp_ops->wr_reg_indirect(ha, | |
1230 | MD_MIU_TEST_AGT_WRDATA_LO, | |
1231 | *data++); | |
1232 | ret_val |= ha->isp_ops->wr_reg_indirect(ha, | |
1233 | MD_MIU_TEST_AGT_WRDATA_HI, | |
1234 | *data++); | |
1235 | ret_val |= ha->isp_ops->wr_reg_indirect(ha, | |
1236 | MD_MIU_TEST_AGT_WRDATA_ULO, | |
1237 | *data++); | |
1238 | ret_val |= ha->isp_ops->wr_reg_indirect(ha, | |
1239 | MD_MIU_TEST_AGT_WRDATA_UHI, | |
1240 | *data++); | |
1241 | if (ret_val == QLA_ERROR) { | |
1242 | ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n", | |
1243 | __func__); | |
1244 | goto exit_ms_mem_write_unlock; | |
1245 | } | |
1246 | ||
1247 | /* Check write status */ | |
1248 | ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, | |
1249 | MIU_TA_CTL_WRITE_ENABLE); | |
1250 | ret_val |= ha->isp_ops->wr_reg_indirect(ha, | |
1251 | MD_MIU_TEST_AGT_CTRL, | |
1252 | MIU_TA_CTL_WRITE_START); | |
1253 | if (ret_val == QLA_ERROR) { | |
1254 | ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", | |
1255 | __func__); | |
1256 | goto exit_ms_mem_write_unlock; | |
1257 | } | |
1258 | ||
1259 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1260 | ret_val = ha->isp_ops->rd_reg_indirect(ha, | |
1261 | MD_MIU_TEST_AGT_CTRL, | |
1262 | &agt_ctrl); | |
1263 | if (ret_val == QLA_ERROR) { | |
1264 | ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", | |
1265 | __func__); | |
1266 | goto exit_ms_mem_write_unlock; | |
1267 | } | |
1268 | if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) | |
1269 | break; | |
1270 | } | |
1271 | ||
1272 | /* Status check failed */ | |
1273 | if (j >= MAX_CTL_CHECK) { | |
1274 | printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n", | |
1275 | __func__); | |
1276 | ret_val = QLA_ERROR; | |
1277 | goto exit_ms_mem_write_unlock; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | exit_ms_mem_write_unlock: | |
1282 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
1283 | ||
1284 | exit_ms_mem_write: | |
1285 | return ret_val; | |
1286 | } | |
1287 | ||
f4f5df23 | 1288 | static int |
f8086f4f | 1289 | qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) |
f4f5df23 | 1290 | { |
4cd83cbe | 1291 | int i, rval = 0; |
f4f5df23 VC |
1292 | long size = 0; |
1293 | long flashaddr, memaddr; | |
1294 | u64 data; | |
1295 | u32 high, low; | |
1296 | ||
1297 | flashaddr = memaddr = ha->hw.flt_region_bootload; | |
4cd83cbe | 1298 | size = (image_start - flashaddr) / 8; |
f4f5df23 VC |
1299 | |
1300 | DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", | |
1301 | ha->host_no, __func__, flashaddr, image_start)); | |
1302 | ||
1303 | for (i = 0; i < size; i++) { | |
f8086f4f VC |
1304 | if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || |
1305 | (qla4_82xx_rom_fast_read(ha, flashaddr + 4, | |
f4f5df23 | 1306 | (int *)&high))) { |
4cd83cbe LC |
1307 | rval = -1; |
1308 | goto exit_load_from_flash; | |
f4f5df23 VC |
1309 | } |
1310 | data = ((u64)high << 32) | low ; | |
f8086f4f | 1311 | rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); |
4cd83cbe LC |
1312 | if (rval) |
1313 | goto exit_load_from_flash; | |
1314 | ||
f4f5df23 VC |
1315 | flashaddr += 8; |
1316 | memaddr += 8; | |
1317 | ||
4cd83cbe | 1318 | if (i % 0x1000 == 0) |
f4f5df23 VC |
1319 | msleep(1); |
1320 | ||
1321 | } | |
1322 | ||
1323 | udelay(100); | |
1324 | ||
1325 | read_lock(&ha->hw_lock); | |
f8086f4f VC |
1326 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); |
1327 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | |
f4f5df23 VC |
1328 | read_unlock(&ha->hw_lock); |
1329 | ||
4cd83cbe LC |
1330 | exit_load_from_flash: |
1331 | return rval; | |
f4f5df23 VC |
1332 | } |
1333 | ||
f8086f4f | 1334 | static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) |
f4f5df23 VC |
1335 | { |
1336 | u32 rst; | |
1337 | ||
f8086f4f VC |
1338 | qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); |
1339 | if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { | |
f4f5df23 VC |
1340 | printk(KERN_WARNING "%s: Error during CRB Initialization\n", |
1341 | __func__); | |
1342 | return QLA_ERROR; | |
1343 | } | |
1344 | ||
1345 | udelay(500); | |
1346 | ||
1347 | /* at this point, QM is in reset. This could be a problem if there are | |
1348 | * incoming d* transition queue messages. QM/PCIE could wedge. | |
1349 | * To get around this, QM is brought out of reset. | |
1350 | */ | |
1351 | ||
f8086f4f | 1352 | rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); |
f4f5df23 VC |
1353 | /* unreset qm */ |
1354 | rst &= ~(1 << 28); | |
f8086f4f | 1355 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); |
f4f5df23 | 1356 | |
f8086f4f | 1357 | if (qla4_82xx_load_from_flash(ha, image_start)) { |
f4f5df23 VC |
1358 | printk("%s: Error trying to load fw from flash!\n", __func__); |
1359 | return QLA_ERROR; | |
1360 | } | |
1361 | ||
1362 | return QLA_SUCCESS; | |
1363 | } | |
1364 | ||
1365 | int | |
f8086f4f | 1366 | qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, |
f4f5df23 VC |
1367 | u64 off, void *data, int size) |
1368 | { | |
1369 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | |
1370 | int shift_amount; | |
1371 | uint32_t temp; | |
1372 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; | |
1373 | ||
1374 | /* | |
1375 | * If not MN, go check for MS or invalid. | |
1376 | */ | |
1377 | ||
de8c72da | 1378 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
f4f5df23 VC |
1379 | mem_crb = QLA82XX_CRB_QDR_NET; |
1380 | else { | |
1381 | mem_crb = QLA82XX_CRB_DDR_NET; | |
f8086f4f VC |
1382 | if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) |
1383 | return qla4_82xx_pci_mem_read_direct(ha, | |
f4f5df23 VC |
1384 | off, data, size); |
1385 | } | |
1386 | ||
1387 | ||
1388 | off8 = off & 0xfffffff0; | |
1389 | off0[0] = off & 0xf; | |
1390 | sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); | |
1391 | shift_amount = 4; | |
1392 | ||
1393 | loop = ((off0[0] + size - 1) >> shift_amount) + 1; | |
1394 | off0[1] = 0; | |
1395 | sz[1] = size - sz[0]; | |
1396 | ||
1397 | for (i = 0; i < loop; i++) { | |
1398 | temp = off8 + (i << shift_amount); | |
f8086f4f | 1399 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); |
f4f5df23 | 1400 | temp = 0; |
f8086f4f | 1401 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); |
f4f5df23 | 1402 | temp = MIU_TA_CTL_ENABLE; |
f8086f4f | 1403 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); |
c38fa3ab | 1404 | temp = MIU_TA_CTL_START_ENABLE; |
f8086f4f | 1405 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); |
f4f5df23 VC |
1406 | |
1407 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
f8086f4f | 1408 | temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); |
f4f5df23 VC |
1409 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
1410 | break; | |
1411 | } | |
1412 | ||
1413 | if (j >= MAX_CTL_CHECK) { | |
068237c8 TP |
1414 | printk_ratelimited(KERN_ERR |
1415 | "%s: failed to read through agent\n", | |
1416 | __func__); | |
f4f5df23 VC |
1417 | break; |
1418 | } | |
1419 | ||
1420 | start = off0[i] >> 2; | |
1421 | end = (off0[i] + sz[i] - 1) >> 2; | |
1422 | for (k = start; k <= end; k++) { | |
f8086f4f | 1423 | temp = qla4_82xx_rd_32(ha, |
f4f5df23 VC |
1424 | mem_crb + MIU_TEST_AGT_RDDATA(k)); |
1425 | word[i] |= ((uint64_t)temp << (32 * (k & 1))); | |
1426 | } | |
1427 | } | |
1428 | ||
1429 | if (j >= MAX_CTL_CHECK) | |
1430 | return -1; | |
1431 | ||
1432 | if ((off0[0] & 7) == 0) { | |
1433 | val = word[0]; | |
1434 | } else { | |
1435 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | |
1436 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | |
1437 | } | |
1438 | ||
1439 | switch (size) { | |
1440 | case 1: | |
1441 | *(uint8_t *)data = val; | |
1442 | break; | |
1443 | case 2: | |
1444 | *(uint16_t *)data = val; | |
1445 | break; | |
1446 | case 4: | |
1447 | *(uint32_t *)data = val; | |
1448 | break; | |
1449 | case 8: | |
1450 | *(uint64_t *)data = val; | |
1451 | break; | |
1452 | } | |
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | int | |
f8086f4f | 1457 | qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, |
f4f5df23 VC |
1458 | u64 off, void *data, int size) |
1459 | { | |
1460 | int i, j, ret = 0, loop, sz[2], off0; | |
1461 | int scale, shift_amount, startword; | |
1462 | uint32_t temp; | |
1463 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; | |
1464 | ||
1465 | /* | |
1466 | * If not MN, go check for MS or invalid. | |
1467 | */ | |
de8c72da | 1468 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
f4f5df23 VC |
1469 | mem_crb = QLA82XX_CRB_QDR_NET; |
1470 | else { | |
1471 | mem_crb = QLA82XX_CRB_DDR_NET; | |
f8086f4f VC |
1472 | if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) |
1473 | return qla4_82xx_pci_mem_write_direct(ha, | |
f4f5df23 VC |
1474 | off, data, size); |
1475 | } | |
1476 | ||
1477 | off0 = off & 0x7; | |
1478 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | |
1479 | sz[1] = size - sz[0]; | |
1480 | ||
1481 | off8 = off & 0xfffffff0; | |
1482 | loop = (((off & 0xf) + size - 1) >> 4) + 1; | |
1483 | shift_amount = 4; | |
1484 | scale = 2; | |
1485 | startword = (off & 0xf)/8; | |
1486 | ||
1487 | for (i = 0; i < loop; i++) { | |
f8086f4f | 1488 | if (qla4_82xx_pci_mem_read_2M(ha, off8 + |
f4f5df23 VC |
1489 | (i << shift_amount), &word[i * scale], 8)) |
1490 | return -1; | |
1491 | } | |
1492 | ||
1493 | switch (size) { | |
1494 | case 1: | |
1495 | tmpw = *((uint8_t *)data); | |
1496 | break; | |
1497 | case 2: | |
1498 | tmpw = *((uint16_t *)data); | |
1499 | break; | |
1500 | case 4: | |
1501 | tmpw = *((uint32_t *)data); | |
1502 | break; | |
1503 | case 8: | |
1504 | default: | |
1505 | tmpw = *((uint64_t *)data); | |
1506 | break; | |
1507 | } | |
1508 | ||
1509 | if (sz[0] == 8) | |
1510 | word[startword] = tmpw; | |
1511 | else { | |
1512 | word[startword] &= | |
1513 | ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | |
1514 | word[startword] |= tmpw << (off0 * 8); | |
1515 | } | |
1516 | ||
1517 | if (sz[1] != 0) { | |
1518 | word[startword+1] &= ~(~0ULL << (sz[1] * 8)); | |
1519 | word[startword+1] |= tmpw >> (sz[0] * 8); | |
1520 | } | |
1521 | ||
1522 | for (i = 0; i < loop; i++) { | |
1523 | temp = off8 + (i << shift_amount); | |
f8086f4f | 1524 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); |
f4f5df23 | 1525 | temp = 0; |
f8086f4f | 1526 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); |
f4f5df23 | 1527 | temp = word[i * scale] & 0xffffffff; |
f8086f4f | 1528 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); |
f4f5df23 | 1529 | temp = (word[i * scale] >> 32) & 0xffffffff; |
f8086f4f | 1530 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); |
f4f5df23 | 1531 | temp = word[i*scale + 1] & 0xffffffff; |
f8086f4f | 1532 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, |
f4f5df23 VC |
1533 | temp); |
1534 | temp = (word[i*scale + 1] >> 32) & 0xffffffff; | |
f8086f4f | 1535 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, |
f4f5df23 VC |
1536 | temp); |
1537 | ||
c38fa3ab | 1538 | temp = MIU_TA_CTL_WRITE_ENABLE; |
f8086f4f | 1539 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); |
c38fa3ab | 1540 | temp = MIU_TA_CTL_WRITE_START; |
f8086f4f | 1541 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); |
f4f5df23 VC |
1542 | |
1543 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
f8086f4f | 1544 | temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); |
f4f5df23 VC |
1545 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
1546 | break; | |
1547 | } | |
1548 | ||
1549 | if (j >= MAX_CTL_CHECK) { | |
1550 | if (printk_ratelimit()) | |
1551 | ql4_printk(KERN_ERR, ha, | |
068237c8 TP |
1552 | "%s: failed to read through agent\n", |
1553 | __func__); | |
f4f5df23 VC |
1554 | ret = -1; |
1555 | break; | |
1556 | } | |
1557 | } | |
1558 | ||
1559 | return ret; | |
1560 | } | |
1561 | ||
f8086f4f | 1562 | static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) |
f4f5df23 VC |
1563 | { |
1564 | u32 val = 0; | |
1565 | int retries = 60; | |
1566 | ||
1567 | if (!pegtune_val) { | |
1568 | do { | |
f8086f4f | 1569 | val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); |
f4f5df23 VC |
1570 | if ((val == PHAN_INITIALIZE_COMPLETE) || |
1571 | (val == PHAN_INITIALIZE_ACK)) | |
1572 | return 0; | |
1573 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1574 | schedule_timeout(500); | |
1575 | ||
1576 | } while (--retries); | |
1577 | ||
f4f5df23 | 1578 | if (!retries) { |
f8086f4f | 1579 | pegtune_val = qla4_82xx_rd_32(ha, |
f4f5df23 VC |
1580 | QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); |
1581 | printk(KERN_WARNING "%s: init failed, " | |
1582 | "pegtune_val = %x\n", __func__, pegtune_val); | |
1583 | return -1; | |
1584 | } | |
1585 | } | |
1586 | return 0; | |
1587 | } | |
1588 | ||
f8086f4f | 1589 | static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) |
f4f5df23 VC |
1590 | { |
1591 | uint32_t state = 0; | |
1592 | int loops = 0; | |
1593 | ||
1594 | /* Window 1 call */ | |
1595 | read_lock(&ha->hw_lock); | |
f8086f4f | 1596 | state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); |
f4f5df23 VC |
1597 | read_unlock(&ha->hw_lock); |
1598 | ||
1599 | while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { | |
1600 | udelay(100); | |
1601 | /* Window 1 call */ | |
1602 | read_lock(&ha->hw_lock); | |
f8086f4f | 1603 | state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); |
f4f5df23 VC |
1604 | read_unlock(&ha->hw_lock); |
1605 | ||
1606 | loops++; | |
1607 | } | |
1608 | ||
1609 | if (loops >= 30000) { | |
1610 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
1611 | "Receive Peg initialization not complete: 0x%x.\n", state)); | |
1612 | return QLA_ERROR; | |
1613 | } | |
1614 | ||
1615 | return QLA_SUCCESS; | |
1616 | } | |
1617 | ||
626115cd | 1618 | void |
f4f5df23 VC |
1619 | qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) |
1620 | { | |
1621 | uint32_t drv_active; | |
1622 | ||
33693c7a | 1623 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
6e7b4292 VC |
1624 | |
1625 | /* | |
b37ca418 | 1626 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1627 | * shift 1 by func_num to set a bit for the function. |
1628 | * For ISP8022, drv_active has 4 bits per function | |
1629 | */ | |
b37ca418 | 1630 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1631 | drv_active |= (1 << ha->func_num); |
1632 | else | |
1633 | drv_active |= (1 << (ha->func_num * 4)); | |
1634 | ||
068237c8 TP |
1635 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", |
1636 | __func__, ha->host_no, drv_active); | |
33693c7a | 1637 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); |
f4f5df23 VC |
1638 | } |
1639 | ||
1640 | void | |
1641 | qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) | |
1642 | { | |
1643 | uint32_t drv_active; | |
1644 | ||
33693c7a | 1645 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
6e7b4292 VC |
1646 | |
1647 | /* | |
b37ca418 | 1648 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1649 | * shift 1 by func_num to set a bit for the function. |
1650 | * For ISP8022, drv_active has 4 bits per function | |
1651 | */ | |
b37ca418 | 1652 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1653 | drv_active &= ~(1 << (ha->func_num)); |
1654 | else | |
1655 | drv_active &= ~(1 << (ha->func_num * 4)); | |
1656 | ||
068237c8 TP |
1657 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", |
1658 | __func__, ha->host_no, drv_active); | |
33693c7a | 1659 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); |
f4f5df23 VC |
1660 | } |
1661 | ||
33693c7a | 1662 | inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) |
f4f5df23 | 1663 | { |
2232be0d | 1664 | uint32_t drv_state, drv_active; |
f4f5df23 VC |
1665 | int rval; |
1666 | ||
33693c7a VC |
1667 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
1668 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); | |
6e7b4292 VC |
1669 | |
1670 | /* | |
b37ca418 | 1671 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1672 | * shift 1 by func_num to set a bit for the function. |
1673 | * For ISP8022, drv_active has 4 bits per function | |
1674 | */ | |
b37ca418 | 1675 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1676 | rval = drv_state & (1 << ha->func_num); |
1677 | else | |
1678 | rval = drv_state & (1 << (ha->func_num * 4)); | |
1679 | ||
2232be0d LC |
1680 | if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) |
1681 | rval = 1; | |
1682 | ||
f4f5df23 VC |
1683 | return rval; |
1684 | } | |
1685 | ||
6e7b4292 | 1686 | void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) |
f4f5df23 VC |
1687 | { |
1688 | uint32_t drv_state; | |
1689 | ||
33693c7a | 1690 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
6e7b4292 VC |
1691 | |
1692 | /* | |
b37ca418 | 1693 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1694 | * shift 1 by func_num to set a bit for the function. |
1695 | * For ISP8022, drv_active has 4 bits per function | |
1696 | */ | |
b37ca418 | 1697 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1698 | drv_state |= (1 << ha->func_num); |
1699 | else | |
1700 | drv_state |= (1 << (ha->func_num * 4)); | |
1701 | ||
068237c8 TP |
1702 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", |
1703 | __func__, ha->host_no, drv_state); | |
33693c7a | 1704 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); |
f4f5df23 VC |
1705 | } |
1706 | ||
6e7b4292 | 1707 | void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) |
f4f5df23 VC |
1708 | { |
1709 | uint32_t drv_state; | |
1710 | ||
33693c7a | 1711 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
6e7b4292 VC |
1712 | |
1713 | /* | |
b37ca418 | 1714 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1715 | * shift 1 by func_num to set a bit for the function. |
1716 | * For ISP8022, drv_active has 4 bits per function | |
1717 | */ | |
b37ca418 | 1718 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1719 | drv_state &= ~(1 << ha->func_num); |
1720 | else | |
1721 | drv_state &= ~(1 << (ha->func_num * 4)); | |
1722 | ||
068237c8 TP |
1723 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", |
1724 | __func__, ha->host_no, drv_state); | |
33693c7a | 1725 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); |
f4f5df23 VC |
1726 | } |
1727 | ||
1728 | static inline void | |
1729 | qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) | |
1730 | { | |
1731 | uint32_t qsnt_state; | |
1732 | ||
33693c7a | 1733 | qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
6e7b4292 VC |
1734 | |
1735 | /* | |
b37ca418 | 1736 | * For ISP8324 and ISP8042, drv_active register has 1 bit per function, |
6e7b4292 VC |
1737 | * shift 1 by func_num to set a bit for the function. |
1738 | * For ISP8022, drv_active has 4 bits per function. | |
1739 | */ | |
b37ca418 | 1740 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
1741 | qsnt_state |= (1 << ha->func_num); |
1742 | else | |
1743 | qsnt_state |= (2 << (ha->func_num * 4)); | |
1744 | ||
33693c7a | 1745 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); |
f4f5df23 VC |
1746 | } |
1747 | ||
1748 | ||
1749 | static int | |
f8086f4f | 1750 | qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) |
f4f5df23 | 1751 | { |
f4f5df23 VC |
1752 | uint16_t lnk; |
1753 | ||
1754 | /* scrub dma mask expansion register */ | |
f8086f4f | 1755 | qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); |
f4f5df23 VC |
1756 | |
1757 | /* Overwrite stale initialization register values */ | |
f8086f4f VC |
1758 | qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); |
1759 | qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); | |
1760 | qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); | |
1761 | qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); | |
f4f5df23 | 1762 | |
f8086f4f | 1763 | if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { |
f4f5df23 VC |
1764 | printk("%s: Error trying to start fw!\n", __func__); |
1765 | return QLA_ERROR; | |
1766 | } | |
1767 | ||
1768 | /* Handshake with the card before we register the devices. */ | |
f8086f4f | 1769 | if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { |
f4f5df23 VC |
1770 | printk("%s: Error during card handshake!\n", __func__); |
1771 | return QLA_ERROR; | |
1772 | } | |
1773 | ||
1774 | /* Negotiated Link width */ | |
5548bfd0 | 1775 | pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); |
f4f5df23 VC |
1776 | ha->link_width = (lnk >> 4) & 0x3f; |
1777 | ||
1778 | /* Synchronize with Receive peg */ | |
f8086f4f | 1779 | return qla4_82xx_rcvpeg_ready(ha); |
f4f5df23 VC |
1780 | } |
1781 | ||
33693c7a | 1782 | int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) |
f4f5df23 VC |
1783 | { |
1784 | int rval = QLA_ERROR; | |
1785 | ||
1786 | /* | |
1787 | * FW Load priority: | |
1788 | * 1) Operational firmware residing in flash. | |
1789 | * 2) Fail | |
1790 | */ | |
1791 | ||
1792 | ql4_printk(KERN_INFO, ha, | |
1793 | "FW: Retrieving flash offsets from FLT/FDT ...\n"); | |
1794 | rval = qla4_8xxx_get_flash_info(ha); | |
1795 | if (rval != QLA_SUCCESS) | |
1796 | return rval; | |
1797 | ||
1798 | ql4_printk(KERN_INFO, ha, | |
1799 | "FW: Attempting to load firmware from flash...\n"); | |
f8086f4f | 1800 | rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); |
f4f5df23 | 1801 | |
f581a3f7 VC |
1802 | if (rval != QLA_SUCCESS) { |
1803 | ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" | |
1804 | " FAILED...\n"); | |
1805 | return rval; | |
1806 | } | |
f4f5df23 VC |
1807 | |
1808 | return rval; | |
1809 | } | |
1810 | ||
33693c7a | 1811 | void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) |
b25ee66f | 1812 | { |
f8086f4f | 1813 | if (qla4_82xx_rom_lock(ha)) { |
b25ee66f SS |
1814 | /* Someone else is holding the lock. */ |
1815 | dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); | |
1816 | } | |
1817 | ||
1818 | /* | |
1819 | * Either we got the lock, or someone | |
1820 | * else died while holding it. | |
1821 | * In either case, unlock. | |
1822 | */ | |
f8086f4f | 1823 | qla4_82xx_rom_unlock(ha); |
b25ee66f SS |
1824 | } |
1825 | ||
b1829789 TP |
1826 | static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha, |
1827 | uint32_t addr1, uint32_t mask) | |
1828 | { | |
1829 | unsigned long timeout; | |
1830 | uint32_t rval = QLA_SUCCESS; | |
1831 | uint32_t temp; | |
1832 | ||
1833 | timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); | |
1834 | do { | |
1835 | ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); | |
1836 | if ((temp & mask) != 0) | |
1837 | break; | |
1838 | ||
1839 | if (time_after_eq(jiffies, timeout)) { | |
1840 | ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n"); | |
1841 | return QLA_ERROR; | |
1842 | } | |
1843 | } while (1); | |
1844 | ||
1845 | return rval; | |
1846 | } | |
1847 | ||
02ccda2a | 1848 | static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1, |
b1829789 TP |
1849 | uint32_t addr3, uint32_t mask, uint32_t addr, |
1850 | uint32_t *data_ptr) | |
1851 | { | |
1852 | int rval = QLA_SUCCESS; | |
1853 | uint32_t temp; | |
1854 | uint32_t data; | |
1855 | ||
1856 | rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); | |
1857 | if (rval) | |
1858 | goto exit_ipmdio_rd_reg; | |
1859 | ||
1860 | temp = (0x40000000 | addr); | |
1861 | ha->isp_ops->wr_reg_indirect(ha, addr1, temp); | |
1862 | ||
1863 | rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); | |
1864 | if (rval) | |
1865 | goto exit_ipmdio_rd_reg; | |
1866 | ||
1867 | ha->isp_ops->rd_reg_indirect(ha, addr3, &data); | |
1868 | *data_ptr = data; | |
1869 | ||
1870 | exit_ipmdio_rd_reg: | |
1871 | return rval; | |
1872 | } | |
1873 | ||
1874 | ||
1875 | static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha, | |
1876 | uint32_t addr1, | |
1877 | uint32_t addr2, | |
1878 | uint32_t addr3, | |
1879 | uint32_t mask) | |
1880 | { | |
1881 | unsigned long timeout; | |
1882 | uint32_t temp; | |
1883 | uint32_t rval = QLA_SUCCESS; | |
1884 | ||
1885 | timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); | |
1886 | do { | |
1887 | ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp); | |
1888 | if ((temp & 0x1) != 1) | |
1889 | break; | |
1890 | if (time_after_eq(jiffies, timeout)) { | |
1891 | ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n"); | |
1892 | return QLA_ERROR; | |
1893 | } | |
1894 | } while (1); | |
1895 | ||
1896 | return rval; | |
1897 | } | |
1898 | ||
1899 | static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha, | |
1900 | uint32_t addr1, uint32_t addr3, | |
1901 | uint32_t mask, uint32_t addr, | |
1902 | uint32_t value) | |
1903 | { | |
1904 | int rval = QLA_SUCCESS; | |
1905 | ||
1906 | rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); | |
1907 | if (rval) | |
1908 | goto exit_ipmdio_wr_reg; | |
1909 | ||
1910 | ha->isp_ops->wr_reg_indirect(ha, addr3, value); | |
1911 | ha->isp_ops->wr_reg_indirect(ha, addr1, addr); | |
1912 | ||
1913 | rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); | |
1914 | if (rval) | |
1915 | goto exit_ipmdio_wr_reg; | |
1916 | ||
1917 | exit_ipmdio_wr_reg: | |
1918 | return rval; | |
1919 | } | |
1920 | ||
068237c8 | 1921 | static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, |
7664a1fd | 1922 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
1923 | uint32_t **d_ptr) |
1924 | { | |
1925 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; | |
7664a1fd | 1926 | struct qla8xxx_minidump_entry_crb *crb_hdr; |
068237c8 TP |
1927 | uint32_t *data_ptr = *d_ptr; |
1928 | ||
1929 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 1930 | crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; |
068237c8 TP |
1931 | r_addr = crb_hdr->addr; |
1932 | r_stride = crb_hdr->crb_strd.addr_stride; | |
1933 | loop_cnt = crb_hdr->op_count; | |
1934 | ||
1935 | for (i = 0; i < loop_cnt; i++) { | |
33693c7a | 1936 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
068237c8 TP |
1937 | *data_ptr++ = cpu_to_le32(r_addr); |
1938 | *data_ptr++ = cpu_to_le32(r_value); | |
1939 | r_addr += r_stride; | |
1940 | } | |
1941 | *d_ptr = data_ptr; | |
1942 | } | |
1943 | ||
41f79bde SV |
1944 | static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha) |
1945 | { | |
1946 | int rval = QLA_SUCCESS; | |
1947 | uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; | |
1948 | uint64_t dma_base_addr = 0; | |
1949 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; | |
1950 | ||
1951 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) | |
1952 | ha->fw_dump_tmplt_hdr; | |
1953 | dma_eng_num = | |
1954 | tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; | |
1955 | dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + | |
1956 | (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); | |
1957 | ||
1958 | /* Read the pex-dma's command-status-and-control register. */ | |
1959 | rval = ha->isp_ops->rd_reg_indirect(ha, | |
1960 | (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), | |
1961 | &cmd_sts_and_cntrl); | |
1962 | ||
1963 | if (rval) | |
1964 | return QLA_ERROR; | |
1965 | ||
1966 | /* Check if requested pex-dma engine is available. */ | |
1967 | if (cmd_sts_and_cntrl & BIT_31) | |
1968 | return QLA_SUCCESS; | |
1969 | else | |
1970 | return QLA_ERROR; | |
1971 | } | |
1972 | ||
1973 | static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha, | |
1974 | struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr) | |
1975 | { | |
1976 | int rval = QLA_SUCCESS, wait = 0; | |
1977 | uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; | |
1978 | uint64_t dma_base_addr = 0; | |
1979 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; | |
1980 | ||
1981 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) | |
1982 | ha->fw_dump_tmplt_hdr; | |
1983 | dma_eng_num = | |
1984 | tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; | |
1985 | dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + | |
1986 | (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); | |
1987 | ||
1988 | rval = ha->isp_ops->wr_reg_indirect(ha, | |
1989 | dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW, | |
1990 | m_hdr->desc_card_addr); | |
1991 | if (rval) | |
1992 | goto error_exit; | |
1993 | ||
1994 | rval = ha->isp_ops->wr_reg_indirect(ha, | |
1995 | dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); | |
1996 | if (rval) | |
1997 | goto error_exit; | |
1998 | ||
1999 | rval = ha->isp_ops->wr_reg_indirect(ha, | |
2000 | dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL, | |
2001 | m_hdr->start_dma_cmd); | |
2002 | if (rval) | |
2003 | goto error_exit; | |
2004 | ||
2005 | /* Wait for dma operation to complete. */ | |
2006 | for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { | |
2007 | rval = ha->isp_ops->rd_reg_indirect(ha, | |
2008 | (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), | |
2009 | &cmd_sts_and_cntrl); | |
2010 | if (rval) | |
2011 | goto error_exit; | |
2012 | ||
2013 | if ((cmd_sts_and_cntrl & BIT_1) == 0) | |
2014 | break; | |
2015 | else | |
2016 | udelay(10); | |
2017 | } | |
2018 | ||
2019 | /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ | |
2020 | if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) { | |
2021 | rval = QLA_ERROR; | |
2022 | goto error_exit; | |
2023 | } | |
2024 | ||
2025 | error_exit: | |
2026 | return rval; | |
2027 | } | |
2028 | ||
3c3cab17 | 2029 | static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha, |
41f79bde SV |
2030 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
2031 | uint32_t **d_ptr) | |
2032 | { | |
2033 | int rval = QLA_SUCCESS; | |
2034 | struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL; | |
2035 | uint32_t size, read_size; | |
2036 | uint8_t *data_ptr = (uint8_t *)*d_ptr; | |
2037 | void *rdmem_buffer = NULL; | |
2038 | dma_addr_t rdmem_dma; | |
2039 | struct qla4_83xx_pex_dma_descriptor dma_desc; | |
2040 | ||
2041 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
2042 | ||
2043 | rval = qla4_83xx_check_dma_engine_state(ha); | |
2044 | if (rval != QLA_SUCCESS) { | |
2045 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2046 | "%s: DMA engine not available. Fallback to rdmem-read.\n", | |
2047 | __func__)); | |
2048 | return QLA_ERROR; | |
2049 | } | |
2050 | ||
2051 | m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr; | |
2052 | rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, | |
2053 | QLA83XX_PEX_DMA_READ_SIZE, | |
2054 | &rdmem_dma, GFP_KERNEL); | |
2055 | if (!rdmem_buffer) { | |
2056 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2057 | "%s: Unable to allocate rdmem dma buffer\n", | |
2058 | __func__)); | |
2059 | return QLA_ERROR; | |
2060 | } | |
2061 | ||
2062 | /* Prepare pex-dma descriptor to be written to MS memory. */ | |
2063 | /* dma-desc-cmd layout: | |
2064 | * 0-3: dma-desc-cmd 0-3 | |
2065 | * 4-7: pcid function number | |
2066 | * 8-15: dma-desc-cmd 8-15 | |
2067 | */ | |
2068 | dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); | |
2069 | dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); | |
2070 | dma_desc.dma_bus_addr = rdmem_dma; | |
2071 | ||
2072 | size = 0; | |
2073 | read_size = 0; | |
2074 | /* | |
2075 | * Perform rdmem operation using pex-dma. | |
2076 | * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE. | |
2077 | */ | |
2078 | while (read_size < m_hdr->read_data_size) { | |
2079 | if (m_hdr->read_data_size - read_size >= | |
2080 | QLA83XX_PEX_DMA_READ_SIZE) | |
2081 | size = QLA83XX_PEX_DMA_READ_SIZE; | |
2082 | else { | |
2083 | size = (m_hdr->read_data_size - read_size); | |
2084 | ||
2085 | if (rdmem_buffer) | |
2086 | dma_free_coherent(&ha->pdev->dev, | |
2087 | QLA83XX_PEX_DMA_READ_SIZE, | |
2088 | rdmem_buffer, rdmem_dma); | |
2089 | ||
2090 | rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size, | |
2091 | &rdmem_dma, | |
2092 | GFP_KERNEL); | |
2093 | if (!rdmem_buffer) { | |
2094 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2095 | "%s: Unable to allocate rdmem dma buffer\n", | |
2096 | __func__)); | |
2097 | return QLA_ERROR; | |
2098 | } | |
2099 | dma_desc.dma_bus_addr = rdmem_dma; | |
2100 | } | |
2101 | ||
2102 | dma_desc.src_addr = m_hdr->read_addr + read_size; | |
2103 | dma_desc.cmd.read_data_size = size; | |
2104 | ||
2105 | /* Prepare: Write pex-dma descriptor to MS memory. */ | |
3c3cab17 | 2106 | rval = qla4_8xxx_ms_mem_write_128b(ha, |
41f79bde SV |
2107 | (uint64_t)m_hdr->desc_card_addr, |
2108 | (uint32_t *)&dma_desc, | |
2109 | (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); | |
9c4f8d92 | 2110 | if (rval != QLA_SUCCESS) { |
41f79bde SV |
2111 | ql4_printk(KERN_INFO, ha, |
2112 | "%s: Error writing rdmem-dma-init to MS !!!\n", | |
2113 | __func__); | |
2114 | goto error_exit; | |
2115 | } | |
2116 | ||
2117 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2118 | "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", | |
2119 | __func__, size)); | |
2120 | /* Execute: Start pex-dma operation. */ | |
2121 | rval = qla4_83xx_start_pex_dma(ha, m_hdr); | |
2122 | if (rval != QLA_SUCCESS) { | |
2123 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2124 | "scsi(%ld): start-pex-dma failed rval=0x%x\n", | |
2125 | ha->host_no, rval)); | |
2126 | goto error_exit; | |
2127 | } | |
2128 | ||
2129 | memcpy(data_ptr, rdmem_buffer, size); | |
2130 | data_ptr += size; | |
2131 | read_size += size; | |
2132 | } | |
2133 | ||
2134 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); | |
2135 | ||
2136 | *d_ptr = (uint32_t *)data_ptr; | |
2137 | ||
2138 | error_exit: | |
2139 | if (rdmem_buffer) | |
2140 | dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer, | |
2141 | rdmem_dma); | |
2142 | ||
2143 | return rval; | |
2144 | } | |
2145 | ||
068237c8 | 2146 | static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, |
7664a1fd | 2147 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2148 | uint32_t **d_ptr) |
2149 | { | |
2150 | uint32_t addr, r_addr, c_addr, t_r_addr; | |
2151 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; | |
2152 | unsigned long p_wait, w_time, p_mask; | |
2153 | uint32_t c_value_w, c_value_r; | |
7664a1fd | 2154 | struct qla8xxx_minidump_entry_cache *cache_hdr; |
068237c8 TP |
2155 | int rval = QLA_ERROR; |
2156 | uint32_t *data_ptr = *d_ptr; | |
2157 | ||
2158 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2159 | cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; |
068237c8 TP |
2160 | |
2161 | loop_count = cache_hdr->op_count; | |
2162 | r_addr = cache_hdr->read_addr; | |
2163 | c_addr = cache_hdr->control_addr; | |
2164 | c_value_w = cache_hdr->cache_ctrl.write_value; | |
2165 | ||
2166 | t_r_addr = cache_hdr->tag_reg_addr; | |
2167 | t_value = cache_hdr->addr_ctrl.init_tag_value; | |
2168 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; | |
2169 | p_wait = cache_hdr->cache_ctrl.poll_wait; | |
2170 | p_mask = cache_hdr->cache_ctrl.poll_mask; | |
2171 | ||
2172 | for (i = 0; i < loop_count; i++) { | |
33693c7a | 2173 | ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); |
068237c8 TP |
2174 | |
2175 | if (c_value_w) | |
33693c7a | 2176 | ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); |
068237c8 TP |
2177 | |
2178 | if (p_mask) { | |
2179 | w_time = jiffies + p_wait; | |
2180 | do { | |
33693c7a VC |
2181 | ha->isp_ops->rd_reg_indirect(ha, c_addr, |
2182 | &c_value_r); | |
068237c8 TP |
2183 | if ((c_value_r & p_mask) == 0) { |
2184 | break; | |
2185 | } else if (time_after_eq(jiffies, w_time)) { | |
2186 | /* capturing dump failed */ | |
2187 | return rval; | |
2188 | } | |
2189 | } while (1); | |
2190 | } | |
2191 | ||
2192 | addr = r_addr; | |
2193 | for (k = 0; k < r_cnt; k++) { | |
33693c7a | 2194 | ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); |
068237c8 TP |
2195 | *data_ptr++ = cpu_to_le32(r_value); |
2196 | addr += cache_hdr->read_ctrl.read_addr_stride; | |
2197 | } | |
2198 | ||
2199 | t_value += cache_hdr->addr_ctrl.tag_value_stride; | |
2200 | } | |
2201 | *d_ptr = data_ptr; | |
2202 | return QLA_SUCCESS; | |
2203 | } | |
2204 | ||
2205 | static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |
7664a1fd | 2206 | struct qla8xxx_minidump_entry_hdr *entry_hdr) |
068237c8 | 2207 | { |
7664a1fd | 2208 | struct qla8xxx_minidump_entry_crb *crb_entry; |
068237c8 TP |
2209 | uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; |
2210 | uint32_t crb_addr; | |
2211 | unsigned long wtime; | |
2212 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; | |
2213 | int i; | |
2214 | ||
2215 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
2216 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) | |
2217 | ha->fw_dump_tmplt_hdr; | |
7664a1fd | 2218 | crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; |
068237c8 TP |
2219 | |
2220 | crb_addr = crb_entry->addr; | |
2221 | for (i = 0; i < crb_entry->op_count; i++) { | |
2222 | opcode = crb_entry->crb_ctrl.opcode; | |
de8c72da | 2223 | if (opcode & QLA8XXX_DBG_OPCODE_WR) { |
33693c7a VC |
2224 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, |
2225 | crb_entry->value_1); | |
de8c72da | 2226 | opcode &= ~QLA8XXX_DBG_OPCODE_WR; |
068237c8 | 2227 | } |
de8c72da | 2228 | if (opcode & QLA8XXX_DBG_OPCODE_RW) { |
33693c7a VC |
2229 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
2230 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); | |
de8c72da | 2231 | opcode &= ~QLA8XXX_DBG_OPCODE_RW; |
068237c8 | 2232 | } |
de8c72da | 2233 | if (opcode & QLA8XXX_DBG_OPCODE_AND) { |
33693c7a | 2234 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
068237c8 | 2235 | read_value &= crb_entry->value_2; |
de8c72da VC |
2236 | opcode &= ~QLA8XXX_DBG_OPCODE_AND; |
2237 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { | |
068237c8 | 2238 | read_value |= crb_entry->value_3; |
de8c72da | 2239 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
068237c8 | 2240 | } |
33693c7a | 2241 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); |
068237c8 | 2242 | } |
de8c72da | 2243 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { |
33693c7a | 2244 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
068237c8 | 2245 | read_value |= crb_entry->value_3; |
33693c7a | 2246 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); |
de8c72da | 2247 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
068237c8 | 2248 | } |
de8c72da | 2249 | if (opcode & QLA8XXX_DBG_OPCODE_POLL) { |
068237c8 TP |
2250 | poll_time = crb_entry->crb_strd.poll_timeout; |
2251 | wtime = jiffies + poll_time; | |
33693c7a | 2252 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
068237c8 TP |
2253 | |
2254 | do { | |
2255 | if ((read_value & crb_entry->value_2) == | |
33693c7a | 2256 | crb_entry->value_1) { |
068237c8 | 2257 | break; |
33693c7a | 2258 | } else if (time_after_eq(jiffies, wtime)) { |
068237c8 TP |
2259 | /* capturing dump failed */ |
2260 | rval = QLA_ERROR; | |
2261 | break; | |
33693c7a VC |
2262 | } else { |
2263 | ha->isp_ops->rd_reg_indirect(ha, | |
2264 | crb_addr, &read_value); | |
2265 | } | |
068237c8 | 2266 | } while (1); |
de8c72da | 2267 | opcode &= ~QLA8XXX_DBG_OPCODE_POLL; |
068237c8 TP |
2268 | } |
2269 | ||
de8c72da | 2270 | if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { |
068237c8 TP |
2271 | if (crb_entry->crb_strd.state_index_a) { |
2272 | index = crb_entry->crb_strd.state_index_a; | |
2273 | addr = tmplt_hdr->saved_state_array[index]; | |
2274 | } else { | |
2275 | addr = crb_addr; | |
2276 | } | |
2277 | ||
33693c7a | 2278 | ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); |
068237c8 TP |
2279 | index = crb_entry->crb_ctrl.state_index_v; |
2280 | tmplt_hdr->saved_state_array[index] = read_value; | |
de8c72da | 2281 | opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; |
068237c8 TP |
2282 | } |
2283 | ||
de8c72da | 2284 | if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { |
068237c8 TP |
2285 | if (crb_entry->crb_strd.state_index_a) { |
2286 | index = crb_entry->crb_strd.state_index_a; | |
2287 | addr = tmplt_hdr->saved_state_array[index]; | |
2288 | } else { | |
2289 | addr = crb_addr; | |
2290 | } | |
2291 | ||
2292 | if (crb_entry->crb_ctrl.state_index_v) { | |
2293 | index = crb_entry->crb_ctrl.state_index_v; | |
2294 | read_value = | |
2295 | tmplt_hdr->saved_state_array[index]; | |
2296 | } else { | |
2297 | read_value = crb_entry->value_1; | |
2298 | } | |
2299 | ||
33693c7a | 2300 | ha->isp_ops->wr_reg_indirect(ha, addr, read_value); |
de8c72da | 2301 | opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; |
068237c8 TP |
2302 | } |
2303 | ||
de8c72da | 2304 | if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { |
068237c8 TP |
2305 | index = crb_entry->crb_ctrl.state_index_v; |
2306 | read_value = tmplt_hdr->saved_state_array[index]; | |
2307 | read_value <<= crb_entry->crb_ctrl.shl; | |
2308 | read_value >>= crb_entry->crb_ctrl.shr; | |
2309 | if (crb_entry->value_2) | |
2310 | read_value &= crb_entry->value_2; | |
2311 | read_value |= crb_entry->value_3; | |
2312 | read_value += crb_entry->value_1; | |
2313 | tmplt_hdr->saved_state_array[index] = read_value; | |
de8c72da | 2314 | opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; |
068237c8 TP |
2315 | } |
2316 | crb_addr += crb_entry->crb_strd.addr_stride; | |
2317 | } | |
2318 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); | |
2319 | return rval; | |
2320 | } | |
2321 | ||
2322 | static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, | |
7664a1fd | 2323 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2324 | uint32_t **d_ptr) |
2325 | { | |
2326 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; | |
7664a1fd | 2327 | struct qla8xxx_minidump_entry_rdocm *ocm_hdr; |
068237c8 TP |
2328 | uint32_t *data_ptr = *d_ptr; |
2329 | ||
2330 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2331 | ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; |
068237c8 TP |
2332 | r_addr = ocm_hdr->read_addr; |
2333 | r_stride = ocm_hdr->read_addr_stride; | |
2334 | loop_cnt = ocm_hdr->op_count; | |
2335 | ||
2336 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2337 | "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", | |
2338 | __func__, r_addr, r_stride, loop_cnt)); | |
2339 | ||
2340 | for (i = 0; i < loop_cnt; i++) { | |
2341 | r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); | |
2342 | *data_ptr++ = cpu_to_le32(r_value); | |
2343 | r_addr += r_stride; | |
2344 | } | |
2345 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", | |
26fdf922 | 2346 | __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); |
068237c8 TP |
2347 | *d_ptr = data_ptr; |
2348 | } | |
2349 | ||
2350 | static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, | |
7664a1fd | 2351 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2352 | uint32_t **d_ptr) |
2353 | { | |
2354 | uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; | |
7664a1fd | 2355 | struct qla8xxx_minidump_entry_mux *mux_hdr; |
068237c8 TP |
2356 | uint32_t *data_ptr = *d_ptr; |
2357 | ||
2358 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2359 | mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; |
068237c8 TP |
2360 | r_addr = mux_hdr->read_addr; |
2361 | s_addr = mux_hdr->select_addr; | |
2362 | s_stride = mux_hdr->select_value_stride; | |
2363 | s_value = mux_hdr->select_value; | |
2364 | loop_cnt = mux_hdr->op_count; | |
2365 | ||
2366 | for (i = 0; i < loop_cnt; i++) { | |
33693c7a VC |
2367 | ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); |
2368 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); | |
068237c8 TP |
2369 | *data_ptr++ = cpu_to_le32(s_value); |
2370 | *data_ptr++ = cpu_to_le32(r_value); | |
2371 | s_value += s_stride; | |
2372 | } | |
2373 | *d_ptr = data_ptr; | |
2374 | } | |
2375 | ||
2376 | static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, | |
7664a1fd | 2377 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2378 | uint32_t **d_ptr) |
2379 | { | |
2380 | uint32_t addr, r_addr, c_addr, t_r_addr; | |
2381 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; | |
2382 | uint32_t c_value_w; | |
7664a1fd | 2383 | struct qla8xxx_minidump_entry_cache *cache_hdr; |
068237c8 TP |
2384 | uint32_t *data_ptr = *d_ptr; |
2385 | ||
7664a1fd | 2386 | cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; |
068237c8 TP |
2387 | loop_count = cache_hdr->op_count; |
2388 | r_addr = cache_hdr->read_addr; | |
2389 | c_addr = cache_hdr->control_addr; | |
2390 | c_value_w = cache_hdr->cache_ctrl.write_value; | |
2391 | ||
2392 | t_r_addr = cache_hdr->tag_reg_addr; | |
2393 | t_value = cache_hdr->addr_ctrl.init_tag_value; | |
2394 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; | |
2395 | ||
2396 | for (i = 0; i < loop_count; i++) { | |
33693c7a VC |
2397 | ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); |
2398 | ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); | |
068237c8 TP |
2399 | addr = r_addr; |
2400 | for (k = 0; k < r_cnt; k++) { | |
33693c7a | 2401 | ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); |
068237c8 TP |
2402 | *data_ptr++ = cpu_to_le32(r_value); |
2403 | addr += cache_hdr->read_ctrl.read_addr_stride; | |
2404 | } | |
2405 | t_value += cache_hdr->addr_ctrl.tag_value_stride; | |
2406 | } | |
2407 | *d_ptr = data_ptr; | |
2408 | } | |
2409 | ||
2410 | static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, | |
7664a1fd | 2411 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2412 | uint32_t **d_ptr) |
2413 | { | |
2414 | uint32_t s_addr, r_addr; | |
2415 | uint32_t r_stride, r_value, r_cnt, qid = 0; | |
2416 | uint32_t i, k, loop_cnt; | |
7664a1fd | 2417 | struct qla8xxx_minidump_entry_queue *q_hdr; |
068237c8 TP |
2418 | uint32_t *data_ptr = *d_ptr; |
2419 | ||
2420 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2421 | q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; |
068237c8 TP |
2422 | s_addr = q_hdr->select_addr; |
2423 | r_cnt = q_hdr->rd_strd.read_addr_cnt; | |
2424 | r_stride = q_hdr->rd_strd.read_addr_stride; | |
2425 | loop_cnt = q_hdr->op_count; | |
2426 | ||
2427 | for (i = 0; i < loop_cnt; i++) { | |
33693c7a | 2428 | ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); |
068237c8 TP |
2429 | r_addr = q_hdr->read_addr; |
2430 | for (k = 0; k < r_cnt; k++) { | |
33693c7a | 2431 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
068237c8 TP |
2432 | *data_ptr++ = cpu_to_le32(r_value); |
2433 | r_addr += r_stride; | |
2434 | } | |
2435 | qid += q_hdr->q_strd.queue_id_stride; | |
2436 | } | |
2437 | *d_ptr = data_ptr; | |
2438 | } | |
2439 | ||
2440 | #define MD_DIRECT_ROM_WINDOW 0x42110030 | |
2441 | #define MD_DIRECT_ROM_READ_BASE 0x42150000 | |
2442 | ||
f8086f4f | 2443 | static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, |
7664a1fd | 2444 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2445 | uint32_t **d_ptr) |
2446 | { | |
2447 | uint32_t r_addr, r_value; | |
2448 | uint32_t i, loop_cnt; | |
7664a1fd | 2449 | struct qla8xxx_minidump_entry_rdrom *rom_hdr; |
068237c8 TP |
2450 | uint32_t *data_ptr = *d_ptr; |
2451 | ||
2452 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2453 | rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; |
068237c8 TP |
2454 | r_addr = rom_hdr->read_addr; |
2455 | loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); | |
2456 | ||
2457 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2458 | "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", | |
2459 | __func__, r_addr, loop_cnt)); | |
2460 | ||
2461 | for (i = 0; i < loop_cnt; i++) { | |
33693c7a VC |
2462 | ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, |
2463 | (r_addr & 0xFFFF0000)); | |
2464 | ha->isp_ops->rd_reg_indirect(ha, | |
2465 | MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), | |
2466 | &r_value); | |
068237c8 TP |
2467 | *data_ptr++ = cpu_to_le32(r_value); |
2468 | r_addr += sizeof(uint32_t); | |
2469 | } | |
2470 | *d_ptr = data_ptr; | |
2471 | } | |
2472 | ||
2473 | #define MD_MIU_TEST_AGT_CTRL 0x41000090 | |
2474 | #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 | |
2475 | #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 | |
2476 | ||
41f79bde | 2477 | static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, |
7664a1fd | 2478 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2479 | uint32_t **d_ptr) |
2480 | { | |
2481 | uint32_t r_addr, r_value, r_data; | |
2482 | uint32_t i, j, loop_cnt; | |
7664a1fd | 2483 | struct qla8xxx_minidump_entry_rdmem *m_hdr; |
068237c8 TP |
2484 | unsigned long flags; |
2485 | uint32_t *data_ptr = *d_ptr; | |
2486 | ||
2487 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); | |
7664a1fd | 2488 | m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; |
068237c8 TP |
2489 | r_addr = m_hdr->read_addr; |
2490 | loop_cnt = m_hdr->read_data_size/16; | |
2491 | ||
2492 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2493 | "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", | |
2494 | __func__, r_addr, m_hdr->read_data_size)); | |
2495 | ||
2496 | if (r_addr & 0xf) { | |
2497 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
cf2fbdd2 | 2498 | "[%s]: Read addr 0x%x not 16 bytes aligned\n", |
068237c8 TP |
2499 | __func__, r_addr)); |
2500 | return QLA_ERROR; | |
2501 | } | |
2502 | ||
2503 | if (m_hdr->read_data_size % 16) { | |
2504 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2505 | "[%s]: Read data[0x%x] not multiple of 16 bytes\n", | |
2506 | __func__, m_hdr->read_data_size)); | |
2507 | return QLA_ERROR; | |
2508 | } | |
2509 | ||
2510 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2511 | "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", | |
2512 | __func__, r_addr, m_hdr->read_data_size, loop_cnt)); | |
2513 | ||
2514 | write_lock_irqsave(&ha->hw_lock, flags); | |
2515 | for (i = 0; i < loop_cnt; i++) { | |
33693c7a VC |
2516 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, |
2517 | r_addr); | |
068237c8 | 2518 | r_value = 0; |
33693c7a VC |
2519 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, |
2520 | r_value); | |
068237c8 | 2521 | r_value = MIU_TA_CTL_ENABLE; |
33693c7a | 2522 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); |
c38fa3ab | 2523 | r_value = MIU_TA_CTL_START_ENABLE; |
33693c7a | 2524 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); |
068237c8 TP |
2525 | |
2526 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
33693c7a VC |
2527 | ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, |
2528 | &r_value); | |
068237c8 TP |
2529 | if ((r_value & MIU_TA_CTL_BUSY) == 0) |
2530 | break; | |
2531 | } | |
2532 | ||
2533 | if (j >= MAX_CTL_CHECK) { | |
2534 | printk_ratelimited(KERN_ERR | |
2535 | "%s: failed to read through agent\n", | |
2536 | __func__); | |
2537 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
2538 | return QLA_SUCCESS; | |
2539 | } | |
2540 | ||
2541 | for (j = 0; j < 4; j++) { | |
33693c7a VC |
2542 | ha->isp_ops->rd_reg_indirect(ha, |
2543 | MD_MIU_TEST_AGT_RDDATA[j], | |
2544 | &r_data); | |
068237c8 TP |
2545 | *data_ptr++ = cpu_to_le32(r_data); |
2546 | } | |
2547 | ||
2548 | r_addr += 16; | |
2549 | } | |
2550 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
2551 | ||
2552 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", | |
2553 | __func__, (loop_cnt * 16))); | |
2554 | ||
2555 | *d_ptr = data_ptr; | |
2556 | return QLA_SUCCESS; | |
2557 | } | |
2558 | ||
41f79bde SV |
2559 | static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, |
2560 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2561 | uint32_t **d_ptr) | |
2562 | { | |
2563 | uint32_t *data_ptr = *d_ptr; | |
2564 | int rval = QLA_SUCCESS; | |
2565 | ||
3c3cab17 TP |
2566 | rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr); |
2567 | if (rval != QLA_SUCCESS) | |
41f79bde SV |
2568 | rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, |
2569 | &data_ptr); | |
41f79bde SV |
2570 | *d_ptr = data_ptr; |
2571 | return rval; | |
2572 | } | |
2573 | ||
5e9bcec7 | 2574 | static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, |
7664a1fd | 2575 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
068237c8 TP |
2576 | int index) |
2577 | { | |
de8c72da | 2578 | entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; |
068237c8 TP |
2579 | DEBUG2(ql4_printk(KERN_INFO, ha, |
2580 | "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", | |
2581 | ha->host_no, index, entry_hdr->entry_type, | |
2582 | entry_hdr->d_ctrl.entry_capture_mask)); | |
58e2bbe9 TP |
2583 | /* If driver encounters a new entry type that it cannot process, |
2584 | * it should just skip the entry and adjust the total buffer size by | |
2585 | * from subtracting the skipped bytes from it | |
2586 | */ | |
2587 | ha->fw_dump_skip_size += entry_hdr->entry_capture_size; | |
068237c8 TP |
2588 | } |
2589 | ||
6e7b4292 VC |
2590 | /* ISP83xx functions to process new minidump entries... */ |
2591 | static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, | |
2592 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2593 | uint32_t **d_ptr) | |
2594 | { | |
2595 | uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; | |
2596 | uint16_t s_stride, i; | |
2597 | uint32_t *data_ptr = *d_ptr; | |
2598 | uint32_t rval = QLA_SUCCESS; | |
2599 | struct qla83xx_minidump_entry_pollrd *pollrd_hdr; | |
2600 | ||
2601 | pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; | |
2602 | s_addr = le32_to_cpu(pollrd_hdr->select_addr); | |
2603 | r_addr = le32_to_cpu(pollrd_hdr->read_addr); | |
2604 | s_value = le32_to_cpu(pollrd_hdr->select_value); | |
2605 | s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); | |
2606 | ||
2607 | poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); | |
2608 | poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); | |
2609 | ||
2610 | for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { | |
2611 | ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); | |
2612 | poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); | |
2613 | while (1) { | |
2614 | ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); | |
2615 | ||
2616 | if ((r_value & poll_mask) != 0) { | |
2617 | break; | |
2618 | } else { | |
2619 | msleep(1); | |
2620 | if (--poll_wait == 0) { | |
2621 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", | |
2622 | __func__); | |
2623 | rval = QLA_ERROR; | |
2624 | goto exit_process_pollrd; | |
2625 | } | |
2626 | } | |
2627 | } | |
2628 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); | |
2629 | *data_ptr++ = cpu_to_le32(s_value); | |
2630 | *data_ptr++ = cpu_to_le32(r_value); | |
2631 | s_value += s_stride; | |
2632 | } | |
2633 | ||
2634 | *d_ptr = data_ptr; | |
2635 | ||
2636 | exit_process_pollrd: | |
2637 | return rval; | |
2638 | } | |
2639 | ||
b1829789 TP |
2640 | static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha, |
2641 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2642 | uint32_t **d_ptr) | |
2643 | { | |
2644 | int loop_cnt; | |
2645 | uint32_t addr1, addr2, value, data, temp, wrval; | |
2646 | uint8_t stride, stride2; | |
2647 | uint16_t count; | |
2648 | uint32_t poll, mask, data_size, modify_mask; | |
2649 | uint32_t wait_count = 0; | |
2650 | uint32_t *data_ptr = *d_ptr; | |
2651 | struct qla8044_minidump_entry_rddfe *rddfe; | |
2652 | uint32_t rval = QLA_SUCCESS; | |
2653 | ||
2654 | rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr; | |
2655 | addr1 = le32_to_cpu(rddfe->addr_1); | |
2656 | value = le32_to_cpu(rddfe->value); | |
2657 | stride = le32_to_cpu(rddfe->stride); | |
2658 | stride2 = le32_to_cpu(rddfe->stride2); | |
2659 | count = le32_to_cpu(rddfe->count); | |
2660 | ||
2661 | poll = le32_to_cpu(rddfe->poll); | |
2662 | mask = le32_to_cpu(rddfe->mask); | |
2663 | modify_mask = le32_to_cpu(rddfe->modify_mask); | |
2664 | data_size = le32_to_cpu(rddfe->data_size); | |
2665 | ||
2666 | addr2 = addr1 + stride; | |
2667 | ||
2668 | for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { | |
2669 | ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value)); | |
2670 | ||
2671 | wait_count = 0; | |
2672 | while (wait_count < poll) { | |
2673 | ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); | |
2674 | if ((temp & mask) != 0) | |
2675 | break; | |
2676 | wait_count++; | |
2677 | } | |
2678 | ||
2679 | if (wait_count == poll) { | |
2680 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); | |
2681 | rval = QLA_ERROR; | |
2682 | goto exit_process_rddfe; | |
2683 | } else { | |
2684 | ha->isp_ops->rd_reg_indirect(ha, addr2, &temp); | |
2685 | temp = temp & modify_mask; | |
2686 | temp = (temp | ((loop_cnt << 16) | loop_cnt)); | |
2687 | wrval = ((temp << 16) | temp); | |
2688 | ||
2689 | ha->isp_ops->wr_reg_indirect(ha, addr2, wrval); | |
2690 | ha->isp_ops->wr_reg_indirect(ha, addr1, value); | |
2691 | ||
2692 | wait_count = 0; | |
2693 | while (wait_count < poll) { | |
2694 | ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); | |
2695 | if ((temp & mask) != 0) | |
2696 | break; | |
2697 | wait_count++; | |
2698 | } | |
2699 | if (wait_count == poll) { | |
2700 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", | |
2701 | __func__); | |
2702 | rval = QLA_ERROR; | |
2703 | goto exit_process_rddfe; | |
2704 | } | |
2705 | ||
2706 | ha->isp_ops->wr_reg_indirect(ha, addr1, | |
2707 | ((0x40000000 | value) + | |
2708 | stride2)); | |
2709 | wait_count = 0; | |
2710 | while (wait_count < poll) { | |
2711 | ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); | |
2712 | if ((temp & mask) != 0) | |
2713 | break; | |
2714 | wait_count++; | |
2715 | } | |
2716 | ||
2717 | if (wait_count == poll) { | |
2718 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", | |
2719 | __func__); | |
2720 | rval = QLA_ERROR; | |
2721 | goto exit_process_rddfe; | |
2722 | } | |
2723 | ||
2724 | ha->isp_ops->rd_reg_indirect(ha, addr2, &data); | |
2725 | ||
2726 | *data_ptr++ = cpu_to_le32(wrval); | |
2727 | *data_ptr++ = cpu_to_le32(data); | |
2728 | } | |
2729 | } | |
2730 | ||
2731 | *d_ptr = data_ptr; | |
2732 | exit_process_rddfe: | |
2733 | return rval; | |
2734 | } | |
2735 | ||
2736 | static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha, | |
2737 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2738 | uint32_t **d_ptr) | |
2739 | { | |
2740 | int rval = QLA_SUCCESS; | |
2741 | uint32_t addr1, addr2, value1, value2, data, selval; | |
2742 | uint8_t stride1, stride2; | |
2743 | uint32_t addr3, addr4, addr5, addr6, addr7; | |
2744 | uint16_t count, loop_cnt; | |
2745 | uint32_t poll, mask; | |
2746 | uint32_t *data_ptr = *d_ptr; | |
2747 | struct qla8044_minidump_entry_rdmdio *rdmdio; | |
2748 | ||
2749 | rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr; | |
2750 | addr1 = le32_to_cpu(rdmdio->addr_1); | |
2751 | addr2 = le32_to_cpu(rdmdio->addr_2); | |
2752 | value1 = le32_to_cpu(rdmdio->value_1); | |
2753 | stride1 = le32_to_cpu(rdmdio->stride_1); | |
2754 | stride2 = le32_to_cpu(rdmdio->stride_2); | |
2755 | count = le32_to_cpu(rdmdio->count); | |
2756 | ||
2757 | poll = le32_to_cpu(rdmdio->poll); | |
2758 | mask = le32_to_cpu(rdmdio->mask); | |
2759 | value2 = le32_to_cpu(rdmdio->value_2); | |
2760 | ||
2761 | addr3 = addr1 + stride1; | |
2762 | ||
2763 | for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { | |
2764 | rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, | |
2765 | addr3, mask); | |
2766 | if (rval) | |
2767 | goto exit_process_rdmdio; | |
2768 | ||
2769 | addr4 = addr2 - stride1; | |
2770 | rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4, | |
2771 | value2); | |
2772 | if (rval) | |
2773 | goto exit_process_rdmdio; | |
2774 | ||
2775 | addr5 = addr2 - (2 * stride1); | |
2776 | rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5, | |
2777 | value1); | |
2778 | if (rval) | |
2779 | goto exit_process_rdmdio; | |
2780 | ||
2781 | addr6 = addr2 - (3 * stride1); | |
2782 | rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, | |
2783 | addr6, 0x2); | |
2784 | if (rval) | |
2785 | goto exit_process_rdmdio; | |
2786 | ||
2787 | rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, | |
2788 | addr3, mask); | |
2789 | if (rval) | |
2790 | goto exit_process_rdmdio; | |
2791 | ||
2792 | addr7 = addr2 - (4 * stride1); | |
2793 | rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, | |
2794 | mask, addr7, &data); | |
2795 | if (rval) | |
2796 | goto exit_process_rdmdio; | |
2797 | ||
2798 | selval = (value2 << 18) | (value1 << 2) | 2; | |
2799 | ||
2800 | stride2 = le32_to_cpu(rdmdio->stride_2); | |
2801 | *data_ptr++ = cpu_to_le32(selval); | |
2802 | *data_ptr++ = cpu_to_le32(data); | |
2803 | ||
2804 | value1 = value1 + stride2; | |
2805 | *d_ptr = data_ptr; | |
2806 | } | |
2807 | ||
2808 | exit_process_rdmdio: | |
2809 | return rval; | |
2810 | } | |
2811 | ||
2812 | static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha, | |
2813 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2814 | uint32_t **d_ptr) | |
2815 | { | |
2816 | uint32_t addr1, addr2, value1, value2, poll, mask, r_value; | |
2817 | struct qla8044_minidump_entry_pollwr *pollwr_hdr; | |
2818 | uint32_t wait_count = 0; | |
2819 | uint32_t rval = QLA_SUCCESS; | |
2820 | ||
2821 | pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; | |
2822 | addr1 = le32_to_cpu(pollwr_hdr->addr_1); | |
2823 | addr2 = le32_to_cpu(pollwr_hdr->addr_2); | |
2824 | value1 = le32_to_cpu(pollwr_hdr->value_1); | |
2825 | value2 = le32_to_cpu(pollwr_hdr->value_2); | |
2826 | ||
2827 | poll = le32_to_cpu(pollwr_hdr->poll); | |
2828 | mask = le32_to_cpu(pollwr_hdr->mask); | |
2829 | ||
2830 | while (wait_count < poll) { | |
2831 | ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); | |
2832 | ||
2833 | if ((r_value & poll) != 0) | |
2834 | break; | |
2835 | ||
2836 | wait_count++; | |
2837 | } | |
2838 | ||
2839 | if (wait_count == poll) { | |
2840 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); | |
2841 | rval = QLA_ERROR; | |
2842 | goto exit_process_pollwr; | |
2843 | } | |
2844 | ||
2845 | ha->isp_ops->wr_reg_indirect(ha, addr2, value2); | |
2846 | ha->isp_ops->wr_reg_indirect(ha, addr1, value1); | |
2847 | ||
2848 | wait_count = 0; | |
2849 | while (wait_count < poll) { | |
2850 | ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); | |
2851 | ||
2852 | if ((r_value & poll) != 0) | |
2853 | break; | |
2854 | wait_count++; | |
2855 | } | |
2856 | ||
2857 | exit_process_pollwr: | |
2858 | return rval; | |
2859 | } | |
2860 | ||
6e7b4292 VC |
2861 | static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, |
2862 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2863 | uint32_t **d_ptr) | |
2864 | { | |
2865 | uint32_t sel_val1, sel_val2, t_sel_val, data, i; | |
2866 | uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; | |
2867 | struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; | |
2868 | uint32_t *data_ptr = *d_ptr; | |
2869 | ||
2870 | rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; | |
2871 | sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); | |
2872 | sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); | |
2873 | sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); | |
2874 | sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); | |
2875 | sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); | |
2876 | read_addr = le32_to_cpu(rdmux2_hdr->read_addr); | |
2877 | ||
2878 | for (i = 0; i < rdmux2_hdr->op_count; i++) { | |
2879 | ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); | |
2880 | t_sel_val = sel_val1 & sel_val_mask; | |
2881 | *data_ptr++ = cpu_to_le32(t_sel_val); | |
2882 | ||
2883 | ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); | |
2884 | ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); | |
2885 | ||
2886 | *data_ptr++ = cpu_to_le32(data); | |
2887 | ||
2888 | ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); | |
2889 | t_sel_val = sel_val2 & sel_val_mask; | |
2890 | *data_ptr++ = cpu_to_le32(t_sel_val); | |
2891 | ||
2892 | ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); | |
2893 | ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); | |
2894 | ||
2895 | *data_ptr++ = cpu_to_le32(data); | |
2896 | ||
2897 | sel_val1 += rdmux2_hdr->select_value_stride; | |
2898 | sel_val2 += rdmux2_hdr->select_value_stride; | |
2899 | } | |
2900 | ||
2901 | *d_ptr = data_ptr; | |
2902 | } | |
2903 | ||
2904 | static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, | |
2905 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2906 | uint32_t **d_ptr) | |
2907 | { | |
2908 | uint32_t poll_wait, poll_mask, r_value, data; | |
2909 | uint32_t addr_1, addr_2, value_1, value_2; | |
2910 | uint32_t *data_ptr = *d_ptr; | |
2911 | uint32_t rval = QLA_SUCCESS; | |
2912 | struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; | |
2913 | ||
2914 | poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; | |
2915 | addr_1 = le32_to_cpu(poll_hdr->addr_1); | |
2916 | addr_2 = le32_to_cpu(poll_hdr->addr_2); | |
2917 | value_1 = le32_to_cpu(poll_hdr->value_1); | |
2918 | value_2 = le32_to_cpu(poll_hdr->value_2); | |
2919 | poll_mask = le32_to_cpu(poll_hdr->poll_mask); | |
2920 | ||
2921 | ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); | |
2922 | ||
2923 | poll_wait = le32_to_cpu(poll_hdr->poll_wait); | |
2924 | while (1) { | |
2925 | ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); | |
2926 | ||
2927 | if ((r_value & poll_mask) != 0) { | |
2928 | break; | |
2929 | } else { | |
2930 | msleep(1); | |
2931 | if (--poll_wait == 0) { | |
2932 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", | |
2933 | __func__); | |
2934 | rval = QLA_ERROR; | |
2935 | goto exit_process_pollrdmwr; | |
2936 | } | |
2937 | } | |
2938 | } | |
2939 | ||
2940 | ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); | |
2941 | data &= le32_to_cpu(poll_hdr->modify_mask); | |
2942 | ha->isp_ops->wr_reg_indirect(ha, addr_2, data); | |
2943 | ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); | |
2944 | ||
2945 | poll_wait = le32_to_cpu(poll_hdr->poll_wait); | |
2946 | while (1) { | |
2947 | ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); | |
2948 | ||
2949 | if ((r_value & poll_mask) != 0) { | |
2950 | break; | |
2951 | } else { | |
2952 | msleep(1); | |
2953 | if (--poll_wait == 0) { | |
2954 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", | |
2955 | __func__); | |
2956 | rval = QLA_ERROR; | |
2957 | goto exit_process_pollrdmwr; | |
2958 | } | |
2959 | } | |
2960 | } | |
2961 | ||
2962 | *data_ptr++ = cpu_to_le32(addr_2); | |
2963 | *data_ptr++ = cpu_to_le32(data); | |
2964 | *d_ptr = data_ptr; | |
2965 | ||
2966 | exit_process_pollrdmwr: | |
2967 | return rval; | |
2968 | } | |
2969 | ||
2970 | static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, | |
2971 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | |
2972 | uint32_t **d_ptr) | |
2973 | { | |
2974 | uint32_t fl_addr, u32_count, rval; | |
2975 | struct qla8xxx_minidump_entry_rdrom *rom_hdr; | |
2976 | uint32_t *data_ptr = *d_ptr; | |
2977 | ||
2978 | rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; | |
2979 | fl_addr = le32_to_cpu(rom_hdr->read_addr); | |
2980 | u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); | |
2981 | ||
2982 | DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", | |
2983 | __func__, fl_addr, u32_count)); | |
2984 | ||
2985 | rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, | |
2986 | (u8 *)(data_ptr), u32_count); | |
2987 | ||
2988 | if (rval == QLA_ERROR) { | |
2989 | ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", | |
2990 | __func__, u32_count); | |
2991 | goto exit_process_rdrom; | |
2992 | } | |
2993 | ||
2994 | data_ptr += u32_count; | |
2995 | *d_ptr = data_ptr; | |
2996 | ||
2997 | exit_process_rdrom: | |
2998 | return rval; | |
2999 | } | |
3000 | ||
068237c8 | 3001 | /** |
f8086f4f | 3002 | * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. |
068237c8 TP |
3003 | * @ha: pointer to adapter structure |
3004 | **/ | |
3005 | static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |
3006 | { | |
3007 | int num_entry_hdr = 0; | |
7664a1fd | 3008 | struct qla8xxx_minidump_entry_hdr *entry_hdr; |
068237c8 TP |
3009 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; |
3010 | uint32_t *data_ptr; | |
3011 | uint32_t data_collected = 0; | |
3012 | int i, rval = QLA_ERROR; | |
3013 | uint64_t now; | |
3014 | uint32_t timestamp; | |
3015 | ||
58e2bbe9 | 3016 | ha->fw_dump_skip_size = 0; |
068237c8 TP |
3017 | if (!ha->fw_dump) { |
3018 | ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", | |
3019 | __func__, ha->host_no); | |
3020 | return rval; | |
3021 | } | |
3022 | ||
3023 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) | |
3024 | ha->fw_dump_tmplt_hdr; | |
3025 | data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + | |
3026 | ha->fw_dump_tmplt_size); | |
3027 | data_collected += ha->fw_dump_tmplt_size; | |
3028 | ||
3029 | num_entry_hdr = tmplt_hdr->num_of_entries; | |
3030 | ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", | |
3031 | __func__, data_ptr); | |
3032 | ql4_printk(KERN_INFO, ha, | |
3033 | "[%s]: no of entry headers in Template: 0x%x\n", | |
3034 | __func__, num_entry_hdr); | |
3035 | ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", | |
3036 | __func__, ha->fw_dump_capture_mask); | |
3037 | ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", | |
3038 | __func__, ha->fw_dump_size, ha->fw_dump_size); | |
3039 | ||
3040 | /* Update current timestamp before taking dump */ | |
3041 | now = get_jiffies_64(); | |
3042 | timestamp = (u32)(jiffies_to_msecs(now) / 1000); | |
3043 | tmplt_hdr->driver_timestamp = timestamp; | |
3044 | ||
7664a1fd | 3045 | entry_hdr = (struct qla8xxx_minidump_entry_hdr *) |
068237c8 TP |
3046 | (((uint8_t *)ha->fw_dump_tmplt_hdr) + |
3047 | tmplt_hdr->first_entry_offset); | |
3048 | ||
b37ca418 | 3049 | if (is_qla8032(ha) || is_qla8042(ha)) |
6e7b4292 VC |
3050 | tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = |
3051 | tmplt_hdr->ocm_window_reg[ha->func_num]; | |
3052 | ||
068237c8 TP |
3053 | /* Walk through the entry headers - validate/perform required action */ |
3054 | for (i = 0; i < num_entry_hdr; i++) { | |
4812d070 | 3055 | if (data_collected > ha->fw_dump_size) { |
068237c8 TP |
3056 | ql4_printk(KERN_INFO, ha, |
3057 | "Data collected: [0x%x], Total Dump size: [0x%x]\n", | |
3058 | data_collected, ha->fw_dump_size); | |
3059 | return rval; | |
3060 | } | |
3061 | ||
3062 | if (!(entry_hdr->d_ctrl.entry_capture_mask & | |
3063 | ha->fw_dump_capture_mask)) { | |
3064 | entry_hdr->d_ctrl.driver_flags |= | |
de8c72da | 3065 | QLA8XXX_DBG_SKIPPED_FLAG; |
068237c8 TP |
3066 | goto skip_nxt_entry; |
3067 | } | |
3068 | ||
3069 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
3070 | "Data collected: [0x%x], Dump size left:[0x%x]\n", | |
3071 | data_collected, | |
3072 | (ha->fw_dump_size - data_collected))); | |
3073 | ||
3074 | /* Decode the entry type and take required action to capture | |
3075 | * debug data | |
3076 | */ | |
3077 | switch (entry_hdr->entry_type) { | |
de8c72da | 3078 | case QLA8XXX_RDEND: |
5e9bcec7 | 3079 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
068237c8 | 3080 | break; |
de8c72da | 3081 | case QLA8XXX_CNTRL: |
068237c8 TP |
3082 | rval = qla4_8xxx_minidump_process_control(ha, |
3083 | entry_hdr); | |
3084 | if (rval != QLA_SUCCESS) { | |
5e9bcec7 | 3085 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
068237c8 TP |
3086 | goto md_failed; |
3087 | } | |
3088 | break; | |
de8c72da | 3089 | case QLA8XXX_RDCRB: |
068237c8 TP |
3090 | qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, |
3091 | &data_ptr); | |
3092 | break; | |
de8c72da | 3093 | case QLA8XXX_RDMEM: |
068237c8 TP |
3094 | rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, |
3095 | &data_ptr); | |
3096 | if (rval != QLA_SUCCESS) { | |
5e9bcec7 | 3097 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
068237c8 TP |
3098 | goto md_failed; |
3099 | } | |
3100 | break; | |
de8c72da VC |
3101 | case QLA8XXX_BOARD: |
3102 | case QLA8XXX_RDROM: | |
6e7b4292 VC |
3103 | if (is_qla8022(ha)) { |
3104 | qla4_82xx_minidump_process_rdrom(ha, entry_hdr, | |
3105 | &data_ptr); | |
b37ca418 | 3106 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3107 | rval = qla4_83xx_minidump_process_rdrom(ha, |
3108 | entry_hdr, | |
3109 | &data_ptr); | |
3110 | if (rval != QLA_SUCCESS) | |
3111 | qla4_8xxx_mark_entry_skipped(ha, | |
3112 | entry_hdr, | |
3113 | i); | |
3114 | } | |
068237c8 | 3115 | break; |
de8c72da VC |
3116 | case QLA8XXX_L2DTG: |
3117 | case QLA8XXX_L2ITG: | |
3118 | case QLA8XXX_L2DAT: | |
3119 | case QLA8XXX_L2INS: | |
068237c8 TP |
3120 | rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, |
3121 | &data_ptr); | |
3122 | if (rval != QLA_SUCCESS) { | |
5e9bcec7 | 3123 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
068237c8 TP |
3124 | goto md_failed; |
3125 | } | |
3126 | break; | |
6e7b4292 VC |
3127 | case QLA8XXX_L1DTG: |
3128 | case QLA8XXX_L1ITG: | |
de8c72da VC |
3129 | case QLA8XXX_L1DAT: |
3130 | case QLA8XXX_L1INS: | |
068237c8 TP |
3131 | qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, |
3132 | &data_ptr); | |
3133 | break; | |
de8c72da | 3134 | case QLA8XXX_RDOCM: |
068237c8 TP |
3135 | qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, |
3136 | &data_ptr); | |
3137 | break; | |
de8c72da | 3138 | case QLA8XXX_RDMUX: |
068237c8 TP |
3139 | qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, |
3140 | &data_ptr); | |
3141 | break; | |
de8c72da | 3142 | case QLA8XXX_QUEUE: |
068237c8 TP |
3143 | qla4_8xxx_minidump_process_queue(ha, entry_hdr, |
3144 | &data_ptr); | |
3145 | break; | |
6e7b4292 | 3146 | case QLA83XX_POLLRD: |
b37ca418 | 3147 | if (is_qla8022(ha)) { |
6e7b4292 VC |
3148 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
3149 | break; | |
3150 | } | |
3151 | rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, | |
3152 | &data_ptr); | |
3153 | if (rval != QLA_SUCCESS) | |
3154 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | |
3155 | break; | |
3156 | case QLA83XX_RDMUX2: | |
b37ca418 | 3157 | if (is_qla8022(ha)) { |
6e7b4292 VC |
3158 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
3159 | break; | |
3160 | } | |
3161 | qla83xx_minidump_process_rdmux2(ha, entry_hdr, | |
3162 | &data_ptr); | |
3163 | break; | |
3164 | case QLA83XX_POLLRDMWR: | |
b37ca418 | 3165 | if (is_qla8022(ha)) { |
6e7b4292 VC |
3166 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
3167 | break; | |
3168 | } | |
3169 | rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, | |
3170 | &data_ptr); | |
3171 | if (rval != QLA_SUCCESS) | |
3172 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | |
3173 | break; | |
b1829789 TP |
3174 | case QLA8044_RDDFE: |
3175 | rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr, | |
3176 | &data_ptr); | |
3177 | if (rval != QLA_SUCCESS) | |
3178 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | |
3179 | break; | |
3180 | case QLA8044_RDMDIO: | |
3181 | rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr, | |
3182 | &data_ptr); | |
3183 | if (rval != QLA_SUCCESS) | |
3184 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | |
3185 | break; | |
3186 | case QLA8044_POLLWR: | |
3187 | rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr, | |
3188 | &data_ptr); | |
3189 | if (rval != QLA_SUCCESS) | |
3190 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | |
3191 | break; | |
de8c72da | 3192 | case QLA8XXX_RDNOP: |
068237c8 | 3193 | default: |
5e9bcec7 | 3194 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
068237c8 TP |
3195 | break; |
3196 | } | |
3197 | ||
4812d070 | 3198 | data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump; |
068237c8 TP |
3199 | skip_nxt_entry: |
3200 | /* next entry in the template */ | |
7664a1fd | 3201 | entry_hdr = (struct qla8xxx_minidump_entry_hdr *) |
068237c8 TP |
3202 | (((uint8_t *)entry_hdr) + |
3203 | entry_hdr->entry_size); | |
3204 | } | |
3205 | ||
58e2bbe9 | 3206 | if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) { |
068237c8 TP |
3207 | ql4_printk(KERN_INFO, ha, |
3208 | "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", | |
3209 | data_collected, ha->fw_dump_size); | |
35a9c2ab | 3210 | rval = QLA_ERROR; |
068237c8 TP |
3211 | goto md_failed; |
3212 | } | |
3213 | ||
3214 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", | |
3215 | __func__, i)); | |
3216 | md_failed: | |
3217 | return rval; | |
3218 | } | |
3219 | ||
3220 | /** | |
3221 | * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. | |
3222 | * @ha: pointer to adapter structure | |
3223 | **/ | |
3224 | static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) | |
3225 | { | |
3226 | char event_string[40]; | |
3227 | char *envp[] = { event_string, NULL }; | |
3228 | ||
3229 | switch (code) { | |
3230 | case QL4_UEVENT_CODE_FW_DUMP: | |
3231 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
3232 | ha->host_no); | |
3233 | break; | |
3234 | default: | |
3235 | /*do nothing*/ | |
3236 | break; | |
3237 | } | |
3238 | ||
3239 | kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); | |
3240 | } | |
3241 | ||
6e7b4292 | 3242 | void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) |
aec07cae VC |
3243 | { |
3244 | if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && | |
3245 | !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { | |
3246 | if (!qla4_8xxx_collect_md_data(ha)) { | |
3247 | qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); | |
3248 | set_bit(AF_82XX_FW_DUMPED, &ha->flags); | |
3249 | } else { | |
3250 | ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", | |
3251 | __func__); | |
3252 | } | |
3253 | } | |
3254 | } | |
3255 | ||
f4f5df23 VC |
3256 | /** |
3257 | * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw | |
3258 | * @ha: pointer to adapter structure | |
3259 | * | |
3260 | * Note: IDC lock must be held upon entry | |
3261 | **/ | |
6e7b4292 | 3262 | int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) |
f4f5df23 | 3263 | { |
b25ee66f | 3264 | int rval = QLA_ERROR; |
32436aaa | 3265 | int i; |
80645dc0 | 3266 | uint32_t old_count, count; |
4ebbb5cf | 3267 | int need_reset = 0; |
f4f5df23 | 3268 | |
33693c7a | 3269 | need_reset = ha->isp_ops->need_reset(ha); |
b25ee66f SS |
3270 | |
3271 | if (need_reset) { | |
3272 | /* We are trying to perform a recovery here. */ | |
4ebbb5cf | 3273 | if (test_bit(AF_FW_RECOVERY, &ha->flags)) |
33693c7a | 3274 | ha->isp_ops->rom_lock_recovery(ha); |
b25ee66f | 3275 | } else { |
4ebbb5cf VC |
3276 | old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); |
3277 | for (i = 0; i < 10; i++) { | |
3278 | msleep(200); | |
3279 | count = qla4_8xxx_rd_direct(ha, | |
3280 | QLA8XXX_PEG_ALIVE_COUNTER); | |
3281 | if (count != old_count) { | |
3282 | rval = QLA_SUCCESS; | |
3283 | goto dev_ready; | |
3284 | } | |
b25ee66f | 3285 | } |
4ebbb5cf | 3286 | ha->isp_ops->rom_lock_recovery(ha); |
f4f5df23 VC |
3287 | } |
3288 | ||
f4f5df23 VC |
3289 | /* set to DEV_INITIALIZING */ |
3290 | ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); | |
33693c7a VC |
3291 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
3292 | QLA8XXX_DEV_INITIALIZING); | |
f4f5df23 | 3293 | |
33693c7a | 3294 | ha->isp_ops->idc_unlock(ha); |
6e7b4292 VC |
3295 | |
3296 | if (is_qla8022(ha)) | |
3297 | qla4_8xxx_get_minidump(ha); | |
3298 | ||
33693c7a VC |
3299 | rval = ha->isp_ops->restart_firmware(ha); |
3300 | ha->isp_ops->idc_lock(ha); | |
f4f5df23 VC |
3301 | |
3302 | if (rval != QLA_SUCCESS) { | |
3303 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); | |
3304 | qla4_8xxx_clear_drv_active(ha); | |
33693c7a VC |
3305 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
3306 | QLA8XXX_DEV_FAILED); | |
f4f5df23 VC |
3307 | return rval; |
3308 | } | |
3309 | ||
3310 | dev_ready: | |
3311 | ql4_printk(KERN_INFO, ha, "HW State: READY\n"); | |
33693c7a | 3312 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); |
f4f5df23 | 3313 | |
b25ee66f | 3314 | return rval; |
f4f5df23 VC |
3315 | } |
3316 | ||
3317 | /** | |
f8086f4f | 3318 | * qla4_82xx_need_reset_handler - Code to start reset sequence |
f4f5df23 VC |
3319 | * @ha: pointer to adapter structure |
3320 | * | |
3321 | * Note: IDC lock must be held upon entry | |
3322 | **/ | |
3323 | static void | |
f8086f4f | 3324 | qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) |
f4f5df23 VC |
3325 | { |
3326 | uint32_t dev_state, drv_state, drv_active; | |
068237c8 | 3327 | uint32_t active_mask = 0xFFFFFFFF; |
f4f5df23 VC |
3328 | unsigned long reset_timeout; |
3329 | ||
3330 | ql4_printk(KERN_INFO, ha, | |
3331 | "Performing ISP error recovery\n"); | |
3332 | ||
3333 | if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { | |
f8086f4f | 3334 | qla4_82xx_idc_unlock(ha); |
f4f5df23 | 3335 | ha->isp_ops->disable_intrs(ha); |
f8086f4f | 3336 | qla4_82xx_idc_lock(ha); |
f4f5df23 VC |
3337 | } |
3338 | ||
de8c72da | 3339 | if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
068237c8 TP |
3340 | DEBUG2(ql4_printk(KERN_INFO, ha, |
3341 | "%s(%ld): reset acknowledged\n", | |
3342 | __func__, ha->host_no)); | |
3343 | qla4_8xxx_set_rst_ready(ha); | |
3344 | } else { | |
3345 | active_mask = (~(1 << (ha->func_num * 4))); | |
3346 | } | |
f4f5df23 VC |
3347 | |
3348 | /* wait for 10 seconds for reset ack from all functions */ | |
3349 | reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); | |
3350 | ||
f8086f4f VC |
3351 | drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); |
3352 | drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
f4f5df23 VC |
3353 | |
3354 | ql4_printk(KERN_INFO, ha, | |
3355 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", | |
3356 | __func__, ha->host_no, drv_state, drv_active); | |
3357 | ||
068237c8 | 3358 | while (drv_state != (drv_active & active_mask)) { |
f4f5df23 | 3359 | if (time_after_eq(jiffies, reset_timeout)) { |
068237c8 TP |
3360 | ql4_printk(KERN_INFO, ha, |
3361 | "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", | |
3362 | DRIVER_NAME, drv_state, drv_active); | |
f4f5df23 VC |
3363 | break; |
3364 | } | |
3365 | ||
068237c8 TP |
3366 | /* |
3367 | * When reset_owner times out, check which functions | |
3368 | * acked/did not ack | |
3369 | */ | |
de8c72da | 3370 | if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
068237c8 TP |
3371 | ql4_printk(KERN_INFO, ha, |
3372 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", | |
3373 | __func__, ha->host_no, drv_state, | |
3374 | drv_active); | |
3375 | } | |
f8086f4f | 3376 | qla4_82xx_idc_unlock(ha); |
f4f5df23 | 3377 | msleep(1000); |
f8086f4f | 3378 | qla4_82xx_idc_lock(ha); |
f4f5df23 | 3379 | |
f8086f4f VC |
3380 | drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); |
3381 | drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
f4f5df23 VC |
3382 | } |
3383 | ||
068237c8 | 3384 | /* Clear RESET OWNER as we are not going to use it any further */ |
de8c72da | 3385 | clear_bit(AF_8XXX_RST_OWNER, &ha->flags); |
068237c8 | 3386 | |
f8086f4f | 3387 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
068237c8 TP |
3388 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, |
3389 | dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); | |
f4f5df23 VC |
3390 | |
3391 | /* Force to DEV_COLD unless someone else is starting a reset */ | |
de8c72da | 3392 | if (dev_state != QLA8XXX_DEV_INITIALIZING) { |
f4f5df23 | 3393 | ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); |
de8c72da | 3394 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); |
068237c8 | 3395 | qla4_8xxx_set_rst_ready(ha); |
f4f5df23 VC |
3396 | } |
3397 | } | |
3398 | ||
3399 | /** | |
3400 | * qla4_8xxx_need_qsnt_handler - Code to start qsnt | |
3401 | * @ha: pointer to adapter structure | |
3402 | **/ | |
3403 | void | |
3404 | qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) | |
3405 | { | |
33693c7a | 3406 | ha->isp_ops->idc_lock(ha); |
f4f5df23 | 3407 | qla4_8xxx_set_qsnt_ready(ha); |
33693c7a | 3408 | ha->isp_ops->idc_unlock(ha); |
f4f5df23 VC |
3409 | } |
3410 | ||
83dbdf6f VC |
3411 | static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) |
3412 | { | |
3413 | int idc_ver; | |
3414 | uint32_t drv_active; | |
3415 | ||
3416 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); | |
3417 | if (drv_active == (1 << (ha->func_num * 4))) { | |
3418 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, | |
3419 | QLA82XX_IDC_VERSION); | |
3420 | ql4_printk(KERN_INFO, ha, | |
3421 | "%s: IDC version updated to %d\n", __func__, | |
3422 | QLA82XX_IDC_VERSION); | |
3423 | } else { | |
3424 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); | |
3425 | if (QLA82XX_IDC_VERSION != idc_ver) { | |
3426 | ql4_printk(KERN_INFO, ha, | |
3427 | "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", | |
3428 | __func__, QLA82XX_IDC_VERSION, idc_ver); | |
3429 | } | |
3430 | } | |
3431 | } | |
3432 | ||
6e7b4292 | 3433 | static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) |
83dbdf6f | 3434 | { |
6e7b4292 VC |
3435 | int idc_ver; |
3436 | uint32_t drv_active; | |
3437 | int rval = QLA_SUCCESS; | |
3438 | ||
3439 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); | |
3440 | if (drv_active == (1 << ha->func_num)) { | |
3441 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); | |
3442 | idc_ver &= (~0xFF); | |
3443 | idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; | |
3444 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); | |
3445 | ql4_printk(KERN_INFO, ha, | |
3446 | "%s: IDC version updated to %d\n", __func__, | |
ecca5120 | 3447 | idc_ver); |
6e7b4292 VC |
3448 | } else { |
3449 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); | |
3450 | idc_ver &= 0xFF; | |
3451 | if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { | |
3452 | ql4_printk(KERN_INFO, ha, | |
3453 | "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", | |
3454 | __func__, QLA83XX_IDC_VER_MAJ_VALUE, | |
3455 | idc_ver); | |
3456 | rval = QLA_ERROR; | |
3457 | goto exit_set_idc_ver; | |
3458 | } | |
3459 | } | |
3460 | ||
3461 | /* Update IDC_MINOR_VERSION */ | |
3462 | idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); | |
3463 | idc_ver &= ~(0x03 << (ha->func_num * 2)); | |
3464 | idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); | |
3465 | qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); | |
3466 | ||
3467 | exit_set_idc_ver: | |
3468 | return rval; | |
3469 | } | |
3470 | ||
39c95826 | 3471 | int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) |
6e7b4292 VC |
3472 | { |
3473 | uint32_t drv_active; | |
3474 | int rval = QLA_SUCCESS; | |
3475 | ||
3476 | if (test_bit(AF_INIT_DONE, &ha->flags)) | |
3477 | goto exit_update_idc_reg; | |
3478 | ||
3479 | ha->isp_ops->idc_lock(ha); | |
3480 | qla4_8xxx_set_drv_active(ha); | |
3481 | ||
3482 | /* | |
3483 | * If we are the first driver to load and | |
3484 | * ql4xdontresethba is not set, clear IDC_CTRL BIT0. | |
3485 | */ | |
b37ca418 | 3486 | if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3487 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
3488 | if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) | |
3489 | qla4_83xx_clear_idc_dontreset(ha); | |
3490 | } | |
3491 | ||
3492 | if (is_qla8022(ha)) { | |
83dbdf6f | 3493 | qla4_82xx_set_idc_ver(ha); |
b37ca418 | 3494 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3495 | rval = qla4_83xx_set_idc_ver(ha); |
3496 | if (rval == QLA_ERROR) | |
3497 | qla4_8xxx_clear_drv_active(ha); | |
83dbdf6f | 3498 | } |
6e7b4292 VC |
3499 | |
3500 | ha->isp_ops->idc_unlock(ha); | |
3501 | ||
3502 | exit_update_idc_reg: | |
3503 | return rval; | |
f4f5df23 VC |
3504 | } |
3505 | ||
3506 | /** | |
3507 | * qla4_8xxx_device_state_handler - Adapter state machine | |
3508 | * @ha: pointer to host adapter structure. | |
3509 | * | |
3510 | * Note: IDC lock must be UNLOCKED upon entry | |
3511 | **/ | |
3512 | int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) | |
3513 | { | |
3514 | uint32_t dev_state; | |
3515 | int rval = QLA_SUCCESS; | |
3516 | unsigned long dev_init_timeout; | |
3517 | ||
6e7b4292 VC |
3518 | rval = qla4_8xxx_update_idc_reg(ha); |
3519 | if (rval == QLA_ERROR) | |
3520 | goto exit_state_handler; | |
f4f5df23 | 3521 | |
33693c7a | 3522 | dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); |
068237c8 TP |
3523 | DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", |
3524 | dev_state, dev_state < MAX_STATES ? | |
3525 | qdev_state[dev_state] : "Unknown")); | |
f4f5df23 VC |
3526 | |
3527 | /* wait for 30 seconds for device to go ready */ | |
3528 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); | |
3529 | ||
33693c7a | 3530 | ha->isp_ops->idc_lock(ha); |
f4f5df23 | 3531 | while (1) { |
f4f5df23 VC |
3532 | |
3533 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
068237c8 TP |
3534 | ql4_printk(KERN_WARNING, ha, |
3535 | "%s: Device Init Failed 0x%x = %s\n", | |
3536 | DRIVER_NAME, | |
3537 | dev_state, dev_state < MAX_STATES ? | |
3538 | qdev_state[dev_state] : "Unknown"); | |
33693c7a VC |
3539 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
3540 | QLA8XXX_DEV_FAILED); | |
f4f5df23 VC |
3541 | } |
3542 | ||
33693c7a | 3543 | dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); |
068237c8 TP |
3544 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", |
3545 | dev_state, dev_state < MAX_STATES ? | |
3546 | qdev_state[dev_state] : "Unknown"); | |
f4f5df23 VC |
3547 | |
3548 | /* NOTE: Make sure idc unlocked upon exit of switch statement */ | |
3549 | switch (dev_state) { | |
de8c72da | 3550 | case QLA8XXX_DEV_READY: |
f4f5df23 | 3551 | goto exit; |
de8c72da | 3552 | case QLA8XXX_DEV_COLD: |
f4f5df23 | 3553 | rval = qla4_8xxx_device_bootstrap(ha); |
f4f5df23 | 3554 | goto exit; |
de8c72da | 3555 | case QLA8XXX_DEV_INITIALIZING: |
33693c7a | 3556 | ha->isp_ops->idc_unlock(ha); |
f4f5df23 | 3557 | msleep(1000); |
33693c7a | 3558 | ha->isp_ops->idc_lock(ha); |
f4f5df23 | 3559 | break; |
de8c72da | 3560 | case QLA8XXX_DEV_NEED_RESET: |
6e7b4292 | 3561 | /* |
b37ca418 VC |
3562 | * For ISP8324 and ISP8042, if NEED_RESET is set by any |
3563 | * driver, it should be honored, irrespective of | |
3564 | * IDC_CTRL DONTRESET_BIT0 | |
6e7b4292 | 3565 | */ |
b37ca418 | 3566 | if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3567 | qla4_83xx_need_reset_handler(ha); |
3568 | } else if (is_qla8022(ha)) { | |
3569 | if (!ql4xdontresethba) { | |
3570 | qla4_82xx_need_reset_handler(ha); | |
3571 | /* Update timeout value after need | |
3572 | * reset handler */ | |
3573 | dev_init_timeout = jiffies + | |
3574 | (ha->nx_dev_init_timeout * HZ); | |
3575 | } else { | |
3576 | ha->isp_ops->idc_unlock(ha); | |
3577 | msleep(1000); | |
3578 | ha->isp_ops->idc_lock(ha); | |
3579 | } | |
f4f5df23 | 3580 | } |
f4f5df23 | 3581 | break; |
de8c72da | 3582 | case QLA8XXX_DEV_NEED_QUIESCENT: |
f4f5df23 VC |
3583 | /* idc locked/unlocked in handler */ |
3584 | qla4_8xxx_need_qsnt_handler(ha); | |
e3f37d16 | 3585 | break; |
de8c72da | 3586 | case QLA8XXX_DEV_QUIESCENT: |
33693c7a | 3587 | ha->isp_ops->idc_unlock(ha); |
f4f5df23 | 3588 | msleep(1000); |
33693c7a | 3589 | ha->isp_ops->idc_lock(ha); |
f4f5df23 | 3590 | break; |
de8c72da | 3591 | case QLA8XXX_DEV_FAILED: |
33693c7a | 3592 | ha->isp_ops->idc_unlock(ha); |
f4f5df23 VC |
3593 | qla4xxx_dead_adapter_cleanup(ha); |
3594 | rval = QLA_ERROR; | |
33693c7a | 3595 | ha->isp_ops->idc_lock(ha); |
f4f5df23 VC |
3596 | goto exit; |
3597 | default: | |
33693c7a | 3598 | ha->isp_ops->idc_unlock(ha); |
f4f5df23 VC |
3599 | qla4xxx_dead_adapter_cleanup(ha); |
3600 | rval = QLA_ERROR; | |
33693c7a | 3601 | ha->isp_ops->idc_lock(ha); |
f4f5df23 VC |
3602 | goto exit; |
3603 | } | |
3604 | } | |
3605 | exit: | |
33693c7a | 3606 | ha->isp_ops->idc_unlock(ha); |
6e7b4292 | 3607 | exit_state_handler: |
f4f5df23 VC |
3608 | return rval; |
3609 | } | |
3610 | ||
3611 | int qla4_8xxx_load_risc(struct scsi_qla_host *ha) | |
3612 | { | |
3613 | int retval; | |
78764999 SR |
3614 | |
3615 | /* clear the interrupt */ | |
b37ca418 | 3616 | if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3617 | writel(0, &ha->qla4_83xx_reg->risc_intr); |
3618 | readl(&ha->qla4_83xx_reg->risc_intr); | |
3619 | } else if (is_qla8022(ha)) { | |
3620 | writel(0, &ha->qla4_82xx_reg->host_int); | |
3621 | readl(&ha->qla4_82xx_reg->host_int); | |
3622 | } | |
78764999 | 3623 | |
f4f5df23 VC |
3624 | retval = qla4_8xxx_device_state_handler(ha); |
3625 | ||
1b3d399c TP |
3626 | /* Initialize request and response queues. */ |
3627 | if (retval == QLA_SUCCESS) | |
3628 | qla4xxx_init_rings(ha); | |
3629 | ||
137257da | 3630 | if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags)) |
f4f5df23 | 3631 | retval = qla4xxx_request_irqs(ha); |
f581a3f7 | 3632 | |
f4f5df23 VC |
3633 | return retval; |
3634 | } | |
3635 | ||
3636 | /*****************************************************************************/ | |
3637 | /* Flash Manipulation Routines */ | |
3638 | /*****************************************************************************/ | |
3639 | ||
3640 | #define OPTROM_BURST_SIZE 0x1000 | |
3641 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | |
3642 | ||
3643 | #define FARX_DATA_FLAG BIT_31 | |
3644 | #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 | |
3645 | #define FARX_ACCESS_FLASH_DATA 0x7FF00000 | |
3646 | ||
3647 | static inline uint32_t | |
3648 | flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) | |
3649 | { | |
3650 | return hw->flash_conf_off | faddr; | |
3651 | } | |
3652 | ||
3653 | static inline uint32_t | |
3654 | flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) | |
3655 | { | |
3656 | return hw->flash_data_off | faddr; | |
3657 | } | |
3658 | ||
3659 | static uint32_t * | |
f8086f4f | 3660 | qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, |
f4f5df23 VC |
3661 | uint32_t faddr, uint32_t length) |
3662 | { | |
3663 | uint32_t i; | |
3664 | uint32_t val; | |
3665 | int loops = 0; | |
f8086f4f | 3666 | while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { |
f4f5df23 VC |
3667 | udelay(100); |
3668 | cond_resched(); | |
3669 | loops++; | |
3670 | } | |
3671 | if (loops >= 50000) { | |
3672 | ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); | |
3673 | return dwptr; | |
3674 | } | |
3675 | ||
3676 | /* Dword reads to flash. */ | |
3677 | for (i = 0; i < length/4; i++, faddr += 4) { | |
f8086f4f | 3678 | if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { |
f4f5df23 VC |
3679 | ql4_printk(KERN_WARNING, ha, |
3680 | "Do ROM fast read failed\n"); | |
3681 | goto done_read; | |
3682 | } | |
3683 | dwptr[i] = __constant_cpu_to_le32(val); | |
3684 | } | |
3685 | ||
3686 | done_read: | |
f8086f4f | 3687 | qla4_82xx_rom_unlock(ha); |
f4f5df23 VC |
3688 | return dwptr; |
3689 | } | |
3690 | ||
3691 | /** | |
3692 | * Address and length are byte address | |
3693 | **/ | |
3694 | static uint8_t * | |
f8086f4f | 3695 | qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, |
f4f5df23 VC |
3696 | uint32_t offset, uint32_t length) |
3697 | { | |
f8086f4f | 3698 | qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); |
f4f5df23 VC |
3699 | return buf; |
3700 | } | |
3701 | ||
3702 | static int | |
3703 | qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) | |
3704 | { | |
3705 | const char *loc, *locations[] = { "DEF", "PCI" }; | |
3706 | ||
3707 | /* | |
3708 | * FLT-location structure resides after the last PCI region. | |
3709 | */ | |
3710 | ||
3711 | /* Begin with sane defaults. */ | |
3712 | loc = locations[0]; | |
3713 | *start = FA_FLASH_LAYOUT_ADDR_82; | |
3714 | ||
3715 | DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); | |
3716 | return QLA_SUCCESS; | |
3717 | } | |
3718 | ||
3719 | static void | |
3720 | qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) | |
3721 | { | |
3722 | const char *loc, *locations[] = { "DEF", "FLT" }; | |
3723 | uint16_t *wptr; | |
3724 | uint16_t cnt, chksum; | |
6e7b4292 | 3725 | uint32_t start, status; |
f4f5df23 VC |
3726 | struct qla_flt_header *flt; |
3727 | struct qla_flt_region *region; | |
3728 | struct ql82xx_hw_data *hw = &ha->hw; | |
3729 | ||
3730 | hw->flt_region_flt = flt_addr; | |
3731 | wptr = (uint16_t *)ha->request_ring; | |
3732 | flt = (struct qla_flt_header *)ha->request_ring; | |
3733 | region = (struct qla_flt_region *)&flt[1]; | |
6e7b4292 VC |
3734 | |
3735 | if (is_qla8022(ha)) { | |
3736 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, | |
3737 | flt_addr << 2, OPTROM_BURST_SIZE); | |
b37ca418 | 3738 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3739 | status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, |
3740 | (uint8_t *)ha->request_ring, | |
3741 | 0x400); | |
3742 | if (status != QLA_SUCCESS) | |
3743 | goto no_flash_data; | |
3744 | } | |
3745 | ||
f4f5df23 VC |
3746 | if (*wptr == __constant_cpu_to_le16(0xffff)) |
3747 | goto no_flash_data; | |
3748 | if (flt->version != __constant_cpu_to_le16(1)) { | |
3749 | DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " | |
3750 | "version=0x%x length=0x%x checksum=0x%x.\n", | |
3751 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), | |
3752 | le16_to_cpu(flt->checksum))); | |
3753 | goto no_flash_data; | |
3754 | } | |
3755 | ||
3756 | cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; | |
3757 | for (chksum = 0; cnt; cnt--) | |
3758 | chksum += le16_to_cpu(*wptr++); | |
3759 | if (chksum) { | |
3760 | DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " | |
3761 | "version=0x%x length=0x%x checksum=0x%x.\n", | |
3762 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), | |
3763 | chksum)); | |
3764 | goto no_flash_data; | |
3765 | } | |
3766 | ||
3767 | loc = locations[1]; | |
3768 | cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); | |
3769 | for ( ; cnt; cnt--, region++) { | |
3770 | /* Store addresses as DWORD offsets. */ | |
3771 | start = le32_to_cpu(region->start) >> 2; | |
3772 | ||
3773 | DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " | |
3774 | "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, | |
3775 | le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); | |
3776 | ||
3777 | switch (le32_to_cpu(region->code) & 0xff) { | |
3778 | case FLT_REG_FDT: | |
3779 | hw->flt_region_fdt = start; | |
3780 | break; | |
3781 | case FLT_REG_BOOT_CODE_82: | |
3782 | hw->flt_region_boot = start; | |
3783 | break; | |
3784 | case FLT_REG_FW_82: | |
93823956 | 3785 | case FLT_REG_FW_82_1: |
f4f5df23 VC |
3786 | hw->flt_region_fw = start; |
3787 | break; | |
3788 | case FLT_REG_BOOTLOAD_82: | |
3789 | hw->flt_region_bootload = start; | |
3790 | break; | |
2a991c21 MR |
3791 | case FLT_REG_ISCSI_PARAM: |
3792 | hw->flt_iscsi_param = start; | |
3793 | break; | |
4549415a LC |
3794 | case FLT_REG_ISCSI_CHAP: |
3795 | hw->flt_region_chap = start; | |
3796 | hw->flt_chap_size = le32_to_cpu(region->size); | |
3797 | break; | |
1e9e2be3 AC |
3798 | case FLT_REG_ISCSI_DDB: |
3799 | hw->flt_region_ddb = start; | |
3800 | hw->flt_ddb_size = le32_to_cpu(region->size); | |
3801 | break; | |
f4f5df23 VC |
3802 | } |
3803 | } | |
3804 | goto done; | |
3805 | ||
3806 | no_flash_data: | |
3807 | /* Use hardcoded defaults. */ | |
3808 | loc = locations[0]; | |
3809 | ||
3810 | hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; | |
3811 | hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; | |
3812 | hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; | |
3813 | hw->flt_region_fw = FA_RISC_CODE_ADDR_82; | |
9a16f65b | 3814 | hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2; |
4549415a | 3815 | hw->flt_chap_size = FA_FLASH_CHAP_SIZE; |
1e9e2be3 AC |
3816 | hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2; |
3817 | hw->flt_ddb_size = FA_FLASH_DDB_SIZE; | |
4549415a | 3818 | |
f4f5df23 | 3819 | done: |
9a16f65b | 3820 | DEBUG2(ql4_printk(KERN_INFO, ha, |
1e9e2be3 | 3821 | "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n", |
9a16f65b VC |
3822 | loc, hw->flt_region_flt, hw->flt_region_fdt, |
3823 | hw->flt_region_boot, hw->flt_region_bootload, | |
1e9e2be3 AC |
3824 | hw->flt_region_fw, hw->flt_region_chap, |
3825 | hw->flt_chap_size, hw->flt_region_ddb, | |
3826 | hw->flt_ddb_size)); | |
f4f5df23 VC |
3827 | } |
3828 | ||
3829 | static void | |
f8086f4f | 3830 | qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) |
f4f5df23 VC |
3831 | { |
3832 | #define FLASH_BLK_SIZE_4K 0x1000 | |
3833 | #define FLASH_BLK_SIZE_32K 0x8000 | |
3834 | #define FLASH_BLK_SIZE_64K 0x10000 | |
3835 | const char *loc, *locations[] = { "MID", "FDT" }; | |
3836 | uint16_t cnt, chksum; | |
3837 | uint16_t *wptr; | |
3838 | struct qla_fdt_layout *fdt; | |
3c3e2108 VC |
3839 | uint16_t mid = 0; |
3840 | uint16_t fid = 0; | |
f4f5df23 VC |
3841 | struct ql82xx_hw_data *hw = &ha->hw; |
3842 | ||
3843 | hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
3844 | hw->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
3845 | ||
3846 | wptr = (uint16_t *)ha->request_ring; | |
3847 | fdt = (struct qla_fdt_layout *)ha->request_ring; | |
f8086f4f | 3848 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, |
f4f5df23 VC |
3849 | hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); |
3850 | ||
3851 | if (*wptr == __constant_cpu_to_le16(0xffff)) | |
3852 | goto no_flash_data; | |
3853 | ||
3854 | if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || | |
3855 | fdt->sig[3] != 'D') | |
3856 | goto no_flash_data; | |
3857 | ||
3858 | for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; | |
3859 | cnt++) | |
3860 | chksum += le16_to_cpu(*wptr++); | |
3861 | ||
3862 | if (chksum) { | |
3863 | DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " | |
3864 | "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], | |
3865 | le16_to_cpu(fdt->version))); | |
3866 | goto no_flash_data; | |
3867 | } | |
3868 | ||
3869 | loc = locations[1]; | |
3870 | mid = le16_to_cpu(fdt->man_id); | |
3871 | fid = le16_to_cpu(fdt->id); | |
3872 | hw->fdt_wrt_disable = fdt->wrt_disable_bits; | |
3873 | hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); | |
3874 | hw->fdt_block_size = le32_to_cpu(fdt->block_size); | |
3875 | ||
3876 | if (fdt->unprotect_sec_cmd) { | |
3877 | hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | | |
3878 | fdt->unprotect_sec_cmd); | |
3879 | hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? | |
3880 | flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : | |
3881 | flash_conf_addr(hw, 0x0336); | |
3882 | } | |
3883 | goto done; | |
3884 | ||
3885 | no_flash_data: | |
3886 | loc = locations[0]; | |
3887 | hw->fdt_block_size = FLASH_BLK_SIZE_64K; | |
3888 | done: | |
3889 | DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " | |
3890 | "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, | |
3891 | hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, | |
3892 | hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, | |
3893 | hw->fdt_block_size)); | |
3894 | } | |
3895 | ||
3896 | static void | |
f8086f4f | 3897 | qla4_82xx_get_idc_param(struct scsi_qla_host *ha) |
f4f5df23 VC |
3898 | { |
3899 | #define QLA82XX_IDC_PARAM_ADDR 0x003e885c | |
3900 | uint32_t *wptr; | |
3901 | ||
3902 | if (!is_qla8022(ha)) | |
3903 | return; | |
3904 | wptr = (uint32_t *)ha->request_ring; | |
f8086f4f | 3905 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, |
f4f5df23 VC |
3906 | QLA82XX_IDC_PARAM_ADDR , 8); |
3907 | ||
3908 | if (*wptr == __constant_cpu_to_le32(0xffffffff)) { | |
3909 | ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; | |
3910 | ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; | |
3911 | } else { | |
3912 | ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); | |
3913 | ha->nx_reset_timeout = le32_to_cpu(*wptr); | |
3914 | } | |
3915 | ||
3916 | DEBUG2(ql4_printk(KERN_DEBUG, ha, | |
3917 | "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); | |
3918 | DEBUG2(ql4_printk(KERN_DEBUG, ha, | |
3919 | "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); | |
3920 | return; | |
3921 | } | |
3922 | ||
33693c7a VC |
3923 | void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, |
3924 | int in_count) | |
3925 | { | |
3926 | int i; | |
3927 | ||
3928 | /* Load all mailbox registers, except mailbox 0. */ | |
3929 | for (i = 1; i < in_count; i++) | |
3930 | writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); | |
3931 | ||
3932 | /* Wakeup firmware */ | |
3933 | writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); | |
3934 | readl(&ha->qla4_82xx_reg->mailbox_in[0]); | |
3935 | writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); | |
3936 | readl(&ha->qla4_82xx_reg->hint); | |
3937 | } | |
3938 | ||
3939 | void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) | |
3940 | { | |
3941 | int intr_status; | |
3942 | ||
3943 | intr_status = readl(&ha->qla4_82xx_reg->host_int); | |
3944 | if (intr_status & ISRX_82XX_RISC_INT) { | |
3945 | ha->mbox_status_count = out_count; | |
3946 | intr_status = readl(&ha->qla4_82xx_reg->host_status); | |
3947 | ha->isp_ops->interrupt_service_routine(ha, intr_status); | |
3948 | ||
3949 | if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && | |
f5b893c9 | 3950 | (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled)) |
33693c7a VC |
3951 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, |
3952 | 0xfbff); | |
3953 | } | |
f4f5df23 VC |
3954 | } |
3955 | ||
3956 | int | |
3957 | qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) | |
3958 | { | |
3959 | int ret; | |
3960 | uint32_t flt_addr; | |
3961 | ||
3962 | ret = qla4_8xxx_find_flt_start(ha, &flt_addr); | |
3963 | if (ret != QLA_SUCCESS) | |
3964 | return ret; | |
3965 | ||
3966 | qla4_8xxx_get_flt_info(ha, flt_addr); | |
6e7b4292 VC |
3967 | if (is_qla8022(ha)) { |
3968 | qla4_82xx_get_fdt_info(ha); | |
3969 | qla4_82xx_get_idc_param(ha); | |
b37ca418 | 3970 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
6e7b4292 VC |
3971 | qla4_83xx_get_idc_param(ha); |
3972 | } | |
f4f5df23 VC |
3973 | |
3974 | return QLA_SUCCESS; | |
3975 | } | |
3976 | ||
3977 | /** | |
3978 | * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance | |
3979 | * @ha: pointer to host adapter structure. | |
3980 | * | |
3981 | * Remarks: | |
3982 | * For iSCSI, throws away all I/O and AENs into bit bucket, so they will | |
3983 | * not be available after successful return. Driver must cleanup potential | |
3984 | * outstanding I/O's after calling this funcion. | |
3985 | **/ | |
3986 | int | |
3987 | qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) | |
3988 | { | |
3989 | int status; | |
3990 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
3991 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
3992 | ||
3993 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
3994 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
3995 | ||
3996 | mbox_cmd[0] = MBOX_CMD_STOP_FW; | |
3997 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, | |
3998 | &mbox_cmd[0], &mbox_sts[0]); | |
3999 | ||
4000 | DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, | |
4001 | __func__, status)); | |
4002 | return status; | |
4003 | } | |
4004 | ||
4005 | /** | |
f8086f4f | 4006 | * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. |
f4f5df23 VC |
4007 | * @ha: pointer to host adapter structure. |
4008 | **/ | |
4009 | int | |
f8086f4f | 4010 | qla4_82xx_isp_reset(struct scsi_qla_host *ha) |
f4f5df23 VC |
4011 | { |
4012 | int rval; | |
4013 | uint32_t dev_state; | |
4014 | ||
f8086f4f VC |
4015 | qla4_82xx_idc_lock(ha); |
4016 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
f4f5df23 | 4017 | |
de8c72da | 4018 | if (dev_state == QLA8XXX_DEV_READY) { |
f4f5df23 | 4019 | ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); |
f8086f4f | 4020 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
de8c72da VC |
4021 | QLA8XXX_DEV_NEED_RESET); |
4022 | set_bit(AF_8XXX_RST_OWNER, &ha->flags); | |
f4f5df23 VC |
4023 | } else |
4024 | ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); | |
4025 | ||
f8086f4f | 4026 | qla4_82xx_idc_unlock(ha); |
f4f5df23 VC |
4027 | |
4028 | rval = qla4_8xxx_device_state_handler(ha); | |
4029 | ||
f8086f4f | 4030 | qla4_82xx_idc_lock(ha); |
f4f5df23 | 4031 | qla4_8xxx_clear_rst_ready(ha); |
f8086f4f | 4032 | qla4_82xx_idc_unlock(ha); |
f4f5df23 | 4033 | |
068237c8 | 4034 | if (rval == QLA_SUCCESS) { |
f8086f4f | 4035 | ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); |
21033639 | 4036 | clear_bit(AF_FW_RECOVERY, &ha->flags); |
068237c8 | 4037 | } |
21033639 | 4038 | |
f4f5df23 VC |
4039 | return rval; |
4040 | } | |
4041 | ||
4042 | /** | |
4043 | * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number | |
4044 | * @ha: pointer to host adapter structure. | |
4045 | * | |
4046 | **/ | |
4047 | int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) | |
4048 | { | |
4049 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
4050 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
4051 | struct mbx_sys_info *sys_info; | |
4052 | dma_addr_t sys_info_dma; | |
4053 | int status = QLA_ERROR; | |
4054 | ||
750afb08 LC |
4055 | sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), |
4056 | &sys_info_dma, GFP_KERNEL); | |
f4f5df23 VC |
4057 | if (sys_info == NULL) { |
4058 | DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", | |
4059 | ha->host_no, __func__)); | |
4060 | return status; | |
4061 | } | |
4062 | ||
f4f5df23 VC |
4063 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
4064 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
4065 | ||
4066 | mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; | |
4067 | mbox_cmd[1] = LSDW(sys_info_dma); | |
4068 | mbox_cmd[2] = MSDW(sys_info_dma); | |
4069 | mbox_cmd[4] = sizeof(*sys_info); | |
4070 | ||
4071 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], | |
4072 | &mbox_sts[0]) != QLA_SUCCESS) { | |
4073 | DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", | |
4074 | ha->host_no, __func__)); | |
4075 | goto exit_validate_mac82; | |
4076 | } | |
4077 | ||
2ccdf0dc | 4078 | /* Make sure we receive the minimum required data to cache internally */ |
b37ca418 | 4079 | if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) < |
e19dd66f | 4080 | offsetof(struct mbx_sys_info, reserved)) { |
f4f5df23 VC |
4081 | DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" |
4082 | " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); | |
4083 | goto exit_validate_mac82; | |
f4f5df23 VC |
4084 | } |
4085 | ||
4086 | /* Save M.A.C. address & serial_number */ | |
2a991c21 | 4087 | ha->port_num = sys_info->port_num; |
f4f5df23 VC |
4088 | memcpy(ha->my_mac, &sys_info->mac_addr[0], |
4089 | min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); | |
4090 | memcpy(ha->serial_number, &sys_info->serial_number, | |
4091 | min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); | |
91ec7cec VC |
4092 | memcpy(ha->model_name, &sys_info->board_id_str, |
4093 | min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); | |
4094 | ha->phy_port_cnt = sys_info->phys_port_cnt; | |
4095 | ha->phy_port_num = sys_info->port_num; | |
4096 | ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; | |
f4f5df23 | 4097 | |
d1d81bd0 OK |
4098 | DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n", |
4099 | ha->host_no, __func__, ha->my_mac, ha->serial_number)); | |
f4f5df23 VC |
4100 | |
4101 | status = QLA_SUCCESS; | |
4102 | ||
4103 | exit_validate_mac82: | |
4104 | dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, | |
4105 | sys_info_dma); | |
4106 | return status; | |
4107 | } | |
4108 | ||
4109 | /* Interrupt handling helpers. */ | |
4110 | ||
5c19b92a | 4111 | int qla4_8xxx_intr_enable(struct scsi_qla_host *ha) |
f4f5df23 VC |
4112 | { |
4113 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
4114 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
4115 | ||
4116 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); | |
4117 | ||
4118 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
4119 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
4120 | mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; | |
4121 | mbox_cmd[1] = INTR_ENABLE; | |
4122 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], | |
4123 | &mbox_sts[0]) != QLA_SUCCESS) { | |
4124 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
4125 | "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", | |
4126 | __func__, mbox_sts[0])); | |
4127 | return QLA_ERROR; | |
4128 | } | |
4129 | return QLA_SUCCESS; | |
4130 | } | |
4131 | ||
5c19b92a | 4132 | int qla4_8xxx_intr_disable(struct scsi_qla_host *ha) |
f4f5df23 VC |
4133 | { |
4134 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
4135 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
4136 | ||
4137 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); | |
4138 | ||
4139 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
4140 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
4141 | mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; | |
4142 | mbox_cmd[1] = INTR_DISABLE; | |
4143 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], | |
4144 | &mbox_sts[0]) != QLA_SUCCESS) { | |
4145 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
4146 | "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", | |
4147 | __func__, mbox_sts[0])); | |
4148 | return QLA_ERROR; | |
4149 | } | |
4150 | ||
4151 | return QLA_SUCCESS; | |
4152 | } | |
4153 | ||
4154 | void | |
f8086f4f | 4155 | qla4_82xx_enable_intrs(struct scsi_qla_host *ha) |
f4f5df23 | 4156 | { |
5c19b92a | 4157 | qla4_8xxx_intr_enable(ha); |
f4f5df23 VC |
4158 | |
4159 | spin_lock_irq(&ha->hardware_lock); | |
4160 | /* BIT 10 - reset */ | |
f8086f4f | 4161 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); |
f4f5df23 VC |
4162 | spin_unlock_irq(&ha->hardware_lock); |
4163 | set_bit(AF_INTERRUPTS_ON, &ha->flags); | |
4164 | } | |
4165 | ||
4166 | void | |
f8086f4f | 4167 | qla4_82xx_disable_intrs(struct scsi_qla_host *ha) |
f4f5df23 | 4168 | { |
5fa8b573 | 4169 | if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) |
5c19b92a | 4170 | qla4_8xxx_intr_disable(ha); |
f4f5df23 VC |
4171 | |
4172 | spin_lock_irq(&ha->hardware_lock); | |
4173 | /* BIT 10 - set */ | |
f8086f4f | 4174 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); |
f4f5df23 | 4175 | spin_unlock_irq(&ha->hardware_lock); |
f4f5df23 VC |
4176 | } |
4177 | ||
f4f5df23 VC |
4178 | int |
4179 | qla4_8xxx_enable_msix(struct scsi_qla_host *ha) | |
4180 | { | |
f5b893c9 | 4181 | int ret; |
f4f5df23 | 4182 | |
f5b893c9 CH |
4183 | ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES, |
4184 | QLA_MSIX_ENTRIES, PCI_IRQ_MSIX); | |
4185 | if (ret < 0) { | |
f4f5df23 VC |
4186 | ql4_printk(KERN_WARNING, ha, |
4187 | "MSI-X: Failed to enable support -- %d/%d\n", | |
4188 | QLA_MSIX_ENTRIES, ret); | |
f5b893c9 | 4189 | return ret; |
f4f5df23 | 4190 | } |
f5b893c9 CH |
4191 | |
4192 | ret = request_irq(pci_irq_vector(ha->pdev, 0), | |
4193 | qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)", | |
4194 | ha); | |
4195 | if (ret) | |
4196 | goto out_free_vectors; | |
4197 | ||
4198 | ret = request_irq(pci_irq_vector(ha->pdev, 1), | |
4199 | qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha); | |
4200 | if (ret) | |
4201 | goto out_free_default_irq; | |
4202 | ||
4203 | return 0; | |
4204 | ||
4205 | out_free_default_irq: | |
4206 | free_irq(pci_irq_vector(ha->pdev, 0), ha); | |
4207 | out_free_vectors: | |
4208 | pci_free_irq_vectors(ha->pdev); | |
f4f5df23 VC |
4209 | return ret; |
4210 | } | |
37418cc6 NJ |
4211 | |
4212 | int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha) | |
4213 | { | |
4214 | int status = QLA_SUCCESS; | |
4215 | ||
4216 | /* Dont retry adapter initialization if IRQ allocation failed */ | |
4217 | if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) { | |
4218 | ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n", | |
4219 | __func__); | |
4220 | status = QLA_ERROR; | |
4221 | goto exit_init_adapter_failure; | |
4222 | } | |
4223 | ||
4224 | /* Since interrupts are registered in start_firmware for | |
4225 | * 8xxx, release them here if initialize_adapter fails | |
4226 | * and retry adapter initialization */ | |
4227 | qla4xxx_free_irqs(ha); | |
4228 | ||
4229 | exit_init_adapter_failure: | |
4230 | return status; | |
4231 | } |